TPS53129
www.ti.com
SLVSAE6 – JULY 2010
DUAL SYNCHRONOUS STEP-DOWN CONTROLLER
FOR LOW VOLTAGE POWER RAILS
Check for Samples: TPS53129
1FEATURES • 700-kHz Switching Frequency
2• D-CAP2™ Mode Control • Cycle-by-Cycle Over-Current Limiting Control
– Fast Transient Response • 30-mV to 300-mV OCP Threshold Voltage
– No External Parts Required for Loop • Thermally Compensated OCP by 4000 ppm/°C
Compensation at ITRIP
– Compatible With Ceramic Output APPLICATIONS
Capacitors • Point-of-Load Regulation in Low Power
• High Initial Reference Accuracy (±1%) Systems for Wide Range of Applications
• Low Output Ripple – Digital TV Power Supply
• Wide Input Voltage Range: 4.5 V to 24 V – Networking Home Terminal
• Output Voltage Range: 0.76 V to 5.5 V – Digital Set-Top Box (STB)
• Low-Side RDS(ON) Loss-Less Current Sensing – DVD Player/Recorder
• Adaptive Gate Drivers with Integrated Boost – Gaming Consoles
Diode
• Adjustable Soft Start
• Non-Sinking Pre-Biased Soft Start
DESCRIPTION
The TPS53129 is a dual, adaptive on-time D-CAP2™ mode synchronous buck controller. The TPS53129
enables system designers to complete the suite of various end equipment’s power bus regulators with cost
effective, low component count, and low standby current solution. The main control loop for the TPS53129 uses
the D-CAP2™ mode control which provides a very fast transient response with no external components. The
TPS53129 also has a circuit that enables the device to adapt to both low equivalent series resistance (ESR)
output capacitors such as POSCAP or SP-CAP, and ultra-low ESR, ceramic capacitors. The fixed frequency
emulated adaptive on-time control supports seamless operation between PWM mode at heavy load condition
and reduced frequency operation at light load for high efficiency down to milliampere range.The device provides
convenient and efficient operation with input voltages from 4.5 V to 24 V and output voltages from 0.76 V to
5.5 V.
The TPS53129 is available in 4-mm x 4-mm 24-pin QFN (RGE) or 24-pin TSSOP (PW) packages, and is
specified from -40°C to 85°C ambient temperature range.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2D-CAP2 is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Copyright © 2009–2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS53129 RGE
(QFN )
DRVH2
VBST2
EN2
SW1
DRVL1
DRVH1
VBST1
EN1
VFB2
VO2
VO1
VFB1
GND
PGND2 PGND1
DRVL2
SW2
C3
10uF
VO2
1.05V/4A
C5
0.1uF
Input Voltage
PGND
C4
22uFx2
10uF
C6
10uF
L1
PGND
Q3
FDS8878
R4
3.63kΩ
R5
10kΩ
PGND
SGND
R6
4.7kΩ
24
22
23
19
20
21
13 14 15 16 17 18
8
9
10
11
12
7
123456
Power PAD
PGND
SGND
SS1
SS2
TRIP2
V5FILT
VREG5
VIN
TRIP1
4.5V to 24V
VO1
1.8V/4A
Q4
FDS8690
Q1
FDS8878
C9
Q2
FDS8690
L2
SPM6530T
1.5uH
L1
SPM6530T
1.5uH
C2
0.1uF
R３
4.3kΩ
R2
10kΩ
C８
1uF
C7
4.7uF
R1
13.5kΩ
C1
22uFx2
C11
4700pF
C10
4700pF
TPS53129PW
TSSOP24
SW1
DRVL1
DRVH1
VBST1
EN1
VFB2
VO2
VO1
VFB1
GND
TRIP2
VREG5
TRIP1
PGND1
3
24
8
21
22
23
15
916
18
19
20
5
7
1
10
11
VIN
SS2
DRVH2
VBST2
EN2 PGND2
DRVL2
SW2 13
14
12
V5FILT
17
SS1
6
2
4PGND
PGND
SGND
PGND
SGND
Input Voltage
4.5V to 24V
C9
10uF
VO1
1.8V/4A
C1
22uFx2
C3
10uF
Q1
FDS8878
L1
SPM6530T
1.5uH
Q2
FDS8690
C2
0.1uF
R３
4.3kΩ
R6
4.7kΩ
C８
1uF
C7
4.7uF
L2
SPM6530T
1.5uH
VO2
1.05V/4A
C6
10uF
Q3
FDS8878
Q4
FDS8690
C5
0.1uF
R2
10kΩ
R1
13.5k
Ω
R5
10kΩ
R4
3.63kΩ
C11
4700pF
C10
4700pF
C4
22uFx2
TPS53129
SLVSAE6B –OCTOBER 2009– REVISED JULY 2010
www.ti.com
TYPICAL APPLICATION CIRCUITS
Figure 1. QFN
Figure 2. TSSOP
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Product Folder Link(s): TPS53129
TPS53129
www.ti.com
SLVSAE6B –OCTOBER 2009 – REVISED JULY 2010
ORDERING INFORMATION(1)
ORDERING
TAPACKAGE(2) (3) PINS OUTPUT SUPPLY ECO PLAN
PART NUMBER
TPS53129RGET Tape-and-Reel
Plastic Quad
Flat Pack (QFN) TPS53129RGER Tape-and-Reel Green
–40°C to 85°C 24 (RoHS and no Sb/Br)
TPS53129PWR Tape-and-Reel
TSSOP TPS53129PW Tube
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(3) All packaging options have Cu NIPDAU lead/ball finish.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
VALUE UNIT
VIN, EN1, EN2 –0.3 to 26
VBST1, VBST2 –0.3 to 32
VBST1 - SW1, VBST2 - SW2 –0.3 to 6
VIInput voltage range V
V5FILT, VFB1, VFB2, TRIP1, TRIP2, –0.3 to 6
VO1, VO2
SW1, SW2 –2 to 26
DRVH1, DRVH2 –1 to 32
DRVH1 - SW1, DRVH2 - SW2 –0.3 to 6
VOOutput voltage range V
DRVL1, DRVL2, VREG5, SS1, SS2 –0.3 to 6
PGND1, PGND2 –0.3 to 0.3
TAOperating ambient temperature range –40 to 85 °C
TSTG Storage temperature range –55 to 150 °C
TJJunction temperature range –40 to 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" are not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATINGS
2-oz. trace and copper pad with solder
TA< 25°C DERATING FACTOR TA= 85°C
PACKAGE POWER RATING ABOVE TA= 25°C POWER RATING
24-pin QFN 2.33 W 23.3 mW/°C 0.93 W
24-pin TSSOP 0.778 W 7.8 mW/°C 0.31 W
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VIN 4.5 24
VIN Supply input voltage V
V5FILT 4.5 5.5
VBST1, VBST2 –0.1 30
VBST1 - SW1, VBST2 - SW2 –0.1 5.5
VFB1, VFB2, VO1, VO2 –0.1 5.5
VIInput voltage V
TRIP1, TRIP2 –0.1 0.3
EN1, EN2 –0.1 24
SW1, SW2 –1.8 24
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SLVSAE6B –OCTOBER 2009– REVISED JULY 2010
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RECOMMENDED OPERATING CONDITIONS (continued)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
DRVH1, DRVH2 –0.1 30
VBST1 - SW1, VBST2 - SW2 –0.1 5.5
VOOutput voltage V
DRVL1, DRVL2, VREG5, SS1, SS2 –0.1 5.5
PGND1, PGND2 –0.1 0.1
TAOperating free-air temperature –40 85 °C
TJOperating junction temperature –40 125 °C
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
VIN current, TA= 25°C, VREG5 tied
to V5FILT, EN1 = EN2 = 5 V,
IIN VIN supply current 450 800 mA
VFB1 = VFB2 = 0.8 V,
SW1 = SW2 = 0.5 V
VIN current, TA= 25°C,
IVINSDN VIN shutdown current no load , EN1 = EN2 = 0 V, 30 60 mA
VREG5 = ON
VFB VOLTAGE AND DISCHARGE RESISTANCE
VBG Bandgap initial regulation accuracy TA= 25°C –1 1 %
TA= 25°C, SWinj = OFF 748 758 768
TA = 0°C to 70°C, 746.6 769.4
VVFBTHx VFBx threshold voltage SWinj = OFF(1) mV
TA= -40°C to 85°C, 745 771
SWinj = OFF (1)
IVFB VFB input current VFBx = 0.8 V, TA= 25°C –100 –10 100 nA
RDischg VO discharge resistance ENx = 0 V, VOx = 0.5 V, TA= 25°C 40 80 Ω
VREG5 OUTPUT
TA= 25°C, 5.5 V < VIN < 24 V,
VVREG5 VREG5 output voltage 4.8 5.0 5.2 V
0 < IVREG5 < 10 mA
VLN5 Line regulation 5.5 V < VIN < 24 V, IVREG5 = 10 mA 20 mV
VLD5 Load regulation 1 mA < IVREG5 < 10 mA 40 mV
VIN = 5.5 V, VREG5 = 4.0 V,
IVREG5 Output current 170 mA
TA= 25°C
OUTPUT: N-CHANNEL MOSFET GATE DRIVERS
Source, IDRVHx = –100 mA 5.5 11
RDRVH DRVH resistance Ω
Sink, IDRVHx = 100 mA 2.5 5
Source, IDRVLx = –100 mA 4 8
RDRVL DRVL resistance Ω
Sink, IDRVLx = 100 mA 2 4
DRVHx-low to DRVLx-on 20 50 80
TDDead time ns
DRVLx-low to DRVHx-on 20 40 80
INTERNAL BOOST DIODE
VFBST Forward voltage VVREG5-VBSTx, IF= 10 mA, TA= 25°C 0.7 0.8 0.9 V
VBSTx = 29 V, SWx = 24 V,
IVBSTLK VBST leakage current 0.1 1 mA
TA= 25°C
ON-TIME TIMER CONTROL
TON1L CH1 on time SW1 = 12 V, VO1 = 1.8 V 165 ns
TON2L CH2 on time SW2 = 12 V, VO2 = 1.8 V 140 ns
(1) Not production tested - ensured by design.
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SLVSAE6B –OCTOBER 2009 – REVISED JULY 2010
ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SW1 = 0.7 V, TA= 25°C,
TOFF1L CH1 min off time 216 ns
VFB1 = 0.7 V
SW2 = 0.7 V, TA= 25°C,
TOFF2L CH2 min off time 216 ns
VFB2 = 0.7 V
SOFT START
ISSC SS1/SS2 charge current VSS1/VSS2 = 0 V, TA= 25°C –1.44 –2 –2.56 mA
TCISSC ISSC temperature coefficient On the basis of 25°C(1) –3.3 3.3 nA/°C
ISSD SS1/SS2 discharge current VSS1/VSS2 = 0.5 V 100 150 mA
UVLO
V5FILT rising 3.7 4.0 4.3
VUV5VFILT V5FILT UVLO threshold V
Hysteresis 0.2 0.3 0.4
LOGIC THRESHOLD
VENH ENx high-level input voltage EN 1/2 2.0 V
VENL ENx low-level input voltage EN 1/2 0.3 V
CURRENT SENSE
ITRIP TRIP source current VTRIPx = 0.1 V, TA= 25°C 8.5 10 11.5 mA
TCITRIP ITRIP temperature coefficient On the basis of 25°C 4000 ppm/°C
(VTRIPx-GND-VPGNDx-SWx) voltage, –15 0 15
VTRIPx-GND = 60 mV, TA= 25°C
VOCLoff OCP compensation offset mV
(VTRIPx-GND-VPGNDx-SWx) voltage, –20 20
VTRIPx-GND = 60 mV
Zero cross detection comparator
VZC VPGNDx-LLx voltage 0.5 mV
offset
VRtrip Current limit threshold setting range VTRIPx-GND voltage 30 300 mV
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
VOVP Output OVP trip threshold OVP detect 110 115 120 %
TOVPDEL Output OVP prop delay 1.5 ms
UVP detect 65 70 75
VUVP Output UVP trip threshold %
Hysteresis (recover < 20 ms) 10
TUVPDEL Output UVP delay 17 30 40 ms
TUVPEN Output UVP enable delay UVP enable delay / soft-start time x1.4 x1.7 x2.0 ms
THERMAL SHUTDOWN
Shutdown temperature (2) 150
TSDN Thermal shutdown threshold °C
Hysteresis (2) 20
(2) Not production tested - ensured by design.
TERMINAL FUNCTIONS
PIN Fucntion Table
TERMINAL I/O DESCRIPTION
QFN TSSOP
NAME 24 24
Supply input for high-side NFET driver. Bypass to SWx with a high-quality
VBST1, 23, 8 2, 11 I 0.1-mF ceramic capacitor. An external schottky diode can be added from
VBST2 VREG5 if forward drop is critical to drive the high-side FET.
EN1, EN2 24, 7 3, 10 I Enable. Pull High to enable SMPS.
Output voltage inputs for on-time adjustment and output discharge. Connect
VO1, VO2 1, 6 4, 9 I directly to the output voltage.
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VBST1
EN1
VO1
VFB1
GND
SS1
VFB2
VO2
EN2
VBST2
DRVH1 SW1
DRVL1
PGND1
TRIP1
VIN
VREG5
V5FILT
SS2
TRIP2
PGND2
DRVL2
SW2
DRVH2
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
16
15
14
13
TSSOP PACKAGE
(TOP VIEW)
TRIP1
VIN
VO1
VFB1
GND
SS1
VREG5
V5FILT
SS 2
TRIP2
VFB2
VO2
EN2 EN1
VBST1
DRVH1
SW1
DRVL1
PGND1
VBST2
DRVH2
SW2
DRVL2
PGND2
16
15
14
13
18
17
1
2
3
4
5
6
9
10
11
12
7
823
20
24
22
21
19
QFN PACKAGE
(TOP VIEW)
TPS53129
SLVSAE6B –OCTOBER 2009– REVISED JULY 2010
www.ti.com
PIN Fucntion Table (continued)
TERMINAL I/O DESCRIPTION
QFN TSSOP
NAME 24 24
VFB1, 2, 5 5, 8 I D-CAP2 feedback inputs. Connect to output voltage with resistor divider.
VFB2
Signal ground pin. Connect to PGND1, PGND2 and system ground at a single
GND 3 6 I point.
DRVH1, High-side N-Channel MOSFET gate driver outputs. SWx referenced drivers
22, 9 1, 12 O
DRVH2 switch between SWx (OFF) and VBSTx (ON).
Switch node connections for both the high-side drivers and the over current
SW1, SW2 21, 10 24, 13 I/O comparators.
DRVL1, Low-side N-Channel MOSFET gate driver outputs. PGND referenced drivers
20, 11 23, 14 O
DRVL2 switch between PGNDx (OFF) and VREG5 (ON).
Power ground connections for both the low-side drivers and the over current
PGND1, 19, 12 22, 15 I/O comparators. Connect PGND1, PGND2 and GND strongly together near the
PGND2 IC.
TRIP1, Over current threshold programming pin. Connect to GND with a resistor to
18, 13 21, 16 I
TRIP2 GND to set threshold for low-side RDS(ON) current limit.
Supply Input for 5-V linear regulator. Bypass to GND with a minimum
VIN 17 20 I high-quality 0.1-mF ceramic capacitor.
5-V supply input for the entire control circuitry except the MOSFET drivers.
V5FILT 15 18 I Bypass to GND with a minimum high-quality 1.0-mF ceramic capacitor. V5FILT
is connected to VREG5 via an internal 10-Ωresistor.
Output of 5-V linear regulator and supply for MOSFET drivers. Bypass to GND
VREG5 16 19 O with a minimum high-quality 4.7-mF ceramic capacitor. VREG5 is connected to
V5FILT via an internal 10-Ωresistor.
Soft-start programming pin. Connect capacitor from SSx pin to GND to program
SS1, SS2 4,14 7, 17 I soft-start time.
xxx
xxx
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SS1
SS2
SW SW
TPS53129
www.ti.com
SLVSAE6B –OCTOBER 2009 – REVISED JULY 2010
FUNCTIONAL BLOCK DIAGRAM
Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 7
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SWX
ERR
COMP
TPS53129
SLVSAE6B –OCTOBER 2009– REVISED JULY 2010
www.ti.com
8Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS53129
( )
1
2
IN
OUT LL
IN
V Vox Vox
L fsw V
I-
= ´
´ ´
TPS53129
www.ti.com
SLVSAE6B –OCTOBER 2009 – REVISED JULY 2010
DETAILED DESCRIPTION
PWM Operation
The main control loop of the TPS53129 is an adaptive on-time pulse width modulation (PWM) controller using a
proprietary D-CAP2™ mode control. D-CAP2™ mode control combines constant on-time control with an internal
compensation circuit for pseudo-fixed frequency and low external component count configuration with both low
ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output.
At the beginning of each cycle, the synchronous high-side MOSFET is turned on. After an internal one-shot timer
expires, this MOSFET is turned off. When the feedback voltage falls below the reference voltage, the one-shot
timer is reset and the high-side MOSFET is turned back on. The one shot is set by the converter input voltage
VIN, and the output voltage VO, to maintain a pseudo-fixed frequency over the input voltage range. An internal
ramp is added to the reference voltage to simulate output ripple, eliminating the need for ESR induced output
ripple from D-CAP mode control. The low-side MOSFET is turned off when the inductor current information
detects zero level. This enables seamless transition to the reduced frequency operation at light-load conditions
so that high efficiency is kept over a broad range of load current.
Light-Load Condition
TPS53129 automatically reduces switching frequency at light-load conditions to maintain high efficiency. This
reduction of frequency is achieved smoothly and without increase of Vout ripple or load regulation. Detail
operation is described as follows. As the output current decreases from heavy-load condition, the inductor
current is also reduced, and eventually comes to the point that its valley touches zero current, which is the
boundary between continuous conduction and discontinuous condition modes. The low-side MOSFET is turned
off when this zero inductor current is detected. As the load current is further decreased, the converter runs in
discontinuous conduction mode and it takes longer and longer to discharge the output capacitor to the level that
requires the next ON cycle. The ON time is kept the same as that in the heavy-load condition. In reverse, when
the output current increases from light load to heavy load, the switching frequency increases to the preset value
as the inductor current reaches the continuous conduction. The transition load point to the light load operation,
IOUT(LL) (i.e., threshold between continuous and discontinuous condition mode) can be calculated as follows.
(1)
Where fSW is the PWM switching frequency.
Switching frequency versus output current in the light-load condition is a function of L, fSW, VIN and VOUT, but it
decreases almost proportional to the output current from the IOUT(LL) given in Equation 1.
Drivers
Each channel of the TPS53129 contains two high-current resistive MOSFET gate drivers. The low-side driver is a
PGND referenced, VREG5 powered driver designed to drive the gate of a high-current, low RDS(ON) N-channel
MOSFET whose source is connected to PGND. The high-side driver is a floating SWx referenced VBST powered
driver designed to drive the gate of a high-current, low RDS(ON) N-channel MOSFET. To maintain the VBST
voltage during the high-side driver ON time, a capacitor is placed from SWx to VBSTx. Each driver draws
average current equal to gate charge (Qgat Vgs = 5 V) times switching frequency (fSW).
To prevent cross-conduction, there is a narrow dead-time when both high-side and low-side drivers are OFF
between each driver transition. During this time the inductor current is carried by one of the MOSFETs body
diodes.
PWM Frequency and Adaptive On-Time Control
TPS53129 employs adaptive on-time control scheme and does not have a dedicated on board oscillator.
TPS53129 runs with pseudo-constant frequency by using the input voltage and output voltage to set the on-time
one-shot timer. The on-time is inversely proportional to the input voltage and proportional to the output voltage.
Therefore, when the duty ratio is VOUT/VIN, the frequency is constant.
Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Link(s): TPS53129
V =
TRIP
(V-V )
IN O
2 1· ·L fSW
¾
·VO
¾
VIN
·RDS(ON)
I -
OCL
( )
R (k )=
TRIP WV (mV)
TRIP
I ( A)
TRIP m
¾
TPS53129
SLVSAE6B –OCTOBER 2009– REVISED JULY 2010
www.ti.com
5-Volt Regulator
The TPS53129 has an internal 5-V low-dropout (LDO) regulator to provide a regulated voltage for all both drivers
and the IC's internal logic. A high-quality 4.7-mF or greater ceramic capacitor from VREG5 to GND is required to
stabilize the internal regulator. An internal 10-Ωresistor from VREG5 filters the regulator output to the IC's
analog and logic input voltage, V5FILT. An additional high-quality 1.0-mF ceramic capacitor is required from
V5FILT to GND to filter switching noise from VREG5.
Soft Start
The TPS53129 has a programmable soft-start . When the ENx pin becomes high, 2.0-mA current begins charging
the capacitor connected from the SS pin to GND. The internal reference for the D-CAP2™ mode control
comparator is overridden by the soft-start voltage until the soft-start voltage is greater than the internal reference
for smooth control of the output voltage during start up.
Pre-Bias Support
The TPS53129 supports pre-bias start-up without sinking current from the output capacitor. When enabled, the
low-side driver is held off until the soft-start commands a voltage higher than the pre-bias level (internal soft-start
becomes greater than feedback voltage (VFB)), then the TPS53129 slowly activates synchronous rectification by
limiting the first DRVL pulses with a narrow on-time. This limited on-time is then incremented on a cycle-by-cycle
basis until it coincides with the full 1-D off-time. This scheme prevents the initial sinking of current from the
pre-bias output, and ensure that the output voltage (VOUT) starts and ramps up smoothly into regulation and the
control loop is given time to transition from pre-biased start-up to normal mode operation.
Output Discharge Control
TPS53129 discharges the outputs when ENx is low, or the controller is turned off by the protection functions
(OVP, UVP, UVLO, and thermal shutdown). The device discharges output using an internal 40-ΩMOSFET which
is connected to VOx and PGNDx. The external low-side MOSFET is not turned on during the output discharge
operation to avoid the possibility of causing negative voltage at the output. This discharge ensures that on start
the regulated voltage always initializes from 0 V.
Over Current Limit
TPS53129 has cycle-by-cycle over current limit feature. The over current limits the inductor valley current by
monitoring the voltage drop across the low-side MOSFET RDS(ON) during the low-side driver on-time. If the
inductor current is larger than the over current limit (OCL), the TPS53129 delays the start of the next switching
cycle until the sensed inductor current falls below the OCL current. MOSFET RDS(ON) current sensing is used to
provide an accuracy and cost effective solution without external devices. To program the OCL, the TRIP pin
should be connected to GND through a trip voltage setting resistor, according to the following equations.
(2)
(3)
The trip voltage should be between 30 mV to 300 mV over all operational temperature, including the
4000-ppm/°C temperature slope compensation for the temperature dependency of the RDS(ON).
If the load current exceeds the over current limit, the voltage will begin to drop. If the over current conditions
continues the output voltage will fall below the under voltage protection threshold and the TPS53129 will shut
down.
In an over current condition, the current to the load exceeds the current to the output capacitor; thus the output
voltage tends to fall off. Eventually, it will end up with crossing the under voltage protection threshold and
shutdown.
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SLVSAE6B –OCTOBER 2009 – REVISED JULY 2010
Over/Under Voltage Protection
TPS53129 monitors a resistor divided feedback voltage to detect over and under voltage. If the feedback voltage
is higher than 115% of the reference voltage, the OVP comparator output goes high and the circuit latches the
high-side MOSFET driver OFF and the low-side MOSFET driver ON.
When the feedback voltage is lower than 70% of the reference voltage, the UVP comparator output goes high
and an internal UVP delay counter begins counting. After 30 ms, TPS53129 latches OFF both top and bottom
MOSFET drivers. This function is enabled approximately 1.7 x TSS after power-on. The OVP and UVP latch off is
reset when EN goes low level.
UVLO Protection
TPS53129 has V5FILT under voltage lock out protection (UVLO) that monitors the voltage of V5FILT pin.
When the V5FILT voltage is lower than UVLO threshold voltage, the device is shut off. All output drivers are OFF
and output discharge is ON. The UVLO is non-latch protection.
Thermal Shutdown
The TPS53129 includes an over temperature protection shut-down feature. If the TPS53129 die temperature
exceeds the OTP threshold (typically 150°C), both the high-side and low-side drivers are shut off, the output
voltage discharge function is enabled and then the device is shut off until the die temperature drops. Thermal
shutdown is a non-latch protection.
Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Link(s): TPS53129
0
10
20
30
40
50
60
-50 0 50 100 150
T - Junction Temperature - °C
J
I - A
VINSDN m
0
100
200
300
400
500
600
700
-50 0 50 100 150
T - Junction Temperature - °C
J
I - Supply Current - A
IN m
5.000
5.010
5.020
5.030
5.040
5.050
5.060
5.070
-50 0 50 100 150
T - Junction Temperature - °C
J
VFB Voltage - V
0
5
10
15
20
-50 0 50 100 150
T - Junction Temperature - °C
J
I - SOURCE CURRENT - A
TRIP m
TPS53129
SLVSAE6B –OCTOBER 2009– REVISED JULY 2010
www.ti.com
TYPICAL CHARACTERISTICS
VIN SUPPLY CURRENT VIN SHUTDOWN CURRENT
vs vs
JUNCTION TEMPERATURE JUNCTION TEMPERATURE
Figure 3. Figure 4.
TRIP SOURCE CURRENT VREG5 VOLTAGE
vs vs
JUNCTION TEMPERATURE JUNCTION TEMPERATURE
Figure 5. Figure .
12 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS53129
4.500
4.700
4.900
5.100
5.300
5.500
0 5 10 15 20 25
VREG5 Voltage - V
VIN - Input Voltage - V
0.750
0.755
0.760
0.765
0.770
0.775
0.780
0.785
0.790
0.795
0.800
0 5 10 15 20 25
V - Input Voltage - V
IN
VFB1 Voltage - V
0.750
0.755
0.760
0.765
0.770
0.775
0.780
0.785
0.790
0.795
0.800
0 5 10 15 20 25
V - Input Voltage - V
IN
VFB2 Voltage - V
0.750
0.755
0.760
0.765
0.770
0.775
0.780
0.785
0.790
0.795
0.800
-50 0 50 100 150
T - Junction Temperature - °C
J
VFB1 Voltage - V
TPS53129
www.ti.com
SLVSAE6B –OCTOBER 2009 – REVISED JULY 2010
TYPICAL CHARACTERISTICS (continued)
VREG5 VOLTAGE VFB1
vs vs
INPUT VOLTAGE INPUT VOLTAGE
Figure 6. Figure 7.
VFB2 VFB1
vs vs
INPUT VOLTAGE JUNCTION TEMPERATURE
Figure 8. Figure 9.
Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): TPS53129
0.750
0.755
0.760
0.765
0.770
0.775
0.780
0.785
0.790
0.795
0.800
-50 0 50 100 150
T - Junction Temperature - °C
J
VFB2 Voltage - V
TPS53129
SLVSAE6B –OCTOBER 2009– REVISED JULY 2010
www.ti.com
TYPICAL CHARACTERISTICS (continued)
VFB2
vs
JUNCTION TEMPERATURE
Figure 10.
14 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS53129
0
100
200
300
400
500
600
700
800
0 5 10 15 20 25
V - Input Voltage - V
IN
f - Switching Frequency - KHz
SW
VO1 = 1.05V
VO1 = 1.2V
VO1 = 1.8V
VO1 = 2.5V
VO1 = 3.3V
VO1 = 5V
0
100
200
300
400
500
600
700
800
0 5 10 15 20 25
V - Input Voltage - V
IN
f - Switching Frequency - KHz
SW
VO2 = 1.05V
VO2 = 1.2V
VO2 = 1.8V
VO2 = 2.5V
VO2 = 3.3V
VO2 = 5V
0
100
200
300
400
500
600
0.01 0.1 1 10
I - Output Current - A
O
f - Switching Frequency - KHz
SW
VO2=1.05V
0
100
200
300
400
500
600
700
0.01 0.1 1 10
I - Output Current - A
O
f - Switching Frequency - KHz
SW
VO1=1.8V
TPS53129
www.ti.com
SLVSAE6B –OCTOBER 2009 – REVISED JULY 2010
TYPICAL APPLICATION PERFORMANCE
SWITCHING FREQUENCY (IO1 = 3 A) SWITCHING FREQUENCY (IO2 = 3 A)
vs vs
INPUT VOLTAGE (CH1) INPUT VOLTAGE (CH2)
Figure 11. Figure 12.
SWITCHING FREQUENCY SWITCHING FREQUENCY
vs vs
OUTPUT CURRENT (CH1) OUTPUT CURRENT (CH2)
Figure 13. Figure 14.
Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): TPS53129
1.000
1.010
1.020
1.030
1.040
1.050
1.060
1.070
1.080
1.090
1.100
0.001 0.01 0.1 1 10
I - Output Current - A
OUT
V - Output Voltage - V
OUT
VO2=1.05V
1.760
1.770
1.780
1.790
1.800
1.810
1.820
1.830
1.840
1.850
1.860
1.870
1.880
0.001 0.01 0.1 1 10
I - Output Current - A
OUT
V - Output Voltage - V
OUT
VO1=1.8V
1.000
1.010
1.020
1.030
1.040
1.050
1.060
1.070
1.080
1.090
1.100
0 5 10 15 20 25
V - Input Voltage - V
I
V - Output Voltage - V
OUT2
VO2=1.05V
1.760
1.770
1.780
1.790
1.800
1.810
1.820
1.830
1.840
1.850
1.860
1.870
1.880
0 5 10 15 20 25
V - Input Voltage - V
I
V - Output Voltage - V
OUT1
VO1=1.8V
TPS53129
SLVSAE6B –OCTOBER 2009– REVISED JULY 2010
www.ti.com
OUTPUT VOLTAGE (VIN = 12 V) OUTPUT VOLTAGE (VIN = 12 V)
vs vs
OUTPUT CURRENT (CH1) OUTPUT CURRENT (CH2)
Figure 15. Figure 16.
OUTPUT VOLTAGE (VIN = 12 V) OUTPUT VOLTAGE (VIN = 12 V)
vs vs
INPUT VOLTAGE (CH1) INPUT VOLTAGE (CH2)
Figure 17. Figure 18.
16 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS53129
VO1=1.8V (50mV/div)
Iout1 (2A/div)
VO2=1.05V (50mV/div)
Iout2 (2A/div)
EN1 (5 V/div)
SS1 (0.2 V/div)
VO1 = 1.8 V (0.5 V/div)
EN2 (5 V/div)
SS2 (0.2 V/div)
VO2 = 1.05 V (0.5 V/div)
TPS53129
www.ti.com
SLVSAE6B –OCTOBER 2009 – REVISED JULY 2010
LOAD TRANSIENT RESPONSE LOAD TRANSIENT RESPONSE
Figure 19. Figure 20.
START-UP WAVEFORMS START-UP WAVEFORMS
Figure 21. Figure 22.
Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): TPS53129
0
10
20
30
40
50
60
70
80
90
100
0.001 0.01 0.1 1 10
I - Output Current - A
OUT
Efficiency - %
VO1=1.8V
0
10
20
30
40
50
60
70
80
90
0.001 0.01 0.1 1 10
I - Output Current - A
OUT
Efficiency - %
VO2=1.05V
VO2 (20mV/div)
VO2=1.05V
VO1 (20mV/div)
VO1=1.8V
TPS53129
SLVSAE6B –OCTOBER 2009– REVISED JULY 2010
www.ti.com
1.8-V EFFICIENCY 1.05-V EFFICIENCY
vs vs
OUTPUT CURRENT (CH1) OUTPUT CURRENT (CH2)
Figure 23. Figure 24.
1.8-V OUTPUT RIPPLE VOLTAGE 1.05-V OUTPUT RIPPLE VOLTAGE
Figure 25. Figure 26.
18 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS53129
( ) ( )
(max) (max)
1( ) (max) (max)
1 3 1
1 1
11
IN IN
L ripple IN IN
Vo Vo
Vo Vo
Lfsw Io fsw
V V
V V
I
- ´ -
= ´ = ´
´ ´
I =
L (RIPPLE)1
V -V
IN(MAX) O1
¾
L f1·SW
·Vo1
¾
VIN(MAX)
I =
L (PEAK)1
VTRIP
¾
RDS(ON)
+IL (RIPPLE)1
I =
L (RMS)1ÖIO12+1
¾
12 (I )
L (RIPPLE)1
2
¾
C =1IL (RIPPLE)1
¾
8 1·VO (RIPPLE)
·1
¾
fSW
C1 =D
I L
load
2·1
¾
2 1· ·VODVOS
C1 =D
I L
load
2·1
¾
2· ·KDVUS
K=(V-V
IN O1)·Ton1
¾
T T
on min(off)
1+
TPS53129
www.ti.com
SLVSAE6B –OCTOBER 2009 – REVISED JULY 2010
APPLICATION INFORMATION
1. Choose inductor.
The inductance value is selected to provide approximately 30% peak to peak ripple current at maximum load.
Larger ripple current increases output ripple voltage, improve S/N ratio and contribute to stable operation.
Equation 4 can be used to calculate L1.
(4)
The inductors current ratings needs to support both the RMS (thermal) current and the Peak (saturation)
current. The RMS and peak inductor current can be estimated as follows.
(5)
(6)
(7)
Note: The calculation above shall serve as a general reference. To further improve transient response, the
output inductance could be reduced further. This needs to be considered along with the selection of the
output capacitor.
2. Choose output capacitor.
The capacitor value and ESR determines the amount of output voltage ripple and load transient response. it
is recommended to use a ceramic output capacitor.
(8)
(9)
(10)
Where
(11)
Select the capacitance value greater than the largest value calculated from Equation 8,Equation 9 and
Equation 10. The capacitance for C1 should be greater than 66 mF.
Where
ΔVOS = The allowable amount of overshoot voltage in load transition
ΔVUS = The allowable amount of undershoot voltage in load transition
Tmin(off) = Minimum off time
3. Choose input capacitor.
The TPS53129 requires an input decoupling capacitor and a bulk capacitor is needed depending on the
application. A minimum 10-mF high-quality ceramic capacitor is recommended for the input capacitor. The
capacitor voltage rating needs to be greater than the maximum input voltage.
Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Link(s): TPS53129
V = (V - V )
swinj IN O1 0.5875· ·
1
¾
fSW
VO1
¾
VIN
4975
··
()()
R1 =(VO
¾
VFB +VFB(RIPPLE)
¾
2
-1
)·R2
1
+Vswinj
V =
TRIP
(V-V )
IN O
¾
2 1· ·L fSW
·VO
¾
VIN
R·DS(ON)
(I -
OCL )
R (k )=
TRIP WV (mV)-V
TRIP OCLoff
¾
I ( A)
TRIP(min) m
C=
SS
T I
SS SSC
·
¾
VFB
TPS53129
SLVSAE6B –OCTOBER 2009– REVISED JULY 2010
www.ti.com
4. Choose bootstrap capacitor.
The TPS53129 requires a bootstrap capacitor from SW to VBST to provide the floating supply for the
high-side drivers. A minimum 0.1-mF high-quality ceramic capacitor is recommended. The voltage rating
should be greater than 10 V.
5. Choose VREG5 and V5FILT capacitor.
The TPS53129 requires both the VREG5 regulator and V5FILT input are bypassed. A minimum 4.7-mF
high-quality ceramic capacitor must be connected between the VREG5 and GND for proper operation. A
minimum 1-mF high-quality ceramic capacitor must be connected between the V5FILT and GND for proper
operation. Both of these capacitors’ voltage ratings should be greater than 10 V.
6. Choose output voltage divider resistors.
The output voltage is set with a resistor divider from the output voltage node to the VFBx pin. It is
recommended to use 1% tolerance or better resisters. Select R2 between 10 kΩand 100 kΩand use
Equation 12 or Equation 13 to calculate R1.
(12)
(13)
Where
VFB(RIPPLE) = Ripple voltage at VFB
Vswinj = Ripple voltage at error comparator
7. Choose register setting for over current limit.
(14)
(15)
Where
RDS(ON) = Low side FET on-resistance
ITRIP(min) = TRIP pin source current （8.5 mA）
VOCL0ff = Minimum over current limit offset voltage (–20 mV)
IOCL = Over current limit
8. Choose soft start capacitor.
Soft start time equation is as follows.
(16)
20 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS53129
TPS53129
www.ti.com
SLVSAE6B –OCTOBER 2009 – REVISED JULY 2010
LAYOUT SUGGESTIONS
• Keep the input switching current loop as small as possible.
• Place the input capacitor (C3,C6) close to the top switching FET. The output current loop should also be kept
as small as possible.
• Keep the SW node as physically small and short as possible as to minimize parasitic capacitance and
inductance and to minimize radiated emissions. Kelvin connections should be brought from the output to the
feedback pin (FBx) of the device.
• Keep analog and non-switching components away from switching components.
• Make a single point connection from the signal ground to power ground.
• Do not allow switching current to flow under the device.
Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Link(s): TPS53129
PACKAGE OPTION ADDENDUM
www.ti.com 13-Sep-2010
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS53129PW ACTIVE TSSOP PW 24 60 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
TPS53129PWR ACTIVE TSSOP PW 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
TPS53129RGER ACTIVE VQFN RGE 24 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Request Free Samples
TPS53129RGET ACTIVE VQFN RGE 24 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Purchase Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS53129PWR TSSOP PW 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1
TPS53129RGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
TPS53129RGET VQFN RGE 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS53129PWR TSSOP PW 24 2000 367.0 367.0 38.0
TPS53129RGER VQFN RGE 24 3000 367.0 367.0 35.0
TPS53129RGET VQFN RGE 24 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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