ANALOG DEVICES LC?M0S Parallel Loading Dual 12-Bit DAC AD7947 FEATURES Two 12-Bit DACs in One Package DAC Ladder Resistance Matching: 0.5% Space Saving Skinny DIP and Surface Mount Packages 4-Quadrant Multiplication Low Gain Error (1LSB max Over Temperature} Fast Interface Timing APPLICATIONS Automatic Test Equipment Programmable Filters Audio Applications Synchro Applications Process Control GENERAL DESCRIPTION The AD7547 contains two 12-bit current output DACs on one monolithic chip. Also on-chip are the level shifters, data registers and control logic for easy microprocessor interfacing. There are 12 data inputs. CSA, CSB, WR control DAC selection and loading. Data is latched into the DAC registers on the rising edge of WR. The device is speed compatible with most micro- processors and accepts TTL, 74HC and 5V CMOS logic level inputs. The D/A converters provide 4-quadrant multiplication capabilities with separate reference inputs and feedback resistors. Monolithic construction ensures that thermal and gain error tracking is excellent. 12-bit monotonicity is guaranteed for both DACs over the full temperature range. The AD7547 is manufactured using the Linear Compatible CMOS (LC?MOS) process. This allows fast digital logic and precision linear circuitry to be fabricated on the same die. REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implica- tion or otherwise under any patent or patent rights of Analog Devices. FUNCTIONAL BLOCK DIAGRAM Voo (01) @) 0 AD7547 Resa louta (1) acno csa am 4) Vrera 22) Vrere (23) Rees CSB Go (24) louts _] wa G4 lel OPCK DAC B REGISTER (B Gey 7 _@J { DGND DB11 DBO (MSB} (LSB) PRODUCT HIGHLIGHTS 1. DAC to DAC Matching Since both DACs are fabricated on the same chip, precise matching and tracking is inherent. Many applications which are not practical using two discrete DACs are now possible. Typical matching: 0.5%. 2. Small Package Size The AD7547 is available in 0.3 wide 24-pin DIPs and SOICs and in 28-terminal surface mount packages. 3. Wide Power Supply Tolerance The device operates on a +12V to + 15V Vpp, with + 10% tolerance on this nominal figure. All specifications are guaran- teed over this range. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 Twx: 710/394-6577 Telex: 924491 Cable: ANALOG NORWOODMASSAD7547SPECIFICATIONS' war srtcstons os setment Sorc pees) Parameter J, A Versions | K, B Versions] L, C Versions | S Version T Version U Version Units Test Conditions/Comments ACCURACY Resolution 12 12 12 12 12 12 Bits Relative Accuracy =1 + 1/2 = 1/2 =1 =12 21/2 LSB max Differential Nonlinearity +1 =1 =1 =1 =1 =1 LSB max All grades guaranteed monotonic over temperature. Gain Error +6 =3 +1 +6 ~3 =2 LSB max Measured using Rega, Reps. Both DAC registers loaded with all 1's. Gain Temperature Coefficient; AGain/ATemperature +5 =5 +5 =5 =5 =5 ppm/C max | Typical value is lppm/C Output Leakage Current louta + 25C 10 10 10 10 10 10 nA max DAC A Register loaded Tmin tO Tmax 150 150 150 250 250 250 nA max with all 0s. Touts + 25C 10 10 10 10 10 10 nA max DAC B Register loaded Tinin tO Tmax 150 150 150 250 250 250 nA max with all 0s. REFERENCE INPUT Input Resistance 9 9 9 9 9 9 kQ min Typical Input Resistance -- 14k) 20 20 20 20 20 20 kOQmax Vrera, VREFB Input Resistance Match =3 +3 +) =3 23 =] % max Typically + 0.5% DIGITALINPUTS Vin (Input High Voltage) 2.4 2.4 2.4 2.4 2.4 2.4 V min Vin. (Input Low Voltage) 0.8 0.8 0.8 0.8 0.8 0.8 V max Tin input Currend) + 25C =] =1 +1 =1 +1 =1 pA max Vin = Vpp Trin t0 Tmax +10 +10 +10 =10 =10 =10 vA max Cin (Input Capacitance)? 10 10 10 10 10 10 pF max POWER SUPPLY? Vop 10.8/16.5 10.8/16.5 10.8/16.5 10.8/16.5 10.8/16.5 10.8/16.5 V min/V max Ipp 2 2 2 2 2 2 mA max + 4 +- .- L AC PERFORMANCE CHARACTERISTICS These characteristics are included for Design Guidance only and are not subject to test. (Von = +12V to + 15V; Viera = Vecrs = + 10V, loura = lourg = AGND = OV. Output Amplifiers are AD644 except where stated.) Parameter . Ta= +25C Ta = Tinias Tmax Units Test Conditions/Comments Output Current Settling Time 1.5 - ps max To 0.01% of full-scale range. Iout load = 1000, Cext = 13pF. DAC output measured from rising edge of WR. Typical Value of Settling Time is 0.85. Digital-to-Analog Glitch Impulse 7 - nV-s typ Measured with Vrrra = Vrers = OV. outa; louts load = 1002, Cex = 13pF. DAC registers alternately loaded with all 0s and all 1s. AC Feedthrough* Vrera to louta 70 65 dB max Vrera> Vrere = 20Vp-p 10kHz sinewave. DAC Vrere to loutr ~ 70 65 dB max registers loaded with all 0s. Power Supply Rejection AGain/AVpp +0.01 0.02 % per % max AVpp = Vpp max Vpp min Output Capacitance Couta 70 70 pF max DAC A, DACB loaded with all 0s. Couts 70 70 pF max Couta 140 140 pF max DAC A, DAC B loaded with all 1s. Couts 140 140 pF max Channel-to-Channel Isolation Vrera to louts 84 - dBtyp Vrera = 20V p-p 10kHz sinewave, Vrgrp = OV. Both DACs loaded with all 1s. Vererpstolouta 84 - dBtyp Vrere = 20V p-p 10kHz sinewave, Vrera =0V. Both DACs loaded with all 1s. Digital Crosstalk 7 - nV-styp Measured for a Code Transition of all 0s to all 1s. Iouta>louts Load = 1000, Ceyz = 13pF Output Noise Voltage Density 25 - nV/\Hz typ Measured between Rega and Iouta or Regg and Iouts. (10Hz-100kHz) Frequency of measurement is 10Hz-100kHz. Total Harmonic Distortion 82 - dBtyp Vin = 6V rms, 1kHz. Both DACs loaded with all 1s. . ee L ee NOTES Temperature range as follows: J, K, L Versions: - 40C to + 85C. A,B,C Versions: 40C to + 85C. S,T, U Versions: 55C to + 125C. *Sample tested at 25C to ensure compliance. Functional at Vpn = 5V with degraded specifications. Pin 12(DGND) on ceramic DIPs is connected to lid. Specifications subject to change without notice. -2- REV.AAD7547 TIMING CHARACTERISTICS w,, = 10.8v to 16.5V, Versa = Veers = +10, loura = lourg = AGND = OV) Limit at Limit at Limit at Ta= 40C Ta=55C Parameter Ta = +25C to + 85C to +125C Units Test Conditions/Comments uy 60 80 80 ns min Data Setup Time to 25 25 25 ns min Data Hold Time ts 80 80 100 ns min Chip Select to Write Setup Time ty 0 0 0 ns min Chip Select to Write Hold Time ts 80 80 100 ns min Write Pulse Width NOTE Specifications subject to change without notice. - t | tb be sv ABSOLUTE MAXIMUM RATINGS* fff, | LLL 7 (Ta = 25C unless otherwise stated) a : = . | ov VpptoDGND ...........2...0004 0.3V, +17V | Vrera> Vrers to AGND, Vrrsa> Varss to AGND, Digital Input Voltage to DGND Iouta> louts to DGND AGND toDGND .............. Power Dissipation (Any Package) To +75C Derates above +75C ... 2... 2. ee ee ee Operating Temperature Range Commercial Plastic (J, K, L Versions) ... . Industrial Hermetic (A, B, C Versions)... . 40C to +85C Extended Hermetic (S, T, U Versions) . . . . 55C to +125C Storage Temperature ............. 65C to + 150C Lead Temperature (Soldering, 10secs) + 300C +25V Cee +25V -0.3V, Vpp +0.3V -0.3V, Vpp +0.3V -0.3V, Vpp +0.3V 40C to +85C *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. FUNCTION No Data Transfer No Data Transfer A Rising Edge on CSA or CSB Loads Data to the Respective DAC from the Data Bus DAC A Register Loaded from Data Bus DAC B Register Loaded from Data Bus DAC A and DACB Registers Loaded from Data Bus oro ly = g oor 19 ol mhh c#elg NOTES 1. X = Dontcare 2._ means rising edge triggered Table |. AD7547 Truth Table CAUTION 5V CSA, CSB \ / /~ ts; "| 5y WR \ i NOTES 1, ALL INPUT SIGNAL RISE AND FALL TIMES MEASURED FROM 10% TO 90% OF +5V. t, = t, = 20n Yort 2. TIMING MEASUREMENT REFERENCE LEVEL Ig 47" Figure 1. Timing Diagram for AD7547 ORDERING GUIDE! Temperature Relative | Gain Package Model? Range Accuracy | Error | Option? AD7547JN | 40Cto +85C: | +1LSB + 6LSB | N-24 AD7547KN | 40C to + 85C: | +1/2LSB | +3LSB | N-24 AD7547LN | 40Cto +85C | +1/2LSB | +1LSB | N-24 AD7547JP | 40Cto + 85C | +1LSB + 6LSB | P-28A AD7547KP | 40C1o +85C | +1/2LSB | +3LSB | P-28A AD7547LP | 40Cto +85C | +1/2LSB | +1LSB | P-28A AD7547JR | 40Cto +85C |+1LSB + 6LSB | R-24 AD7547KR j 40Cto +85C | +1/2LSB | +3LSB | R-24 AD7547LR | 40Cto + 85C | +1/2LSB | +1LSB | R-24 AD7547AQ | 40Cto +85C | +1LSB + 6LSB | Q-24 AD7547BQ | 40Cto + 85C: | +1/2LSB | +3LSB | Q-24 AD7547CQ | 40Cto +85C: | +1/2LSB | +1LSB | Q-24 AD7547SQ_ | 55Cto + 125C | + 1LSB + 6LSB | Q-24 AD7547TQ | 55Cto + 125C | + 1/2LSB | +3LSB | Q-24 AD7547UQ | 55Cto + 125C | + 1/2LSB | +2LSB | Q-24 AD7547SE | 55Cto + 125C | + 1LSB +6LSB | E-28A AD7547TE | 55C to + 125C | + 1/2LSB | +3LSB | E-28A AD7547UE | 55Cto + 125C | + 1/2LSB | +2LSB | E-28A NOTES "Analog Devices reserves the right to ship ceramic packages (D-24A) in lieu of cerdip packages (Q-24). To order MIL-STD-883, Class B processed parts, add /883B to part number. Contact your local sales office for military data sheets. 3E = Leadless Ceramic Chip Carrier; N = Plastic DIP; P = Plastic Leaded Chip Carrier; Q = Cerdip; R = SOIC. ESD electrostatic discharge) sensitive device. The digital control inputs are diode protected; however, permanent damage may occur on unconnected devices subject to high energy electro- static fields. Unused devices must be stored in conductive foam or shunts. The protective foam should be discharged to the destination socket before devices are removed. TT en Pee ESD SENSITIVE DEVICE REV. A -3-AD7547 PIN CONFIGURATIONS 25 Voo 24 CSB 23 WR AD7547 22 NC TOP VIEW (Not to Scale} 0811 (MSB) 20 DB10 19 DBS DIP, SOIC LCCC ST ao acno [1] 24) loute $53. be oe Sf 2B oO gf > loura L2 23] Pens 4 3 2 1 28 27 26 Pron [3 22) Vaere Mi Vrera 4 211 Vop Vara CSA | 5 [20] cs8 CSA (LSB) DBO | 6 AD7547 19] WR "SBI DB0 AD7547 TOP VIEW nce DB1 7 {Not to Scale) 18 | 0B11 (MSB} TOP VIEW (Not to Scale) BI pB2 [ 8 17] pe10 DB2 oa3 f 9 16] 0B9 pB3 ope | 10 15 | DB8 DBS | 11 14} DB? 12 13 14 15 16 17 18 s w a y wo th ao DGND [12 13 | DB6 886878488 NC =NOCONNECT PIN FUNCTION DESCRIPTION (DIP) PIN MNEMONIC DESCRIPTION 1 AGND Analog Ground. 2 loutra Current output terminal of DACA. 3 Rega Feedback resistor for DACA. 4 VREFA Reference input to DACA. 5 CSA Chip Select Input for DAC A. Active low. 6-18 DBO-DB1! 12 data inputs, DBO (LSB)- DB11 (MSB). 12 DGND Digita! Ground. 19 WR Write Input. Data transfer occurs on rising edge of WR. See Table J. 20 CSB Chip Select Input for DACB. Active low. 21 Vpp Power supply input. Nominally + 12V to + 15V with + 10% tolerance. 22 VREFRB Reference input to DACB. 23 Resp Feedback resistor of DACB. 24 Ioutrs Current output terminal of DACB. CIRCUIT INFORMATION D/A SECTION The AD7547 contains two identical 12-bit multiplying D/A converters. Each DAC consists of a highly stable R-2R ladder and 12 N-channel current steering switches. Figure 2 shows a simplified D/A circuit for DAC A. In the R-2R ladder, binary weighted currents are steered between Inyra and AGND. The current flowing in each ladder leg is constant, irrespective of switch state. The feedback resistor Rega is used with an op-amp (see Figures 4 and 5) to convert the current flowing in Ioura to a voltage output. R R Vrera | 2R 2R 2R =22R < si $10 so Rrea R L I 55 I @0 'outa $5 O AGND Figure 2. Simplified Circuit Diagram for DACA EQUIVALENT CIRCUIT ANALYSIS Figure 3 shows the equivalent circuit for one of the D/A converters (DAC A) in the AD7547. A similar equivalent circuit can be drawn for DACB. Note that AGND is common to both DAC A and DAC B. Figure 3. Equivalent Analog Circuit for DACA Court is the output capacitance due to the N-channel switches and varies from about 50pF to 150pF with digital input code. The current source I, xg is composed of surface and junction leakages and approximately doubles every 10C. Ro is the equi- valent output resistance of the device which varies with input code. DIGITAL CIRCUIT INFORMATION The digital inputs are designed to be both TTL and 5V CMOS compatible. All logic inputs are static-protected MOS gates with typical input currents of less than InA. -4- REV. AAD7947 UNIPOLAR BINARY OPERATION (2-QUADRANT MULTIPLICATION) Figure 4 shows the circuit diagram for unipolar binary operation. With an ac input, the circuit performs 2-quadrant multiplication. The code table for Figure 4 is given in Table II. Operational amplifiers Al and A2 can be in a single package (AD644, AD712) or separate packages (AD544, AD711, AD OP-27). Capacitors Cl and C2 provide phase compensation to help prevent overshoot and ringing when high speed op-amps are used. For zero offset adjustment, the appropriate DAC register is loaded with all 0s and amplifier offset adjusted so that Voura or Vourg is OV. Full-scale trimming is accomplished by loading the DAC register with all 1s and adjusting R1 (R3) so that Vouta (Vouts) = Vin (4095/4096). For high temperature operation, resistors and potentiometers should have a low Tem- perature Coefficient. In many applications, because of the excellent Gain T.C. and Gain Error specifications of the AD7547, Gain Error trimming is not necessary. In fixed reference applications, full-scale can also be adjusted by omitting R1, R2, R3, R4 and trimming the reference voltage magnitude. DATA | t INPUTS; 4 ! *CONTROL CIRCUITRY OMITTED FOR CLARITY Figure 4. AD7547 Unipolar Binary Operation Binary Number in DAC Register Analog Output, MSB LSB Vouta or VoutB Wi wi uw - Vix (S096) 1000 0000 0000 - Vin 356 = -1/2Viy 0000 0000 0001 -Vix( 7%) 0000 0000 0000 ov Table Ii. Unipolar Binary Code Table for Circuit of Figure 4 REV. A BIPOLAR OPERATION (4-QUADRANT MULTIPLICATION) The recommended circuit diagram for bipolar operation is shown in Figure 5. Offset binary coding is used. With the appropriate DAC register loaded to 1000 0000 0000, adjust R1 (R3) so that Voura (Voutr) = OV. Alternatively, R1, R2 (R3, R4) may be omitted and the ratios of R6, R7 (RY, R10) varied for Voutra (Vourr) = OV. Full-scale trimming can be accomplished by adjusting the amplitude of Vyx or by varying the value of R5 (R8). If Rl, R2 (R3, R4) are not used, then resistors R5, R6, R7 (R8, R9, R10) should be ratio matched to 0.01% to ensure gain error performance to the data sheet specification. When operating over a wide temperature range, it is important that the resistors be of the same type so that their temperature coefficients match. The code table for Figure 5 is given in Table ITI. R6 20k22 AAA R7 > 10k22 R10 20k2 ANA VW *CONTROL CIRCUITRY OMITTED FOR CLARITY V Figure 5. Bipolar Operation (Offset Binary Coding) Binary Number in DAC Register Analog Output, MSB LSB Voura or Vouts 1 Wi 1111 + Vo 3047 1000 0000 0001 +Vox(so8 1000 0000 0000 ov O11) 111) 1111 -Vox( 58) 0000 0000 0000 Vox (3348) = -Viy Table Ill. Bipolar Code Table for Offset Binary Circuit of Figure 5.AD7547 Applications PROGRAMMABLE STATE VARIABLE FILTER outputs by biasing AGND to +5V with respect to DGND, The circuit shown in Figure 6 provides three filter outputs: low which in this case is also the system ground. The two DAC pass, high pass and bandpass. It is called a State Variable Filter reference inputs are also tied to system ground. and the particular version shown in Figure 6 uses two AD7547s to control the critical parameters f,, Q and Ag. Instead of several Voo 1+ 15V) fixed resistors, the circuit uses the DAC equivalent resistances as circuit elements. Thus, RI in Figure 6 is controlled by the 12-bit digital word loaded to DAC A of the AD7547. This is also the case with R2, R3 and R4. The fixed resistor RS is the feedback resistor, Regp. Vouta = +5V to +10V 4096 x Ryan DAC Equivalent Resistance, Req = N where Ry an = DAC Ladder Resistance N = DAC Digital Code in Decimal. (0<N<4095) Vouts = +5V to +10V In the circuit of Figure 6: Cl = C2, R7 = R8, R3 = R4 (..e., the same code is in each DAC) Resonant frequency, f, = ! _ SIGNAL 2a R3 Cl \/ GROUND NOTES: 1. Al: TLO272 . R6 R2 2. CONTROL CIRCUITRY OMITTED FOR CLARITY Quality Factor, Q = R8 RS Rp Figure 7. AD7547 Single Supply Operation Bandpass Gain, Ag = RL The transfer function for each channel is: Using the values shown in Figure 6 the Q range is 0.3 to 5 and 1+ Rep f, range is 0 to 12kHz. Vour = 5V ( aa C3 Reg cH With all 0s loaded to the DAC, Reg = * and Vout = +5V. w 7 With all 1s loaded Reg = Riapprr = Reg and Vovy = +10V. q 30ks) 30kKi2 q => HGH 4 Low Figure 8 shows both DACs of the AD7547 connected in the Re O PASS O PASS . . . . . oes OUTPUT outeut voltage switching mode. For further information on this mode iy of operation see the CMOS DAC Application Guide from Analog eanp Devices, publication number G872a-15-4/86. To optmize per- rass | formance when using this circuit, V;, must be in the range 0 to RON Ne a +1.25V and the output buffered. V,;, must be driven from a os Daca pace 4 DACA pace low impedance source (e.g. a buffer amplifier). Figure 9 shows how differential linearity degrades with increasing V,. AD7547 AD7547 - 21 2 wen . Voo(+15V) SIGNAL GROUND Yoo OAT a2, A3, Ad: 1:2 x AD712 0 vm sy) (+15V) 2 ALL DIGITAL INPUTS OMITTED FOR CLARITY (Oto +1. 3. C3 1S A COMPENSATION CAPACITOR TO ELIMINATE O AND GAIN VARIATIONS CAUSED BY AMPLIFIER GAIN BANDWIDTH LIMITATIONS. Vouta SIGNAL GROUND Figure 6. Programmable State Variable Filter INPUTS SINGLE SUPPLY APPLICATIONS DAC A and DAC B of the AD7547 have termination resistors which are tied to the AGND line within the device. This ar- rangement is ideal for single supply operation because AGND may be biased at any voltage between DGND and Vpp. Figure = NOTES: 7 shows a circuit which provides two +5V to + 10V analog oA e272ACUITRY OMITTED FOR CLARITY Figure 8. AD7547 Operated in Single Supply, Voltage Switching Mode -6- REV.AAD7547 (LSB) A CW ~10 Y, ss Y) vs A. Vaer - VOLTS Figure 9. Differential Nonlinearity vs. Reference Voltage for Circuit of Figure 8. Vpp=15V. Shaded Area Shows Range of Values of Differential Nonlinearity that Typically Occur for L, C and U Grades APPLICATION HINTS Output Offset: CMOS D/A converters in circuits such as Figures 4 and 5 exhibit a code dependent output resistance which in turn can cause a code dependent error voltage at the output of the amplifier. The maximum amplitude of this error, which adds to the D/A converter nonlinearity, depends on Vos, where Vos is the amplifier input offset voltage. To maintain specified operation, it is recommended that Vos be no greater than (25 x 10-6)(Vppr) over the temperature range of operation. Suitable op amps are the AD711C and its dual version, the AD712C. These op amps have a wide bandwidth and high slew rate and are recommended for wide bandwidth ac applications. AD711/ AD712 settling time to 0.01% is typically lps. Temperature Coefficients: The gain temperature coefficient of the AD7547 has a maximum value of Sppm/C and typical value of lppm/C. This corresponds to worst case gain shifts of 2LSBs and 0.4LSBs respectively over a 100C temperature range. When trim resistors R1(R3) and R2(R4) are used to adjust full-scale range as in Figure 4, the temperature coefficient of R1(R3) and R2(R4) should also be taken into account. For further information see Gain Error and Gain Temperature Coefficient of CMOS Multiplying DACs, Application Note, Publication Number E630c-5-3/86 available from Analog Devices. High Frequency Considerations: AD7547 output capacitance works in conjunction with the amplifier feedback resistance to add a pole to the open loop response. This can cause ringing or oscillation. Stability can be restored by adding a phase compen- sation capacitor in parallel with the feedback resistor. This is shown as Cl and C2 in Figures 4 and 5. Feedthrough: The dynamic performance of the AD7547 depends upon the gain and phase stability of the output amplifier, together with the optimum choice of PC board layout and decoupling components. A suggested printed circuit layout for Figure 4 is shown in Figure 10 which minimizes feedthrough from Vpgra; Vrere to the output in multiplying applications. REV.A PIN 8, AD712 V+ Qn a om ee PIN 1, AD7547 oft mney) Vine o oa oe o LAYOUT IS FOR DOUBLE-SIDED BOARD. FULL LINE INDICATES TRACK ON ad o COMPONENT SIDE. o o o o eo Qo o oe oe eo Figure 10. Suggested Layout for Circuit of Figure 4 MICROPROCESSOR INTERFACING The AD7547 is designed for easy interfacing to 16-bit micropro- cessors. Figures 11 and 12 show the interface circuits for two of the most popular 16-bit microprocessors; the 8086 and the 68000. Note that the amount of external logic needed is minimal. Since data is loaded into the DAC registers on the rising edge of WR, the possiblity of invalid data being loaded temporarily to the DAC is removed. This considerably eases the interface circuit design. Al - A23 ADDRESS BUS ( AS q ADDRESS O CsA Mc68000 DECODE jo 1 cae DTACK AD7547* WR Lbs po Do - D15 DATA BUS DBO - 0B11 Figure 11. AD7547 - MC68000 Interface *LINEAR CIRCUITRY OMITTED FOR CLARITY ADDRESS BUS g cSA csB ADDRESS DECODE 16-BIT ALE LATCH 8086 wR AD7547* WR ADO - AD15 DATA BUS DBo - DB11 *LINEAR CIRCUITRY OMITTED FOR CLARITY po Figure 12. AD7547 - 8086 InterfaceAD7947 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 24-Pin Plastic DIP (N-24) AAA AAAAAAAAA 0.260 + 0.001 (6.61 + 0.03) VVVVVVVVVV VY 1.228(31.19) 0,130 (3.30) 0.128 (3.25) 1,226(31.14) 0.32 (8.428) f 0.30(7.62) * 0.225 (6.715) SEATING TT 22! 24-Pin Cerdip (Q-24) nooo oom mom el 0.295 (7.493) MAX t aoouaunooooOoOoo 0.320 (8.128) 1.290 (32.77) MAX a 1 (0.290 (7.366) [ ] 0.180 (4.572) SEATING __\/_\/_\ 7) )/-\f\~\(=\ (=) t pane oes if -M-W WT A 0,011 (0.28) {3.175) 0.070 [1.778] a.009 1023) = o 0.020(0.508} le: ae ~ 9.021 {0.539 0.11012,794) 0.065 (1.651) 0.02 (0.5) 0.11 {2.79} 0.07 (1.78) 15 0.015 (0.381) 0.090 (2.286) 0.055 (1.397) 0.016 (0.41) 0.09 (2.28) 0.05 (1.27) oe TyYe TYP NOTES NOTES 1. LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH. 2. PLASTIC LEADS WILL BE EITHER SOLDER DIPPED OR TIN LEAD PLATED IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS. 1. LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH. 2. CERDIP LEAOS WILL BE EITHER TIN PLATED OR SOLDER DIPPED IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS. 24-Pin Ceramic DIP (D-24A) etd 2 1.200 + 0.012 (30.48 0.31} seatinc _# \)_\/ \7_\7_\ 7A) NIN D NDA NO PLANE 9.175 tea 0.018 +0.002 0.100 0.005 0.051127) {oss 20.05) = (2.54 0.13) TYP TYP 1.190 + 0.005 127.94 = 0.13) TOLNON ACCUM NOTES 1, LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH. = 0.295 0.01 (7.49 + 0.26) 0.300 + 0.010 [* (7.62 +0.25) ) 0.085 + 0.009 (2.46 +0.23) elle + 0.002 0.001 +0.05 0.03 0.010 (0.28 2. CERAMIC OIF LEADS WILL BE EITHER GOLD OR TIN PLATED IN ACCORDANCE WITH MIL-M-38S TO REQUIREMENTS. 3. METAL LID 1S CONNECTED TO DGND. 28-Terminal Leadless Ceramic Chip Carrier 28-Terminal Plastic Leaded Chip Carrier 0,045 (1.14) 0.085 (7.40) 2.78 1.91 t REF O NO.1PIN A IDENTIFIER zon A ooze (0.56) q H Fo (0.71) q a 0.430 (10.5) 0.390 (9.9) q TOP a] 0.050 + 0.005 x d VIEW D +2021 oem (1.27 0.13) NO. 1 PIN INDEX H Fo " BOTTOM VIEW q 0.032 (0.812) q a Py 0.026 10.661) 0.040 x 45 4 (1.02 45") 0.020 x 45 REF 3 PLCS [+> : A651 x 457) REF ooOoOUae (, 0.120 13.04) Tt 0.442 (11.23) af 0.456 (11,582) . 0.486 (71.63) 2.480 (11.490) 0.180 (6.51) |, 090 (2.29) 0.064 (1.63)! 0.495 (12.57) cq. 0.165 {4.20} 0.100 (2.54 0.485 (12.32) NOTES 1. THIS DIMENSION CONTROLS THE OVERALL PACKAGE THICKNESS. 2. APPLIES TO ALL FOUR SIDES. 3. ALL TERMINALS ARE GOLD PLATED. PRICING (100+) $ AD7547JN $14.50 AD7547KN $17.00 AD7547LN $23.00 AD7547AQ $19.80 AD7547BQ $22.30 AD7547CQ $28.30 AD7547SQ $60.00 AD7547TQ $70.00 AD7547UQ $85.00 REV. A C977b 5 - 6/88 PRINTED IN U.S.A.