SI4410DY - NXP SEMICONDUCTORS

SI4410DY

N-channel TrenchMOS logic level FET

Rev. 03 — 4 December 2009 Product data sheet

1. Product profile

1.1 General description

Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic

package using TrenchMOS technology. This product is designed and qualified for use in

computing, communications, consumer and industria l applications only.

1.2 Features and benefits

Low conduction losses due to low

on-state resistance

Suitable for high frequency

applicat ion s du e to fast swit ch ing

characteristics

1.3 Applications

DC motor control

DC-to-DC convertors

Lithium-ion batt er y applica tio n s

Notebook computers

Porta ble equipment

1.4 Quick reference data

Table 1. Quick reference

Symbol Parameter Conditions Min Typ Max Unit

VDS drain-source voltage Tj≥25 °C; Tj≤150 °C - - 30 V

IDdrain current Tamb = 25 °C; pulsed;

see Figure 1 and 3--10A

Ptot total power

dissipation Tamb = 25 °C; pulsed;

see Figure 2 --2.5W

Dynamic characteristics

QGD gate-drain charge VGS =10V; I

D=10A;

VDS =15V; T

j=25°C;

see Figure 12

-7-nC

Static characteristics

RDSon drain-source

on-state resistance VGS = 4.5 V; ID=5A;

Tj=25°C;

see Figure 10 and 11

- 1520mΩ

VGS =10V; I

D=10A;

Tj=25°C;

see Figure 10 and 11

- 11 13.5 mΩ

Product data sheet Rev. 03 — 4 December 2009 2 of 12

NXP Semiconductors SI4410DY

N-channel TrenchMOS logic level FET

2. Pinning information

3. Ordering information

4. Limiting values

Table 2. Pinning information

Pin Symbol Description Simplified outline Graphic symbol

1S source

SOT96-1 (SO8)

2S source

3S source

4G gate

5D drain

6D drain

7D drain

8D drain

bb076

Table 3. Orderi ng informatio n

Type number Package

Name Description Version

SI4410DY SO8 plastic small outline package; 8 leads; body width 3.9 mm SOT96-1

Table 4. Limiting values

In accordance with the Absolute Maxi mum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VDS drain-source voltage Tj≥25 °C; Tj≤150 °C - 30 V

VGS gate-source voltage -20 20 V

IDdrain current Tamb = 70 °C; pulsed;

see Figure 1 -8A

Tamb = 25 °C; pulsed;

see Figure 1 and 3-10A

IDM peak drain current tp≤10 µs; Tamb = 25 °C; pulsed;

see Figure 3 -50A

Ptot total power dissipation Tamb = 70 °C; pulsed;

see Figure 2 -1.6W

Tamb = 25 °C; pulsed;

see Figure 2 -2.5W

Tstg storage temperature -55 150 °C

Tjjunction temperature -55 150 °C

Source-drain diode

ISsource current Tamb = 25 °C; pulsed - 2.3 A

Product data sheet Rev. 03 — 4 December 2009 3 of 12

NXP Semiconductors SI4410DY

N-channel TrenchMOS logic level FET

Fig 1. Normalized continuous drain current as a

function of ambient temperature Fig 2. Normalized total power dissipation as a

function of ambient temperature

Fig 3. Safe operating area; continuous and peak drain curren ts as a function of drain-source voltage

03aa19

120

0 50 100 150 200

Tamb (°C)

Ider

(%)

03aa11

120

0 50 100 150 200

Tamb (°C)

Pder

(%)

03ae23

10−1

102

(A)

10−2

VDS (V)

10−1102

101

10 s

100 ms

10 ms

1 ms

tp = 10

D.C.

RDSon = VDS/ID

δ =

Product data sheet Rev. 03 — 4 December 2009 4 of 12

NXP Semiconductors SI4410DY

N-channel TrenchMOS logic level FET

5. Thermal characteristics

Table 5. Thermal characteristics

Symbol Parameter Conditions Min Typ Max Unit

Rth(j-sp) thermal resistance from

junction to solder point ---K/W

Rth(j-a) thermal resistance from

junction to ambient mounted on a printed-circuit board;

minimum footprint; tp ≤ 10 s;

see Figure 4

--50K/W

Fig 4. Transient thermal impedance from junction to solder point as a function of pulse duration

03ad49

−2

−1

−4

−3

−2

−1

1 10 10

(s)

Zth(j-amb)

(K/W)

single pulse

δ = 0.5

0.2

0.1

0.05

0.02

δ =

Product data sheet Rev. 03 — 4 December 2009 5 of 12

NXP Semiconductors SI4410DY

N-channel TrenchMOS logic level FET

6. Characteristics

Table 6. Characteristics

Symbol Parameter Conditions Min Typ Max Unit

Static characteristics

VGS(th) gate-source threshold

voltage ID=250µA; V

DS= VGS; Tj=25°C;

see Figure 9 1- - V

IDSS drain leakage current VDS =30V; V

GS =0V; T

j=25°C --1µA

VDS =30V; V

GS =0V; T

j=55°C --25µA

IGSS gate leakage current VGS =20V; V

DS =0V; T

j= 25 °C - - 100 nA

VGS =-20V; V

DS =0V; T

j= 25 °C - - 100 nA

RDSon drain-source on-state

resistance VGS =4.5V; I

D=5A; T

j=25°C;

see Figure 10 and 11 -1520mΩ

VGS =10V; I

D=10A; T

j=25°C;

see Figure 10 and 11 -1113.5mΩ

IDSon on-state drain-source

current VDS ≥5V; V

GS =10V 20 - - A

Dynamic character i stics

QG(tot) total gate charge ID=10A; V

DS =15V; V

GS =5V;

Tj=25°C; see Figure 12 - 21.5 34 nC

ID=10A; V

DS =15V; V

GS =10V;

Tj=25°C; see Figure 12 -4060nC

QGS gate-source charge - 8 - nC

QGD gate-drain charge - 7 - nC

td(on) turn-on delay time VDS =25V; R

L=25Ω; VGS =10V;

RG(ext) =6Ω; Tj=25°C - 13.5 30 ns

trrise time - 9 20 ns

td(off) turn-off delay time - 70 100 ns

tffall time - 30 80 ns

gfs transfer conductance VDS =15V; I

D=10A; T

j=25°C;

see Figure 13 -34-S

Source-drain diode

VSD source-drain voltage IS= 2.3 A; VGS =0V; T

j=25°C;

see Figure 14 -0.71.1V

trr reverse recovery time IS= 2.3 A; dIS/dt = -100 A/µs; VGS =0V;

VDS =25V; T

j=25°C -5080ns

Product data sheet Rev. 03 — 4 December 2009 6 of 12

NXP Semiconductors SI4410DY

N-channel TrenchMOS logic level FET

Fig 5. Output characteristics: drain current as a

function of drain-source voltage; typical values Fig 6. Transfer characteristics: drain current as a

function of gate-source vo ltage; typical values

Fig 7. Sub-threshold drain current as a function of

gate-source voltage Fig 8. Input, output and reverse transfer capacitances

as a function of drain-source voltage; typical

values

03ad50

0 0.5 1 1.5

VDS

(V)

(A)

3 V

3.2 V

3.4 V

3.6 V

3.8 V10 V

2.8 V

5 V

VGS = 2.6 V

03ad52

01234

(V)

(A)

> I

x R

DSon

= 150 °C

25 °C

03aa36

10-6

10-5

10-4

10-3

10-2

10-1

0123

VGS (V)

(A)

maxtypmin

03ad54

103

104

10−1 1 10 102

VDS (V)

(pF)

Ciss

Coss

Crss

Product data sheet Rev. 03 — 4 December 2009 7 of 12

NXP Semiconductors SI4410DY

N-channel TrenchMOS logic level FET

Fig 9. Gate-source threshold voltage as a function of

junction temperature Fig 10. Drain-source on-state resistance as a function

of drain current; typical values

Fig 11. Normalized drain-source on-state resistance

factor as a function of junction temperature Fig 12. Gate-source voltage as a function of gate

charge; typical values

03aa33

0.5

1.5

2.5

-60 0 60 120 180

Tj (°C)

VGS(th)

(V)

max

typ

min

03ad51

0.01

0.02

0.03

0 1020304050

ID (A)

RDSon

(Ω)

Tj = 25 °C VGS = 3.2 V

5 V

10 V

3.4 V 3.6 V

4.5 V

3.8 V

03ad57

−60 0 60 120 180

Tj (°C)

0.5

1.5

03ad55

0 10203040

QG (nC)

VGS

(V)

ID = 10 A

Tj = 25 ºC

VDD = 15 V

Product data sheet Rev. 03 — 4 December 2009 8 of 12

NXP Semiconductors SI4410DY

N-channel TrenchMOS logic level FET

Fig 13. Forward transconductance as a function of

drain current; typical values Fig 14. Source current as a function of source-drain

voltage; typical values

03ae24

0 1020304050

ID (A)

gfs

(S)

j = 25 °C

150 °C

VDS > ID x RDSon

03ad53

0 0.4 0.8 1.2 1.6

VSD (V)

(A)

Tj = 25 °C

150 °C

VGS = 0 V

Product data sheet Rev. 03 — 4 December 2009 9 of 12

NXP Semiconductors SI4410DY

N-channel TrenchMOS logic level FET

7. Package outline

Fig 15. Package outline SOT96-1 (SO8)

UNIT A

max. A1A2A3bpcD

(1) E(2) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

1.75 0.25

0.10

1.45

1.25 0.25 0.49

0.36

0.25

0.19

5.0

4.8

4.0

3.8 1.27 6.2

5.8 1.05 0.7

0.6

0.7

0.3 8

0.25 0.10.25

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

1.0

0.4

SOT96-1

detail X

vMA

(A )

pin 1 index

076E03 MS-012

0.069 0.010

0.004

0.057

0.049 0.01 0.019

0.014

0.0100

0.0075

0.20

0.19

0.16

0.15 0.05 0.244

0.228

0.028

0.024

0.028

0.012

0.010.010.041 0.004

0.039

0.016

0 2.5 5 mm

scale

O8: plastic small outline package; 8 leads; body width 3.9 mm SOT96

-1

99-12-27

03-02-18

Product data sheet Rev. 03 — 4 December 2009 10 of 12

NXP Semiconductors SI4410DY

N-channel TrenchMOS logic level FET

8. Revision history

Table 7. Revision history

Document ID Release date Data sheet status Change notice Supersedes

SI4410DY_3 20091204 Product data sheet - SI4410DY-02

Modifications: •The format of this data sheet has been redesigned to comply with the new identity

guidelines of NXP Semiconductors.

•Legal texts have been adapted to the new company name where appropriate .

SI4410DY-02 20010705 Product specification - SI4410DY-01

SI4410DY-01 20010220 Product specification - -

Product data sheet Rev. 03 — 4 December 2009 11 of 12

NXP Semiconductors SI4410DY

N-channel TrenchMOS logic level FET

9. Legal information

9.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term 'short data sheet' is explained in section "Definitions".

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest pro duct

status information is available on the Internet at URLhttp://www.nxp.com.

9.2 Definitions

Draft— The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warrant ies as to t he accuracy or completeness of

information included herein and shall have no liab ility for the consequences of

use of such information.

Short data s heet— A short data sheet is an extract from a full dat a sheet with

the same product type number(s) and title. A short data sheet is intended for

quick reference only and sh ould not be re lied upon to co ntain detailed and full

information. For detailed and full informat i on see the relevant full data sheet,

which is available on request via the local NXP Semiconductors sales office.

In case of any inconsistency or conflict with the short data sheet, the full data

sheet shall prevail.

9.3 Disclaimers

General— Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does no t give any representa tions or

warranties, expressed or impli ed, as to the accuracy or completeness of such

information and shall have no liability for th e co nsequences of use of such

information.

Right to make changes— NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all informa tion supplied prior

to the publication hereof .

Suitability for use— NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, milit ary, aircraf t,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environment al

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Applications— Applications that are described herein for any of these

products are for il lustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Quick reference data— The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

Limiting values— Stress above one or more limiting values (as defined in

the Absolute Maximum Rati ngs System of I EC 60134) may cause perman ent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other co nditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may af fect device reliability.

Terms and conditions of sale— NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

athttp://www.nxp.com/profile/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conflict between inf ormation in this document and such

terms and conditions, the latter will prevail.

No offer to sell or license — Not hing in t his docume nt may b e int erpret ed or

construed as an of fer t o sell product s that is open for accept ance or the gr ant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property right s.

Export control— This document as well as the item(s) described here in may

be subject to export control regulations. Export might require a prior

authorization from national authorities.

9.4 Trademarks

Notice: All refe renced brands, produc t names, service names and trademarks

are the property of their respective ow ners.

TrenchMOS— is a tradema r k of NXP B.V.

10. Contact information

For more information, please visit:http://www.nxp.com

For sales office addresses, please send an email to:salesaddresses@nxp.com

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the objective specification for product development.

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.

Product [short] dat a sheet Production This doc ument contains the product specification.

NXP Semiconductors SI4410DY

N-channel TrenchMOS logic level FET

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 4 December 2009

Document identifier: SI4410DY_3

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

11. Contents

1 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1

1.1 General description . . . . . . . . . . . . . . . . . . . . . .1

1.2 Features and benefits. . . . . . . . . . . . . . . . . . . . .1

1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

1.4 Quick reference data . . . . . . . . . . . . . . . . . . . . .1

2 Pinning information. . . . . . . . . . . . . . . . . . . . . . .2

3 Ordering information. . . . . . . . . . . . . . . . . . . . . .2

4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .2

5 Thermal characteristics . . . . . . . . . . . . . . . . . . .4

6 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . .5

7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . .9

8 Revision history. . . . . . . . . . . . . . . . . . . . . . . . .10

9 Legal information. . . . . . . . . . . . . . . . . . . . . . . .11

9.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . .11

9.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

9.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . .11

9.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .11

10 Contact information. . . . . . . . . . . . . . . . . . . . . .11