IRFR1010Z - International Rectifier

9/29/04

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HEXFET® is a registered trademark of International Rectifier.

HEXFET® Power MOSFET

VDSS = 55V

RDS(on) = 7.5mΩ

ID = 42A

Specifically designed for Automotive applications,

this HEXFET® Power MOSFET utilizes the latest

processing techniques to achieve extremely low

on-resistance per silicon area. Additional features

of this design are a 175°C junction operating

temperature, fast switching speed and improved

repetitive avalanche rating . These features com-

bine to make this design an extremely efficient and

reliable device for use in Automotive applications

and a wide variety of other applications.

Description

lAdvanced Process Technology

lUltra Low On-Resistance

l175°C Operating Temperature

lFast Switching

lRepetitive Avalanche Allowed up to Tjmax

Features

D-Pak

IRFR1010Z

I-Pak

IRFU1010Z

AUTOMOTIVE MOSFET

PD - 96897

IRFR1010Z

IRFU1010Z

Absolute Maximum Ratings

Parameter Units

ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Silicon Limited)

ID @ TC = 100°C Continuous Drain Current, VGS @ 10V A

ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Package Limited)

IDM Pulsed Drain Current

PD @TC = 25°C Power Dissipation W

Linear Derating Factor W/°C

VGS Gate-to-Source Voltage V

EAS (Thermally limited) Single Pulse Avalanche Energy

EAS (Tested ) Single Pulse Avalanche Energy Tested Value

IAR Avalanche Current

c

EAR Repetitive Avalanche Energy

TJ Operating Junction and

TSTG Storage Temperature Range °C

Soldering Temperature, for 10 seconds

Mounting Torque, 6-32 or M3 screw

Thermal Resistance

Parameter Typ. Max. Units

RθJC Junction-to-Case

––– 1.11

RθJA Junction-to-Ambient (PCB mount)

––– 40 °C/W

RθJA Junction-to-Ambient

––– 110

220

110

See Fig.12a, 12b, 15, 16

140

0.9

± 20

Max.

360

-55 to + 175

300 (1.6mm from case )

10 lbf

in (1.1N

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Parameter Min. Typ. Max. Units

V(BR)DSS Drain-to-Source Breakdown Voltage 55 ––– ––– V

∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient ––– 0.051 ––– V/°C

RDS(on) Static Drain-to-Source On-Resistance ––– 5.8 7.5 mΩ

VGS(th) Gate Threshold Voltage 2.0 ––– 4.0 V

gfs Forward Transconductance 31 ––– ––– S

IDSS Drain-to-Source Leakage Current ––– ––– 20 µA

––– ––– 250

IGSS Gate-to-Source Forward Leakage ––– ––– 200 nA

Gate-to-Source Reverse Leakage ––– ––– -200

QgTotal Gate Charge ––– 63 95

Qgs Gate-to-Source Charge ––– 17 ––– nC

Qgd Gate-to-Drain ("Miller") Charge ––– 23 –––

td(on) Turn-On Delay Time ––– 17 –––

trRise Time ––– 76 –––

td(off) Turn-Off Delay Time ––– 42 ––– ns

tfFall Time ––– 48 –––

LDInternal Drain Inductance ––– 4.5 ––– Between lead,

nH 6mm (0.25in.)

LSInternal Source Inductance ––– 7.5 ––– from package

and center of die contact

Ciss Input Capacitance ––– 2840 –––

Coss Output Capacitance ––– 470 –––

Crss Reverse Transfer Capacitance ––– 250 ––– pF

Coss Output Capacitance ––– 1630 –––

Coss Output Capacitance ––– 360 –––

Coss eff. Effective Output Capacitance ––– 560 –––

Source-Drain Ratin

s and Characteristics

Parameter Min. Typ. Max. Units

ISContinuous Source Current ––– ––– 42

(Body Diode) A

ISM Pulsed Source Current ––– ––– 360

(Body Diode)

c

VSD Diode Forward Voltage ––– ––– 1.3 V

trr Reverse Recovery Time ––– 24 36 ns

Qrr Reverse Recovery Charge ––– 20 30 nC

ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

VGS = 10V

VDD = 28V

ID = 42A

RG = 7.6 Ω

TJ = 25°C, IS = 42A, VGS = 0V

TJ = 25°C, IF = 42A, VDD = 28V

di/dt = 100A/µs

Conditions

VGS = 0V, ID = 250µA

Reference to 25°C, ID = 1mA

VGS = 10V, ID = 42A

VDS = VGS, ID = 100µA

VDS = 55V, VGS = 0V

VDS = 55V, VGS = 0V, TJ = 125°C

MOSFET symbol

showing the

integral reverse

p-n junction diode.

Conditions

VGS = 10V

VGS = 0V

VDS = 25V

ƒ = 1.0MHz

VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz

VGS = 0V, VDS = 44V, ƒ = 1.0MHz

VGS = 0V, VDS = 0V to 44V

VGS = 20V

VGS = -20V

VDS = 44V

VDS = 25V, ID = 42A

ID = 42A

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Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics

Fig 3. Typical Transfer Characteristics Fig 4. Typical Forward Transconductance

vs. Drain Current

0.1 110 100

VDS, Drain-to-Source Voltage (V)

100

1000

ID, Drain-to-Source Current (A)

VGS

TOP 15V

10V

8.0V

7.0V

6.0V

5.5V

5.0V

BOTTOM 4.5V

≤60µs PULSE WIDTH

Tj = 25°C

4.5V

0.1 110 100

VDS, Drain-to-Source Voltage (V)

100

1000

ID, Drain-to-Source Current (A)

VGS

TOP 15V

10V

8.0V

7.0V

6.0V

5.5V

5.0V

BOTTOM 4.5V

≤60µs PULSE WIDTH

Tj = 175°C

4.5V

246810

VGS, Gate-to-Source Voltage (V)

0.1

100

1000

ID, Drain-to-Source Current

(Α)

TJ = 25°C

TJ = 175°C

VDS = 25V

≤60µs PULSE WIDTH

0 20406080100

ID,Drain-to-Source Current (A)

100

120

Gfs, Forward Transconductance (S)

TJ = 25°C

TJ = 175°C

VDS = 10V

380µs PULSE WIDTH

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Fig 8. Maximum Safe Operating Area

Fig 6. Typical Gate Charge vs.

Gate-to-Source Voltage

Fig 5. Typical Capacitance vs.

Drain-to-Source Voltage

Fig 7. Typical Source-Drain Diode

Forward Voltage

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

VSD, Source-to-Drain Voltage (V)

0.10

1.00

10.00

100.00

1000.00

ISD, Reverse Drain Current (A)

TJ = 25°C

TJ = 175°C

VGS = 0V

110 100

VDS, Drain-to-Source Voltage (V)

1000

2000

3000

4000

5000

C, Capacitance(pF)

VGS = 0V, f = 1 MHZ

Ciss = Cgs + Cgd, Cds SHORTED

Crss = Cgd

Coss = Cds + Cgd

Coss

Crss

Ciss

0 20406080100

QG Total Gate Charge (nC)

VGS, Gate-to-Source Voltage (V)

VDS= 44V

VDS= 28V

VDS= 11V

ID= 42A

1 10 100

VDS , Drain-toSource Voltage (V)

0.1

100

1000

10000

ID, Drain-to-Source Current (A)

Tc = 25°C

Tj = 175°C

Single Pulse

1msec

10msec

OPERATION IN THIS AREA

LIMITED BY RDS(on)

100µsec

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Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case

Fig 9. Maximum Drain Current vs.

Case Temperature

Fig 10. Normalized On-Resistance

vs. Temperature

25 50 75 100 125 150 175

TC , Case Temperature (°C)

100

ID , Drain Current (A)

LIMITED BY PACKAGE

-60 -40 -20 020 40 60 80 100 120 140 160 180

TJ , Junction Temperature (°C)

0.5

1.0

1.5

2.0

2.5

RDS(on) , Drain-to-Source On Resistance

(Normalized)

ID = 42A

VGS = 10V

1E-006 1E-005 0.0001 0.001 0.01 0.1

t1 , Rectangular Pulse Duration (sec)

0.001

0.01

0.1

Thermal Response ( Z

thJC )

0.20

0.10

D = 0.50

0.02

0.01

0.05

SINGLE PULSE

( THERMAL RESPONSE )

Notes:

1. Duty Factor D = t1/t2

2. Peak Tj = P dm x Zthjc + Tc

Ri (°C/W) τi (sec)

0.3854 0.000251

0.3138 0.001092

0.4102 0.015307

τJ

τ1

τ2

τ2τ3

τ3

R1R2

R2R3

τC

Ci τi/Ri

Ci= τi/Ri

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QGS QGD

Charge

10 V

Fig 13b. Gate Charge Test Circuit

Fig 13a. Basic Gate Charge Waveform

Fig 12c. Maximum Avalanche Energy

vs. Drain Current

Fig 12b. Unclamped Inductive Waveforms

Fig 12a. Unclamped Inductive Test Circuit

(BR)DSS

Fig 14. Threshold Voltage vs. Temperature

0.01

Ω

D.U.T

VDS

-V

DRIVER

15V

20V

VGS

VCC

DUT

25 50 75 100 125 150 175

Starting TJ, Junction Temperature (°C)

100

200

300

400

500

EAS, Single Pulse Avalanche Energy (mJ)

I D

TOP 7.6A

11A

BOTTOM 42A

-75 -50 -25 025 50 75 100 125 150 175

TJ , Temperature ( °C )

1.0

1.5

2.0

2.5

3.0

3.5

4.0

VGS(th) Gate threshold Voltage (V)

ID = 1.0mA

ID = 250µA

ID = 100µA

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Fig 15. Typical Avalanche Current vs.Pulsewidth

Fig 16. Maximum Avalanche Energy

vs. Temperature

Notes on Repetitive Avalanche Curves , Figures 15, 16:

(For further info, see AN-1005 at www.irf.com)

1. Avalanche failures assumption:

Purely a thermal phenomenon and failure occurs at a

temperature far in excess of Tjmax. This is validated for

every part type.

2. Safe operation in Avalanche is allowed as long asTjmax is

not exceeded.

3. Equation below based on circuit and waveforms shown in

Figures 12a, 12b.

4. PD (ave) = Average power dissipation per single

avalanche pulse.

5. BV = Rated breakdown voltage (1.3 factor accounts for

voltage increase during avalanche).

6. Iav = Allowable avalanche current.

7. ∆T = Allowable rise in junction temperature, not to exceed

Tjmax (assumed as 25°C in Figure 15, 16).

tav = Average time in avalanche.

D = Duty cycle in avalanche = tav ·f

ZthJC(D, tav) = Transient thermal resistance, see figure 11)

PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC

Iav = 2DT/ [1.3·BV·Zth]

EAS (AR) = PD (ave)·tav

1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01

tav (sec)

0.1

100

1000

Avalanche Current (A)

0.05

Duty Cycle = Single Pulse

0.10

Allowed avalanche Current vs

avalanche pulsewidth, tav

assuming ∆Tj = 25°C due to

avalanche losses

0.01

25 50 75 100 125 150 175

Starting TJ , Junction Temperature (°C)

100

120

EAR , Avalanche Energy (mJ)

TOP Single Pulse

BOTTOM 1% Duty Cycle

ID = 42A

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Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel

HEXFET® Power MOSFETs

Circuit Layout Considerations

• Low Stray Inductance

• Ground Plane

• Low Leakage Inductance

Current Transformer

P.W. Period

di/dt

Diode Recovery

dv/dt

Ripple ≤5%

Body Diode Forward Drop

Re-Applied

Voltage

Reverse

Recovery

Current

Body Diode Forward

Current

VGS=10V

VDD

ISD

Driver Gate Drive

D.U.T. ISD Waveform

D.U.T. VDS Waveform

Inductor Curent

D = P. W .

Period

* VGS = 5V for Logic Level Devices







RGVDD

• dv/dt controlled by RG

• Driver same type as D.U.T.

• ISD controlled by Duty Factor "D"

• D.U.T. - Device Under Test

D.U.T



90%

10%

d(on)

d(off)

VDS

Pulse Width ≤ 1 µs

Duty Factor ≤ 0.1 %

VGS

D.U.T.

10V

VDD

Fig 18a. Switching Time Test Circuit

Fig 18b. Switching Time Waveforms

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D-Pak (TO-252AA) Package Outline

Dimensions are shown in millimeters (inches)

6.73 (.265)

6.35 (.250)

- A -

1 2 3

6.22 (.245)

5.97 (.235)

- B -

3X 0.89 (.035)

0.64 (.025)

0.25 (.010) M A M B

4.57 (.180)

2.28 (.090)

2X 1.14 (.045)

0.76 (.030)

1.52 (.060)

1.15 (.045)

1.02 (.040)

1.64 (.025)

5.46 (.215)

5.21 (.205)

1.27 (.050)

0.88 (.035)

2.38 (.094)

2.19 (.086) 1.14 (.045)

0.89 (.035)

0.58 (.023)

0.46 (.018)

6.45 (.245)

5.68 (.224)

0.51 (.020)

MIN.

0.58 (.023)

0.46 (.018)

LEAD ASSIGNMENTS

1 - GATE

2 - DRAIN

3 - SOURCE

4 - DRAIN

10.42 (.410)

9.40 (.370)

NOTES:

1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982.

2 CONTROLLING DIMENSION : INCH.

3 CONFORMS TO JEDEC OUTLINE TO-252AA.

4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP,

SOLDER DIP MAX. +0.16 (.006).

D-Pak (TO-252AA) Part Marking Information

INTERNATIONAL

LOGO

RECTIFIER

3412

IRFR120

916A

LOT CODE

AS S E MB L Y

EXAMPLE:

WI T H AS S E MB L Y

THIS IS AN IRFR120

YEAR 9 = 1999

DAT E CODE

LINE A

WEEK 16

IN THE AS SEMBLY LINE "A"

AS S EMBLED ON WW 16, 1999

LOT CODE 1234

PART NUMBER

Note: "P" in assembly line

pos ition indicates "L ead-F ree"

P916A

IRFR120

LOT CODE

AS S E MB L Y

INTERNATIONAL

RECT IFIER

LOGO

PART NUMBER

WE E K 16

A = AS S E MB L Y S I T E CODE

DAT E CODE

YEAR 9 = 1999

P = DE S I GNAT E S L E AD-F R E E

PRODUCT (OPTIONAL)

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I-Pak (TO-251AA) Package Outline

Dimensions are shown in millimeters (inches)

6.73 (.265)

6.35 (.250)

- A -

6.22 (.245)

5.97 (.235)

- B -

3X 0.89 (.035)

0.64 (.025)

0.25 (.010) M A M B

2.28 (.090)

1.14 (.045)

0.76 (.030)

5.46 (.215)

5.21 (.205)

1.27 (.050)

0.88 (.035)

2.38 (.094)

2.19 (.086)

1.14 (.045)

0.89 (.035)

0.58 (.023)

0.46 (.018)

LEAD ASSIGNMENTS

1 - GATE

2 - DRAIN

3 - SOURCE

4 - DRAIN

NOTES:

1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982.

2 CONTROLLING DIMENSION : INCH.

3 CONFORMS TO JEDEC OUTLINE TO-252AA.

4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP,

SOLDER DIP MAX. +0.16 (.006).

9.65 (.380)

8.89 (.350)

2.28 (.090)

1.91 (.075)

1.52 (.060)

1.15 (.045)

1 2 3

6.45 (.245)

5.68 (.224)

0.58 (.023)

0.46 (.018)

I-Pak (TO-251AA) Part Marking Information

ASSEMBLY

EXAMPLE:

WITH ASSEMBLY

THIS IS AN IRFU120

YEAR 9 = 1999

DAT E CODE

LINE A

WEEK 19

IN THE ASSEMBLY LINE "A"

AS S E MBLED ON WW 19, 1999

LOT CODE 5678

PART NUMBER

IRFU120

INTERNAT IONAL

LOGO

RECTIFIER

LOT CODE

919A

Note: "P" in as s embly line

pos ition indicates "L ead-F ree"

56 78

ASSEMBLY

LOT CODE

RECTIFIER

LOGO

INT ERNATIONAL

IRF U120

PART NUMBER

WE E K 1 9

DAT E CODE

YEAR 9 = 1999

A = AS S E MB L Y S IT E CODE

P = DESIGNATES LEAD-FREE

PRODUCT (OPTIONAL)

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Data and specifications subject to change without notice.

This product has been designed for the Automotive [Q101] market.

Qualification Standards can be found on IR’s Web site.

D-Pak (TO-252AA) Tape & Reel Information

Dimensions are shown in millimeters (inches)

16.3 ( .641 )

15.7 ( .619 )

8.1 ( .318 )

7.9 ( .312 )

12.1 ( .476 )

11.9 ( .469 ) FEED DIRECTION FEED DIRECTION

16.3 ( .641 )

15.7 ( .619 )

TRR TRL

NOTES :

1. CONTROLLING DIMENSION : MILLIMETER.

2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).

3. OUTLINE CONFORMS TO EIA-481 & EIA-541.

NOTES :

1. OUTLINE CONFORMS TO EIA-481.

16 mm

13 INCH

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105

TAC Fax: (310) 252-7903

Visit us at www.irf.com for sales contact information.9/04

 Repetitive rating; pulse width limited by

max. junction temperature. (See fig. 11).

 Limited by TJmax, starting TJ = 25°C, L = 0.13mH

RG = 25Ω, IAS = 42A, VGS =10V. Part not

recommended for use above this value.

Pulse width ≤ 1.0ms; duty cycle ≤ 2%.

Notes:

 Coss eff. is a fixed capacitance that gives the same charging time

as Coss while VDS is rising from 0 to 80% VDSS .

 Limited by TJmax , see Fig.12a, 12b, 15, 16 for typical repetitive

avalanche performance.

 This value determined from sample failure population. 100%

tested to this value in production.

 When mounted on 1" square PCB (FR-4 or G-10 Material) .

For recommended footprint and soldering techniques refer to

application note #AN-994

 Rθ is measured at TJ approximately 90°C

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Note: For the most current drawings please refer to the IR website at:

http://www.irf.com/package/

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