Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
Description
The Atmel® | SMART SAM9XE microcontroller series is based on the integration
of an ARM926EJ-S™ processor with fast ROM, RAM and Flash, and a wide
range of peripherals.
The embedded Flash memory can be programmed in-system via the JTAG-ICE
interface or via a parallel interface on a production programmer prior to mounting.
Built-in lock bits, a security bit and MMU protect the firmware from accidental
overwrite and preserve its confidentiality.
The SAM9XE series embeds an Eth ernet MAC, o ne USB Device Port, and a USB
Host Controller. It also integrates several standard peripherals, including six
UARTs, SPI, TWI, Timer Counters, Synchronou s Serial Controller, ADC and a
MultiMedia/SD Card Interface.
The SAM9XE system controller includes a reset controller capable of managing
the power-on sequence of th e microcontroller a nd the complete sys tem. Correct
device operatio n can be monitored by a built-in brownout detector and a watchdog
running off an integrated RC oscillator.
The SAM9XE series architecture includes a 6-layer matrix, allowing a maximum
internal bandwidth of six 32-bit buses. It also features an External Bus Interface
capable of interfacing with a wide range of memory devices.
The pinout and ball-out are fully compatible with the Atmel | SMART SAM9260
eMPU with the exception that the pin BMS is replaced by the pin ERASE.
SAM9XE Embedded Internal Memories Configuration
Device ROM SRAM High-speed Flash
SAM9XE128 32 KB 16 KB 128 KB
SAM9XE256 32 KB 32 KB 256 KB
SAM9XE512 32 KB 32 KB 512 KB
SAM9XE Series
Atmel | SMART ARM-based Embedded MCU
DATASHEET
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
2
Features
Incorporates the ARM926EJ-S ARM® Thumb® Processor
DSP instruction Extensions, ARM Jazelle® Technology for Java® Acceleration
8 KB Data Cache, 16 KB Instruction Cache, Write Buffer
200 MIPS at 180 MHz
Memory Management Unit
EmbeddedICE, Debug Communication Channel Support
Additional Embedded Memories
One 32 KB Internal ROM, Single-cycle Access at Maximum Matrix Speed
One 32 KB (SAM9XE256 and SAM9XE512) or 16 KB (SAM9XE128) Internal SRAM, Single-cycle Access at
Maximum Matrix Speed
Internal High-speed Flash: 128 KB (SAM9XE128), 256 KB (SAM9XE256) or 512 KB (SAM9XE512) organized
in 256, 512 or 1024 pages of 512 bytes respectively
128-bit Wide Access
Fast Read Time: 45 ns
Page Programming Time: 4 ms, Including Page Auto-erase
Full Erase Time: 10 ms
10,000 Write Cycles, 10 Years Data Retention, Page Lock Capabilities, Flash Security Bit
Enhanced Embedded Flash Controller (EEFC)
Interface of the Flash Block with the 32-bit Internal Bus
Increases Performance in ARM and Thumb Mode with 128-bit Wide Memory Interface
External Bus Interface (EBI)
Supports SDRAM, Static Memory, ECC-enabled NAND Flash and CompactFlash®
USB 2.0 Full Speed (12 Mbit/s) Device Port
On-chip Transceiver, 2688-byte Configurable Integrated DPRAM
USB 2.0 Full Speed (12 Mbit/s) Host Single Port in 208-pin PQFP Device and Double Port in 217-ball LFBGA
Device
Single or Dual On-chip Transceivers
Integrated FIFOs and Dedicated DMA Channels
Ethernet MAC 10/100 Base-T
Media Independent Interface (MII) or Reduced Media Independent Interface (RMII)
128-byte FIFOs and Dedicated DMA Channels for Receive and Transmit
Image Sensor Interface (ISI)
ITU-R BT. 601/656 External Interface, Programmable Frame Capture Rate
12-bit Data Interface for Support of High Sensibility Sensors
SAV and EAV Synchronization, Preview Path with Scaler, YCbCr Format
Bus Matrix
Six 32-bit-layer Matrix
Remap Command
Fully-featured System Controller, including
Reset Controller (RSTC), Shutdown Controller (SHDWC)
128-bit (4 x 32-bit) General Purpose Backup Registers
Clock Generator and Power Management Controller
Advanced Interrupt Controller (AIC) and Debug Unit (DBGU)
Periodic Interval Timer (PIT), Watchdog Timer (WDT) and Real-time Timer (RTT)
Reset Controller (RSTC)
Based on a Power-on Reset Cell, Reset Source Identification and Reset Output Control
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SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
Clock Generator (CKGR)
Selectable 32768 Hz Low-power Oscillator or Internal Low Power RC Oscillator on Battery Backup Power
Supply, Providing a Permanent Slow Clock
3 to 20 MHz On-chip Oscillator, One Up to 240 MHz PLL and One Up to 100 MHz PLL
Power Management Controller (PMC)
Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities
Two Programmable External Clock Signals
Advanced Interrupt Controller (AIC)
Individually Maskable, Eight-level Priority, Vectored Interrupt Sources
Three External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected
Debug Unit (DBGU)
2-wire UART and support for Debug Communication Channel, Programmable ICE Access Prevention
Mode for General Purpose Two-wire UART Serial Communication
Periodic Interval Timer (PIT)
20-bit Interval Timer Plus 12-bit Interval Counter
Watchdog Timer (WDT)
Key-protected, Programmable Only Once, Windowed 16-bit Counter Running at Slow Clock
Real-time Timer (RTT)
32-bit Free-running Backup Counter Running at Slow Clock with 16-bit Prescaler
One 4-channel 10-bit Analog-to-Digital Converter
Three 32-bit Parallel Input/Output Controllers (PIOA, PIOB, PI OC)
96 Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os
Input Change Interrupt Capability on Each I/O Line
Individually Programmable Open-drain, Pull-up Resistor and Synchronous Output
Peripheral DMA Controller (PDC) Channels
Two-slot Multimedia Card Interface (MCI)
SDCard/SDIO and MultiMediaCard™ Compliant
Automatic Protocol Control and Fast Automatic Data Transfers with PDC
One Synchronous Serial Controllers (SSC)
Independent Clock and Frame Sync Signals for Each Receiver and Transmitter
I²S Analog Interface Support, Time Division Multiplex Support
High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer
Four Universal Synchronous/Asynchronous Receiver Transmitters (USART)
Individual Baud Rate Generator, IrDA® Infrared Modulation/Demodulation, Manchester Encoding/Decoding
Support for ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support
Full Modem Signal Control on USART0
One 2-wire UART
Two Master/Slave Serial Peripheral Interface (SPI)
8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects
Synchronous Communications
Two 3-channel 16-bit Timer/Counters (TC)
Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel
Double PWM Generation, Capture/Waveform Mode, Up/Down Capability
High-Drive Capability on Outputs TIOA0, TIOA1, TIOA2
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
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2 Two-wire Interfaces (TWI)
Master, Multi-master and Slave Mode Operation
General Call Supported in Slave Mode
Connection to PDC Channel to Optimize Data Transfers in Master Mode Only
IEEE® 1149.1 JTAG Boundary Scan on All Digital Pins
Required Power Supplies:
1.65V to 1.95V for VDDBU, VDDCORE and VDDPLL
1.65V to 3.6V for VDDIOP1 (Peripheral I/Os)
3.0V to 3.6V for VDDIOP0 and VDDANA (Analog-to-Digital Converter)
Programmable 1.65V to 1.95V or 3.0V to 3.6V for VDDIOM (Memory I/Os)
Available in 208-pin PQFP and 217-ball LFBGA Green-compliant Packages
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SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
1. Block Diagram
Figure 1-1, “SAM9XE Series Block Diagram,” on page 6 shows all the features for the 217-LFBGA package.
Some functions are not accessible in the 208-PQFP package and the unavailable pins are highlighted in
“Multiplexing on PIO Contro ller A” on page 40, “Multiplexing on PIO Controller B” on page 41 , “Multiplexing on PIO
Controller C” on page 42. The USB Host Port B is also not available.
Table 1-1 defines all the multiplexed and not multiplexed pins not available in the 208-PQFP package.
Table 1-1. Unavailable Signals in 208-pin PQFP Device
PIO Peripheral A Peripheral B
– HDPB –
– HDMB –
PA30 SCK2 RXD4
PA31 SCK0 TXD4
PB12 TWD1 ISI_D10
PB13 TWCK1 ISI_D11
PC2 AD2 PCK1
PC3 AD3 SPI1_NPCS3
PC12 IRQ0 NCS7
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
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Figure 1-1. SAM9XE Series Block Diagram
ARM926EJ-S Processor
JTAG Selection and Boundary Scan
In-Circuit Emulator
AIC
ROM
32 Kbytes
D0-D15
A0/NBS0
A2-A15, A18-A20
A16/BA0
A17/BA1
NCS0
NCS1/SDCS
NRD
NWR0/NWE
NWR1/NBS1
NWR3/NBS3
SDCK, SDCKE
RAS, CAS
SDWE, SDA10
FIQ
IRQ0-IRQ2
PLLRCA
DRXD
DTXD MMU
APB
Flash
128, 256
or 512
Kbytes
Peripheral
Bridge 24-channel
Peripheral
DMA
PLLA Bus Interface
A1/NBS2/NWR2
TST
PCK0-PCK1
System Controller
XIN
TDI
TDO
TMS
TCK
JTAGSEL
ID
NANDOE, NANDWE
PMC
PLLB
3–20 MHz
Main Osc.
XOUT PITWDT
DBGU
SLAVEMASTER
PDC
A23-A24
NCS5/CFCS1
A25/CFRNW
NCS4/CFCS0
NWAIT
CFCE1-CFCE2
EBI
Static
Memory
Controller
CompactFlash
NAND Flash
SDRAM
Controller
NCS2, NCS6, NCS7
NCS3/NANDCS
RTCK
ECC
Controller
ETXCK-ERXCK
ETXEN-ETXER
ECRS-ECOL
ERXER-ERXDV
ERX0-ERX3
ETX0-ETX3
MDC
MDIO
F100
10/100 Ethernet
MAC
FIFO
DMA
FIFO
SSC
PDC
USB
Device
DDM
DDP
TK
TF
TD
RD
RF
RK
TC0
TC1
TC2
TCLK0-TCLK2
TIOA0-TIOA2
TIOB0-TIOB2
SPI0
SPI1
PDC
USART0
USART1
USART2
USART3
USART4
RTS0-RTS3
SCK0-SCK3
TXD0-TXD5
RXD0-RXD5
CTS0-CTS3
PDC
TWI0
TWI1
TWCK
TWD
MCI
PDC
Transceiver
DPRAM
ICache
16 Kbytes DCache
8 Kbytes
6-layer Matrix
NPCS2
NPCS1
SPCK
MOSI
MISO
NPCS0
NPCS3
SPI0_, SPI1_
MCCK
MCDA0-MCDA3
MCCDA
NRST
XIN32
XOUT32
VDDCORE
PIOA
PIOB
PIOC
DSR0
DCD0
DTR0
RI0
USB
OHCI
DMA
Transc.
Transc.
HDPA
HDMA
HDPB
HDMB
Image
Sensor
Interface
DMA
ISI_PCK
ISI_DO-ISI_D7
ISI_HSYNC
ISI_VSYNC
ISI_MCK
4-channel
10-bit ADC
AD0-AD3
ADTRIG
ADVREF
VDDANA
GNDANA
PDC
D16-D31
RTT
32 kHz
XTAL Osc.
RSTC
POR
128-bit
GPBR
SHDN
WKUP SHDWC
POR
RC
Oscillator
OSCSEL
VDDBU
MCDB0-MCDB3
MCCDB
TC3
TC4
TC5
TCLK3-TCLK5
TIOA3-TIOA5
TIOB3-TIOB5
Fast SRAM
16 or 32
Kbytes
Filter
A21/NANDALE
A22/NANDCLE
NTRST
ERASE
PDC
BOD
Backup Section
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SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
2. Signal Description
Table 2-1 gives details on the signal name classified by peripheral.
Table 2-1. Signal Description List
Signal Name Function Type Active
Level Reference
Voltage Comments
Power Supplies
VDDIOM EBI I/O Lines Power Supply Power 1.65V to 1.95V or 3.0V to 3.6V
VDDIOP0 Peripherals I/O Lines Power Supply Power 3.0V to 3.6V
VDDIOP1 Peripherals I/O Lines Power Supply Power 1.65V to 3.6V
VDDBU Backup I/O Lines Power Supply Power 1.65V to 1.95V
VDDANA Analog Power Supply Power 3.0V to 3.6V
VDDPLL PLL Power Supply Power 1.65V to 1.95V
VDDCORE Core Chip and Embedded Memories
Power Supply Power 1.65V to 1.95V
GND Ground Ground
GNDPLL PLL Ground Ground
GNDANA Analog Ground Ground
GNDBU Backup Ground Ground
Clocks, Os cillators an d PLL s
XIN Main Oscillator Input Input
XOUT Main Oscillator Output Output
XIN32 Slow Clock Oscillator Input Input
XOUT32 Slow Clock Oscillator Output Output
OSCSEL Slow Clock Oscillator Selection Input VDDBU Accepts between 0V and VDDBU
PLLRCA PLL A Filter Input
PCK0–PCK1 Programmable Clock Output Output (2)
Shutdown, Wakeup Logic
SHDN Shutdown Control Output Low VDDBU Driven at 0V only
WKUP Wa ke-up Input Input VDDBU Accepts between 0V and VDDBU
ICE and JTAG
NTRST Test Reset Signal Input Low VDDIOP0 Pull-up resistor (100 kΩ)
TCK Test Clock Input VDDIOP0 No pull-up resistor, Schmitt trigger
TDI Test Data In Input VDDIOP0 No pull-up resistor , Schmitt trigger
TDO Test Data Out Output VDDIOP0
TMS Test Mode Select Input VDDIOP0 No pull -up resist or, Schmitt tr igger
JTAGSEL JTAG Selection Input VDDBU Pull-down res istor (15 kΩ)
RTCK Return Test Clock Output VDDIOP0
Flash Memory
ERASE Flash and NVM Configuration Bits
Erase Command Input High VDDIOP0 Pull-down resistor (15 kΩ)
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
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Reset/Test
NRST Microcontroller Reset I/O Low VDDIOP0 Open-drain output, Pull-up
resistor (100 kΩ)
Inserted in the Boundary Scan
TST Test Mode Select Input VDDBU Pull-down resistor (15 kΩ)
Debug Unit - DBGU
DRXD Debug Receive Data Inpu t (2)
DTXD Debug Transmit Data Output (2)
Advanced Interrupt Controller - AIC
IRQ0–IRQ2 External Interrupt Inputs Input (2)
FIQ Fast Interrupt Input Input (2)
PIO Controller - PIOA / PIOB / PIOC
PA0–PA31 Parallel IO Controller A I/O VDDIOP0 Pulled-up inpu t at reset
(100 kΩ)(1)
PB0–PB31 Parallel IO Controller B I/O VDDIOP0 Pulled-up input at reset
(100 kΩ)(1)
PC0–PC31 Parallel IO Controller C I/O (2) Pulled-up input at reset
(100 kΩ)(1)
External Bus Interface - EBI
D0–D31 Data Bus I/O VDDIOM Pulled-up input at reset
A0–A25 Address Bus Output VDDIOM 0 at reset
NWAIT External Wait Signal Input Low VDDIOM
Static Memory Controller - SMC
NCS0–NCS7 Chip Select Lines Output Low VDDIOM
NWR0–NWR3 Write Signal Output Low VDDIOM
NRD Read Signal Output Low VDDIOM
NWE Write Enable Output Low VDDIOM
NBS0–NBS3 Byte Mask Signal Output Low VDDIOM
CompactFlash Support
CFCE1–CFCE2 CompactFlash Chip Enable Output Low VDDIOM
CFOE CompactFlash Output Enable Output Low VDDIOM
CFWE CompactFlash Write Enable Output Low VDDIOM
CFIOR CompactFlash IO Read Output Low VDDIOM
CFIOW CompactFlash IO Write Output Low VDDIOM
CFRNW CompactFlash Read Not Write Output VDDIOM
CFCS0–CFCS1 CompactFlash Chip Select Lines Output Low VDDIOM
NAND Flash Support
NANDCS NAND Flash Chip Select Output Low VDDIOM
NANDOE NAND Flash Output Enable Output Low VDDIOM
NANDWE NAND Flash Write Enable Output Low VDDIOM
Table 2-1. Signal Description List (Continued)
Signal Name Function Type Active
Level Reference
Voltage Comments
9
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
SDRAM Controller - SDRAMC
SDCK SDRAM Clock Output VDDIOM
SDCKE SDRAM Clock Enable Output High VDDIOM
SDCS SDRAM Controller Chip Select Output Low VDDIOM
BA0–BA1 Bank Select Output VDDIOM
SDWE SDRAM Write Enable Output Low VDDIOM
RAS - CAS Row and Column Signal Output Low VDDIOM
SDA10 SDRAM Address 10 Line Output VDDIOM
Multimedia Card Interface - MCI
MCCK Multimedia Card Clock Output VDDIOP0
MCCDA Multimedia Card Slot A Command I/O VDDIOP0
MCDA0–MCDA3 Multimedia Card Slot A Data I/O VDDIOP0
MCCDB Multimedia Card Slot B Command I/O VDDIOP0
MCDB0–MCDB3 Multimedia Card Slot B Data I/O VDDIOP0
Universal Synchronous Asynchronous Receiv er Transmitter - USARTx
SCKx USARTx Serial Clock I/O (2)
TXDx USARTx Transmit Data I/O (2)
RXDx USARTx Receive Data Input (2)
RTSx USARTx Request To Send Output (2)
CTSx USARTx Clear To Send Input (2)
DTR0 USART0 Data Terminal Ready Output (2)
DSR0 USART0 Data Set Ready Input (2)
DCD0 USART0 Data Carrier Detect Input (2)
RI0 USART0 Ring Indicator Input (2)
Synchronous Serial Controller - SSC
TD SSC Transmit Data Output (2)
RD SSC Receive Data Input (2)
TK SSC Transmit Clock I/O (2)
RK SSC Receive Clock I/O (2)
TF SSC Transmit Frame Sync I/O (2)
RF SSC Receive Frame Sync I/O (2)
Timer/Counter - TCx
TCLKx TC Channel x External Clock Input Input (2)
TIOAx TC Channel x I/O Line A I/O (2)
TIOBx TC Channel x I/O Line B I/O (2)
Serial Peripheral Interface - SPIx
SPIx_MISO Master In Slave Out I/O (2)
SPIx_MOSI Mast er Out Slave In I/O (2)
SPIx_SPCK SPI Serial Clock I/O (2)
SPIx_NPCS0 SPI Peripheral Chip Select 0 I/O Low (2)
SPIx_NPCS1–SPIx_NPCS3 SPI Peripheral Chip Select Output Low (2)
Table 2-1. Signal Description List (Continued)
Signal Name Function Type Active
Level Reference
Voltage Comments
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
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Two-wire Interface - TWI
TWDx Two-wire Serial Data I/O (2)
TWCKx Two-wire Serial Clock I/O (2)
USB Host Port - UHP
HDPA USB Host Port A Data + Analog VDDIOP0
HDMA USB Host Port A Data - Analog VDDIOP0
HDPB USB Host Port B Data + Analog VDDIOP0
HDMB USB Host Port B Data + Analog VDDIOP0
USB Device Port - UDP
DDM USB Device Port Data - Analog VDDIOP0
DDP USB Device Port Data + Analog VDDIOP0
Ethernet MAC 10/100 - EMAC
ETXCK Transmit Clock or Reference Clock Input VDDIOP0 MII only, REFCK in RMII
ERXCK Receive Clock Input VDDIOP0 MII only
ETXEN Transmit Enable Output VDDIOP0
ETX0–ETX3 Transmit Data Output VDDIOP0 ETX0–ETX1 only in RMII
ETXER Transmit Coding Error Output VDDIOP0 MII only
ERXDV Receive Data Valid Input VDDIOP0 RXDV in MII, CRSDV in RMII
ERX0–ERX3 Receive Data Input VDDIOP0 ERX0–ERX1 only in RMII
ERXER Receive Error Input VDDIOP0
ECRS Carrier Sense and Data Valid Input VDDIOP0 MII only
ECOL Collision Detect Input VDDIOP0 MII only
EMDC Management Data Clock Output VDDIOP0
EMDIO M anagement Data Input/Output I/O VDDIOP0
EF100 Force 100Mbit/sec. Output High VDDIOP0
Image Sensor Interface - ISI
ISI_D0–ISI_D11 Image Sensor Data Input VDDIOP1
ISI_MCK Image sensor Reference clock output VDDIOP1
ISI_HSYNC Image Sensor Horizontal Synchro input VDDIOP1
ISI_VSYNC Image Sensor Vertical Synchro input VDDIOP1
ISI_PCK Image Sensor Data clock input VDDIOP1
Analog-to-Digital Converter - ADC
AD0–AD3 Analog Inputs Analog VDDANA Digital pulled-up inputs at reset
ADVREF Analog Positive Reference Analog VDDANA
ADTRG ADC T rigger Input VDDANA
Table 2-1. Signal Description List (Continued)
Signal Name Function Type Active
Level Reference
Voltage Comments
11
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
Notes: 1. Programming of this pull-up resistor is performed independently for each I/O line through the PIO Controllers. After reset, all
the I/O lines default as inputs with pull-up resistors enabled, exce pt those which are multiplexed with the External Bus
Interface signals that require to be enab led as Peripheral at reset. This is explicitly indicated in the column “Reset State” of
the peripheral multiplexing tables.
2. Refer to PIO Multiplexing (see Section 9.3 “Peripheral Signals Multiplexing on I/O Lines”).
Fast Flash Programming Interface - FFPI
PGMEN[3:0] Programming Enabling Input VDDIOP0
PGMNCMD Programming Command Input Low VDDIOP0
PGMRDY Programming Ready Output High VDDIOP0
PGMNOE Programming Read Input Low VDDIOP0
PGMNVALID Data Direction Output Low VDDIOP0
PGMM[3:0] Programming Mode Input VDDIOP0
PGMD[15:0] Programming Data I/O VDDIOP0
Table 2-1. Signal Description List (Continued)
Signal Name Function Type Active
Level Reference
Voltage Comments
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
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3. Package and Pinout
The SAM9XE devices are available in the following Green-compliant packages:
208-pin PQFP (0.5 mm pitch)
217-ball LFBGA (0.8 mm ball pitch)
3.1 208-pin PQFP Package Outline
Figure 3-1 shows the orientation of the 208-pin PQFP package.
A detailed mechanical description is given in Section 43. “Mec ha nic al Ch ar ac ter i stic s”.
Figure 3-1. 208-pin PQFP Package Outlin e (Top View)
3.2 208-pin PQFP Package Pinout
152
53
104
105156
157
208
Table 3-1. Pinout for 208-pin PQFP Package
Pin Signal Name Pin Signal Name Pin Signal Name Pin Signal Name
1 PA24 53 GND 105 RAS 157 ADVREF
2 PA25 54 DDM 106 D0 158 PC0
3 PA26 55 DDP 107 D1 159 PC1
4 PA27 56 PC13 108 D2 160 VDDANA
5 VDDIOP0 57 PC11 109 D3 161 PB10
6 GND 58 PC10 110 D4 162 PB11
7 PA28 59 PC14 111 D5 163 PB20
8 PA29 60 PC9 112 D6 164 PB21
9 PB0 61 PC8 113 GND 165 PB22
10 PB1 62 PC4 114 VDDIOM 166 PB23
11 PB2 63 PC6 115 SDCK 167 PB24
12 PB3 64 PC7 116 SDWE 168 PB25
13 VDDIOP0 65 VDDIOM 117 SDCKE 169 VDDIOP1
14 GND 66 GND 118 D7 170 GND
15 PB4 67 PC5 119 D8 171 PB26
16 PB5 68 NCS0 120 D9 172 PB27
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SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
17 PB6 69 CFOE/NRD 121 D10 173 GND
18 PB7 70 CFWE/NWE/NWR0 122 D11 174 VDDCORE
19 PB8 71 NANDOE 123 D12 175 PB28
20 PB9 72 NANDWE 124 D13 176 PB29
21 PB14 73 A22 125 D14 177 PB30
22 PB15 74 A21 126 D15 178 PB31
23 PB16 75 A20 127 PC15 179 PA0
24 VDDIOP0 76 A19 128 PC16 180 PA1
25 GND 77 VDDCORE 129 PC17 181 PA2
26 PB17 78 GND 130 PC18 182 PA3
27 PB18 79 A18 131 PC19 183 PA4
28 PB19 80 BA1/A17 132 VDDIOM 184 PA5
29 TDO 81 BA0/A16 133 GND 185 PA6
30 TDI 82 A15 134 PC20 186 PA7
31 TMS 83 A14 135 PC21 187 VDDIOP0
32 VDDIOP0 84 A13 136 PC22 188 GND
33 GND 85 A12 137 PC23 189 PA8
34 TCK 86 A11 138 PC24 190 PA9
35 NTRST 87 A10 139 PC25 191 PA10
36 NRST 88 A9 140 PC26 192 PA11
37 RTCK 89 A8 141 PC27 193 PA12
38 VDDCORE 90 VDDIOM 142 PC28 194 PA13
39 GND 91 GND 143 PC29 195 PA14
40 ERASE 92 A7 144 PC30 196 PA15
41 OSCSEL 93 A6 145 PC31 197 PA16
42 TST 94 A5 146 GND 198 PA17
43 JTAGSEL 95 A4 147 VDDCORE 199 VDDIOP0
44 GNDBU 96 A3 148 VDDPLL 200 GND
45 XOUT32 97 A2 149 XIN 201 PA18
46 XIN32 98 NWR2/NBS2/A1 150 XOUT 202 PA19
47 VDDBU 99 NBS0/A0 151 GNDPLL 203 VDDCORE
48 WKUP 100 SDA10 152 NC 204 GND
49 SHDN 101 CFIOW/NBS3/NWR3 153 GNDPLL 205 PA20
50 HDMA 102 CFIOR/NBS1/NWR1 154 PLLRCA 206 PA21
51 HDPA 103 SDCS/NCS1 155 VDDPLL 207 PA22
52 VDDIOP0 104 CAS 156 GNDANA 208 PA23
Table 3-1. Pinout for 208-pin PQFP Package (Continued)
Pin Signal Name Pin Signal Name Pin Signal Name Pin Signal Name
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
14
3.3 217-ball LFBGA Package Outline
Figure 3-2 shows the orientation of the 217-ball LFBGA package.
A detailed mechanical description is given in Section 43. “Mec ha nic al Ch ar ac ter i stic s”.
Figure 3-2. 217-ball LFBGA Package Outline (Top View)
3.4 217-ball LFBGA Package Pinout
12
1
2
3
4
5
6
7
8
9
10
11
13
14
15
16
17
ABCDEFGHJKLMNPRTU
Ball A1
Table 3-2. Pinout for 217-ball LFBGA Package
Pin Signal Name Pin Signal Name Pin Signal Name Pin Signal Name
A1 CFIOW/NBS3/NWR3 D5 A5 J14 TDO P17 PB5
A2 NBS0/A0 D6 GND J15 PB19 R1 NC
A3 NWR2/NBS2/A1 D7 A10 J16 TDI R2 GNDANA
A4 A6 D8 GND J17 PB16 R3 PC29
A5 A8 D9 VDDCORE K1 PC24 R4 VDDANA
A6 A11 D10 GND K2 PC20 R5 PB12
A7 A13 D11 VDDIOM K3 D15 R6 PB23
A8 BA0/A16 D12 GND K4 PC21 R7 GND
A9 A18 D13 DDM K8 GND R8 PB26
A10 A21 D14 HDPB K9 GND R9 PB28
A11 A22 D15 NC K10 GND R10 PA0
A12 CFWE/NWE/NWR0 D16 VDDBU K14 PB4 R11 PA4
A13 CFOE/NRD D17 XIN32 K15 PB17 R12 PA5
A14 NCS0 E1 D10 K16 GND R13 PA10
A15 PC5 E2 D5 K17 PB15 R14 PA21
A16 PC6 E3 D3 L1 GND R15 PA23
A17 PC4 E4 D4 L2 PC26 R16 PA24
B1 SDCK E14 HDPA L3 PC25 R17 PA29
B2 CFIOR/NBS1/NWR1 E15 HDMA L4 VDDIOP0 T1 PLLRCA
B3 SDCS/NCS1 E16 GNDBU L14 PA28 T2 GNDPLL
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B4 SDA10 E17 XOUT32 L15 PB9 T3 PC0
B5 A3 F1 D13 L16 PB8 T4 PC1
B6 A7 F2 SDWE L17 PB14 T5 PB10
B7 A12 F3 D6 M1 VDDCORE T6 PB22
B8 A15 F4 GND M2 PC31 T7 GND
B9 A20 F14 OSCSEL M3 GND T8 PB29
B10 NANDWE F15 ERASE M4 PC22 T9 PA2
B11 PC7 F16 JTAGSEL M14 PB1 T10 PA6
B12 PC10 F17 TST M15 PB2 T11 PA8
B13 PC13 G1 PC15 M16 PB3 T12 PA11
B14 PC11 G2 D7 M17 PB7 T13 VDDCORE
B15 PC14 G3 SDCKE N1 XIN T14 PA20
B16 PC8 G4 VDDIOM N2 VDDPLL T15 GND
B17 WKUP G14 GND N3 PC23 T16 PA22
C1 D8 G15 NRST N4 PC27 T17 PA27
C2 D1 G16 RTCK N14 PA31 U1 GNDPLL
C3 CAS G17 TMS N15 PA30 U2 ADVREF
C4 A2 H1 PC18 N16 PB0 U3 PC2
C5 A4 H2 D14 N17 PB6 U4 PC3
C6 A9 H3 D12 P1 XOUT U5 PB20
C7 A14 H4 D11 P2 VDDPLL U6 PB21
C8 BA1/A17 H8 GND P3 PC30 U7 PB25
C9 A19 H9 GND P4 PC28 U8 PB27
C10 NANDOE H10 GND P5 PB11 U9 PA12
C11 PC9 H14 VDDCORE P6 PB13 U10 PA13
C12 PC12 H15 TCK P7 PB24 U11 PA14
C13 DDP H16 NTRST P8 VDDIOP1 U12 PA15
C14 HDMB H17 PB18 P9 PB30 U13 PA19
C15 NC J1 PC19 P10 PB31 U14 PA17
C16 VDDIOP0 J2 PC17 P11 PA1 U15 PA16
C17 SHDN J3 VDDIOM P12 PA3 U16 PA18
D1 D9 J4 PC16 P13 PA7 U17 VDDIOP0
D2 D2 J8 GND P14 PA9
D3 RAS J9 GND P15 PA26
D4 D0 J10 GND P16 PA25
Table 3-2. Pinout for 217-ball LF BGA Package (Continued)
Pin Signal Name Pin Signal Name Pin Signal Name Pin Signal Name
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16
4. Power Considerations
4.1 Power Supplies
The SAM9XE devices have several types of power supply pins. Some supply pins share common ground (GND)
pins whereas others have separate grounds. See Table 4-1.
Note: 1. Desired voltage range selectable by software
The power supplies VDDIOM, VDDIOP0 and VDDIOP1 are identified in the pinout table and their associated I/O
lines in the multiplexing tables. These supplies enable the user to power the device differently for interfacing with
memories and for interfacing with peripherals.
4.2 Power Sequence Requirements
The board design must comply with the power-up guidelines below to guarantee reliable operation of the device.
Any deviation from these sequences may prevent the device from booting.
4.2.1 Power-up Sequence
VDDCORE and VDDBU are controlled by internal POR (Power-On-Reset) to guarantee that these power sources
reach their target values prior to the release of POR.
To ensure a working system, VDDIOP0, VDDIOP1, and VDDIOM should be established to power external
memories and I/Os before the first access. This can be achieved if VDDIOP0, VDDIOP1, and VDDIOM are
powered before VDDCORE.
4.2.2 Power-down Sequence
To ensure external memories and I/Os are powered until the last access, switch off VDDIOM, VDDIOP0 and
VDDIOP1 power supplies after or at the same time as switching off VDDCORE.
No power-up or power-down restrictions apply to VDDBU, VDDPLL and VDDANA.
Table 4-1. SAM9XE Power Supply Pins
Pin(s) Item(s) powere d Range Typical Ground
VDDCORE Core, including th e processor
Embedded memories
Peripherals 1.65–1.95 V 1.8V
GND
VDDIOM External Bus Interface I/O lines 1.65–1.95 V(1) 1.8V
3.0–3.6 V(1) 3.3V
VDDIOP0 Peripheral I/O lines and the USB transceivers 3.0–3.6 V 3.3V
VDDIOP1 Peripherals I/O lines involving the Image Sensor Interface 1.65–3.6 V 1.8V
2.5V
3.3V
VDDBU Slow Clock oscillator
Part of the System Controller 1.65–1.95 V 1.8V GNDBU
VDDPLL PLL cells main oscillator 1.65–1.95 V 1.8V GNDPLL
VDDANA Analog-to-Digital Converter 3.0–3.6 V 3.3V GNDANA
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5. I/O Line Considerations
5.1 ERASE Pin
The ERASE pin is used to re-initialize the Flash content and the NVM bits. It integrates a permanent pull-down
resistor of about 15 kΩ, so that it can be left unconnected for normal operations. The ERASE pin is powered by
VDDIOP0 rail.
This pin is debounced on the RC oscillator or 32768 Hz low-power oscillator to improve the glitch tolera nce.
Minimum debouncing time is 200 ms.
5.2 I/O Line Drive Levels
The PIO lines PA0 to PA31 and PB0 to PB31 and PC0 to PC 3 are high-drive current capable. Each of these I/O
lines can drive up to 16 mA permanently with a total of 350 mA on all I/O lines.
Refer to Section 42.2 “DC Characteristics”.
5.3 Shutdown Logic Pins
The SHDN pin is a tri-state output only pin, which is drive n by the Shutdown Contro ller. There is no inter nal pull-up.
An external pull-up to VDDBU is needed and its value must be higher than 1 MΩ. The resistor value is calculated
according to the regulator enable implementation and the SHDN level.
The WKUP pin is an input-only. It can accept voltages only between 0V and VDDBU.
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18
6. Processor and Architecture
6.1 ARM926EJ-S Processor
RISC Processor Based on ARM v5TEJ Architecture with Jazelle technology for Java acceleration
Two Instruction Sets
ARM High-performance 32-bit Instruction Set
Thumb High Code Density 16-bit Instruction Set
DSP Instruction Extensio ns
5-Stage Pipeline Architecture:
Instruction Fetch (F)
Instruction Decode (D)
Execute (E)
Data Memory (M)
Register Write (W)
8 KB Data Cache, 16 KB Instruction Cache
Virtually-addressed 4-way Associative Cache
Eight words per line
Write-through and Write-back Operation
Pseudo-random or Round-robin Replacement
Write Buffer
Main Write Buffer with 16-word Data Buffer and 4-address Buffer
DCache Write-back Buffer with 8-word Entries and a Single Address Entry
Software Control Drain
Standard ARM v4 and v5 Memory Management Unit (MMU)
Access Permission for Sections
Access Permission for large pages and small pages can be specified separately for each quarter of
the page
16 embedded domains
Bus Interface Unit (BIU)
Arbitrates and Schedules AHB Requests
Separate Masters for both instruction and data access providing complete Matrix system flexibility
Separate Address and Dat a Buses for both the 32-bi t instru ction interface and the 32-b it dat a interface
On Address and D ata Buses, data can be 8-bit (Byt es), 16-bit (Half- wo rds) or 32- b it (Words)
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6.2 Bus Matrix
6-layer Matrix, handling requests from 6 masters
Programmable Arbitration strategy
Fixed-priority Arbitration
Round-Robin Arbitration, either with no default master, last accessed default master or fixed default
master
Burst Management
Breaking with Slot Cycle Limit Support
Undefined Burst Length Support
One Address De co de r provided per Mast er
Three different slaves may be assigned to each decoded memory area: one for internal ROM boot,
one for internal flash boot, one after remap
Boot Mode Select
Non-volatile Boot Memo ry ca n be inte rn al RO M or inte rnal Fla s h
Selection is made by General purpose NVM bit sampled at reset
Remap Command
Allows Remapping of an Internal SRAM in Place of the Boot Non-Volatile Memory (ROM or Flash)
Allows Handling of Dynamic Exception Vectors
6.2.1 Matrix Masters
The Bus Matrix manages six Masters, thus each master can perform an access concurrently with others,
depending on whether the slave it accesses is available.
Each Master has its own deco der, which can be defined specifically for each m aster. In order to simplify the
addressing, all the masters have the same decodings.
6.2.2 Matrix Slaves
Each Slave has its own ar bit er , thu s allo win g a diff er en t ar bit ra tio n pe r Slav e to be pro gra mm e d.
Table 6-1. List of Bus Matrix Masters
Master 0 ARM926™ Instruction
Master 1 ARM926 Data
Master 2 Peripheral DMA Controller
Master 3 USB Host Controller
Master 4 Image Sensor Controller
Master 5 Ethernet MAC
Table 6-2. List of Bus Matrix Slaves
Slave 0 Internal SRAM
Slave 1 Internal ROM
USB Host User Interface
Slave 2 External Bus Interface
Slave 3 Internal Flash
Slave 4 Internal Perip herals
Slave 5 Reserved
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6.2.3 Masters to Slaves Access
All the Masters can normally access all the Slaves. However, some paths do not make sense, such as allowing
access from the Ethernet MAC to the internal peripherals.
Thus, these paths are forbidden or simply not wired, and shown as “–” in the following table.
Table 6-3. Masters to Slaves Access
Master 0 and 1 2 3 4 5
Slave
ARM926
Instruction and
Data
Peripheral DMA
Controller ISI Controller Ethernet MAC USB Host
Controller
0 Internal SRAM X XXXX
1Internal ROM XX–––
UHP User Interface X ––––
2 External Bus In terface X XXXX
3 Internal Flash X––X–
4 Internal Peri pherals XX–––
– Reserved – ––––
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6.3 Peripheral DMA Controller
Acting as one Matrix Master
Allows data transfers from/to peripheral to/from any memory space without an y intervention of the processor.
Next Pointer Support, forbids strong real-time constraints on buffer management.
Twenty-four channels
Two for each USART
Two for the Debu g Un it
Two for each Serial Synchronous Controller
Two for each Serial Peripheral Interface
Two for the Two Wire Interface
One for Multimedia Card Interface
One for Analog-to-Digital Converter
The Peripheral DMA Controller handles transfer requests from the channel according to the following priorities
(Low to High priorities):
TWI0 Transmit Channel
TWI1 Transmit Channel
DBGU Transmit Channel
USART4 Transm it Chan ne l
USART3 Transm it Chan ne l
USART2 Transm it Chan ne l
USART1 Transm it Chan ne l
USART0 Transm it Chan ne l
SPI1 Transmit Channe l
SPI0 Transmit Channe l
SSC Transmit Channel
TWI0 Receive Channel
TWI1 Receive Channel
DBGU Receive Channel
USART4 Receive Channel
USART3 Receive Channel
USART2 Receive Channel
USART1 Receive Channel
USART0 Receive Channel
ADC Receive Channel
SPI1 Receive Channe l
SPI0 Receive Channe l
SSC Receive Channel
MCI Transmit/Receive Channel
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6.4 Debug and Test Features
ARM926 Real-time In-circuit Emulator
Two real-time Watchpoint Units
Two Independent Registers: Debug Control Register and Debug Status Register
Test Access Port Accessible through JTAG Protocol
Debug Communications Channel
Debug Unit
Two-pin UART
Debug Communication Channel Interrupt Handling
Chip ID Register
IEEE1149.1 JTAG Boundary-scan on All Digital Pins
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7. Memories
Figure 7-1. Memory Mapping
16 Kbytes
16 Kbytes
0xFFFC 0000 16 Kbytes
0xFFFC 4000
SPI1
0xFFFC C000
SPI0
16 Kbytes
0xFFFC 8000
16 Kbytes
16 Kbytes
16 Kbytes
0xFFFA 4000 TCO, TC1, TC2
0xFFFA 8000
MCI
0xFFFB 0000
0xFFFB 4000 USART0
0xFFFB C000
USART1
0xFFFA 0000
0xFFFA C000
USART2
16 Kbytes
TWI0
16 Kbytes
16 Kbytes
0xFFFB 8000
16 Kbytes
16 Kbytes
UDP
SSC
256 Mbytes
0x1000 0000
0x0000 0000
0x0FFF FFFF
0xFFFF FFFF
0xF000 0000
0xEFFF FFFF
Address Memory Space
Internal Peripherals
Internal Memories
EBI
Chip Select 0
EBI
Chip Select 1/
SDRAMC
EBI
Chip Select 2
EBI
Chip Select 3/
NANDFlash
EBI
Chip Select 4/
Compact Flash
Slot 0
EBI
Chip Select 5/
Compact Flash
Slot 1
EBI
Chip Select 6
EBI
Chip Select 7
Undefined
(Abort)
256 Mbytes
256 Mbytes
256 Mbytes
256 Mbytes
256 Mbytes
256 Mbytes
256 Mbytes
1,518 Mbytes
0x2000 0000
0x1FFF FFFF
0x3000 0000
0x2FFF FFFF
0x4000 0000
0x3FFF FFFF
0x6FFF FFFF
0x6000 0000
0x5FFF FFFF
0x5000 0000
0x4FFF FFFF
0x7000 0000
0x7FFF FFFF
0x8000 0000
0x8FFF FFFF
0x9000 0000
256 Mbytes
0xFFFF FD00
0xFFFF FC00
0xFFFF FA00
0xFFFF F800
0xFFFF F600
0xFFFF F400
0xFFFF F200
16 bytes
256 bytes
512 bytes
512 bytes
512 bytes
512 bytes
PMC
PIOC
PIOB
PIOA
DBGU
RSTC
0xFFFF F000
512 bytes
AIC
0xFFFF EE00
512 bytes
MATRIX
0xFFFF EC00
512 bytesSMC
0xFFFF FD10 16 bytes
SHDWC
0xFFFF EA00
512 bytesSDRAMC
0xFFFF FD20 16 bytes
RTT
0xFFFF FD30 16 bytes
PIT
0xFFFF FD40 16 bytes
WDT
0xFFFF FD50
16 bytes
GPBR
0xFFFF FD60
0xFFFF FD70
EEFC
Reserved
256 Mbytes
Peripheral Mapping
Internal Memory Mapping (1) Can be ROM or Flash
depending on GPNVM[3]
Notes :
ISI
EMAC
0xFFFF C000
SYSC
0xFFFF FFFF
System Controller Mapping
16 Kbytes
0xFFFF FFFF
Reserved
0xFFFF C000
ADC
USART3
USART4
TWI1
TC3, TC4, TC5
16 Kbytes
16 Kbytes
16 Kbytes
16 Kbytes
16 Kbytes
0xFFFD 4000
0xFFFD 8000
0xFFFD 0000
0xFFFE 0000
0xFFFD C000
0xFFFE 4000
0xFFFF E800
ECC 512 bytes
32 Kbytes
128, 256 or 512 Kbytes
0x10 8000
ROM
0x20 0000
Flash
0x30 0000
0x30 8000
SRAM
0x50 4000
0x10 0000
0x28 0000
UHP
32 Kbytes
16 Kbytes
0x50 0000
Reserved
Reserved
Reserved
Reserved
0x0FFF FFFF
Boot Memory (1)
0x0000 0000
Reserved
0xF000 0000
512 bytes
Reserved
Reserved
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24
A first level of address decoding is performed by the Bus Matrix, i.e., the implementation of the Advanced High
performanc e Bus (AHB) for its Master an d Sl ave interfaces with additional features.
Decoding breaks up the 4 Gbytes of address space into 16 banks of 256 MB. Banks 1 to 7 are directed to the EBI
that associates these banks to the external chip selects EBI_NCS0 to EBI_NCS7. Bank 0 is reserved for the
addressing of the internal memor ies, an d a second l evel of deco ding pro vides 1 MB o f inter nal memor y ar ea. Bank
15 is reserved for the peripherals and provides access to the Advanced Peripheral Bus (APB).
Other areas are unu sed and pe rforming an access with in th em provides an abort to the maste r requ esting such an
access.
Each Master has its own bus and its own decoder, thus allowing a different memory mapping per Master.
However, in order to simplify the mappings, all the masters have a similar address decoding.
Regarding Master 0 and Master 1 (ARM926 Instruction and Data), three different Slaves are assigned to the
memory space decode d at address 0x0: one for internal boot, one for extern al boot, one after remap, refer to
Table 7-3, “Internal Memory Mapping,” on page 28 for details.
7.1 Embedded Memories
7.1.1 SAM9XE128
32 KB ROM
Single Cycle Access at full matrix speed
16 KB Fast SRAM
Single Cycle Access at full matrix speed
128 KB Embedded Flash
7.1.2 SAM9XE256
32 KB ROM
Single Cycle Access at full matrix speed
32 KB Fast SRAM
Single Cycle Access at full matrix speed
256 KB Embedded Flash
7.1.3 SAM9XE512
32 KB ROM
Single Cycle Access at full matrix speed
32 KB Fast SRAM
Single Cycle Access at full matrix speed
512 KB Embedded Flash
7.1.4 ROM Topology
The embedded ROM contains the Fast Flash Programming and the SAM-BA® boot programs. Each of these two
programs is stored on 16 KB Boundary of FFPI and the program executed at address zero depends on the
combination of the TST pin and PA0 to PA3 pins. Figure 7-2 shows the contents of the ROM and the program
available at address zero.
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Figure 7-2. ROM Boot Memory Map
7.1.4.1 Fast Flash Programming Interface
The Fast Flash Programming Interface programs the device through a serial JTAG interface or a multiplexed fully-
handshaked parallel port. It allows gang-programming with market-standard industrial programmers.
The FFPI suppo rts read, page progr am , pa ge era se , fu ll er as e, lock, unlo ck an d pr ot ec t com m an d s.
The Fast Flash Programming Interface is enabled and the Fast Programming Mode is entered when the TST pin
and the PA0 and PA1 pins are all tied high, while PA2 and PA3 are tied low.
7.1.4.2 SAM-BA Boot Assistant
The SAM-BA Boo t Assistant is a default Bo ot Program that pro vides an easy way t o program in situ the on -chip
Flash memory.
The SAM-BA Boot Assistan t su ppor ts se ria l com m unica tio n thro ugh th e DBG U or thro ug h th e USB Dev ice Por t.
Communication through the DBGU supports a wide range of crysta ls from 3 to 20 MHz via software auto-
detection.
Communication through the USB Device Port is depends on crystal selected:
limited to an 18432 Hz crystal if the internal RC oscillator is selected
supports a wide range of crystals from 3 to 20 MHz if the 32768 Hz crystal is selected
The SAM-BA Boot provides an interface with SAM-BA Graphic User Interface (GUI).
0x0000 0000
0x0000 3FFF
FFPI
Program
TST=1
PA0=1
PA1=1
PA2=0
PA3=0
0x0000 0000
0x0000 3FFF
SAM-BA
Program
TST=0
0x0000 0000
0x0000 7FFF
SAM-BA
Program
FFPI
Program
ROM
Table 7-1. Signal Description
Signal Name PIO Type Active Level Comment s
PGMEN0 PA0 Input High Must be connected to VDDIO
PGMEN1 PA1 Input High Must be connected to VDDIO
PGMEN2 PA2 Input Low Must be connected to GND
PGMEN3 PA3 Input Low Must be connected to GND
PGMNCMD PA4 Input Low Pulled-up input at reset
PGMRDY PA 5 Output Hi gh Pulled-up input at reset
PGMNOE PA6 Input Low Pulled-up input at reset
PGMNVALID PA7 Output Low Pulled-up input at reset
PGMM[3:0] PA8 ..PA10 Input Pulled-up input at reset
PGMD[15:0] PA12..PA27 Input/Output Pulled-up input at reset
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7.1.5 Embedded Flash
The Flash is organized in 256/512/1024 pages of 512 bytes directly connected to the 32-bit internal bus. Each
page contains 128 words.
The Flash contains a 512-byte write buffer allowing the programming of a page. This buffer is write-only as 128 32-
bit words, and accessible all along the 1 MB address space, so that each word can be written at its final address.
The Flash benefits from the integration of a power reset cell and from a brownout detector to prevent code
corruption during power supply changes, even in the worst conditions.
7.1.5.1 Enhanced Embedded Flash Controller
The Enhanced Embedded Flash Controller (EEFC) is continuously clocked.
The Enhanced Embedded Flash Controller (EEFC) is a slave for the bus matrix and is configurable through its
User Interface on the APB bus. It ensures the interface of the Flash block with the 32-b it internal bus. Its 128-bit
wide memory interface increase s performance, four 32-bit data are read durin g each access, this multiply the
throughput by 4 in case of consecutive data.
It also manages the programming, erasing, locking and unlocking sequences of the Flash using a full set of
commands. One of the comma nd s retur ns the embedd ed Flash d escriptor d efinition th at informs th e syste m about
the Flash organization, thus making the software generic programming of the access parameters of the Flash
(number of wait sta te s , timi ng s, et c.)
7.1.5.2 Lock Regions
The memory p lane of 128, 25 6 or 512 KB is organize d in 8, 16 or 32 locked regions of 32 pages each. Each lock
region can be locked independently, so that the software protects the first memory plane against erroneous
programming:
If a locked-regions erase or program command occurs, the command is aborted and the EEFC could trigger an
interrupt.
The Lock bits are software programmable through the EEFC User Interface. The command “Set Lock Bit” enables
the protection. The command “Clear Lock Bit” unlocks the lock region.
Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash.
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Figure 7-3. Flash First Memory Plane Mapping
7.1.5.3 GPNVM Bits
The SAM9XE devices feature four GPNVM bits that can be cleared or set respectively through the commands
“Clear GPNVM Bit” and “Set GPNVM Bit” of the EEFC User Interface.
7.1.5.4 Security Bit
The SAM9XE devices feature a secu rity bit, based on a specific GPNVM bit, GPNVMBit[0]. When the security is
enabled, access to the Flash, either through the ICE interface or through the Fast Flash Programmin g Interface, is
forbidden. This ensures the confidentiality of the code programmed in the Flash.
Disabling the security bit can only be achieved by asserting the ERASE pin at 1, and after a full Flash erase is
performed. When the security bit is deactivated, all accesses to the Flash are permitted.
As the ERASE pin integrates a permanent pull-down, it can be left unconnected during normal operation.
0x0020 0000
0x0021 FFFF
or 0x0023 FFFF
or 0x0027 FFFF
Page 0Locked Region 0
512 bytes
16 Kbytes
Locked Region 7, 15 or 31
Page 31
Locked Regions Area
128, 256 or 512 Kbytes
256, 512 or
1024 Pages
32 bits wide
Table 7-2. General-purpose Non-volatile Memory Bits
GPNVMBit[#] Function
0 Security Bit
1 Brownout Detector Enable
2 Brownout Detector Reset Enable
3 Boot Mode Select (BMS)
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28
7.1.5.5 Non-volatile Brownout Detector Control
Two GPNVM bits are used for controlling the brownout detector (BOD), so that even after a power loss, the
brownout detector operations remain in their state.
GPNVMBit[1] is used as a brownout detector enable bit. Setting GPNVMBit[1] enables the BOD, clearing it
disables the BOD. Asserting ERASE clears GPNVMBit[1] and thus disables the brownout detector by
default.
GPNVMBit[2] is used as a brownout reset enable signal for the reset controller. Setting GPNVMBit[2]
enables the brownout reset when a brownout is detected, clearing GPNVMBit[2] disables the bro wnout
reset. Asserting ERASE disables the brownout reset by default.
7.1.6 Boot Strategies
Table 7-3 summarizes the Internal Me mory Mapping for each Master, depending on the Remap status and the
GPNVMBit[3] state at reset.
The system always boots at address 0x0. To ensure a maximum number of possibilities for boot, the memory
layout can be configured with two parameters.
REMAP allows the user to lay out the first internal SRAM bank to 0x0 to ease development. This is done by
software once the system has booted. Refer to Section 20. “SAM9XE Bus Matrix” for more details.
When REMAP = 0, a non-volatile bit stored in Fla sh memory (GPNVMBit[3]) allows the user to lay out to 0x0, at his
convenience, th e ROM or the Flash. Re fer to Section 19. “E nhanced Embedd ed Flash Controller (EEFC)” for mor e
details.
Note: Memory blocks not affected by these parameters can always be seen at their specified base addresses. See the
complete memory map presented in Figure 7-1 on page 23.
The SAM9XE Matrix manages a boot memory that depends on the value of GPNVMBit[3] at reset. The internal
memory area mapped between address 0x0 and 0x0FFF FFFF is reserved for this purpose.
If GPNVMBit[3] is set, the boot memory is the internal Flash memory
If GPNVMBit[3] is clear (Flash reset State), the boot memory is the embedded ROM. After a Flash erase, the boot
memory is the internal ROM.
7.1.6.1 GPNVMBit[3] = 0, Boot on Embedded ROM
The system boots using the Boot Program.
Boot on slow clock (On-chip RC oscillator or 32768 Hz low-power oscillator)
Auto baud rate detection
SAM-BA Boot in case no valid program is detected in external NVM, supporting
Serial communication on a DBGU
USB Device Port
7.1.6.2 GPNVMBit[3] = 1, Boot on Internal Flash
Boot on slow clock (On-chip RC oscillator or 32768 Hz low-power oscillator)
The custome r -p rogr am m e d sof twa re mu st pe rf or m a comp le te conf igu ratio n .
Table 7-3. Internal Memory Mapping
Address
REMAP = 0
REMAP = 1GPNVMBit[3] clear GPNVMBit[3] set
0x0000 0000 ROM Flash SRAM
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SAM9XE Series [DATASHEET]
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To speed up the boot sequence when booting at 32 kHz, the user must take the following steps:
1. Program the PMC (main oscillator enable or bypass mode)
2. Program and start the PLL
3. Switch the main clock to the new value.
7.2 External Memories
The external memories are accessed through the External Bus Interface. Each Chip Select line has a 256 MB
memory area assigned.
Refer to the memory map in Figure 7-1 on page 23.
7.2.1 External Bus Interface
Integrates three External Memory Controllers:
Static Memory Controller
SDRAM Controller
ECC Controller
Additional logic for NAND Flash
Full 32-bit External Data Bus
Up to 26-bit Address Bus (up to 64 MB linear)
Up to 8 chip selects, Configurable Assignment:
Static Memory Controller on NCS0
SDRAM Controller or Static Memory Controller on NCS1
Static Memory Controller on NCS2
Static Memory Controller on NCS3, Optional NAND Flash support
Static Memory Controller on NCS4–NCS5, Optional CompactFlash support
Static Memory Controller on NCS6–NCS7
7.2.2 Sta tic Memory Controller
8-, 16- or 32-bit Data Bus
Multiple Access Modes supported
Byte Write or Byte Select Lines
Asynchronous read in Page Mode supported (4- up to 32-byte page size)
Multiple device adaptability
Compliant with LCD Module
Control signals programmable setup, pulse and hold time for each Memory Bank
Multiple Wait State Management
Programmable Wait State Generation
External Wait Request
Programmable Data Float Time
Slow Clock mode supported
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30
7.2.3 SDRAM Controller
Supported devices:
Standard and Low Power SDRAM (Mobile SDRAM)
Numerous configurations supported
2K, 4K, 8K Row Address Memory Parts
SDRAM with two or four Internal Banks
SDRAM with 16- or 32-bit Datapath
Programming facilities
Word, half-word, byte access
Automatic page break when Memory Boundary has been reached
Multibank Ping-pong Access
Timing parameters specified by software
Automatic refresh operation, refresh rate is programmable
Energy-saving capabilities
Self-refresh, power down and deep power down modes supported
Error detection
Refresh Error Interrupt
SDRAM Power-up Initialization by software
CAS Latency of 1, 2 and 3 supported
Auto Precharge Command not used
7.2.4 Error Correction Code Controller
Hardware error correction code generation
Detection and correction by software
Supports NAND Flash and SmartMedia devices with 8- or 16-bit datapath
Supports NAND Flash and SmartMedia with page sizes of 528,1056, 2112 and 4224 bytes specified by
software
Supports 1 bit correction for a page of 512, 1024, 2112 and 4096 bytes with 8- or 16-bit datapath
Supports 1 bit correction per 512 bytes of data for a page size of 512, 2048 and 4096 bytes with 8-bit
datapath
Supports 1 bit correction per 256 bytes of data for a page size of 512, 2048 and 4096 bytes with 8-bit
datapath
7.2.5 I/O Drive Selection
The purpose of this control is to adapt the signal to the frequency. Two bits enable the user to select High or Low
Drive for memory data/addresses/control signals.
Setting the EBI_DRIVE field [17:16] in the EBI Chip Select Assignment Register (EBI_CSA) located in the Chip
Configuration User Interface of the Bus Matrix, enables control of the EBI.
31
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8. System Controller
The System Controller is a set of peripherals that allows handling of key elements of the system, such as power,
resets, clocks, time, interrupts, watchd og , et c.
The System Controller User Interface also embeds the registers that configure the Matrix and a set of registers for
the chip configuration. The chip configuration r egisters configure the EBI chi p select assignmen t and voltage range
for external memories.
The System Controller’s peripherals are all mapped within the highest 16 KB of address space, between
addresses 0xFFFF E800 and 0xFFFF FFFF.
However, all the registers of System Controlle r are mapped on the top of the address space. All the registers of the
System Controller can be addre ssed from a single pointer by using the standard ARM instruction set, as the
Load/Store instruction have an indexing mode of ±4 KB.
Figure 8-1 on page 32 shows the System Controller block diagram.
Figure 7-1 on page 23 shows the mapping of the User Interfaces of the System Controller peripherals.
SAM9XE Series [DATASHEET]
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32
8.1 System Controller Block Diagram
Figure 8-1. System Controller Block Diagram
BOD
NRST
SLCK
Advanced
Interrupt
Controller
Real-time
Timer
Periodic
Interval
Timer
Reset
Controller
PA0-PA31
periph_nreset
System Controller
Watchdog
Timer
wdt_fault
WDRPROC
PIO
Controllers
Power
Management
Controller
XIN
XOUT
PLLRCA
MAINCK
PLLACK
pit_irq
MCK
proc_nreset
wdt_irq
periph_irq[2..4]
periph_nreset
periph_clk[2..27]
PCK
MCK
pmc_irq
nirq
nfiq
rtt_irq
Embedded
Peripherals
periph_clk[2..4]
pck[0-1]
in
out
enable
ARM926EJ-S
SLCK
SLCK
irq0-irq2
fiq
irq0-irq2
fiq
periph_irq[6..24]
periph_irq[2..24]
int
int
periph_nreset
periph_clk[6..24]
jtag_nreset
por_ntrst
proc_nreset
periph_nreset
dbgu_txd
dbgu_rxd
pit_irq
dbgu_irq
pmc_irq
rstc_irq
wdt_irq
rstc_irq
SLCK
Boundary Scan
TAP Controller
jtag_nreset
debug
PCK
debug
idle
debug
Bus Matrix
MCK
periph_nreset
proc_nreset
backup_nreset
periph_nreset
idle
Debug
Unit dbgu_irq
MCK
dbgu_rxd
periph_nreset dbgu_txd
rtt_alarm
Shutdown
Controller
SLCK
rtt0_alarm
backup_nreset
SHDN
WKUP
128-bit General-Purpose
Backup Registers
backup_nreset
XIN32
XOUT32
PLLBCK
PB0-PB31
PC0-PC31
VDDBU Powered
VDDCORE Powered
ntrst
POR
Main
Oscillator
PLLA
VDDBU
POR
Slow Clock
Osicllator
PLLB
por_ntrst
VDDBU
rtt_irq
UDPCK
USB
Device
Port
UDPCK
periph_nreset
periph_clk[10]
periph_irq[10]
USB Host
Port
periph_nreset
periph_clk[20]
periph_irq[20]
UHPCK
UHPCK
RC
Oscillator
OSCSEL
VDDCORE
flash_wrdis
flash_poe
gpnvm[1]
cal gpnvm[2]
bod_rst_en
Embedded
Flash
flash_poe
gpnvm[1..3]
flash_wrdis
security_bit(gpnvm0)
cal
gpnvm[3]
VDDCORE
efc2_irq
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SAM9XE Series [DATASHEET]
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8.2 Reset Controller
Based on two Power-on reset cells
One on VDDBU and one on VDDCORE
Status of the last reset
Either general reset (VDDBU rising), wake-up reset (VDDCORE rising), software reset, user reset or
watchdog reset
Controls the internal resets and the NRST pin output
Allows shaping a reset signal for the external devices
At reset the NRST pin is an output
8.3 Brownout Detector and Power-on Reset
The SAM9XE devices embed one brownout detection circuit and pow er-on reset cells. The power-on reset are
supplied with and monitor VDDCORE and VDDBU.
Signals (flash_poe and flash_wrdis) are provided to the Flash to prevent any code corruption during power-up or
power-down sequences or if brownouts occur on the VDDCORE power supply.
The power-on reset cell has a limited-accuracy threshold at around 1.5V. Its output remains low during power-up
until VDDCORE goes over this voltage level. This signal goes to the reset controller and allows a full re-
initialization of the device.
The brownout detector monitors the VDDCORE leve l during operation by comparing it to a fixed trigger level. It
secures system operations in the most difficult environments and prevents code corruption in case of brownout on
the VDDCORE.
When the brownout detector is enabled and VDDCORE decreases to a value below the trigger level (VBOT-), the
brownout outp ut is imme dia te ly act i vate d. For more details on V BOT, see Table 42-3, “Brownout Detector
Characteristics”.
When VDDCORE increases above the trigger level (VBOT+, defined as VBOT + Vhys), the reset is released. The
brownout detector only detects a drop if the voltage on VDDCORE stays below the threshold vo ltage for longer
than about 1 µs.
The VDDCORE threshold voltage has a hysteresis of about 50 mV typical, to ensure spike free brownout
detection. The typical value of the brownout detector threshold is 1.55V with an accuracy of ± 2% and is factory
calibrated.
The brownout detector is low-power, as it consumes less than 12 µA static current. Howeve r, it can be deactivate d
to save its static current. In this case, it consumes less than 1 µA. The deactivation is configured through the
GPNVMBit[1] of the Flash.
Additional information can be found in Section 42. “Electrical Characteristics”.
8.4 Shutdown Controller
Shutdown and Wake-up logic
Software programm ab le assertion of the SHD N pin
Deassertion Programmable on a WKUP pin level change or on alarm
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34
8.5 Clock Generator
Embeds a low power 32768 Hz slow clock oscillator and a low-power RC oscillator selectable with OSCSEL
signal
Provides the permanent slow clock SLCK to the system
Embeds the main oscillator
Oscillator bypass feature
Supports 3 to 20 MHz crystals
Embeds 2 PLLs
PLL A outputs 80 to 240 MHz clock
PLL B outputs 70 MHz to 130 MHz clock
Both integrate an inpu t div i de r to incre as e ou tp ut accura cy
PLLB embeds its own filter
8.6 Power Management Controller
Provides:
the Processor Clock PCK
the Master Clock MCK, in particular to the Matrix and the memory interfaces
the USB Device Clock UDPCK
independent peripheral clocks, typically at the frequency of MCK
2 programmable clock outputs: PCK0, PCK1
Five flexible operating modes:
Normal Mode, processor and peripherals running at a programmable frequency
Idle Mode, processor stopped waiting for an interrupt
Slow Clock Mode, processor and peripherals running at low frequency
Standby Mode, mix of Idle a nd Backup Mod e, peripher al r unn ing at low fr eq uen cy, processor stopped
waiting for an interrupt
Backup Mode, Main Power Supplies off, VDDBU powered by a battery
8.7 Periodic Interval Timer
Includes a 20-bit Periodic Counter, with less than 1 µs accuracy
Includes a 12-bit Interval Overlay Counter
Real-time OS or Linux®/WindowsCE® compliant tick generator
8.8 Watchdog Timer
16-bit key-protected only-once-Programmable Counter
Windowed, prevents the processor to be in a dead-lock o n the watchdog access
8.9 Real-time Timer
Real-time Timer with 32-bit free-running back-up counter
Integrates a 16-bit programmable prescaler running on slow clock
Alarm Register capable to generate a wake-up of the system through the Shutdown Controller
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SAM9XE Series [DATASHEET]
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8.10 General-purpose Back-up Registers
Four 32-bit general-purpose backup registers
8.11 Advanced Interrupt Controller
Controls the int erru pt lines (n IRQ an d nFIQ ) of the ARM Proc essor
Thirty-two individually maskable and vectored interrupt sources
Source 0 is reserved for the Fast Interrup t Input (FIQ)
Source 1 is reserved for system peripherals (PIT, RTT, PMC, DBGU, etc.)
Programmable Edge-triggered or Level-sensitive Internal Sources
Programmable Positive/Negative Edge-triggered or High/Low Level-sensitive
Three External Sources plus the Fast Interrupt signal
8-level Priority Controller
Drives the Normal Interrupt of the processor
Handles priori ty of the int erru pt sou rce s 1 to 31
Higher priority interrupts can be served during service of lower priority interrupt
Vectoring
Optimizes Interrupt Service Routine Branch and Execution
One 32-bit Vector Register per interrupt source
Interrupt Vector Register reads the corresponding current Interrupt Vector
Protect Mode
Easy debugging by preventing automatic operations when protect modules are enabled
Fast Forcing
Permits redirecting any normal interrupt source on the Fast Interr upt of the processor
8.12 Debug Unit
Composed of two functions
Two-pin UART
Debug Communication Channel (DCC) support
Two-pin UART
Implemented features are 100% compatible with the standard Atmel USART
Independent receiver and transmitter with a common programmable Baud Rate Generator
Even, Odd, Mark or Space Parity Generation
Parity, Framing and Over ru n Err or Detect ion
Automatic Echo, Local Loopback and Remote Loopback Channel Modes
Support for two PDC channels with connection to receiver and transmitter
Debug Communication Channel Support
Offers visibility of and interrupt trigger from COMMRX and COMMTX signals from the ARM
Processor’s ICE Interface
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36
8.13 Chip Identification
Chip ID:
0x329AA3A0 for the SAM9XE512
0x329A93A0 for the SAM9XE256
0x329973A0 for the SAM9XE128
JTAG ID: 05B1_C03F
ARM926 TAP ID: 0x0792603F
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9. Peripherals
9.1 User Interface
The Peripheral s are m app ed in th e up per 25 6 MB of the a ddr ess sp ace betwe en the add resses 0xFF FA 000 0 an d
0xFFFC FFFF. Each User Peripheral is allocated 16 KB of address space. A complete memory map is presented
in Figure 7-1 on page 23.
9.2 Peripheral Identifier
The SAM9XE devices embed a wide range of peripherals. Table 9-1 defines the Peripheral Identifiers of the
SAM9XE devices. A peripheral identifier is required for the control of the peripheral interrupt with the Advanced
Interrupt Controller and for the control of the peripheral clock with the Power Management Controller.
Table 9-1. Peripheral Identifiers
Peripheral ID Peripheral Mnemonic Peripheral Name External Interrupt
0 AIC Advanced Interrupt Controller FIQ
1 SYSC System Controller Interrupt
2 P IOA Parallel I/O Controller A
3 P IOB Parallel I/O Controller B
4 P IOC Parallel I/O Controller C
5 ADC Analog-to-Digital Converter
6 US0 USART 0
7 US1 USART 1
8 US2 USART 2
9 MCI Multimedia Card Interface
10 UDP USB Device Port
11 TWI0 Two Wire Interface 0
12 SPI0 Serial Peripheral Interface 0
13 SPI1 Serial Peripheral Interface1
14 SSC Synchronous Serial Controller
15 – Reserved
16 – Reserved
17 TC0 Timer/Counter 0
18 TC1 Timer/Counter 1
19 TC2 Timer/Counter 2
20 UHP USB Host Port
21 EMAC Ethernet MAC
22 ISI Image Sensor Interface
23 US3 USART 3
24 US4 USART 4
25 TWI1 Two Wire Interface 1
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38
Note: Setting AIC, SYSC, UHP, ADC and IRQ0–2 bits in the clock set/clear registers of the PMC has no effect. The ADC
clock is automatically started for the first conversion. In Sleep Mode the ADC clock is automatically stopped after each
conversion.
9.2.1 Peripheral Interrupts and Clock Control
9.2.1.1 System Interrupt
The System Interrupt in Source 1 is the wired-OR of the interrupt signals coming from:
SDRAM Controller
Debug Unit
Periodic Interval Timer
Real-time Timer
Watchdog Timer
Reset Controller
Power Management Controller
Enhanced Embedded Flash Controller
The clock of these peripherals cannot be deactivated and Peripheral ID 1 can only be used within the Advanced
Interrupt Controller.
9.2.1.2 External Interrupts
All external interrupt signals, i.e., the Fast Interrupt signal FIQ or the Interrupt signals IRQ0 to IRQ2, use a
dedicated Peripheral ID. However, there is no clo ck control associated with these peripheral IDs.
26 TC3 Timer/Counter 3
27 TC4 Timer/Counter 4
28 TC5 Timer/Counter 5
29 AIC Advanced Interrupt Co nt roller IRQ 0
30 AIC Advanced Interrupt Co nt roller IRQ 1
31 AIC Advanced Interrupt Co nt roller IRQ 2
Table 9-1. Peripheral Identifiers (Continued)
Peripheral ID Peripheral Mnemonic Peripheral Name External Interrupt
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9.3 Peripheral Signals Multiplexing on I/O Lines
The SAM9XE devices feature three PIO controllers (PIOA, PIOB, PIOC) which multiplex the I/O lines of the
peripheral set.
Each PIO Controller controls up to 32 lines. Each line can be assigned to one of two peripheral functions, A or B.
The multiplexing tables in the following sections define how the I/O lines of peripherals A and B ar e multip lexed on
the PIO Controllers. The two co lumns “Function” and “Comm ents” have been inserted in this table for th e user’s
own comments; they may be used to track how pins are defined in an application.
Note that some peripheral functions which are output only, might be duplicated within both tables.
The column “Reset State” indicates whether the PI O Line resets in I/O mode or in peripheral mode. If I/O is
mentioned, the PIO Line resets in input with the pull-up enabled, so that the device is maintained in a static state
as soon as the reset is released. As a result, the bit corresponding to the PIO Line in the register PIO_PSR
(Periphera l Statu s Re gist er ) re se ts low.
If a signal name is mentioned in the “Reset State” column, the PIO Line is assigned to this function and the
corresponding bit in PIO_PSR resets high. This is the case of pins controlling memories, in particular the address
lines, which require the pin to be driven as soon as the reset is released. Note that the pull-up resistor is also
enabled in this case.
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40
9.3.1 PIO Controller A Multiplexing
Note: 1. Not available in the 208-lead PQFP package.
Table 9-2. Multiplexing on PIO Controller A
PIO Controller A Application Usage
I/O Line Peripheral A Peripheral B C omments Reset Sta t e Power Supply F unction Comments
PA0 SPI0_MISO MCDB0 I/O VDDIOP0
PA1 SPI0_MOSI MCCDB I/O VDDIOP0
PA2 SPI0_SPCK I/O VDDIOP0
PA3 SPI0_NPCS0 MCDB3 I/O VDDIOP0
PA4 RTS2 MCDB2 I/O VDDIOP0
PA5 CTS2 MCDB1 I/O VDDIOP0
PA6 MCDA0 I/O VDDIOP0
PA7 MCCDA I/O VDDIOP0
PA8 MCCK I/O VDDIOP0
PA9 MCDA1 I/O VDDIOP0
PA10 MCDA2 ETX2 I/O VDDIOP0
PA11 MCDA3 ETX3 I/O VDDIOP0
PA12 ETX0 I/O VDDIOP0
PA13 ETX1 I/O VDDIOP0
PA14 ERX0 I/O VDDIOP0
PA15 ERX1 I/O VDDIOP0
PA16 ETXEN I/O VDDIOP0
PA17 ERXDV I/O VDDIOP0
PA18 ERXER I/O VDDIOP0
PA19 ETXCK I/O VDDIOP0
PA20 EMDC I/O VDDIOP0
PA21 EMDIO I/O VDDIOP0
PA22 ADTRG ETXER I/O VDDIOP0
PA23 TWD0 ETX2 I/O VDDIOP0
PA24 TWCK0 ETX3 I/O VDDIOP0
PA25 TCLK0 ERX2 I/O VDDIOP0
PA26 TIOA0 ERX3 I/O VDDIOP0
PA27 TIOA1 ERXCK I/O VDDIOP0
PA28 TIOA2 ECRS I/O VDDIOP0
PA29 SCK1 ECOL I/O VDDIOP0
PA30(1) SCK2 RXD4 I/O VDDIOP0
PA31(1) SCK0 TXD4 I/O VDDIOP0
41
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Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
9.3.2 PIO Controller B Multiplexing
Note: 1. Not available in the 208-lead PQFP package.
Table 9-3. Multiplexing on PIO Controller B
PIO Controller B Application Usage
I/O Line Peripheral A Peripheral B Comments Reset State Power Supply Function Comments
PB0 SPI1_MISO TIOA3 I/O VDDIOP0
PB1 SPI1_MOSI TIOB3 I/O VDDIOP0
PB2 SPI1_SPCK TIOA4 I/O VDDIOP0
PB3 SPI1_NPCS0 TIOA5 I/O VDDIOP0
PB4 TXD0 I/O VDDIOP0
PB5 RXD0 I/O VDDIOP0
PB6 TXD1 TCLK1 I/O VDDIOP0
PB7 RXD1 TCLK2 I/O VDDIOP0
PB8 TXD2 I/O VDDIOP0
PB9 RXD2 I/O VDDIOP0
PB10 TXD3 ISI_D8 I/O VDDIOP1
PB11 RXD3 ISI_D9 I/O VDDIOP1
PB12(1) TWD1 ISI_D10 I/O VDDIOP1
PB13(1) TWCK1 ISI_D11 I/O VDDIOP1
PB14 DRXD I/O VDDIOP0
PB15 DTXD I/O VDDIOP0
PB16 TK TCLK3 I/O VDDIOP0
PB17 TF TCLK4 I/O VDDIOP0
PB18 TD TIOB4 I/O VDDIOP0
PB19 RD TIOB5 I/O VDDIOP0
PB20 RK ISI_D0 I/O VDDIOP1
PB21 RF ISI_D1 I/O VDDIOP1
PB22 DSR0 ISI_D2 I/O VDDIOP1
PB23 DCD0 ISI_D3 I/O VDDIOP1
PB24 DTR0 ISI_D4 I/O VDDIOP1
PB25 RI0 ISI_D5 I/O VDDIOP1
PB26 RTS0 ISI_D6 I/O VDDIOP1
PB27 CTS0 ISI_D7 I/O VDDIOP1
PB28 RTS1 ISI_PCK I/O VDDIOP1
PB29 CTS1 ISI_VSYNC I/O VDDIOP1
PB30 PCK0 ISI_HSYNC I/O VDDIOP1
PB31 PCK1 ISI_MCK I/O VDDIOP1
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
42
9.3.3 PIO Controller C Multiplexing
Note: 1. Not available in the 208-lead PQFP package.
Table 9-4. Multiplexing on PIO Controller C
PIO Controller C Application Usage
I/O Line Peripheral A Peripheral B Comments Reset State Power Supply Function Comments
PC0 SCK3 AD0 I/O VDDANA
PC1 PCK0 AD1 I/O VDDANA
PC2(1) PCK1 AD2 I/O VDDANA
PC3(1) SPI1_NPCS3 AD3 I/O VDDANA
PC4 A23 SPI1_NPCS2 A23 VDDIOM
PC5 A24 SPI1_NPCS1 A24 VDDIOM
PC6 TIOB2 CFCE1 I/O VDDIOM
PC7 TIOB1 CFCE2 I/O VDDIOM
PC8 NCS4/CFCS0 RTS3 I/O VDDIOM
PC9 NCS5/CFCS1 TIOB0 I/O VDDIOM
PC10 A25/CFRNW CTS3 A25 VDDIOM
PC11 NCS2 SPI0_NPCS1 I/O VDDIOM
PC12(1) IRQ0 NCS7 I/O VDDIOM
PC13 FIQ NCS6 I/O VDDIOM
PC14 NCS3/NANDCS IRQ2 I/O VDDIOM
PC15 NWAIT IRQ1 I/O VDDIOM
PC16 D16 SPI0_NPCS2 I/O VDDIOM
PC17 D17 SPI0_NPCS3 I/O VDDIOM
PC18 D18 SPI1_NPCS1 I/O VDDIOM
PC19 D19 SPI1_NPCS2 I/O VDDIOM
PC20 D20 SPI1_NPCS3 I/O VDDIOM
PC21 D21 EF100 I/O VDDIOM
PC22 D22 TCLK5 I/O VDDIOM
PC23 D23 I/O VDDIOM
PC24 D24 I/O VDDIOM
PC25 D25 I/O VDDIOM
PC26 D26 I/O VDDIOM
PC27 D27 I/O VDDIOM
PC28 D28 I/O VDDIOM
PC29 D29 I/O VDDIOM
PC30 D30 I/O VDDIOM
PC31 D31 I/O VDDIOM
43
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
9.4 Embedded Peripherals
9.4.1 Serial Peripheral Interface
Supports communication with serial external devices
Four chip selects with external decoder support allow communication with up to 15 peripherals
Serial memories, such as DataFlash and 3-wire EEPROMs
Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and Sensors
External co-p ro ce sso rs
Master or slave serial peripheral bus interface
8- to 16-bit programmable data length per chip select
Programmable phase and polarity per chip select
Programmable transfer delays between consecutive transfers and between clock and data pe r chip
select
Programmable delay between consecutive transfers
Selectable mode fault detection
Very fast transfers supported
Transfers with baud rates up to MCK
The chip select line may be left active to speed up transfers on the same device
9.4.2 Two-wire Interface
Master, Multi-master and Slave modes supported
General call supported in Slave mode
Connection to PDC Channel
9.4.3 USART
Programmable Baud Rate Generator
5- to 9-bit full-duplex synchronous or asynchronous serial communications
1, 1.5 or 2 stop bits in Asynchronous Mode or 1 or 2 stop bits in Synchronous Mode
Parity generation and error detection
Framing error detection, overrun error detection
MSB- or LSB-first
Optional break generation and detection
By 8 or by 16 oversampling receiver frequency
Hardware handshaking RTS-CTS
Receiver time-out and transmitter timeguard
Optional Multi-drop Mode with address generation and detection
Optional Manchester Encoding
RS485 with driver control signal
ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards
NACK handling, error counter with repetition and iteration limit
IrDA modulation and demodulation
Communication at up to 115.2 kbps
Test Modes
Remote Loopback, Local Loopback, Automatic Echo
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
44
9.4.4 Serial Synchronous Controller
Provides serial synchronous communication links used in audio and telecommunications applications (with
CODECs in Master or Slave Modes, I2S, TDM Buses, Magnetic Card Reader, etc.)
Contains an independent receiver and transmitter and a common clock divide r
Offers a configurable frame sync and data length
Receiver and transmitter can be programmed to start automatically or on detection of different event on the
frame sync signal
Receiver and transmitter include a data signal, a clock signal and a frame synchronization signal
9.4.5 Timer Counter
Six 16-bit Timer Counter Channels
Wide range of functions including:
Frequency Measurement
Event Counting
Interval Measurement
Pulse Generation
Delay Timing
Pulse Width Modulation
Up/down Capabilities
Each channel is user-configurable and contains:
Three exte rn al cloc k inp uts
Five internal clock inputs
Two multi-purpose input/output signals
Two global registers that act on all three TC Channels
9.4.6 Multimedia Card Interface
One double-channel Multimedia Card Interface
Compatibility with MultiMedia Card Spec ification Version 2.2
Compatibility with SD Memory Card Specification Version 1.0
Compatibility with SDIO Specification Version V1.0.
Cards clock rate up to Master Clock divided by 2
Embedded power management to slow down clock rate when not used
MCI has two slot, each supporting
One slot for one MultiMediaCard bus (up to 30 cards) or
One SD Memory Card
Support for stream, block and multi-block data read and write
9.4.7 USB Host Port
Compliance with Open HCI Rev 1.0 Specification
Compliance with USB V2.0 Full-speed and Low-speed Specification
Supports both Low-Speed 1.5 Mbps and Full-speed 12 Mbps devices
Root hub integrated with two downstream USB ports in the 217-LFBGA package
Two embedded USB transceivers
Supports power management
Operates as a master on the Matrix
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9.4.8 USB Device Port
USB V2.0 full-speed compliant, 12 Mbits per second
Embedded USB V2.0 full-speed transceiver
Embedded 2,688-byte dual-port RAM for endpoints
Suspend/Resume logic
Ping-pong mode (two memory banks) for isochronous and bulk endpoin ts
Eight general-purpose endpoints
Endpoint 0 and 3: 64 bytes, no ping-pong mode
Endpoint 1, 2, 6, 7: 64 bytes, ping-pong mode
Endpoint 4 and 5: 512 bytes, ping-pong mode
Embedded pad pull-up
9.4.9 Ethernet 10/100 MAC
Compatibility with IEEE Standard 802.3
10 and 100 Mbits per second data throughput capability
Full- and half-duplex operations
MII or RMII interface to the physical layer
Register Interface to address, data, status and control registers
DMA Interface, operating as a master on the Memory Controller
Interrupt generation to signal receive and transmit completion
128-byte transmit and 128-byte receive FIFOs
Automatic pad and CRC generation on transmitted frames
Address checking logic to recognize four 48-bit addresses
Supports promiscuous mode where all valid frames are copied to memory
Supports physical layer management through MDIO interface
9.4.10 Image Sensor Interface
ITU-R BT. 601/656 8-bit mode external interface support
Support for ITU-R BT.656-4 SAV and EAV synchronization
Vertical and horizontal resolutions up to 2048 x 2048
Preview Path up to 640*480
Support for packed data formatting for YCbCr 4:2:2 formats
Preview scaler to ge n er ate smaller size image
9.4.11 Analog-to-Digital Converter
4-channel ADC
10-bit 312K samples/sec. Successive Approximation Register ADC
-2/+2 LSB Integral Non Linearity, -1/+1 LSB Differential Non Linearity
Individual enable and disable of each channel
External voltage reference for better accuracy on low voltage inputs
Multiple trigger source – Hardware or software trigger – External trigger pin – Timer Counter 0 to 2 outpu ts
TIOA0 to TIOA2 trigger
Sleep Mode and conversion sequencer – Automatic wakeup on trigger and back to sleep mode after
conversions of all enabled channels
Four analog inputs shared with digital signals
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10. ARM926EJ-S Processor
10.1 Overview
The ARM926EJ-S processor is a member of the ARM9™ family of general-purpose microprocessors. The
ARM926EJ-S implements ARM architectu re version 5TEJ and is targeted at multi-tasking applications where full
memory management, high performance, low die size and low power are all impor tant features.
The ARM926EJ-S processor supports the 32 -bit ARM and 16-bit Thumb instruction sets, enabling the user to
trade off between high performance and high code density. It also supports 8-bit Java instruction set and includes
features for efficient execution of Java bytecode, providing a Java performance similar to a JIT (Just-In-Time
compilers), for the next generation of Java-powered wireless and embedded devices. It includes an enhanced
multiplier design for improved DSP performance.
The ARM926EJ-S processor supports the ARM debug architecture an d includes logic to assist in both hardware
and software debug.
The ARM926EJ-S provides a complete high performance processor subsystem, including:
an ARM9EJ-S integer core
a Memory Management Unit (MMU)
separate instruction and data AMBA AHB bus interfaces
separate instruction and data TCM interfaces
Table 10-1. Reference Document Table
Owner-Reference Denomination
ARM Ltd. - DD10198B ARM926EJS Technical Reference Manual
ARM Ltd. - DD10222B ARM9EJ-S Technical Reference Manual
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10.2 Block Diagram
Figure 10-1. ARM926 EJ-S Interna l Fu nctional Block Diagram
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10.3 ARM9EJ-S Processor
10.3.1 ARM9EJ-S Operating States
The ARM9EJ-S processor can operate in three different states, each with a specific instruction set:
ARM state: 32-bit, word-aligned ARM instructions.
Thumb state: 16-bit, halfword-aligned Thumb instructions.
Jazelle state: variable length, byte-aligned Jazelle instructions.
In Jazelle state, all instruction Fetches are in words.
10.3.2 Switching State
The operating state of the ARM9EJ-S core can be switched between:
ARM state and Thumb state using the BX and BLX instructions, and loads to the PC
ARM state and Jazelle state using the BXJ instruction
All exceptions are entere d, handled and exited in ARM state. If an exception occur s in Thumb or Jazelle states, the
processor reverts to ARM state. The transition back to Thumb or Jazelle states occurs automatically on return from
the exception handler.
10.3.3 Instruction Pipelines
The ARM9EJ-S core uses two kinds of pipe lines to incre ase the spe ed of the flow of instructions to the processor.
A five-stage (five clock cycles) pipeline is used for ARM and Thumb st ates. It consists of Fetch, Decode, Execute,
Memory and Writeback stages.
A six-stage (six clock cycles) pipelin e is used for Jazelle state It consists of Fetch, Ja zelle/Decode (two clock
cycles), Execute, Memory and Writeback stages.
10.3.4 Memory Access
The ARM9EJ-S core supports byte (8-bit), half-word (16-bit) and word (32-bit) access. Words must be aligned to
four-byte boundaries, half-words must be aligned to two-byte boundaries and bytes can be placed on any byte
boundary.
Because of th e nat ure of th e pip elines , it is poss ible fo r a value to be re quir ed for us e bef ore it h as be en plac ed in
the register bank by the actions of an earlier instruction. The ARM9EJ-S control logic automatically detects these
cases and stalls the core or forward data.
10.3.5 Jazelle Technology
The Jazelle technology enables direct and efficient execution of Java byte codes on ARM processors, providing
high performance for the next generation of Java-powered wireless and embedded devices.
The new Java feature of ARM9EJ-S can be described as a hardware emulation of a JVM (Java Virtual Machine).
Java mode will appear as another state: instead of executing ARM or Thumb instructions, it executes Java byte
codes. The Java byte code decoder logic implemented in ARM9EJ-S decodes 95% of executed byte codes and
turns them into ARM instructions without any overhead, while less frequently used byte codes are broken down
into optimized sequences of ARM instructions. The hardware/software split is invisible to the p rogrammer, invisib le
to the application and invisible to the operating system. All existing ARM registers are re-used in Jazelle state and
all registers then have particular functions in th is mode.
Minimum interrupt latency is main tained across both ARM state and Java state. Since byte codes execution can
be restarted, an in terrup t automatically triggers the core to switch from Java state to ARM state for the execution of
the interrupt handler. This means that no special provision has to be made for handling interrupts wh ile executing
byte codes, whether in hardware or in software.
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10.3.6 ARM9EJ-S Operating Modes
In all states, there are seven operation modes:
User mode is the usual ARM program execution state. It is used for executing most application programs
Fast Interrupt (FIQ) mode is used for handling fast interrupts. It is suitable for high-speed data transfer or
channel process
Interrupt (IRQ) mode is used for general-purpose interrupt handling
Supervisor mode is a protected mode for the operating system
Abort mode is enter ed after a data or instructio n pr ef et ch ab o rt
System mode is a privileged user mode for the operating system
Undefined mode is entered when an undefined instruction exception occurs
Mode cha nges may be made under so ftware co ntrol, or m ay be brought about by external interrupts or exception
processing. Most application programs execute in User Mode. The non-user modes, known as privileged modes,
are entered in order to service interrupts or exceptions or to access protected resources.
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10.3.7 ARM9EJ-S Registers
The ARM9EJ-S core has a to ta l of 37 regis te rs:
31 general-purpose 32-bit registers
Six 32-bit status registers
Table 10-2 shows all the registers in all modes.
The ARM stat e register set contains 16 directly-accessible registers, r0 to r15, and an additional register, the
Current Program Status Register (CPSR). Registers r0 to r13 are general-purpose registers used to hold either
data or address values. Register r14 is used as a Link register that holds a value (return address) of r15 when BL
or BLX is executed. Register r15 is used as a program counter (PC), whereas the Current Program Status
Register (CPSR) contains condition code flags and the current mode bits.
In privileged modes (FIQ, Supervisor, Abort, IRQ, Undefined) , mode-specific banked registers (r8 to r14 in FIQ
mode or r13 to r14 in the other modes) become available. The corresponding banked registers r14_fiq, r14_svc,
r14_abt, r14_irq, r14_ und are similarly used to hold th e values (return address for each mode) of r15 (PC) when
interrupts and exceptions arise , or when BL or BLX instructions are executed within interrupt or exception routines.
There is another register called Saved Program Status Register (SPSR) that becomes available in privileged
modes instead of CPSR. This register contains condition code flags and the current mode bits saved as a result of
the exception that caused entry to the current (privileged) mode.
Table 10-2. ARM9TDMI Modes and Registers Layout
User and
System Mode Supervisor
Mode Abort Mode Undefined Mode Interrupt Mode Fast Interrupt
Mode
R0 R0 R0 R0 R0 R0
R1 R1 R1 R1 R1 R1
R2 R2 R2 R2 R2 R2
R3 R3 R3 R3 R3 R3
R4 R4 R4 R4 R4 R4
R5 R5 R5 R5 R5 R5
R6 R6 R6 R6 R6 R6
R7 R7 R7 R7 R7 R7
R8 R8 R8 R8 R8 R8_FIQ
R9 R9 R9 R9 R9 R9_FIQ
R10 R10 R10 R10 R10 R10_FIQ
R11R11R11R11R11
R11_FIQ
R12 R12 R12 R12 R12 R12_FIQ
R13 R13_SVC R13_ABORT R13_UNDEF R13_IRQ R13_FIQ
R14 R14_SVC R14_ABORT R14_UNDEF R14_IRQ R14_FIQ
PC PC PC PC PC PC
CPSR CPSR CPSR CPSR CPSR CPSR
SPSR_SVC SPSR_ABORT SPSR_UNDEF SPSR_IRQ SPSR_FIQ
Mode-specific banked registers
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In all modes and due to a software agreement, register r13 is used as stack pointer.
The use and the function of all the registers described above should obey ARM Procedure Call Standard (APCS)
which defines:
constraints on the use of registers
stack conventions
argument passing and result return
For more details, refer to ARM Software Development Kit.
The Thumb state register set is a subse t of th e ARM stat e set . Th e prog r am m er has dire ct acc es s to:
Eight general-purpose registers r0–r7
Stack pointer, SP
Link register, LR (ARM r14)
PC
CPSR
There are banked registers SPs, LRs and SPSRs for each privileged mode (for more details see the ARM9EJ-S
Technical Reference Manual, revision r1p2 page 2-12).
10.3.7.1Status Registers
The ARM9EJ-S core contains one CPSR, and five SPSRs for exception handlers to use. The program status
registers:
hold informatio n ab ou t th e mo st recently performed ALU operation
control the enabling and disabling of interrupts
set the proc essor operat io n mode
Figure 10-2. Sta t us Register Format
Figure 10-2 shows the status register format, where:
N: Negative, Z: Zero, C: Carry, and V: Overflow are the four ALU flags
The Sticky Overflow (Q) flag can be set by certain multiply and fractional arithmetic instructions like QADD,
QDADD, QSUB, QDSUB, SMLAxy, and SMLAWy needed to achieve DSP operations.
The Q flag is sticky in that, when set by an instruction, it remains set until explicitly cleared by an MSR
instruction writing to the CPSR. Instructions cannot execute conditionally on the status of the Q flag.
The J bit in the CPSR indicates when the ARM9EJ-S core is in Jazelle state, where:
J = 0: The processor is in ARM or Thumb state, depending on the T bit
J = 1: The processor is in Jazelle state.
Mode: five bits to encode the current processor mode
NZCVQ JIFT
Mode
Reserved
Mode bits
Thumb state bit
FIQ disable
IRQ disable
Jazelle state bit
Reserved
Sticky Overflow
Overflow
Carry/Borrow/Extend
Zero
Negative/Less than
3130292827 24 7 6 5 0
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10.3.7.2Exceptions
10.3.7.3Exception Types and Priorities
The ARM9EJ-S supports five types of exceptions. Each type drives the ARM9EJ-S in a privileged mode. The types
of exceptions are:
Fast interrupt (FIQ)
Normal interrupt (IRQ)
Data and Prefetched aborts (Abort)
Undefined instruction (Undefined)
Software interrupt and Reset (Supervisor)
When an exception occurs, the banked version of R14 and the SPSR for the exception mode are used to save the
state.
More than one exception can happen at a time, therefore the ARM9EJ-S takes the arisen exceptions according to
the following priority order:
Reset (highest priority)
Data Abort
FIQ
IRQ
Prefetch Abort
BKPT, Undefined instruction, and Software Interrupt (SWI) (Lowest pr iority)
The BKPT, or Undefined instruction, and SWI exceptions are mutually exclusive.
Note that there is one exception in the priority scheme: when FIQs are ena bled and a Data Abort occurs at the
same time as an FIQ, the ARM9EJ-S core enters the Data Abort handle r, and proceeds immediately to FIQ vecto r.
A normal return from the FIQ causes the Data Abort handler to resume execution. Data Aborts must have higher
priority than FIQs to ensure that the transfer error does not escape detection.
10.3.7.4Exception Modes and Handling
Exceptions arise whenever the normal flow of a program must be halted temporarily, for example, to service an
interrupt from a peripheral.
When handling an ARM exception, the ARM9EJ-S core performs the followin g operations:
1. Preserves the address of the next instruction in the appropriate Link Register that corresponds to the new
mode that has been entered. When the exception entry is from:
ARM and Jazelle states, the ARM9EJ-S copies the address of the next instruction into LR (current
PC(r15) + 4 or PC + 8 depending on the exception).
Thumb state, the ARM9EJ-S writes the value of the PC into LR, offset by a value (current PC + 2,
PC + 4 or PC + 8 depending on the exception) that causes the program to resume from the correct
place on ret ur n.
2. Copies the CPSR into the appropriate SPSR.
3. Forces the CPSR mode bits to a value that depends on the exception.
4. Forces the PC to fetch the next instruction from the relevant exception vector.
The register r13 is also banked across exception modes to provide each exception handler with private stack
pointer.
The ARM9EJ-S can also set the interrupt disable flags to prevent otherwise unmanageable nesting of exceptions.
When an exception has completed, the exception handler must move both the return value in the banked LR
minus an offset to the PC and the SPSR to the CPSR. The offset value varies according to the type of exception.
This action restores both PC and the CPSR.
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The fast interrupt mode has seven private registers r8 to r14 (banked registers) to reduce or remove the
requirement for register saving which minimizes the overhead of context switching.
The Prefetch Abort is one of the aborts that indicates that the current memory access cannot be completed. When
a Prefetch Abort occurs, the ARM9EJ-S marks the prefetched instruction as invalid, but does not take the
exception un til the instruction reaches th e Execute stage in the pipeline. If the instruction is not executed, for
example because a branch occurs while it is in the pipeline, the abort does not take place.
The breakpoint (BKPT) instruction is a new feature of ARM9EJ-S that is destined to solve the problem of the
Prefetch Abort. A breakpoint instruction operates as though the instruction caused a Prefetch Abort.
A breakpoint instruction does not cause the ARM9EJ-S to take the Prefetch Abort exception until the instruction
reaches the Execute stage of the pipeline. If the instr uc tio n is no t exe cuted, for example because a branch occurs
while it is in the pipeline, the breakpoint does not take place.
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10.3.8 ARM Instruction Set Overview
The ARM instruction set is divided into:
Branch instructions
Data processing instructions
Status register transfer instructions
Load and Store instructions
Coprocessor instructions
Exception-generating instructions
ARM instructions can be executed conditionally. Every instruction contains a 4-bit co ndition code field (bits[31:28]).
For further details, see the ARM Technical Reference Manual referenced in Table 10-1 on page 46.
Table 10-3 gives the ARM instruction mnemonic list.
Table 10-3. ARM Instruction Mnemonic List
Mnemonic Operation Mnemonic Operation
MOV Move MVN Move Not
ADD Add ADC Add with Carry
SUB Subtract SBC Subtract with Carry
RSB Reverse Subtract RSC Reverse Subtract with Carry
CMP Compare CMN Compare Negated
TST Test TEQ Test Equivalence
AND Logical AND BIC Bit Clear
EOR Logical Exclusive OR ORR Logical (inclusive) OR
MUL Multiply MLA Multiply Accumulate
SMULL Sign Long Multiply UMULL Unsigned Long Multiply
SMLAL Signed Long Multiply Accumulate UMLAL Unsigned Long Multiply Accumulate
MSR Move to Status Register MRS Move From Status Register
B Branch BL Branch and Link
BX Branch and Exchange SWI Software Interrupt
LDR Load Word STR Store Word
LDRSH Load Signed Halfword
LDRSB Load Signed Byte
LDRH Load Half Word STRH Store Half Word
LDRB Load Byte STRB Store Byte
LDRBT Load Register Byte with Translation S TRBT Store Register Byte with Translation
LDRT Load Register with Translation STRT Store Register with Translation
LDM Load Multiple STM Store Multiple
SWP Swap Word SWPB Swap Byte
MCR Move To Coproce ssor MRC Move From Coprocessor
LDC Load To Coprocessor STC Store From Coprocessor
CDP Coprocessor Data Processing
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10.3.9 New ARM Instruction Set
Note: 1. A Thumb BLX contains two consecutive Thumb instructions, and takes four cycles.
Table 10-4. New ARM Instruction Mnemonic List
Mnemonic Operation Mnemonic Operation
BXJ Branch and exchange to Java MRRC Move double from coprocessor
BLX (1) Branch, Link and exchange MCR2 Alternative move of ARM reg to copr ocessor
SMLAxy Signed Multiply Accumulate 16 * 16 bit MCRR Move double to coprocessor
SMLAL Signed Multiply Accumulate Long CDP2 Alternative Coprocessor Data Processing
SMLAWy Signed Multiply Accumulate 32 * 16 bit BKPT Breakpoint
SMULxy Signed Multiply 16 * 16 bit PLD Soft Preload, Memory prepare to load from
address
SMULWy Signed Multiply 32 * 16 bit STRD Store Double
QADD Saturated Add STC2 Alternative Store from Coprocessor
QDADD Saturated Add with Double LDRD Load Double
QSUB Saturated subtract LDC2 Alternative Load to Coprocessor
QDSUB Saturated Subtract with double CLZ Count Leading Zeroes
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10.3.10 Thumb Instruction Set Overview
The Thumb instr u ctio n se t is a re-e n cod e d subse t of the ARM instr u ctio n se t.
The Thumb instruction set is divided into:
Branch instructions
Data processing instructions
Load and Store instructions
Load and Store multiple instructions
Exception-generating instruction
For further details, see the ARM Technical Reference Manual referenced in Table 10-1 on page 46.
Table 10-5 gives the Thumb instruction mnemonic list.
Table 10-5. Thumb Instruction Mnemonic List
Mnemonic Operation Mnemonic Operation
MOV Move MVN Move Not
ADD Add ADC Add with Carry
SUB Subtract SBC Subtract with Carry
CMP Compare CMN Compare Negated
TST Test NEG Negate
AND Logical AND BIC Bit Clear
EOR L ogical Exclusive OR ORR Logical (inclusive) OR
LSL Logical Shift Left LSR Logical Shift Right
ASR Arithmetic Shift Right ROR Rotate Right
MUL Multiply BLX Branch , Link, and Exchange
B Branch BL Branch and Link
BX Branch and Exchange SWI Software Interrupt
LDR Load Word STR Store Word
LDRH Load Half Word STRH Store Half Word
LDRB Load Byte STRB Store Byte
LDRSH Load Signed Hal fword LDRSB Load Signed Byte
LDMIA Load Multiple STMIA Store Multiple
PUSH Push Register to stack POP Pop Register from stack
BCC Conditional Branch BKPT Breakpoint
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10.4 CP15 Coprocessor
Coprocessor 15, or System Contro l Coprocessor CP15, is used to configure and control all the item s in the list
below:
ARM9EJ-S
Caches (ICache, DCache and write buffer)
TCM
MMU
Other system options
To control these features, CP15 provides 16 additional registers. See Table 10-6.
Notes: 1. Register locations 0,5, and 13 each provide access to more than one register . The register accessed depends on
the value of the opcode_2 field.
2. Register location 9 provides access to more than one register . The register accessed depends on the value of the
CRm field.
Table 10-6. CP15 Registers
Register Name Read/Write
0 ID Code(1) Read/Unpredictable
0 Cache type(1) Read/Unpredictable
0 TCM status(1) Read/Unpredictable
1 Control Read/write
2 Transl ation Table Base Read/write
3 Domain Access Control Read/write
4 Reserved None
5 Data fault Status(1) Read/write
5 Instruction fault status(1) Read/write
6 Fault Address Read/write
7 Cache Operations Read/Write
8 TLB operations Unpredictable/Write
9 cache lockdown(2) Read/write
9 TCM region Read/write
10 TLB lockdown Read/write
11 Reserved None
12 Reserved None
13 FCSE PID(1) Read/write
13 Context ID(1) Read/Write
14 Reserved None
15 Test configuration Read/Write
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10.4.1 CP1 5 Registers Access
CP15 registers can only be accessed in privileged mode by:
MCR (Move to Coprocessor from ARM Register) instruction is used to write an ARM register to CP15.
MRC (Move to ARM Register from Coprocessor) instruction is used to read the value of CP15 to an ARM
register.
Other instructions like CDP, LDC, STC can cause an undefined instruction exception.
The assemb ler code fo r these instructions is:
MCR/MRC{cond} p15, opcode_1, Rd, CRn, CRm, opcode_2.
The MCR, MRC instructions bit pattern is shown below:
• CRm[3:0]: Specified Coprocessor Action
Determines specific coprocessor action. Its value is dependent on the CP15 register used. For details, refer to CP15 spe-
cific register behavior.
• opcode_2[7:5]
Determines specific coprocessor operation code. By default, set to 0.
• Rd[15:12]: ARM Register
Defines the ARM register whose value is transferred to the coprocessor. If R15 is chosen, the result is unpredictable.
• CRn[19:16]: Coprocessor Register
Determines the destination coprocessor register.
• L: Instruct ion Bit
0: MCR instruction
1: MRC instruction
• opcode_1[23:20]: Coprocessor Code
Defines the coprocessor specific code. Value is c15 for CP15.
• cond [31:28]: Condition
For more details, see Chapter 2 in ARM926EJ-S TRM.
31 30 29 28 27 26 25 24
cond 1110
23 22 21 20 19 18 17 16
opcode_1 L CRn
15 14 13 12 11 10 9 8
Rd 1111
76543210
opcode_2 1 CRm
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10.5 Memory Management Unit (MMU)
The ARM926EJ-S pro cessor implements an enhanced ARM architecture v5 MMU to provide virtual memory
features required by op er ating systems like Symbian® OS, WindowsCE, and Linux. These virtual memory features
are memory access permission controls and virtual to physical address translations.
The Virtual Address generated by the CPU core is converted to a Modified Virtual Address (MVA) by the FCSE
(Fast Context Switch Extension) using the value in CP15 register13. The MMU translates modified virtual
addresses to physical addre sses by using a single, two-level page ta ble set stored in physica l memory. Each entry
in the set contains the access permissions and the physical address that correspond to the virtual address.
The first level translation tables contain 4096 entries indexed by bits [31:20] of the MVA. These entries contain a
pointer to either a 1 MB section of physical memory along with attribute information (access permissions, domain,
etc.) or an entry in the second level translation tables; coarse table and fine table.
The second level translation tables contain two subtables, coarse ta ble and fine table. An entry in the coarse table
contains a pointer to both large pages and small pages along with access permissions. An entry in the fine table
contains a pointer to large, small and tiny pages.
Table 10-7 shows the different attributes of each page in the physical memory.
The MMU consis ts of :
Access control logic
Translation Look-aside Buffer (TLB)
Translation table walk hardware
10.5.1 Access Control Logic
The access control logic controls access information for ev ery entry in the translation table. The access control
logic checks two pieces of access information: domain and access permissions. The domain is the primary access
control mechanism for a memory re gion ; there are 16 of them. It defines the conditions ne cessa ry fo r an acce ss to
proceed. The domain determines whether the access permissions are used to qualify the access or whethe r they
should be ignored.
The second access control mechanism is access permissions that are defined for sections and for large, small and
tiny pages. Sections and tiny pages have a single set of access permissions whereas large and small pages can
be associated with 4 sets of access permissions, one for each subpage (quarter of a page).
10.5.2 Translation Look-aside Buffer (TLB)
The Translatio n Look-aside Buffer (T LB) caches translated entrie s and thus avoids going through the translation
process every time. When the TLB contains an entry for the MVA (Modified Virtual Address), the access control
logic determines if the access is permitted and output s the appropriate physical address corresponding to the
MVA. If access is not permitted, the MMU signals the CPU core to abort.
If the TLB does not contain an entry for the MVA, the translation table wa lk hardware is invoked to retrieve the
translation information from the translation table in physical memory.
Table 10-7. Mapping Details
Mapping Name Mapping Size Access Permission By Subpage Size
Section 1 Mbyte Section –
Large Page 64 Kbytes 4 separated subpages 16 Kbytes
Small Page 4 Kbytes 4 separated subpages 1 Kbyte
Tiny Page 1 Kbyte Tiny Page –
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10.5.3 Translation Table Walk Hardware
The translation table walk hard ware is a logic that trav erses th e translat ion tables located in physical memory, ge ts
the physical address and access permissions and updates the TLB.
The number of stag es in the ha rdware table walkin g is one or two depending whether the address is marked as a
section-mapped access or a page-mapped access.
There are three size s of page-map ped accesses and o ne size of section- mapped access. Page-mappe d accesses
are for large pages, small pages and tiny pages. The translation process always begins with a level one fetch. A
section-mapped acce ss requires only a level o ne fetch, but a page-mapped access requires a n additional level two
fetch. For further details on the MMU, please refer to chapter 3 in ARM926EJ-S Technical Reference Manual.
10.5.4 MMU Faults
The MMU generates an abort on the following types of faults:
Alignment faults (for data accesses only)
Translation faults
Domain faults
Permission faults
The access control mechanism of the MMU detects the conditions that produce these faults. If the fault is a result
of memory access, the MMU aborts the access and signals the fault to the CPU core.The MMU retains status and
address information about faults generated by the data accesses in the data fault status register and fault address
register. It also retains the status of faults generated by instruction fetches in the instruction fault status register.
The fault status register (register 5 in CP15) indicates the cause of a data or prefetch abort, and the domain
number of the aborted access when it happens. The fault address register (register 6 in CP15) holds the MVA
associated with the acce ss tha t caused the Data Abo rt. For furt her details on MMU faults, pl ease re fer to chapter 3
in ARM926EJ-S Technical Reference Manual.
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10.6 Caches and Write Buffer
The ARM926EJ-S contains a 16-Kbyte Instruction Cache (ICache), a 8-Kbyte Data Cache (DCache), and a write
buffer. Although the ICache and DCache share common features, each still has some specific mechanisms.
The caches (ICache and DCache) are four-way set associative, addressed, indexed and tagged using the
Modified Virtual Address (MVA), with a cache line length of eight words with two dirty bits for the DCache. The
ICache and DCache provide mechanisms for cache lockdown, cache pollution control, and line replacement.
A new feature is now supported by ARM926EJ-S caches called allocate on read-miss commonly known as
wrapping. This feature enables the caches to perform critical word first cache refilling. Th is means that when a
request for a word causes a read-miss, the cache per forms an AHB access. Instead of loading the whole line
(eight words), the cache loads the critical word first, so the processor can reach it quickly, and then the remaining
words, no matter where the word is located in the line.
The caches and the write buffer are controlled by the CP15 register 1 (Control), CP15 register 7 (cache
operations) and CP15 register 9 (cache lockdown).
10.6.1 Instruction Cache (ICache)
The ICache caches fetched instructions to be executed by the processor. The ICache can be enabled by writing 1
to I bit of the CP15 Register 1 and disabled by writing 0 to this same bit.
When the MMU is enabled, all instruction fetches are subject to translation and permission checks. If the MMU is
disabled, all instructions fetches are cachable, no protection checks are made and the physical address is flat-
mapped to the modified virtual address. With the MVA use disabled, context switching incurs ICache cleaning
and/or invalidating.
When the ICache is disabled, all instruction fetches appear on external memory (AHB) (see Tables 4-1 and 4-2 in
page 4-4 in ARM926EJ-S TRM).
On reset, the ICache entries are invalidated and the ICache is disabled. For best pe rformance, IC ache should be
enabled as soon as possible after reset.
10.6.2 Data Cache (DCache) and Write Buffer
ARM926EJ-S includes a DCa che and a write buffer to reduc e the effect of ma in memory bandwidth an d latency on
data access performance. The operations of DCache and write buffer are closely connected.
10.6.2.1DCache
The DCache needs the MMU to be enabled. All data accesses are subject to MMU permission and translation
checks. Data accesses that are aborted by the MMU do not cause linefills or data accesses to appear on the
AMBA ASB interface. If the MMU is disabled, all data accesses are noncachable, nonbufferable, with no protection
checks, and appear on the AHB bus. All a ddresses are flat-mapped, VA = MVA = PA, wh ich incurs DCache
cleaning and/or invalidating every time a context switch occurs.
The DCache stores the Physica l Address Ta g (PA Ta g) fr om wh ich e very lin e was loade d a nd uses it whe n wr iting
modified lines back to external memory. This means that the MMU is not involved in write-back operations.
Each line (8 words) in the DCache has two dirty bits, one for the first four words and the other one for the second
four words. These bits, if set, mark the associated half-lines as dirty. If the cache line is replaced due to a linefill or
a cache clean operation, the dirty bits are used to decide whether all, half or none is written back to memory.
DCache can be enabled or disabled by writing either 1 or 0 to bit C in register 1 of CP15 (see Tables 4-3 and 4-4
on page 4-5 in ARM926EJ-S TRM).
The DCache supports write-through and write-back cache operations, selected by memory region using the C and
B bits in the MMU translation tables.
The DCache contains an eight data word entry, single address entry write-back buffer used to hold write-back data
for cache line eviction or cleaning of dirty cache lines.
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The Write Buffer can hold up to 16 words of data and four separate addresses. DCache and Write Buffer
operations are closely conne cted as their configuration is set in each section by the page descriptor in the MMU
translation table.
10.6.2.2Write Buffer
The ARM926EJ-S contains a write buffer that has a 16-word data buffer and a four- address buffer. T he write
buffer is used for all writes to a bufferable region, write-thr ough region and write-back regio n. It also allows to avoid
stalling the processor when writes to external memory are performed. When a store occurs, data is written to the
write buffer at core spe ed (high speed). The wr ite buffer then complete s the store to e xternal me mory at bus spee d
(typically slower than the core speed). During this time, the ARM9EJ-S processor can preform other tasks.
DCache and Write Buffer support write-back and write-through memory regions, controlled by C and B bits in each
section and page descriptor within the MMU translation tables.
10.6.2.3Write-though Operation
When a cache write hit occurs, the DCache line is updated. The updated data is then written to the write buffer
which transfers it to external memory.
When a cache write miss occurs, a line, chosen by round robin or another algorithm, is stored in the write buffer
which transfers it to external memory.
10.6.2.4Write-back Operation
When a cache write hit occurs, the cache line or half line is marked as dirty, meaning that its contents are not up-
to-date with those in the external memory.
When a cache write miss occurs, a line, chosen by round robin or another algorithm, is stored in the write buffer
which transfers it to external memory.
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10.7 Bus Interface Unit
The ARM926EJ-S features a Bus Interface Unit (BIU) that arbitrates and schedules AHB requests. The BIU
implements a multi-layer AHB, based on the AHB-Lite protocol, that enables parallel access paths between
multiple AHB masters and slaves in a system. This is achieved by using a more com plex interconnectio n matrix
and gives the benefit of increased overall bus bandwidth, and a more flexible system architecture.
The multi-master bus architecture has a number of benefits:
It allows the development of multi-master systems with an increased bus ba nd width and a flexib le
architecture.
Each AHB layer becomes simple because it only has one master, so no arbitration or master-to-slave
muxing is required. AHB layers, implementing AHB-Lite protocol, do not have to support request and grant,
nor do they have to support retry and split transactions.
The arbitration becomes effective when more than one master wants to access the same slave
simultaneously.
10.7.1 Supported Transfers
The ARM926EJ-S processor performs all AHB accesses as single word, bursts of four words, or bursts of eight
words. Any ARM9EJ-S core request that is not 1, 4, 8 words in size is split into packets of these sizes. Note that
the Atmel bus is AHB-Lite protocol compliant, hence it does not support split and retry requests.
Table 10-8 gives an overview of the supported transfers and different kinds of transactions they are used for.
10.7.2 Thumb Instruction Fetches
All instructions fetches, regardless of the state of ARM9EJ-S core, are made as 32-bit accesses on the AHB. If the
ARM9EJ-S is in Thumb state, then two instructions can be fetched at a time.
10.7.3 Address Alignment
The ARM926EJ-S BIU performs address alignment checking and aligns AHB addresses to the necessary
boundary. 16-bit accesses are aligned to halfword boundaries, and 32-bit accesses are aligned to word
boundaries.
Table 10-8. Supported Transfers
HBurst[2:0] Description Operation
Single Single transfer
Single transfer of word, half wo rd, or byte:
data write (NCNB, NCB, WT, or WB that has missed in DCache)
data read (NCNB or NCB)
NC instruction fetch (prefetched and non-prefetched)
page table walk read
Incr4 Four-word incrementing burst Ha lf-line cache write-back, Instruction prefetch, if enabled. Four-word burst NCNB,
NCB, WT, or WB write.
Incr8 Eight-word incrementing burst Full-line cache write-back, eight-word burst NCNB, NCB, WT, or WB write.
Wrap8 Eight-word wrapping burst Cache linefill
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11. SAM9XE Debug and Test
11.1 Overview
The SAM9XE features a number of complementary debug and test capabilities. A common JTAG/ICE (In-Circuit
Emulator) port is used for standard debuggin g functions, such as downloading code and single-stepping through
programs. The Debug Un it pr ovides a two- pin UART that can be used to upload an application into internal SRAM.
It manages the interr upt handling of the internal COMMTX and COMMRX sig nals that trace the activity of the
Debug Communication Channel.
A set of dedicated debug and test input/output pins gives direct access to these capabilities from a PC-based test
environment.
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11.2 Block Diagram
Figure 11-1. Debug and Test Block Diagram
ICE-RT
ARM9EJ-S
PDC DBGU
PIO
DRXD
DTXD
TMS
TCK
TDI
JTAGSEL
TDO
TST
Reset
and
Test
TAP: Test Access Port
Boundary
Port
ICE/JTAG
TAP
ARM926EJ-S
POR
RTCK
NTRST
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11.3 Application Examples
11.3.1 Debug Environment
Figure 11-2 shows a complete debug environment example. The ICE/JTAG interface is used for standard
debugging funct ions, such as download ing code and single-step ping through the progra m. A software debugg er
running on a per sonal computer provides the user interface for conf iguring a Trace Port interfa ce utilizing the
ICE/JTAG interface.
Figure 11-2. Application Debug and Trace Environment Example
SAM9XE-based Application Board
ICE/JTAG
Interface
Host Debugger PC
ICE/JTAG
Connector
SAM9XE Terminal
RS232
Connector
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11.3.2 Test Environment
Figure 11-3 shows a test environment example. Test vectors are sent and interpreted by the tester. In this
example, the “board in test” is designed using a number of JTAG-compliant devices. These devices can be
connected to form a single scan chain.
Figure 11-3. Application Test Environment Example
11.4 Debug and Test Pin Description
JTAG
Interface
SAM9XE
Test Adaptor
Chip 2Chip n
Chip 1
ICE/JTAG
Connector
Tester
SAM9XE-based Application Board In Test
Table 11-1. Debug and Test Pin List
Pin Name Function Type Active Level
Reset/Test
NRST Microcontroller Reset Input/Output Low
TST Test Mode Select Input High
ICE and JTAG
NTRST Test Reset Signal Input Low
TCK Test Clock Input
TDI Test Data In Input
TDO Test Data Out Output
TMS Test Mode Select Input
RTCK Returned Test Clock Output
JTAGSEL JTAG Selection Input
Debug Unit
DRXD Debug Receive Data Input
DTXD Debug Transmit Data Output
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11.5 JTAG Port Pins
TMS, TDI and TCK are Schmitt trigger inputs and have no pull-up resistors.
TDO and RTCK are outputs, driven at up to VDDIOP0, and have no pull-up resistors.
The JTAGSEL pin is used to select the JTAG b oundary scan when asserted at a high level (tied to VDDBU). It
integrates a permanent pull-down resistor of about 15 kΩ to GNDBU, so that it can be left unconnected for normal
operations.
All the JTAG signals are supplied with VDDIOP0.
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11.6 Functional Description
11.6.1 Test Pin
One dedica ted pin, TST, is u sed to de fine th e device operating mod e. The user must make sure that this pin is tied
at low level to ensure normal operating conditions. Other values associated with this pin are reserved for
manufacturing test.
11.6.2 Embedded In-circuit Emulator
The ARM9EJ-S Embedded In-Circuit Emulator-RT is supported via the ICE/JTAG port. It is connected to a host
computer via an ICE interface. Debug support is impl emented using an ARM9EJ-S core embedde d within the
ARM926EJ-S. The internal state of the ARM926EJ-S is examined through an ICE/JTAG port which allows
instructions to be serially inserted into the pipeline of the core without using the external data bus. Therefore, when
in debug state, a store-multiple (STM) can be insert ed into the instruction pip eline. This exports th e contents of the
ARM9EJ-S registers. This data can be serially shifted out without affecting the rest of the system.
There are two scan chains inside the ARM9EJ-S processor which support testing, debugging, and programming of
the Embedded ICE-RT. The scan chains are controlled by the ICE/JTAG port.
Embedded ICE mo de is selected when JTAGSEL is low. It is not possible to switch directly between ICE and
JTAG operations. A chip reset must be performed after JTAGSEL is changed.
For further details on the Embedded In-Circuit-Emulator-RT, see the ARM document:
ARM9EJ-S Technical Reference Manual (DDI 0222A).
11.6.3 Debug Unit
The Debug Unit provides a two-pin (DXRD and TXRD) USART that can be used for several debug and trace
purposes and offers an ideal means for in-situ programming solutions and debug monitor communication.
Moreover, the association with two peripheral data controller channels permits packet handling of these tasks with
processor time reduced to a minimum.
The Debug Unit also manages the interrupt ha ndling of the COMMTX and COMMRX signals that come from the
ICE and that trace the activity of th e Debug Com munication Channel.The Debug Unit allows blockage of access to
the system through the ICE interface.
A specific register , the Debug Unit Chip ID Re gister, gives informatio n about the product v ersion and its internal
configuration.
The SAM9XE Debug Unit C hip ID value is 0x0198 03A0 on 32-bit width.
For further details on the Debug Unit, see Section 29. “Debug Unit (DBGU)”.
11.6.4 IEEE 1149.1 JTAG Boundary Scan
IEEE 1149.1 JTAG Boundary Scan allows pin-level access independent of the device packaging technology.
IEEE 1149.1 JTAG Boundary Scan is enabled when JTAGSEL is high. The SAMPLE, EXTEST and BYPASS
functions are implemented. In ICE debug mode, the ARM processor responds with a non-JTAG chip ID that
identifies the processor to the ICE system. This is not IEEE 1149.1 JTAG-compliant.
It is not possible to switch directly between JTAG and ICE operations. A chip reset must be performe d after
JTAGSEL is changed.
A Boundary-scan Descriptor Language (BSDL) file is provided to set up test.
11.6.4.1 JTAG Boundary-scan Register
The Boundary-scan Register (BSR) contains 484 bits that correspond to active pins and associated control
signals.
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Each SAM9XE input/output pin corr esponds to a 3-bit re gister in the BSR. The OUTPUT bit contains data that can
be forced on the pad. The INPUT bit facilitates the observability of data applied to the pad. The CONTROL bit
selects the direc tio n of the pa d .
Table 11-2. SAM9XE JTAG Boundary Scan Register
Bit Number Pin Name Pin Type Associated BSR Cells
307 A0 IN/OUT CONTROL
306 INPUT/OUTPUT
305 A1 IN/OUT CONTROL
304 INPUT/OUTPUT
303 A10 IN/OUT CONTROL
302 INPUT/OUTPUT
301 A11 IN/OUT CONTROL
300 INPUT/OUTPUT
299 A12 IN/OUT CONTROL
298 INPUT/OUTPUT
297 A13 IN/OUT CONTROL
296 INPUT/OUTPUT
295 A14 IN/OUT CONTROL
294 INPUT/OUTPUT
293 A15 IN/OUT CONTROL
292 INPUT/OUTPUT
291 A16 IN/OUT CONTROL
290 INPUT/OUTPUT
289 A17 IN/OUT CONTROL
288 INPUT/OUTPUT
287 A18 IN/OUT CONTROL
286 INPUT/OUTPUT
285 A19 IN/OUT CONTROL
284 INPUT/OUTPUT
283 A2 IN/OUT CONTROL
282 INPUT/OUTPUT
281 A20 IN/OUT CONTROL
280 INPUT/OUTPUT
279 A21 IN/OUT CONTROL
278 INPUT/OUTPUT
277 A22 IN/OUT CONTROL
276 INPUT/OUTPUT
275 A3 IN/OUT CONTROL
274 INPUT/OUTPUT
273 A4 IN/OUT CONTROL
272 INPUT/OUTPUT
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271 A5 IN/OUT CONTROL
270 INPUT/OUTPUT
269 A6 IN/OUT CONTROL
268 INPUT/OUTPUT
267 A7 IN/OUT CONTROL
266 INPUT/OUTPUT
265 A8 IN/OUT CONTROL
264 INPUT/OUTPUT
263 A9 IN/OUT CONTROL
262 INPUT/OUTPUT
261 BMS INPUT INPUT
260 CAS IN/OUT CONTROL
259 INPUT/OUTPUT
258 D0 IN/OUT CONTROL
257 INPUT/OUTPUT
256 D1 IN/OUT CONTROL
255 INPUT/OUTPUT
254 D10 IN/OUT CONTROL
253 INPUT/OUTPUT
252 D11 IN/OUT CONTROL
251 INPUT/OUTPUT
250 D12 IN/OUT CONTROL
249 INPUT/OUTPUT
248 D13 IN/OUT CONTROL
247 INPUT/OUTPUT
246 D14 IN/OUT CONTROL
245 INPUT/OUTPUT
244 D15 IN/OUT CONTROL
243 INPUT/OUTPUT
242 D2 IN/OUT CONTROL
241 INPUT/OUTPUT
240 D3 IN/OUT CONTROL
239 INPUT/OUTPUT
238 D4 IN/OUT CONTROL
237 INPUT/OUTPUT
236 D5 IN/OUT CONTROL
235 INPUT/OUTPUT
234 D6 IN/OUT CONTROL
233 INPUT/OUTPUT
Table 11-2. SAM9XE JT AG Boundary Scan Register (Continued)
Bit Number Pin Name Pin Type Associated BSR Cells
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232 D7 IN/OUT CONTROL
231 INPUT/OUTPUT
230 D8 IN/OUT CONTROL
229 INPUT/OUTPUT
228 D9 IN/OUT CONTROL
227 INPUT/OUTPUT
226 NANDOE IN/OUT CONTROL
225 INPUT/OUTPUT
224 NANDWE IN/OUT CONTROL
223 INPUT/OUTPUT
222 NCS0 IN/OUT CONTROL
221 INPUT/OUTPUT
220 NCS1 IN/OUT CONTROL
219 INPUT/OUTPUT
218 NRD IN/OUT CONTROL
217 INPUT/OUTPUT
216 NRST IN/OUT CONTROL
215 INPUT/OUTPUT
214 NWR0 IN/OUT CONTROL
213 INPUT/OUTPUT
212 NWR1 IN/OUT CONTROL
211 INPUT/OUTPUT
210 NWR3 IN/OUT CONTROL
209 INPUT/OUTPUT
208 OSCSEL INPUT INPUT
207 PA0 IN/OUT CONTROL
206 INPUT/OUTPUT
205 PA1 IN/OUT CONTROL
204 INPUT/OUTPUT
203 PA10 IN/OUT CONTROL
202 INPUT/OUTPUT
201 PA11 IN/OUT CONTROL
200 INPUT/OUTPUT
199 PA12 IN/OUT CONTROL
198 INPUT/OUTPUT
197 PA13 IN/OUT CONTROL
196 INPUT/OUTPUT
195 PA14 IN/OUT CONTROL
194 INPUT/OUTPUT
Table 11-2. SAM9XE JT AG Boundary Scan Register (Continued)
Bit Number Pin Name Pin Type Associated BSR Cells
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193 PA15 IN/OUT CONTROL
192 INPUT/OUTPUT
191 PA16 IN/OUT CONTROL
190 INPUT/OUTPUT
189 PA17 IN/OUT CONTROL
188 INPUT/OUTPUT
187 PA18 IN/OUT CONTROL
186 INPUT/OUTPUT
185 PA19 IN/OUT CONTROL
184 INPUT/OUTPUT
183 PA2 IN/OUT CONTROL
182 INPUT/OUTPUT
181 PA20 IN/OUT CONTROL
180 INPUT/OUTPUT
179 PA21 IN/OUT CONTROL
178 INPUT/OUTPUT
177 PA22 IN/OUT CONTROL
176 INPUT/OUTPUT
175 PA23 IN/OUT CONTROL
174 INPUT/OUTPUT
173 PA24 IN/OUT CONTROL
172 INPUT/OUTPUT
171 PA25 IN/OUT CONTROL
170 INPUT/OUTPUT
169 PA26 IN/OUT CONTROL
168 INPUT/OUTPUT
167 PA27 IN/OUT CONTROL
166 INPUT/OUTPUT
165 PA28 IN/OUT CONTROL
164 INPUT/OUTPUT
163 PA29 IN/OUT CONTROL
162 INPUT/OUTPUT
161 PA3 IN/OUT CONTROL
160 INPUT/OUTPUT
159 internal
158 internal
157 internal
156 internal
155 PA4 IN/OUT CONTROL
154 INPUT/OUTPUT
Table 11-2. SAM9XE JT AG Boundary Scan Register (Continued)
Bit Number Pin Name Pin Type Associated BSR Cells
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153 PA5 IN/OUT CONTROL
152 INPUT/OUTPUT
151 PA6 IN/OUT CONTROL
150 INPUT/OUTPUT
149 PA7 IN/OUT CONTROL
148 INPUT/OUTPUT
147 PA8 IN/OUT CONTROL
146 INPUT/OUTPUT
145 PA9 IN/OUT CONTROL
144 INPUT/OUTPUT
143 PB0 IN/OUT CONTROL
142 INPUT/OUTPUT
141 PB1 IN/OUT CONTROL
140 INPUT/OUTPUT
139 PB10 IN/OUT CONTROL
138 INPUT/OUTPUT
137 PB11 IN/OUT CONTROL
136 INPUT/OUTPUT
135 internal
134 internal
133 internal
132 internal
131 PB14 IN/OUT CONTROL
130 INPUT/OUTPUT
129 PB15 IN/OUT CONTROL
128 INPUT/OUTPUT
127 PB16 IN/OUT CONTROL
126 INPUT/OUTPUT
125 PB17 IN/OUT CONTROL
124 INPUT/OUTPUT
123 PB18 IN/OUT CONTROL
122 INPUT/OUTPUT
121 PB19 IN/OUT CONTROL
120 INPUT/OUTPUT
119 PB2 IN/OUT CONTROL
118 INPUT/OUTPUT
117 PB20 IN/OUT CONTROL
116 INPUT/OUTPUT
115 PB21 IN/OUT CONTROL
114 INPUT/OUTPUT
Table 11-2. SAM9XE JT AG Boundary Scan Register (Continued)
Bit Number Pin Name Pin Type Associated BSR Cells
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113 PB22 IN/OUT CONTROL
112 INPUT/OUTPUT
111 PB23 IN/OUT CONTROL
110 INPUT/OUTPUT
109 PB24 IN/OUT CONTROL
108 INPUT/OUTPUT
107 PB25 IN/OUT CONTROL
106 INPUT/OUTPUT
105 PB26 IN/OUT CONTROL
104 INPUT/OUTPUT
103 PB27 IN/OUT CONTROL
102 INPUT/OUTPUT
101 PB28 IN/OUT CONTROL
100 INPUT/OUTPUT
99 PB29 IN/OUT CONTROL
98 INPUT/OUTPUT
97 PB3 IN/OUT CONTROL
96 INPUT/OUTPUT
95 PB30 IN/OUT CONTROL
94 INPUT/OUTPUT
93 PB31 IN/OUT CONTROL
92 INPUT/OUTPUT
91 PB4 IN/OUT CONTROL
90 INPUT/OUTPUT
89 PB5 IN/OUT CONTROL
88 INPUT/OUTPUT
87 PB6 IN/OUT CONTROL
86 INPUT/OUTPUT
85 PB7 IN/OUT CONTROL
84 INPUT/OUTPUT
83 PB8 IN/OUT CONTROL
82 INPUT/OUTPUT
81 PB9 IN/OUT CONTROL
80 INPUT/OUTPUT
79 PC0 IN/OUT CONTROL
78 INPUT/OUTPUT
77 PC1 IN/OUT CONTROL
76 INPUT/OUTPUT
75 PC10 IN/OUT CONTROL
74 INPUT/OUTPUT
Table 11-2. SAM9XE JT AG Boundary Scan Register (Continued)
Bit Number Pin Name Pin Type Associated BSR Cells
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73 PC11 IN/OUT CONTROL
72 INPUT/OUTPUT
71 internal
70 internal
69 PC13 IN/OUT CONTROL
68 INPUT/OUTPUT
67 PC14 IN/OUT CONTROL
66 INPUT/OUTPUT
65 PC15 IN/OUT CONTROL
64 INPUT/OUTPUT
63 PC16 IN/OUT CONTROL
62 INPUT/OUTPUT
61 PC17 IN/OUT CONTROL
60 INPUT/OUTPUT
59 PC18 IN/OUT CONTROL
58 INPUT/OUTPUT
57 PC19 IN/OUT CONTROL
56 INPUT/OUTPUT
55 internal
54 internal
53 PC20 IN/OUT CONTROL
52 INPUT/OUTPUT
51 PC21 IN/OUT CONTROL
50 INPUT/OUTPUT
49 PC22 IN/OUT CONTROL
48 INPUT/OUTPUT
47 PC23 IN/OUT CONTROL
46 INPUT/OUTPUT
45 PC24 IN/OUT CONTROL
44 INPUT/OUTPUT
43 PC25 IN/OUT CONTROL
42 INPUT/OUTPUT
41 PC26 IN/OUT CONTROL
40 INPUT/OUTPUT
39 PC27 IN/OUT CONTROL
38 INPUT/OUTPUT
37 PC28 IN/OUT CONTROL
36 INPUT/OUTPUT
35 PC29 IN/OUT CONTROL
34 INPUT/OUTPUT
Table 11-2. SAM9XE JT AG Boundary Scan Register (Continued)
Bit Number Pin Name Pin Type Associated BSR Cells
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33 internal
32 internal
31 PC30 IN/OUT CONTROL
30 INPUT/OUTPUT
29 PC31 IN/OUT CONTROL
28 INPUT/OUTPUT
27 PC4 IN/OUT CONTROL
26 INPUT/OUTPUT
25 PC5 IN/OUT CONTROL
24 INPUT/OUTPUT
23 PC6 IN/OUT CONTROL
22 INPUT/OUTPUT
21 PC7 IN/OUT CONTROL
20 INPUT/OUTPUT
19 PC8 IN/OUT CONTROL
18 INPUT/OUTPUT
17 PC9 IN/OUT CONTROL
16 INPUT/OUTPUT
15 RAS IN/OUT CONTROL
14 INPUT/OUTPUT
13 RTCK OUT CONTROL
12 OUTPUT
11 SDA10 IN/OUT CONTROL
10 INPUT/OUTPUT
09 SDCK IN/OUT CONTROL
08 INPUT/OUTPUT
07 SDCKE IN/OUT CONTROL
06 INPUT/OUTPUT
05 SDWE IN/OUT CONTROL
04 INPUT/OUTPUT
03 SHDN OUT CONTROL
02 OUTPUT
01 TST INPUT INPUT
00 WKUP INPUT INPUT
Table 11-2. SAM9XE JT AG Boundary Scan Register (Continued)
Bit Number Pin Name Pin Type Associated BSR Cells
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11.6.5 JID Code Register
Access: Read-only
• VERSION[31:28]: Product Version Number
Set to 0x0.
• PART NUMBER[27:12]: Product Part Number
Product part Number is 0x5B13
• MANUFACTURER IDENTITY[11:1]
Set to 0x01F.
Bit[0] Required by IEEE Std. 1149.1.
Set to 0x1.
JTAG ID Code value is 0x05B1_303F.
31 30 29 28 27 26 25 24
VERSION PART NUMBER
23 22 21 20 19 18 17 16
PART NUMBER
15 14 13 12 11 10 9 8
PAR T NUMBER MANUFACTURER IDENTITY
76543210
MANUFACTURER IDENTITY 1
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12. SAM9XE Boot Program
12.1 Overview
The Boot Program integrates different programs permitting download and/or upload into the different memories of
the product.
First, it initializes the Debug Unit serial port (DBGU) and the USB Device Port.
SAM-BA Boot is then executed. It waits for transactions either on the USB device, or on the DBGU serial port.
12.2 Flow Diagram
The Boot Program im plements the algorithm in Figure 12-1.
Figure 12-1. Boot Program Algorithm Flow Diagram
Large
Crystal Table
SAM-BA Boot
Internal RC Oscillator Yes
No
Main Oscillator Bypass Yes
Start
Reduced
Crystal Table
No
Input Frequency
Table
Character(s) received
on DBGU ?
Run SAM-BA Boot Run SAM-BA Boot
USB Enumeration
Successful ?
Yes Yes
No
No
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12.3 Device Initialization
Initialization follows the steps described below:
1. FIQ Initialization
2. Stack setup for ARM supervisor mode
3. External Cloc k Detection
4. Switch Master Clock on Main Oscillator
5. C variable initialization
6. Main oscillator frequency detection if no external clock detected
7. PLL setup: PLLB is initialized to generate a 48 MHz clock necessary to use the USB Device. A register
located in the Power Management Controller (PMC) determines the frequency of the main oscillator and
thus the correct factor for the PLLB.
a. If Internal RC Oscillator is used (OSCSEL = 0) and Main Oscillator is active, Table 12-1 defines the
crystals supported by the Boot Program when using the internal RC oscillator.
Note: Any other crystal can be used but it prevents using the USB.
b. If Internal RC Oscillator is used (OSCSEL = 0) and Main Oscillator is bypassed, T ab le 12 -2 defines
the frequencies supported by the Boot Program when bypassing main oscillator.
Note: Any other input frequency can be used but it prevents using the USB.
c. If an external 32768 Hz Oscillator is used (OSCSEL = 1) (OSCSEL = 1 and Bypass mode), Table 12-
3 defines the crystals supported by the Boot Program.
Note: Booting on USB or on DBGU is possible with any of these crystals.
8. Initialization of the DBGU serial port (115200 bauds, 8, N, 1) only if OSCSEL = 1
9. Enable the user reset
10. Jump to SAM-BA Boot sequence
11. Disable the Watchdog
12. Initialization of the USB Device Port
Table 12-1. Reduced Crystal Table (MHz) OSCSEL = 0
3.0 6.0 18.432 Other
Boot on DBGU Yes Yes Yes Yes
Boot on USB Yes Yes Yes No
Table 12-2. Input Frequencies Supported by Software Auto-detection (MHz) OSCSEL = 0
1.0 2.0 6.0 12.0 25.0 50.0 Other
Boot on DBGU Yes Yes Yes Yes Yes Yes Yes
Boot on USB Yes Yes Yes Yes Yes Yes No
Table 12-3. Large Crystal Table (MHz) OSCSEL = 1
3.0 3.2768 3.6864 3.84 4.0
4.433619 4.9152 5.0 5.24288 6.0
6.144 6.4 6.5536 7.159090 7.3728
7.864320 8.0 9.8304 10.0 11 .05920
12.0 12.288 13.56 14.31818 14.7456
16.0 16.367667 17.734470 18.432 20.0
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Figure 12-2 . Clocks and DBGU Configurations
EndEnd
Scan Large Crystal Table
Yes
Start
Internal RC Oscillator?
(OSCSEL = 0)
No
MCK = PLLB/2
UDPCK = PLLB/2
"ROMBoot>" displayed on DBGU
MCK = Mosc
UDPCK = PLLB/2
DBGU not configured
Yes (DBGU)
Autobaudrate ?
No (USB)
MCK = Mosc
UDPCK = PLLB/2
DBGU not configured
MCK = PLLB
UDPCK = xxxx
DBGU configured
End
Scan Reduced Crystal Table
No
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12.4 SAM-BA Boot
The SAM-BA boot princip le is to:
Wait for USB Device enumeration.
In parallel, wait for char acte r(s) r eceived on the DBGU if M CK is configur ed to 4 8 MHz (OSCSEL = 1).
If not, the auto baud rate sequence is executed in parallel (see Figure 12-3).
Figure 12-3. Auto Baud Rate Flow Diagram
Once the communication interface is identified, the application runs in an infinite loop waiting for different
commands as in Table 12-4 on page 83.
Device
Setup
Character '0x80'
received ? No
Yes
Character '0x80'
received ? No
Yes
Character '#'
received ?
Yes
Run SAM-BA Boot
Send Character '>'
No
1st measurement
2nd measurement
Test Communication
UART operational
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Write commands: Writes a byte (O), a halfword (H) or a word (W) to the t arget.
Address: Address in hexadecimal.
Value: Byte, halfword or word to write in hexadecimal.
Output: ‘>’.
Read commands: Reads a byte (o), a halfword (h) or a word (w) from the target.
Address: Address in hexadecimal
Output: Th e byte, halfword or word read in hexadecimal following by ‘>’
Send a file (S): Sends a file to a specified address
Address: Address in hexadecimal
Output: ‘>’.
Note: There is a time-out on this command which is reached whe n the prompt ‘>’ appears before the end of the command
execution.
Receive a file (R): Receives data into a file from a specified address
Address: Address in hexadecimal
NbOfBytes: Number of bytes in hexadecimal to receive
Output: ‘>’
Go (G): Jumps to a specified address and execute the code
Address: Address to jump in hexadecimal
Output: ‘>’
Get Version (V): Returns the SAM-BA boot version
Output: ‘>’
12.4.1 DBGU Serial Port
Communication is performed through the DBGU serial port initialized to 115200 baud, 8, n, 1.
The Send and Receive File commands use the Xmodem protocol to communicate. Any terminal performing this
protocol can be used to send th e application file to the target. The size of the binary file to se nd depends on the
SRAM size embedded in the product. In all cases, the size of the binary file must be lower than the SRAM size
because the Xmodem protocol requires some SRAM memory to work.
Table 12-4. Commands Available throu gh the SAM-BA Boot
Command Action Argument(s) Example
Owrite a byte Address, Value# O200001,CA#
oread a byte Address,# o200001,#
Hwrite a half word Address, Value# H200002,CAFE#
hread a half word Address,# h200002,#
Wwrite a word Address, Value# W200000,CAFEDECA#
wread a word Address,# w200000,#
Ssend a file Address,# S200000,#
Rreceive a file Address, NbOfBytes# R200000,1234#
Ggo Address# G200200#
Vdisplay version No argument V#
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12.4.2 Xmodem Protocol
The Xmodem protocol supported is the 128-byte length block. This protocol uses a two-character CRC-16 to
guarantee detection of a maximum bit error.
Xmodem protocol with CRC is accurate provided both sender and receiver repo rt successful transmission. Each
block of the transfer looks like:
<SOH><blk #><255-blk #><--128 data by te s-- ><c he ck sum > in wh ich:
<SOH> = 01 hex
<blk #> = binary number, starts at 01, increments by 1, and wraps 0FFH to 00H (not to 01)
<255-blk #> = 1’s complement of the blk#.
<checksum> = 2 bytes CRC16
Figure 12-4 shows a transm issio n us ing this pr ot oc ol.
Figure 12-4. Xmodem Transfer Example
12.4.3 USB Device Port
A 48 MHz USB clock is necessary to use the USB Device port. It has been programmed earlier in the device
initialization procedure with PLLB configuration.
The device uses the USB communication device class (CDC) drivers to take advantage of the installed PC RS- 232
software to talk over the USB. The CDC class is implemented in all releases of Windows®, beginning with
Windows 98SE. The CDC document, available at www.usb.org, describes a way to implement devices such as
ISDN modems and virtual COM ports.
The Vendor ID is Atmel’s vendor ID 0x03EB. The product ID is 0x6124. These references are used by the host
operating system to mount the correct driver. On Windows systems, the INF files co ntain the correspondence
between vendor ID and product ID.
Atmel provides an INF example to see the device as a new serial port and also provides another cu stom driver
used by the SAM-BA application: atm6124.sys.
Host Device
SOH 01 FE Data[128] CRC CRC
C
ACK
SOH 02 FD Data[128] CRC CRC
ACK
SOH 03 FC Data[100] CRC CRC
ACK
EOT
ACK
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12.4.3.1Enumeration Process
The USB protocol is a master/slave protocol. This is the host that starts the enumeration sending requests to the
device through the control endpoint. The device handles standard requests as defined in the USB Specification.
The device also handles some class requests defined in the CDC class.
Unhandled requests are STALLed.
12.4.3.2Communication End points
There are two communication endpoints and endpoint 0 is used for the enumeration process. Endpoint 1 is a 64-
byte Bulk OUT endp oint and endpoin t 2 is a 64-byte Bu lk IN endpoint. SAM -BA Boot command s are sent by the
host through the endpoint 1. If required, the message is split by the host into several data payloads by the host
driver.
If the command requires a response, the host can send IN transactions to pick up the response.
12.4.4 In -Application Programming (IAP) Feature
The IAP feature is a function located in ROM that can be called by any software application.
When called, this function sends the desired FLASH command to the EEFC and waits for the FLASH to be ready
(looping while the FRDY bit is not set in the MC_FSR).
Since this function is executed from ROM, this allows FLASH programming (like sector write) to be done by code
running in FLASH.
The IAP function entry point is retrieved by reading the SWI vector in ROM (0x100008).
This function takes one argument in parameter: the command to be sent to the EEFC.
This function returns the value of the MC_FSR.
Table 12-5. Handled Standard Requests
Request Definition
GET_DESCRIPTOR Returns the current device configurati on value.
SET_ADDRESS Sets the device address for all future device access.
SET_CONFIGURATION Sets the device configuration.
GET_CONFIGURATION Returns the current device configuration value.
GET_STATUS Returns status for the specified recipient.
SET_FEATURE Use d to set or enable a specific feature.
CLEAR_FEATURE Used to clear or disable a speci fi c fe ature.
Table 12-6. Handled Class Requests
Request Definition
SET_LINE_CODING Configure s DTE rate, stop bits, parity and number of character bits.
GET_LINE_CODING Requests current DTE rate, stop bits, parity and number of character bits.
SET_CONTROL_LINE_STATE RS-232 signal used to tell th e DCE device the DT E device is now present.
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IAP software code example:
(unsigned int) (*IAP_Function)(unsigned long);
void main (void)
{unsigned long FlashSectorNum = 200;
unsigned long flash_cmd = 0;
unsigned long flash_status = 0;
/* Initialize the function pointer (retrieve function addre ss from SWI vector)
*/
IAP_Function = ((unsigned long) (*)(unsigned long))
0x100008;
/* Send your data to the sector */
/* build the command to send to EFC */
flash_cmd = (0x5A << 24) | (FlashSectorNum << 8) |
AT91C_MC_FCMD_EWP;
/* Call the IAP function with appropriate command */
flash_status = IAP_Function (flash_cmd);
}
12.5 Hardware and Software Constraints
USB requirements:
Crystal or Input Frequencies supported by Software Auto-detection. See Table 12-1, Table 12-2 and
Table 12-3 on page 80 for more information.
Table 12-7 contains a list of pins that are driven during the boot program execution. These pins are driven during
the boot sequence.
Table 12-7. Pins Driven during Boot Program Execution
Peripheral Pin PIO Line
DBGU DRXD PIOB14
DBGU DTXD PIOB15
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13. Fast Flash Programming Interface (FFPI)
13.1 Description
The Fast Flash Programming Interface provides two solutions - parallel or serial - for high-volume programming
using a standard gang pr ogra mmer. Th e paralle l interface is fully ha ndshaked and the d evice is con sidered to be a
standard EEPROM. Additionally, the parallel protocol offers an optimized access to all the embedded Flash
functionalities. The serial interface uses the standard IEEE 1149.1 JTAG protocol. It offers an optimized access to
all the embedded Flash functionalities.
Although the Fast F lash Programming Mode is a dedicated mode for high volum e programming, this mode no t
designed for in-situ programming.
13.2 Parallel Fast Flash Programming
13.2.1 Device Configuration
In Fast Flash Programming M ode, the device is in a specific test mode. Only a certain set of pins is significant.
Other pins must be left unconnected.
Figure 13-1. Parallel Programming Interface
Table 13-1. Signal Description List
Signal Name Function Type Active
Level Comments
Power
VDDBU Backup Power Supply
VDDIO I/O Lines Power Supply Power
VDDCORE Core Power Supply Power
VDDPLL PLL Power Supply Power
GND Ground Ground
NCMD PGMNCMD
RDY PGMRDY
NOE PGMNOE
NVALID PGMNVALID
MODE[3:0] PGMM[3:0]
DATA[15:0] PGMD[15:0]
XIN
TST
VDDBU PGMEN0
PGMEN1
0 - 50MHz
VDDIO
VDDCORE
VDDIO
VDDPLL
GND
GND
VDDIO
PGMEN2
GND PGMEN3
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13.2.2 Signal Names
Depending on the MODE settings, DATA is latched in different internal registers.
When MODE is equal to CMDE, then a new command (strobed on DATA[15:0] signals) is stored in the command
register.
Clocks
XIN Main Clock Input.
This input can be tied to GND. In this case, the
device is clocked by the internal RC oscillator. Input 32 kHz to 50 MHz
Test
TST Test Mo de Select Input High Must be connected to VDDBU
PGMEN0 Test Mo de Select Input High Must be connected to VDDIO
PGMEN1 Test Mo de Select Input High Must be connected to VDDIO
PGMEN2 Test Mode Select Input Low Must be connected to GND
PGMEN3 Test Mode Select Input Low Must be connected to GND
PIO
PGMNCMD Val id command available Input Low Pulled-up input at reset
PGMRDY 0: Device is busy
1: Device is ready for a new command Output High Pulled-up input at reset
PGMNOE Output Enable (active high) Input Low Pulled-up input at reset
PGMNVALID 0: DATA[15:0] is in input mode
1: DATA[15:0] is in output mode Output Low Pulled-up input at reset
PGMM[3:0] Specifies DATA type (See Table 13-2) Input Pulled-up input at reset
PGMD[15:0] Bi-directional data bus Input/Output Pulled-up input at reset
Table 13-1. Signal Description List (Continued)
Signal Name Function Type Active
Level Comments
Table 13-2. Mode Codi ng
MODE[3:0] Symbol Data
0000 CMDE Command Register
0001 ADDR0 Address Register LSBs
0010 ADDR1
0011 ADDR2
0100 ADDR3 Address Register MSBs
0101 DATA Data Register
Default IDLE No register
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13.2.3 Entering Programming Mode
The following algorithm puts the device in Parallel Programming Mode:
Apply GND, VDDIO, VDDCORE and VDDPLL.
Apply XIN clock within TPOR_RESET if an external clock is available.
Wait for TPOR_RESET
Start a read or write handshaking.
Note: After reset, the device is clocked by the internal RC oscillator. Before clearing RDY signal, if an external clock ( > 32
kHz) is connected to XIN, then the device switches on the external clock. Else, XIN input is not considered. A higher
frequency on XIN speeds up the programmer handshake.
13.2.4 Programmer Handshaking
An handshake is de fined for read and writ e operations. When th e device is ready to start a new oper ation (RDY
signal set), the programmer starts the handshake by clearing the NCMD signal. The handshaking is achieved once
NCMD signal is high and RDY is high.
13.2.4.1 Write Handshaking
For details on the write handshaking sequence, refer to Figure 13-2 and Table 13-4.
Table 13-3. Command Bit Coding
DATA[15:0] Symbol Command Executed
0x0011 READ Read Flash
0x0012 WP Write Page Fl ash
0x0022 WPL Write Page and Lock Flash
0x0032 EWP Erase Page and Write Page
0x0042 EWPL Erase Page and Write Page then Lock
0x0013 EA Erase All
0x0014 SLB Set Lock Bit
0x0024 CLB Clear Lock Bit
0x0015 GLB Get Lock Bit
0x0034 SGPB Set General Purpose NVM bit
0x0044 CGPB Clear Gen eral Purpose NVM bit
0x0025 GGPB Get General Purpose NVM bit
0x0054 SSE Set Security Bit
0x0035 GSE Get Security Bit
0x001F WRAM Write Memory
0x001E GVE Get Version
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Figure 13-2. Parallel Programming Timing, Write Sequence
13.2.4.2 Read Handshaking
For details on the read handshaking sequence, refer to Figure 13-3 and Table 13-5.
Figure 13-3. Parallel Programming Timing, Read Sequence
Table 13-4. Write Handshake
Step Program m e r Action Device Action Data I/O
1 Sets MODE and DATA signals Waits for NCMD low Input
2 Clears NCMD signal Latches MODE and DATA Input
3 Waits for RDY low Clears RDY signal Input
4 Releases MODE and DATA signals Executes comma nd and polls NCMD high Input
5 Sets NCMD signal Executes command and polls NCMD high Input
6 Waits for RDY high Sets RDY Input
NCMD
RDY
NOE
NVALID
DATA[15:0]
MODE[3:0]
1
2
3
4
5
NCMD
RDY
NOE
NVALID
DATA[15:0]
MODE[3:0]
1
2
3
4
5
6
7
9
8
ADDR
Adress IN Z Data OUT
10
11
XIN
12
13
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13.2.5 Device Operations
Several commands on the Flash memory are available. These commands are summarized in Table 13-3 on page
89. Each command is driven by the programmer through the parallel interface running several read/write
handshaking sequences.
When a new command is executed, the previous one is automatically achieved. Thus, chaining a read command
after a write automatically flushes the load buffer in the Flash.
13.2.5.1 Flash Read Command
This command is used to read the contents of the Flash memory. The read command can start at any valid
address in the memory plane and is optimized for consecutive reads. Read handshaking can be chained; an
internal address buffer is automatically increased.
Table 13-5. Read Hand shake
Step Program mer Action Device Action DATA I/O
1 Sets MODE and DATA signal s Waits for NCMD low Input
2 Clears NCMD signal Latch MODE and DATA Input
3 W ait s for RDY low Clears RDY signal Input
4 Sets DATA signal in tristate Waits for NOE Low Input
5 Clears NOE signal Tristate
6 W aits for NVALID low Sets DATA bus in output mode and outputs the flash contents. Output
7 Clears NVALID signal Output
8 Reads value on DATA Bus Waits for NOE high Output
9 Sets NOE signal Output
10 Waits for NVALID high Sets DATA bus in input mode X
11 Sets DATA in output mode Sets NVALID signal Input
12 Sets NCMD signal Waits for NCMD high Input
13 Waits for RDY high Sets RDY signal Input
Table 13-6. Read Command
Step Handshake Sequence MODE[3:0] DATA[15:0]
1 W rite handshaking CMDE READ
2 Write handshaking ADDR0 Memory Address LSB
3 W rite handshaking ADDR1 Memory Address
4 Read handshaking DATA *Memory Address++
5 Read handshaking DATA *Memory Address++
... ... ... ...
n Write handshaking ADDR0 Memory Address LSB
n+1 Write handshaking ADDR1 Memory Address
n+2 Read handshaking DATA *Memory Address++
n+3 Read handshaking DATA *Memory Address++
... ... ... ...
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13.2.5.2 Flash Write Command
This command is used to write the Flash contents.
The Flash memory plane is organized into several pages. Data to be written are stored in a load buffer that
corresponds to a Flash memory page. The load buffer is automatically flushed to the Flash:
before access to any page other than the current one
when a new command is validated (MODE = CMDE)
The Write Page command (WP) is optimized for consecutive writes. Write handshaking can be chained; an
internal address buffer is automatically increased
The Flash command Write Page and Lock (WPL) is equivalent to the Flash Write Command. However, the lock
bit is automatically set at the end of the Flash write operation. As a lock region is composed of several pages, the
programmer writes to the first pages of the lock region using Flash write commands and writes to the last page of
the lock region using a Flash write and lock command.
The Flash command Erase Page and Write (EWP) is equivalent to the Flash Write Command. However, before
programming the load buffer, the page is erased.
The Flash command Erase Page and Write the Lock (EWPL) combines EWP and WPL commands.
13.2.5.3 Flash Full Erase Command
This command is used to erase the Flash memory planes.
All lock regions must be unlocked before the Full Erase command by using the CLB command. Otherwise, the
erase command is aborted and no page is erased.
13.2.5.4 Flash Lock Commands
Lock bits can be set using WPL or EWPL commands. They can also be set by using the Set Lock command
(SLB). With this command, several lock bits can be activated. A Bit Mask is provided as argument to the
command. When bit 0 of the bit mask is set, then the first lock bit is activated.
Table 13-8. Write Command
Step Handshake Sequence MODE[3:0] DATA[15:0]
1 Write handshaking CMDE WP or WPL or EWP or EWPL
2 W rite handshaking ADDR0 Memory Address LSB
3 W rite handshaking ADDR1 Memory Address
4 W rite handshaking DATA *Memory Address++
5 W rite handshaking DATA *Memory Address++
... ... ... ...
n W rite handshaking ADDR0 Memory Address LSB
n+1 Write handshaking ADDR1 Memory Address
n+2 Write handshaking DATA *Memory Address++
n+3 Write handshaking DATA *Memory Address++
... ... ... ...
Table 13-9. Full Erase Command
Step Handshake Sequence MODE[3:0] DATA[15:0]
1 Write handshaking CMDE EA
2 Write handshaking DATA 0
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In the same way, the Clear Lock command (CLB) is used to clear lock bits. All the lock bi ts are also cleared by the
EA command.
Lock bits can be read using Get Lock Bit command (GLB). The nth lock bit is active when the bit n of the bit mask
is set..
13.2.5.5 Flash General-purpose NVM Commands
General-purpose NVM bits (GP NVM bits) can be set using the Set GPNVM command (SGPB). This command
also activates GP NVM bits. A bit mask is provided as argument to the command. When bit 0 of the bit mask is set,
then the first GP NVM bit is activated.
In the same way, the Clear GPNVM command (CGPB) is used to clear general-purp ose NVM bits. All the genera l-
purpose NVM bits are also cleared by the EA command. The general-purpose NVM bit is deactivated when the
corresponding bit in the pattern value is set to 1.
General-purpose NVM bits can be read using the Get GPNVM Bit command (GGPB). The nth GP NVM bit is
active when bit n of the bit mask is set..
13.2.5.6 Flash Security Bit Command
A security bit can be set using the Set Security Bit command (SSE). Once the security bit is active, the Fast Flash
programming is disabled. No other command can be run. An event on the Erase pin can erase the security bit
once the contents of the Flash have been erased.
Table 13-10. Set and Clear Lock Bit Command
Step Handshake Sequence MODE[3:0] DATA[15:0]
1 Write handshaking CMDE SLB or CLB
2 Write handshaking D ATA Bit Mask
Table 13-11. Get Lock Bit Command
Step Handshake Sequence MODE[3:0] DATA[15:0]
1 Write handshaking CMDE GLB
2 Read handshaking DATA Lock Bit Mask Status
0 = Lock bit is cleared
1 = Lock bit is set
Table 13-12. Set/Clear GP NVM Command
Step Handshake Sequence MODE[3:0] DATA[15:0]
1 Write handshaking CMDE SGPB or CGPB
2 Write handshaking DATA GP NVM bit pattern value
Table 13-13. Get GP NVM Bit Command
Step Handshake Sequence MODE[3:0] DATA[15:0]
1 Write handshaking CMDE GGPB
2 Read handshaking DATA GP NVM Bit Mask Status
0 = GP NVM bit is cleared
1 = GP NVM bit is set
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Once the security bit is set, it is not possible to access FFPI. The only way to erase the security bit is to erase the
Flash.
In order to erase the Flash, the user must perform the following:
Power-off the chip
Power-on the chip with TST = 0
Assert Erase during a period of more than 220 ms
Power-off the chip
Then it is possible to return to FFPI mode and check that Flash is erased.
13.2.5.7 Memory Write Command
This command is used to perform a write access to any memory location.
The Memory Write command (WRAM) is optimized for consecutive writes. Write handshaking can be chained; an
internal address buffer is automatically increased
13.2.5.8 Get Version Command
The Get Version (GVE) command retrieves the ver sio n of the F FPI inte rfa ce .
Table 13-14. Set Security Bit Command
Step Handshake Sequence MODE[3:0] DATA[15:0]
1 Write handshaking CMDE SSE
2 Write handshaking DATA 0
Table 13-15. Write Command
Step Handshake Sequence MODE[3:0] DATA[15:0]
1 W rite handshaking CMDE WRAM
2 W rite handshaking ADDR0 Memory Address LSB
3 W rite handshaking ADDR1 Memory Address
4 W rite handshaking DATA *Memory Address++
5 W rite handshaking DATA *Memory Address++
... ... ... ...
n W rite handshaking ADDR0 Memory Address LSB
n+1 Write handshaking ADDR1 Memory Address
n+2 Write handshaking DATA *Memory Address++
n+3 Write handshaking DATA *Memory Address++
... ... ... ...
Table 13-16. Get Version Command
Step Handshake Sequence MODE[3:0] DATA[15:0]
1 Write handshaking CMDE GVE
2 Write handshaking DATA Version
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13.3 Serial Fast Flash Programming
The Serial Fast Flash programming interface is based on IEEE Std. 1149.1 “Standard Test Access Port and
Boundary-Scan Architecture”. Refer to this standard for an exp lanation of terms used in this section and for a
description of the TAP controller states.
In this mode, data read/written from/to the embedded Flash of the device are transmitted through the JTAG
interface of the device.
13.3.1 Device Configuration
In Serial Fast Flash Programming Mode, the device is in a specific test mode. Only a distinct set of pins is
significant. Other pins must be left unconnected.
Figure 13-4. Serial Programming
TDI
TDO
TMS
TCK
XIN
TST
VDDBU PGMEN0
PGMEN1
0-50MHz
VDDIO
VDDCOR
E
VDDIO
VDDPLL
GND
VDDIO
GND PGMEN2
GND PGMEN3
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13.3.2 Entering Serial Programming Mode
The following algorithm puts the device in Serial Programming Mode:
Apply GND, VDDIO, VDDCORE and VDDPLL.
Apply XIN clock within TPOR_RESET + 32(TSCLK) if an external clock is available.
Wait for TPOR_RESET.
Reset the TAP controller clocking 5 TCK pulses with TMS set.
Shift 0x2 into the IR register (IR is 4 bits long, LSB first) without going through the Run-Test-Idle state.
Shift 0x2 into the DR register (DR is 4 bits long, LSB fir st) without going through the Run-Test-Idle state.
Shift 0xC into the IR register (IR is 4 bits long, LSB first) without going through the Run-Test-Idle state.
Note: After reset, the device is clocked by the internal RC oscillator. Before clearing RDY signal, if an external clock ( > 32
kHz) is connected to XIN, then the device will switch on the external clock. Else, XIN input is not considered. An higher
frequency on XIN speeds up the programmer handshake.
Table 13-17. Sign al Description List
Signal Name Function Type Active Level Comments
Power
VDDBU Backup Power Supply Power
VDDIO I/O Lines Power Supply Power
VDDCORE Core Power Supply Power
VDDPLL PLL Power Supply Power
GND Ground Ground
Clocks
XIN Main Clock Input
This input can be tied to GND. In this case, the device is
clocked by the internal RC oscillator . Input 32 kHz to 50 MHz
Test
TST Test Mode Select Input High Must be connected to VDDBU
PGMEN0 Test Mode Select Input Hi g h Must be connected to VDDIO
PGMEN1 Test Mode Select Input Hi g h Must be connected to VDDIO
PGMEN2 Test Mode Select Input Low Must be connected to GND
PGMEN3 Test Mode Select Input Low Must be connected to GND
JTAG
TCK JTAG TCK Input – Pulled-up inp ut at reset
TDI JTAG Test Data In Input – Pulled-up input at reset
TDO JTAG Test Data Out Output –
TMS JTAG Test Mode Select Input – Pulled-up input at reset
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13.3.3 Read/Write Handshake
The read/write handshake is done by carrying out read/write operations on tw o registers of the device that are
accessible through the JTAG:
Debug Comms Control Register: DCCR
Debug Comms Data Register: DCDR
Access to these registers is done thro ugh the TAP 38-bi t DR register comprising a 32- bit data field, a 5-bit addre ss
field and a r ea d/write bit. The d ata to b e wr itten is scan ne d in to the 3 2- bit data fie ld with the addr ess of th e reg iste r
to the 5-bit address field an d 1 to the rea d/write bit. A re gister is read by scanning its address into the a ddress field
and 0 into the read/write bit, going through the UPDATE-DR TAP state, then scanning out the data.
Refer to the ARM7TDMI reference manuel for more information on Comm channel operations.
Figure 13-5. TAP 8-bit DR Register
A read or write takes place when the TAP controller enters UPDATE -DR state. Refer to the IEEE 1149.1 for more
details on JTAG operations.
The address of th e Deb u g Com m s Con tr o l Re gis te r is 0x04 .
The address of the Debug Comms Data Register is 0x05.
The Debug Comms Control Register is read-only and allows synchronized handshaking between the
processor and the debugger.
Bit 1 (W): Denotes whether the programmer can read a data throug h the Debug Comms Data
Register. If the device is busy W = 0, then the programmer must poll until W = 1.
Bit 0 (R): Denotes whether the progr ammer can send dat a from the Debug Comms Da ta Regi ster. If R
= 1, data previously placed there through the scan chain has not been collected by the device and so
the programmer must wait.
The write handshake is done by polling the Debug Comms Control Register until the R bit is cleared. Once
cleared, data can be written to the Debug Comms Data Register.
Table 13-18. Reset TAP Controller and Go to Select-DR-Scan
TDI TMS TAP Controller State
X1
X1
X1
X1
X 1 Test-Logic Re set
X 0 Run-Test/Idle
Xt 1 Select-DR-Scan
TDI TDO
40
r/w Address 31 Data 0
Address
Decoder
Debug Comms Control Register
Debug Comms Data Register
32
5
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The read handshake is done by polling the Debug Comms Control Register un til the W bit is set. Once set, data
can be read in the Debug Comms Data Register.
13.3.4 Device Operations
Several commands on the Flash memory are available. These commands are summarized in Table 13-3 on page
89. Commands are run by the programmer through the serial interface that is reading and writing the Debug
Comms Registers.
13.3.4.1 Flash Read Command
This command is used to rea d the Flash conte nts. The me mory map is accessible throu gh this command. Memo ry
is seen as an array of words (32-bit wi de) . Th e read comm and ca n start at an y valid address in the mem ory pla ne.
This address must be word-aligned. The address is automatically incremented.
13.3.4.2 Flash Write Command
This command is used to write the Flash contents. The address transmitted must be a valid Flash address in the
memory plane.
The Flash memory plane is organized into several pages. Data to be written is stored in a load buffer that
corresponds to a Flash memory page. The load buffer is automatically flushed to the Flash:
before access to any page than the current one
at the end of the number of words transmitted
The Write Page command (WP) is optimized for consecutive writes. Write handshaking can be chained; an
internal address buffer is automatically increased.
Flash Write Page and Lock command (WPL) is equivalent to the Flash Write Command. However, the lock bit is
automatically set at the end of the Flash write operation. As a lock region is composed of several pages, the
programmer writes to the first pages of the lock region using Flash write commands and writes to the last page of
the lock region using a Flash write and lock command.
Table 13-19. Read Command
Read/Write DR Data
Write (Number of W ords to Read) << 16 | READ
Write Address
Read Memory [address]
Read Memory [address+4]
... ...
Read Memory [address+(Number of Words to Read - 1)* 4]
Table 13-20. Write Command
Read/Write DR Data
Write (Number of Words to Write) << 16 | (WP or WPL or EWP or EWPL)
Write Address
Write Memory [address]
Write Memory [address+4]
Write Memory [address+8]
Write Memory [address+(Number of Words to Write - 1)* 4]
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Flash Erase Page and Write command (EWP) is equivalent to the Flash Write Command. However, before
programming the load buffer, the page is erased.
Flash Erase Page and Write the Lock command (EWPL) combines EWP and WPL commands.
13.3.4.3 Flash Full Erase Command
This command is used to erase the Flash memory planes.
All lock bits must be deactivated before using the Full Erase command. This can be done by using the CLB
command.
13.3.4.4 Flash Lock Commands
Lock bits can be set using WPL or EWPL commands. They can also be set by using the Set Lock command
(SLB). With this command, several lock bits can be activated at the same time. Bit 0 of Bit Mask corresponds to
the first lock bit and so on.
In the same way, the Clear Lock command (CLB) is used to clear lock bits. All the lock bits can also be cleared by
the EA command.
Lock bits can be read using Get Lock Bit command (GLB). When a bit set in the Bit Mask is returned, then t he
corresponding lock bit is active.
13.3.4.5 Flash General-purpose NVM Commands
General-purpose NVM bits ( GP NVM) can be set with th e Set GPNVM command (SGPB). Usin g this command,
several GP NVM bits can be activated at the same time. Bit 0 of Bit Mask corresponds to the first GPNVM bit and
so on.
In the same way, the Clear GPNVM command (CGPB) is used to clear GP NVM bits. All the general-purpose
NVM bits are also cleared by the EA command.
Table 13-21. Full Erase Command
Read/Write DR Dat a
Write EA
Table 13-22. Set and Clear Lock Bit Command
Read/Write DR Data
Writ e SLB or CLB
Write Bit Mask
Table 13-23. Get Lock Bit Command
Read/Write DR Data
Write GLB
Read Bit Mask
Table 13-24. Set and Clear General-pu rpose NVM Bit Command
Read/Write DR Data
Write SGPB or CGPB
Write Bit Mask
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GP NVM bits can be read using Get GPNVM Bit command (GGPB). When a bit set in the Bit Mask is returned,
then the corresponding GPNVM bit is set.
13.3.4.6 Flash Security Bit Command
Security bits can be set using Set Security Bit command (SSE). Once the security bit is active, the Fast Flash
programming is disable d. No oth er command can be run. Only an event on the Erase pin can erase the security bit
once the contents of the Flash have been erased.
Once the security bit is set, it is not possible to access FFPI. The only way to erase the security bit is to erase the
Flash.
In order to erase the Flash, the user must perform the following:
Power-off the chip
Power-on the chip with TST = 0
Assert Erase during a period of more than 220 ms
Power-off the chip
Then it is possible to return to FFPI mode and check that Flash is erased.
13.3.4.7 Memory Write Command
This command is used to perform a write access to any memory location.
The Memory Write command (WRAM) is optimized for consecutive writes. An internal address buffer is
automatically increased.
Table 13-25. Get General-p urpose NVM Bit Command
Read/Write DR Data
Write GGPB
Read Bit Mask
Table 13-26. Set Security Bit Command
Read/Write DR Data
Write SSE
Table 13-27. Write Command
Read/Write DR Dat a
Write (Number of Words to Writ e) << 16 | (WRAM)
Write Address
Write Memory [address]
Write Memory [address+4]
Write Memory [address+8]
Write Memory [address+(Number of Words to Write - 1)* 4]
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13.3.4.8 Get Version Command
The Get Version (GVE) command retrieves the ver sio n of the F FPI inte rfa ce .
Table 13-28. Get Version Command
Read/Write DR Data
Write GVE
Read Version
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14. Reset Controller (RSTC)
14.1 Description
The Reset Controller (RSTC), based on power-on reset cells, handles all the resets of the system without any
external components. It reports which reset occurred last.
The Reset Controller also drives independently or simultaneously the external reset and the peripheral and
processor resets.
A brownout detection is also available to prevent the processor from falling into an unpredictable state.
14.2 Block Diagram
Figure 14-1. Reset Controller Block Diagram
NRST
Startup
Counter
proc_nreset
wd_fault
periph_nreset
backup_neset
SLCK
Reset
State
Manager
Reset Controller
rstc_irq
NRST
Manager
exter_nreset
nrst_out
Backup Supply
POR
Main Supply
POR
WDRPROC
user_reset
brown_out
bod_rst_en Brownout
Manager bod_reset
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14.3 Functional Description
14.3.1 Reset Controller Overview
The Reset Controller is made up of an NRST Manag er, a Browno ut Manager, a Star tup Counter an d a Reset State
Manager. It runs at Slow Clock and generates the following reset signals:
proc_nreset: Processor reset line. It also resets the Watchdog Timer.
backup_nreset: Affects all the peripherals powered by VDDBU.
periph_nreset: Affects the whole set of embedded peripherals.
nrst_out: Drives the NRST pin.
These reset signals are asserted by the Reset Controller, either on external events or on software action. The
Reset State Manager controls the gener ation o f reset signals and provid es a signal to the NRST Manag er when an
assertion of the NRST pin is required.
The NRST Manager shapes the NRST assertion during a programmable time, thus controlling external device
resets.
The startup counter waits for the complete crystal oscillator startup. The wait delay is given by the crystal oscillator
startup time maximum value that can be found in the section Crystal Oscillator Characteristics in the Electrical
Characteristics section of the product data sheet.
The Reset Controller Mode Register (RST C_MR), allowing the con figuration of the Rese t Controller, is power ed
with VDDBU, so that its configuration is saved as long as VDDBU is on.
14.3.2 NRST Manager
The NRST Manager samples the NRST input pin and drives this pin low when required by the Reset State
Manager. Figure 14-2 shows the block diagram of the NRST Manager.
Figure 14-2. NRST Manager
External Reset Timer
URSTS
URSTEN
ERSTL
exter_nreset
URSTIEN
RSTC_MR
RSTC_MR
RSTC_MR
RSTC_SR
NRSTL
nrst_out
NRST
rstc_irq
Other
interrupt
sources
user_reset
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14.3.2.1 NRST Signal or Interrupt
The NRST Manager samples the NRST pin at Slow Clock speed. When the line is detected low, a User Reset is
reported to the Reset State Manager.
However, the NRST Manager can be programmed to not trigger a reset when an assertion of NRST occurs.
Writing the bit URSTEN at 0 in RSTC_MR disables the User Reset trigger.
The level of the pin NRST can be read at any time in the bit NRSTL (NRST level) in RSTC_SR. As soon as the pin
NRST is asserted, the bit URSTS in RSTC_SR is set. This bit clears only when RSTC_SR is read.
The Reset Controller ca n also be pr ogrammed to gen erate an in terrup t inste ad of gene ratin g a reset. To do so, th e
bit URSTIEN in RSTC_MR must be written at 1.
14.3.2.2 NRST External Reset Control
The Reset State Manager asserts the signal ext_nreset to assert the NRST pin. When this occurs, the “nrst_out”
signal is driven lo w by the NRST Manager for a time prog ramme d by the field ERSTL in RSTC_ MR. This assertion
duration, named EXTERNAL_RESET_LENGTH, lasts 2(ERSTL+1) Slow Clock cycles. This gives the approximate
duration of an assertion between 60 µs and 2 seconds. Note that ERSTL at 0 defines a two-cycle duration for the
NRST pulse.
This feature allows the Reset Controller to shape the NRST pin level, and thus to guarantee that the NRST line is
driven low for a time compliant with potential external devices connected on the system reset.
As the field is within RSTC_MR, which is backed-u p, this field can be used to shape th e system powe r-up reset for
devices requiring a longer startup time than the Slow Clock Oscillator.
14.3.3 Brownout Manager
Brownout detection prevents the processor from falling into an unpredictable st ate if the power supply drop s below
a certain level. When VDDCORE drop s below the brownout threshold, the brownout manager requests a brownout
reset by asserting the bod_reset signal.
The programmer can disable the brownout reset by setting low the bod_ rst_en input signal, i.e., by locking the
corresponding general-purpose NVM bit in the Flash. When the brownout reset is disabled, no reset is performed.
Instead, the brownout detection is reported in the bit BODSTS of RSTC_SR. BODSTS is set and clears only when
RSTC_SR is read.
The bit BODSTS can trigger an interrupt if the bit BODIEN is set in the RSTC_MR.
At factory, the brownout reset is disabled.
Figure 14-3. Brownout Manager
rstc_irq
brown_out
bod_reset
bod_rst_en
BODIEN
RSTC_MR
BODSTS
RSTC_SR
Other
interrupt
sources
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14.3.4 Reset States
The Reset State Manager handles the different reset sources and generates the internal rese t signals. It reports
the reset status in the field RSTTYP of the Status Register (RSTC_SR). The update of the field RSTTYP is
performed when the processor reset is released.
14.3.4.1 General Reset
A general reset occurs when VDDBU and VDDCORE are powered on. The backup supply POR cell output rises
and is filtered with a Startup Counter, which operates at Slow Clock. The purpose of this counter is to make sure
the Slow Clock oscillator is stable before starting up the device. The length of startup time is hardcoded to comply
with the Slow Clock Oscillator startup time.
After this time , the pr ocess or c lock is release d at Slow Clo ck and all the other signals remain valid for 3 cycles for
proper processor and lo gic reset. Then, all the reset signals are released and the field RSTTYP in RSTC_ SR
reports a General Reset. As the RSTC_MR is reset, the NRST line rises 2 cycles after the backup_nreset, as
ERSTL defaults at value 0x0.
When VDDBU is detected low by the Backup Supply POR Cell, all resets signals are immediately asserted, even if
the Main Supply POR Cell does not report a Main Supply shutdown.
VDDBU only activates the backup_nreset signal.
The backup_nreset must be released so that any other reset can be generated by VDDCORE (Main Supply POR
output).
Figure 14-4 shows how the General Reset affects the reset signals.
Figure 14-4. General Reset State
SLCK
periph_nreset
proc_nreset
Backup Supply
POR output
NRST
(nrst_out)
EXTERNAL RESET LENGTH
= 2 cycles
Startup Time
MCK
Processor Startup
= 3 cycles
backup_nreset
Any
Freq.
RSTTYP XXX 0x0 = General Reset XXX
Main Supply
POR output
BMS Sampling
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14.3.4.2 Wake-up Reset
The Wake-up Reset occurs when the Main Supply is down. When the Main Supply POR output is active, all the
reset signals are asserted except backup_nreset. When the Main Supply powers up, the POR output is
resynchronized on Slow Clock. The processor clock is then re-enabled during 3 Slow Clock cycles, depending on
the requirements of the ARM processor.
At the end of this delay, the processor and other reset signals rise. The field RSTTYP in RSTC_SR is updated to
report a Wake-up Reset.
The “nrst_out” remains asserted for EXTERNAL_RESET _LENGTH cycles. As RSTC_MR is backed-up, the
programmed number of cycles is applicable.
When the Main Supply is detected falling, the reset signals are immediately asserted. This transition is
synchronous with the output of the Main Supply POR.
Figure 14-5. Wake-up State
SLCK
periph_nreset
proc_nreset
Main Supply
POR output
NRST
(nrst_out)
EXTERNAL RESET LENGTH
= 4 cycles (ERSTL = 1)
MCK
Processor Startup
= 3 cycles
backup_nreset
Any
Freq.
Resynch.
2 cycles
RSTTYP XXX 0x1 = WakeUp Reset XXX
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14.3.4.3 User Reset
The User Reset is entered when a low level is detected on the NRST pin and the bit URSTEN in RSTC_MR is at 1.
The NRST input signal is resynchronized with SLCK to insure proper behavior of the system.
The User Reset is entered as soon as a low level is detected on NRST. The Processor Reset and the Peripheral
Reset are asser te d .
The User Reset is left when NRST rises, after a two-cycle resynchronization time and a 3-cycle processor startup.
The processor clock is re-enabled as soon as NRST is confirmed high.
When the processor reset signal is released, the RSTTYP field of the Status Register (RSTC_SR) is loaded with
the value 0x4, indicating a User Reset.
The NRST Manager guarantees that the NRST line is asserted for EXTERNAL_RESET_LENGTH Slow Clock
cycles, as programmed in the field ERSTL. However, if NRST does not rise after EXTERNAL_RESET_LENGTH
because it is driven low externally, the internal reset lines remain asserted until NRST actually rises.
Figure 14-6. User Reset State
SLCK
periph_nreset
proc_nreset
NRST
NRST
(nrst_out)
>= EXTERNAL RESET LENGTH
MCK
Processor Startup
= 3 cycles
Any
Freq.
Resynch.
2 cycles
RSTTYP Any XXX
Resynch.
2 cycles
0x4 = User Reset
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14.3.4.4 Brownout Reset
When the brown_out/bod_reset signal is asserted, the Reset State Manager immediately enters the Brownout
Reset. In this state, the processor, the peripheral and the external reset lines are asserted.
The Brownout Reset is left 3 Slow Clock cycles after the rising edge of brown_out/bod_reset after a two-cycle
resynchronization. An external reset is also triggered.
When the processor reset is released, the field RSTTYP in RSTC_SR is loaded with the value 0x5, thus indicating
that the last reset is a Brownout Reset.
Figure 14-7. Bro wnou t Reset State
SLCK
periph_nreset
proc_nreset
brown_out
or bod_reset
NRST
(nrst_out)
EXTERNAL RESET LENGTH
8 cycles (ERSTL=2)
MCK
Processor Startup
= 3 cycles
Any
Freq.
RSTTYP Any XXX 0x5 = Brownout Reset
Resynch.
2 cycles
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14.3.4.5 Software Reset
The Reset Controller offers several commands used to assert the different reset signals. Th ese commands are
performed by writing the Control Register (RSTC_CR) with the following bits at 1:
PROCRST: Writing PROCRST at 1 resets the processor and the watchdog timer.
PERRST: Writing PERRST at 1 resets all the embedded peripherals, including the memory system, and, in
particular, the Remap Command. The Peripheral Reset is generally used for debug purposes.
Except for Debug purposes, PERRST must always be used in conjunction with PROCRST (PERRST and
PROCRST set both at 1 simultaneously.)
EXTRST: Writing EXTRST at 1 asserts low the NRST pin during a time defined by the field ERSTL in the
Mode Register (RSTC_MR).
The software reset is entered if at least one of these bits is set by the software. All these commands can be
performed independently or simultaneously. The software reset lasts 3 Slow Clock cycles.
The internal reset signals are asserted as soon as the register write is performed. This is detected on the Master
Clock (MCK). They are released when the software reset is left, i.e., synchronously to SLCK.
If EXTRST is set, the nrst_out signal is asserted depending on the pro gramming of the field ERSTL. However, the
resulting falling edge on NRST does not lead to a User Reset.
If and only if the PROCRST bit is set, the Reset Controller reports the software status in the field RSTTYP of the
Status Register (RSTC_SR). Other Software Resets are not reported in RSTTYP.
As soon as a softw are operatio n is detected , the bit SRCMP (Software Reset Command in Progress) is set in the
Status Register (RSTC_SR). It is cleared as soon as the software reset is left. No other software reset can be
performed while the SRCMP bit is set, and writing any value in RSTC_CR has no effect.
Figure 14-8. Software Reset
SLCK
periph_nreset
if PERRST=1
proc_nreset
if PROCRST=1
Write RSTC_CR
NRST
(nrst_out)
if EXTRST=1 EXTERNAL RESET LENGTH
8 cycles (ERSTL=2)
MCK
Processor Startup
= 3 cycles
Any
Freq.
RSTTYP Any XXX 0x3 = Software Reset
Resynch.
1 cycle
SRCMP in RSTC_SR
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14.3.4.6 Watchdog Reset
The Watchdog Reset is entered when a watchdog fault occurs. This state lasts 3 Slow Clock cycles.
When in Watchdog Reset, assertion of the reset signals depends on the WDRPROC bit in WDT_MR:
If WDRPROC is 0, the Processor Reset and the Peripheral Reset are asserted. The NRST line is also
asserted, depending on the programming of the field ERSTL. However, the resulting low level on NRST
does not result in a User Reset state.
If WDRPROC = 1, only the processor reset is asserted.
The Watchdog Timer is reset by the proc_nreset signal. As the watchdog fault always causes a processor reset if
WDRSTEN is set, the Watchdog Timer is always reset after a Watchdog Reset, and the Watchdog is enabled by
default and with a period set to a maximum.
When the WDRSTEN in WDT_MR bit is reset, the watchdog fault has no impact on the reset controller.
Figure 14-9. Watchdog Reset
14.3.5 Reset State Priorities
The Reset State Manager manages the following priorities between the different reset sources, given in
descending order:
Backup Reset
Wake-up Reset
Brownout Reset
Watchdog Reset
Software Reset
User Reset
Only if
WDRPROC = 0
SLCK
periph_nreset
proc_nreset
wd_fault
NRST
(nrst_out)
EXTERNAL RESET LENGTH
8 cycles (ERSTL=2)
MCK
Processor Startup
= 3 cycles
Any
Freq.
RSTTYP Any XXX 0x2 = Watchdog Reset
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Particular cases are listed below:
When in User Reset:
A watchdog event is impossible because the W atchdog T imer is being reset by the proc_nrese t signal.
A software reset is impossible, since the processor reset is being activated.
When in Software Reset:
A watchdog event ha s pr ior ity over the current state.
The NRST has no effect.
When in Watchdog Reset:
The processor reset is active and so a Software Reset cannot be programmed.
A User Reset cannot be entered.
14.3.6 Reset Controller Status Register
The Reset Controller status register (RSTC_SR) provides several status fields:
RSTTYP field: This field gives the type of the last reset, as explained in previous sections.
SRCMP bit: This field indicates that a Software Reset Command is in progress and that no further software
reset should be p er fo rmed u ntil th e e nd o f the cu rr en t o ne. This b it is a utoma tical ly clea re d at the end of th e
current software reset.
NRSTL bit: The NRSTL bit of the Status Register gives the level of the NRST pin sampled on each MCK
rising edge.
URSTS bit: A high-to-low transition of the NRST pin sets the URSTS bit of the RSTC_SR. This transition is
also detected on the Master Clock (MCK) rising edge (see Figure 14-10). If the User Reset is disabled
(URSTEN = 0) and if the interruption is enabled by the URSTIEN bit in the RSTC_MR, the URSTS bit
triggers an interrupt. Reading the RSTC_SR status register resets the URSTS bit and clears the interrupt.
BODSTS bit: This bit indicates a brownout detection when the brownout reset i s disabled (bod_rst_e n = 0). It
triggers an interrupt if the bit BODIEN in the RSTC_MR enables the interru pt. Readi ng the RSTC_SR r esets
the BODSTS bit and clears the interrupt.
Figure 14-10. Reset Controller Status and Interrupt
MCK
NRST
NRSTL
2 cycle
resynchronization 2 cycle
resynchronization
URSTS
read
RSTC_SR
Peripheral Access
rstc_irq
if (URSTEN = 0) and
(URSTIEN = 1)
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14.4 Reset Controller (RSTC) User Interface
Note: 1. The reset value of RSTC_SR either reports a General Reset or a Wake-up Reset depending on last rising power supply.
Table 14-1. Register Mapping
Offset Register Name Access Reset Back-up Reset
0x00 Control Register RSTC_CR Write-only – –
0x04 Status Register RSTC_SR Read-only 0x0000_0001 0x0000_0000
0x08 Mode Register RSTC_MR Read/Write – 0x0000_0000
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14.4.1 Reset Controller Control Register
Name: RSTC_CR
Address: 0xFFFFFD00
Access: Write-only
• PROCRST: Processor Reset
0: No effect.
1: If KEY is correct, resets the processor.
• PERRST: Peripheral Reset
0: No effect.
1: If KEY is correct, resets the peripherals.
• EXTRST: External Reset
0: No effect.
1: If KEY is correct, asserts the NRST pin.
• KEY: Password
Should be written at value 0xA5. Writing any other value in this field aborts the write operation.
31 30 29 28 27 26 25 24
KEY
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––––– –
76543210
––––EXTRSTPERRST–PROCRST
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14.4.2 Reset Controller Status Register
Name: RSTC_SR
Address: 0xFFFFFD04
Access: Read-only
• URSTS: User Reset Status
0: No high-to-low edge on NRST happened since the last read of RSTC_SR.
1: At least one high-to-low transition of NRST has been detected sin ce the last read of RSTC_SR.
• BODSTS: Brownout Detection Status
0: No brownout high-to-low transition happened since the last read of RSTC_SR.
1: A brownout high-to-low transition has been detected since the last read of RSTC_SR.
• RSTTYP: Reset Type
Reports the cause of the last processor reset. Reading this RSTC_SR does not reset this field.
• NRSTL: NRST Pin Level
Registers the NRST Pin Level at Master Clock (MCK).
• SRCMP: Software Reset Command in Progress
0: No software command is being perfor med b y the reset con troller. The reset controller is rea dy for a so ftware co mmand.
1: A software reset command is being performed by the reset controller. The reset controller is busy.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––SRCMPNRSTL
15 14 13 12 11 10 9 8
––––– RSTTYP
76543210
–––––––BODSTSURSTS
RSTTYP Reset Type Comment s
0 0 0 General Reset Both VDDCORE and VDDBU rising
0 0 1 Wake Up Reset VDDCORE rising
0 1 0 Watchdog Reset Watchdog fault occurred
0 1 1 Software Reset Processor reset required by the software
1 0 0 User Reset NRST pin detected low
1 0 1 Brownout Reset Brownout reset occurred
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14.4.3 Reset Controller Mode Register
Name: RSTC_MR
Address: 0xFFFFFD08
Access: Read/Write
• URSTEN: User Reset Enable
0: The detection of a low level on the pin NRST does not generate a User Reset.
1: The detection of a low level on the pin NRST triggers a User Reset.
• URSTIEN: User Reset Interrupt Enable
0: USRTS bit in RSTC_SR at 1 has no effect on rstc_irq.
1: USRTS bit in RSTC_SR at 1 asserts rstc_irq if URSTEN = 0.
• BODIEN: Brownout Detection Interrupt Enable
0: BODSTS bit in RSTC_SR at 1 has no effect on rstc_irq.
1: BODSTS bit in RSTC_SR at 1 asserts rstc_irq.
• ERSTL: Exte rna l Re se t Le n gth
This field defines the external reset length. The external reset is asserted during a time of 2(ERSTL+1) Slow Clock cycles .
This allows assertion duration to be programmed between 60 µs and 2 seconds.
• KEY: Password
Should be written at value 0xA5. Writing any other value in this field aborts the write operation.
31 30 29 28 27 26 25 24
KEY
23 22 21 20 19 18 17 16
–––––––BODIEN
15 14 13 12 11 10 9 8
–––– ERSTL
76543210
– – URSTIEN – – – URSTEN
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15. Real-time Timer (RTT)
15.1 Description
The Real-time Timer is built around a 32-bit coun ter and used to count elapsed seconds. It generates a perio dic
interrupt and/or triggers an alarm on a programmed value.
15.2 Block Diagram
Figure 15-1. Real-time Timer
15.3 Functional Description
The Real-time Timer is used to count elapsed seconds. It is built around a 32-bit counter fed by Slow Clock divided
by a programmable 16-bit value. The value can be p rogrammed in the field RTPRES of the Real-time Mode
Register (RTT _ MR ).
Programming RTPRES a t 0x0000800 0 corresponds to feeding the re al -time counter with a 1 Hz sign al (if the Slow
Clock is 32768 Hz). The 32-bit counter can count up to 232 seconds, corresponding to more than 136 years, then
roll over to 0.
The Real-time Timer can also be used as a free-running timer with a lower time-base. The best accuracy is
achieved by writing RTPRES to 3. Programming RTPRES to 1 or 2 is possible, but may result in losing status
events because the status register is cleared two Slow Clock cycles after read. Thus if the RTT is configured to
trigger an interrupt, the interrupt occurs during 2 Slow Clock cycles after reading RTT_SR. To prevent several
executions of the interrupt handler, the inter rupt must be disab led in the interrupt han dler and re-e nabled when th e
status register is clear.
SLCK
RTPRES
RTTINC
ALMS
16-bit
Divider
32-bit
Counter
ALMV =
CRTV
RTT_MR
RTT_VR
RTT_AR
RTT_SR
RTTINCIEN
RTT_MR
0
10
ALMIEN
rtt_int
RTT_MR
set
set
RTT_SR
read
RTT_SR
reset
reset
RTT_MR
reload
rtt_alarm
RTTRST
RTT_MR
RTTRST
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The Real-time Timer value (CRTV) can be read at any time in the register RTT_VR (R eal-time Value Register). As
this value can be updated a synchronously from the Master Clock, it is advisable to read this register twice at the
same value to improve accuracy of the returned value.
The current value of the co unter is compar ed with the value written in the a larm r egister RTT_ AR (Rea l-time Alarm
Register). If the counter value matches the alarm, the bit ALMS in RTT_SR is set. The alarm register is set to its
maximum value, corresponding to 0xFFFF_FFFF, after a reset.
The bit RTTINC in RTT_SR is set each time the Real-time Timer counter is incremented. This bit can be used to
start a periodic interrupt, th e period being one second when the RT PRES is programmed with 0x8000 and Slow
Clock equal to 32768 Hz.
Reading the RTT_SR status register resets the RTTINC and ALMS fields.
Writing the bit RTTRST in RTT_MR immediately reloads and restarts the clock divider with the new programmed
value. This also resets the 32-bit counter.
Note: Because of the asynchronism between the Slow Clock (SCLK) and the Syste m Clock (MCK):
1) The restart of the counter and the reset of the RTT_VR current value register is effective only 2 slow clock cycles
after the write of the RTTRST bit in the RTT_MR.
2) The status register flags reset is taken into account only 2 slow clock cycles after the read of the RTT_SR (Status
Register).
Figure 15-2. RTT Counting
Prescaler
ALMVALMV-10 ALMV+1
0
RTPRES - 1
RTT
APB cycle
read RTT_SR
ALMS (RTT_SR)
APB Interface
MCK
RTTINC (RTT_SR)
ALMV+2 ALMV+3
...
APB cycle
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15.4 Real-time Timer (RTT) User Interface
Table 15-1. Register Mapping
Offset Register Name Access Reset
0x00 Mode Register RTT_MR Read/Write 0x0000_8000
0x04 Alarm Register RTT_AR Read/Write 0xFFFF_FFFF
0x08 Value Register RTT_VR Read-only 0x0000_0000
0x0C Status Register RTT_SR Read-only 0x0000_0000
119
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15.4.1 Real-time Timer Mode Register
Name: RTT_MR
Address: 0xFFFFFD20
Access: Read/Write
• RTPRES: Real- ti me Timer Prescale r Valu e
Defines the number of SLCK periods required to increment the Real-time timer. RTPRES is defined as follows:
RTPRES = 0: The prescaler period is equal to 216.
RTPRES ≠ 0: The prescaler period is equal to RTPRES.
• ALMIEN: Alarm Interrupt Enable
0: The bit ALMS in RTT_SR has no effect on interrupt.
1: The bit ALMS in RTT_SR asserts interrupt.
• RTTINCIEN: Real-time Timer Increment Interrupt Enable
0: The bit RTTINC in RTT_SR has no effect on interrupt.
1: The bit RTTINC in RTT_SR asserts interrupt.
• RTTRST: Real-time Timer Restart
1: Reloads and restarts the clock divider with the new programmed value. This also resets th e 32-bit counter.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
–––––RTTRSTRTTINCIENALMIEN
15 14 13 12 11 10 9 8
RTPRES
76543210
RTPRES
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15.4.2 Real-time Timer Alarm Register
Name: RTT_AR
Address: 0xFFFFFD24
Access: Read/Write
• ALMV: Alarm Value
Defines the alarm value (ALMV+1) compared with the Real-time Timer.
31 30 29 28 27 26 25 24
ALMV
23 22 21 20 19 18 17 16
ALMV
15 14 13 12 11 10 9 8
ALMV
76543210
ALMV
121
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15.4.3 Real-time Timer Value Register
Name: RTT_VR
Address: 0xFFFFFD28
Access: Read-only
• CRTV: Current Real-time Value
Returns the curre n t valu e of the Real- tim e Time r.
31 30 29 28 27 26 25 24
CRTV
23 22 21 20 19 18 17 16
CRTV
15 14 13 12 11 10 9 8
CRTV
76543210
CRTV
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15.4.4 Real-time Timer Status Register
Name: RTT_SR
Address: 0xFFFFFD2C
Access: Read-only
• ALMS: Real-time Alarm Status
0: The Real-time Alarm has not occurred since the last read of RTT_SR.
1: The Real-time Alarm occurred since the last read of RTT_SR.
• RTTINC: Re al -ti me Timer Increme nt
0: The Real-time Timer has not been incremented since the last read of the RTT_SR.
1: The Real-time T ime r ha s been incr em e nt ed since the last read of the RTT_SR.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
––––––RTTINCALMS
123
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16. Periodic Interval Timer (PIT)
16.1 Description
The Periodic In terval Timer (PIT) provid es the operating system ’s scheduler interrupt. It is designed to offer
maximum accuracy and efficient management, even for systems with long response time.
16.2 Block Diagram
Figure 16-1. Periodic Interval Timer
20-bit
Counter
MCK/16
PIV
PIT_MR
CPIV PIT_PIVR PICNT
12-bit
Adder
0
0
read PIT_PIVR
CPIV PICNT
PIT_PIIR
PITS
PIT_SR
set
reset
PITIEN
PIT_MR
pit_irq
1
0
10
MCK
Prescaler
= ?
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16.3 Functional Description
The Periodic Interval Timer aims at providing periodic interrupts for use by operating systems.
The PIT provides a programmable overflow counter and a reset-on-read feature. It is built around two counter s: a
20-bit CPIV counter and a 12-bit PICNT counter. Both counters work at Master Clock /16.
The first 20-bit CPIV counter increments from 0 up to a programmable overflow value set in the field PIV of the
Mode Register (PIT_MR). When the counter CPIV reaches this value, it resets to 0 and increments the Periodic
Interval Counter, PICNT. The status bit PITS in the Status Register (PIT_SR) rises and triggers an interrupt,
provided the interrupt is enabled (PITIEN in PIT_MR).
Writing a new PIV value in PIT_MR does not reset/restart the counters.
When CPIV and PICNT values are obtained by reading the Periodic Interval Value Register (PIT_PIVR), the
overflow counter (PICNT) is reset and the PITS is cleared, thus acknowledging the interrupt. The value of PICNT
gives the number of periodic intervals elapsed since the last read of PIT_PIVR.
When CPIV and PICNT values are obtained by reading the Per iodic Interval Image Register (PIT _PIIR), there is
no effect on the counters CPIV and PICNT, nor on the bit PITS. For example, a profiler can read PIT_PIIR without
clearing any pe nd in g int er rupt , w here as a time r interr u pt cle ar s the inte rr upt by re ad in g PIT _P IVR.
The PIT may be enable d/disabled using the PITEN bit in the PIT_MR (disable d on reset). The PITEN bit only
becomes effective when the CPIV value is 0. Figure 16-2 illustrates the PIT counting. After the PIT Enable bit is
reset (PITEN= 0), the CPIV goes on counting until the PIV value is reached, and is then reset. PIT restarts
counting, only if the PITEN is set again.
The PIT is stopped when the core enters debug state.
Figure 16-2. Enabling/Disabling PIT with PITEN
MCK Prescaler
PIVPIV - 10
PITEN
10
0
15
CPIV 1
restarts MCK Prescaler
01
APB cycle
read PIT_PIVR
0
PICNT
PITS (PIT_SR)
MCK
APB Interface
APB cycle
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16.4 Periodic Interval Timer (PIT) User Interface
Table 16-1. Register Mapping
Offset Register Name Access Reset
0x00 Mode Register PIT_MR Read/Write 0x000F_FFFF
0x04 Status Register PIT_SR Read-only 0x0000_0000
0x08 Periodic Interval Value Register PIT_PIVR Read-only 0x0000_0000
0x0C Periodic Interval Image Register PIT_PIIR Read-only 0x0000_0000
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16.4.1 Periodic Interval Timer Mode Register
Name: PIT_MR
Address: 0xFFFFFD30
Access: Read/Write
• PIV: Periodic Interval Value
Defines the value compared with the primary 20-bit counter of the Periodic Interval Timer (CPIV). The period is equal to
(PIV + 1).
• PITEN: Period Interval Timer Enabled
0: The Periodic Interval Timer is disabled when the PIV value is reached.
1: The Periodic Interval Timer is enabled.
• PITIEN: Periodic Interval Timer Interrupt Enable
0: The bit PITS in PIT_SR has no effect on interrupt.
1: The bit PITS in PIT_SR asserts interrupt.
31 30 29 28 27 26 25 24
––––––PITIENPITEN
23 22 21 20 19 18 17 16
–––– PIV
15 14 13 12 11 10 9 8
PIV
76543210
PIV
127
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16.4.2 Periodic Interval Timer Status Register
Name: PIT_SR
Address: 0xFFFFFD34
Access: Read-only
• PITS: Periodic Interval Timer Status
0: The Periodic Inte rva l time r ha s no t re ach e d PIV sinc e th e last rea d of PIT_PIVR.
1: The Periodic Inte rva l time r ha s re ac he d PIV sin ce th e last rea d of PIT_ PIVR .
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––PITS
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16.4.3 Periodic Interval Timer Value Register
Name: PIT_PIVR
Address: 0xFFFFFD38
Access: Read-only
Reading this register clears PITS in PIT_SR.
• CPIV: Current Periodic Interval Value
Returns the current value of the periodic interval timer.
• PICNT: Periodic Interval Counter
Returns the num be r of occu rr en ce s of pe rio d ic interva l s sinc e th e last rea d of PIT_PIVR .
31 30 29 28 27 26 25 24
PICNT
23 22 21 20 19 18 17 16
PICNT CPIV
15 14 13 12 11 10 9 8
CPIV
76543210
CPIV
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16.4.4 Periodic Interval Timer Image Register
Name: PIT_PIIR
Address: 0xFFFFFD3C
Access: Read-only
• CPIV: Current Periodic Interval Value
Returns the current value of the periodic interval timer.
• PICNT: Periodic Interval Counter
Returns the num be r of occu rr en ce s of pe rio d ic interva l s sinc e th e last rea d of PIT_PIVR .
31 30 29 28 27 26 25 24
PICNT
23 22 21 20 19 18 17 16
PICNT CPIV
15 14 13 12 11 10 9 8
CPIV
76543210
CPIV
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17. Watch Dog Timer (WDT)
17.1 Description
The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. It
features a 12-bit down counter that allows a watchdog period of up to 16 seconds (slow clock at 32.768 kHz). It
can generate a general reset or a processor reset only. In addition, it can be stopped while the processor is in
debug mode or idle mode.
17.2 Block Diagram
Figure 17-1. Watchdog Timer Block Diagram
=0
10
set
reset
read WDT_SR
or
reset
wdt_fault
(to Reset Controller)
set
reset
WDFIEN
wdt_int
WDT_MR
SLCK
1/128
12-bit Down
Counter
Current
Value
WDD
WDT_MR
<= WDD
WDV
WDRSTT
WDT_MR
WDT_CR
reload
WDUNF
WDERR
reload
write WDT_MR
WDT_MR
WDRSTEN
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17.3 Functional Description
The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. It is
supplied with VDDCORE. It restarts with initial values on processor reset.
The Watchdog is built around a 12-bit down counter, which is loaded with the value defined in the field WDV of the
Mode Register (WDT_ MR). The Watchdog Timer uses the Slow Clock divided by 128 to establish the maximum
Watchdog period to be 16 seconds (with a typical Slow Clock of 32.768 kHz).
After a Processor Reset, the value of WDV is 0xFFF, corresponding to the maximum value of the counter with the
external reset generation enabled (field WDRSTEN at 1 after a Backup Reset). This means that a default
Watchdog is running at reset, i.e., at power-up. The user must either disable it (by setting the WDDIS bit in
WDT_MR) if he does not expect to use it or must reprogram it to meet the maximum Watchdog period the
application requires.
The Watchdog Mode Register (WDT_MR) can be written only once. Only a processor reset resets it. Writing the
WDT_MR reloads the timer with the newly programmed mode parameters.
In normal oper ation, the user reloads the Watchdog at regu lar intervals before the timer underflow occurs, b y
writing the Control Register (WDT_CR) with the bit WDRSTT to 1. T he Watchdog counter is then immediately
reloaded from WDT_MR and restarted, and th e Slow Clock 128 divider is re set and restarted. The WDT_CR is
write-protected. As a res ult, writing WDT_CR without th e correct hard-coded key has no effect. If an underflow
does occur, the “wdt_fault” signal to the Reset Controller is asserted if the bit WDRSTEN is set in the Mode
Register (WDT_MR). Moreover, the bit WDUNF is set in the Watchdog Status Register (WDT_SR).
To prevent a software deadlock that continu ously triggers the Watchdog, the relo ad of the Watchdog m ust occur
while the Watchdog cou nter is within a window between 0 and WDD , WDD is defined in the WatchDog Mode
Register WDT_MR.
Any attempt to restart the Watchdog while the Watchdog counter is between WDV and WDD results in a
Watchdog error, even if the Watchdog is disabled. The bit WDERR is updated in the WDT_SR and the “wdt_fault”
signal to the Reset Controller is asserted.
Note that this feature can be disabled by progr amming a WDD value greater than or equal to the WDV value. In
such a configuration, restarting the Watchdog Timer is permitted in the whole range [0; WDV] and does not
generate an error. This is the default configuration on reset (the WDD and WDV values are equal).
The status bits WDUNF (Watch dog Unde rflow) and WDERR ( Watch dog Erro r) trigger an inter rupt, provide d the bit
WDFIEN is set in the mode register. The signal “wdt_fault” to the reset controller causes a Watchdog reset if the
WDRSTEN bit is set as already explained in the Reset Controller documentation. In this case, the processor and
the Watchdog Timer are reset, and the WDERR and WDUNF flags are reset.
If a reset is generated or if WDT_SR is read, the status bits are reset, the interrupt is cleared, and the “wdt_fault”
signal to the reset controller is deasserted.
Writing the WDT_MR reloads and restarts the down counter.
While the processor is in debug state or in idle mode, the counter may be stopped depending on the value
programmed for the bits WDIDLEHLT and WDDBGHLT in the WDT_MR.
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Figure 17-2 . Watchdog Behavior
0
WDV
WDD
WDT_CR = WDRSTT
Watchdog
Fault
Normal behavior
Watchdog Error Watchdog Underflow
FFF if WDRSTEN is 1
if WDRSTEN is 0
Forbidden
Window
Permitted
Window
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17.4 Watchdog Timer (WDT) User Interface
Table 17-1. Register Mapping
Offset Register Name Access Reset
0x00 Control Register WDT_CR Write-only –
0x04 Mode Register WDT_MR Read-write Once 0x3FFF_2FFF
0x08 Status Register WDT_SR Read-only 0x0000_0000
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17.4.1 Watchdog Timer Control Register
Name: WDT_CR
Address: 0xFFFFFD40
Access: Write-only
• WDRSTT: Watchdog Restart
0: No effect.
1: Restarts the Watchdog.
• KEY: Password
Should be written at value 0xA5. Writing any other value in this field aborts the write operation.
31 30 29 28 27 26 25 24
KEY
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––WDRSTT
135
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17.4.2 Watchdog Timer Mode Register
Name: WDT_MR
Address: 0xFFFFFD44
Access: Read-write Once
• WDV: Watchdog Counter Value
Defines the value loaded in the 12-bit Watchdog Counter.
• WDFIEN: Watchdog Fault Interrupt Enable
0: A Watchdog fault (underflow or error) has no effect on interrupt.
1: A Watchdog fault (underflow or error) asserts interrupt.
• WDRSTEN: Watchdog Reset Enable
0: A Watchdog fault (underflow or error) has no effect on the resets.
1: A Watchdog fault (underflow or error) triggers a Watchdog reset.
• WDRPROC: Watchdog Reset Processor
0: If WDRSTEN is 1, a Watchdog fault (underflow or erro r) activates all resets.
1: If WDRSTEN is 1, a Watchdog fault (underflow or error) activates the processor reset.
• WDD: Watchdog Delta Value
Defines the permitted range for reloading the Watchdog Timer.
If the Watchdog Timer value is less than or equal to WDD, writing WDT_CR with WDRSTT = 1 restarts the timer.
If the Watchdog Timer value is greater than WDD, writing WDT_CR with WDRSTT = 1 causes a Watchdog error.
• WDDBGHLT: Watchdog Debug Halt
0: The Watchdog runs when the processor is in debug state.
1: The Watchdog stops when the processor is in debug state.
• WDIDLEHLT: Watchdog Idle Halt
0: The Watchdog runs when the system is in idle mode.
1: The Watchdog stops when the system is in idle state.
31 30 29 28 27 26 25 24
WDIDLEHLT WDDBGHLT WDD
23 22 21 20 19 18 17 16
WDD
15 14 13 12 11 10 9 8
WDDIS WDRPROC WDRSTEN WDFIEN WDV
76543210
WDV
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• WDDIS: Watchdog Disable
0: Enables the Watchdog Timer.
1: Disables the Watchdog Timer.
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17.4.3 Watchdog Timer Status Register
Name: WDT_SR
Address: 0xFFFFFD48
Access: Read-only
• WDUNF: Watchdog Underflow
0: No Watchdog underflow occurred since the last read of WDT_ SR.
1: At least one Watchdog underflow occurred since the last read of WDT_SR.
• WDERR: Watchdog Error
0: No Watchdog error occurred since the last read of WDT_SR.
1: At least one Watchdog error occurred since the last read of WDT_SR.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
––––––WDERRWDUNF
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18. Shutdown Controller (SHDWC)
18.1 Description
The Shutdown Controller controls the power supplies VDDIO and VDDCORE and the wake-up detection on
debounced input lines.
18.2 Block Diagram
Figure 18-1. Shutdown Controller Block Diagram
18.3 I/O Lines Description
18.4 Product Dependencies
18.4.1 Power Management
The Shutdown Controller is continuously clocked by Slow Clock. The Power Management Controller has no effect
on the behavior of the Shut do wn Con tro ller.
Shutdown
Wake-up
Shutdown
Output
Controller
SHDN
WKUP0
SHDW
WKMODE0
Shutdown Controller
RTT Alarm
RTTWKEN
SHDW_MR
SHDW_MR
SHDW_CR
CPTWK0
WAKEUP0
RTTWK SHDW_SR
SHDW_SR
set
set
reset
reset
read SHDW_SR
read SHDW_SR
SLCK
Table 18-1. I/O Lines Description
Name Description Type
WKUP0 Wake-up 0 input Input
SHDN Shutdown output Output
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18.5 Functional Description
The Shutdown Controller manages the main power supply. To do so, it is supplied with VDDBU and manages
wake-up input pins and one output pin, SHDN.
A typical application connects the pin SHDN to the shutdown input of the DC/DC Converter providing the main
power supplies of the system, and especially VDDCORE and/or VDDIO. The wake-up inputs (WKUP0) connect to
any push-buttons or signal that wake up the system.
The software is able to control the pin SHDN by writing the Shutdown Control Register (SHDW_CR) with the bit
SHDW at 1. The shutdown is taken into account only 2 slow clock cycles after the write of SHDW _CR. This
register is password-protected and so the value writte n should contain the correct key for the command to be
taken into account. As a result, the system should be powered down.
A level change on WKUP0 is used as wake-up. Wake-up is configured in the Shutdown Mode Register
(SHDW_MR). The transition detector can be programmed to detect either a positive or negative transition or any
level change on WKUP0. The detection can also be disabled. Programming is performed by defining WKMODE0.
Moreover, a debouncing circuit can be programmed for WKUP0. The debouncing circuit filters pulses on WKUP0
shorter than the programmed number of 16 SLCK cycles in CPTWK0 of the SHDW_MR. If the pr ogrammed level
change is detected on a pin, a counter starts. When the counter reaches the value programmed in the
corresponding field, CPTWK0, the SHDN pin is released. If a new input change is detected before the counter
reaches the corresponding value, the counter is stopped and cleared. WAKEUP0 of the Status Register
(SHDW_SR) reports th e detectio n of the pro grammed e vents on WKUP0 with a reset after the read of SHDW_SR.
The Shutdown Controller can be programmed so as to activate the wake-up using the RTT alarm (the detection of
the rising edge of the RTT alarm is synch ronized with SLCK). This is done by wr iting the SHDW_MR using the
RTTWKEN fields. When enabled, the detection of the RTT alarm is reported in the RTTWK bit of the SHDW_SR
Status register. It is reset after the read of SHDW_SR. When using the RTT alarm to wake up the system, the user
must ensure that the RTT alarm status flag is cleared before shutting down the system. Otherwise, no rising edge
of the status flag may be detected and the wake-up fails.
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18.6 Shutdown Controller (SHDWC) User Interface
Table 18-2. Register Mapping
Offset Register Name Access Reset
0x00 Shutdown Control Register SHDW_CR Write-only –
0x04 Shutdown Mode Register SHDW_MR Read/Write 0x0000 _0003
0x08 Shutdown Status Register SHDW_SR Read-only 0x0000_0000
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18.6.1 Shutdown Control Register
Name: SHDW_CR
Address: 0xFFFFFD10
Access: Write-only
• SHDW: Shutdown Command
0: No effect.
1: If KEY is correct, asserts the SHDN pin.
• KEY: Password
Should be written at value 0xA5. Writing any other value in this field aborts the write operation.
31 30 29 28 27 26 25 24
KEY
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––SHDW
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18.6.2 Shutdown Mode Register
Name: SHDW_MR
Address: 0xFFFFFD14
Access: Read/Write
• WKMODE0: Wake-up Mode 0
• CPTWK0: Counter on Wake-up 0
Defines the number of 16 Slow Clock cycles, the level detection on the corresponding input pin shall last before the wake-
up event occurs. Because of the internal synchronization of WKUP0, the SHDN pin is released
(CPTWK x 16 + 1) Slow Clock cycles after the event on WKUP.
• RTTWKEN: Real-time Timer Wake-up Enable
0: The RTT Alarm signal has no effect on the Shutdown Controller.
1: The RTT Alarm signal forces the de-assertion of the SHDN pin.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
–––––––RTTWKEN
15 14 13 12 11 10 9 8
––––––––
76543210
CPTWK0 – – WKMODE0
WKMODE[1:0] Wake-up Input Transition Sele ction
0 0 None. No detection is performed on the wake-up input
0 1 Low to high level
1 0 High to low level
1 1 Both levels change
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18.6.3 Shutdown Status Register
Name: SHDW_SR
Address: 0xFFFFFD18
Access: Read-only
• WAKEUP0: Wake-up 0 Status
0: No wake-up event occurred on the corresponding wake-up input since the last read of SHDW_SR.
1: At least one wake-up event occurred on the corresponding wake-up input since the last read of SHDW_SR.
• RTTWK: Real-time Timer Wake-up
0: No wake-up alarm from the RTT occurred since the last read of SHDW_SR.
1: At least one wake-up alarm from the RTT occurred since the la st read of SHDW_SR.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
–––––––RTTWK
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––WAKEUP0
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19. Enhanced Embedded Flash Controller (EEFC)
19.1 Description
The Enhanced Embedded Flash Controller (EEFC) ensures the interface of the Flash block with the 32-bit internal
bus. Its 128-bit wide memory interface increases performance. It also manages the programming, erasing, locking
and unlocking sequences of the Flash using a full set of commands. One of the commands returns the embedded
Flash descriptor definition th at infor ms the syste m ab ou t the Flash organ iza t ion, thus m aking th e softwa re gen er ic.
19.2 Product Dependencies
19.2.1 Power Management
The Enhanced Embedded Flash Controller (EEFC) is continuously clocked. The Power Management Controller
has no effect on its behavior.
19.2.2 Interrupt Sources
The Enhanced Embedded Flash Controller (EEFC) interrupt line is connected to the System Controller inter nal
source of the Advanced Interrupt Controller. Using the Enhanced Embedded Flash Controller (EEFC) interrupt
requires the AIC to be programmed first. The EEFC interrupt is generated only on FRDY bit rising. To know the
Flash status, EEFC Flash Status Register should be read each time a system interrupt (SYSIRQ, periph ID = 0)
occurs.
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19.3 Functional Description
19.3.1 Embedded Flash Organization
The embedded Flash interfaces directly with the 32-bit internal bus. The embedded Flash is composed of:
One memory plane organized in several pages of the same size.
Two 128-bit read buffers used for code read optimization.
One 128-bit read buffer used for data read optimization.
One write buf fer that manage s page programming. The write buf fer size is equal to the pag e size. This buffer
is write-only and accessible all along the 1 MB address space, so that each word can be written to its final
address.
Several lock bits used to protect write/erase operation on several pages (lock region). A lock bit is
associated with a lock region composed of several pages in the memory plane.
Several bits that may be set and cleared through the Enhanced Embedded Flash Controller (EEFC)
interface, called General Purpose Non-volatile Memory bits (GPNVM bits).
The embedded Flash size, the page size, the lock reg ions organization and GPNVM bits definition are described in
the product definition section. The Enhanced Embedded Flash Controller (EEFC) returns a descriptor of the Flash
controlled after a get descriptor command issued by the application (see “Getting Embedded Flash Descriptor” on
page 149).
Figure 19-1. Embedded Flash Organization
19.3.2 Read Operations
An optimized controller manage s embedded Flash reads, thus increasing perfor mance when the processor is
running in ARM and Thumb mode by means of the 128-bit wide memory interface.
The Flash memory is accessible through 8-, 16- and 32-bit reads.
As the Flash block size is smaller than the address space rese rved for the internal memory area, the embedded
Flash wraps around the address space and appears to be repeated within it.
Start Address
Page 0
Lock Region 0
Lock Region 1
Memory Plane
Page (m-1)
Lock Region (n-1)
Page (n*m-1)
Start Address + Flash size -1
Lock Bit 0
Lock Bit 1
Lock Bit (n-1)
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The read operations can be performed with or without wait states. Wait states must be programmed in the field
FWS (Flash Read Wait State) in the Flash Mode Register (EEFC_FMR). Defining FWS to be 0 en able s the sin gle-
cycle access of the embedded Flash. Refer to the Electrical Characteristics for more details.
19.3.2.1Code Read Optimization
A system of 2 x 128-bit buffers is added in order to optimize sequential Code Fetch.
Note: Immediate consecutive code read accesses are not mandatory to benefit from this optimization.
Figure 19-2. Code Read Optimization in ARM Mode for FWS = 0
Note: When FWS is equal to 0, all the accesses are performed in a single-cycle access.
Figure 19-3. Code Read Optimization in ARM Mode for FWS = 3
Note: When FWS is included between 1 and 3, in case of sequential reads, the first access takes (FWS+1) cycles, the other ones only
1 cycle.
Flash Access
Buffer 0 (128bits)
Master Clock
ARM Request
(32-bit)
XXX
Data To ARM
Bytes 0-15 Bytes 16-31 Bytes 32-47
Bytes 0-15
Buffer 1 (128bits)
Bytes 32-47
Bytes 0-3 Bytes 4-7 Bytes 8-11 Bytes 12-15 Bytes 16-19 Bytes 20-23 Bytes 24-27
XXX
XXX Bytes 16-31
@Byte 0 @Byte 4 @Byte 8 @Byte 12 @Byte 16 @Byte 20 @Byte 24 @Byte 28 @Byte 32
Bytes 28-31
Flash Access
Buffer 0 (128bits)
Master Clock
ARM Request
(32-bit)
Data To ARM
Buffer 1 (128bits)
0-3
XXX
XXX
Bytes 16-31
@Byte 0 @4 @8
Bytes 0-15 Bytes 16-31 Bytes 32-47 Bytes 48-63
XXX Bytes 0-15
4-7 8-11 12-15
@12 @16 @20
24-27 28-31 32-35 36-3916-19 20-23 40-43 44-47
@24 @28 @32 @36 @40 @44 @48 @52
Bytes 32-47
48-51
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Figure 19-4. Code Read Optimization in ARM Mode for FWS = 4
Note: When FWS is included between 4 and 10, in case of sequential reads, the first access takes (FWS+1) cycles, each first access of
the 128-bit read (FWS-2) cycles, and the others only 1 cycle.
19.3.2.2Data Read Optimization
The organiza tion of the Fla sh in 128 bits is as sociat ed with two 128-bit prefetch buffers and one 128-bit data read
buffer, thus providing maximum system performance. Th is buffer is added in or der to start acces s at the following
data during the second read. This speeds up sequential data reads if, for example, FWS is equal to 1 (see Figure
19-5).
Note: No consecutive data read accesses are mandatory to benefit from this optimization.
Figure 19-5. Data Read Optimization in ARM Mode for FWS = 1
Flash Access
Buffer 0 (128bits)
Master Clock
ARM Request
(32-bit)
Data To ARM
Buffer 1 (128bits)
0-3
XXX
XXX
Bytes 16-31
@Byte 0 @4 @8
Bytes 0-15 Bytes 16-31 Bytes 32-47
XXX
Bytes 0-15
4-7 8-11 12-15
@12 @16 @20
24-2716-19 20-23
@24 @28 @32 @36 @40
Bytes 32-47
Bytes 48-63
28-31 32-35 36-39
Flash Access
Buffer (128bits)
Master Clock
ARM Request
(32-bit)
XXX
Data To ARM
Bytes 0-15 Bytes 16-31
Bytes 0-15
Bytes 0-3 4-7 8-11 12-15 16-19 20-23
XXX
Bytes 16-31
@Byte 0 @ 4 @ 8 @ 12 @ 16 @ 20 @ 24 @ 28 @ 32 @ 36
XXX Bytes 32-47
24-27 28-31 32-35
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19.3.3 Flash Commands
The Enhanced Embedded Flash Controller (EEFC) offers a set of commands such as programming the memory
Flash, locking and unlocking lock regions, consecutive programming and locking and full Flash er as in g , etc.
Commands and read operations can be performed in parallel only on different memory planes. Code can be
fetched from one memory plane while a write or an erase operation is performed on another.
In order to perform one of these commands, the Fl ash Command Register (EEFC_FCR) has to be written with the
correct command using the field FCMD. As soon as the EEFC_FCR is written, the FRDY flag and the field
FVALUE in the EEFC_FRR are automatically cleared. Once the current command is achieved, then the FRDY
flag is automatically set. If an interrupt has been enabled by setting the bit FRDY in EEFC_FMR, the interrupt line
of the System Controller is activated.
All the commands are protected by the same keyword, which has to be written in the 8 highest bits of the
EEFC_FCR.
Writing EEFC_FCR with data that does not contain the correct key and/or with an invalid command has no effect
on the whole memory plane, but the FCMDE flag is set in the EEFC_FSR. This flag is automatically cleared by a
read access to the EEFC_FSR.
When the current command writes or erases a page in a locked region, the command has no effect on the whole
memory plane, but the FLOCKE flag is set in the EEFC_FSR. This flag is automatically cleared by a read access
to the EEFC_FSR.
Table 19-1. Set of Commands
Command Value Mnemonic
Get Flash Descriptor 0x0 GETD
Write page 0x1 WP
Write page and lock 0x2 WPL
Erase page and write page 0x3 EWP
Erase page and write page then lock 0x4 EWPL
Erase all 0x5 EA
Set Lock Bit 0x8 SLB
Clear Lock Bit 0x9 CLB
Get Lock Bit 0xA GLB
Set GPNVM Bit 0xB SGPB
Clear GPNVM Bit 0xC CGPB
Get GPNVM Bit 0xD GGPB
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Figure 19-6. Command State Cha rt
19.3.3.1Getting Embedded Flash Descriptor
This command allows the system to le ar n a bout the Flash organization. The system ca n take full a dvanta ge of this
information. For instan ce , a device coul d be rep laced by one with more Flash capacity, and so the software is able
to adapt itself to the new configuration.
To get the embedded Flash descriptor, the application writes the GETD command in the EEFC_FCR. The first
word of the descriptor can be read by the software application in the EEFC_FRR as soon as the FRDY flag in the
EEFC_FSR rises. The next reads of the EEFC_FRR provide the following word of the descriptor. If extra read
operations to the EEFC_FRR are done after the last word of the descriptor has been returned, then the
EEFC_FRR value is 0 until the next valid command.
Check if FRDY flag Set No
Yes
Read Status: MC_FSR
Write FCMD and PAGENB in Flash Command Register
Check if FLOCKE flag Set
Check if FRDY flag Set No
Read Status: MC_FSR
Yes
Yes Locking region violation
No
Check if FCMDE flag Set Yes
No
Bad keyword violation
Command Successfull
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19.3.3.2Write Commands
Several commands can be used to program the Flash.
Flash technology requires that an erase is done before programming. The full memory plan e ca n b e er a sed a t t he
same time, or several pages can be erased at the same time (refer to “Erase Commands” on page 151 ). Also, a
page erase can be automatically done before a page write using EWP or EWPL commands.
After programming, the page (the whole lock region) can be locked to prevent miscellaneous write or erase
sequences. The lock bit can be automatically set after page programming using WPL or EWPL commands.
Data to be written are stored in an internal latch buffer. The size of the latch buffer corresponds to the page size.
The latch buffer wraps around within the internal memory area address space and is repeated as many times as
the number of pages within this address space.
Note: Writing of 8-bit and 16-bit data is not allowed and may lead to unpredictable data corruption.
Write operations are performed in a number of wait states equal to the number of wait states for read operations.
Data are written to the latch buffe r before the programming comm and is written to the Flash Command Re gister
EEFC_FCR. The sequence is as follows:
Write the full page, at any page address, within the internal memory area address space.
Programming starts as soon as the page number and the programming command are written to the Flash
Command Register. The FRDY bit in the Flash Programming Status Register (EEFC_FSR) is automatically
cleared.
When progra m m ing is comp le te d, the bit FRDY in the Flash Programming Status Register (EEFC_FSR)
rises. If an interrupt has been enabled by setting the bit FRDY in EEFC_FMR, the interrupt line of the
System Controller is activated.
Two errors can be detected in the EEFC_FSR after a programming sequence:
a Command Error: a bad keyword has been written in the EEFC_FCR.
a Lock Error: the page to be programmed b elongs to a lo cked regio n. A command mu st be previously r un to
unlock the corresponding region.
By using the WP command, a page can be programmed in several steps if it has been erased before (see Figure
19-7).
Table 19-2. Flash Descriptor Definitio n
Symbol W o rd Index Description
FL_ID 0 Flash Interface Description
FL_SIZE 1 Flash size in bytes
FL_PAGE_SIZE 2 Page size in bytes
FL_NB_PLANE 3 Number of planes.
FL_PLANE[0] 4 Number of bytes in the first plane.
...
FL_PLANE[FL_NB_PLANE-1] 4 + FL_NB_PLANE - 1 Number of bytes in the last plane.
FL_NB_LOCK 4 + FL_NB_PLANE Number of lock bits. A bit is associated with a lock region. A lock bit is
used to prevent write or erase operations in the lock region.
FL_LOCK[0] 4 + FL_NB_PLANE + 1 Number of bytes in the first lock region.
...
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Figure 19-7. Example of Partial Page Programming
The Partial Programming mode works only with 32-bit (or higher) boundaries. It can not be used with boundaries
lower than 32 bits (one or two bytes, for example).
19.3.3.3Erase Commands
Erase commands are allowed only on unlocked regions.
The erase sequence is:
Erase starts as soon as one of the eras e co mm and s an d th e FARG field are written in the Flash Command
Register.
When the prog ra m ming com ple te s, th e FRDY bit in the Flash Programming Status Register (EEFC_FSR)
rises. If an interrupt has been enabled by setting the bit FRDY in EEFC_FMR, the interrupt line of the
System Controller is activated.
Two errors can be detected in the EEFC_FSR after a programming sequence:
a Command Error: a bad keyword has been written in the EEFC_FCR.
a Lock Error: at least one page to be erased belongs to a locked region. The erase command has been
refused, no page has been erased. A command must be previously r un to unlock the corresponding region.
19.3.3.4Lock Bit Protection
Lock bits are associated with several pages in the embed ded Flash memo ry plane. This defines lock re gions in the
embedded Fla sh me mo ry pl an e. Th ey pr ev en t writing/erasing pr ot ected pages.
The lock sequence is:
The Set Lock command (SLB) and a page number to be protected are written in the Flash Command
Register.
When the locking completes, the bit FRDY in the Flash Programming Status Register (EEFC_FSR) rises. If
an interrupt has been enabled by setting the bit FRDY in EEFC_FMR, the interrupt line of the System
Controller is activated.
If the lock bit number is greater than the total number of lock bits, then the command has no effect. The
result of the SLB command can be checked running a GL B (Ge t Lock Bit) comm a nd .
One error can be detected in the EEFC_FSR after a programming sequence:
a Command Error: a bad keyword has been written in the EEFC_FCR.
Erase All Flash Programming of the second part of Page Y Programming of the third part of Page Y
32-bit wide 32-bit wide 32-bit wide
X words
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
...
CA FE CA FE
CA FE CA FE
CA FE CA FE
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF CA FE CA FE
CA FE CA FE
CA FE CA FE
DE CA DE CA
DE CA DE CA
DE CA DE CA
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
Step 1. Step 2. Step 3.
...
...
...
...
...
...
...
...
...
...
...
X words
X words
X words
So Page Y erased
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It is possible to clear lock bits previously set. Then th e locked region can be erased or progra mmed. The unlock
sequence is:
The Clear Lock command (CLB) and a page number to be unprotected are written in the Flash Command
Register.
When the unlock completes, the bit FRDY in the Flash Programming Status Register (EEFC_FSR) rises. If
an interrupt has been enabled by setting the bit FRDY in EEFC_FMR, the interrupt line of the System
Controller is activated.
If the lock bit number is greater than the total number of lock bits, then the command has no effect.
One error can be detected in the EEFC_FSR after a programming sequence:
a Command Error: a bad keyword has been written in the EEFC_FCR.
The status of lock bits can be returned by the Enhanced Embedded Flash Controller (EEFC) . The Get Lock Bit
status sequence is:
The Get Lock Bit command (GLB) is written in the Flash Command Register. FARG field is meaningless.
When the command completes, th e bit FRDY in the Flash Pro gramming Status Register (EEFC_FSR) rises.
If an interrupt has been enabled by setting the bit FRDY in EEFC_FMR, the interrupt line of the System
Controller is activated.
Lock bits can be read by the software application in the EEFC_FRR. The first word read corresponds to the
32 first lock bits, next reads providing the next 32 lock bits as long as it is meaningful. Extra reads to the
EEFC_FRR return 0.
For example, if the third bit of the first word read in the EEFC_FRR is set, then the third lock region is locked.
One error can be detected in the EEFC_FSR after a programming sequence:
a Command Error: a bad keyword has been written in the EEFC_FCR.
Note: Access to the Flash in read is permitted when a set, clear or get lock bit command is performed.
19.3.3.5GPNVM Bit
GPNVM bits do not interfere with the embedded Flash memory plane. Refer to the product definition section for
information on the GPNVM Bit Action.
The set GPNVM bit sequence is:
Start the Set GPNVM Bit command (SGPB) by writing the Flash Command Register with th e SGPB
command and the number of the GPNVM bit to be set.
When the GPVNM bit is set, the bit FRDY in the Flash Programming Status Register (EEFC_FSR) rises. If
an interrupt was enabled by setting the bit FRDY in EEFC_FMR, the in terrupt line of the Syste m Controller is
activated.
If the GPNVM bit number is greater than the total number of GPNVM bits, then the command has no effect.
The result of the SGPB command can be checked by running a GGPB (Get GPNVM Bit) command.
One error can be detected in the EEFC_FSR after a programming sequence:
A Command Error: a bad keyword has been written in the EEFC_FCR.
It is possible to clear GPNVM bits previously set. The clear GPNVM bit sequence is:
Start the Clear GPNVM Bit command (CGPB) by writing the Flash Command Register with CGPB and the
number of the GPNVM bit to be cleared.
When the clear comp letes, the bit FRDY in th e Flash Programming Status Re gister (EEFC_FSR) ri ses. If an
interrupt has been enabled by setting the bit FRDY in EEFC_FMR, the interrupt line of the System Controller
is activated.
If the GPNVM bit number is greater than the total number of GPNVM bits, then the command has no effect.
One error can be detected in the EEFC_FSR after a programming sequence:
A Command Error: a bad keyword has been written in the EEFC_FCR.
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The status of GPNVM bits can be returned by t he Enhanced Embedded Flash Controller (EEFC). The sequence
is:
Start the Get GPNVM bit command by writing the Flash Command Register with GGPB. The FARG field is
meaningless.
When the command completes, th e bit FRDY in the Flash Pro gramming Status Register (EEFC_FSR) rises.
If an interrupt has been enabled by setting the bit FRDY in EEFC_FMR, the interrupt line of the System
Controller is activated.
GPNVM bits can be read by the software application in the EEFC_FRR. The first word read corresponds to
the 32 first GPNVM bits, following reads provide the next 32 GPNVM bits as long as it is meaningful. Extra
reads to the EEFC_FRR return 0.
For example, if the third bit of the first word read in the EEFC_FRR is set, then the third GPNVM bit is active.
One error can be detected in the EEFC_FSR after a programming sequence:
a Command Error: a bad keyword has been written in the EEFC_FCR.
Note: Access to the Flash in read is permitted when a set, clear or get GPNVM bi t command is performed.
19.3.3.6Security Bit Protection
When the security is enabled, access to the Flash, either through the ICE interface or through the Fast Flash
Programmi ng Inter face, is forbidden. Th is en su re s th e confidentiality of the code programmed in the Flash.
The security bit is GPNVM0 .
Disabling the security bit can only be achieved by asserting the ERASE pin at 1, and after a full Flash erase is
performed. When the security bit is deactivated, all accesses to the Flash are permitted.
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19.4 Enhanced Embedded Flash Controller (EEFC) User Interface
The User Interface of the Enhanced Embedded Flash Controller (EEFC) is integrated within the System Controller with
base address 0xFFFF FA00.
Table 19-3. Register Mapping
Offset Re gister Name Access Reset State
0x00 EEFC Flash Mode Register EEFC_FMR Read/Write 0x0
0x04 EEFC Flash Command Register EEFC_FCR Write-only –
0x08 EEFC Flash Status Register EEFC_FSR Read-only 0x00000001
0x0C EEFC Flash Result Register EEFC_FRR Read-only 0x0
0x10 Reserved – – –
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19.4.1 EEFC Flash Mode Register
Name: EEFC_FMR
Address: 0xFFFFFA00
Access: Read/Write
• FRDY: Ready Interrupt Enable
0: Flash Ready does not generate an interrupt.
1: Flash Ready (to accept a new command) generates an interrupt.
• FWS: Flash Wait State
This field defines the number of wait states for read and write operations:
Number of cycles for Read/Write operations = FWS+1
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––– FWS
76543210
–––––––FRDY
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19.4.2 EEFC Flash Command Register
Name: EEFC_FCR
Address: 0xFFFFFA04
Access: Write-only
• FCMD: Flash Command
This field defines the flash commands. Refer to “Flash Commands” on page 148.
• FARG: Flash Command Argument
• FKEY: Flash Writing Protection Key
This field should be written with the value 0x5A to e nable the comman d defined by the b its of the regi ster. If the field is wri t-
ten with a different value, the write is not performed and no action is started.
31 30 29 28 27 26 25 24
FKEY
23 22 21 20 19 18 17 16
FARG
15 14 13 12 11 10 9 8
FARG
76543210
FCMD
Erase command For erase all command, this field is meaningless.
Programming command FARG defines the page number to be programmed.
Lock command FARG defines the page number to be locked.
GPNVM command FARG defines the GPNVM number.
Get commands Field is meaningless.
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19.4.3 EEFC Flash Status Register
Name: EEFC_FSR
Address: 0xFFFFFA08
Access: Read-only
• FRDY: Flash Ready Status
0: The Enhanced Embedded Flash Controller (EEFC) is busy.
1: The Enhanced Embedded Flash Controller (EEFC) is ready to start a new command.
When it is set, this flags triggers an interrupt if the FRDY flag is set in the EEFC_FMR.
This flag is automatically cleared when the Enhanced Embedded Flash Controller (EEFC) is busy.
• FCMDE: Flash Command Error Status
0: No invalid commands and no bad keywords were written in the Flash Mode Register EEFC_FMR.
1: An invalid command and/or a bad keyword was/were written in the Flash Mode Register EEFC_FMR.
This flag is automatically cleared when EEFC_FSR is read or EEFC_FCR is written.
• FLOCKE: Flash Lock Error Status
0: No programming/erase of at least one locked region has happened since the last read of EEFC_FSR.
1: Programming/erase of at least one locked region has happened since the last read of EEFC_FSR.
This flag is automatically cleared when EEFC_FSR is read or EEFC_FCR is written.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––FLOCKEFCMDEFRDY
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19.4.4 EEFC Flash Result Register
Name: EEFC_FRR
Address: 0xFFFFFA0C
Access: Read-only
• FVALUE: Flash Result Value
The result of a Flash command is returned in this register. If the size of the result is greater than 32 bits, then the next
resulting value is accessible at the next register read.
31 30 29 28 27 26 25 24
FVALUE
23 22 21 20 19 18 17 16
FVALUE
15 14 13 12 11 10 9 8
FVALUE
76543210
FVALUE
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20. SAM9XE Bus Matrix
20.1 Description
Bus Matrix implements a multi-layer AHB, based on AHB-Lite protocol, that enables parallel access paths between
multiple AHB masters and slaves in a system, which increases the overall bandwidth. Bus Matrix interconnects 6
AHB Masters to 5 AHB Slaves. The normal latency to connect a master to a slave is one cycle except for the
default master of the accessed slave which is connected directly (zero cycle latency).
The Bus Matrix user interface is compliant with ARM Advance Peripheral Bus and provides a Chip Configuration
User Interface with Registers that allow the Bus Matrix to support application specific features.
20.2 Memory Mapping
Bus Matrix provides one decoder for every AHB Master Interface. The deco der offers each AHB Master seve ral
memory mappings. In fact, depending on the product, each memory area may be assigned to seve ral slaves.
Booting at the same address while using different AHB slaves (i.e., external RAM, internal ROM or internal Flash,
etc.) becomes possible.
The Bus Matrix user interfa ce provides Master Remap Control Register (MATRIX_MRCR) that allows to perform
remap action for every master independently.
20.3 Special Bus Granting Techniques
The Bus Matrix provides some speculative bus granting techniques in order to anticipate access req uests from
some masters. This mechanism allows to reduce latency at first accesses of a burst or single transfer. The bus
granting mechanism allows to set a default master for every slave.
At the end of the current access, if no other request is pending, the slave remains connected to its associated
default master. A slave can be associated with three kinds of default masters: no default master, last access
master and fixed default master.
20.3.1 No Default Master
At the end of the current acce ss, if no other request is pending, the slav e is disconnected from all masters. No
Default Master suits low power mode.
20.3.2 Last Access Master
At the end of th e current access, if no oth er request is pending, the slave remains connected to the last master that
performed an access request.
20.3.3 Fixed Default Master
At the end of the cu rrent access, if no other r equest is pending, the slave conn ects to itsfixed default master .
Unlike last access master, the fixed master doesn’t change unless the user modifies it by a software action (field
FIXED_DEFMSTR of the related MATRIX_SCFG).
To change from one kind of default master to another, the Bus Matrix user interface provides the Slave
Configuration Registers, one for each slave, that allow to set a default master for each slave. The Slave
Configuration Register contains two fields:
DEFMSTR_TYPE and FIXED_DEFMSTR. The 2-bit DEFMSTR_TYPE field allows to choose the default master
type (no default, last access master, fixed default master) whereas the 4-bit FIXED_DEF MSTR field allows to
choose a fixed default master provided that DEFMSTR_TYPE is set to fixed default master. Please refer to the
Bus Matrix user interface description.
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20.4 Arbitration
The Bus Matrix provides an arbitration mechanism that allows to reduce latency when conflict cases occur,
basically when two or more masters try to access the same slave at the same time. One arbiter per AHB slave is
provided, allowing to arbitrate each slave differently.
The Bus Matrix provides to the user the possibility to choose between two arbitration types, and this for each slave:
1. Round-Robin Arbitration (the default)
2. Fixed Priority Arbitration
This choice is given through the field ARBT of the Slave Configuration Registers (MATRIX_SCFG).
Each algorithm may be complemented by selecting a default master configuration for each slave.
When a re-arbitration has to be done, it is realized only under some specific conditions detailed in the following
paragraph.
20.4.1 Arbitration Rules
Each arbiter has the ability to arbitrate b etween two or more different master’s requests. In order to avoid burst
breaking and also to provide the maximum throughput for slave interfaces, arbitration may only take place during
the following cycles:
1. Idle Cycles: when a slave is not connected to any master or is connected to a master which is not currently
accessing it.
2. Single Cycles: when a slave is currently doing a single access.
3. End of Burst Cycles: when the current cycle is the last cycle of a burst transfer. For defined length burst,
predicted end of burst match the size of the transfer but is managed differently for undefined length burst
(See Section 20.4.1.1 “Undefined Length Burst Arbitration”).
4. Slot Cycle Limit: when the slot cycle counter has reach the limit value indicating that the current master
access is too long and mu st be br ok en (see Section 20.4.1.2 “Slot Cycle Limit Arbitration”).
20.4.1.1Undefined Length Burst Arbitration
In order to avoid too long slave handling during undefined length bursts (INCR), the Bus Matrix provides specific
logic in order to re-arbitrate before the end of the INCR transfe r.
A predicted end of burst is used as for defined length burst transfer, which is selected between the following:
1. Infinite: no predicted end of burst is generated and therefore INCR burst transfer will never be broken.
2. Four beat bursts: predicted end of burst is generated at the end of each four beat boundary inside INCR
transfer.
3. Eight beat bursts: predicted end of burst is generated at the end of each eight beat boundary inside INCR
transfer.
4. Sixteen beat bursts: predicted end of burst is generated at the end of each sixteen beat boundary inside
INCR transfer.
This selection can be done through the field ULBT of the Master Configuration Registers (MATRIX_MCFG).
20.4.1.2Slot Cycle Limit Arbitration
The Bus Matrix contains spe cific logic to break too long access es such as very long bursts on a very slow slave
(e.g. an external low speed memory). At the beginning of the burst access, a counter is loaded with th e value
previously written in the SLOT_CYCLE field of the related Slave Configuration Register (MATRIX_SCFG) and
decreased at each clock cycle. When the counter reaches zero, the arbiter has the ability to re-arbitrate at the end
of the current byte, half word or word transfer.
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20.4.2 Round-Robin Arbitration
This algorithm allows the Bus Matrix arbiters to dispatch the requests from different masters to the sam e slave in a
round-robin manne r. If two or more master’s req uests arise at the same time, the master with the lowest number is
first serviced then the others are serviced in a round-robin manner.
There are th re e ro un d -r ob in alg o rith m s imp lem e nt ed :
Round-Robin arbitration without default master
Round-Robin arbitration with last access master
Round-Robin arbitration with fixed default master
20.4.2.1Round-Robin Arbitration without Default Master
This is the main algorithm used by Bus Matrix arbiters. It allows the Bus Matrix to dispatch requests from different
masters to the same slave in a pu re round-robin manner. At the end of th e current access, if no other request is
pending, the slave is disconnected fro m all ma sters. T his co nfigu ration incurs one latency cycle for th e first acce ss
of a burst. Arbitration without default master can be used for masters that perform significant bursts.
20.4.2.2Round-Robin Arbitration with Last Access Master
This is a biased round-robin algorithm used by Bus Matrix arbiters. It allows the Bus Matrix to remove the one
latency cycle for the last master that accessed the slave. At the end of the current transfer, if no other master
request is pe nd in g, th e slave rem ain s c on nec t ed to the last master that performs the access. Other non privileged
masters will still get one latency cycle if they want to access the same slave. This technique can be used for
masters that mainly perform single accesses.
20.4.2.3Round-Robin Arbitration with Fixed Default Master
This is another biased round-robin algorithm, it allows the Bus Matrix arbiters to remove the one latency cycle for
the fixed defaul t master per slave. At the end o f the curr ent access, the slave remains connected to its fixed default
master. Requests attempted by this fixed default master do not cause any latency whereas other non privileged
masters get one latency cycle. This technique can be used for masters that mainly perform single accesses.
20.4.3 Fixed Priority Arbitration
This algorithm allows the Bus Matrix arbiters to dispatch the requests from different masters to the same slave by
using the fixed priority defined by the user. If two or more master’s requests are active at the same time, the
master with the highest priority numbe r is serviced first. If two or more master’s requests with the same priority are
active at the same time, the master with the highest number is serviced first.
For each slave, the priority of each master may be defined through the Priority Registers for Slaves
(MATRIX_PRAS and MATRIX_PRBS).
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20.5 Bus Matrix (MATRIX) User Interface
Table 20-1. Register Mapping
Offset Register Name Access Reset
0x0000 Master Configuration Register 0 MATRIX_MCFG0 Read/Write 0x00000000
0x0004 Master Configuration Register 1 MATRIX_MCFG1 Read/Write 0x00000000
0x0008 Master Configuration Register 2 MATRIX_MCFG2 Read/Write 0x00000000
0x000C Master Configuration Register 3 MATRIX_MCFG3 Read/Write 0x00000000
0x0010 Master Configuration Register 4 MATRIX_MCFG4 Read/Write 0x00000000
0x0014 Master Configuration Register 5 MATRIX_MCFG5 Read/Write 0x00000000
0x0018–0x003C Reserved – – –
0x0040 Slave Configuration Register 0 MATRIX_SCFG0 Read/Write 0x00010010
0x0044 Slave Configuration Register 1 MATRIX_SCFG1 Read/Write 0x00050010
0x0048 Slave Configuration Register 2 MATRIX_SCFG2 Read/Write 0x00000010
0x004C Slave Configuration Register 3 MATRIX_SCFG3 Read/Write 0x00000010
0x0050 Slave Configuration Register 4 MATRIX_SCFG4 Read/Write 0x00000010
0x0054–0x007C Reserved – – –
0x0080 Priority Register A for Slave 0 MATRIX_PRAS0 Read/Write 0x00000000
0x0084 Reserved – – –
0x0088 Priority Register A for Slave 1 MATRIX_PRAS1 Read/Write 0x00000000
0x008C Reserved – – –
0x0090 Priority Register A for Slave 2 MATRIX_PRAS2 Read/Write 0x00000000
0x0094 Reserved – – –
0x0098 Priority Register A for Slave 3 MATRIX_PRAS3 Read/Write 0x00000000
0x009C Reserved – – –
0x00A0 Priority Register A for Slave 4 MATRIX_PRAS4 Read/Write 0 x00000000
0x00A8–0x00FC Reserved – – –
0x0100 Master Remap Control Register MATRIX_MRCR Read/Write 0x00000000
0x0104–0x010C Reserved – – –
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20.5.1 Bus Matrix Master Configuration Registers
Name: MATRIX_MCFG0...MATRIX_MCFG5
Address: 0xFFFFEE00
Access: Read/Write
• ULBT: Undefined Length Burst Type
0: Infinite Length Burst
No predicted end of burst is generated and therefore INCR bursts coming from this master cannot be broken.
1: Single Access
The undefined length burst is treated as a succession of single access allowing rearbitration at each beat of the INCR
burst.
2: Four Beat Burst
The undefined length burst is split into 4-beat burst allowing rearbitration at each 4-beat burst end.
3: Eight Beat Burst
The undefined length burst is split into 8-beat burst allowing rearbitration at each 8-beat burst end.
4: Sixteen Beat Burst
The undefined length burst is split into 16-beat burst allowing rearbitration at each 16-beat burst end.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
––––– ULBT
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20.5.2 Bus Matrix Slave Configuration Registers
Name: MATRIX_SCFG0...MATRIX_SCFG4
Address: 0xFFFFEE40
Access: Read/Write
• SLOT_CYCLE: Maximum Number of Allowed Cycles for a Burst
When the SLOT_CYCLE limit is reach for a burst it may be broken by another master tryin g to access this slave.
This limit has been placed to avoid locking very slow slave by when very long burst are used.
This limit should not be very small though. Unreasonable small value will break every burst and Bus Matrix will spend its
time to arbitrate without performing any data transfer. 16 cycles is a reasonable value for SLOT_CYCLE.
• DEFMASTR_TYPE: Default Master Type
0: No Default Master
At the end of current slave access, if no other master request is pending, the slave is disconnected from all masters.
This results in having a one cycle latency for the first access of a burst transfer or for a single access.
1: Last Default Master
At the end of current slave access, if no other master request is pending, the slave stay connected with th e last master
having accessed it.
This results in not having the one cycle latency when the last master re-tries acc es s on th e sla ve ag a in.
2: Fixed Default Master
At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master which
number has been written in the FIXED_DEFMSTR field.
This results in not having the one cycle latency when the fixed master re-tries access on the slave again.
• FIXED_DEF MST R : Fix e d Defa ul t Ma s te r
This is the number of the Default Master for this slave. Only used if DEFMASTR_TYPE is 2. Specifying the number of a
master which is not connected to the selected slave is equivalent to setting DEFMASTR_TYPE to 0.
• ARBT: Arbitration Type
0: Round-Robin Arbitration
1: Fixed Priority Arbitration
2: Reserved
3: Reserved
31 30 29 28 27 26 25 24
–––––– ARBT
23 22 21 20 19 18 17 16
– FIXED_DEFMSTR DEFMSTR_TYPE
15 14 13 12 11 10 9 8
––––––––
76543210
SLOT_CYCLE
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20.5.3 Bus Matrix Priority Registers For Slaves
Name: MATRIX_PRS0...MATRIX_PRS4
Access: Read/Write
• MxPR: Master x Priority
Fixed priority of Master x for access to the selected slave. The higher the number, the higher the priority.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
–– M5PR –– M4PR
15 14 13 12 11 10 9 8
–– M3PR –– M2PR
76543210
–– M1PR –– M0PR
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20.5.4 Bus Matrix Master Remap Control Register
Name: MATRIX_MRCR
Address: 0xFFFFEF00
Access: Read/Write
• RCBx: Remap Command Bit for AHB Master x
0: Disable remapped address decoding for the selected Master
1: Enable remapped address decoding for the selected Master
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––––––-
76543210
––––––RCB1RCB0
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20.6 Chip Configuration User Interface
Table 20-2. Chip Configuration User Interface
Offset Register Name Access Reset Value
0x0110–0x0118 Reserved – – –
0x011C EBI Chip Select Assignment Register EBI_CSA Read/Write 0x00010000
0x0130–0x01FC Reserved – – –
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20.6.1 EBI Chip Select Assignment Register
Name: EBI_CSA
Access: Read/Write
• EBI_CS1A: EBI Chip Select 1 Assignment
0: EBI Chip Select 1 is assigned to the Static Memory Controller.
1: EBI Chip Select 1 is assigned to the SDRAM Controller.
• EBI_CS3A: EBI Chip Select 3 Assignment
0: EBI Chip Select 3 is only assigned to the Static Memory Controller and EBI_NCS3 behaves as defined by the SMC.
1: EBI Chip Select 3 is assigned to the Static Memory Controlle r and the SmartMedia Logic is activated.
• EBI_CS4A: EBI Chip Select 4 Assignment
0: EBI Chip Select 4 is only assigned to the Static Memory Controller and EBI_NCS4 behaves as defined by the SMC.
1: EBI Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic (first slot) is activated.
• EBI_CS5A: EBI Chip Select 5 Assignment
0: EBI Chip Select 5 is only assigned to the Static Memory Controller and EBI_NCS5 behaves as defined by the SMC.
1: EBI Chip Select 5 is assigned to the Static Memory Controller and the CompactFlash Logic (second slot) is activated.
• EBI_DBPUC: EBI Data Bus Pull-Up Configuration
0: EBI D0–D15 Data Bus bits are internally pulled-up to the VDDIOM0 power supply.
1: EBI D0–D15 Data Bus bits are not internally pulled-up.
• EBI_DRIVE EBI I/O Drive Configuration
Used to avoid overshoots and to give the best performance acco rding to bus load and external memories.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
–––––– EBI_DRIVE
15 14 13 12 11 10 9 8
–––––––EBI_DBPUC
76543210
– – EBI_CS5A EBI_CS4A EBI_CS3A – EBI_CS1A –
Value Drive Conf iguration Conditions
00 Optimized for 1.8V powered memories with Low Drive Maximum load capacitance 20 pF
01 Optimized for 3.3V powered memories with Low Drive Maximum load capacitance 27 pF
10 Optimized for 1.8V powered memories with High Drive M aximum load capacitance 40 pF
11 Optimized for 3.3V powered memories with High Drive Maximu m lo ad capacitance 55 pF
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21. SAM9XE External Bus Interface
21.1 Description
The External Bus Interface (EBI) is designed to ensure the successful data transfer between several external
devices and the embedded memory controller of an ARM-based device. The Static Memory, SDRAM and ECC
controllers are all featured extern al memory controllers on the EBI. Th ese external memory co ntrollers are capab le
of handling several types of external memory and peripheral devices, such as SRAM, PROM, EPROM, EEPROM,
Flash, and SDRAM.
The EBI also supports the CompactFlash and the NAND Flash protocols via integrated circuitry that greatly
reduces the requirements for external components. Furthermore, the EBI handles data transfers with up to six
external devices, each assigned to six address spaces defined by the embedded Memory Controller. Data
transfers ar e perfo rm e d th ro ug h a 16-b it or 32 -b it da ta bu s, an ad dr e ss bu s of up to 26 bits, up to eight ch ip select
lines (NCS[7:0]) and several control pins that are generally multiplexed between the different external memory
controllers.
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21.2 Block Diagram
21.2.1 External Bus Interface
Figure 21-1 shows the organization of the External Bus Interface.
Figure 21-1. Organization of the External Bus Interface
External Bus Interface
D[15:0]
A[15:2], A[22:18]
PIO
MUX
Logic
User Interface
Chip Select
Assignor
Static
Memory
Controller
SDRAM
Controller
Bus Matrix
APB
AHB
Address Decoders
A16/BA0
A0/NBS0
A1/NWR2/NBS2
A17/BA1
NCS0
NRD/NOE/CFOE
NCS1/SDCS
NWR0/NWE/CFWE
NWR1/NBS1/CFIOR
NWR3/NBS3/CFIOW
SDCK
SDCKE
RAS
CAS
SDWE
D[31:16]
A[25:23]
CFRNW/A25
NCS4/CFCS0
NCS5/CFCS1
NCS2/NCS6/NCS7
CFCE1
CFCE2
NWAIT
SDA10
NANDOE
NANDWE
NAND Flash
Logic
CompactFlash
Logic
ECC
Controller
NCS3/NANDCS
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21.3 I/O Lines Description
The connection of some signals through the MUX logic is not direct and depends on the memory controller
currently being used.
Table 21-1. EBI I/O Lines Description
Name Function Type Active Level
EBI
EBI_D0–EBI_D31 Data Bus I/O
EBI_A0–EBI_A25 Address Bus Output
EBI_NWAIT External Wait Signal Input Low
SMC
EBI_NCS0–EBI_NCS7 Chip Select Lines Output Low
EBI_NWR0–EBI_NWR3 Write Signals Output Low
EBI_NOE Output Enable Output Low
EBI_NRD Read Signal Output Low
EBI_NWE Write Enable Output Low
EBI_NBS0–EBI_NBS3 Byte Mask Signals Output Low
EBI for CompactFlash Support
EBI_CFCE1–EBI_CFCE2 CompactFlash Chip Enable Output Low
EBI_CFOE CompactFlash Output Enable Output Low
EBI_CFWE CompactFlash Write Enable Output Low
EBI_CFIOR CompactFlash I/O Read Signal Output Low
EBI_CFIOW CompactFlash I/O Write Signal Output Low
EBI_CFRNW CompactFlash Read Not Write Signal Output
EBI_CFCS0–EBI_CFCS1 C ompactFlash Chip Select Lines Output Low
EBI for NAND Flash Support
EBI_NANDCS NAND Flash Chip Select Line Output Low
EBI_NANDOE NAND Flash Output Enable Output Low
EBI_NANDWE NAND Flash Write Enable Output Low
SDRAM Controller
EBI_SDCK SDRAM Clock Output
EBI_SDCKE SDRAM Clock Enable Output High
EBI_SDCS SDRAM Controller Chip Select Line Output Low
EBI_BA0–EBI_BA1 Bank Select Output
EBI_SDWE SDRAM Write Enable Output Low
EBI_RAS - EBI_CAS Row and Column Signal Output Low
EBI_NWR0–EBI_NWR3 Write Signals Output Low
EBI_NBS0–EBI_NBS3 Byte Mask Signals Output Low
EBI_SDA10 SDRAM Address 10 Line Output
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Table 21-2 details the connections between the two memory controllers and the EBI pins.
Table 21-2. EBI Pins and Memory Controllers I/O Lines Connections
EBIx Pins SDRAMC I/O Lines SMC I/O Lines
EBI_NWR1/NBS1/CFIOR NBS1 NWR1/NUB
EBI_A0/NBS0 Not Supported SMC_A0/NLB
EBI_A1/NBS2/NWR2 Not Supported SMC_A1
EBI_A[11:2] SDRAMC_A[9:0] SMC_A[11:2]
EBI_SDA10 SDRAMC_A10 Not Supported
EBI_A12 Not Supported SMC_A12
EBI_A[14:13] SDRAMC_A[12:11] SMC_A[14:13]
EBI_A[22:15] Not Supported SMC_A[22:15]
EBI_A[25:23] Not Supported SMC_A[25:23]
EBI_D[31:0] D[31:0] D[31:0]
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21.4 Application Example
21.4.1 Hardware Interface
Table 21-3 details the connections to be applied between the EBI pins and the external devices for each memory
controller.
Notes: 1. NWR1 enables upper byte writes. NWR0 enables lower byte writes.
2. NWRx enables corresponding byte x writes. (x = 0, 1, 2 or 3)
3. NBS0 and NBS1 enable respectively lower and upper bytes of the lower 16-bit word.
4. NBS2 and NBS3 enable respectively lower and upper bytes of the upper 16-bit word.
5. BEx: Byte x Enable (x = 0, 1, 2 or 3)
Table 21-3. EBI Pins and External Static Devices Connection s
Signals: EBI_
Pins of the SMC Interfaced Device
8-bit
Static Device 2 x 8-bit
Static Devices 16-bit
Static Device 4 x 8-bit
Static Devices 2 x 16-bit
Static Devices 32-bit
Static Device
D0–D7 D0–D7 D0–D7 D0–D7 D0–D7 D0–D7 D0–D7
D8–D15 – D8–D15 D8–D15 D8–D15 D8–15 D8–15
D16–D23 – – – D16–D23 D16–D23 D16–D23
D24–D31 – – – D24–D31 D24–D31 D24–D31
A0/NBS0 A0 – NLB – NLB(3) BE0(5)
A1/NWR2/NBS2 A1 A0 A0 WE(2) NLB(4) BE2(5)
A2–A22 A[2:22] A[1:21] A[1:21] A[0:20] A[0:20] A[0:20]
A23–A25 A[23:25] A[22:24] A[22:24] A[21:23] A[21:23] A[21:23]
NCS0 CS CS CS CS CS CS
NCS1/SDCSCSCSCSCSCSCS
NCS2 CS CS CS CS CS CS
NCS3/NANDCS CS CS CS CS CS CS
NCS4/CFCS0 CS CS CS CS CS CS
NCS5/CFCS1 CS CS CS CS CS CS
NCS6 CS CS CS CS CS CS
NCS7 CS CS CS CS CS CS
NRD/CFOE OE OE OE OE OE OE
NWR0/NWE WE WE(1) WE WE(2) WE WE
NWR1/NBS1 – WE(1) NUB WE(2) NUB(3) BE1(5)
NWR3/NBS3 – – – WE(2) NUB(4) BE3(5)
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Table 21-4. EBI Pins and External Devices Connections
Signals: EBI_
Pins of the Interfaced Device
SDRAM Controller Static Memory Controller
SDRAM CompactFlash
(EBI only)
CompactFlash
True IDE Mode
(EBI only) NAND Flash
D0–D7 D0–D7 D0–D7 D0–D7 I/O0–I/O7
D8–D15 D8–D15 D8–15 D8–15 I/O8–I/O15
D16–D31 D16–D31 – – –
A0/NBS0 DQM0 A0 A0 –
A1/NWR2/NBS2 DQM2 A1 A1 –
A2–A10 A[0:8] A[2:10] A[2:10] –
A11 A9 – – –
SDA10 A10 – – –
A12 ––––
A13–A14 A[11:12] – – –
A15 ––––
A16/BA0 BA0 – – –
A17/BA1 BA1 – – –
A18–A20 – – – –
A21 – – – ALE
A22 – REG REG CLE
A23–A24 – – – –
A25 – CFRNW(1) CFRNW(1) –
NCS0 ––––
NCS1/SDCS CS – – –
NCS2 ––––
NCS3/NANDCS – – – –
NCS4/CFCS0 – CFCS0(1) CFCS0(1) –
NCS5/CFCS1 – CFCS1(1) CFCS1(1) –
NCS6 ––––
NCS7 ––––
NANDOE – – – RE
NANDWE – – – WE
NRD/CFOE – OE – –
NWR0/NWE/CFWE – WE WE –
NWR1/NBS1/CFIOR DQM1 IOR IOR –
NWR3/NBS3/CFIOW DQM3 IOW IOW –
CFCE1 – CE1 CS0 –
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Notes: 1. Not directly connected to the CompactFlash slot. Permits the control of the bidirectional buffer between the EBI data bus
and the CompactFlash slot.
2. Any PIO line.
CFCE2 – CE2 CS1 –
SDCK CLK – – –
SDCKE CKE – – –
RAS RAS – – –
CAS CAS – – –
SDWE WE – – –
NWAIT – WAIT WAIT –
Pxx(2) – CD1 or CD2 CD1 or CD2 –
Pxx(2) –––CE
Pxx(2) –––RDY
Table 21-4. EBI Pins and External Devices Connections (Continued)
Signals: EBI_
Pins of the Interfaced Device
SDRAM Controller Static Memory Controller
SDRAM CompactFlash
(EBI only)
CompactFlash
True IDE Mode
(EBI only) NAND Flash
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21.4.2 Connection Examples
Figure 21-2 shows an example of connections between the EBI and external devices.
Figure 21-2. EBI Connections to Memory Devices
21.5 Product Dependencies
21.5.1 I/O Lines
The pins used for interfacing the Externa l Bus Interface may be multiplexed with the PIO lines. The programmer
must first program the PIO controller to assign the External Bus Interface pins to their peripheral function. If I/O
lines of the External Bus Interface are no t use d by the application, they can be used for other purposes by the PIO
Controller.
EBI
D0-D31
A2-A15
RAS
CAS
SDCK
SDCKE
SDWE
A0/NBS0
2M x 8
SDRAM
D0-D7
A0-A9, A11
RAS
CAS
CLK
CKE
WE
DQM
CS
BA0
BA1
NWR1/NBS1
A1/NWR2/NBS2
NWR3/NBS3
NCS1/SDCS
D0-D7 D8-D15
A16/BA0
A17/BA1
A18-A25
A10
SDA10
SDA10
A2-A11, A13
NCS0
NCS2
NCS3
NCS4
NCS5
A16/BA0
A17/BA1
2M x 8
SDRAM
D0-D7
A0-A9, A11
RAS
CAS
CLK
CKE
WE
DQM
CS
BA0
BA1
A10 SDA10
A2-A11, A13
A16/BA0
A17/BA1
2M x 8
SDRAM
D0-D7
A0-A9, A11
RAS
CAS
CLK
CKE
WE
DQM
CS
BA0
BA1
D16-D23 D24-D31
A10 SDA10
A2-A11, A13
A16/BA0
A17/BA1
2M x 8
SDRAM
D0-D7
A0-A9, A11
RAS
CAS
CLK
CKE
WE
DQM
CS
BA0
BA1
A10 SDA10
A2-A11, A13
A16/BA0
A17/BA1
NBS0 NBS1
NBS3
NBS2
NRD/NOE
NWR0/NWE
128K x 8
SRAM 128K x 8
SRAM
D0-D7 D0-D7
A0-A16 A0-A16
A1-A17 A1-A17
CS CS
OE
WE
D0-D7 D8-D15
OE
WE
NRD/NOE
A0/NWR0/NBS0 NRD/NOE
NWR1/NBS1
SDWE
SDWE
SDWE
SDWE
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21.6 Functional Description
The EBI transfers da ta between the interna l AHB Bus (handled by the Bus Matrix) and the external memories or
peripheral devices. It controls the waveforms and the parameters of the external address, data and control buses
and is composed of the following elements:
the Static Memory Controller (SMC)
the SDRAM Controller (SDRAMC)
the ECC Controller (ECC)
a chip select assignment feature that assigns an AHB address space to the external devices
a multiplex controller circuit that shares the pins between the different Memory Controllers
programmable CompactFlash support logic
programmable NAND Flash support logic
21.6.1 Bus Multiplexing
The EBI offers a complete set of control signals that share the 32-bit data lines, the address lines of up to 26 bits
and the control signals through a multiplex logic operating in function of the memory area requests.
Multiplexing is specifically organize d in order to guaran tee the maintenance o f th e address an d output contr ol lines
at a stable state while no external access is being performed. Mu ltiplexing is also designed to r espect the data float
times defined in the Memory Controllers. Furthermore, refresh cycles of the SDRAM are executed independently
by the SDRAM Controller without delaying the other external Memory Controller accesses.
21.6.2 Pull-up Control
The EBI Chip Select Assignment Register (EBI _CSA) in Section 20.6 “Chip Configuration User Interface” permits
enabling of on-chip pull-up resistors on th e data bus lines not multiplexed with the PIO Controller lines. The pull-up
resistors are enabled after reset. Setting the EBI_CSA.EBI_DBPUC bit disables the pull-up resistors on the lines
D0–D15. Enabling the pull-up resistor on the lines D16–D31 can be performed by programming the appropriate
PIO controller.
21.6.3 Static Memory Controller
For information on the Static Memory Controller, refer to Section 22. “Static Memory Controller (SMC)”.
21.6.4 SDRAM Controller
For information on the SDRAM Controller, refer to Section 23. “SDRAM Controller (SDRAMC)”.
21.6.5 ECC Controller
For information on the ECC Controller, refer to Section 24. “Error Correction Code Controller (ECC)”.
21.6.6 CompactFlash Support
The External Bus Interface integrates circuitry that interfaces to Co mpactFlash devices.
The CompactFlash logic is driven by the Static Memory Controller (SMC) on the NCS4 and/or NCS5 address
space. Programming the EBI_CS4A and/or EBI_CS5A bit of the EBI_CSA register to the appropriate value
enables this logic. For details on this register, refer to Section 20. “SAM9XE Bus Matrix”. Access to an external
CompactFlash device is then made by accessing the address sp ace reserved to NCS4 and/o r NCS5 (i.e., between
0x5000 0000 and 0x5FFF FFFF for NCS4 and between 0x6000 0000 and 0x6FFF FFFF for NCS5).
All CompactFlash modes (Attribute Memory, Common Memory, I/O and True IDE) are supported but the signals
_IOIS16 (I/O and True IDE modes) and _ATA SEL (True IDE mode) are not handled.
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21.6.6.1 I/O Mode, Common Memory Mode, Attribute Memory Mode and True IDE Mode
Within the NCS4 and/or NCS5 address space, the current transfer address is used to distinguish I/O mode,
common memory mode, attribute memory mode and True IDE mode.
The different modes are accessed through a specific memory mapping as illustrated on Figure 21-3. A[23:21] bits
of the transfer address are used to select the desired mode as described in Table 21-5.
Figure 21-3. CompactFlash Memory Mapping
Note: The A22 pin is used to drive the REG signal of the CompactFlash Device (except in Tr ue ID E mode ).
21.6.6.2 CFCE1 and CFCE2 Signals
To cover all types of access, the SMC mu st be alternatively set to drive 8-bit data bus or 16-bit data bus. The odd
byte access on the D[7:0] bus is only possible when the SMC is config ured to drive 8-bit memory devices on the
corresponding NCS pin (NCS4 or NCS5). The DBW field in the SMC MODE Register corresponding to the NCS4
and/or NCS5 address space must be configured as shown in Table 21-6 to enable the required access type.
NBS1 and NBS0 are the byte selection signals from SMC and are available when the SMC is set in Byte Select
mode on the corresponding Chip Select.
The CFCE1 and CFCE2 waveforms are identical to the corresponding NCSx waveform. For details on these
waveforms and timings, refer to Section 22. “Static Memory Controller (SMC)”.
Table 21-5. CompactFlash Mode Selection
A[23:21] Mode Base Address
000 Attribute Memory
010 Common Memory
100 I/O Mode
110 True IDE Mode
111 Alternate True IDE Mode
CF Address Space
Attribute Memory Mode Space
Common Memory Mode Space
I/O Mode Space
True IDE Mode Space
True IDE Alternate Mode Space
Offset 0x00E0 0000
Offset 0x00C0 0000
Offset 0x0080 0000
Offset 0x0040 0000
Offset 0x0000 0000
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21.6.6.3 Read/Write Signals
In I/O mode and True IDE mode, the CompactFlash logic drives the read and write command signals of the SMC
on CFIOR and CFIOW signals, while the CFOE and CFWE signals are deactivated. Likewise, in com mon memo ry
mode and attr ibute mem ory mo de, th e SMC sig nals a re driven on the CFOE and CFWE signals, while the CFIOR
and CFIOW are deactivated. Figure 21-4 demonstrates a schematic representation of this logic.
Attribute memory mode, common memory mode and I/O mode are supported by setting the address setup and
hold time on the NCS4 (and/or NCS5) chip select to the appropriate values.
Figure 21-4. CompactFlash Read/Write Control Signals
Table 21-6. CFCE1 and CFCE2 Truth Table
Mode CFCE2 CFCE1 DBW Comment SMC Access Mode
Attribute Memory NBS1 NBS0 16 bits Access to Even Byte on D[7:0] Byte Select
Common Memory NBS1 NBS0 16 bits Access to Even Byte on D[7:0]
Access to Odd Byte on D[15:8] Byte Select
1 0 8 bits Access to Odd Byte on D[7:0]
I/O Mode NBS1 NBS0 16 bits Access to Even Byte on D[7:0]
Access to Odd Byte on D[15:8] Byte Select
1 0 8 bits Access to Odd Byte on D[7:0]
True IDE Mode
Task File 1 0 8 bits Access to Even Byte on D[7:0]
Access to Odd Byte on D[7:0]
Data Register 1 0 16 bits Access to Even Byte on D[7:0]
Access to Odd Byte on D[15:8] Byte Select
Alternate T rue IDE Mode
Control Register
Alternate Status Read 0 1 Don’t Care Access to Even Byte on D[7:0] Don’t Care
Drive Address 0 1 8 bits Access to Odd Byte on D[7:0]
Standby Mode or Address Space
is not assigned to CF 11–– –
SMC
NRD_NOE
NWR0_NWE
A23
CFIOR
CFIOW
CFOE
CFWE
1
1
CompactFlash Logic
External Bus Interface
1
1
1
0
A22
1
0
1
0
1
0
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21.6.6.4 Multiplexing of CompactFlash Signals on EBI Pins
Table 21-8 and Table 21-9 illustrate the multiplexing of the CompactFlash logic signals with other EBI signals on
the EBI pins. The EBI pins in Table 21-8 are strictly dedicated to the CompactFlash interface as soon as the
EBI_CS4A and/or EBI_CS5A bit(s) in the EBI_CSA register is/are set. These pins must not be used to drive any
other memory devices.
The EBI pins in Table 21-9 remain sha red between all memory areas when the corresponding CompactF lash
interface is enabled (EBI_CS4A = 1 and/or EBI_CS5A = 1).
Table 21-7. CompactFlash Mode Selection
Mode Base Address CFOE CFWE CFIOR CFIOW
Attribute Memory
Common Memory NRD NWR0_NWE 1 1
I/O Mode 1 1 NRD NWR0_NWE
True IDE Mode 0 1 NRD NWR0_NWE
Table 21-8. Dedicated Compac tFlash Interface Multiplexing
Pins
CompactFlash Signals EBI Signals
CS4A = 1 CS5A = 1 CS4A = 0 CS5A = 0
NCS4/CFCS0 CFCS0 NCS4
NCS5/CFCS1 CFCS1 NCS5
Table 21-9. Shared Compac tFlash Interface Multiplexing
Pins
Access to CompactFlash Device Access to Other EBI Devices
CompactFlash Signals EBI Signals
NRD/CFOE CFOE NRD
NWR0/NWE/CFWE CFWE NWR0/NWE
NWR1/NBS1/CFIOR CFIOR NWR1/NBS1
NWR3/NBS3/CFIOW CFIOW NWR3/NBS3
A25/CFRNW CFRNW A25
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21.6.6.5 Application Example
Figure 21-5 illustrates an examp le of a CompactFlash application. CFCS0 and CFRNW signals are not directly
connected to the Com pactFlash slot 0, but do control the dir ection and the output enable of th e buffers between
the EBI and the CompactFlash Device. The timing of the CFCS0 signal is identical to the NCS4 signal. Moreover,
the CFRNW signal remains valid throughout the transfer, as does the address bus. The CompactFlash _WAIT
signal is connected to the NWAIT input of the Static Memory Controller. For details on these waveforms and
timings, refer to Section 22. “Static Memory Controller (SMC)”.
Figure 21-5. CompactFlash Application Example
CompactFlash ConnectorEBI
D[15:0]
/OEDIR
_CD1
_CD2
/OE
D[15:0]
A25/CFRNW
NCS4/CFCS0
CD (PIO)
A[10:0]
A22/REG
NOE/CFOE
A[10:0]
_REG
_OE
_WE
_IORD
_IOWR
_CE1
_CE2
NWE/CFWE
NWR1/CFIOR
NWR3/CFIOW
CFCE1
CFCE2
_WAIT
NWAIT
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21.6.7 NAND Flash Support
External Bus Interface integrate circuitry that interfaces to NAND Flash devices.
21.6.7.1 External Bus Interface
The NAND Fla sh logic is driven by the Static Memory Controller on the NCS3 address space. Programming the
EBI_CS3A field in the EBI_CSA r egister to th e appropriate value enables the NAND Flash logic. For details on this
register, refer to Section 20. “SAM9XE Bus Matrix”. Access to an external NAND Flash device is then made by
accessing the address space reserved to NCS3 (i.e., between 0x4000 0000 and 0x4FFF FFFF).
The NAND Flash Logic drives the read and write command signals of the SMC on the NANDOE and NANDWE
signals when the NCS3 signal is active. NANDOE and NANDWE are invalidated as soon as the transfer address
fails to lie in the NCS3 ad dress space. See Fi gure 21- 6 for more informa tion. For details on the waveforms, refer to
Section 22. “Static Memory Controller (SMC)”.
Figure 21-6. NAND Flash Signal Multiplexing on EBI Pins
21.6.7.2 NAND Flash Signals
The address latch ena ble and co mmand latch enable sig nals on the NAND Fla sh device are dr iven by address b its
A22 and A21 of the EBI address bus. The user should note that any bit on the EBI address bus can also be used
for this purpose. The command, address or data words on the data bus of the NAND Flash device are
distinguished by using their address within the NCSx address space. The chip enable (CE) signal of the device
and the ready/busy (R/B) signals are connected to PIO lines. The CE signal then rema ins asserted even when
NCSx is not selected, preventing the device from returning to standby mode.
SMC
NRD_NOE
NWR0_NWE
NANDOE
NANDWE
NAND Flash Logic
NCSx
NANDWE
NANDOE
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Figure 21-7. NAND Flas h Application Example
Note: The External Bus Interface is also able to support 16-bit devices.
D[7:0]
ALE
NANDWE
NANDOE NOE
NWE
A[22:21]
CLE
AD[7:0]
PIO R/B
EBI
CE
NAND Flash
PIO
NCSx/NANDCS Not Connected
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21.7 Implementation Examples
The following hardware configurations are given for illustration only. The user should refer to the memory
manufacturer web site to check device availability.
21.7.1 16-bit SDRAM
Figure 21-8. Hardware Configuration - 16-bit SDRAM
21.7.1.1 Software Configuration - 16-bit SDRAM
The following configuration has to be performed:
Assign the EBI CS1 to the SDRAM controller by setting the bit EBI_CS1A in the EBI Chip Select Assignment
Register located in the bus matrix memory space .
Initialize the SDRAM Controller depending on the SDRAM device and system bus frequency.
The Data Bus Width is to be programmed to 16 bits.
The SDRAM initialization sequence is described in Section 23.4.1 “SDRAM Device Initialization”.
D13
D12
D8
D7
D3
D11
D2
D14
D4
D0
RAS
D1
D10
CAS
SDA10
SDCK
D9
SDWE
SDCKE
D5
D15
D6
A4
A9
A14
A5
A2
A6
A3
BA0
A10
A13
A8
BA1
A7
A11
A0
RAS
CAS
SDA10
SDWE
SDCKE
SDCK
CFIOR_NBS1_NWR1
SDCS_NCS1
BA0
BA1
D[0..15]
A[0..14]
3V3
1%6
1%6
(Not used A12)
C6 100NFC6 100NF
C4 100NFC4 100NF
U1U1
A0
23 A1
24 A2
25 A3
26 A4
29 A5
30 A6
31 A7
32 A8
33 A9
34 A10
22
BA0
20
A12
36
DQ0 2
DQ1 4
DQ2 5
DQ3 7
DQ4 8
DQ5 10
DQ6 11
DQ7 13
DQ8 42
DQ9 44
DQ10 45
DQ11 47
DQ12 48
DQ13 50
DQ14 51
DQ15 53
VDD 1
VSS 28
VSS 41
VDDQ 3
VDD 27
N.C
40
CLK
38
CKE
37
DQML
15 DQMH
39
CAS
17 RAS
18
WE
16 CS
19
VDDQ 9
VDDQ 43
VDDQ 49
VSSQ 6
VSSQ 12
VSSQ 46
VSSQ 52
VDD 14
VSS 54
A11
35
BA1
21
C2 100NFC2 100NF
C1 100NFC1 100NF
C5 100NFC5 100NF
C3 100NFC3 100NF
C7 100NFC7 100NF
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21.7.2 32-bit SDRAM
Figure 21-9. Hardware Configuration - 32-bit SDRAM
21.7.2.1 Software Configuration - 32-bit SDRAM
The following configuration has to be performed:
Assign the EBI CS1 to the SDRAM controller by setting the bit EBI_CS1A in the EBI Chip Select Assignment
Register located in the bus matrix memory space .
Initialize the SDRAM Controller depending on the SDRAM device and system bus frequency.
The Data Bus Width is to be programmed to 3 2 bits. The data lines D[16..31] are multiplexed with PIO lines and
thus the dedicated PIOs must be programmed in peripheral mode in the PIO controller.
The SDRAM initialization sequence is described in Section 23.4.1 “SDRAM Device Initialization”.
CAS
SDCKE
SDCK
RAS
SDWE
SDA10
D13
D18
D12
D22
D8
D7
D3
D28
D11 D26
D21
D2
D14
D4
D24
D0
D23
RAS
D27
D1
D19
D10
D31
D17
CAS
SDA10 D25
D29
D16
SDCK
D9
D20
SDWE
SDCKE
D5
D30
D15
D6
A5
BA0
A2
A11
A7
A4
A9
A14
A8
A1
A5
A2
BA1
A13
A6
A3A3
A10
BA0
A10
A13
A8
BA1
A6
A4
A14
A9
A7
A11
A0
RAS
CAS
SDA10
SDWE
SDCKE
SDCK
CFIOW_NBS3_NWR3CFIOR_NBS1_NWR1
SDCS_NCS1
BA0
BA1
D[0..31]
A[0..14]
3V33V3
1%6 1%6
1%61%6
(Not used A12)
C5 100NFC5 100NF C12 100NFC12 100NF
C14 100NFC14 100NF
C3 100NFC3 100NF C10 100NFC10 100NF
C8 100NFC8 100NF
C7 100NFC7 100NF
C6 100NFC6 100NF
C11 100NFC11 100NF
C13 100NFC13 100NF
C4 100NFC4 100NF
C2 100NFC2 100NF C9 100NFC9 100NF
U1U1
A0
23 A1
24 A2
25 A3
26 A4
29 A5
30 A6
31 A7
32 A8
33 A9
34 A10
22
BA0
20
A12
36
DQ0 2
DQ1 4
DQ2 5
DQ3 7
DQ4 8
DQ5 10
DQ6 11
DQ7 13
DQ8 42
DQ9 44
DQ10 45
DQ11 47
DQ12 48
DQ13 50
DQ14 51
DQ15 53
VDD 1
VSS 28
VSS 41
VDDQ 3
VDD 27
N.C
40
CLK
38
CKE
37
DQML
15 DQMH
39
CAS
17 RAS
18
WE
16 CS
19
VDDQ 9
VDDQ 43
VDDQ 49
VSSQ 6
VSSQ 12
VSSQ 46
VSSQ 52
VDD 14
VSS 54
A11
35
BA1
21
U2U2
A0
23 A1
24 A2
25 A3
26 A4
29 A5
30 A6
31 A7
32 A8
33 A9
34 A10
22
BA0
20
A12
36
DQ0 2
DQ1 4
DQ2 5
DQ3 7
DQ4 8
DQ5 10
DQ6 11
DQ7 13
DQ8 42
DQ9 44
DQ10 45
DQ11 47
DQ12 48
DQ13 50
DQ14 51
DQ15 53
VDD 1
VSS 28
VSS 41
VDDQ 3
VDD 27
N.C
40
CLK
38
CKE
37
DQML
15 DQMH
39
CAS
17 RAS
18
WE
16 CS
19
VDDQ 9
VDDQ 43
VDDQ 49
VSSQ 6
VSSQ 12
VSSQ 46
VSSQ 52
VDD 14
VSS 54
A11
35
BA1
21
C1 100NFC1 100NF
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
186
21.7.3 8-bit NAND Flash
Figure 21-10. Hardware Configuration - 8-bit NAND Flash
21.7.3.1 Software Configuration - 8-bit NAND Flash
The following configuration has to be performed:
Assign the EBI CS3 to the NAND Flash by setting the bit EBI_CS3A in the EBI Chip Select Assignment
Register located in the bus matrix memory space
Reserve A21 / A22 for ALE / CLE functions. Address and Command Latches are controlled respectively by
setting to 1 the address bit A21 and A22 during accesses.
Configure a PIO line as an input to manage the Ready/Busy signal.
Configure Static Memory Controller CS3 Setup, Pulse, Cycle and Mode accordingly to NAND Flash timing s,
the data bus width and the system bus frequency.
D6
D0
D3
D4
D2
D1
D5
D7
NANDOE
NANDWE
(ANY PIO)
(ANY PIO)
ALE
CLE
D[0..7]
3V3
3V3
C1
100NF
C1
100NF
U1U1
WE
18
N.C
6
VCC 37
CE
9
RE
8
N.C
20
WP
19
N.C
5
N.C
1N.C
2N.C
3N.C
4
N.C
21 N.C
22 N.C
23 N.C
24
R/B
7
N.C
26
N.C 27
N.C 28
I/O0 29
N.C 34
N.C 35
VSS 36
PRE 38
N.C 39
VCC 12
VSS 13
ALE
17
N.C
11 N.C
10
N.C
14 N.C
15
CLE
16
N.C
25
N.C 33
I/O1 30
I/O3 32
I/O2 31
N.C 47
N.C 46
N.C 45
I/O7 44
I/O6 43
I/O5 42
I/O4 41
N.C 40
N.C 48
R1 10K
R1 10K
R2 10KR2 10K
C2
100NF
C2
100NF
187
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
21.7.4 16-bit NAND Flash
Figure 21-11. Hardware Configuration - 16-bit NAND Flash
21.7.4.1 Software Configuration - 16-bit NAND Flash
The software configuration is the same as for an 8-bit NAND Flash except the data bus width programmed in the
SMC MODE Register.
D6
D0
D3
D4
D2
D1
D5
D7
D14
D8
D11
D12
D10
D9
D13
D15
NANDOE
NANDWE
(ANY PIO)
ALE
CLE
D[0..15]
(ANY PIO)
3V3
3V3
C1
100NF
C1
100NF
U1U1
WE
18
N.C
6
VCC 37
CE
9
RE
8
N.C
20
WP
19
N.C
5
N.C
1N.C
2N.C
3N.C
4
N.C
21 N.C
22 N.C
23 N.C
24
R/B
7
I/O0 26
I/O8 27
I/O1 28
I/O9 29
N.C
34 N.C
35
N.C 36
PRE 38
N.C 39
VCC 12
VSS 13
ALE
17
N.C
11 N.C
10
N.C
14 N.C
15
CLE
16
VSS 25
I/O11 33
I/O2 30
I/O3 32
I/O10 31
I/O15 47
I/O7 46
I/O14 45
I/O6 44
I/O13 43
I/O5 42
I/O12 41
I/O4 40
VSS 48
R1 10K
R1 10K
R2 10KR2 10K
C2
100NF
C2
100NF
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
188
21.7.5 NOR Flash on NCS0
Figure 21-12. Hardware Configu ration - NOR Flash on NCS0
21.7.5.1 Software Configuration - NOR Flash on NCS0
The default configuration for the Static Memory Controller, byte select mode, 16-bit data bus, Read/Write
controlled by Chip Select, allows boot on 16-bit non-volatile memory at slow clock.
For another configuration, configure the Static Memory Controller CS0 Setup, Pulse, Cycle and Mode depending
on Flash timings and system bus frequency.
A21
A22
A1
A2
A3
A4
A5
A6
A7
A8
A15
A9
A12
A13
A11
A10
A14
A16
D6
D0
D3
D4
D2
D1
D5
D7
D14
D8
D11
D12
D10
D9
D13
D15
A17
A20
A18
A19
D[0..15]
A[1..22]
NRST
NWE
NCS0
NRD
3V3
3V3
C1
100NF
C1
100NF
U1U1
A0
25 A1
24 A2
23 A3
22 A4
21 A5
20 A6
19 A7
18 A8
8A9
7A10
6A11
5A12
4A13
3A14
2A15
1A16
48 A17
17 A18
16
A21
9A20
10 A19
15
WE
11 RESET
12
WP
14
OE
28 CE
26 VPP
13
DQ0 29
DQ1 31
DQ2 33
DQ3 35
DQ4 38
DQ5 40
DQ6 42
DQ7 44
DQ8 30
DQ9 32
DQ10 34
DQ11 36
DQ12 39
DQ13 41
DQ14 43
DQ15 45
VCCQ 47
VSS 27
VSS 46
VCC 37
C2
100NF
C2
100NF
189
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
21.7.6 Compact Flash
Figure 21-13. Hardware Configu ration - Compa ct Flash
D15
D14
D13
D12
D10
D11
D9
D8
D7
D6
D5
D4
D2
D1
D0
D3
A10
A9
A8
A7
A3
A4
A5
A6
A0
A2
A1
CD1
CD2
CD2
CD1
WE
OE
IOWR
IORD
CE2
CE1
REG
WAIT#
RESET
CF_D3
CF_D2
CF_D1
CF_D0
CF_D7
CF_D6
CF_D5
CF_D4
CF_D11
CF_D10
CF_D9
CF_D8
CF_D15
CF_D14
CF_D13
CF_D12
CF_A10
CF_A9
CF_A8
CF_A7
CF_A6
CF_A5
CF_A4
CF_A3
CF_A2
CF_A1
CF_A0
REG
WE
OE
IOWR
IORD
CF_A10
CF_A9
CF_A8
CF_A7
CF_A6
CF_A5
CF_A4
CF_A3
CF_A2
CF_A1
CF_A0
CF_D4
CF_D13
CF_D15
CF_D14
CF_D12
CF_D11
CF_D10
CF_D9
CF_D8
CF_D7
CF_D6
CF_D5
CF_D3
CF_D2
CF_D1
CF_D0
CE2
CE1
RESET
RDY/BSY
RDY/BSY
WAIT#
CFWE
(ANY PIO)
A25/CFRNW
D[0..15]
A[0..10]
CFCSx
A22/REG
CFOE
CFIOW
CFIOR
NWAIT
(ANY PIO)
CFCE2
CFCE1
(ANY PIO)
3V3
3V3
3V3
3V3
3V3
3V3
&$5''(7(&7
CFIRQ
CFRST
MEMORY & I/O MODE
(CFCS0 or CFCS1)
MN2A
SN74ALVC32
MN2A
SN74ALVC32
31
2
C2
100NF
C2
100NF
MN1D
74ALVCH32245
MN1D
74ALVCH32245
4DIR
T3 4OE
T4
4A1
N5 4A2
N6 4A3
P5 4A4
P6 4A5
R5 4A6
R6 4A7
T6 4A8
T5
4B1 N2
4B2 N1
4B3 P2
4B4 P1
4B5 R2
4B6 R1
4B7 T1
4B8 T2
MN1C
74ALVCH32245
MN1C
74ALVCH32245
3DIR
J3 3OE
J4
3A1
J5 3A2
J6 3A3
K5 3A4
K6 3A5
L5 3A6
L6 3A7
M5 3A8
M6
3B1 J2
3B2 J1
3B3 K2
3B4 K1
3B5 L2
3B6 L1
3B7 M2
3B8 M1
R2
47K
R2
47K
MN3B
SN74ALVC125
MN3B
SN74ALVC125
6
4
5
R147K
R147K
MN1B
74ALVCH32245
MN1B
74ALVCH32245
2DIR
H3 2OE
H4
2A1 E5
2A2 E6
2A3 F5
2A4 F6
2A5 G5
2A6 G6
2A7 H5
2A8 H6
2B1
E2 2B2
E1 2B3
F2 2B4
F1 2B5
G2 2B6
G1 2B7
H2 2B8
H1
VCC
GND
MN4
SN74LVC1G125-Q1
VCC
GND
MN4
SN74LVC1G125-Q1
5 1
2
3
4
MN3A
SN74ALVC125
MN3A
SN74ALVC125
3
1
2
R3
10K
R3
10K
MN2B
SN74ALVC32
MN2B
SN74ALVC32
6
4
5
MN3C
SN74ALVC125
MN3C
SN74ALVC125
89
10
R4
10K
R4
10K
C1
100NF
C1
100NF
J1
N7E50-7516VY-20
J1
N7E50-7516VY-20
GND 1
D3
2D4
3D5
4D6
5D7
6
CE1#
7
A10
8
OE#
9
A9
10 A8
11 A7
12
VCC 13
A6
14 A5
15 A4
16 A3
17 A2
18 A1
19 A0
20
D0
21 D1
22 D2
23
WP
24
CD2#
25 CD1#
26
D11
27 D12
28 D13
29 D14
30 D15
31
CE2#
32
VS1# 33
IORD#
34 IOWR#
35
WE#
36
RDY/BSY 37
VCC 38
CSEL# 39
VS2# 40
RESET
41
WAIT#
42
INPACK# 43
REG#
44
BVD2 45
BVD1 46
D8
47 D9
48 D10
49 GND 50
MN1A
74ALVCH32245
MN1A
74ALVCH32245
1A1 A5
1A2 A6
1A3 B5
1A4 B6
1A5 C5
1A6 C6
1A7 D5
1A8 D6
1DIR
A3 1OE
A4
1B1
A2 1B2
A1 1B3
B2 1B4
B1 1B5
C2 1B6
C1 1B7
D2 1B8
D1
MN3D
SN74ALVC125
MN3D
SN74ALVC125
11 12
13
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
190
21.7.6.1 Software Configuration - Compact Flash
The following configuration has to be performed:
Assign the EBI CS4 and/or EBI_CS 5 to the Co mpactFlash Slot 0 or/a nd Slot 1 by setting th e bit EBI_CS4A
or/and EBI_CS5A in the EBI Chip Select Assignment Register located in the bus matrix memory space.
The address line A23 is to select I/O ( A23 = 1) or Me mory mode (A23 = 0) and the address line A22 for REG
function.
A23, CFRNW, CFS0, CFCS1, CFCE1 and CFCE2 signals are multiplexed with PIO lines and thus the
dedicated PIOs must be programmed in peripheral mode in the PIO controller.
Configure a PIO line as an output for CFRST and two others as an input for CFIRQ and CARD DETECT
functions respectively.
Configure SMC CS4 a nd/or SMC_CS5 (for Slot 0 or 1 ) Setup, Pulse, Cycle and Mode acco rding to Comp act
Flash timings and system bus frequency.
191
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
21.7.7 Compact Flash True IDE
Figure 21-14. Hardware Configuration - Compact Flash True IDE
D15
D14
D13
D12
D10
D11
D9
D8
D7
D6
D5
D4
D2
D1
D0
D3
A10
A9
A8
A7
A3
A4
A5
A6
A0
A2
A1
CD1
CD2
CF_D3
CF_D2
CF_D1
CF_D0
CF_D7
CF_D6
CF_D5
CF_D4
CF_D11
CF_D10
CF_D9
CF_D8
CF_D15
CF_D14
CF_D13
CF_D12
RESET#
CF_A10
CF_A9
CF_A8
CF_A7
CF_A6
CF_A5
CF_A4
CF_A3
CF_A2
CF_A1
CF_A0
CD2
CD1
IOWR
IORD
CE2
CE1
REG
WE
OE
IOWR
IORD
IORDY
CF_A0
CF_A2
CF_A1
CF_D4
CF_D13
CF_D15
CF_D14
CF_D12
CF_D11
CF_D10
CF_D9
CF_D8
CF_D7
CF_D6
CF_D5
CF_D3
CF_D2
CF_D1
CF_D0
CE2
CE1
RESET#
INTRQ
IORDY
INTRQ
CFWE
(ANY PIO)
A25/CFRNW
D[0..15]
A[0..10]
CFCSx
A22/REG
CFOE
CFIOW
CFIOR
NWAIT
(ANY PIO)
CFCE2
CFCE1
(ANY PIO)
3V3
3V3
3V3
3V3
3V3
3V3
3V3
&$5''(7(&7
CFIRQ
CFRST
TRUE IDE MODE
(CFCS0 or CFCS1)
C2
100NF
C2
100NF
MN1D
74ALVCH32245
MN1D
74ALVCH32245
4DIR
T3 4OE
T4
4A1
N5 4A2
N6 4A3
P5 4A4
P6 4A5
R5 4A6
R6 4A7
T6 4A8
T5
4B1 N2
4B2 N1
4B3 P2
4B4 P1
4B5 R2
4B6 R1
4B7 T1
4B8 T2
VCC
GND
MN4
SN74LVC1G125-Q1
VCC
GND
MN4
SN74LVC1G125-Q1
5 1
2
3
4
MN3C
SN74ALVC125
MN3C
SN74ALVC125
89
10
R4
10K
R4
10K
MN1C
74ALVCH32245
MN1C
74ALVCH32245
3DIR
J3 3OE
J4
3A1
J5 3A2
J6 3A3
K5 3A4
K6 3A5
L5 3A6
L6 3A7
M5 3A8
M6
3B1 J2
3B2 J1
3B3 K2
3B4 K1
3B5 L2
3B6 L1
3B7 M2
3B8 M1
R3
10K
R3
10K
J1
N7E50-7516VY-20
J1
N7E50-7516VY-20
GND 1
D3
2D4
3D5
4D6
5D7
6
CS0#
7
A10
8
ATA SEL#
9
A9
10 A8
11 A7
12
VCC 13
A6
14 A5
15 A4
16 A3
17 A2
18 A1
19 A0
20
D0
21 D1
22 D2
23
IOIS16#
24
CD2#
25 CD1#
26
D11
27 D12
28 D13
29 D14
30 D15
31
CS1#
32
VS1# 33
IORD#
34 IOWR#
35
WE#
36
INTRQ 37
VCC 38
CSEL# 39
VS2# 40
RESET#
41
IORDY
42
INPACK# 43
REG#
44
DASP# 45
PDIAG# 46
D8
47 D9
48 D10
49 GND 50
MN1A
74ALVCH32245
MN1A
74ALVCH32245
1A1 A5
1A2 A6
1A3 B5
1A4 B6
1A5 C5
1A6 C6
1A7 D5
1A8 D6
1DIR
A3 1OE
A4
1B1
A2 1B2
A1 1B3
B2 1B4
B1 1B5
C2 1B6
C1 1B7
D2 1B8
D1
MN1B
74ALVCH32245
MN1B
74ALVCH32245
2DIR
H3 2OE
H4
2A1 E5
2A2 E6
2A3 F5
2A4 F6
2A5 G5
2A6 G6
2A7 H5
2A8 H6
2B1
E2 2B2
E1 2B3
F2 2B4
F1 2B5
G2 2B6
G1 2B7
H2 2B8
H1
MN2A
SN74ALVC32
MN2A
SN74ALVC32
31
2
C1
100NF
C1
100NF
R2
47K
R2
47K
R147K
R147K
MN3B
SN74ALVC125
MN3B
SN74ALVC125
6
4
5
MN3D
SN74ALVC125
MN3D
SN74ALVC125
11 12
13
MN2B
SN74ALVC32
MN2B
SN74ALVC32
6
4
5
MN3A
SN74ALVC125
MN3A
SN74ALVC125
3
1
2
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
192
21.7.7.1 Software Configuration - Compact Flash True IDE
The following configuration has to be performed:
Assign the EBI CS4 and/or EBI_CS 5 to the Co mpactFlash Slot 0 or/a nd Slot 1 by setting th e bit EBI_CS4A
or/and EBI_CS5A in the EBI Chip Select Assignment Register located in the bus matrix memory space.
The address line A21 is to select Alternate True IDE (A21 = 1) or True IDE (A21 = 0) modes.
CFRNW, CFS0, CFCS1, CFCE1 and CFCE2 signals are multiplexed with PIO lines and thus the dedica ted
PIOs must be programmed in peripheral mode in the PIO controller.
Configure a PIO line as an output for CFRST and two others as an input for CFIRQ and CARD DETECT
functions respectively.
Configure SMC CS4 a nd/or SMC_CS5 (for Slot 0 or 1 ) Setup, Pulse, Cycle and Mode acco rding to Comp act
Flash timings and system bus frequency.
193
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
22. Static Memory Controller (SMC)
22.1 Description
The Static Memory Controller ( SMC) g ene ra tes the signa ls that co ntro l th e access to th e exter nal m emory de vices
or peripheral devices. It has 8 Chip Selects and a 26-bit address bus. The 32-bit data bus can be configured to
interface with 8-, 16-, or 32-bit exte rnal devices. Separate read and write contr ol signals allow for direct memory
and peripheral interfacing. Read and write signal waveforms are fully parametrizable.
The SMC can manage wait requests from external devices to extend the current access. The SMC is provided with
an automatic slow clock mode. In slow clock mode, it switches from user-programmed waveforms to slow-rate
specific waveforms on read and write signals. The SMC supports asynchronous burst read in page mode access
for page size up to 32 bytes.
22.2 I/O Lines Description
22.3 Multiplexed Signals
Table 22-1. I/O Line Description
Name Description Type Active Level
NCS[7:0] Static Memory Controller Chip Select Line s Output Low
NRD Read Signal Output Low
NWR0/NWE Write 0/Write Enable Signal Output Low
A0/NBS0 Address Bit 0/Byte 0 Select Signal Output Low
NWR1/NBS1 Write 1/Byte 1 Select Signal Output Low
A1/NWR2/NBS2 Address Bit 1/Write 2/Byte 2 Select Signal Output Low
NWR3/NBS3 Write 3/Byte 3 Select Signal Output Low
A[25:2] Address Bus Output
D[31:0] Data Bus I/O
NWAIT External Wait Signal Input Low
Table 22-2. Static Memory Con t roller (SMC) Multiplexed Signals
Multiplexed Signals Related Function
NWR0 NWE Byte-write or byte-select access, see “Byte Write or Byte Select Access” on page 195
A0 NBS0 8-bit or 16-/32-bit data bus, see “Data Bus Width” on page 195
NWR1 NBS1 Byte-write or byte-select access see “Byte Write or Byte Select Access” on page 195
A1 NWR2 NBS2 8-/16-bit or 32-bit data bus, see “D ata Bus Width” on page 195.
Byte-write or byte-select access, see “Byte Write or Byte Select Access” on page 195
NWR3 NBS3 Byte-write or byte-select access see “Byte Write or Byte Select Access” on page 195
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
194
22.4 Application Example
22.4.1 Hardware Interface
Figure 22-1. SMC Co nn ections to Static Memory Devices
22.5 Product Dependencies
22.5.1 I/O Lines
The pins used for interfacing the Static Memory Controller may be multiplexed with the PIO lines. The progra mmer
must first program the PIO controller to assign the Static Memory Controller pins to their peripheral function. If I/O
Lines of the SMC are not used by the application, they can be used for other purposes by the PIO Controller.
Static Memory
Controller
D0-D31
A2 - A25
A0/NBS0
NWR0/NWE
NWR1/NBS1
A1/NWR2/NBS2
NWR3/NBS3
128K x 8
SRAM
D0 - D7
A0 - A16
OE
WE
CS
D0 - D7 D8-D15
A2 - A18
128K x 8
SRAM
D0-D7
CS
D16 - D23 D24-D31
128K x 8
SRAM
D0-D7
CS
NWR1/NBS1
NWR3/NBS3
NRD
NWR0/NWE
128K x 8
SRAM
D0 - D7
OE
WE
CS
NRD
A1/NWR2/NBS2
NCS0
NCS1
NCS2
NCS3
NCS4
NCS5
NCS6
NCS7
A2 - A18
A0 - A16
NRD OE
WE
OE
WE
NRD
A2 - A18
A0 - A16
A2 - A18
A0 - A16
195
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
22.6 External Memory Mapping
The SMC provides up to 26 address lines, A[25:0]. T his allows each chip select line to address up to 64 MB of
memory.
If the physical memory device connected on one chip select is smaller than 64 MB, it wraps around and appear s to
be repeated within this space. The SMC correctly handles any valid access to the memory device within the page
(see Figur e 22-2).
A[25:0] is only significant for 8-bit memory, A[25:1] is used for 16-bit memory, A[25:2] is used for 32-bit memory.
Figure 22-2. Memory Connections for Eight External Devices
22.7 Connection to External Devices
22.7.1 Data Bus Width
A data bus width of 8, 16, or 32 bits ca n be selected for each chip select. This option is con trolled by th e field DBW
in SMC_MODE (Mode Register) for the corresponding chip select.
Figure 22-3 shows how to connect a 512K x 8-bit memory on NCS2. Figure 22-4 shows how to connect a 512K x
16-bit memory on NCS2. Figure 22-5 shows two 16-bit memories connected as a single 32-bit memory
22.7.2 Byte Write or Byte Select Access
Each chip select with a 16-bit or 32-bit data bus can operate with one of two different types of write access: byte
write or byte select access. This is controlled by the BAT field of the SMC_MODE register for the corresponding
chip select.
NRD
NWE
A[25:0]
D[31:0]
8 or 16 or 32
Memory Enable
Memory Enable
Memory Enable
Memory Enable
Memory Enable
Memory Enable
Memory Enable
Memory Enable
Output Enable
Write Enable
A[25:0]
D[31:0] or D[15:0] or
D[7:0]
NCS3
NCS0
NCS1
NCS2
NCS7
NCS4
NCS5
NCS6
NCS[0] - NCS[7]
SMC
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Figure 22-3. Memory Conn ection for an 8-bit Data Bus
Figure 22-4. Memory Connection for a 16-b it Data Bus
Figure 22-5. Memory Connection for a 32-bit Data Bus
SMC
A0
NWE
NRD
NCS[2]
A0
Write Enable
Output Enable
Memory Enable
D[7:0] D[7:0]
A[18:2]
A[18:2]
A1 A1
SMC NBS0
NWE
NRD
NCS[2]
Low Byte Enable
Write Enable
Output Enable
Memory Enable
NBS1 High Byte Enable
D[15:0] D[15:0]
A[19:2] A[18:1]
A[0]A1
D[31:16]
SMC NBS0
NWE
NRD
NCS[2]
NBS1
D[15:0]
A[20:2]
D[31:16]
NBS2
NBS3
Byte 0 Enable
Write Enable
Output Enable
Memory Enable
Byte 1 Enable
D[15:0]
A[18:0]
Byte 2 Enable
Byte 3 Enable
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22.7.2.1Byte Write Access
Byte write access supports one byte write signal per byte of the data bus and a single read signal.
Note that the SMC does not allow boot in Byte Write Access mode.
For 16-bit devices: the SMC provides NWR0 and NWR1 write signals for respectively byte0 (lower byte) and
byte1 (upper byte) of a 16-bit bus. One single read signal (NRD) is provided.
Byte Write Access is used to connect 2 x 8-bit devices as a 16-bit memory.
For 32-bit devices: NWR0, NWR1, NWR2 and NWR3, are the write signals of byte0 (lower byte), byte1,
byte2 and byte 3 (upper byte) respectively. One single read signal (NRD) is provided.
Byte Write Access is used to connect 4 x 8-bit devices as a 32-bit memory.
Byte Write option is illustrated on Figure 22-6.
22.7.2.2Byte Select Access
In this mode, read/write operations can be enabled/disabled at a byte level. One byte-select line per byte of the
data bus is provided. One NRD and one NWE signal control read and write.
For 16-bit devices: the SMC provides NBS0 and NBS1 selection signals for respectively byte0 (lower byte)
and byte1 (upper byte) of a 16-bit bus.
Byte Select Access is used to connect one 16-bit device.
For 32-bit devices: NBS0, NBS1, NBS2 and NBS3, are the selection signals of byte0 (lower byte), byte1,
byte2 and byte 3 (upper byte) respectively. Byte Select Access is used to connect two 16-bit devices.
Figure 22-7 shows how to connect two 16-bit devices on a 32-bit data bus in Byte Select Access mode, on NCS3
(BAT = Byte Select Access).
Figure 22-6. Connection of 2 x 8-bit Devices on a 16-bit Bus: Byte Write Option
SMC A1
NWR0
NRD
NCS[3]
Write Enable
Read Enable
Memory Enable
NWR1
Write Enable
Read Enable
Memory Enable
D[7:0] D[7:0]
D[15:8]
D[15:8]
A[24:2]
A[23:1]
A[23:1]
A[0]
A[0]
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22.7.2.3Signal Multiplexing
Depending on the BAT, only the write signals or the byte select signals are used. To save IOs at the external bus
interface, control signals at the SMC interface are multiplexed. Table 22- 3 shows signal multiplexing depending on
the data bus widt h an d th e byt e ac ce ss typ e.
For 32-bit devices, bits A0 and A1 are unused. For 16-bit devices, bit A0 of addre ss is un used. When By te Select
Option is selected, NWR1 to NWR3 are unused. When Byte Write option is selected, NBS0 to NBS3 are unused.
Figure 22-7. Connection of 2x16-bit Data Bus on a 32-bit Data Bus (Byte Select Option)
SMC
NWE
NRD
NCS[3]
Write Enable
Read Enable
Memory Enable
NBS0
D[15:0] D[15:0]
D[31:16]
A[25:2] A[23:0]
Write Enable
Read Enable
Memory Enable
D[31:16]
A[23:0]
Low Byte Enable
High Byte Enable
Low Byte Enable
High Byte Enable
NBS1
NBS2
NBS3
Table 22-3. SMC Multiplexed Signal Tra nslation
Signal Name 32-bit Bus 1 6-bit Bus 8-bit Bus
Device Type 1 x 32-bit 2 x 16-bit 4 x 8-bit 1 x 16-bit 2 x 8-bit 1 x 8-bit
Byte Access Type (BAT) Byte Select Byte Select Byte Write Byte Select Byte Write
NBS0_A0 NBS0 NBS0 NBS0 A0
NWE_NWR0 NWE NWE NWR0 NWE NWR0 NWE
NBS1_NWR1 NBS1 NBS1 NWR1 NBS1 NWR1
NBS2_NWR2_A1 NBS2 NBS2 NWR2 A1 A1 A1
NBS3_NWR3 NBS3 NBS3 NWR3
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22.8 Standard Read and Write Protocols
In the following sections, the byte access type is not considered. Byte select lines (NBS0 to NBS3) always have
the same timing as the A addre ss b us. NWE r epresen ts e ither the NWE signal in byte select access type or one of
the byte write lines (NWR0 to NWR3) in byte write access type. NWR0 to NWR3 have the same timings and
protocol as NWE. In the same way, NCS represents one of the NCS[0..7] chip select lines.
22.8.1 Read Waveforms
The read cycle is shown on Figure 22-8.
The read cycle starts with the address setting on the memory address bus, i.e.:
{A[25:2], A1, A0} for 8-bit devices
{A[25:2], A1} for 16-bit devices
A[25:2] for 32-bit devices.
Figure 22-8. Standard Read Cycle
22.8.1.1NRD Waveform
The NRD signal is characterized by a setup timing, a pulse width and a hold timing.
1. NRD_SETUP: the NRD setup time is defined as the setup of address before the NRD falling edge;
2. NRD_PULSE: the NRD pulse length is the time between NRD falling edge and NRD rising edge;
3. NRD_HOLD: the NRD hold time is defined as the hold time of address after the NRD rising edge.
22.8.1.2NCS Waveform
Similarly, the NCS signal can be divided into a setup time, pulse length and hold time:
1. NCS_RD_SETUP: the NCS setup time is defined as the setup time of address before the NCS falling edge.
2. NCS_RD_PULSE: the NCS pulse length is the time between NCS falling edge and NCS rising edge;
3. NCS_RD_HOLD: the NCS hold time is defined as the hold time of address after the NCS rising edge.
A[25:2]
NBS0,NBS1,
NBS2,NBS3,
A0, A1
NCS
NRD_SETUP NRD_PULSE NRD_HOLD
MCK
NRD
D[31:0]
NCS_RD_SETUP NCS_RD_PULSE NCS_RD_HOLD
NRD_CYCLE
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22.8.1.3Read Cycle
The NRD_CYCLE time is defined as the total duration of the read cycle, i.e., from the time wher e address is se t on
the address bus to the point where address may change. The total read cycle time is equal to :
NRD_CYCLE = NRD_SETUP + NRD_PULSE + NRD_HOLD
= NCS_RD_SETUP + NCS_RD_PULSE + NCS_RD_HOLD
All NRD and NCS timings are d efined separate ly for each ch ip select as an integer num ber of Master Clo ck cycles.
To ensure that the NRD and NCS timings are coherent, user must define the total read cycle instead of the hold
timing. NRD_CYCLE implicitly defines the NRD hold time and NCS hold time as:
NRD_HOLD = NRD_CYCLE - NRD SETUP - NRD PULSE
NCS_RD_HOLD = NRD_CYCLE - NCS_RD_SETUP - NCS_RD_PULSE
22.8.1.4Null Delay Setup and Hold
If null setup and hold parameters are programmed for NRD and/or NCS, NRD and NCS remain active continuously
in case of consecutive read cycles in the same memory (see Figure 22 -9).
Figure 22-9. No Setup, No Hold On NRD and NCS Read Signals
22.8.1.5Null Pulse
Programming null pulse is not permitted. Pulse must be at least set to 1. A null value leads to unpredictable
behavior.
MCK
NRD_PULSE
NCS_RD_PULSE
NRD_CYCLE
NRD_PULSE NRD_PULSE
NCS_RD_PULSE NCS_RD_PULSE
NRD_CYCLE NRD_CYCLE
A[25:2]
NBS0,NBS1,
NBS2,NBS3,
A0, A1
NCS
NRD
D[31:0]
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22.8.2 Read Mode
As NCS and NRD waveforms are de fined ind epe ndently of o ne other, the SMC ne eds to know whe n th e rea d d ata
is available on the data bus. The SMC d oes not compare NCS and NRD timings to know which signal rises first.
The READ_MODE parameter in the SMC_MODE register of the corresponding chip select indicates which signal
of NRD and NCS controls the read operation.
22.8.2.1Read is Controlled by NRD (READ_MODE = 1):
Figure 22-10 shows the waveforms of a read operation of a typical asynchronous RAM. The read data is available
tPACC after the falling edge of NRD, and turns to ‘Z’ after the rising edge of NRD. In this case, the READ_MODE
must be set to 1 (read is controlled by NRD), to indicate that data is availab le with the rising edge of NRD. The
SMC samples the read data internally on the rising edge of Master Clock that generates the rising edge of NRD,
whatever the programmed waveform of NCS may be.
Figure 22-10. READ_MODE = 1: Data is sampled by SMC before the rising edge of NRD
Data Sampling
tPACC
MCK
A[25:2]
NBS0,NBS1,
NBS2,NBS3,
A0, A1
NCS
NRD
D[31:0]
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22.8.2.2Read is Controlled by NCS (READ_MODE = 0)
Figure 22-11 shows the typical read cycle of an LCD module. The read data is valid tPACC after the falling edge of
the NCS signal and remains valid until the rising edge of NCS. Data must be sampled when NCS is raised. In that
case, the READ_MODE must be set to 0 (read is controlled by NCS): the SMC internally samples the data on the
rising edge of Master Clock that gener ates the rising edge of NCS, whatever the programmed waveform of NRD
may be.
Figure 22-11. READ_MODE = 0: Data is sampled by SMC before the rising edge of NCS
Data Sampling
tPACC
MCK
D[31:0]
A[25:2]
NBS0,NBS1,
NBS2,NBS3,
A0, A1
NCS
NRD
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22.8.3 Write Waveforms
The write protocol is similar to the read protocol. It is depicted in Figure 22-1 2. The write cycle starts with the
address setting on the memory address bus.
22.8.3.1NWE Waveforms
The NWE signal is characterized by a setup timing, a pulse width and a hold timing.
1. NWE_SETUP: the NWE setup time is defined as the setup of address and data before the NWE falling
edge;
2. NWE_PULSE: The NWE pulse length is the time between NWE falling edge and NWE rising edge;
3. NWE_HOLD: The NWE hold time is defined as the hold time of address an d dat a af ter the NWE rising edge.
The NWE waveforms apply to all byte-write lines in Byte Write access mode: NWR0 to NWR3.
22.8.3.2NCS Waveforms
The NCS signal wa veforms in write operation are not the same that those ap plied in read operations, b ut are
separately defined:
1. NCS_WR_SETUP: the NCS setup time is defined as the setup time of address before the NCS fa lling edge.
2. NCS_WR_PULSE: the NCS pulse length is the time between NCS falling edge and NCS rising edge;
3. NCS_WR_HOLD: the NCS hold time is defined as the hold time of address after the NCS rising edge.
Figure 22-12. Write Cycle
22.8.3.3Write Cycle
The write_cycle time is defined as the total duration of the write cycle, that is, from the time where address is set
on the address bus to the point where address may change. The total write cycle time is equal to:
NWE_CYCLE = NWE_SETUP + NWE_PULSE + NWE_HOLD
= NCS_WR_SETUP + NCS_WR_PULSE + NCS_WR_HOLD
A
[25:2]
NBS0, NBS1,
NBS2, NBS3,
A0, A1
NCS
NWE_SETUP NWE_PULSE NWE_HOLD
MCK
NWE
NCS_WR_SETUP NCS_WR_PULSE NCS_WR_HOLD
NWE_CYCLE
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All NWE and NCS (write) timing s are d efined sepa rately fo r each chip select as an integer num ber of Master Clock
cycles. To ensure that the NWE an d NCS timi ngs are coher ent, the user must define the total write cycle instead of
the hold timing. This implicitly defines the NWE hold time and NCS (write) hold times as:
NWE_HOLD = NWE_CYCLE - NWE_SETUP - NWE_PULSE
NCS_WR_HOLD = NWE_CYCLE - NCS_WR_SETUP - NCS_WR_PULSE
22.8.3.4Null Delay Setup and Hold
If null setup parameters are programmed for NWE and/or NCS, NWE and/or NCS remain active continuously in
case of cons ecutive w rite cy cles in the sa me mem ory (se e Figure 22-13). However, for devices that perform write
operations on the rising edge of NWE or NCS, such as SRAM, either a setup or a hold must be programmed.
Figure 22-13. Null Setup and Hold Values of NCS and NW E in Write Cycle
22.8.3.5Null Pulse
Programming null pulse is not permitted. Pulse must be at least set to 1. A null value leads to unpredictable
behavior.
22.8.4 Write Mode
The WRITE_MODE paramet er in th e SMC_MODE re gister of the corresponding chip select indicates which signal
controls the writ e op er ation .
NCS
MCK
NWE,
NWR0, NWR1,
NWR2, NWR3
D[31:0]
NWE_PULSE
NCS_WR_PULSE
NWE_CYCLE
NWE_PULSE
NCS_WR_PULSE
NWE_CYCLE
NWE_PULSE
NCS_WR_PULSE
NWE_CYCLE
A
[25:2]
NBS0, NBS1,
NBS2, NBS3,
A0, A1
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22.8.4.1Write is Controlled by NWE (WRITE_MODE = 1):
Figure 22-1 4 shows the waveforms of a write operation with WRITE_MODE set to 1. The data is put on the bus
during the pulse and hold steps of the NWE signal. The in ternal data buffers are turne d out after the NWE_SETUP
time, and until the end of the write cycle, regardless of the programmed waveform on NCS.
Figure 22-14. WRITE_MODE = 1. The write operation is controlled by NWE
22.8.4.2Write is Controlled by NCS (WRITE_MODE = 0)
Figure 22-1 5 shows the waveforms of a write operation with WRITE_MODE set to 0. The data is put on the bus
during the pulse and hold steps of the NCS signal. The internal data buffers are turned out after the
NCS_WR_SETUP time , an d un til th e en d of the writ e cyc le, reg ardle ss of the pro gram m ed wav efo r m on NW E.
Figure 22-15. WRITE_MODE = 0. The write operation is controlled by NCS
MCK
D[31:0]
NCS
A
[25:2]
NBS0, NBS1,
NBS2, NBS3,
A0, A1
NWE,
NWR0, NWR1,
NWR2, NWR3
MCK
D[31:0]
NCS
NWE,
NWR0, NWR1,
NWR2, NWR3
A
[25:2]
NBS0, NBS1,
NBS2, NBS3,
A0, A1
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22.8.5 Coding Timing Parameters
All timing parameters ar e d efine d for one ch ip select and are grouped together in one SMC_ REGIST ER accor ding
to their type.
The SMC_SETUP register groups the definition of all setup parameters:
NRD_SETUP, NCS_RD_SETUP, NWE_SETUP, NCS_WR_SETUP
The SMC_PULSE register groups the definition of all pulse parameters:
NRD_PULSE, NCS_RD_PULSE, NWE_PULSE, NCS_WR_PULSE
The SMC_CYCLE register groups the definition of all cycle parameter s:
NRD_CYCLE, NWE_CYCLE
Table 22-4 shows how the timing parameters are coded and their permitted range.
22.8.6 Reset Values of Timing Parameters
Table 22-8, “Register Mapping,” gives the default value of timing parameters at reset.
22.8.7 Usage Restriction
The SMC does not check the validity of the user-programmed parameters. If the sum of SETUP and PULSE
parameters is larger than the corresponding CYCLE parameter, this leads to unpredictable behavior of the SMC.
For read operations:
Null but positive setup and hold of address and NRD and/or NCS can not be guaranteed at the memory interface
because of the propagation delay of theses signals through external logic and pads. If positive setup and hold
values must be verified, then it is strictly recommended to program non-null values so as to cover possible skews
between address, NCS and NRD signals.
For write operations:
If a null hold value is programmed on NWE, the SMC can guarantee a positive hold of address, byte select lines,
and NCS signal after the rising edge of NWE. This is true for WRITE_MODE = 1 only. See “Early Read Wait State”
on page 207.
For read and write operations: a null value for pulse parameters is forbidden and may lead to unpredictable
behavior.
In read and write cycles, the setup and hold time parameters are defined in reference to the address bus. For
external devices that require setup and hold time between NCS and NRD signals (read), or between NCS and
NWE signals (write), these setup and hold times must be converted into setup and hold times in reference to the
address bus.
Table 22-4. Coding and Range of Timing Parameters
Coded Valu e Number of Bits Effective Value
Permitted Range
Coded Value Effective Value
setup [5:0] 6 128 x setup[5] + setup[4:0] 0 ≤ 31 0 ≤ 128+31
pulse [6:0] 7 256 x pulse[6] + pulse[5:0] 0 ≤ 63 0 ≤ 256+63
cycle [8:0] 9 256 x cycle[8:7] + cycle[6:0] 0 ≤ 127 0 ≤ 256+127
0 ≤ 512+127
0 ≤ 768+127
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22.9 Automatic Wait States
Under certain cir c umstances, the SMC automatically inserts idle cycles between accesses to avoid bus co ntentio n
or operation conflict.
22.9.1 Chip Select Wait States
The SMC always inserts an idle cycle between 2 transfers on separate chip selects. This idle cycle ensures that
there is no bus contention between the de-activation of one device and the activatio n of the next one.
During chip select wait state, all control lines are turned inactive: NBS0 to NBS3, NWR0 to NWR3, NCS[0..7], NRD
lines are all set to 1.
Figure 22-16 illustrates a chip select wait state between access on Chip Select 0 and Chip Select 2.
Figure 22-16. Chip Selec t Wa it State between a Read Access on NCS0 an d a Write Access on NCS2
22.9.2 Early Read Wait State
In some cases, the SMC inserts a wait st ate cycle between a writ e access and a read acce ss to allow time for the
write cycle to end before the subsequent read cycle begins. This wait state is not generated in addition to a chip
select wait state. The early read cycle thus only occurs between a write and read access to the same memory
device (same chip select).
An early read wait state is automatically inserted if at least one of the following conditions is valid:
if the write controlling signal has no hold time and the read controlling signal has no setup time (Figure 22-
17).
in NCS write controlled mode (WRITE_MODE = 0), if there is no hold timing on the NCS signal and the
NCS_RD_SETUP parameter is set to 0, regardless of the read mode (Figure 22-18). The write operation
must end with a NCS rising edge. Without an Early Read Wait State, the write operation could not complete
properly.
A[25:2]
NBS0, NBS1,
NBS2, NBS3,
A0,A1
NCS0
NRD_CYCLE
Chip Select
Wait State
NWE_CYCLE
MCK
NCS2
NRD
NWE
D[31:0]
Read to Write
Wait State
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in NWE controlled mode (WRITE_MODE = 1) an d if ther e is no ho ld timing (NWE_HOLD = 0), th e feedba ck
of the write control signal is used to control address, data, chip select and byte select lines. If the external
write control signal is not inactivated as expected due to load capacitances, an Early Read Wait State is
inserted and address, data and control signals are maintained one more cycle. See Figure 22-19.
Figure 22-17. Early Read Wait State: Write with No Hold Followed by Read with No Setup
Figure 22-18. Early Read Wait State: NCS Controlled Write with No Hold Followed by a Read with No NCS Setup
write cycle Early Read
wait state
MCK
NRD
NWE
read cycle
no setup
no hold
D[31:0]
NBS0, NBS1,
NBS2, NBS3,
A0, A1
A[25:2]
write cycle
(WRITE_MODE = 0) Early Read
wait state
MCK
NRD
NCS
read cycle
(READ_MODE = 0 or READ_MODE = 1)
no setup
no hold
D[31:0]
NBS0, NBS1,
NBS2, NBS3,
A0,A1
A[25:2]
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Figure 22-19. Early Read Wait State: NWE-contro lled Write with No Hold Followed by a Read with one Set-up Cycle
22.9.3 Reload User Configuration Wait State
The user may change any of the configuration parameters by writing the SMC user interface.
When detecting that a new user configuration has been written in the user interface, the SMC inserts a wait state
before starting the next access. Th e so called “Reload User Configuration Wait State” is used by the SMC to load
the new set of parameters to apply to next accesses.
The Reload Configuration Wait State is not applied in addition to the Chip Select Wait State. If accesses before
and after re-programming the user interface are made to different devices (Chip Selects), then one single Chip
Select Wait State is applied.
On the ot her hand , if access es before and afte r writing th e user inte rface ar e made to the same device, a Reload
Configuration Wait State is inserted, even if the change does not concern the current Chip Select.
22.9.3.1User Procedure
To insert a Reload Configura tion Wait State, the SMC detects a write access to any SMC _MODE register of the
user interface. If the user only modifies timing registers (SMC_SETUP, SMC_PULSE, SMC_CYCLE registers) in
the user interface, he must validate the modification by writing the SMC_MODE, even if no change was made on
the mode parameters.
The user must not change the configuration parameters of an SMC Chip Select (Setup, Pulse, Cycle, Mode) if
accesses are performed on this CS during the modification. Any change of the Chip Sele ct parameters, while
fetching the code from a memory conn ected on this CS, may lead to unpredicta ble behavior. The instructions used
to modify the parameters of an SMC Chip Select can be executed from the internal RAM or from a memory
connected to another CS.
A
[25:2]
NBS0, NBS1,
NBS2, NBS3,
A0, A1
write cycle
(WRITE_MODE = 1) Early Read
wait state
MCK
NRD
internal write controlling signal
external write controlling signal
(NWE)
D[31:0]
read cycle
(READ_MODE = 0 or READ_MODE = 1)
no hold read setup = 1
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22.9.3.2Slow Clock Mode Transition
A Reload Configuration Wait State is also inserted when the Slo w Clock M ode is entered or exited , after the end of
the current transfer (see “Slow Clock Mode” on page 220).
22.9.4 Read to Write Wait State
Due to an internal mechanism, a wait cycle is always inserted between consecutive read and write SMC accesses.
This wait cycle is referred to as a read to write wait state in this document.
This wait cycle is applied in addition to chip select and reload user configuration wait states when they are to be
inserted. See Figure 22-16 on page 207.
22.10 Data Float Wait States
Some memory devices are slow to release the external bus. For such devices, it is necessary to add wait states
(data float wait states) after a read access:
before starting a read access to a different external memory
before starting a write access to the same device or to a different external one.
The Data Float Output Time (tDF) for each ex ternal memor y device is programmed in the TDF_ CYCLES field o f the
SMC_MODE register for the corresponding chip select. The value of TDF_CYCLES ind icates the n umber of data
float wait cycles (between 0 and 15) before the external device releases the bus, and represents the time allowed
for the data output to go to high impedance after the memory is disabled.
Data float wait states do not delay internal memory accesses. Hence, a single access to an external memory with
long tDF will not slow down the execution of a program from internal memory.
The data float wait states management depends on the READ_MODE and the TDF_MODE fields of the
SMC_MODE register for the corresponding chip select.
22.10.1 READ_MODE
Setting the READ_MODE to 1 indicates to the SMC that the NRD signal is responsible for turning off the tri-state
buffers of the external memory device. The Data Float Period then begins after the rising edge of the NRD signal
and lasts TDF_CYCLES MCK cycles.
When the read ope ration is controlled by the NCS sign al (READ_MODE = 0), the TD F field gives the number of
MCK cycles during which the data bus remains busy after the rising edge of NCS.
Figure 22-20 illustrates the Data Float Period in NRD-controlled mode (READ_MODE =1), assuming a data float
period of 2 cycles (TDF_CYCLES = 2). Figure 22-21 shows the read operation when controlled by NCS
(READ_MODE = 0) and the TDF_CYCLES parameter equals 3.
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Figure 22-20. TDF Period in NRD Controlled Read Access (TDF = 2)
Figure 22-21. TDF Period in NCS Controlled Read Operation (TDF = 3)
NBS0, NBS1,
NBS2, NBS3,
A0, A1
NCS
NRD controlled read operation
tpacc
MCK
NRD
D[31:0]
TDF = 2 clock cycles
A[25:2]
NCS
TDF = 3 clock cycles
tpacc
MCK
D[31:0]
NCS controlled read operation
A[25:2]
NBS0, NBS1,
NBS2, NBS3,
A0,A1
NRD
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22.10.2 TDF Optimization Enabled (TDF_MODE = 1)
When the TDF_MODE of the SMC_MODE register is set to 1 (TDF optimization is enabled), the SMC takes
advantage of the setup period of the next access to optimize the number of wait states cycle to insert.
Figure 22-22 shows a read access controlled by NRD, followed by a write access controlled by NWE, on Chip
Select 0. Chip Select 0 has been programmed with :
NRD_HOLD = 4; READ_MODE = 1 (NRD controlled)
NWE_SETUP = 3; WRITE_MODE = 1 (NWE controlled)
TDF_CYCLES = 6; TDF_MODE = 1 (optimization enabled).
Figure 22-22. TDF Optimization: No TDF wait states are inserted if the TDF period is over when the next access be gins
22.10.3 TDF Optimization Disabled (TDF_MODE = 0)
When optimization is disabled, tdf wait states ar e inserted at the end of the read transfer, so that the d ata float
period is ended when the second access begins. If the hold period of the read1 controlling signal overlaps the data
float period, no additional tdf wait states will be inserted.
Figure 22-23, Figure 22-24 and Figure 22-25 illustrate the cases:
read access followed by a read access on another chip select,
read access followed by a write access on another chip select,
read access followed by a write access on the same chip select,
with no TDF optimization.
A
[25:2]
NCS0
MCK
NRD
NWE
D[31:0]
Read to Write
Wait State
TDF_CYCLES = 6
read access on NCS0 (NRD controlled)
NRD_HOLD= 4
NWE_SETUP= 3
write access on NCS0 (NWE controlled)
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Figure 22-23. TDF Optimization Disabled (TDF Mode = 0). TDF wait states between 2 read accesses on different chip selec ts
Figure 22-24. TDF Mode = 0: TDF wait states betwe en a read and a write access on different chip selec ts
TDF_CYCLES = 6
TDF_CYCLES = 6 TDF_MODE = 0
(optimization disabled)
A[
25:2]
read1 cycle
Chip Select Wait State
MCK
read1 controlling signal
(NRD)
read2 controlling signal
(NRD)
D[31:0]
read1 hold = 1
read 2 cycle
read2 setup = 1
5 TDF WAIT STATES
NBS0, NBS1,
NBS2, NBS3,
A0, A1
TDF_CYCLES = 4
TDF_CYCLES = 4 TDF_MODE = 0
(optimization disabled)
A
[25:2]
read1 cycle
Chip Select
Wait State
Read to Write
Wait State
MCK
read1 controlling signal
(NRD)
write2 controlling signal
(NWE)
D[31:0]
read1 hold = 1
write2 cycle
write2 setup = 1
2 TDF WAIT STATES
NBS0, NBS1,
NBS2, NBS3,
A0, A1
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Figure 22-25. TDF Mode = 0: TDF wait states between read and write accesses on the same chip select
22.11 External Wait
Any access can be extended by an external device using the NWAIT input signal of the SMC. The EXNW_MODE
field of the SMC_MODE register on the corresponding chip select must be set to either to “10” (frozen mode) or
“11” (ready mode ). When the EXNW_MODE is set to “00” (disabled) , the NWAIT signal is simply ignored on the
corresponding chip select. The NWAIT signal delays the read or write operation in regards to the read or write
controlling signal, depending on the read and write modes of the corresponding chip select.
22.11.1 Restriction
When one of the EXNW_MODE is enabled, it is mandatory to program at least one hold cycle for the read/write
controlling signal. For that reason, the NWAIT signal cannot be used in Page Mode (“Asynchronous Page Mode”
on page 222), or in Slow Clock Mode (“Slow Clock Mode” on page 220).
The NWAIT signal is as sume d to be a respon se of th e exte rnal d evice to the read /w rite requ est of the SMC. Then
NWAIT is examined by the SMC only in the pulse state of the read or write controlling signal. The assertion of the
NWAIT signal outside the expected period has no impact on SMC behavior.
TDF_CYCLES = 5
TDF_CYCLES = 5
TDF_MODE = 0
(optimization disabled)
A
[25:2]
read1 cycle
Read to Write
Wait State
MCK
read1 controlling signal
(NRD)
write2 controlling signal
(NWE)
D[31:0]
read1 hold = 1
write2 cycle
write2 setup = 1
4 TDF WAIT STATES
NBS0, NBS1,
NBS2, NBS3,
A0, A1
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22.11.2 Frozen Mode
When the external device asserts the NWAIT signal (active low), and after internal synchronization of this signal,
the SMC state is frozen, i.e., SMC internal counters are frozen, and all control signals r emain unchanged. When
the resynchronized NWAIT signal is deasserted, the SMC completes the access, resuming the access from the
point where it was stopped. See Figure 22-26. This mode must be selected when the external device uses the
NWAIT signal to delay the access and to freeze the SMC.
The assertion of the NWAIT signal outside the expected period is ignored as illustrated in Figure 22-27.
Figure 22-26. Write Access with NWAIT Assertion in Frozen Mode (EXNW_MODE = 10)
EXNW_MODE = 10 (Frozen)
WRITE_MODE = 1 (NWE_controlled)
NWE_PULSE = 5
NCS_WR_PULSE = 7
A
[25:2]
MCK
NWE
NCS
432 1 1101
4563222210
Write cycle
D[31:0]
NWAIT
FROZEN STATE
NBS0, NBS1,
NBS2, NBS3,
A0,A1
internally synchronized
NWAIT signal
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Figure 22-27. Read Access with NWAIT Assertion in Frozen Mode (EXNW_MODE = 10)
EXNW_MODE = 10 (Frozen)
READ_MODE = 0 (NCS_controlled)
NRD_PULSE = 2, NRD_HOLD = 6
NCS_RD_PULSE =5, NCS_RD_HOLD =3
A
[25:2]
MCK
NCS
NRD
10
43
43
2
555
22 0 210
210
1
Read cycle
Assertion is ignored
NWAIT
internally synchronized
NWAIT signal
FROZEN STATE
NBS0, NBS1,
NBS2, NBS3,
A0,A1
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22.11.3 Ready Mode
In Ready mode (EXNW_MODE = 11), the SMC beha ves differently. Normally, the SMC begins the access by
down counting the setup and pulse counters of the read/write controlling signal. In the last cycle of the pulse
phase, the resynchronized NWAIT signal is examined.
If asserted, the SMC suspends the access as shown in Figure 22-28 and Figure 22-29. After deassertion, the
access is completed: the hold step of the access is performed.
This mode must be selected when the external device uses deassertion of the NWAIT signal to indicate its ability
to complete the read or write operation.
If the NWAIT signal is deasserted before the end of the pulse, or asserted after the end of the pulse of the
controlling read/write signal, it has no impact on the access length as shown in Figure 22-29.
Figure 22-28. NWAIT Assertion in Write Access: Ready Mode (EXNW_MODE = 11)
EXNW_MODE = 11 (Ready mode)
WRITE_MODE = 1 (NWE_controlled)
NWE_PULSE = 5
NCS_WR_PULSE = 7
A
[25:2]
MCK
NWE
NCS
432 1 000
456321110
Write cycle
D[31:0]
NWAIT
internally synchronized
NWAIT signal
Wait STATE
NBS0, NBS1,
NBS2, NBS3,
A0,A1