SPC560B54x SPC560B60x, SPC560B64x 32-bit MCU family built on the Power Architecture(R) for automotive body electronics applications Features High performance 64 MHz e200z0h CPU - 32-bit Power Architecture(R) technology CPU - Up to 60 DMIPs operation - Variable length encoding (VLE) Memory - Up to 1.5 MB on-chip Code Flash with ECC - 64 KB on-chip Data Flash with ECC - Up to 96 KB on-chip SRAM with ECC - 8-entry MPU Interrupts - 16 priority levels - Non-maskable interrupt (NMI) - Up to 51 external interrupts lines including 27 wake-up lines 16-channel eDMA (linked to PITs, DSPI, ADCs, eMIOS, LINFlex and I2C) GPIOs: 77 (LQFP100), 121 (LQFP144) and 149 (LQFP176) Timer units - 8-channel 32-bit periodic interrupt timer - 4-channel 32-bit system timer - System watchdog timer - Real-time clock timer eMIOS, 16-bit counter timed I/O units - Up to 64 channels with PWM/MC/IC/OC - Up to 10 counter basis - ADC diagnostic trigger via CTU One 10-bit and one 12-bit ADC with up to 53 channels - Extendable to 81 channels - Individual conversion registers - Cross triggering unit (CTU) Dedicated diagnostic module for lighting - Advanced PWM generation - Time-triggered diagnostics - PWM-synchronized ADC measurements On-chip CAN/UART bootstrap loader Communications interfaces September 2013 LQFP100 LQFP144 (14 x 14 x 1.4 mm) (20 x 20 x 1.4 mm) LQFP176 (24 x 24 x 1.4 mm) - Up to 6 FlexCAN (2.0B active) with 64 message buffers each - Up to 10 LINFlex/UART channels - Up to 6 buffered DSPI channels - I2C interface Clock generation - 4 to 16 MHz fast external crystal oscillator - 32 kHz slow external crystal oscillator - 16 MHz fast internal RC oscillator - 128 kHz slow internal RC oscillator for lowpower modes - Software-controlled FMPLL - Clock monitoring unit Low-power capabilities - Several low-power mode configurations - Ultra-low-power standby with RTC and communication - Fast wakeup schemes Exhaustive debugging capability - Nexus 2+ interface on LBGA208 package - Nexus 1 on all packages Voltage supply - Single 5 V or 3.3 V supply - On-chip voltage regulator - External ballast resistor support LQFP100, LQFP144, and LQFP176 packages; LBGA208 package for Nexus2+ Operating temperature range -40 to 125 C Table 1. Device summary 768 KByte Code Flash 1 MByte Code Flash 1.5 MByte Code Flash LQFP176 -- SPC560B60L7 SPC560B64L7 LQFP144 SPC560B54L5 SPC560B60L5 SPC560B64L5 LQFP100 SPC560B54L3 SPC560B60L3 -- Package Doc ID 15131 Rev 7 1/134 www.st.com 1 Contents SPC560B54/6x Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1 Document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 Package pinouts and signal descriptions . . . . . . . . . . . . . . . . . . . . . . . 13 4 3.1 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2 Pad configuration during reset phases . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3 Pad configuration during standby mode exit . . . . . . . . . . . . . . . . . . . . . . 17 3.4 Voltage supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.5 Pad types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.6 System pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.7 Functional port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.8 Nexus 2+ pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4.1 Parameter classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4.2 NVUSRO register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 NVUSRO[PAD3V5V] field description . . . . . . . . . . . . . . . . . . . . . . . . . . 58 4.2.2 NVUSRO[OSCILLATOR_MARGIN] field description . . . . . . . . . . . . . . . 58 4.2.3 NVUSRO[WATCHDOG_EN] field description . . . . . . . . . . . . . . . . . . . . 58 4.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.4 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 4.5 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.6 2/134 4.2.1 4.5.1 External ballast resistor recommendations . . . . . . . . . . . . . . . . . . . . . . 61 4.5.2 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 4.5.3 Power considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 I/O pad electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4.6.1 I/O pad types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4.6.2 I/O input DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4.6.3 I/O output DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.6.4 Output pin transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Doc ID 15131 Rev 7 SPC560B54/6x Contents 4.6.5 4.7 RESET electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 4.8 Power management electrical characteristics . . . . . . . . . . . . . . . . . . . . . 80 4.8.1 Voltage regulator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 80 4.8.2 Low voltage detector electrical characteristics . . . . . . . . . . . . . . . . . . . . 83 4.9 Power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 4.10 Flash memory electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 86 4.11 4.10.1 Program/erase characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 4.10.2 Flash power supply DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 87 4.10.3 Start-up/Switch-off timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Electromagnetic compatibility (EMC) characteristics . . . . . . . . . . . . . . . . 88 4.11.1 Designing hardened software to avoid noise problems . . . . . . . . . . . . . 88 4.11.2 Electromagnetic interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 4.11.3 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 89 4.12 Fast external crystal oscillator (4 to 16 MHz) electrical characteristics . . 90 4.13 Slow external crystal oscillator (32 kHz) electrical characteristics . . . . . . 93 4.14 FMPLL electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 4.15 Fast internal RC oscillator (16 MHz) electrical characteristics . . . . . . . . . 96 4.16 Slow internal RC oscillator (128 kHz) electrical characteristics . . . . . . . . 97 4.17 ADC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 4.18 5 I/O pad current specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 4.17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 4.17.2 Input impedance and ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 4.17.3 ADC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 4.18.1 Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 4.18.2 DSPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 4.18.3 Nexus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 4.18.4 JTAG characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 5.1 ECOPACK(R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 5.2 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 5.2.1 LQFP176 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 5.2.2 LQFP144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 5.2.3 LQFP100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Doc ID 15131 Rev 7 3/134 Contents SPC560B54/6x 5.2.4 6 LBGA208 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Appendix A Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 4/134 Doc ID 15131 Rev 7 SPC560B54/6x List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SPC560B54/6 family comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 SPC560B54/6 series block summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Voltage supply pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 System pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Functional port pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Nexus 2+ pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Parameter classifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 PAD3V5V field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 OSCILLATOR_MARGIN field description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 WATCHDOG_EN field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Recommended operating conditions (3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Recommended operating conditions (5.0 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 LQFP thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 I/O input DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 I/O pull-up/pull-down DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 SLOW configuration output buffer electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 66 MEDIUM configuration output buffer electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 67 FAST configuration output buffer electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 67 Output pin transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 I/O supply segments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 I/O consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 I/O weight . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Reset electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Voltage regulator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Low voltage detector electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Power consumption on VDD_BV and VDD_HV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Program and erase specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Flash module life. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Flash read access timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Flash power supply DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Start-up time/Switch-off time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 EMI radiated emission measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Latch-up results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Crystal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Fast external crystal oscillator (4 to 16 MHz) electrical characteristics. . . . . . . . . . . . . . . . 92 Crystal motional characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Slow external crystal oscillator (32 kHz) electrical characteristics . . . . . . . . . . . . . . . . . . . 95 FMPLL electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Fast internal RC oscillator (16 MHz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 96 Slow internal RC oscillator (128 kHz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . 97 ADC input leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 ADC_0 conversion characteristics (10-bit ADC_0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 ADC_1 conversion characteristics (12-bit ADC_1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 On-chip peripherals current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 DSPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Doc ID 15131 Rev 7 5/134 List of tables Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. 6/134 SPC560B54/6x Nexus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 JTAG characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 LQFP176 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 LQFP144 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 LQFP100 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 LBGA208 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Doc ID 15131 Rev 7 SPC560B54/6x List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. SPC560B54/6 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 LQFP176 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 LQFP144 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 LQFP100 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 LBGA208 configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 I/O input DC electrical characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Start-up reset requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Noise filtering on reset signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Voltage regulator capacitance connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Low voltage detector vs reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Crystal oscillator and resonator connection scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Fast external crystal oscillator (4 to 16 MHz) timing diagram . . . . . . . . . . . . . . . . . . . . . . . 92 Crystal oscillator and resonator connection scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 lEquivalent circuit of a quartz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Slow external crystal oscillator (32 kHz) timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . 95 ADC_0 characteristic and error definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Input equivalent circuit (precise channels) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Input equivalent circuit (extended channels) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Transient behavior during sampling phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Spectral representation of input signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 ADC_1 characteristic and error definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 DSPI classic SPI timing -- master, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 DSPI classic SPI timing -- master, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 DSPI classic SPI timing -- slave, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 DSPI classic SPI timing -- slave, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 DSPI modified transfer format timing -- master, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . 115 DSPI modified transfer format timing -- master, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . 115 DSPI modified transfer format timing -- slave, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . 116 DSPI modified transfer format timing -- slave, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . 116 DSPI PCS strobe (PCSS) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Nexus TDI, TMS, TDO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Timing diagram -- JTAG boundary scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 LQFP176 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 LQFP144 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 LQFP100 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 LBGA208 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Commercial product code structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Doc ID 15131 Rev 7 7/134 Introduction SPC560B54/6x 1 Introduction 1.1 Document overview This document describes the features of the family and options available within the family members, and highlights important electrical and physical characteristics of the device. 1.2 Description This family of 32-bit system-on-chip (SoC) microcontrollers is the latest achievement in integrated automotive application controllers. It belongs to an expanding family of automotive-focused products designed to address the next wave of body electronics applications within the vehicle. The advanced and cost-efficient e200z0h host processor core of this automotive controller family complies with the Power Architecture technology and only implements the VLE (variable-length encoding) APU (Auxiliary Processor Unit), providing improved code density. It operates at speeds of up to 64 MHz and offers high performance processing optimized for low power consumption. It capitalizes on the available development infrastructure of current Power Architecture devices and is supported with software drivers, operating systems and configuration code to assist with users implementations. SPC560B54/6 family comparison(1) Table 2. Feature SPC560B54 SPC560B60 CPU SPC560B64 e200z0h Execution speed(2) Up to 64 MHz Code flash memory 768 KB 1 MB 1.5 MB 64 (4 16) KB Data flash memory SRAM 64 KB 80 KB 96 KB MPU 8-entry eDMA 16 ch 10-bit ADC Yes dedicated (3) 7 ch 15 ch 7 ch 15 ch shared with 12-bit ADC 29 ch 29 ch 29 ch 64 ch, 16-bit 64 ch, 16-bit 64 ch, 16-bit 19 ch 12-bit ADC Yes dedicated (4) 5 ch shared with 10-bit ADC Total timer I/O(5) eMIOS 19 ch 37 ch, 16-bit 64 ch, 16-bit 37 ch, 16-bit 64 ch, 16-bit 64 ch, 16-bit Counter / OPWM / ICOC(6) 10 ch O(I)PWM / OPWFMB / OPWMCB / ICOC(7) 7 ch 8/134 15 ch Doc ID 15131 Rev 7 SPC560B54/6x Table 2. Introduction SPC560B54/6 family comparison(1) (continued) Feature SPC560B54 O(I)PWM / ICOC(8) SPC560B60 SPC560B64 7 ch 14 ch 7 ch 14 ch 14 ch 14 ch 14 ch 14 ch 13 ch 33 ch 13 ch 33 ch 33 ch 33 ch 33 ch 33 ch SCI (LINFlex) 4 8 4 8 10 8 10 10 SPI (DSPI) 3 5 3 5 6 5 6 6 149 121 149 149 OPWM / ICOC (9) CAN (FlexCAN) 6 I2 1 C 32 KHz oscillator (10) GPIO Yes 77 121 77 Debug Package 121 JTAG LQFP100 LQFP144 LQFP100 LQFP144 LQFP176 LQFP144 LQFP176 N2+ LBGA208 (11) 1. Feature set dependent on selected peripheral multiplexing; table shows example 2. Based on 125 C ambient operating temperature 3. Not shared with 12-bit ADC, but possibly shared with other alternate functions 4. Not shared with 10-bit ADC, but possibly shared with other alternate functions 5. See the eMIOS section of the chip reference manual for information on the channel configuration and functions. 6. Each channel supports a range of modes including Modulus counters, PWM generation, Input Capture, Output Compare. 7. Each channel supports a range of modes including PWM generation with dead time, Input Capture, Output Compare. 8. Each channel supports a range of modes including PWM generation, Input Capture, Output Compare, Period and Pulse width measurement. 9. Each channel supports a range of modes including PWM generation, Input Capture, and Output Compare. 10. Maximum I/O count based on multiplexing with peripherals 11. LBGA208 available only as development package for Nexus2+ Doc ID 15131 Rev 7 9/134 Block diagram 2 SPC560B54/6x Block diagram Figure 1 shows a top-level block diagram of the SPC560B54/6. SPC560B54/6 block diagram SRAM 96 KB eDMA JTAG JTAG Port Code Flash 1.5 MB Data Flash 64 KB (Master) e200z0h Nexus (Master) Data NMI Nexus 2+ (Master) SIUL Voltage Regulator Interrupt requests from peripheral blocks NMI INTC Clocks SRAM Controller MPU Instructions Nexus Port 64-bit 2 x 3 Crossbar Switch Figure 1. Flash Controller (Slave) (Slave) Interrupt request with wakeup functionality (Slave) MPU Registers WKPU CMU FMPLL STM RTC SWT ECSM MC_RGM PIT MC_CGM MC_ME MC_PCU BAM SSCM I2C 6x FlexCAN Peripheral Bridge Interrupt Request SIUL Reset Control 19 ch 10-bit/12-bit ADC External Interrupt Request 29 ch 10-bit ADC 10 x LINFlex 64 ch eMIOS CTU 6x DSPI 5 ch 12-bit ADC IMUX GPIO & Pad Control I/O ... ... ... ... ... Legend: ADC BAM CMU CTU DSPI ECSM eDMA eMIOS Flash FlexCAN FMPLL GPIO I2C IMUX INTC JTAG LINFlex 10/134 Analog-to-Digital Converter Boot Assist Module Clock Monitor Unit Cross Triggering Unit Deserial Serial Peripheral Interface Error Correction Status Module Enhanced Direct Memory Access Enhanced Modular Input Output System Flash memory Controller Area Network Frequency-Modulated Phase-Locked Loop General-purpose input/output Inter-Integrated Circuit bus Internal Multiplexer Interrupt Controller JTAG controller Serial Communication Interface (LIN support) MC_CGM MC_ME MC_PCU MC_RGM MPU NMI PIT RTC SIUL SRAM SSCM STM SWT VREG WKPU XBAR Doc ID 15131 Rev 7 Clock Generation Module Mode Entry Module Power Control Unit Reset Generation Module Memory Protection Unit Non-Maskable Interrupt Periodic Interrupt Timer Real-Time Clock System Integration Unit Lite Static Random-Access Memory System Status Configuration Module System Timer Module Software Watchdog Timer Voltage regulator Wakeup Unit Crossbar switch SPC560B54/6x Block diagram Table 3 summarizes the functions of the blocks present on the SPC560B54/6. Table 3. SPC560B54/6 series block summary Block Function Analog-to-digital converter (ADC) Converts analog voltages to digital values Boot assist module (BAM) A block of read-only memory containing VLE code which is executed according to the boot mode of the device Clock generation module (MC_CGM) Provides logic and control required for the generation of system and peripheral clocks Clock monitor unit (CMU) Monitors clock source (internal and external) integrity Cross triggering unit (CTU) Enables synchronization of ADC conversions with a timer event from the eMIOS or from the PIT Crossbar switch (XBAR) Supports simultaneous connections between two master ports and three slave ports. The crossbar supports a 32-bit address bus width and a 64-bit data bus width. Deserial serial peripheral interface (DSPI) Provides a synchronous serial interface for communication with external devices Enhanced Direct Memory Access Performs complex data transfers with minimal intervention from a host (eDMA) processor via "n" programmable channels Enhanced modular input output system (eMIOS) Provides the functionality to generate or measure events Error Correction Status Module (ECSM) Provides a myriad of miscellaneous control functions for the device including program-visible information about configuration and revision levels, a reset status register, wakeup control for exiting sleep modes, and optional features such as information on memory errors reported by error-correcting codes Flash memory Provides non-volatile storage for program code, constants and variables FlexCAN (controller area network) Supports the standard CAN communications protocol Frequency-modulated phaselocked loop (FMPLL) Generates high-speed system clocks and supports programmable frequency modulation Inter-integrated circuit (I2CTM) bus A two wire bidirectional serial bus that provides a simple and efficient method of data exchange between devices Internal multiplexer (IMUX) SIU subblock Allows flexible mapping of peripheral interface on the different pins of the device Interrupt controller (INTC) Provides priority-based preemptive scheduling of interrupt requests JTAG controller (JTAGC) Provides the means to test chip functionality and connectivity while remaining transparent to system logic when not in test mode LINFlex controller Manages a high number of LIN (Local Interconnect Network protocol) messages efficiently with a minimum of CPU load Memory protection unit (MPU) Provides hardware access control for all memory references generated in a device Mode entry module (MC_ME) Provides a mechanism for controlling the device operational mode and modetransition sequences in all functional states; also manages the power control unit, reset generation module and clock generation module, and holds the configuration, control and status registers accessible for applications Doc ID 15131 Rev 7 11/134 Block diagram Table 3. SPC560B54/6x SPC560B54/6 series block summary (continued) Block Function Non-Maskable Interrupt (NMI) Handles external events that must produce an immediate response, such as power down detection Periodic interrupt timer (PIT) Produces periodic interrupts and triggers Power control unit (MC_PCU) Reduces the overall power consumption by disconnecting parts of the device from the power supply via a power switching device; device components are grouped into sections called "power domains" which are controlled by the PCU Real-time counter (RTC) A free running counter used for time keeping applications, the RTC can be configured to generate an interrupt at a predefined interval independent of the mode of operation (run mode or low-power mode) Reset generation module (MC_RGM) Centralizes reset sources and manages the device reset sequence of the device Static random-access memory (SRAM) Provides storage for program code, constants, and variables Provides control over all the electrical pad controls and up 32 ports with 16 bits System integration unit lite (SIUL) of bidirectional, general-purpose input and output signals and supports up to 32 external interrupts with trigger event configuration System status and configuration module (SSCM) Provides system configuration and status data (such as memory size and status, device mode and security status), device identification data, debug status port enable and selection, and bus and peripheral abort enable/disable System timer module (STM) Provides a set of output compare events to support AUTOSAR (AUTomotive Open System ARchitecture) and operating system tasks System watchdog timer (SWT) Provides protection from runaway code WKPU (wakeup unit) The wakeup unit supports up to 27 external sources that can generate interrupts or wakeup events, of which 1 can cause non-maskable interrupt requests or wakeup events. 12/134 Doc ID 15131 Rev 7 SPC560B54/6x Package pinouts and signal descriptions 3 Package pinouts and signal descriptions 3.1 Package pinouts The available LQFP pinouts and the ballmap are provided in the following figures. For pin signal descriptions, please see Table 6. Figure 2 shows the SPC560B54/6 in the LQFP176 package. LQFP176 pin configuration LQFP176 Top view 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 PA[11] PA[10] PA[9] PA[8] PA[7] PE[13] PF[14] PF[15] VDD_HV VSS_HV PG[0] PG[1] PH[3] PH[2] PH[1] PH[0] PG[12] PG[13] PA[3] PI[13] PI[12] PI[11] PI[10] PI[9] PI[8] PB[15] PD[15] PB[14] PD[14] PB[13] PD[13] PB[12] PD[12] VDD_HV_ADC1 VSS_HV_ADC1 PB[11] PD[11] PD[10] PD[9] PB[7] PB[6] PB[5] VDD_HV_ADC0 VSS_HV_ADC0 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 PC[7] PF[10] PF[11] PA[15] PF[13] PA[14] PA[4] PA[13] PA[12] VDD_LV VSS_LV XTAL VSS_HV EXTAL VDD_HV PB[9] PB[8] PB[10] PF[0] PF[1] PF[2] PF[3] PF[4] PF[5] PF[6] PF[7] PJ[3] PJ[2] PJ[1] PJ[0] PI[15] PI[14] PD[0] PD[1] PD[2] PD[3] PD[4] PD[5] PD[6] PD[7] VDD_HV VSS_HV PD[8] PB[4] PB[3] PC[9] PC[14] PC[15] PJ[4] VDD_HV VSS_HV PH[15] PH[13] PH[14] PI[6] PI[7] PG[5] PG[4] PG[3] PG[2] PA[2] PE[0] PA[1] PE[1] PE[8] PE[9] PE[10] PA[0] PE[11] VSS_HV VDD_HV VSS_HV RESET VSS_LV VDD_LV VDD_BV PG[9] PG[8] PC[11] PC[10] PG[7] PG[6] PB[0] PB[1] PF[9] PF[8] PF[12] PC[6] 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 PB[2] PC[8] PC[13] PC[12] PI[0] PI[1] PI[2] PI[3] PE[7] PE[6] PH[8] PH[7] PH[6] PH[5] PH[4] PE[5] PE[4] PC[4] PC[5] PE[3] PE[2] PH[9] PC[0] VSS_LV VDD_LV VDD_HV VSS_HV PC[1] PH[10] PA[6] PA[5] PC[2] PC[3] PI[4] PI[5] PH[12] PH[11] PG[11] PG[10] PE[15] PE[14] PG[15] PG[14] PE[12] Figure 2. Doc ID 15131 Rev 7 13/134 Package pinouts and signal descriptions SPC560B54/6x Figure 3 shows the SPC560B54/6 in the LQFP144 package. LQFP144 pin configuration 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 PB[2] PC[8] PC[13] PC[12] PE[7] PE[6] PH[8] PH[7] PH[6] PH[5] PH[4] PE[5] PE[4] PC[4] PC[5] PE[3] PE[2] PH[9] PC[0] VSS_LV VDD_LV VDD_HV VSS_HV PC[1] PH[10] PA[6] PA[5] PC[2] PC[3] PG[11] PG[10] PE[15] PE[14] PG[15] PG[14] PE[12] Figure 3. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 LQFP144 Top view PC[7] PF[10] PF[11] PA[15] PF[13] PA[14] PA[4] PA[13] PA[12] VDD_LV VSS_LV XTAL VSS_HV EXTAL VDD_HV PB[9] PB[8] PB[10] PF[0] PF[1] PF[2] PF[3] PF[4] PF[5] PF[6] PF[7] PD[0] PD[1] PD[2] PD[3] PD[4] PD[5] PD[6] PD[7] PD[8] PB[4] 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 PB[3] PC[9] PC[14] PC[15] PG[5] PG[4] PG[3] PG[2] PA[2] PE[0] PA[1] PE[1] PE[8] PE[9] PE[10] PA[0] PE[11] VSS_HV VDD_HV VSS_HV RESET VSS_LV VDD_LV VDD_BV PG[9] PG[8] PC[11] PC[10] PG[7] PG[6] PB[0] PB[1] PF[9] PF[8] PF[12] PC[6] Figure 4 shows the SPC560B54/6 in the LQFP100 package. 14/134 Doc ID 15131 Rev 7 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 PA[11] PA[10] PA[9] PA[8] PA[7] PE[13] PF[14] PF[15] VDD_HV VSS_HV PG[0] PG[1] PH[3] PH[2] PH[1] PH[0] PG[12] PG[13] PA[3] PB[15] PD[15] PB[14] PD[14] PB[13] PD[13] PB[12] VDD_HV_ADC1 VSS_HV_ADC1 PD[11] PD[10] PD[9] PB[7] PB[6] PB[5] VDD_HV_ADC0 VSS_HV_ADC0 SPC560B54/6x 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 PB[2] PC[8] PC[13] PC[12] PE[7] PE[6] PE[5] PE[4] PC[4] PC[5] PE[3] PE[2] PH[9] PC[0] VSS_LV VDD_LV VDD_HV VSS_HV PC[1] PH[10] PA[6] PA[5] PC[2] PC[3] PE[12] LQFP100 pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 LQFP100 Top view 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PA[11] PA[10] PA[9] PA[8] PA[7] VDD_HV VSS_HV PA[3] PB[15] PD[15] PB[14] PD[14] PB[13] PD[13] PB[12] VDD_HV_ADC1 VSS_HV_ADC1 PD[11] PD[10] PD[9] PB[7] PB[6] PB[5] VDD_HV_ADC0 VSS_HV_ADC0 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 PB[3] PC[9] PC[14] PC[15] PA[2] PE[0] PA[1] PE[1] PE[8] PE[9] PE[10] PA[0] PE[11] VSS_HV VDD_HV VSS_HV RESET VSS_LV VDD_LV VDD_BV PC[11] PC[10] PB[0] PB[1] PC[6] PC[7] PA[15] PA[14] PA[4] PA[13] PA[12] VDD_LV VSS_LV XTAL VSS_HV EXTAL VDD_HV PB[9] PB[8] PB[10] PD[0] PD[1] PD[2] PD[3] PD[4] PD[5] PD[6] PD[7] PD[8] PB[4] Figure 4. Package pinouts and signal descriptions Figure 5 shows the SPC560B54/6 in the LBGA208 package. Doc ID 15131 Rev 7 15/134 Package pinouts and signal descriptions Figure 5. SPC560B54/6x LBGA208 configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A PC[8] PC[13] PH[15] PJ[4] PH[8] PH[4] PC[5] PC[0] PI[0] PI[1] PC[2] PI[4] PE[15] PH[11] NC NC A B PC[9] PB[2] PH[13] PC[12] PE[6] PH[5] PC[4] PH[9] PH[10] PI[2] PC[3] PG[11] PG[15] PG[14] PA[11] PA[10] B C PC[14] VDD_H V PB[3] PE[7] PH[7] PE[5] PE[3] VSS_LV PC[1] PI[3] PA[5] PI[5] PE[14] PE[12] PA[9] PA[8] C D PH[14] PI[6] PC[15] PI[7] PH[6] PE[4] PE[2] VDD_LV VDD_H V NC PA[6] PH[12] PG[10] PF[14] PE[13] PA[7] D E PG[4] PG[5] PG[3] PG[2] PG[1] PG[0] PF[15] VDD_H V E F PE[0] PA[2] PA[1] PE[1] PH[0] PH[1] PH[3] PH[2] F G PE[9] PE[8] PE[10] PA[0] VSS_H V VSS_H V VSS_H V VSS_H V VDD_H V PI[12] PI[13] MSEO G H VSS_HV PE[11] VDD_H V NC VSS_H V VSS_H V VSS_H V VSS_H V MDO3 MDO2 MDO0 MDO1 H J RESET VSS_LV NC NC VSS_H V VSS_H V VSS_H V VSS_H V PI[8] PI[9] PI[10] PI[11] J K EVTI NC VDD_B V VDD_LV VSS_H V VSS_H V VSS_H V VSS_H V VDD_H V_ADC 1 PG[12] PA[3] PG[13] K L PG[9] PG[8] NC EVTO PB[15] PD[15] PD[14] PB[14] L M PG[7] PG[6] PC[10] PC[11] PB[13] PD[13] PD[12] PB[12] M N PB[1] PF[9] PB[0] VDD_H V PJ[0] PA[4] VSS_LV EXTAL VDD_H V PF[0] PF[4] VSS_H V_ADC 1 PB[11] PD[10] PD[9] PD[11] N P PF[8] PJ[3] PC[7] PJ[2] PJ[1] PA[14] VDD_LV XTAL PB[10] PF[1] PF[5] PD[0] PD[3] VDD_H V_ADC 0 PB[6] PB[7] P R PF[12] PC[6] PF[10] PF[11] VDD_H V PA[15] PA[13] PI[14] XTAL32 PF[3] PF[7] PD[2] PD[4] PD[7] VSS_H V_ADC 0 PB[5] R T NC NC NC MCKO NC PF[13] PA[12] PI[15] EXTAL 32 PF[2] PF[6] PD[1] PD[5] PD[6] PD[8] PB[4] T 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 NOTE: The LBGA208 is available only as development package for Nexus 2+. 3.2 NC = Not connected Pad configuration during reset phases All pads have a fixed configuration under reset. During the power-up phase, all pads are forced to tristate. After power-up phase, all pads are tristate with the following exceptions: 16/134 PA[9] (FAB) is pull-down. Without external strong pull-up the device starts fetching from flash. PA[8], PC[0] and PH[9:10] are in input weak pull-up when out of reset. RESET pad is driven low by the device till 40 FIRC clock cycles after phase2 completion. Minimum phase3 duration is 40 FIRC cycles. Nexus output pads (MDO[n], MCKO, EVTO, MSEO) are forced to output. Doc ID 15131 Rev 7 SPC560B54/6x 3.3 Package pinouts and signal descriptions Pad configuration during standby mode exit Pad configuration (input buffer enable, pull enable) for low-power wakeup pads is controlled by both the SIUL and WKPU modules. During standby exit, all low power pads PA[0,1,2,4,15], PB[1,3,8,9,10](a), PC[7,9,11], PD[0,1], PE[0,9,11], PF[9,11,13](b), PG[3,5,7,9]b, PI[1,3](c) are configured according to their respective configuration done in the WKPU module. All other pads will have the same configuration as expected after a reset. The TDO pad has been moved into the STANDBY domain in order to allow low-power debug handshaking in STANDBY mode. However, no pull-resistor is active on the TDO pad while in STANDBY mode. At this time the pad is configured as an input. When no debugger is connected the TDO pad is floating causing additional current consumption. To avoid the extra consumption TDO must be connected. An external pull-up resistor in the range of 47-100 kOhms should be added between the TDO pin and VDD. Only if the TDO pin is used as an application pin and a pull-up cannot be used should a pull-down resistor with the same value be used instead between the TDO pin and GND. 3.4 Voltage supply pins Voltage supply pins are used to provide power to the device. Three dedicated VDD_LV/VSS_LV supply pairs are used for 1.2 V regulator stabilization. Table 4. Voltage supply pin descriptions Pin number Port pin Function VDD_HV LQFP100 LQFP144 15, 37, 70, 84 19, 51, 100, 123 14, 16, 35, 69, 83 18, 20, 49, 99, 122 Digital supply voltage VSS_HV Digital ground 19, 32, 85 VDD_LV 1.2 V decoupling pins. Decoupling capacitor must be connected between these pins and the nearest VSS_LV pin.(1) 18, 33, 86 VSS_LV 1.2 V decoupling pins. Decoupling capacitor must be connected between these pins and the nearest VDD_LV pin.1 VDD_BV Internal regulator supply voltage LQFP176 LBGA208 6, 27, 59, 85, 124, 151 C2, D9, E16, G13, H3, N4, N9, R5 7, 26, 28, 57, 86, 123, 150 G7, G8, G9, G10, H7, H8, H9, H10, J7, J8, J9, J10, K7, K8, K9, K10 23, 46, 124 D8, K4, P7 31, 54, 152 22, 47, 125 C8, J2, N7 30, 55, 153 20 24 32 K3 a. PB[8, 9] ports have wakeup functionality in all modes except STANDBY. b. PF[9,11,13], PG[3,5,7,9], PI[1,3] are not available in the 100-pin LQFP. c. PI[1,3] are not available in the 144-pin LQFP. Doc ID 15131 Rev 7 17/134 Package pinouts and signal descriptions Table 4. SPC560B54/6x Voltage supply pin descriptions (continued) Pin number Port pin Function LQFP100 LQFP144 Reference ground and analog VSS_HV_ADC0 ground for the A/D converter 0 (10bit) 51 73 Reference voltage and analog VDD_HV_ADC0 supply for the A/D converter 0 (10bit) 52 Reference ground and analog VSS_HV_ADC1 ground for the A/D converter 1 (12bit) 59 Reference voltage and analog VDD_HV_ADC1 supply for the A/D converter 1 (12bit) 60 LQFP176 LBGA208 R15 89 74 P14 90 81 N12 98 82 K13 99 1. A decoupling capacitor must be placed between each of the three VDD_LV/VSS_LV supply pairs to ensure stable voltage (see the recommended operating conditions in the device datasheet). 3.5 Pad types In the device the following types of pads are available for system pins and functional port pins: S = Slow(d) M = Mediumd (e) F = Fastd e I = Input only with analog featured J = Input/Output (`S' pad) with analog feature X = Oscillator 3.6 System pins The system pins are listed in Table 5. d. See the I/O pad electrical characteristics in the chip datasheet for details. e. All medium and fast pads are in slow configuration by default at reset and can be configured as fast or medium. The only exception is PC[1] which is in medium configuration by default (see the PCR.SRC description in the chip reference manual, Pad Configuration Registers (PCR0-PCR148)). 18/134 Doc ID 15131 Rev 7 SPC560B54/6x Function Pad type Port pin System pin descriptions I/O direction Table 5. Package pinouts and signal descriptions Pin number RESET configuration LQFP 100 LQFP 144 LQFP 176 LBGA 208(1) 17 21 29 J1 I/O M Input weak pull-up after RGM PHASE2 and 40 FIRC cycles EXTAL Analog output of the oscillator amplifier circuit, when the oscillator is not in bypass mode. Analog input for the clock generator when the oscillator is in bypass mode. I/O X Tristate 36 50 58 N8 XTAL Analog input of the oscillator amplifier circuit. Needs to be grounded if oscillator bypass mode is used. I X Tristate 34 48 56 P8 Bidirectional reset with SchmittRESET Trigger characteristics and noise filter. 1. LBGA208 available only as development package for Nexus2+ Doc ID 15131 Rev 7 19/134 Functional port pins The functional port pins are listed in Table 6. configuration(3) Peripheral RESET Function Pad type PCR I/O direction(2) Port pin Functional port pin descriptions Alternate function(1) Table 6. Pin number LQFP 100 LQFP 144 LQFP 176 LBGA 208(4) Port A Doc ID 15131 Rev 7 PA[0] PA[1] PA[2] GPIO[0] E0UC[0] CLKOUT E0UC[13] WKPU[19](5) SIUL eMIOS_0 MC_CGM eMIOS_0 WKPU I/O I/O O I/O I M Tristate 12 16 24 G4 PCR[1] AF0 AF1 AF2 AF3 -- GPIO[1] E0UC[1] NMI(6) -- WKPU[2]5 SIUL eMIOS_0 WKPU -- WKPU I/O I/O I -- I S Tristate 7 11 19 F3 PCR[2] AF0 AF1 AF2 AF3 -- GPIO[2] E0UC[2] -- MA[2] WKPU[3]5 SIUL eMIOS_0 -- ADC_0 WKPU I/O I/O -- O I S Tristate 5 9 17 F2 PCR[3] AF0 AF1 AF2 AF3 -- -- GPIO[3] E0UC[3] LIN5TX CS4_1 EIRQ[0] ADC1_S[0] SIUL eMIOS_0 LINFlex_5 DSPI_1 SIUL ADC_1 I/O I/O O O I I J Tristate 68 90 114 K15 SPC560B54/6x PA[3] PCR[0] AF0 AF1 AF2 AF3 -- Package pinouts and signal descriptions 20/134 3.7 PA[7] GPIO[4] E0UC[4] -- CS0_1 LIN5RX WKPU[9]5 SIUL eMIOS_0 -- DSPI_1 LINFlex_5 WKPU I/O I/O -- I/O I I S PCR[5] AF0 AF1 AF2 AF3 GPIO[5] E0UC[5] LIN4TX -- SIUL eMIOS_0 LINFlex_4 -- I/O I/O O -- PCR[6] AF0 AF1 AF2 AF3 -- -- GPIO[6] E0UC[6] -- CS1_1 EIRQ[1] LIN4RX SIUL eMIOS_0 -- DSPI_1 SIUL LINFlex_4 PCR[7] AF0 AF1 AF2 AF3 -- -- GPIO[7] E0UC[7] LIN3TX -- EIRQ[2] ADC1_S[1] SIUL eMIOS_0 LINFlex_3 -- SIUL ADC_1 configuration(3) PCR[4] AF0 AF1 AF2 AF3 -- -- RESET Pad type PA[6] Peripheral PCR Pin number LQFP 100 LQFP 144 LQFP 176 LBGA 208(4) Tristate 29 43 51 N6 M Tristate 79 118 146 C11 I/O I/O -- O I I S Tristate 80 119 147 D11 I/O I/O O -- I I J Tristate 71 104 128 D16 21/134 Package pinouts and signal descriptions Doc ID 15131 Rev 7 PA[5] Function I/O direction(2) PA[4] Alternate function(1) Port pin Functional port pin descriptions (continued) SPC560B54/6x Table 6. PA[10] PA[11] SIUL eMIOS_0 eMIOS_0 -- SIUL BAM LINFlex_3 I/O I/O I/O -- I I I S PCR[9] AF0 AF1 AF2 AF3 N/A7 GPIO[9] E0UC[9] -- CS2_1 FAB SIUL eMIOS_0 -- DSPI_1 BAM I/O I/O -- O I PCR[10] AF0 AF1 AF2 AF3 -- GPIO[10] E0UC[10] SDA LIN2TX ADC1_S[2] SIUL eMIOS_0 I2C_0 LINFlex_2 ADC_1 PCR[11] AF0 AF1 AF2 AF3 -- -- -- GPIO[11] E0UC[11] SCL -- EIRQ[16] LIN2RX ADC1_S[3] SIUL eMIOS_0 I2C_0 -- SIUL LINFlex_2 ADC_1 configuration(3) GPIO[8] E0UC[8] E0UC[14] -- EIRQ[3] ABS[0] LIN3RX RESET PCR[8] AF0 AF1 AF2 AF3 -- N/A(7) -- PCR Pin number LQFP 100 LQFP 144 LQFP 176 LBGA 208(4) Input, weak pull-up 72 105 129 C16 S Pulldown 73 106 130 C15 I/O I/O I/O O I J Tristate 74 107 131 B16 I/O I/O I/O -- I I I J Tristate 75 108 132 B15 SPC560B54/6x Peripheral Pad type Doc ID 15131 Rev 7 PA[9] Function I/O direction(2) PA[8] Alternate function(1) Port pin Functional port pin descriptions (continued) Package pinouts and signal descriptions 22/134 Table 6. PA[15] GPIO[12] -- E0UC[28] CS3_1 EIRQ[17] SIN_0 SIUL -- eMIOS_0 DSPI_1 SIUL DSPI_0 I/O -- I/O O I I S PCR[13] AF0 AF1 AF2 AF3 GPIO[13] SOUT_0 E0UC[29] -- SIUL DSPI_0 eMIOS_0 -- I/O O I/O -- PCR[14] AF0 AF1 AF2 AF3 -- GPIO[14] SCK_0 CS0_0 E0UC[0] EIRQ[4] SIUL DSPI_0 DSPI_0 eMIOS_0 SIUL PCR[15] AF0 AF1 AF2 AF3 -- GPIO[15] CS0_0 SCK_0 E0UC[1] WKPU[10]5 SIUL DSPI_0 DSPI_0 eMIOS_0 WKPU configuration(3) PCR[12] AF0 AF1 AF2 AF3 -- -- RESET Pad type PA[14] Peripheral PCR Pin number LQFP 100 LQFP 144 LQFP 176 LBGA 208(4) Tristate 31 45 53 T7 M Tristate 30 44 52 R7 I/O I/O I/O I/O I M Tristate 28 42 50 P6 I/O I/O I/O I/O I M Tristate 27 40 48 R6 M Tristate 23 31 39 N3 Port B PB[0] PCR[16] 23/134 AF0 AF1 AF2 AF3 GPIO[16] CAN0TX E0UC[30] LIN0TX SIUL FlexCAN_0 eMIOS_0 LINFlex_0 I/O O I/O O Package pinouts and signal descriptions Doc ID 15131 Rev 7 PA[13] Function I/O direction(2) PA[12] Alternate function(1) Port pin Functional port pin descriptions (continued) SPC560B54/6x Table 6. PB[3] PB[4] SIUL -- eMIOS_0 -- WKPU FlexCAN_0 LINFlex_0 I/O -- I/O -- I I I S PCR[18] AF0 AF1 AF2 AF3 GPIO[18] LIN0TX SDA E0UC[30] SIUL LINFlex_0 I2C_0 eMIOS_0 I/O O I/O I/O PCR[19] AF0 AF1 AF2 AF3 -- -- GPIO[19] E0UC[31] SCL -- WKPU[11]5 LIN0RX SIUL eMIOS_0 I2C_0 -- WKPU LINFlex_0 PCR[20] AF0 AF1 AF2 AF3 -- -- -- -- -- -- -- ADC0_P[0] ADC1_P[0] GPIO[20] -- -- -- -- ADC_0 ADC_1 SIUL configuration(3) GPIO[17] -- E0UC[31] -- WKPU[4]5 CAN0RX LIN0RX RESET PCR[17] AF0 AF1 AF2 AF3 -- -- -- PCR Pin number LQFP 100 LQFP 144 LQFP 176 LBGA 208(4) Tristate 24 32 40 N1 M Tristate 100 144 176 B2 I/O I/O I/O -- I I S Tristate 1 1 1 C3 -- -- -- -- I I I I Tristate 50 72 88 T16 SPC560B54/6x Peripheral Pad type Doc ID 15131 Rev 7 PB[2] Function I/O direction(2) PB[1] Alternate function(1) Port pin Functional port pin descriptions (continued) Package pinouts and signal descriptions 24/134 Table 6. -- -- -- -- ADC0_P[1] ADC1_P[1] GPIO[21] -- -- -- -- ADC_0 ADC_1 SIUL -- -- -- -- I I I I PCR[22] AF0 AF1 AF2 AF3 -- -- -- -- -- -- -- ADC0_P[2] ADC1_P[2] GPIO[22] -- -- -- -- ADC_0 ADC_1 SIUL -- -- -- -- I I I PCR[23] AF0 AF1 AF2 AF3 -- -- -- -- -- -- -- ADC0_P[3] ADC1_P[3] GPIO[23] -- -- -- -- ADC_0 ADC_1 SIUL -- -- -- -- I I I configuration(3) PCR[21] AF0 AF1 AF2 AF3 -- -- -- RESET Pad type PB[7] Peripheral PCR Pin number LQFP 100 LQFP 144 LQFP 176 LBGA 208(4) Tristate 53 75 91 R16 I Tristate 54 76 92 P15 I Tristate 55 77 93 P16 25/134 Package pinouts and signal descriptions Doc ID 15131 Rev 7 PB[6] Function I/O direction(2) PB[5] Alternate function(1) Port pin Functional port pin descriptions (continued) SPC560B54/6x Table 6. PB[10] SIUL -- -- -- OSC32K WKPU ADC_0 ADC_1 I -- -- -- -- I(9) I I I PCR[25] AF0 AF1 AF2 AF3 -- -- -- -- GPIO[25] -- -- -- OSC32K_EXTAL8 WKPU[26]5 ADC0_S[1] ADC1_S[5] SIUL -- -- -- OSC32K WKPU ADC_0 ADC_1 I -- -- -- -- I9 I I PCR[26] AF0 AF1 AF2 AF3 -- -- -- GPIO[26] -- -- -- WKPU[8]5 ADC0_S[2] ADC1_S[6] SIUL -- -- -- WKPU ADC_0 ADC_1 I/O -- -- -- I I I configuration(3) GPIO[24] -- -- -- OSC32K_XTAL(8) WKPU[25]5 ADC0_S[0] ADC1_S[4] RESET PCR[24] AF0 AF1 AF2 AF3 -- -- -- -- PCR Pin number LQFP 100 LQFP 144 LQFP 176 LBGA 208(4) -- 39 53 61 R9 I -- 38 52 60 T9 J Tristate 40 54 62 P9 SPC560B54/6x Peripheral Pad type Doc ID 15131 Rev 7 PB[9] Function I/O direction(2) PB[8] Alternate function(1) Port pin Functional port pin descriptions (continued) Package pinouts and signal descriptions 26/134 Table 6. PB[14] PB[15] 27/134 GPIO[27] E0UC[3] -- CS0_0 ADC0_S[3] SIUL eMIOS_0 -- DSPI_0 ADC_0 I/O I/O -- I/O I J PCR[28] AF0 AF1 AF2 AF3 -- GPIO[28] E0UC[4] -- CS1_0 ADC0_X[0] SIUL eMIOS_0 -- DSPI_0 ADC_0 I/O I/O -- O I PCR[29] AF0 AF1 AF2 AF3 -- GPIO[29] E0UC[5] -- CS2_0 ADC0_X[1] SIUL eMIOS_0 -- DSPI_0 ADC_0 PCR[30] AF0 AF1 AF2 AF3 -- GPIO[30] E0UC[6] -- CS3_0 ADC0_X[2] PCR[31] AF0 AF1 AF2 AF3 -- GPIO[31] E0UC[7] -- CS4_0 ADC0_X[3] configuration(3) PCR[27] AF0 AF1 AF2 AF3 -- RESET Pad type PB[13] Peripheral PCR Pin number LQFP 100 LQFP 144 LQFP 176 LBGA 208(4) Tristate -- -- 97 N13 J Tristate 61 83 101 M16 I/O I/O -- O I J Tristate 63 85 103 M13 SIUL eMIOS_0 -- DSPI_0 ADC_0 I/O I/O -- O I J Tristate 65 87 105 L16 SIUL eMIOS_0 -- DSPI_0 ADC_0 I/O I/O -- O I J Tristate 67 89 107 L13 Package pinouts and signal descriptions Doc ID 15131 Rev 7 PB[12] Function I/O direction(2) PB[11] Alternate function(1) Port pin Functional port pin descriptions (continued) SPC560B54/6x Table 6. configuration(3) RESET Peripheral Pad type Function I/O direction(2) PCR Alternate function(1) Port pin Functional port pin descriptions (continued) Pin number LQFP 100 LQFP 144 LQFP 176 LBGA 208(4) Port C PC[0](10) Doc ID 15131 Rev 7 PC[1]10 PC[2] PC[3] GPIO[32] -- TDI -- SIUL -- JTAGC -- I/O -- I -- M Input, weak pull-up 87 126 154 A8 PCR[33] AF0 AF1 AF2 AF3 GPIO[33] -- TDO -- SIUL -- JTAGC -- I/O -- O -- F(11) Tristate 82 121 149 C9 PCR[34] AF0 AF1 AF2 AF3 -- GPIO[34] SCK_1 CAN4TX DEBUG[0] EIRQ[5] SIUL DSPI_1 FlexCAN_4 SSCM SIUL I/O I/O O O I M Tristate 78 117 145 A11 PCR[35] AF0 AF1 AF2 AF3 -- -- -- GPIO[35] CS0_1 MA[0] DEBUG[1] EIRQ[6] CAN1RX CAN4RX SIUL DSPI_1 ADC_0 SSCM SIUL FlexCAN_1 FlexCAN_4 I/O I/O O O I I I S Tristate 77 116 144 B11 SPC560B54/6x PCR[32] AF0 AF1 AF2 AF3 Package pinouts and signal descriptions 28/134 Table 6. PC[7] GPIO[36] E1UC[31] -- DEBUG[2] EIRQ[18] SIN_1 CAN3RX SIUL eMIOS_1 -- SSCM SIUL DSPI_1 FlexCAN_3 I/O I/O -- O I I I M PCR[37] AF0 AF1 AF2 AF3 -- GPIO[37] SOUT_1 CAN3TX DEBUG[3] EIRQ[7] SIUL DSPI_1 FlexCAN_3 SSCM SIUL I/O O O O I PCR[38] AF0 AF1 AF2 AF3 GPIO[38] LIN1TX E1UC[28] DEBUG[4] SIUL LINFlex_1 eMIOS_1 SSCM PCR[39] AF0 AF1 AF2 AF3 -- -- GPIO[39] -- E1UC[29] DEBUG[5] LIN1RX WKPU[12]5 SIUL -- eMIOS_1 SSCM LINFlex_1 WKPU configuration(3) PCR[36] AF0 AF1 AF2 AF3 -- -- -- RESET Pad type PC[6] Peripheral PCR Pin number LQFP 100 LQFP 144 LQFP 176 LBGA 208(4) Tristate 92 131 159 B7 M Tristate 91 130 158 A7 I/O O I/O O S Tristate 25 36 44 R2 I/O -- I/O O I I S Tristate 26 37 45 P3 29/134 Package pinouts and signal descriptions Doc ID 15131 Rev 7 PC[5] Function I/O direction(2) PC[4] Alternate function(1) Port pin Functional port pin descriptions (continued) SPC560B54/6x Table 6. PC[10] PC[11] GPIO[40] LIN2TX E0UC[3] DEBUG[6] SIUL LINFlex_2 eMIOS_0 SSCM I/O O I/O O S PCR[41] AF0 AF1 AF2 AF3 -- -- GPIO[41] -- E0UC[7] DEBUG[7] WKPU[13]5 LIN2RX SIUL -- eMIOS_0 SSCM WKPU LINFlex_2 I/O -- I/O O I I PCR[42] AF0 AF1 AF2 AF3 GPIO[42] CAN1TX CAN4TX MA[1] SIUL FlexCAN_1 FlexCAN_4 ADC_0 PCR[43] AF0 AF1 AF2 AF3 -- -- -- GPIO[43] -- -- MA[2] WKPU[5]5 CAN1RX CAN4RX SIUL -- -- ADC_0 WKPU FlexCAN_1 FlexCAN_4 configuration(3) PCR[40] AF0 AF1 AF2 AF3 PCR RESET Peripheral Pad type Doc ID 15131 Rev 7 PC[9] Function I/O direction(2) PC[8] Alternate function(1) Port pin Functional port pin descriptions (continued) Pin number LQFP 100 LQFP 144 LQFP 176 LBGA 208(4) Tristate 99 143 175 A1 S Tristate 2 2 2 B1 I/O O O O M Tristate 22 28 36 M3 I/O -- -- O I I I S Tristate 21 27 35 M4 Package pinouts and signal descriptions 30/134 Table 6. SPC560B54/6x PC[15] GPIO[44] E0UC[12] -- -- EIRQ[19] SIN_2 SIUL eMIOS_0 -- -- SIUL DSPI_2 I/O I/O -- -- I I M PCR[45] AF0 AF1 AF2 AF3 GPIO[45] E0UC[13] SOUT_2 -- SIUL eMIOS_0 DSPI_2 -- I/O I/O O -- PCR[46] AF0 AF1 AF2 AF3 -- GPIO[46] E0UC[14] SCK_2 -- EIRQ[8] SIUL eMIOS_0 DSPI_2 -- SIUL PCR[47] AF0 AF1 AF2 AF3 -- GPIO[47] E0UC[15] CS0_2 -- EIRQ[20] SIUL eMIOS_0 DSPI_2 -- SIUL configuration(3) PCR[44] AF0 AF1 AF2 AF3 -- -- RESET Pad type PC[14] Peripheral PCR Pin number LQFP 100 LQFP 144 LQFP 176 LBGA 208(4) Tristate 97 141 173 B4 S Tristate 98 142 174 A2 I/O I/O I/O -- I S Tristate 3 3 3 C1 I/O I/O I/O -- I M Tristate 4 4 4 D3 31/134 Package pinouts and signal descriptions Doc ID 15131 Rev 7 PC[13] Function I/O direction(2) PC[12] Alternate function(1) Port pin Functional port pin descriptions (continued) SPC560B54/6x Table 6. configuration(3) RESET Peripheral Pad type Function I/O direction(2) PCR Alternate function(1) Port pin Functional port pin descriptions (continued) Pin number LQFP 100 LQFP 144 LQFP 176 LBGA 208(4) Port D PD[0] Doc ID 15131 Rev 7 PD[1] PD[2] PCR[48] AF0 AF1 AF2 AF3 -- -- -- GPIO[48] -- -- -- WKPU[27]5 ADC0_P[4] ADC1_P[4] SIUL -- -- -- WKPU ADC_0 ADC_1 I -- -- -- I I I I Tristate 41 63 77 P12 PCR[49] AF0 AF1 AF2 AF3 -- -- -- GPIO[49] -- -- -- WKPU[28]5 ADC0_P[5] ADC1_P[5] SIUL -- -- -- WKPU ADC_0 ADC_1 I -- -- -- I I I I Tristate 42 64 78 T12 PCR[50] AF0 AF1 AF2 AF3 -- -- GPIO[50] -- -- -- ADC0_P[6] ADC1_P[6] SIUL -- -- -- ADC_0 ADC_1 I -- -- -- I I I Tristate 43 65 79 R12 Package pinouts and signal descriptions 32/134 Table 6. SPC560B54/6x PD[6] GPIO[51] -- -- -- ADC0_P[7] ADC1_P[7] SIUL -- -- -- ADC_0 ADC_1 I -- -- -- I I I PCR[52] AF0 AF1 AF2 AF3 -- -- GPIO[52] -- -- -- ADC0_P[8] ADC1_P[8] SIUL -- -- -- ADC_0 ADC_1 I -- -- -- I I PCR[53] AF0 AF1 AF2 AF3 -- -- GPIO[53] -- -- -- ADC0_P[9] ADC1_P[9] SIUL -- -- -- ADC_0 ADC_1 PCR[54] AF0 AF1 AF2 AF3 -- -- GPIO[54] -- -- -- ADC0_P[10] ADC1_P[10] SIUL -- -- -- ADC_0 ADC_1 configuration(3) PCR[51] AF0 AF1 AF2 AF3 -- -- RESET Pad type PD[5] Peripheral PCR Pin number LQFP 100 LQFP 144 LQFP 176 LBGA 208(4) Tristate 44 66 80 P13 I Tristate 45 67 81 R13 I -- -- -- I I I Tristate 46 68 82 T13 I -- -- -- I I I Tristate 47 69 83 T14 33/134 Package pinouts and signal descriptions Doc ID 15131 Rev 7 PD[4] Function I/O direction(2) PD[3] Alternate function(1) Port pin Functional port pin descriptions (continued) SPC560B54/6x Table 6. PD[9] SIUL -- -- -- ADC_0 ADC_1 I -- -- -- I I I PCR[56] AF0 AF1 AF2 AF3 -- -- GPIO[56] -- -- -- ADC0_P[12] ADC1_P[12] SIUL -- -- -- ADC_0 ADC_1 I -- -- -- I I PCR[57] AF0 AF1 AF2 AF3 -- -- GPIO[57] -- -- -- ADC0_P[13] ADC1_P[13] SIUL -- -- -- ADC_0 ADC_1 PCR[58] AF0 AF1 AF2 AF3 -- -- GPIO[58] -- -- -- ADC0_P[14] ADC1_P[14] SIUL -- -- -- ADC_0 ADC_1 configuration(3) GPIO[55] -- -- -- ADC0_P[11] ADC1_P[11] RESET PCR[55] AF0 AF1 AF2 AF3 -- -- PCR Pin number LQFP 100 LQFP 144 LQFP 176 LBGA 208(4) Tristate 48 70 84 R14 I Tristate 49 71 87 T15 I -- -- -- I I I Tristate 56 78 94 N15 I -- -- -- I I I Tristate 57 79 95 N14 SPC560B54/6x PD[10] Peripheral Pad type Doc ID 15131 Rev 7 PD[8] Function I/O direction(2) PD[7] Alternate function(1) Port pin Functional port pin descriptions (continued) Package pinouts and signal descriptions 34/134 Table 6. PD[14] GPIO[59] -- -- -- ADC0_P[15] ADC1_P[15] SIUL -- -- -- ADC_0 ADC_1 I -- -- -- I I I PCR[60] AF0 AF1 AF2 AF3 -- GPIO[60] CS5_0 E0UC[24] -- ADC0_S[4] SIUL DSPI_0 eMIOS_0 -- ADC_0 I/O O I/O -- I PCR[61] AF0 AF1 AF2 AF3 -- GPIO[61] CS0_1 E0UC[25] -- ADC0_S[5] SIUL DSPI_1 eMIOS_0 -- ADC_0 PCR[62] AF0 AF1 AF2 AF3 -- GPIO[62] CS1_1 E0UC[26] -- ADC0_S[6] SIUL DSPI_1 eMIOS_0 -- ADC_0 configuration(3) PCR[59] AF0 AF1 AF2 AF3 -- -- RESET Pad type PD[13] Peripheral PCR Pin number LQFP 100 LQFP 144 LQFP 176 LBGA 208(4) Tristate 58 80 96 N16 J Tristate -- -- 100 M15 I/O I/O I/O -- I J Tristate 62 84 102 M14 I/O O I/O -- I J Tristate 64 86 104 L15 35/134 Package pinouts and signal descriptions Doc ID 15131 Rev 7 PD[12] Function I/O direction(2) PD[11] Alternate function(1) Port pin Functional port pin descriptions (continued) SPC560B54/6x Table 6. GPIO[63] CS2_1 E0UC[27] -- ADC0_S[7] SIUL DSPI_1 eMIOS_0 -- ADC_0 configuration(3) AF0 AF1 AF2 AF3 -- I/O O I/O -- I J Tristate 66 88 106 L14 RESET Peripheral Pad type PCR[63] Function Pin number I/O direction(2) PD[15] PCR Alternate function(1) Port pin Functional port pin descriptions (continued) LQFP 100 LQFP 144 LQFP 176 LBGA 208(4) Port E Doc ID 15131 Rev 7 PE[0] PE[1] PE[2] GPIO[64] E0UC[16] -- -- WKPU[6]5 CAN5RX SIUL eMIOS_0 -- -- WKPU FlexCAN_5 I/O I/O -- -- I I S Tristate 6 10 18 F1 PCR[65] AF0 AF1 AF2 AF3 GPIO[65] E0UC[17] CAN5TX -- SIUL eMIOS_0 FlexCAN_5 -- I/O I/O O -- M Tristate 8 12 20 F4 PCR[66] AF0 AF1 AF2 AF3 -- -- GPIO[66] E0UC[18] -- -- EIRQ[21] SIN_1 SIUL eMIOS_0 -- -- SIUL DSPI_1 I/O I/O -- -- I I M Tristate 89 128 156 D7 SPC560B54/6x PCR[64] AF0 AF1 AF2 AF3 -- -- Package pinouts and signal descriptions 36/134 Table 6. PE[6] PE[7] GPIO[67] E0UC[19] SOUT_1 -- SIUL eMIOS_0 DSPI_1 -- I/O I/O O -- M PCR[68] AF0 AF1 AF2 AF3 -- GPIO[68] E0UC[20] SCK_1 -- EIRQ[9] SIUL eMIOS_0 DSPI_1 -- SIUL I/O I/O I/O -- I PCR[69] AF0 AF1 AF2 AF3 GPIO[69] E0UC[21] CS0_1 MA[2] SIUL eMIOS_0 DSPI_1 ADC_0 PCR[70] AF0 AF1 AF2 AF3 -- GPIO[70] E0UC[22] CS3_0 MA[1] EIRQ[22] PCR[71] AF0 AF1 AF2 AF3 -- GPIO[71] E0UC[23] CS2_0 MA[0] EIRQ[23] configuration(3) PCR[67] AF0 AF1 AF2 AF3 RESET Pad type PE[5] Peripheral PCR Pin number LQFP 100 LQFP 144 LQFP 176 LBGA 208(4) Tristate 90 129 157 C7 M Tristate 93 132 160 D6 I/O I/O I/O O M Tristate 94 133 161 C6 SIUL eMIOS_0 DSPI_0 ADC_0 SIUL I/O I/O O O I M Tristate 95 139 167 B5 SIUL eMIOS_0 DSPI_0 ADC_0 SIUL I/O I/O O O I M Tristate 96 140 168 C4 37/134 Package pinouts and signal descriptions Doc ID 15131 Rev 7 PE[4] Function I/O direction(2) PE[3] Alternate function(1) Port pin Functional port pin descriptions (continued) SPC560B54/6x Table 6. PE[10] PE[11] SIUL FlexCAN_2 eMIOS_0 FlexCAN_3 I/O O I/O O M PCR[73] AF0 AF1 AF2 AF3 -- -- -- GPIO[73] -- E0UC[23] -- WKPU[7]5 CAN2RX CAN3RX SIUL -- eMIOS_0 -- WKPU FlexCAN_2 FlexCAN_3 I/O -- I/O -- I I I PCR[74] AF0 AF1 AF2 AF3 -- GPIO[74] LIN3TX CS3_1 E1UC[30] EIRQ[10] SIUL LINFlex_3 DSPI_1 eMIOS_1 SIUL PCR[75] AF0 AF1 AF2 AF3 -- -- GPIO[75] E0UC[24] CS4_1 -- LIN3RX WKPU[14]5 SIUL eMIOS_0 DSPI_1 -- LINFlex_3 WKPU configuration(3) GPIO[72] CAN2TX E0UC[22] CAN3TX RESET PCR[72] AF0 AF1 AF2 AF3 PCR Pin number LQFP 100 LQFP 144 LQFP 176 LBGA 208(4) Tristate 9 13 21 G2 S Tristate 10 14 22 G1 I/O O O I/O I S Tristate 11 15 23 G3 I/O I/O O -- I I S Tristate 13 17 25 H2 SPC560B54/6x Peripheral Pad type Doc ID 15131 Rev 7 PE[9] Function I/O direction(2) PE[8] Alternate function(1) Port pin Functional port pin descriptions (continued) Package pinouts and signal descriptions 38/134 Table 6. PE[15] GPIO[76] -- E1UC[19](12) -- EIRQ[11] SIN_2 ADC1_S[7] SIUL -- eMIOS_1 -- SIUL DSPI_2 ADC_1 I/O -- I/O -- I I I J PCR[77] AF0 AF1 AF2 AF3 GPIO[77] SOUT_2 E1UC[20] -- SIUL DSPI_2 eMIOS_1 -- I/O O I/O -- PCR[78] AF0 AF1 AF2 AF3 -- GPIO[78] SCK_2 E1UC[21] -- EIRQ[12] SIUL DSPI_2 eMIOS_1 -- SIUL PCR[79] AF0 AF1 AF2 AF3 GPIO[79] CS0_2 E1UC[22] -- SIUL DSPI_2 eMIOS_1 -- configuration(3) PCR[76] AF0 AF1 AF2 AF3 -- -- -- RESET Pad type PE[14] Peripheral PCR Pin number LQFP 100 LQFP 144 LQFP 176 LBGA 208(4) Tristate 76 109 133 C14 S Tristate -- 103 127 D15 I/O I/O I/O -- I S Tristate -- 112 136 C13 I/O I/O I/O -- M Tristate -- 113 137 A13 39/134 Package pinouts and signal descriptions Doc ID 15131 Rev 7 PE[13] Function I/O direction(2) PE[12] Alternate function(1) Port pin Functional port pin descriptions (continued) SPC560B54/6x Table 6. configuration(3) RESET Peripheral Pad type Function I/O direction(2) PCR Alternate function(1) Port pin Functional port pin descriptions (continued) Pin number LQFP 100 LQFP 144 LQFP 176 LBGA 208(4) Port F PF[0] Doc ID 15131 Rev 7 PF[1] PF[2] PF[3] GPIO[80] E0UC[10] CS3_1 -- ADC0_S[8] SIUL eMIOS_0 DSPI_1 -- ADC_0 I/O I/O O -- I J Tristate -- 55 63 N10 PCR[81] AF0 AF1 AF2 AF3 -- GPIO[81] E0UC[11] CS4_1 -- ADC0_S[9] SIUL eMIOS_0 DSPI_1 -- ADC_0 I/O I/O O -- I J Tristate -- 56 64 P10 PCR[82] AF0 AF1 AF2 AF3 -- GPIO[82] E0UC[12] CS0_2 -- ADC0_S[10] SIUL eMIOS_0 DSPI_2 -- ADC_0 I/O I/O I/O -- I J Tristate -- 57 65 T10 PCR[83] AF0 AF1 AF2 AF3 -- GPIO[83] E0UC[13] CS1_2 -- ADC0_S[11] SIUL eMIOS_0 DSPI_2 -- ADC_0 I/O I/O O -- I J Tristate -- 58 66 R10 SPC560B54/6x PCR[80] AF0 AF1 AF2 AF3 -- Package pinouts and signal descriptions 40/134 Table 6. PF[7] PF[8] GPIO[84] E0UC[14] CS2_2 -- ADC0_S[12] SIUL eMIOS_0 DSPI_2 -- ADC_0 I/O I/O O -- I J PCR[85] AF0 AF1 AF2 AF3 -- GPIO[85] E0UC[22] CS3_2 -- ADC0_S[13] SIUL eMIOS_0 DSPI_2 -- ADC_0 I/O I/O O -- I PCR[86] AF0 AF1 AF2 AF3 -- GPIO[86] E0UC[23] CS1_1 -- ADC0_S[14] SIUL eMIOS_0 DSPI_1 -- ADC_0 PCR[87] AF0 AF1 AF2 AF3 -- GPIO[87] -- CS2_1 -- ADC0_S[15] PCR[88] AF0 AF1 AF2 AF3 GPIO[88] CAN3TX CS4_0 CAN2TX configuration(3) PCR[84] AF0 AF1 AF2 AF3 -- RESET Pad type PF[6] Peripheral PCR Pin number LQFP 100 LQFP 144 LQFP 176 LBGA 208(4) Tristate -- 59 67 N11 J Tristate -- 60 68 P11 I/O I/O O -- I J Tristate -- 61 69 T11 SIUL -- DSPI_1 -- ADC_0 I/O -- O -- I J Tristate -- 62 70 R11 SIUL FlexCAN_3 DSPI_0 FlexCAN_2 I/O O O O M Tristate -- 34 42 P1 41/134 Package pinouts and signal descriptions Doc ID 15131 Rev 7 PF[5] Function I/O direction(2) PF[4] Alternate function(1) Port pin Functional port pin descriptions (continued) SPC560B54/6x Table 6. PF[11] PF[12] GPIO[89] E1UC[1] CS5_0 -- WKPU[22]5 CAN2RX CAN3RX SIUL eMIOS_1 DSPI_0 -- WKPU FlexCAN_2 FlexCAN_3 I/O I/O O -- I I I S PCR[90] AF0 AF1 AF2 AF3 GPIO[90] CS1_0 LIN4TX E1UC[2] SIUL DSPI_0 LINFlex_4 eMIOS_1 I/O O O I/O PCR[91] AF0 AF1 AF2 AF3 -- -- GPIO[91] CS2_0 E1UC[3] -- WKPU[15]5 LIN4RX SIUL DSPI_0 eMIOS_1 -- WKPU LINFlex_4 PCR[92] AF0 AF1 AF2 AF3 GPIO[92] E1UC[25] LIN5TX -- SIUL eMIOS_1 LINFlex_5 -- configuration(3) PCR[89] AF0 AF1 AF2 AF3 -- -- -- PCR RESET Peripheral Pad type Doc ID 15131 Rev 7 PF[10] Function I/O direction(2) PF[9] Alternate function(1) Port pin Functional port pin descriptions (continued) Pin number LQFP 100 LQFP 144 LQFP 176 LBGA 208(4) Tristate -- 33 41 N2 M Tristate -- 38 46 R3 I/O O I/O -- I I S Tristate -- 39 47 R4 I/O I/O O -- M Tristate -- 35 43 R1 Package pinouts and signal descriptions 42/134 Table 6. SPC560B54/6x GPIO[93] E1UC[26] -- -- WKPU[16]5 LIN5RX SIUL eMIOS_1 -- -- WKPU LINFlex_5 I/O I/O -- -- I I S PCR[94] AF0 AF1 AF2 AF3 GPIO[94] CAN4TX E1UC[27] CAN1TX SIUL FlexCAN_4 eMIOS_1 FlexCAN_1 I/O O I/O O PCR[95] AF0 AF1 AF2 AF3 -- -- -- GPIO[95] E1UC[4] -- -- EIRQ[13] CAN1RX CAN4RX SIUL eMIOS_1 -- -- SIUL FlexCAN_1 FlexCAN_4 I/O I/O -- -- I I I configuration(3) PCR[93] AF0 AF1 AF2 AF3 -- -- RESET Pad type PF[15] Peripheral PCR Pin number LQFP 100 LQFP 144 LQFP 176 LBGA 208(4) Tristate -- 41 49 T6 M Tristate -- 102 126 D14 S Tristate -- 101 125 E15 M Tristate -- 98 122 E14 Port G PG[0] PCR[96] AF0 AF1 AF2 AF3 GPIO[96] CAN5TX E1UC[23] -- SIUL FlexCAN_5 eMIOS_1 -- I/O O I/O -- 43/134 Package pinouts and signal descriptions Doc ID 15131 Rev 7 PF[14] Function I/O direction(2) PF[13] Alternate function(1) Port pin Functional port pin descriptions (continued) SPC560B54/6x Table 6. PG[3] PG[4] SIUL -- eMIOS_1 -- SIUL FlexCAN_5 I/O -- I/O -- I I S PCR[98] AF0 AF1 AF2 AF3 GPIO[98] E1UC[11] SOUT_3 -- SIUL eMIOS_1 DSPI_3 -- I/O I/O O -- PCR[99] AF0 AF1 AF2 AF3 -- GPIO[99] E1UC[12] CS0_3 -- WKPU[17]5 SIUL eMIOS_1 DSPI_3 -- WKPU PCR[100] AF0 AF1 AF2 AF3 GPIO[100] E1UC[13] SCK_3 -- PCR[101] AF0 AF1 AF2 AF3 -- -- GPIO[101] E1UC[14] -- -- WKPU[18]5 SIN_3 configuration(3) GPIO[97] -- E1UC[24] -- EIRQ[14] CAN5RX RESET PCR[97] AF0 AF1 AF2 AF3 -- -- PCR Pin number LQFP 100 LQFP 144 LQFP 176 LBGA 208(4) Tristate -- 97 121 E13 M Tristate -- 8 16 E4 I/O I/O I/O -- I S Tristate -- 7 15 E3 SIUL eMIOS_1 DSPI_3 -- I/O I/O I/O -- M Tristate -- 6 14 E1 SIUL eMIOS_1 -- -- WKPU DSPI_3 I/O I/O -- -- I I S Tristate -- 5 13 E2 SPC560B54/6x PG[5] Peripheral Pad type Doc ID 15131 Rev 7 PG[2] Function I/O direction(2) PG[1] Alternate function(1) Port pin Functional port pin descriptions (continued) Package pinouts and signal descriptions 44/134 Table 6. PG[9] GPIO[102] E1UC[15] LIN6TX -- SIUL eMIOS_1 LINFlex_6 -- I/O I/O O -- M PCR[103] AF0 AF1 AF2 AF3 -- -- GPIO[103] E1UC[16] E1UC[30] -- WKPU[20]5 LIN6RX SIUL eMIOS_1 eMIOS_1 -- WKPU LINFlex_6 I/O I/O I/O -- I I PCR[104] AF0 AF1 AF2 AF3 -- GPIO[104] E1UC[17] LIN7TX CS0_2 EIRQ[15] SIUL eMIOS_1 LINFlex_7 DSPI_2 SIUL PCR[105] AF0 AF1 AF2 AF3 -- -- GPIO[105] E1UC[18] -- SCK_2 WKPU[21]5 LIN7RX SIUL eMIOS_1 -- DSPI_2 WKPU LINFlex_7 configuration(3) PCR[102] AF0 AF1 AF2 AF3 RESET Pad type PG[8] Peripheral PCR Pin number LQFP 100 LQFP 144 LQFP 176 LBGA 208(4) Tristate -- 30 38 M2 S Tristate -- 29 37 M1 I/O I/O O I/O I S Tristate -- 26 34 L2 I/O I/O -- I/O I I S Tristate -- 25 33 L1 45/134 Package pinouts and signal descriptions Doc ID 15131 Rev 7 PG[7] Function I/O direction(2) PG[6] Alternate function(1) Port pin Functional port pin descriptions (continued) SPC560B54/6x Table 6. PG[12] PG[13] PG[14] SIUL eMIOS_0 eMIOS_1 -- DSPI_4 I/O I/O I/O -- I S PCR[107] AF0 AF1 AF2 AF3 GPIO[107] E0UC[25] CS0_4 -- SIUL eMIOS_0 DSPI_4 -- I/O I/O I/O -- PCR[108] AF0 AF1 AF2 AF3 GPIO[108] E0UC[26] SOUT_4 -- SIUL eMIOS_0 DSPI_4 -- PCR[109] AF0 AF1 AF2 AF3 GPIO[109] E0UC[27] SCK_4 -- PCR[110] AF0 AF1 AF2 AF3 GPIO[110] E1UC[0] LIN8TX -- configuration(3) GPIO[106] E0UC[24] E1UC[31] -- SIN_4 RESET PCR[106] AF0 AF1 AF2 AF3 -- PCR Pin number LQFP 100 LQFP 144 LQFP 176 LBGA 208(4) Tristate -- 114 138 D13 M Tristate -- 115 139 B12 I/O I/O O -- M Tristate -- 92 116 K14 SIUL eMIOS_0 DSPI_4 -- I/O I/O I/O -- M Tristate -- 91 115 K16 SIUL eMIOS_1 LINFlex_8 -- I/O I/O O -- S Tristate -- 110 134 B14 SPC560B54/6x Peripheral Pad type Doc ID 15131 Rev 7 PG[11] Function I/O direction(2) PG[10] Alternate function(1) Port pin Functional port pin descriptions (continued) Package pinouts and signal descriptions 46/134 Table 6. GPIO[111] E1UC[1] -- -- LIN8RX SIUL eMIOS_1 -- -- LINFlex_8 configuration(3) AF0 AF1 AF2 AF3 -- I/O I/O -- -- I M Tristate -- 111 135 B13 RESET Peripheral Pad type PCR[111] Function Pin number I/O direction(2) PG[15] PCR Alternate function(1) Port pin Functional port pin descriptions (continued) LQFP 100 LQFP 144 LQFP 176 LBGA 208(4) SPC560B54/6x Table 6. Port H PH[1] PH[2] PH[3] PCR[112] GPIO[112] E1UC[2] -- -- SIN_1 SIUL eMIOS_1 -- -- DSPI_1 I/O I/O -- -- I M Tristate -- 93 117 F13 PCR[113] AF0 AF1 AF2 AF3 GPIO[113] E1UC[3] SOUT_1 -- SIUL eMIOS_1 DSPI_1 -- I/O I/O O -- M Tristate -- 94 118 F14 PCR[114] AF0 AF1 AF2 AF3 GPIO[114] E1UC[4] SCK_1 -- SIUL eMIOS_1 DSPI_1 -- I/O I/O I/O -- M Tristate -- 95 119 F16 PCR[115] AF0 AF1 AF2 AF3 GPIO[115] E1UC[5] CS0_1 -- SIUL eMIOS_1 DSPI_1 -- I/O I/O I/O -- M Tristate -- 96 120 F15 47/134 Package pinouts and signal descriptions Doc ID 15131 Rev 7 PH[0] AF0 AF1 AF2 AF3 -- PH[6] PH[7] PH[8] SIUL eMIOS_1 -- -- I/O I/O -- -- M PCR[117] AF0 AF1 AF2 AF3 GPIO[117] E1UC[7] -- -- SIUL eMIOS_1 -- -- I/O I/O -- -- PCR[118] AF0 AF1 AF2 AF3 GPIO[118] E1UC[8] -- MA[2] SIUL eMIOS_1 -- ADC_0 PCR[119] AF0 AF1 AF2 AF3 GPIO[119] E1UC[9] CS3_2 MA[1] PCR[120] AF0 AF1 AF2 AF3 PCR[121] AF0 AF1 AF2 AF3 configuration(3) GPIO[116] E1UC[6] -- -- RESET PCR[116] AF0 AF1 AF2 AF3 PCR Pin number LQFP 100 LQFP 144 LQFP 176 LBGA 208(4) Tristate -- 134 162 A6 S Tristate -- 135 163 B6 I/O I/O -- O M Tristate -- 136 164 D5 SIUL eMIOS_1 DSPI_2 ADC_0 I/O I/O O O M Tristate -- 137 165 C5 GPIO[120] E1UC[10] CS2_2 MA[0] SIUL eMIOS_1 DSPI_2 ADC_0 I/O I/O O O M Tristate -- 138 166 A5 GPIO[121] -- TCK -- SIUL -- JTAGC -- I/O -- I -- S Input, weak pull-up 88 127 155 B8 SPC560B54/6x PH[9]10 Peripheral Pad type Doc ID 15131 Rev 7 PH[5] Function I/O direction(2) PH[4] Alternate function(1) Port pin Functional port pin descriptions (continued) Package pinouts and signal descriptions 48/134 Table 6. PH[13] PH[14] PH[15] 49/134 GPIO[122] -- TMS -- SIUL -- JTAGC -- I/O -- I -- M PCR[123] AF0 AF1 AF2 AF3 GPIO[123] SOUT_3 CS0_4 E1UC[5] SIUL DSPI_3 DSPI_4 eMIOS_1 I/O O I/O I/O PCR[124] AF0 AF1 AF2 AF3 GPIO[124] SCK_3 CS1_4 E1UC[25] SIUL DSPI_3 DSPI_4 eMIOS_1 PCR[125] AF0 AF1 AF2 AF3 GPIO[125] SOUT_4 CS0_3 E1UC[26] PCR[126] AF0 AF1 AF2 AF3 PCR[127] AF0 AF1 AF2 AF3 configuration(3) PCR[122] AF0 AF1 AF2 AF3 RESET Pad type PH[12] Peripheral PCR Pin number LQFP 100 LQFP 144 LQFP 176 LBGA 208(4) Input, weak pull-up 81 120 148 B9 M Tristate -- -- 140 A14 I/O I/O O I/O M Tristate -- -- 141 D12 SIUL DSPI_4 DSPI_3 eMIOS_1 I/O O I/O I/O M Tristate -- -- 9 B3 GPIO[126] SCK_4 CS1_3 E1UC[27] SIUL DSPI_4 DSPI_3 eMIOS_1 I/O I/O O I/O M Tristate -- -- 10 D1 GPIO[127] SOUT_5 -- E1UC[17] SIUL DSPI_5 -- eMIOS_1 I/O O -- I/O M Tristate -- -- 8 A3 Package pinouts and signal descriptions Doc ID 15131 Rev 7 PH[11] Function I/O direction(2) PH[10]10 Alternate function(1) Port pin Functional port pin descriptions (continued) SPC560B54/6x Table 6. configuration(3) RESET Peripheral Pad type Function I/O direction(2) PCR Alternate function(1) Port pin Functional port pin descriptions (continued) Pin number LQFP 100 LQFP 144 LQFP 176 LBGA 208(4) Port I PI[0] Doc ID 15131 Rev 7 PI[1] PI[2] PI[3] GPIO[128] E0UC[28] LIN8TX -- SIUL eMIOS_0 LINFlex_8 -- I/O I/O O -- S Tristate -- -- 172 A9 PCR[129] AF0 AF1 AF2 AF3 -- -- GPIO[129] E0UC[29] -- -- WKPU[24]5 LIN8RX SIUL eMIOS_0 -- -- WKPU LINFlex_8 I/O I/O -- -- I I S Tristate -- -- 171 A10 PCR[130] AF0 AF1 AF2 AF3 GPIO[130] E0UC[30] LIN9TX -- SIUL eMIOS_0 LINFlex_9 -- I/O I/O O -- S Tristate -- -- 170 B10 PCR[131] AF0 AF1 AF2 AF3 -- -- GPIO[131] E0UC[31] -- -- WKPU[23]5 LIN9RX SIUL eMIOS_0 -- -- WKPU LINFlex_9 I/O I/O -- -- I I S Tristate -- -- 169 C10 PCR[132] AF0 AF1 AF2 AF3 GPIO[132] E1UC[28] SOUT_4 -- SIUL eMIOS_1 DSPI_4 -- I/O I/O O -- S Tristate -- -- 143 A12 SPC560B54/6x PI[4] PCR[128] AF0 AF1 AF2 AF3 Package pinouts and signal descriptions 50/134 Table 6. PI[8] PI[9] GPIO[133] E1UC[29] SCK_4 -- SIUL eMIOS_1 DSPI_4 -- I/O I/O I/O -- S PCR[134] AF0 AF1 AF2 AF3 GPIO[134] E1UC[30] CS0_4 -- SIUL eMIOS_1 DSPI_4 -- I/O I/O I/O -- PCR[135] AF0 AF1 AF2 AF3 GPIO[135] E1UC[31] CS1_4 -- SIUL eMIOS_1 DSPI_4 -- PCR[136] AF0 AF1 AF2 AF3 -- GPIO[136] -- -- -- ADC0_S[16] PCR[137] AF0 AF1 AF2 AF3 -- GPIO[137] -- -- -- ADC0_S[17] configuration(3) PCR[133] AF0 AF1 AF2 AF3 RESET Pad type PI[7] Peripheral PCR Pin number LQFP 100 LQFP 144 LQFP 176 LBGA 208(4) Tristate -- -- 142 C12 S Tristate -- -- 11 D2 I/O I/O O -- S Tristate -- -- 12 D3 SIUL -- -- -- ADC_0 I/O -- -- -- I J Tristate -- -- 108 J13 SIUL -- -- -- ADC_0 I/O -- -- -- I J Tristate -- -- 109 J14 51/134 Package pinouts and signal descriptions Doc ID 15131 Rev 7 PI[6] Function I/O direction(2) PI[5] Alternate function(1) Port pin Functional port pin descriptions (continued) SPC560B54/6x Table 6. PI[12] PI[13] GPIO[138] -- -- -- ADC0_S[18] SIUL -- -- -- ADC_0 I/O -- -- -- I J PCR[139] AF0 AF1 AF2 AF3 -- -- GPIO[139] -- -- -- ADC0_S[19] SIN_3 SIUL -- -- -- ADC_0 DSPI_3 I/O -- -- -- I I PCR[140] AF0 AF1 AF2 AF3 -- GPIO[140] CS0_3 -- -- ADC0_S[20] SIUL DSPI_3 -- -- ADC_0 PCR[141] AF0 AF1 AF2 AF3 -- GPIO[141] CS1_3 -- -- ADC0_S[21] SIUL DSPI_3 -- -- ADC_0 configuration(3) PCR[138] AF0 AF1 AF2 AF3 -- PCR RESET Peripheral Pad type Doc ID 15131 Rev 7 PI[11] Function I/O direction(2) PI[10] Alternate function(1) Port pin Functional port pin descriptions (continued) Pin number LQFP 100 LQFP 144 LQFP 176 LBGA 208(4) Tristate -- -- 110 J15 J Tristate -- -- 111 J16 I/O I/O -- -- I J Tristate -- -- 112 G14 I/O O -- -- I J Tristate -- -- 113 G15 Package pinouts and signal descriptions 52/134 Table 6. SPC560B54/6x GPIO[142] -- -- -- ADC0_S[22] SIN_4 SIUL -- -- -- ADC_0 DSPI_4 I/O -- -- -- I I J PCR[143] AF0 AF1 AF2 AF3 -- GPIO[143] CS0_4 -- -- ADC0_S[23] SIUL DSPI_4 -- -- ADC_0 I/O I/O -- -- I configuration(3) Pad type PCR[142] AF0 AF1 AF2 AF3 -- -- RESET Peripheral PCR Pin number LQFP 100 LQFP 144 LQFP 176 LBGA 208(4) Tristate -- -- 76 R8 J Tristate -- -- 75 T8 Port J PJ[0] PJ[1] PCR[144] AF0 AF1 AF2 AF3 -- GPIO[144] CS1_4 -- -- ADC0_S[24] SIUL DSPI_4 -- -- ADC_0 I/O O -- -- I J Tristate -- -- 74 N5 PCR[145] AF0 AF1 AF2 AF3 -- -- GPIO[145] -- -- -- ADC0_S[25] SIN_5 SIUL -- -- ---- ADC_0 DSPI_5 I/O -- -- -- I I J Tristate -- -- 73 P5 53/134 Package pinouts and signal descriptions Doc ID 15131 Rev 7 PI[15] Function I/O direction(2) PI[14] Alternate function(1) Port pin Functional port pin descriptions (continued) SPC560B54/6x Table 6. PJ[4] GPIO[146] CS0_5 -- -- ADC0_S[26] SIUL DSPI_5 -- -- ADC_0 I/O I/O -- -- I J PCR[147] AF0 AF1 AF2 AF3 -- GPIO[147] CS1_5 -- -- ADC0_S[27] SIUL DSPI_5 -- -- ADC_0 I/O O -- -- I PCR[148] AF0 AF1 AF2 AF3 GPIO[148] SCK_5 E1UC[18] -- SIUL DSPI_5 eMIOS_1 -- I/O I/O I/O -- configuration(3) PCR[146] AF0 AF1 AF2 AF3 -- PCR RESET Peripheral Pad type Doc ID 15131 Rev 7 PJ[3] Function I/O direction(2) PJ[2] Alternate function(1) Port pin Functional port pin descriptions (continued) Pin number LQFP 100 LQFP 144 LQFP 176 LBGA 208(4) Tristate -- -- 72 P4 J Tristate -- -- 71 P2 M Tristate -- -- 5 A4 Package pinouts and signal descriptions 54/134 Table 6. 1. Alternate functions are chosen by setting the values of the PCR.PA bitfields inside the SIUL module. PCR.PA = 00 AF0; PCR.PA = 01 AF1; PCR.PA = 10 AF2; PCR.PA = 11 AF2. This is intended to select the output functions; to use one of the input functions, the PCR.IBE bit must be written to `1', regardless of the values selected in the PCR.PA bitfields. For this reason, the value corresponding to an input only function is reported as "--". 2. Multiple inputs are routed to all respective modules internally. The input of some modules must be configured by setting the values of the PSMIO.PADSELx bitfields inside the SIUL module. 3. The RESET configuration applies during and after reset. 4. LBGA208 available only as development package for Nexus2+ 5. All WKPU pins also support external interrupt capability. See the WKPU chapter for further details. 7. "Not applicable" because these functions are available only while the device is booting. Refer to the BAM information for details. 8. Value of PCR.IBE bit must be 0 9. This wakeup input cannot be used to exit STANDBY mode. SPC560B54/6x 6. NMI has higher priority than alternate function. When NMI is selected, the PCR.AF field is ignored. 11. PC[1] is a fast/medium pad but is in medium configuration by default. This pad is in Alternate Function 2 mode after reset which has TDO functionality. The reset value of PCR.OBE is `1', but this setting has no impact as long as this pad stays in AF2 mode. After configuring this pad as GPIO (PCR.PA = 0), output buffer is enabled as reset value of PCR.OBE = 1. SPC560B54/6x 10. Out of reset all the functional pins except PC[0:1] and PH[9:10] are available to the user as GPIO. PC[0:1] are available as JTAG pins (TDI and TDO respectively). PH[9:10] are available as JTAG pins (TCK and TMS respectively). It is up to the user to configure these pins as GPIO when needed. 12. Not available in LQFP100 package 55/134 Package pinouts and signal descriptions Doc ID 15131 Rev 7 Package pinouts and signal descriptions 3.8 SPC560B54/6x Nexus 2+ pins In the LBGA208 package, eight additional debug pins are available (see Table 7). Table 7. Nexus 2+ pin descriptions Pin number Port pin Function I/O direction Pad type Function after reset MCKO Message clock out O F MDO0 Message data out 0 O MDO1 Message data out 1 MDO2 LQFP 100 LQFP 144 LBGA 208(1) -- -- -- T4 M -- -- -- H15 O M -- -- -- H16 Message data out 2 O M -- -- -- H14 MDO3 Message data out 3 O M -- -- -- H13 EVTI Event in I M Pull-up -- -- K1 EVTO Event out O M -- -- -- L4 MSEO Message start/end out O M -- -- -- G16 1. LBGA208 available only as development package for Nexus2+ 56/134 Doc ID 15131 Rev 7 SPC560B54/6x 4 Electrical characteristics Electrical characteristics This section contains electrical characteristics of the device as well as temperature and power considerations. This product contains devices to protect the inputs against damage due to high static voltages. However, it is advisable to take precautions to avoid application of any voltage higher than the specified maximum rated voltages. To enhance reliability, unused inputs can be driven to an appropriate logic voltage level (VDD or VSS). This could be done by the internal pull-up and pull-down, which is provided by the product for most general purpose pins. The parameters listed in the following tables represent the characteristics of the device and its demands on the system. In the tables where the device logic provides signals with their respective timing characteristics, the symbol "CC" for Controller Characteristics is included in the Symbol column. In the tables where the external system must provide signals with their respective timing characteristics to the device, the symbol "SR" for System Requirement is included in the Symbol column. 4.1 Parameter classification The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding, the classifications listed in Table 8 are used and the parameters are tagged accordingly in the tables where appropriate. Table 8. Parameter classifications Classification tag Tag description P Those parameters are guaranteed during production testing on each individual device. C Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. T Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category. D Those parameters are derived mainly from simulations. Note: The classification is shown in the column labeled "C" in the parameter tables where appropriate. 4.2 NVUSRO register Bit values in the Non-Volatile User Options (NVUSRO) Register control portions of the device configuration, namely electrical parameters such as high voltage supply and oscillator margin, as well as digital functionality (watchdog enable/disable after reset). Doc ID 15131 Rev 7 57/134 Electrical characteristics SPC560B54/6x For a detailed description of the NVUSRO register, please refer to the device reference manual. 4.2.1 NVUSRO[PAD3V5V] field description The DC electrical characteristics are dependent on the PAD3V5V bit value. Table 9 shows how NVUSRO[PAD3V5V] controls the device configuration. Table 9. PAD3V5V field description(1) Value(2) Description 0 High voltage supply is 5.0 V 1 High voltage supply is 3.3 V 1. See the device reference manual for more information on the NVUSRO register. 2. Default manufacturing value is `1'. Value can be programmed by customer in Shadow Flash. 4.2.2 NVUSRO[OSCILLATOR_MARGIN] field description The fast external crystal oscillator consumption is dependent on the OSCILLATOR_MARGIN bit value. Table 10 shows how NVUSRO[OSCILLATOR_MARGIN] controls the device configuration. Table 10. OSCILLATOR_MARGIN field description(1) Value(2) Description 0 Low consumption configuration (4 MHz/8 MHz) 1 High margin configuration (4 MHz/16 MHz) 1. See the device reference manual for more information on the NVUSRO register. 2. Default manufacturing value is `1'. Value can be programmed by customer in Shadow Flash. 4.2.3 NVUSRO[WATCHDOG_EN] field description The watchdog enable/disable configuration after reset is dependent on the WATCHDOG_EN bit value. Table 11 shows how NVUSRO[WATCHDOG_EN] controls the device configuration. Table 11. WATCHDOG_EN field description Value(1) Description 0 Disable after reset 1 Enable after reset 1. Default manufacturing value is `1'. Value can be programmed by customer in Shadow Flash. 58/134 Doc ID 15131 Rev 7 SPC560B54/6x Electrical characteristics 4.3 Absolute maximum ratings Table 12. Absolute maximum ratings Value Symbol Parameter Conditions Unit Min Max -- 0 0 V VSS SR Digital ground on VSS_HV pins VDD SR Voltage on VDD_HV pins with respect to ground (VSS) -- -0.3 6.0 V VSS_LV SR Voltage on VSS_LV (low voltage digital supply) pins with respect to ground (VSS) -- VSS - 0.1 VSS + 0.1 V -0.3 6.0 SR Voltage on VDD_BV (regulator supply) pin with respect to ground (VSS) -- VDD_BV -0.3 VDD + 0.3 VSS_ADC Voltage on VSS_HV_ADC0, SR VSS_HV_ADC1 (ADC reference) pins with respect to ground (VSS) -- VSS - 0.1 VSS + 0.1 Voltage on VDD_HV_ADC0, SR VDD_HV_ADC1 (ADC reference) pins with respect to ground (VSS) -- -0.3 6.0 VDD_ADC VDD 0.3 VDD + 0.3 -0.3 6.0 -- VDD + 0.3 Voltage on any GPIO pin with respect to ground (VSS) V Relative to VDD Relative to VDD -- V V VIN SR IINJPAD SR Injected input current on any pin during overload condition -- -10 10 IINJSUM SR Absolute sum of all injected input currents during overload condition -- -50 50 VDD = 5.0 V 10%, PAD3V5V = 0 -- 70 VDD = 3.3 V 10%, PAD3V5V = 1 -- 64 -- -55 150 V Relative to VDD mA IAVGSEG Sum of all the static I/O current within a SR supply segment mA TSTORAGE SR Storage temperature Note: C Stresses exceeding the recommended absolute maximum ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification are not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During overload conditions (VIN > VDD or VIN < VSS), the voltage on pins with respect to ground (VSS) must not exceed the recommended values. Doc ID 15131 Rev 7 59/134 Electrical characteristics SPC560B54/6x 4.4 Recommended operating conditions Table 13. Recommended operating conditions (3.3 V) Value Symbol VSS Parameter Conditions SR Digital ground on VSS_HV pins Unit Min Max -- 0 0 V VDD(1) SR Voltage on VDD_HV pins with respect to ground (VSS) -- 3.0 3.6 V VSS_LV(2) SR Voltage on VSS_LV (low voltage digital supply) pins with respect to ground (VSS) -- VSS 0.1 VSS + 0.1 V VDD_BV(3) -- Voltage on VDD_BV pin (regulator supply) with respect to ground (VSS) Relative to VDD 3.0 3.6 SR VDD 0.1 VDD + 0.1 VSS_ADC Voltage on VSS_HV_ADC0, SR VSS_HV_ADC1 (ADC reference) pin with respect to ground (VSS) -- VSS 0.1 VSS + 0.1 -- 3.0(5) 3.6 VDD 0.1 VDD + 0.1 VSS 0.1 -- -- VDD + 0.1 VDD_ADC (4) Voltage on VDD_HV_ADC0, SR VDD_HV_ADC1 (ADC reference) with respect to ground (VSS) Voltage on any GPIO pin with respect to ground (VSS) Relative to VDD -- V V VIN SR IINJPAD SR Injected input current on any pin during overload condition -- 5 5 IINJSUM SR Absolute sum of all injected input currents during overload condition -- 50 50 -- -- 0.25 Relative to VDD V V mA TVDD SR VDD slope to ensure correct power up(6) V/s 1. 100 nF capacitance needs to be provided between each VDD/VSS pair. 2. 330 nF capacitance needs to be provided between each VDD_LV/VSS_LV supply pair. 3. 470 nF capacitance needs to be provided between VDD_BV and the nearest VSS_LV (higher value may be needed depending on external regulator characteristics). Supply ramp slope on VDD_BV should always be faster or equal to slope of VDD_HV. Otherwise, device may enter regulator bypass mode if slope on VDD_BV is slower. 4. 100 nF capacitance needs to be provided between VDD_ADC/VSS_ADC pair. 5. Full electrical specification cannot be guaranteed when voltage drops below 3.0 V. In particular, ADC electrical characteristics and I/Os DC electrical specification may not be guaranteed. When voltage drops below VLVDHVL, device is reset. 6. Guaranteed by device validation Table 14. Recommended operating conditions (5.0 V) Value Symbol VSS VDD(1) 60/134 Parameter Conditions Max -- 0 0 -- 4.5 5.5 Voltage drop(2) 3.0 5.5 SR Digital ground on VSS_HV pins SR Voltage on VDD_HV pins with respect to ground (VSS) Unit Min Doc ID 15131 Rev 7 V V SPC560B54/6x Table 14. Electrical characteristics Recommended operating conditions (5.0 V) (continued) Value Symbol Parameter SR VDD_BV(4) Voltage on VDD_BV pin (regulator supply) SR with respect to ground (VSS) VDD_ADC(5) Max -- VSS 0.1 VSS + 0.1 -- 4.5 5.5 Voltage drop(2) 3.0 5.5 Relative to VDD 3.0 VDD + 0.1 -- VSS 0.1 VSS + 0.1 4.5 5.5 3.0 5.5 VDD 0.1 VDD + 0.1 -- VSS 0.1 -- Relative to VDD -- VDD + 0.1 Voltage on VSS_HV_ADC0, VSS_HV_ADC1 SR (ADC reference) pin with respect to ground (VSS) -- Voltage on VDD_HV_ADC0, VDD_HV_ADC1 SR Voltage drop(2) (ADC reference) with respect to ground (VSS) Relative to VDD Voltage on any GPIO pin with respect to ground (VSS) Unit Min Voltage on VSS_LV (low voltage digital supply) pins with respect to ground (VSS) VSS_LV(3) VSS_ADC Conditions VIN SR IINJPAD SR Injected input current on any pin during overload condition -- 5 5 IINJSUM SR Absolute sum of all injected input currents during overload condition -- 50 50 -- -- 0.25 V V V V V mA TVDD SR VDD slope to ensure correct power up(6) V/s 1. 100 nF capacitance needs to be provided between each VDD/VSS pair. 2. Full device operation is guaranteed by design when the voltage drops below 4.5 V down to 3.0 V. However, certain analog electrical characteristics will not be guaranteed to stay within the stated limits. 3. 330 nF capacitance needs to be provided between each VDD_LV/VSS_LV supply pair. 4. 470 nF capacitance needs to be provided between VDD_BV and the nearest VSS_LV (higher value may be needed depending on external regulator characteristics). While the supply voltage ramps up, the slope on VDD_BV should be less than 0.9VDD_HV in order to ensure the device does not enter regulator bypass mode. 5. 100 nF capacitance needs to be provided between VDD_ADC/VSS_ADC pair. 6. Guaranteed by device validation. Please refer to Section 4.5.1: External ballast resistor recommendations for minimum VDD slope to be guaranteed to ensure correct power up in case of external resistor usage. Note: RAM data retention is guaranteed with VDD_LV not below 1.08 V. 4.5 Thermal characteristics 4.5.1 External ballast resistor recommendations External ballast resistor on VDD_BV pin helps in reducing the overall power dissipation inside the device. This resistor is required only when maximum power consumption exceeds the limit imposed by package thermal characteristics. As stated in Table 15 LQFP thermal characteristics, considering a thermal resistance of LQFP144 as 48.3 C/W, at ambient temperature TA = 125 C, the junction temperature Tj will cross 150 C if the total power dissipation is greater than Doc ID 15131 Rev 7 61/134 Electrical characteristics SPC560B54/6x (150 - 125)/48.3 = 517 mW. Therefore, the total device current IDDMAX at 125 C/5.5 V must not exceed 94.1 mA (i.e., PD/VDD). Assuming an average IDD(VDD_HV) of 15-20 mA consumption typically during device RUN mode, the LV domain consumption IDD(VDD_BV) is thus limited to IDDMAX - IDD(VDD_HV), i.e., 80 mA. Therefore, respecting the maximum power allowed as explained in Section 4.5.2: Package thermal characteristics, it is recommended to use this resistor only in the 125 C/5.5 V operating corner as per the following guidelines: If IDD(VDD_BV) < 80 mA, then no resistor is required. If 80 mA < IDD(VDD_BV) < 90 mA, then 4 resistor can be used. If IDD(VDD_BV) > 90 mA, then 8 resistor can be used. Using resistance in the range of 4-8 , the gain will be around 10-20% of total consumption on VDD_BV. For example, if 8 resistor is used, then power consumption when IDD(VDD_BV) is 110 mA is equivalent to power consumption when IDD(VDD_BV) is 90 mA (approximately) when resistor not used. In order to ensure correct power up, the minimum VDD_BV to be guaranteed is 30 ms/V. If the supply ramp is slower than this value, then LVDHV3B monitoring ballast supply VDD_BV pin gets triggered leading to device reset. Until the supply reaches certain threshold, this low voltage detector (LVD) generates destructive reset event in the system. This threshold depends on the maximum IDD(VDD_BV) possible across the external resistor. 4.5.2 Package thermal characteristics Table 15. LQFP thermal characteristics(1) Symbol C Parameter Conditions(2) Single-layer board -- 1s RJA Thermal resistance, junctionCC D to-ambient natural convection(3) Single-layer board -- 1s CC Thermal resistance, junctionto-board(4) Typ Max 100 -- -- 64 144 -- -- 64 176 -- -- 64 100 -- -- 49.7 144 -- -- 48.3 176 -- -- 47.3 100 -- -- 36 144 -- -- 38 176 -- -- 38 100 -- -- 33.6 144 -- -- 33.4 176 -- -- 33.4 C/W Four-layer board -- 2s2p 62/134 Unit Min C/W Four-layer board -- 2s2p RJB Value Pin count Doc ID 15131 Rev 7 SPC560B54/6x Table 15. Symbol Electrical characteristics LQFP thermal characteristics(1) (continued) C Conditions(2) Parameter Value Pin count Single-layer board -- 1s RJC CC Thermal resistance, junctionto-case(5) Unit Min Typ Max 100 -- -- 23 144 -- -- 23 176 -- -- 23 100 -- -- 19.8 144 -- -- 19.2 176 -- -- 18.8 C/W Four-layer board -- 2s2p 1. Thermal characteristics are targets based on simulation. 2. VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 125 C. 3. Junction-to-ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets JEDEC specification for this package. When Greek letters are not available, the symbols are typed as RthJA and RthJMA. 4. Junction-to-board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification for the specified package. When Greek letters are not available, the symbols are typed as RthJB. 5. Junction-to-case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer. When Greek letters are not available, the symbols are typed as RthJC. 4.5.3 Power considerations The average chip-junction temperature, TJ, in degrees Celsius, may be calculated using <Cross Refs>Equation 1: Equation 1: TJ = TA + (PD x RJA) Where: TA is the ambient temperature in C. RJA is the package junction-to-ambient thermal resistance, in C/W. PD is the sum of PINT and PI/O (PD = PINT + PI/O). PINT is the product of IDD and VDD, expressed in watts. This is the chip internal power. PI/O represents the power dissipation on input and output pins; user determined. Most of the time for the applications, PI/O < PINT and may be neglected. On the other hand, PI/O may be significant, if the device is configured to continuously drive external modules and/or memories. An approximate relationship between PD and TJ (if PI/O is neglected) is given by: Equation 2: PD = K / (TJ + 273 C) Therefore, solving equations <Cross Refs>1 and <Cross Refs>2: Equation 3: K = PD x (TA + 273 C) + RJA x PD2 Where: K is a constant for the particular part, which may be determined from <Cross Refs>Equation 3 by measuring PD (at equilibrium) for a known TA. Using this value Doc ID 15131 Rev 7 63/134 Electrical characteristics SPC560B54/6x of K, the values of PD and TJ may be obtained by solving equations <Cross Refs>1 and <Cross Refs>2 iteratively for any value of TA. 4.6 I/O pad electrical characteristics 4.6.1 I/O pad types The device provides four main I/O pad types depending on the associated alternate functions: Slow pads--are the most common pads, providing a good compromise between transition time and low electromagnetic emission. Medium pads--provide transition fast enough for the serial communication channels with controlled current to reduce electromagnetic emission. Fast pads--provide maximum speed. These are used for improved Nexus debugging capability. Input only pads--are associated with ADC channels and 32 kHz low power external crystal oscillator providing low input leakage. Medium and Fast pads can use slow configuration to reduce electromagnetic emission, at the cost of reducing AC performance. 4.6.2 I/O input DC characteristics Table 16 provides input DC electrical characteristics as described in Figure 6. Figure 6. I/O input DC electrical characteristics definition VIN VDD VIH VHYS VIL PDIx = `1 (GPDI register of SIUL) PDIx = `0' 64/134 Doc ID 15131 Rev 7 SPC560B54/6x Table 16. Electrical characteristics I/O input DC electrical characteristics Symbol C Value Conditions(1) Parameter Unit Min Typ Max VIH SR P Input high level CMOS (Schmitt Trigger) -- 0.65VDD -- VDD + 0.4 VIL SR P Input low level CMOS (Schmitt Trigger) -- 0.4 -- 0.35VDD VHYS CC C Input hysteresis CMOS (Schmitt Trigger) -- 0.1VDD -- -- ILKG WFI (2) WNFI (2) CC D TA = 40 C -- 2 200 D -- 2 200 -- 5 300 D T = 25 C No injection A on adjacent TA = 85 C pin TA = 105 C -- 12 500 P TA = 125 C -- 70 1000 D Digital input leakage V nA SR P Wakeup input filtered pulse -- -- -- 40 ns SR P Wakeup input not filtered pulse -- 1000 -- -- ns 1. VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 125 C, unless otherwise specified 2. In the range from 40 to 1000 ns, pulses can be filtered or not filtered, according to operating temperature and voltage. 4.6.3 I/O output DC characteristics The following tables provide DC characteristics for bidirectional pads: Table 17. Symbol Table 17 provides weak pull figures. Both pull-up and pull-down resistances are supported. Table 18 provides output driver characteristics for I/O pads when in SLOW configuration. Table 19 provides output driver characteristics for I/O pads when in MEDIUM configuration. Table 20 provides output driver characteristics for I/O pads when in FAST configuration. I/O pull-up/pull-down DC electrical characteristics C Parameter Value Conditions(1) Unit Min PAD3V5V = 0 Typ Max 10 -- 150 10 -- 250 VIN = VIL, VDD = 3.3 V 10% PAD3V5V = 1 10 -- 150 PAD3V5V = 0 VIN = VIH, VDD = 5.0 V 10% Weak pull-down PAD3V5V = 1 |IWPD| CC C current absolute value P VIN = VIH, VDD = 3.3 V 10% PAD3V5V = 1 10 -- 150 10 -- 250 10 -- 150 P Weak pull-up current |IWPU| CC C absolute value P VIN = VIL, VDD = 5.0 V 10% PAD3V5V = P 1(2) A A 1. VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 125 C, unless otherwise specified. Doc ID 15131 Rev 7 65/134 Electrical characteristics SPC560B54/6x 2. The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but RESET and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state. Table 18. Symbol SLOW configuration output buffer electrical characteristics C Parameter VOL CC CC Unit Min Typ Max IOH = 2 mA, VDD = 5.0 V 10%, PAD3V5V = 0 (recommended) 0.8VDD -- -- IOH = 2 mA, Push Pull VDD = 5.0 V 10%, PAD3V5V = 1(2) 0.8VDD -- -- C IOH = 1 mA, VDD = 3.3 V 10%, PAD3V5V = 1 (recommended) VDD 0.8 -- -- P IOL = 2 mA, VDD = 5.0 V 10%, PAD3V5V = 0 (recommended) -- -- 0.1VDD IOL = 2 mA, Push Pull VDD = 5.0 V 10%, PAD3V5V = 1(2) -- -- 0.1VDD IOL = 1 mA, VDD = 3.3 V 10%, PAD3V5V = 1 (recommended) -- -- 0.5 P VOH Value Conditions(1) C C C Output high level SLOW configuration Output low level SLOW configuration 1. VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 125 C, unless otherwise specified 2. The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but RESET and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state. 66/134 Doc ID 15131 Rev 7 V V SPC560B54/6x Table 19. Symbol Electrical characteristics MEDIUM configuration output buffer electrical characteristics C Value Conditions(1) Parameter Unit Min Typ Max C IOH = 3.8 mA, VDD = 5.0 V 10%, PAD3V5V = 0 0.8VDD -- -- P IOH = 2 mA, VDD = 5.0 V 10%, PAD3V5V = 0 (recommended) 0.8VDD -- -- IOH = 1 mA, VDD = 5.0 V 10%, PAD3V5V = 1(2) 0.8VDD -- -- Output high level VOH CC C MEDIUM configuration Push Pull C IOH = 1 mA, VDD = 3.3 V 10%, PAD3V5V = 1 (recommended) VDD 0.8 -- -- C IOH = 100 A, VDD = 5.0 V 10%, PAD3V5V = 0 0.8VDD -- -- C IOL = 3.8 mA, VDD = 5.0 V 10%, PAD3V5V = 0 -- -- 0.2VDD P IOL = 2 mA, VDD = 5.0 V 10%, PAD3V5V = 0 (recommended) -- -- 0.1VDD IOL = 1 mA, VDD = 5.0 V 10%, PAD3V5V = 1(2) -- -- 0.1VDD C IOL = 1 mA, VDD = 3.3 V 10%, PAD3V5V = 1 (recommended) -- -- 0.5 C IOL = 100 A, VDD = 5.0 V 10%, PAD3V5V = 0 -- -- 0.1VDD Output low level VOL CC C MEDIUM configuration Push Pull V V 1. VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 125 C, unless otherwise specified 2. The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but RESET and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state. Table 20. Symbol FAST configuration output buffer electrical characteristics C P VOH CC Output high level C FAST configuration C Value Conditions(1) Parameter Push Pull Unit Min Typ Max IOH = 14 mA, VDD = 5.0 V 10%, PAD3V5V = 0 (recommended) 0.8VDD -- -- IOH = 7 mA, VDD = 5.0 V 10%, PAD3V5V = 1(2) 0.8VDD -- -- VDD 0.8 -- -- IOH = 11 mA, VDD = 3.3 V 10%, PAD3V5V = 1 (recommended) Doc ID 15131 Rev 7 V 67/134 Electrical characteristics Table 20. Symbol VOL CC SPC560B54/6x FAST configuration output buffer electrical characteristics (continued) C Value Conditions(1) Parameter Unit Min Typ Max P IOL = 14 mA, VDD = 5.0 V 10%, PAD3V5V = 0 (recommended) -- -- 0.1VDD Output low level Push C FAST Pull configuration IOL = 7 mA, VDD = 5.0 V 10%, PAD3V5V = 1(2) -- -- 0.1VDD C IOL = 11 mA, VDD = 3.3 V 10%, PAD3V5V = 1 (recommended) -- -- 0.5 V 1. VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 125 C, unless otherwise specified 2. The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but RESET and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state. 4.6.4 Output pin transition times Table 21. Output pin transition times Symbol C Value Conditions(1) Parameter Unit Min Typ Max D T Ttr Ttr CC CC CL = 25 pF CL = 50 pF VDD = 5.0 V 10%, PAD3V5V = 0 D Output transition time output pin(2) CL = 100 pF D SLOW configuration CL = 25 pF T CL = 50 pF D CL = 100 pF D CL = 25 pF T CL = 50 pF D Output transition time output pin(2) CL = 100 pF D MEDIUM configuration CL = 25 pF T CL = 50 pF D CL = 100 pF Ttr CC D VDD = 3.3 V 10%, PAD3V5V = 1 VDD = 5.0 V 10%, PAD3V5V = 0 SIUL.PCRx.SRC = 1 VDD = 5.0 V 10%, PAD3V5V = 0 VDD = 3.3 V 10%, PAD3V5V = 1 1. VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 125 C, unless otherwise specified 68/134 Doc ID 15131 Rev 7 -- -- 100 -- -- 125 -- -- 50 -- -- 100 -- -- 125 -- -- 10 -- -- 20 -- -- 40 -- -- 12 -- -- 25 -- -- 40 -- -- 4 -- -- 6 -- -- 12 -- -- 4 -- -- 7 -- -- 12 ns CL = 100 pF 2. CL includes device and package capacitances (CPKG < 5 pF). 50 ns VDD = 3.3 V 10%, PAD3V5V = 1 SIUL.PCRx.SRC = 1 Output transition time output pin(2) CL = 100 pF FAST configuration CL = 25 pF CL = 50 pF -- ns CL = 25 pF CL = 50 pF -- SPC560B54/6x 4.6.5 Electrical characteristics I/O pad current specification The I/O pads are distributed across the I/O supply segment. Each I/O supply segment is associated to a VDD/VSS supply pair as described in Table 22. Table 23 provides I/O consumption figures. In order to ensure device reliability, the average current of the I/O on a single segment should remain below the IAVGSEG maximum value. Table 22. I/O supply segments Supply segment Package 1 2 LBGA208 3 4 5 6 Equivalent to LQFP176 segment pad distribution (1) 7 8 MCKO MDOn /MSEO LQFP176 pin7 - pin27 pin28 - pin57 pin59 - pin85 pin86 - pin123 pin124 - pin150 pin151 - pin6 -- -- LQFP144 pin20 - pin49 pin51 - pin99 pin100 - pin122 pin 123 - pin19 -- -- -- -- LQFP100 pin16 - pin35 pin37 - pin69 pin70 - pin83 pin84 - pin15 -- -- -- -- 1. LBGA208 available only as development package for Nexus2+ Table 23. Symbol I/O consumption C Value Conditions(1) Parameter Unit Min Typ Max ISWTSLW(2) CC D ISWTMED(2) CC D ISWTFST(2) CC D Dynamic I/O current for CL = 25 pF SLOW configuration Dynamic I/O current for CL = 25 pF MEDIUM configuration Dynamic I/O current for CL = 25 pF FAST configuration Doc ID 15131 Rev 7 VDD = 5.0 V 10%, PAD3V5V = 0 -- -- 20 mA VDD = 3.3 V 10%, PAD3V5V = 1 -- -- 16 VDD = 5.0 V 10%, PAD3V5V = 0 -- -- 29 mA VDD = 3.3 V 10%, PAD3V5V = 1 -- -- 17 VDD = 5.0 V 10%, PAD3V5V = 0 -- -- 110 mA VDD = 3.3 V 10%, PAD3V5V = 1 -- -- 50 69/134 Electrical characteristics Table 23. Symbol SPC560B54/6x I/O consumption (continued) C Parameter Value Conditions(1) Unit Min Typ Max CL = 25 pF, 2 MHz -- -- 2.3 -- -- 3.2 CL = 100 pF, 2 MHz -- -- 6.6 CL = 25 pF, 2 MHz -- -- 1.6 -- -- 2.3 -- -- 4.7 -- -- 6.6 -- -- 13.4 CL = 100 pF, 13 MHz -- -- 18.3 CL = 25 pF, 13 MHz -- -- 5 -- -- 8.5 -- -- 11 -- -- 22 -- -- 33 CL = 100 pF, 40 MHz -- -- 56 CL = 25 pF, 40 MHz -- -- 14 -- -- 20 -- -- 35 -- -- 70 -- -- 65 CL = 25 pF, 4 MHz IRMSSLW Root mean square I/O CC D current for SLOW configuration CL = 25 pF, 4 MHz VDD = 5.0 V 10%, PAD3V5V = 0 mA VDD = 3.3 V 10%, PAD3V5V = 1 CL = 100 pF, 2 MHz CL = 25 pF, 13 MHz CL = 25 pF, 40 MHz IRMSMED Root mean square I/O CC D current for MEDIUM configuration CL = 25 pF, 40 MHz VDD = 5.0 V 10%, PAD3V5V = 0 mA VDD = 3.3 V 10%, PAD3V5V = 1 CL = 100 pF, 13 MHz CL = 25 pF, 40 MHz CL = 25 pF, 64 MHz IRMSFST Root mean square I/O CC D current for FAST configuration CL = 25 pF, 64 MHz VDD = 5.0 V 10%, PAD3V5V = 0 mA VDD = 3.3 V 10%, PAD3V5V = 1 CL = 100 pF, 40 MHz IAVGSEG Sum of all the static I/O VDD = 5.0 V 10%, PAD3V5V = 0 SR D current within a supply VDD = 3.3 V 10%, PAD3V5V = 1 segment mA 1. VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to125 C, unless otherwise specified 2. Stated maximum values represent peak consumption that lasts only a few ns during I/O transition. Table 24 provides the weight of concurrent switching I/Os. Due to the dynamic current limitations, the sum of the weight of concurrent switching I/Os on a single segment must not exceed 100% to ensure device functionality. 70/134 Doc ID 15131 Rev 7 SPC560B54/6x Electrical characteristics I/O weight(1) Table 24. LQFP176 LQFP144/100 Supply segment Pad LQFP LQFP LQFP 176 144 4 Weight 5 V Weight 3.3 V Weight 5 V Weight 3.3 V SRC(2)=0 SRC=1 SRC=0 SRC=1 SRC=0 SRC=1 SRC=0 SRC=1 PB[3] 5% -- 6% -- 13% -- 15% -- PC[9] 4% -- 5% -- 13% -- 15% -- PC[14] 4% -- 4% -- 13% -- 15% -- PC[15] 3% 4% 4% 4% 12% 18% 15% 16% 100 4 6 -- -- PJ[4] 3% 4% 3% 3% -- -- -- -- -- -- PH[15] 2% 3% 3% 3% -- -- -- -- -- -- PH[13] 3% 4% 3% 4% -- -- -- -- -- -- PH[14] 3% 4% 4% 4% -- -- -- -- -- -- PI[6] 4% -- 4% -- -- -- -- -- -- -- PI[7] 4% -- 4% -- -- -- -- -- -- PG[5] 4% -- 5% -- 10% -- 12% -- -- PG[4] 4% 6% 5% 5% 9% 13% 11% 12% -- PG[3] 4% -- 5% -- 9% -- 11% -- -- PG[2] 4% 6% 5% 5% 9% 12% 10% 11% PA[2] 4% -- 5% -- 8% -- 10% -- PE[0] 4% -- 5% -- 8% -- 9% -- PA[1] 4% -- 5% -- 8% -- 9% -- PE[1] 4% 6% 5% 6% 7% 10% 9% 9% PE[8] 4% 6% 5% 6% 7% 10% 8% 9% PE[9] 4% -- 5% -- 6% -- 8% -- PE[10] 4% -- 5% -- 6% -- 7% -- PA[0] 4% 6% 5% 5% 6% 8% 7% 7% PE[11] 4% -- 5% -- 5% -- 6% -- 1 4 4 Doc ID 15131 Rev 7 71/134 Electrical characteristics SPC560B54/6x I/O weight(1) (continued) Table 24. LQFP176 LQFP144/100 Supply segment Pad LQFP LQFP LQFP 176 144 100 Weight 5 V Weight 3.3 V Weight 5 V Weight 3.3 V SRC(2)=0 SRC=1 SRC=0 SRC=1 SRC=0 SRC=1 SRC=0 SRC=1 -- PG[9] 9% -- 10% -- 9% -- 10% -- -- PG[8] 9% -- 11% -- 9% -- 11% -- PC[11] 9% -- 11% -- 9% -- 11% -- PC[10] 9% 13% 11% 12% 9% 13% 11% 12% -- PG[7] 9% -- 11% -- 9% -- 11% -- -- PG[6] 10% 14% 11% 12% 10% 14% 11% 12% PB[0] 10% 14% 12% 12% 10% 14% 12% 12% PB[1] 10% -- 12% -- 10% -- 12% -- -- PF[9] 10% -- 12% -- 10% -- 12% -- -- PF[8] 10% 14% 12% 13% 10% 14% 12% 13% -- PF[12] 10% 15% 12% 13% 10% 15% 12% 13% PC[6] 10% -- 12% -- 10% -- 12% -- PC[7] 10% -- 12% -- 10% -- 12% -- -- PF[10] 10% 14% 11% 12% 10% 14% 11% 12% -- PF[11] 9% -- 11% -- 9% -- 11% -- 1 PA[15] 8% 12% 10% 10% 8% 12% 10% 10% -- PF[13] 8% -- 10% -- 8% -- 10% -- PA[14] 8% 11% 9% 10% 8% 11% 9% 10% PA[4] 7% -- 9% -- 7% -- 9% -- PA[13] 7% 10% 8% 9% 7% 10% 8% 9% PA[12] 7% -- 8% -- 7% -- 8% -- 1 1 2 1 1 1 72/134 Doc ID 15131 Rev 7 SPC560B54/6x Electrical characteristics I/O weight(1) (continued) Table 24. LQFP176 LQFP144/100 Supply segment Pad LQFP LQFP LQFP 176 Weight 3.3 V Weight 5 V Weight 3.3 V SRC(2)=0 SRC=1 SRC=0 SRC=1 SRC=0 SRC=1 SRC=0 SRC=1 PB[9] 1% -- 1% -- 1% -- 1% -- PB[8] 1% -- 1% -- 1% -- 1% -- PB[10] 5% -- 6% -- 6% -- 7% -- -- PF[0] 5% -- 6% -- 6% -- 8% -- -- PF[1] 5% -- 6% -- 7% -- 8% -- -- PF[2] 6% -- 7% -- 7% -- 9% -- -- PF[3] 6% -- 7% -- 8% -- 9% -- -- PF[4] 6% -- 7% -- 8% -- 10% -- -- PF[5] 6% -- 7% -- 9% -- 10% -- -- PF[6] 6% -- 7% -- 9% -- 11% -- -- PF[7] 6% -- 7% -- 9% -- 11% -- -- -- PJ[3] 6% -- 7% -- -- -- -- -- -- -- PJ[2] 6% -- 7% -- -- -- -- -- -- -- PJ[1] 6% -- 7% -- -- -- -- -- -- -- PJ[0] 6% -- 7% -- -- -- -- -- -- -- PI[15] 6% -- 7% -- -- -- -- -- -- -- PI[14] 6% -- 7% -- -- -- -- -- PD[0] 1% -- 1% -- 1% -- 1% -- PD[1] 1% -- 1% -- 1% -- 1% -- PD[2] 1% -- 1% -- 1% -- 1% -- PD[3] 1% -- 1% -- 1% -- 1% -- PD[4] 1% -- 1% -- 1% -- 1% -- PD[5] 1% -- 1% -- 1% -- 1% -- PD[6] 1% -- 1% -- 1% -- 2% -- PD[7] 1% -- 1% -- 1% -- 2% -- 144 100 2 2 3 Weight 5 V 2 2 Doc ID 15131 Rev 7 73/134 Electrical characteristics SPC560B54/6x I/O weight(1) (continued) Table 24. LQFP176 LQFP144/100 Supply segment Pad LQFP LQFP LQFP 176 4 74/134 144 2 Weight 5 V Weight 3.3 V Weight 5 V Weight 3.3 V SRC(2)=0 SRC=1 SRC=0 SRC=1 SRC=0 SRC=1 SRC=0 SRC=1 PD[8] 1% -- 1% -- 1% -- 2% -- PB[4] 1% -- 1% -- 1% -- 2% -- PB[5] 1% -- 1% -- 1% -- 2% -- PB[6] 1% -- 1% -- 1% -- 2% -- PB[7] 1% -- 1% -- 1% -- 2% -- PD[9] 1% -- 1% -- 1% -- 2% -- PD[10] 1% -- 1% -- 1% -- 2% -- PD[11] 1% -- 1% -- 1% -- 2% -- 100 2 Doc ID 15131 Rev 7 SPC560B54/6x Electrical characteristics I/O weight(1) (continued) Table 24. LQFP176 LQFP144/100 Supply segment Pad LQFP LQFP LQFP 176 144 100 -- -- -- -- 2 2 Weight 5 V Weight 3.3 V Weight 5 V Weight 3.3 V SRC(2)=0 SRC=1 SRC=0 SRC=1 SRC=0 SRC=1 SRC=0 SRC=1 PB[11] 1% -- 1% -- -- -- -- -- PD[12] 11% -- 13% -- -- -- -- -- PB[12] 11% -- 13% -- 15% -- 17% -- PD[13] 11% -- 13% -- 14% -- 17% -- PB[13] 11% -- 13% -- 14% -- 17% -- PD[14] 11% -- 13% -- 14% -- 17% -- PB[14] 11% -- 13% -- 14% -- 16% -- PD[15] 11% -- 13% -- 13% -- 16% -- PB[15] 11% -- 13% -- 13% -- 15% -- -- -- PI[8] 10% -- 12% -- -- -- -- -- -- -- PI[9] 10% -- 12% -- -- -- -- -- -- -- PI[10] 10% -- 12% -- -- -- -- -- -- -- PI[11] 10% -- 12% -- -- -- -- -- -- -- PI[12] 10% -- 12% -- -- -- -- -- -- -- PI[13] 10% -- 11% -- -- -- -- -- 2 PA[3] 9% -- 11% -- 11% -- 13% -- -- PG[13] 9% 13% 11% 11% 10% 14% 12% 13% -- PG[12] 9% 13% 10% 11% 10% 14% 12% 12% -- PH[0] 6% 8% 7% 7% 6% 9% 7% 8% -- PH[1] 6% 8% 7% 7% 6% 8% 7% 7% -- PH[2] 5% 7% 6% 6% 5% 7% 6% 7% -- PH[3] 5% 7% 5% 6% 5% 7% 6% 6% -- PG[1] 4% -- 5% -- 4% -- 5% -- -- PG[0] 4% 5% 4% 5% 4% 5% 4% 5% 4 2 Doc ID 15131 Rev 7 75/134 Electrical characteristics SPC560B54/6x I/O weight(1) (continued) Table 24. LQFP176 LQFP144/100 Supply segment Pad LQFP LQFP LQFP 176 144 100 Weight 5 V Weight 3.3 V Weight 5 V Weight 3.3 V SRC(2)=0 SRC=1 SRC=0 SRC=1 SRC=0 SRC=1 SRC=0 SRC=1 -- PF[15] 4% -- 4% -- 4% -- 4% -- -- PF[14] 4% 6% 5% 5% 4% 6% 5% 5% -- PE[13] 4% -- 5% -- 4% -- 5% -- PA[7] 5% -- 6% -- 5% -- 6% -- PA[8] 5% -- 6% -- 5% -- 6% -- PA[9] 6% -- 7% -- 6% -- 7% -- PA[10] 6% -- 8% -- 6% -- 8% -- PA[11] 8% -- 9% -- 8% -- 9% -- PE[12] 8% -- 9% -- 8% -- 9% -- -- PG[14] 8% -- 9% -- 8% -- 9% -- -- PG[15] 8% 11% 9% 10% 8% 11% 9% 10% -- PE[14] 8% -- 9% -- 8% -- 9% -- -- PE[15] 8% 11% 9% 10% 8% 11% 9% 10% -- PG[10] 8% -- 9% -- 8% -- 9% -- -- PG[11] 7% 11% 9% 9% 7% 11% 9% 9% -- -- PH[11] 7% 10% 9% 9% -- -- -- -- -- -- PH[12] 7% 10% 8% 9% -- -- -- -- -- -- PI[5] 7% -- 8% -- -- -- -- -- -- -- PI[4] 7% -- 8% -- -- -- -- -- PC[3] 6% -- 8% -- 6% -- 8% -- PC[2] 6% 8% 7% 7% 6% 8% 7% 7% PA[5] 6% 8% 7% 7% 6% 8% 7% 7% PA[6] 5% -- 6% -- 5% -- 6% -- PH[10] 5% 7% 6% 6% 5% 7% 6% 6% PC[1] 5% 19% 5% 13% 5% 19% 5% 13% 3 3 5 3 76/134 3 Doc ID 15131 Rev 7 SPC560B54/6x Electrical characteristics I/O weight(1) (continued) Table 24. LQFP176 LQFP144/100 Supply segment Pad LQFP LQFP LQFP 176 144 Weight 5 V Weight 3.3 V Weight 5 V Weight 3.3 V SRC(2)=0 SRC=1 SRC=0 SRC=1 SRC=0 SRC=1 SRC=0 SRC=1 PC[0] 6% 9% 7% 8% 7% 10% 8% 8% PH[9] 7% -- 8% -- 7% -- 9% -- PE[2] 7% 10% 8% 9% 8% 11% 9% 10% PE[3] 7% 10% 9% 9% 8% 12% 10% 10% PC[5] 7% 11% 9% 9% 8% 12% 10% 11% PC[4] 8% 11% 9% 10% 9% 13% 10% 11% PE[4] 8% 11% 9% 10% 9% 13% 11% 12% PE[5] 8% 11% 10% 10% 9% 14% 11% 12% -- PH[4] 8% 12% 10% 10% 10% 14% 12% 12% -- PH[5] 8% -- 10% -- 10% -- 12% -- -- PH[6] 8% 12% 10% 11% 10% 15% 12% 13% -- PH[7] 9% 12% 10% 11% 11% 15% 13% 13% -- PH[8] 9% 12% 10% 11% 11% 16% 13% 14% PE[6] 9% 12% 10% 11% 11% 16% 13% 14% PE[7] 9% 12% 10% 11% 11% 16% 14% 14% 100 4 4 6 4 -- -- PI[3] 9% -- 10% -- -- -- -- -- -- -- PI[2] 9% -- 10% -- -- -- -- -- -- -- PI[1] 9% -- 10% -- -- -- -- -- -- -- PI[0] 9% -- 10% -- -- -- -- -- PC[12] 8% 12% 10% 11% 12% 18% 15% 16% PC[13] 8% -- 10% -- 13% -- 15% -- PC[8] 8% -- 10% -- 13% -- 15% -- PB[2] 8% 11% 9% 10% 13% 18% 15% 16% 4 4 1. VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 125 C, unless otherwise specified 2. SRC: "Slew Rate Control" bit in SIU_PCRx Doc ID 15131 Rev 7 77/134 Electrical characteristics 4.7 SPC560B54/6x RESET electrical characteristics The device implements a dedicated bidirectional RESET pin. Figure 7. Start-up reset requirements VDD VDDMIN RESET VIH VIL device reset forced by RESET Figure 8. device start-up phase Noise filtering on reset signal VRESET hw_rst VDD `1' VIH VIL `0' filtered by hysteresis filtered by lowpass filter WFRST filtered by lowpass filter unknown reset state WFRST WNFRST 78/134 Doc ID 15131 Rev 7 device under hardware reset SPC560B54/6x Table 25. Electrical characteristics Reset electrical characteristics Symbol C Parameter VIH SR Input High Level P CMOS (Schmitt Trigger) VIL SR P VHYS CC Input hysteresis C CMOS (Schmitt Trigger) VOL Ttr CC CC Output transition time D output pin(3) MEDIUM configuration Unit Min Typ Max -- 0.65VDD -- VDD + 0.4 V -- 0.4 -- 0.35VDD V -- 0.1VDD -- -- V Push Pull, IOL = 2 mA, VDD = 5.0 V 10%, PAD3V5V = 0 (recommended) -- -- 0.1VDD Push Pull, IOL = 1 mA, VDD = 5.0 V 10%, PAD3V5V = 1(2) -- -- 0.1VDD Push Pull, IOL = 1 mA, VDD = 3.3 V 10%, PAD3V5V = 1 (recommended) -- -- 0.5 CL = 25 pF, VDD = 5.0 V 10%, PAD3V5V = 0 -- -- 10 CL = 50 pF, VDD = 5.0 V 10%, PAD3V5V = 0 -- -- 20 CL = 100 pF, VDD = 5.0 V 10%, PAD3V5V = 0 -- -- 40 CL = 25 pF, VDD = 3.3 V 10%, PAD3V5V = 1 -- -- 12 CL = 50 pF, VDD = 3.3 V 10%, PAD3V5V = 1 -- -- 25 CL = 100 pF, VDD = 3.3 V 10%, PAD3V5V = 1 -- -- 40 Input low Level CMOS (Schmitt Trigger) P Output low level Value Conditions(1) V ns SR P RESET input filtered pulse -- -- -- 40 ns WNFRST SR P RESET input not filtered pulse -- 1000 -- -- ns P VDD = 3.3 V 10%, PAD3V5V = 1 10 -- 150 D Weak pull-up current absolute value P VDD = 5.0 V 10%, PAD3V5V = 0 10 -- 150 VDD = 5.0 V 10%, PAD3V5V = 1(4) 10 -- 250 WFRST |IWPU| CC A 1. VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 125 C, unless otherwise specified 2. This is a transient configuration during power-up, up to the end of reset PHASE2 (refer to RGM module section of the device reference manual). 3. CL includes device and package capacitance (CPKG < 5 pF). Doc ID 15131 Rev 7 79/134 Electrical characteristics SPC560B54/6x 4. The configuration PAD3V5 = 1 when VDD = 5 V is only transient configuration during power-up. All pads but RESET and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state. 4.8 Power management electrical characteristics 4.8.1 Voltage regulator electrical characteristics The device implements an internal voltage regulator to generate the low voltage core supply VDD_LV from the high voltage ballast supply VDD_BV. The regulator itself is supplied by the common I/O supply VDD. The following supplies are involved: 80/134 HV: High voltage external power supply for voltage regulator module. This must be provided externally through VDD power pin. BV: High voltage external power supply for internal ballast module. This must be provided externally through VDD_BV power pin. Voltage values should be aligned with VDD. LV: Low voltage internal power supply for core, FMPLL and Flash digital logic. This is generated by the internal voltage regulator but provided outside to connect stability capacitor. It is further split into four main domains to ensure noise isolation between critical LV modules within the device: - LV_COR: Low voltage supply for the core. It is also used to provide supply for FMPLL through double bonding. - LV_CFLA: Low voltage supply for code flash module. It is supplied with dedicated ballast and shorted to LV_COR through double bonding. - LV_DFLA: Low voltage supply for data flash module. It is supplied with dedicated ballast and shorted to LV_COR through double bonding. - LV_PLL: Low voltage supply for FMPLL. It is shorted to LV_COR through double bonding. Doc ID 15131 Rev 7 SPC560B54/6x Figure 9. Electrical characteristics Voltage regulator capacitance connection CREG2 (LV_COR/LV_CFLA) VDD VSS_LV VDD_BV VDD_LVn Voltage Regulator I VSS_LVn VDD_BV CREG1 (LV_COR/LV_DFLA) CDEC1 (Ballast decoupling) VREF VDD_LV VDD_LV DEVICE VSS_LV VSS_LV DEVICE VSS VDD_LV CREG3 (LV_COR/LV_PLL) VDD CDEC2 (supply/IO decoupling) The internal voltage regulator requires external capacitance (CREGn) to be connected to the device in order to provide a stable low voltage digital supply to the device. Capacitances should be placed on the board as near as possible to the associated pins. Care should also be taken to limit the serial inductance of the board to less than 5 nH. Each decoupling capacitor must be placed between each of the three VDD_LV/VSS_LV supply pairs to ensure stable voltage (see Section 4.4: Recommended operating conditions). Table 26. Symbol Voltage regulator electrical characteristics C CREGn SR -- Internal voltage regulator external capacitance RREG SR -- Stability capacitor equivalent serial resistance CDEC1 CDEC2 SR -- Decoupling SR -- Value Conditions(1) Parameter capacitance(2) ballast Decoupling capacitance regulator supply -- Range: 10 kHz to 20 MHz Unit Min Typ Max 200 -- 500 nF -- -- 0.2 W VDD_BV/VSS_LV pair: 100(3) VDD_BV = 4.5 V to 5.5 V VDD_BV/VSS_LV pair: VDD_BV = 3 V to 3.6 V 400 VDD/VSS pair 10 Doc ID 15131 Rev 7 -- 470(4) nF -- 100 -- nF 81/134 Electrical characteristics Table 26. SPC560B54/6x Voltage regulator electrical characteristics (continued) Symbol C T VMREG CC Main regulator output voltage P SR -- Main regulator current provided to VDD_LV domain IMREGINT CC D Main regulator module current consumption VLPREG CC P Low-power regulator output voltage ILPREG SR -- ILPREGINT CC -- 1.32 -- 1.16 1.28 -- -- -- 150 IMREG = 200 mA -- -- 2 IMREG = 0 mA -- -- 1 After trimming 1.16 1.28 -- V -- -- 15 mA -- -- 600 -- -- SR -- Ultra low power regulator current provided to VDD_LV domain Ultra low power regulator module current consumption V mA mA A -- 5 -- 1.16 1.28 -- V -- -- 5 mA IULPREG = 5 mA; TA = 55 C -- -- 100 IULPREG = 0 mA; TA = 55 C -- 2 -- -- TA = 55 C IULPREG CC D -- Before exiting from reset LPREG Ultra low power regulator output voltage IDD_BV Max ILPREG = 15 mA; T Low-power regulator module current A = 55 C consumption I = 0 mA; CC P IULPREGINT CC D Typ Low-power regulator current provided to VDD_LV domain VULPREG Unit Min After trimming IMREG D Value Conditions(1) Parameter After trimming -- In-rush average current on VDD_BV during power-up(5) -- A -- 300 (6) mA 1. VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 125 C, unless otherwise specified 2. This capacitance value is driven by the constraints of the external voltage regulator supplying the VDD_BV voltage. A typical value is in the range of 470 nF. 3. This value is acceptable to guarantee operation from 4.5 V to 5.5 V 4. External regulator and capacitance circuitry must be capable of providing IDD_BV while maintaining supply VDD_BV in operating range. 5. In-rush average current is seen only for short time during power-up and on standby exit (maximum 20 s, depending on external capacitances to be loaded). 6. The duration of the in-rush current depends on the capacitance placed on LV pins. BV decoupling capacitors must be sized accordingly. Refer to IMREG value for minimum amount of current to be provided in cc. 82/134 Doc ID 15131 Rev 7 SPC560B54/6x 4.8.2 Electrical characteristics Low voltage detector electrical characteristics The device implements a power-on reset (POR) module to ensure correct power-up initialization, as well as five low voltage detectors (LVDs) to monitor the VDD and the VDD_LV voltage while device is supplied: Note: POR monitors VDD during the power-up phase to ensure device is maintained in a safe reset state (refer to RGM Destructive Event Status (RGM_DES) Register flag F_POR in device reference manual) LVDHV3 monitors VDD to ensure device reset below minimum functional supply (refer to RGM Destructive Event Status (RGM_DES) Register flag F_LVD27 in device reference manual) LVDHV3B monitors VDD_BV to ensure device reset below minimum functional supply (refer to RGM Destructive Event Status (RGM_DES) Register flag F_LVD27_VREG in device reference manual) LVDHV5 monitors VDD when application uses device in the 5.0 V 10% range (refer to RGM Functional Event Status (RGM_FES) Register flag F_LVD45 in device reference manual) LVDLVCOR monitors power domain No. 1 (refer to RGM Destructive Event Status (RGM_DES) Register flag F_LVD12_PD1 in device reference manual) LVDLVBKP monitors power domain No. 0 (refer to RGM Destructive Event Status (RGM_DES) Register flag F_LVD12_PD0 in device reference manual) When enabled, power domain No. 2 is monitored through LVDLVBKP. Figure 10. Low voltage detector vs reset VDD VLVDHVxH VLVDHVxL RESET Doc ID 15131 Rev 7 83/134 Electrical characteristics Table 27. SPC560B54/6x Low voltage detector electrical characteristics Symbol C Value Conditions(1) Parameter Unit Min Typ Max VPORUP SR P Supply for functional POR module 1.0 -- 5.5 VPORH CC P Power-on reset threshold 1.5 -- 2.6 VLVDHV3H CC T LVDHV3 low voltage detector high threshold -- -- 2.95 VLVDHV3L CC P LVDHV3 low voltage detector low threshold 2.7 -- 2.9 -- -- 2.95 2.7 -- 2.9 VLVDHV3BH CC P LVDHV3B low voltage detector high threshold VLVDHV3BL CC P LVDHV3B low voltage detector low threshold VLVDHV5H CC T LVDHV5 low voltage detector high threshold -- -- 4.5 VLVDHV5L CC P LVDHV5 low voltage detector low threshold 3.8 -- 4.4 VLVDLVCORL CC P LVDLVCOR low voltage detector low threshold 1.08 -- 1.16 CC P LVDLVBKP low voltage detector low threshold 1.08 -- 1.16 VLVDLVBKPL TA = 25 C, after trimming V 1. VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 125 C, unless otherwise specified 4.9 Power consumption Table 28 provides DC electrical characteristics for significant application modes. These values are indicative values; actual consumption depends on the application. Table 28. Power consumption on VDD_BV and VDD_HV Symbol C Value Conditions(1) Parameter Unit Min IDDMAX(2) CC D IDDRUN (4) RUN mode maximum average current (3) 12 -- T fCPU = 16 MHz -- 27 -- fCPU = 32 MHz -- 43 -- fCPU = 48 MHz -- 56 100 fCPU = 64 MHz -- 70 125 TA = 25 C -- 10 18 TA = 125 C -- 17 28 TA = 25 C -- 350 TA = 55 C -- 750 -- TA = 85 C -- 2 7 D TA = 105 C -- 4 10 P TA = 125 C -- 7 14 HALT mode current(6) CC P Slow internal RC oscillator (128 kHz) running P D 84/134 140 -- RUN mode typical average CC T current(5) P CC 115 fCPU = 8 MHz C IDDSTOP -- T P IDDHALT -- Typ Max D STOP mode current(7) Slow internal RC oscillator (128 kHz) running Doc ID 15131 Rev 7 mA mA mA 900 (8) A mA SPC560B54/6x Table 28. Symbol Electrical characteristics Power consumption on VDD_BV and VDD_HV (continued) C Value Conditions(1) Parameter Unit Min P Typ Max TA = 25 C -- 30 100 TA = 55 C -- 75 -- TA = 85 C -- 180 700 TA = 105 C -- 315 1000 P TA = 125 C -- 560 1700 T TA = 25 C -- 20 60 TA = 55 C -- 45 -- TA = 85 C -- 100 350 TA = 105 C -- 165 500 TA = 125 C -- 280 900 D IDDSTDBY2 CC D STANDBY2 mode current (9) D D IDDSTDBY1 CC D STANDBY1 mode D current(10) Slow internal RC oscillator (128 kHz) running Slow internal RC oscillator (128 kHz) running D A A 1. VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 125 C, unless otherwise specified 2. Running consumption does not include I/Os toggling which is highly dependent on the application. The given value is thought to be a worst case value with all peripherals running, and code fetched from code flash while modify operation ongoing on data flash. Notice that this value can be significantly reduced by application: switch off not used peripherals (default), reduce peripheral frequency through internal prescaler, fetch from RAM most used functions, use low power mode when possible. 3. Higher current may be sunk by device during power-up and standby exit. Please refer to in-rush average current in Table 26. 4. RUN current measured with typical application with accesses on both Flash and RAM. 5. Only for the "P" classification: Data and Code Flash in Normal Power. Code fetched from RAM: Serial IPs CAN and LIN in loop back mode, DSPI as Master, PLL as system clock (4 x Multiplier) peripherals on (eMIOS/CTU/ADC) and running at max frequency, periodic SW/WDG timer reset enabled. 6. Data Flash Power Down. Code Flash in Low Power. SIRC 128 kHz and FIRC 16 MHz on. 10 MHz XTAL clock. FlexCAN: instances: 0, 1, 2 ON (clocked but not reception or transmission), instances: 4, 5, 6 clocks gated. LINFlex: instances: 0, 1, 2 ON (clocked but not reception or transmission), instance: 3 to 9 clocks gated. eMIOS: instance: 0 ON (16 channels on PA[0]-PA[11] and PC[12]-PC[15]) with PWM 20 kHz, instance: 1 clock gated. DSPI: instance: 0 (clocked but no communication), instance: 1 to 5 clocks gated. RTC/API ON. PIT ON. STM ON. ADC1 OFF. ADC0 ON but no conversion except two analog watchdogs. 7. Only for the "P" classification: No clock, FIRC 16 MHz off, SIRC 128 kHz on, PLL off, HPvreg off, ULPVreg/LPVreg on. All possible peripherals off and clock gated. Flash in power down mode. 8. When going from RUN to STOP mode and the core consumption is > 6 mA, it is normal operation for the main regulator module to be kept on by the on-chip current monitoring circuit. This is most likely to occur with junction temperatures exceeding 125 C and under these circumstances, it is possible for the current to initially exceed the maximum STOP specification by up to 2 mA. After entering stop, the application junction temperature will reduce to the ambient level and the main regulator will be automatically switched off when the load current is below 6 mA. 9. Only for the "P" classification: ULPreg on, HP/LPVreg off, 32 KB RAM on, device configured for minimum consumption, all possible modules switched off. 10. ULPreg on, HP/LPVreg off, 8 KB RAM on, device configured for minimum consumption, all possible modules switched off. Doc ID 15131 Rev 7 85/134 Electrical characteristics SPC560B54/6x 4.10 Flash memory electrical characteristics 4.10.1 Program/erase characteristics Table 29 shows the program and erase characteristics. Table 29. Program and erase specifications Value Symbol C Parameter Conditions Min Code Flash tdwprogram Double word (64 bits) program time(4) t16Kpperase 16 KB block preprogram and erase time Typ (1) Initial Unit Max max (3) (2) 18 -- Data Flash 50 500 s 500 5000 ms 600 5000 ms 1300 7500 ms s 22 Code Flash 200 -- Data Flash 300 C Code Flash t32Kpperase 300 32 KB block preprogram and erase time CC -- Data Flash 400 Code Flash t128Kpperase 600 128 KB block preprogram and erase time -- Data Flash tesus D Erase Suspend Latency tESRT C Erase Suspend Request Rate 800 -- -- -- 30 30 Code Flash 20 -- -- -- Data Flash 10 -- -- -- ms 1. Typical program and erase times assume nominal supply values and operation at 25 C. All times are subject to change pending device characterization. 2. Initial factory condition: < 100 program/erase cycles, 25 C, typical supply voltage. 3. The maximum program and erase times occur after the specified number of program/erase cycles. These maximum values are characterized but not guaranteed. 4. Actual hardware programming times. This does not include software overhead. Table 30. Flash module life Value Symbol C Parameter Conditions Unit Min Typ Max P/E Number of program/erase cycles per block for 16 KB CC C blocks over the operating temperature range (TJ) -- 100000 -- -- cycles P/E Number of program/erase cycles per block for 32 KB CC C blocks over the operating temperature range (TJ) -- 10000 100000 -- cycles 86/134 Doc ID 15131 Rev 7 SPC560B54/6x Table 30. Electrical characteristics Flash module life Value Symbol C Parameter Conditions Typ Max 1000 100000 -- cycles Blocks with 0-1000 P/E cycles 20 -- -- years Blocks with 1001-10000 P/E cycles 10 -- -- years Blocks with 10001-100000 P/E cycles 5 -- -- years Number of program/erase cycles per block for 128 KB CC C blocks over the operating temperature range (TJ) P/E Minimum data retention at CC C 85 C average ambient temperature(1) Retention Unit Min -- 1. Ambient temperature averaged over duration of application, not to exceed recommended product operating temperature range. ECC circuitry provides correction of single bit faults and is used to improve further automotive reliability results. Some units will experience single bit corrections throughout the life of the product with no impact to product reliability. Table 31. Flash read access timing Symbol C Conditions(1) Parameter P fREAD CC C Maximum frequency for Flash reading C Max 2 wait states 64 1 wait state 40 0 wait states 20 Unit MHz 1. VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 125 C, unless otherwise specified 4.10.2 Flash power supply DC characteristics Table 32 shows the power supply DC characteristics on external supply. Table 32. Flash power supply DC electrical characteristics Symbol Value Conditions(1) Parameter Unit Min ICFREAD IDFREAD CC Sum of the current consumption on Flash module read VDD_HV and VDD_BV on read access fCPU = 64 MHz ICFMOD IDFMOD Sum of the current consumption on CC VDD_HV and VDD_BV on matrix modification (program/erase) Program/Erase on-going while reading Flash registers fCPU = 64 MHz Doc ID 15131 Rev 7 Typ Max Code Flash -- -- 33 Data Flash -- -- 33 Code Flash -- -- 52 Data Flash -- -- 33 mA mA 87/134 Electrical characteristics Table 32. SPC560B54/6x Flash power supply DC electrical characteristics (continued) Symbol Value Conditions(1) Parameter Unit Min ICFLPW IDFLPW ICFPWD IDFPWD Sum of the current consumption on CC VDD_HV and VDD_BV during Flash low power mode -- Sum of the current consumption on CC VDD_HV and VDD_BV during Flash power down mode -- Typ Max Code Flash -- -- 1.1 mA Data Flash -- -- 900 A Code Flash -- -- 150 Data Flash -- -- 150 A 1. VDD = 3.3 V 10% / 5.0 V 10%, TA = -40 to 125 C, unless otherwise specified 4.10.3 Start-up/Switch-off timings Table 33. Start-up time/Switch-off time Symbol C Parameter Value Conditions(1) Unit Min Typ Max tFLARSTEXIT CC T Delay for Flash module to exit reset mode -- -- -- 125 tFLALPEXIT CC T Delay for Flash module to exit low-power mode -- -- -- 0.5 tFLAPDEXIT CC T Delay for Flash module to exit power-down mode -- -- -- 30 tFLALPENTRY CC T Delay for Flash module to enter low-power mode -- -- -- 0.5 tFLAPDENTRY CC T Delay for Flash module to enter power-down mode -- -- -- 1.5 s 1. VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 125 C, unless otherwise specified 4.11 Electromagnetic compatibility (EMC) characteristics Susceptibility tests are performed on a sample basis during product characterization. 4.11.1 Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. 88/134 Doc ID 15131 Rev 7 SPC560B54/6x Electrical characteristics Therefore it is recommended that the user apply EMC software optimization and prequalification tests in relation with the EMC level requested for the application. Software recommendations The software flowchart must include the management of runaway conditions such as: - Corrupted program counter - Unexpected reset - Critical data corruption (control registers...) Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the reset pin or the oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note Software Techniques For Improving Microcontroller EMC Performance (AN1015)). 4.11.2 Electromagnetic interference (EMI) The product is monitored in terms of emission based on a typical application. This emission test conforms to the IEC61967-1 standard, which specifies the general conditions for EMI measurements. EMI radiated emission measurement(1)(2) Table 34. Value Symbol C Parameter Conditions Unit Min -- SR -- Scan range -- 0.150 fCPU SR -- Operating frequency -- -- VDD_LV SR -- LV operating voltages -- SEMI CC T Peak level VDD = 5 V, TA = 25 C, LQFP144 package Test conforming to IEC 61967-2, fOSC = 8 MHz/fCPU = 64 MHz Typ Max 1000 MHz 64 -- MHz -- 1.28 -- V No PLL frequency modulation -- -- 18 dBV 2% PLL frequency modulation -- -- 14 dBV 1. EMI testing and I/O port waveforms per IEC 61967-1, -2, -4 2. For information on conducted emission and susceptibility measurement (norm IEC 61967-4), please contact your local marketing representative. 4.11.3 Absolute maximum ratings (electrical sensitivity) Based on two different tests (ESD and LU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts(n + 1) supply pin). This test Doc ID 15131 Rev 7 89/134 Electrical characteristics SPC560B54/6x conforms to the AEC-Q100-002/-003/-011 standard. For more details, refer to the application note Electrostatic Discharge Sensitivity Measurement (AN1181). Table 35. ESD absolute maximum ratings(1)(2) Class Max value(3) TA = 25 C conforming to AEC-Q100-002 H1C 2000 Electrostatic discharge voltage (Machine Model) TA = 25 C conforming to AEC-Q100-003 M2 200 Electrostatic discharge voltage VESD(CDM) (Charged Device Model) TA = 25 C conforming to AEC-Q100-011 Symbol Ratings Conditions VESD(HBM) Electrostatic discharge voltage (Human Body Model) VESD(MM) Unit V 500 C3A 750 (corners) 1. All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. 2. A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification requirements. Complete DC parametric and functional testing shall be performed per applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. 3. Data based on characterization results, not tested in production Static latch-up (LU) Two complementary static tests are required on six parts to assess the latch-up performance: A supply overvoltage is applied to each power supply pin. A current injection is applied to each input, output and configurable I/O pin. These tests are compliant with the EIA/JESD 78 IC latch-up standard. Table 36. Latch-up results Symbol LU 4.12 Parameter Static latch-up class Conditions TA = 125 C conforming to JESD 78 Class II level A Fast external crystal oscillator (4 to 16 MHz) electrical characteristics The device provides an oscillator/resonator driver. Figure 11 describes a simple model of the internal oscillator driver and provides an example of a connection for an oscillator or a resonator. Table 37 provides the parameter description of 4 MHz to 16 MHz crystals used for the design simulations. 90/134 Doc ID 15131 Rev 7 SPC560B54/6x Electrical characteristics Figure 11. Crystal oscillator and resonator connection scheme EXTAL C1 Crystal EXTAL XTAL C2 DEVICE VDD I R EXTAL XTAL Resonator DEVICE XTAL DEVICE Notes: 1. XTAL/EXTAL must not be directly used to drive external circuits 2. A series resistor may be required, according to crystal oscillator supplier recommendations. Table 37. Crystal description Crystal motional capacitance (Cm) fF Crystal motional inductance (Lm) mH Load on xtalin/xtalout C1 = C2 (pF)(1) Shunt capacitance between xtalout and xtalin C0(2) (pF) Nominal frequency (MHz) NDK crystal reference Crystal equivalent series resistance ESR 4 NX8045GB 300 2.68 591.0 21 2.93 300 2.46 160.7 17 3.01 150 2.93 86.6 15 2.91 12 120 3.11 56.5 15 2.93 16 120 3.90 25.3 10 3.00 8 10 NX5032GA 1. The values specified for C1 and C2 are the same as used in simulations. It should be ensured that the testing includes all the parasitics (from the board, probe, crystal, etc.) as the AC / transient behavior depends upon them. 2. The value of C0 specified here includes 2 pF additional capacitance for parasitics (to be seen with bond-pads, package, etc.). Doc ID 15131 Rev 7 91/134 Electrical characteristics SPC560B54/6x Figure 12. Fast external crystal oscillator (4 to 16 MHz) timing diagram S_MTRANS bit (ME_GS register) 1 0 VXTAL 1/fMXOSC VMXOSC 90% VMXOSCOP 10% TMXOSCSU Table 38. Symbol fFXOSC Fast external crystal oscillator (4 to 16 MHz) electrical characteristics C Parameter Value Conditions(1) Unit Min Typ Max -- 4.0 -- 16.0 CC C VDD = 3.3 V 10%, PAD3V5V = 1 OSCILLATOR_MARGIN = 0 2.2 -- 8.2 CC P VDD = 5.0 V 10%, PAD3V5V = 0 OSCILLATOR_MARGIN = 0 2.0 -- 7.4 SR -- Fast external crystal oscillator frequency Fast external crystal oscillator transconductance gmFXOSC VFXOSC valid internal clock mA/V CC C VDD = 3.3 V 10%, PAD3V5V = 1 OSCILLATOR_MARGIN = 1 2.7 -- 9.7 CC C VDD = 5.0 V 10%, PAD3V5V = 0 OSCILLATOR_MARGIN = 1 2.5 -- 9.2 fOSC = 4 MHz, OSCILLATOR_MARGIN = 0 1.3 -- -- CC T Oscillation amplitude at EXTAL MHz V fOSC = 16 MHz, OSCILLATOR_MARGIN = 1 1.3 -- -- VFXOSCOP CC C Oscillation operating point -- -- 0.95 -- V IFXOSC(2) Fast external crystal oscillator consumption -- -- 2 3 mA 92/134 CC T Doc ID 15131 Rev 7 SPC560B54/6x Table 38. Symbol tFXOSCSU Electrical characteristics Fast external crystal oscillator (4 to 16 MHz) electrical characteristics (continued) C CC T Parameter Fast external crystal oscillator start-up time Value Conditions(1) Unit fOSC = 4 MHz, OSCILLATOR_MARGIN = 0 Min Typ Max -- -- 6 ms fOSC = 16 MHz, OSCILLATOR_MARGIN = 1 -- -- 1.8 VIH SR P Input high level CMOS (Schmitt Trigger) Oscillator bypass mode 0.65VDD -- VDD + 0.4 V VIL SR P Input low level CMOS (Schmitt Trigger) Oscillator bypass mode 0.4 -- 0.35VDD V 1. VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 125 C, unless otherwise specified. 2. Stated values take into account only analog module consumption but not the digital contributor (clock tree and enabled peripherals). 4.13 Slow external crystal oscillator (32 kHz) electrical characteristics The device provides a low power oscillator/resonator driver. Figure 13. Crystal oscillator and resonator connection scheme OSC32K_EXTAL OSC32K_EXTAL Resonator Crystal C1 RP OSC32K_XTAL DEVICE OSC32K_XTAL C2 DEVICE Note: OSC32_XTAL/OSC32_EXTAL must not be directly used to drive external circuits Doc ID 15131 Rev 7 93/134 Electrical characteristics SPC560B54/6x Figure 14. lEquivalent circuit of a quartz crystal C0 C1 Crystal Cm C2 Rm Lm C1 Table 39. C2 Crystal motional characteristics(1) Value Symbol Parameter Conditions Unit Min Typ Max Lm Motional inductance -- -- 11.796 -- KH Cm Motional capacitance -- -- 2 -- fF Load capacitance at OSC32K_XTAL and OSC32K_EXTAL with respect to ground(2) -- 18 -- 28 pF AC coupled at C0 = 2.85 pF(4) -- -- 65 AC coupled at C0 = 4.9 pF(4) -- -- 50 AC coupled at C0 = 7.0 pF(4) -- -- 35 AC coupled at C0 = 9.0 pF(4) -- -- 30 C1/C2 Rm(3) Motional resistance kW 1. The crystal used is Epson Toyocom MC306. 2. This is the recommended range of load capacitance at OSC32K_XTAL and OSC32K_EXTAL with respect to ground. It includes all the parasitics due to board traces, crystal and package. 3. Maximum ESR (Rm) of the crystal is 50 k 4. C0 Includes a parasitic capacitance of 2.0 pF between OSC32K_XTAL and OSC32K_EXTAL pins. 94/134 Doc ID 15131 Rev 7 SPC560B54/6x Electrical characteristics Figure 15. Slow external crystal oscillator (32 kHz) timing diagram OSCON bit (OSC_CTL register) 1 0 VOSC32K_XTAL 1/fLPXOSC32K VLPXOSC32K 90% 10% TLPXOSC32KSU Table 40. valid internal clock Slow external crystal oscillator (32 kHz) electrical characteristics Symbol C Value Conditions(1) Parameter Unit Min Typ Max fSXOSC SR -- Slow external crystal oscillator frequency -- 32 32.768 40 kHz VSXOSC CC T Oscillation amplitude -- -- 2.1 -- V ISXOSCBIAS CC T Oscillation bias current -- 2.5 A ISXOSC CC T Slow external crystal oscillator consumption -- -- -- 8 A tSXOSCSU CC T Slow external crystal oscillator start-up time -- -- -- 2(2) s 1. VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 125 C, unless otherwise specified. Values are specified for no neighbor GPIO pin activity. If oscillator is enabled (OSC32K_XTAL and OSC32K_EXTAL pins), neighboring pins should not toggle. 2. Start-up time has been measured with EPSON TOYOCOM MC306 crystal. Variation may be seen with other crystal. 4.14 FMPLL electrical characteristics The device provides a frequency modulated phase locked loop (FMPLL) module to generate a fast system clock from the main oscillator driver. Table 41. FMPLL electrical characteristics Symbol C Parameter fPLLIN SR -- FMPLL reference clock(2) PLLIN SR -- FMPLL reference clock duty cycle(2) Value Conditions(1) Unit Min Typ Max -- 4 -- 64 MHz -- 40 -- 60 % Doc ID 15131 Rev 7 95/134 Electrical characteristics Table 41. FMPLL electrical characteristics (continued) Symbol fPLLOUT C CC P P fVCO(3) SPC560B54/6x Value Conditions(1) Parameter Unit Min Typ Max FMPLL output clock frequency -- 16 -- 64 VCO frequency without frequency modulation -- 256 -- 512 CC MHz MHz VCO frequency with P frequency modulation -- 245.76 -- 532.48 fCPU SR -- System clock frequency -- -- -- 64(4) MHz fFREE CC P Free-running frequency -- 20 -- 150 MHz tLOCK CC P FMPLL lock time Stable oscillator (fPLLIN = 16 MHz) 40 100 s tSTJIT CC -- FMPLL short term jitter(5) fsys maximum -4 -- 4 % tLTJIT CC -- FMPLL long term jitter fPLLCLK at 64 MHz, 4000 cycles -- -- 10 ns CC C FMPLL consumption TA = 25 C -- -- 4 mA IPLL 1. VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 125 C, unless otherwise specified 2. PLLIN clock retrieved directly from FXOSC clock. Input characteristics are granted when oscillator is used in functional mode. When bypass mode is used, oscillator input clock should verify fPLLIN and PLLIN. 3. Frequency modulation is considered 4%. 4. fCPU 64 MHz can be achieved only at up to 105 C. 5. Short term jitter is measured on the clock rising edge at cycle n and n+4. 4.15 Fast internal RC oscillator (16 MHz) electrical characteristics The device provides a 16 MHz main internal RC oscillator. This is used as the default clock at the power-up of the device. Table 42. Symbol fFIRC Fast internal RC oscillator (16 MHz) electrical characteristics C CC P Fast internal RC oscillator SR -- high frequency Fast internal RC oscillator IFIRCRUN(2) CC T high frequency current in running mode IFIRCPWD 96/134 Value Conditions(1) Parameter Fast internal RC oscillator CC D high frequency current in power down mode TA = 25 C, trimmed -- Unit Min Typ Max -- 16 -- MHz 12 20 TA = 25 C, trimmed -- -- 200 A TA = 25 C -- -- 10 A Doc ID 15131 Rev 7 SPC560B54/6x Table 42. Symbol IFIRCSTOP tFIRCSU Electrical characteristics Fast internal RC oscillator (16 MHz) electrical characteristics (continued) C Fast internal RC oscillator CC T high frequency and system clock current in stop mode CC C Value Conditions(1) Parameter Fast internal RC oscillator start-up time Unit Min Typ Max sysclk = off -- 500 -- sysclk = 2 MHz -- 600 -- sysclk = 4 MHz -- 700 -- sysclk = 8 MHz -- 900 -- sysclk = 16 MHz -- 1250 -- VDD = 5.0 V 10% -- 1.1 2.0 s 1 % TA = 25 C FIRCPRE Fast internal RC oscillator CC C precision after software trimming of fFIRC TA = 25 C 1 -- FIRCTRIM CC C Fast internal RC oscillator trimming step TA = 25 C -- 1.6 FIRCVAR Fast internal RC oscillator variation over temperature CC C and supply with respect to fFIRC at TA = 25 C in highfrequency configuration 5 -- -- A % 5 % 1. VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 125 C, unless otherwise specified 2. This does not include consumption linked to clock tree toggling and peripherals consumption when RC oscillator is ON. 4.16 Slow internal RC oscillator (128 kHz) electrical characteristics The device provides a 128 kHz low power internal RC oscillator. This can be used as the reference clock for the RTC module. Table 43. Symbol fSIRC Slow internal RC oscillator (128 kHz) electrical characteristics C Value Conditions(1) Parameter CC P Slow internal RC oscillator low SR -- frequency TA = 25 C, trimmed -- Unit Min Typ Max -- 128 -- 100 -- 150 kHz ISIRC(2) CC C Slow internal RC oscillator low frequency current TA = 25 C, trimmed -- -- 5 A tSIRCSU CC P Slow internal RC oscillator start-up time TA = 25 C, VDD = 5.0 V 10% -- 8 12 s Doc ID 15131 Rev 7 97/134 Electrical characteristics Table 43. Symbol SPC560B54/6x Slow internal RC oscillator (128 kHz) electrical characteristics (continued) C Value Conditions(1) Parameter Slow internal RC oscillator precision after software trimming of fSIRC SIRCPRE CC C SIRCTRIM Slow internal RC oscillator trimming CC C step SIRCVAR Slow internal RC oscillator variation in temperature and supply with respect High frequency CC C configuration to fSIRC at TA = 55 C in high frequency configuration TA = 25 C Unit Min Typ Max 2 -- 2 % -- -- 2.7 -- 10 -- 10 1. VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 125 C, unless otherwise specified 2. This does not include consumption linked to clock tree toggling and peripherals consumption when RC oscillator is ON. 4.17 ADC electrical characteristics 4.17.1 Introduction The device provides two Successive Approximation Register (SAR) analog-to-digital converters (10-bit and 12-bit). 98/134 Doc ID 15131 Rev 7 % SPC560B54/6x Electrical characteristics Figure 16. ADC_0 characteristic and error definitions Offset Error (EO) Gain Error (EG) 1023 1022 1021 1020 1019 1 LSB ideal = VDD_ADC / 1024 1018 (2) code out 7 (1) 6 5 (1) Example of an actual transfer curve (5) (2) The ideal transfer curve 4 (3) Differential non-linearity error (DNL) (4) (4) Integral non-linearity error (INL) 3 (5) Center of a step of the actual transfer curve (3) 2 1 1 LSB (ideal) 0 1 2 3 4 5 6 7 1017 1018 1019 1020 1021 1022 1023 Vin(A) (LSBideal) Offset Error (EO) 4.17.2 Input impedance and ADC accuracy In the following analysis, the input circuit corresponding to the precise channels is considered. To preserve the accuracy of the A/D converter, it is necessary that analog input pins have low AC impedance. Placing a capacitor with good high frequency characteristics at the input pin of the device can be effective: the capacitor should be as large as possible, ideally infinite. This capacitor contributes to attenuating the noise present on the input pin; furthermore, it sources charge during the sampling phase, when the analog signal source is a high-impedance source. A real filter can typically be obtained by using a series resistance with a capacitor on the input pin (simple RC filter). The RC filtering may be limited according to the value of source impedance of the transducer or circuit supplying the analog signal to be measured. The filter Doc ID 15131 Rev 7 99/134 Electrical characteristics SPC560B54/6x at the input pins must be designed taking into account the dynamic characteristics of the input signal (bandwidth) and the equivalent input impedance of the ADC itself. In fact a current sink contributor is represented by the charge sharing effects with the sampling capacitance: CS being substantially a switched capacitance, with a frequency equal to the conversion rate of the ADC, it can be seen as a resistive path to ground. For instance, assuming a conversion rate of 1 MHz, with CS equal to 3 pF, a resistance of 330 k is obtained (REQ = 1 / (fc*CS), where fc represents the conversion rate at the considered channel). To minimize the error induced by the voltage partitioning between this resistance (sampled voltage on CS) and the sum of RS + RF + RL + RSW + RAD, the external circuit must be designed to respect the <Cross Refs>Equation 4: Equation 4: R +R +R +R V +R S F L SW AD --------------------------------------------------------------------------- 1--- LSB A R 2 EQ <Cross Refs>Equation 4 generates a constraint for external network design, in particular on resistive path. Internal switch resistances (RSW and RAD) can be neglected with respect to external resistances. Figure 17. Input equivalent circuit (precise channels) EXTERNAL CIRCUIT INTERNAL CIRCUIT SCHEME VDD Source RS VA Filter Current Limiter RF RL CF CP1 RS Source Impedance RF Filter Resistance CF Filter Capacitance RL Current Limiter Resistance RSW1 Channel Selection Switch Impedance RADSampling Switch Impedance CP Pin Capacitance (two contributions, CP1 and CP2) CS Sampling Capacitance 100/134 Doc ID 15131 Rev 7 Channel Selection Sampling RSW1 RAD CP2 CS SPC560B54/6x Electrical characteristics Figure 18. Input equivalent circuit (extended channels) EXTERNAL CIRCUIT INTERNAL CIRCUIT SCHEME VDD Source RS Filter Current Limiter RF VA RL CF CP1 Channel Selection Extended Switch Sampling RSW1 RSW2 RAD CP3 CP2 CS RS Source Impedance RF Filter Resistance CF Filter Capacitance RL Current Limiter Resistance RSW Channel Selection Switch Impedance (two contributions RSW1 and RSW2) RADSampling Switch Impedance CP Pin Capacitance (three contributions, CP1, CP2 and CP3) CS Sampling Capacitance A second aspect involving the capacitance network shall be considered. Assuming the three capacitances CF, CP1 and CP2 are initially charged at the source voltage VA (refer to the equivalent circuit reported in Figure 17): A charge sharing phenomenon is installed when the sampling phase is started (A/D switch close). Figure 19. Transient behavior during sampling phase Voltage Transient on CS VCS VA VA2 V <0.5 LSB 1 2 1 < (RSW + RAD) CS << tS 2 = RL (CS + CP1 + CP2) VA1 TS t In particular two different transient periods can be distinguished: 1. A first and quick charge transfer from the internal capacitance CP1 and CP2 to the sampling capacitance CS occurs (CS is supposed initially completely discharged): considering a worst case (since the time constant in reality would be faster) in which Doc ID 15131 Rev 7 101/134 Electrical characteristics SPC560B54/6x CP2 is reported in parallel to CP1 (call CP = CP1 + CP2), the two capacitances CP and CS are in series, and the time constant is Equation 5: 1 = R SW + R AD C C P S ---------------------CP + CS <Cross Refs>Equation 5 can again be simplified considering only CS as an additional worst condition. In reality, the transient is faster, but the A/D converter circuitry has been designed to be robust also in the very worst case: the sampling time tS is always much longer than the internal time constant: Equation 6: 1 R SW + R AD C S t s The charge of CP1 and CP2 is redistributed also on CS, determining a new value of the voltage VA1 on the capacitance according to <Cross Refs>Equation 7: Equation 7: V A1 C S + C P1 + C P2 = V A C P1 + C P2 2. A second charge transfer involves also CF (that is typically bigger than the on-chip capacitance) through the resistance RL: again considering the worst case in which CP2 and CS were in parallel to CP1 (since the time constant in reality would be faster), the time constant is: Equation 8: 2 R L C S + C P1 + C P2 In this case, the time constant depends on the external circuit: in particular imposing that the transient is completed well before the end of sampling time ts, a constraints on RL sizing is obtained: Equation 9: 10 2 = 10 R L C S + C P1 + C P2 t s Of course, RL shall be sized also according to the current limitation constraints, in combination with RS (source impedance) and RF (filter resistance). Being CF definitively bigger than CP1, CP2 and CS, then the final voltage VA2 (at the end of the charge transfer transient) will be much higher than VA1. <Cross Refs>Equation 10 must be respected (charge balance assuming now CS already charged at VA1): Equation 10: VA2 C S + C P1 + C P2 + C F = V A C F + V A1 C P1 + C P2 + C S The two transients above are not influenced by the voltage source that, due to the presence of the RFCF filter, is not able to provide the extra charge to compensate the voltage drop on CS with respect to the ideal source VA; the time constant RFCF of the filter is very high with respect to the sampling time (ts). The filter is typically designed to act as antialiasing. 102/134 Doc ID 15131 Rev 7 SPC560B54/6x Electrical characteristics Figure 20. Spectral representation of input signal Analog source bandwidth (VA) Noise tc < 2 RFCF (Conversion rate vs. filter pole) fF = f0 (Anti-aliasing filtering condition) 2 f0 < fC (Nyquist) f0 f Anti-aliasing filter (fF = RC filter pole) fF f Sampled signal spectrum (fC = Conversion rate) f0 fC f Calling f0 the bandwidth of the source signal (and as a consequence the cut-off frequency of the antialiasing filter, fF), according to the Nyquist theorem the conversion rate fC must be at least 2f0; it means that the constant time of the filter is greater than or at least equal to twice the conversion period (tc). Again the conversion period tc is longer than the sampling time ts, which is just a portion of it, even when fixed channel continuous conversion mode is selected (fastest conversion rate at a specific channel): in conclusion it is evident that the time constant of the filter RFCF is definitively much higher than the sampling time ts, so the charge level on CS cannot be modified by the analog signal source during the time in which the sampling switch is closed. The considerations above lead to impose new constraints on the external circuit, to reduce the accuracy error due to the voltage drop on CS; from the two charge balance equations above, it is simple to derive <Cross Refs>Equation 11 between the ideal and real sampled voltage on CS: Equation 11: V A2 C P1 + C P2 + C F ------------ = -------------------------------------------------------VA C P1 + C P2 + C F + C S From this formula, in the worst case (when VA is maximum, that is for instance 5 V), assuming to accept a maximum error of half a count, a constraint is evident on CF value: Equation 12: ADC_0 (10-bit) C F 2048 C S Equation 13: ADC_1 (12-bit) C F 8192 C S Doc ID 15131 Rev 7 103/134 Electrical characteristics SPC560B54/6x 4.17.3 ADC electrical characteristics Table 44. ADC input leakage current Value Symbol C Parameter Unit Min Typ Max -- 1 70 -- 1 70 3 100 TA = 40 C D TA = 25 C D ILKG CC D Conditions Input leakage current No current injection on adjacent pin TA = 85 C D TA = 105 C -- 8 200 P TA = 125 C -- 45 400 Table 45. Symbol nA ADC_0 conversion characteristics (10-bit ADC_0) C Value Conditions(1) Parameter Unit Min Typ Max VSS_ADC0 Voltage on VSS_HV_ADC0 (ADC_0 SR -- reference) pin with respect to ground (VSS)(2) -- 0.1 -- 0.1 V VDD_ADC0 Voltage on VDD_HV_ADC pin (ADC SR -- reference) with respect to ground (VSS) -- VDD 0.1 -- VDD + 0. 1 V SR -- Analog input voltage(3) -- VSS_ADC0 0.1 -- VAINx VDD_ADC 0 V + 0.1 IADC0pwd SR -- ADC_0 consumption in power down mode -- -- -- 50 A IADC0run SR -- ADC_0 consumption in running mode -- -- -- 40 mA -- 6 -- 32 + 4% MHz 45 -- 55 % -- -- -- 1.5 s fADC = 32 MHz, INPSAMP = 17 0.5 -- fADC = 6 MHz, INPSAMP = 255 -- -- 42 fADC = 32 MHz, INPCMP = 2 0.625 -- -- s -- -- 3 pF fADC0 SR -- ADC_0 analog frequency ADC0_SYS SR -- tADC0_PU tADC0_S tADC0_C CS 104/134 ADC_0 digital clock duty cycle (ipg_clk) SR -- ADC_0 power up delay (5) ADCLKSEL = 1(4) CC T Sampling time CC P Conversion time(6) CC D ADC_0 input sampling capacitance s -- Doc ID 15131 Rev 7 SPC560B54/6x Table 45. Electrical characteristics ADC_0 conversion characteristics (10-bit ADC_0) (continued) Symbol C Parameter Value Conditions(1) Unit Min Typ Max CP1 CC D ADC_0 input pin capacitance 1 -- -- -- 3 pF CP2 CC D ADC_0 input pin capacitance 2 -- -- -- 1 pF CP3 CC D ADC_0 input pin capacitance 3 -- -- -- 1 pF RSW1 CC D Internal resistance of analog source -- -- -- 3 k RSW2 CC D Internal resistance of analog source -- -- -- 2 k RAD CC D Internal resistance of analog source -- -- -- 2 k VDD = 3.3 V 10% 5 -- 5 VDD = 5.0 V 10% 5 -- 5 IINJ SR -- Input current Injection Current injection on one ADC_0 input, different from the converted one mA | INL | CC T Absolute integral nonlinearity No overload -- 0.5 1.5 LSB | DNL | CC T Absolute differential nonlinearity No overload -- 0.5 1.0 LSB | EO | CC T Absolute offset error -- -- 0.5 -- LSB | EG | CC T Absolute gain error -- -- 0.6 -- LSB 2 0.6 2 3 -- 3 Without current injection 3 1 3 With current injection 4 error(7) TUEP TUEX CC CC P Total unadjusted Without current injection for precise channels, input T only pins With current injection T Total unadjusted error(7) T for extended channel LSB LSB 4 1. VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 125 C, unless otherwise specified. 2. Analog and digital VSS must be common (to be tied together externally). 3. VAINx may exceed VSS_ADC0 and VDD_ADC0 limits, remaining on absolute maximum ratings, but the results of the conversion will be clamped respectively to 0x000 or 0x3FF. 4. Duty cycle is ensured by using system clock without prescaling. When ADCLKSEL = 0, the duty cycle is ensured by internal divider by 2. 5. During the sampling time the input capacitance CS can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within tADC0_S. After the end of the sampling time tADC0_S, changes of the analog input voltage have no effect on the conversion result. Values for the sampling clock tADC0_S depend on programming. 6. This parameter does not include the sampling time tADC0_S, but only the time for determining the digital result and the time to load the result's register with the conversion result. 7. Total Unadjusted Error: The maximum error that occurs without adjusting Offset and Gain errors. This error is a combination of Offset, Gain and Integral Linearity errors. Doc ID 15131 Rev 7 105/134 Electrical characteristics SPC560B54/6x Figure 21. ADC_1 characteristic and error definitions Gain Error (EG) Offset Error (EO) 4095 4094 4093 4092 4091 1 LSB ideal = VDD_ADC / 4096 4090 (2) code out 7 (1) 6 5 (1) Example of an actual transfer curve (5) (2) The ideal transfer curve 4 (3) Differential non-linearity error (DNL) (4) (4) Integral non-linearity error (INL) 3 (5) Center of a step of the actual transfer curve (3) 2 1 1 LSB (ideal) 0 1 2 3 4 5 6 7 4090 4091 4092 4093 4094 4095 Vin(A) (LSBideal) Offset Error (EO) Table 46. Symbol VSS_ADC1 ADC_1 conversion characteristics (12-bit ADC_1) C Voltage on VSS_HV_ADC1 (ADC_1 SR -- -- reference) pin with respect (2) to ground (VSS) Voltage on VDD_HV_ADC1 pin VDD_ADC1 SR -- (ADC_1 reference) with respect to ground (VSS) 106/134 Value Conditions(1) Parameter -- Doc ID 15131 Rev 7 Unit Min Typ Max -0.1 -- 0.1 V VDD - 0.1 -- VDD + 0.1 V SPC560B54/6x Table 46. Symbol VAINx Electrical characteristics ADC_1 conversion characteristics (12-bit ADC_1) (continued) C Value Conditions(1) Parameter Unit Min Typ Max SR -- Analog input voltage(3) -- VSS_ADC1 - 0.1 -- VDD_ADC1 + 0.1 V IADC1pwd SR -- ADC_1 consumption in power down mode -- -- -- 50 A IADC1run SR -- ADC_1 consumption in running mode -- -- -- 6 mA VDD = 3.3 V 3.33 -- 20 + 4% VDD = 5 V 3.33 -- 32 + 4% -- -- 1.5 600 -- -- fADC1 tADC1_PU tADC1_S tADC1_C SR -- ADC_1 analog frequency SR -- ADC_1 power up delay CC T CC P ADC1_SYS SR -- MHz -- s time(4) Sampling VDD = 3.3 V fADC1 = 20 MHz, INPSAMP = 12 Samplingtime(4) VDD = 5.0 V fADC1 = 32 MHz, INPSAMP = 17 Sampling time(4) VDD = 3.3 V fADC1 = 3.33 MHz, INPSAMP = 255 Sampling time(4) VDD = 5.0 V fADC1 = 3.33 MHz, INPSAMP = 255 -- -- 76.2 Conversion time(5) VDD = 3 .3 V fADC1 = 20 MHz, INPCMP = 0 2.4 -- -- s Conversion time(5) VDD = 5.0 V fADC 1 = 32 MHz, INPCMP = 0 1.5 -- -- s Conversion time(5) VDD = 3.3 V fADC 1 = 13.33 MHz, INPCMP = 0 -- -- 3.6 s Conversion time(5) VDD = 5.0 V fADC1 = 13.33 MHz, INPCMP = 0 -- -- 3.6 s ADC_1 digital clock duty cycle ADCLKSEL = 1(6) -- 55 % ns 500 -- -- -- -- 76.2 s 45 CS CC D ADC_1 input sampling capacitance -- -- -- 5 pF CP1 CC D ADC_1 input pin capacitance 1 -- -- -- 3 pF CP2 CC D ADC_1 input pin capacitance 2 -- -- -- 1 pF CP3 CC D ADC_1 input pin capacitance 3 -- -- -- 1.5 pF RSW1 CC D Internal resistance of analog source -- -- -- 1 k RSW2 CC D Internal resistance of analog source -- -- -- 2 k Doc ID 15131 Rev 7 107/134 Electrical characteristics Table 46. ADC_1 conversion characteristics (12-bit ADC_1) (continued) Symbol RAD IINJ SPC560B54/6x C CC D Internal resistance of analog source SR -- Input current Injection Value Conditions(1) Parameter Typ Max -- -- 0.3 VDD = 3.3 V 10% -5 -- 5 VDD = 5.0 V 10% -5 -- 5 -- Current injection on one ADC_1 input, different from the converted one Unit Min k mA | INLP | Absolute integral CC T nonlinearity - Precise channels No overload -- 1 3 LSB | INLX | Absolute integral CC T nonlinearity - Extended channels No overload -- 1.5 5 LSB | DNL | CC T No overload -- 0.5 1 LSB Absolute differential nonlinearity | EO | CC T Absolute offset error -- -- 2 -- LSB | EG | CC T Absolute gain error -- -- 2 -- LSB Without current injection -6 -- 6 With current injection -8 -- 8 Without current injection -10 -- 10 With current injection -12 -- 12 TUEP(7) TUEX(7) CC CC P Total unadjusted error for precise channels, input T only pins T Total unadjusted error for T extended channel LSB LSB 1. VDD = 3.3 V 10% / 5.0 V 10%, TA = -40 to 125 C, unless otherwise specified 2. Analog and digital VSS must be common (to be tied together externally). 3. VAINx may exceed VSS_ADC1 and VDD_ADC1 limits, remaining on absolute maximum ratings, but the results of the conversion will be clamped respectively to 0x000 or 0xFFF. 4. During the sampling time the input capacitance CS can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within tADC1_S. After the end of the sampling time tADC1_S, changes of the analog input voltage have no effect on the conversion result. Values for the sampling clock tADC1_S depend on programming. 5. This parameter does not include the sampling time tADC1_S, but only the time for determining the digital result and the time to load the result's register with the conversion result. 6. Duty cycle is ensured by using system clock without prescaling. When ADCLKSEL = 0, the duty cycle is ensured by internal divider by 2. 7. Total Unadjusted Error: The maximum error that occurs without adjusting Offset and Gain errors. This error is a combination of Offset, Gain and Integral Linearity errors. 108/134 Doc ID 15131 Rev 7 SPC560B54/6x Electrical characteristics 4.18 On-chip peripherals 4.18.1 Current consumption Table 47. On-chip peripherals current consumption(1) Symbol C Parameter Conditions Bitrate: 500 Kbyte/s IDD_BV(CAN) CAN (FlexCAN) CC T supply current on VDD_BV IDD_BV(eMIOS) CC T IDD_BV(SCI) IDD_BV(SPI) eMIOS supply current on VDD_BV SCI (LINFlex) CC T supply current on VDD_BV SPI (DSPI) supply CC T current on VDD_BV ADC_0/ADC_1 IDD_BV CC T supply current on (ADC_0/ADC_1) VDD_BV IDD_HV_ADC0 IDD_HV_ADC1 ADC_0 supply CC T current on VDD_HV_ADC0 ADC_1 supply CC T current on VDD_HV_ADC1 Bitrate: 125 Kbyte/s Total (static + dynamic) consumption: - FlexCAN in loop-back mode - XTAL at 8 MHz used as CAN engine clock source - Message sending period is 580 s Static consumption: - eMIOS channel OFF - Global prescaler enabled Dynamic consumption: - It does not change varying the frequency (0.003 mA) Total (static + dynamic) consumption: - LIN mode - Baudrate: 20 Kbyte/s Typical value(2) 8 * fperiph + 85 A 8 * fperiph + 27 29 * fperiph A 3 5 * fperiph + 31 Ballast static consumption (only clocked) 1 Ballast dynamic consumption (continuous communication): - Baudrate: 2 Mbit/s - Trasmission every 8 s - Frame: 16 bits 16 * fperiph Ballast static consumption (no conversion)(3) VDD = 5.5 V Ballast dynamic consumption (continuous conversion)(3) Analog static consumption (no conversion) VDD = 5.5 V Analog dynamic consumption (continuous conversion) Analog static consumption (no conversion) VDD = 5.5 V Analog dynamic consumption (continuous conversion) Doc ID 15131 Rev 7 Unit A A 41 * fperiph A 46 * fperiph 200 A 3 mA 300 * fperiph A 4 mA 109/134 Electrical characteristics Table 47. SPC560B54/6x On-chip peripherals current consumption(1) (continued) Symbol C Parameter CFlash + DFlash IDD_HV(FLASH) CC T supply current on VDD_HV IDD_HV(PLL) CC T Conditions Typical value(2) Unit VDD = 5.5 V -- 12 mA PLL supply current VDD = 5.5 V on VDD_HV -- 30 * fperiph A 1. Operating conditions: TA = 25 C, fperiph = 8 MHz to 64 MHz 2. fperiph is an absolute value. 3. During the conversion, the total current consumption is given from the sum of the static and dynamic consumption, i.e., (41 + 46) * fperiph. 110/134 Doc ID 15131 Rev 7 DSPI characteristics Table 48. DSPI characteristics(1) DSPI0/DSPI1/DSPI5/DSPI6 No. 1 Doc ID 15131 Rev 7 -- -- -- Symbol tSCK C DSPI2/DSPI4 Parameter Unit Min Typ Max Min Typ Max D Master mode (MTFE = 0) 125 -- -- 333 -- -- D Slave mode (MTFE = 0) 125 -- -- 333 -- -- SR SCK cycle time SPC560B54/6x 4.18.2 ns D Master mode (MTFE = 1) 83 -- -- 125 -- -- D Slave mode (MTFE = 1) 83 -- -- 125 -- -- fDSPI SR D DSPI digital controller frequency -- -- fCPU -- -- fCPU MHz tCSC Internal delay between pad associated to SCK and pad CC D Master mode associated to CSn in master mode for CSn1->0 -- -- 130(2) -- -- 15(3) ns tASC Internal delay between pad associated to SCK and pad CC D Master mode associated to CSn in master mode for CSn1->1 -- -- 130(3) -- -- 130(3) ns tCSCext(4) SR D CS to SCK delay Slave mode 32 -- -- 32 -- -- ns 3 tASCext(5) SR D After SCK delay Slave mode 1/fDSPI + 5 -- -- 1/fDSPI + 5 -- -- ns CC D Master mode -- -- tSCK/2 -- tSDC tSCK/2 -- 4 SR D Slave mode tSCK/2 -- -- tSCK/2 -- -- SCK duty cycle ns 111/134 5 tA SR D Slave access time Slave mode -- -- 1/fDSPI + 70 -- -- 1/fDSPI + 130 ns 6 tDI SR D Slave SOUT disable time Slave mode 7 -- -- 7 -- -- ns Master mode 43 -- -- 145 -- -- 9 tSUI SR D Data setup time for inputs Slave mode 5 -- -- 5 -- -- ns Electrical characteristics 2 DSPI characteristics(1) (continued) DSPI0/DSPI1/DSPI5/DSPI6 No. Symbol C Unit Min Typ Max Min Typ Max 0 -- -- 0 -- -- Slave mode 2(6) -- -- 2(6) -- -- Master mode -- -- 32 -- -- 50 Slave mode -- -- 52 -- -- 160 Master mode 0 -- -- 0 -- -- Slave mode 8 -- -- 13 -- -- Master mode 10 11 12 tHI DSPI2/DSPI4 Parameter SR D Data hold time for inputs tSUO(7) CC D Data valid after SCK edge tHO(7) CC D Data hold time for outputs ns ns Electrical characteristics 112/134 Table 48. ns 1. Operating conditions: CL = 10 to 50 pF, SlewIN = 3.5 to 15 ns 2. Maximum value is reached when CSn pad is configured as SLOW pad while SCK pad is configured as MEDIUM. A positive value means that SCK starts before CSn is asserted. DSPI2 has only SLOW SCK available. Doc ID 15131 Rev 7 3. Maximum value is reached when CSn pad is configured as MEDIUM pad while SCK pad is configured as SLOW. A positive value means that CSn is deasserted before SCK. DSPI0 and DSPI1 have only MEDIUM SCK available. 4. The tCSC delay value is configurable through a register. When configuring tCSC (using PCSSCK and CSSCK fields in DSPI_CTARx registers), delay between internal CS and internal SCK must be higher than tCSC to ensure positive tCSCext. 5. The tASC delay value is configurable through a register. When configuring tASC (using PASC and ASC fields in DSPI_CTARx registers), delay between internal CS and internal SCK must be higher than tASC to ensure positive tASCext. 6. This delay value corresponds to SMPL_PT = 00b which is bit field 9 and 8 of DSPI_MCR register. 7. SCK and SOUT are configured as MEDIUM pad. SPC560B54/6x SPC560B54/6x Electrical characteristics Figure 22. DSPI classic SPI timing -- master, CPHA = 0 2 3 PCSx 1 4 SCK Output (CPOL = 0) 4 SCK Output (CPOL = 1) 10 9 SIN First Data Last Data Data 12 SOUT First Data 11 Data Last Data Note: Numbers shown reference Table 47. Figure 23. DSPI classic SPI timing -- master, CPHA = 1 PCSx SCK Output (CPOL = 0) 10 SCK Output (CPOL = 1) 9 SIN Data First Data 12 SOUT First Data Last Data 11 Data Last Data Note: Numbers shown reference Table 47. Doc ID 15131 Rev 7 113/134 Electrical characteristics SPC560B54/6x Figure 24. DSPI classic SPI timing -- slave, CPHA = 0 3 2 SS 1 4 SCK Input (CPOL = 0) 4 SCK Input (CPOL = 1) 5 First Data SOUT 9 6 Data Last Data Data Last Data 10 First Data SIN 11 12 Note: Numbers shown reference Table 47. Figure 25. DSPI classic SPI timing -- slave, CPHA = 1 SS SCK Input (CPOL = 0) SCK Input (CPOL = 1) 11 5 12 SOUT First Data 9 SIN Data Last Data Data Last Data 6 10 First Data Note: Numbers shown reference Table 47. 114/134 Doc ID 15131 Rev 7 SPC560B54/6x Electrical characteristics Figure 26. DSPI modified transfer format timing -- master, CPHA = 0 3 PCSx 4 1 2 SCK Output (CPOL = 0) 4 SCK Output (CPOL = 1) 9 SIN 10 First Data Last Data Data 12 SOUT 11 First Data Last Data Data Note: Numbers shown reference Table 47. Figure 27. DSPI modified transfer format timing -- master, CPHA = 1 PCSx SCK Output (CPOL = 0) SCK Output (CPOL = 1) 10 9 SIN First Data Data 12 SOUT First Data Data Last Data 11 Last Data Note: Numbers shown reference Table 47. Doc ID 15131 Rev 7 115/134 Electrical characteristics SPC560B54/6x Figure 28. DSPI modified transfer format timing -- slave, CPHA = 0 3 2 SS 1 SCK Input (CPOL = 0) 4 4 SCK Input (CPOL = 1) First Data SOUT Data 6 Last Data 10 9 Data First Data SIN 12 11 5 Last Data Note: Numbers shown reference Table 47. Figure 29. DSPI modified transfer format timing -- slave, CPHA = 1 SS SCK Input (CPOL = 0) SCK Input (CPOL = 1) 11 5 12 First Data SOUT 9 SIN Data Last Data Data Last Data 6 10 First Data Note: Numbers shown reference Table 47. 116/134 Doc ID 15131 Rev 7 SPC560B54/6x Electrical characteristics Figure 30. DSPI PCS strobe (PCSS) timing 8 7 PCSS PCSx Note: Numbers shown reference Table 47. 4.18.3 Nexus characteristics Table 49. Nexus characteristics Value No. Symbol C Parameter Unit Min Typ Max 1 tTCYC CC D TCK cycle time 64 -- -- ns 2 tMCYC CC D MCKO cycle time 32 -- -- ns 3 tMDOV CC D MCKO low to MDO data valid -- -- 8 ns 4 tMSEOV CC D MCKO low to MSEO_b data valid -- -- 8 ns 5 tEVTOV CC D MCKO low to EVTO data valid -- -- 8 ns tNTDIS CC D TDI data setup time 15 -- -- ns tNTMSS CC D TMS data setup time 15 -- -- ns tNTDIH CC D TDI data hold time 5 -- -- ns tNTMSH CC D TMS data hold time 5 -- -- ns 6 7 8 tTDOV CC D TCK low to TDO data valid 35 -- -- ns 9 tTDOI CC D TCK low to TDO data invalid 6 -- -- ns Doc ID 15131 Rev 7 117/134 Electrical characteristics SPC560B54/6x Figure 31. Nexus TDI, TMS, TDO timing TCK 10 11 TMS, TDI 12 TDO Note: Numbers shown reference Table 49. 4.18.4 JTAG characteristics Table 50. JTAG characteristics Value No. Symbol C Parameter Unit Min Typ Max 1 tJCYC CC D TCK cycle time 64 -- -- ns 2 tTDIS CC D TDI setup time 15 -- -- ns 3 tTDIH CC D TDI hold time 5 -- -- ns 4 tTMSS CC D TMS setup time 15 -- -- ns 5 tTMSH CC D TMS hold time 5 -- -- ns 6 tTDOV CC D TCK low to TDO valid -- -- 33 ns 7 tTDOI CC D TCK low to TDO invalid 6 -- -- ns 118/134 Doc ID 15131 Rev 7 SPC560B54/6x Electrical characteristics Figure 32. Timing diagram -- JTAG boundary scan TCK 2/4 DATA INPUTS 3/5 INPUT DATA VALID 6 DATA OUTPUTS OUTPUT DATA VALID 7 DATA OUTPUTS Note: Numbers shown reference Table 50. Doc ID 15131 Rev 7 119/134 Package characteristics SPC560B54/6x 5 Package characteristics 5.1 ECOPACK(R) In order to meet environmental requirements, ST offers these devices in different grades of (R) (R) ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. (R) ECOPACK is an ST trademark. 5.2 Package mechanical data 5.2.1 LQFP176 Figure 33. LQFP176 package mechanical drawing 120/134 Doc ID 15131 Rev 7 SPC560B54/6x Table 51. Package characteristics LQFP176 mechanical data(1) inches(2) mm Symbol Min Typ Max A 1.400 -- 1.600 A1 0.050 -- 0.150 0.002 -- A2 1.350 -- 1.450 0.053 -- 0.057 b 0.170 -- 0.270 0.007 -- 0.011 C 0.090 -- 0.200 0.004 -- 0.008 D 23.900 -- 24.100 0.941 -- 0.949 E 23.900 -- 24.100 0.941 -- 0.949 e -- 0.500 -- -- 0.020 -- HD 25.900 -- 26.100 1.020 -- 1.028 HE 25.900 -- 26.100 1.020 -- 1.028 0.450 -- 0.750 0.018 -- 0.030 L1 -- 1.000 -- -- 0.039 -- ZD -- 1.250 -- -- 0.049 -- ZE -- 1.250 -- -- 0.049 -- q 0 -- 7 0 -- 7 (3) L Min Typ Max -- 0.063 Tolerance mm inches ccc 0.080 0.0031 1. Controlling dimension: millimeter 2. Values in inches are converted from mm and rounded to 4 decimal digits. 3. L dimension is measured at gauge plane at 0.25 mm above the seating plane. Doc ID 15131 Rev 7 121/134 Package characteristics 5.2.2 SPC560B54/6x LQFP144 Figure 34. LQFP144 package mechanical drawing 122/134 Doc ID 15131 Rev 7 SPC560B54/6x Table 52. Package characteristics LQFP144 mechanical data inches(1) mm Symbol Min Typ Max Min Typ Max A -- -- 1.600 -- -- 0.0630 A1 0.050 -- 0.150 0.0020 -- 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 -- 0.200 0.0035 -- 0.0079 D 21.800 22.000 22.200 0.8583 0.8661 0.8740 D1 19.800 20.000 20.200 0.7795 0.7874 0.7953 D3 -- 17.500 -- -- 0.6890 -- E 21.800 22.000 22.200 0.8583 0.8661 0.8740 E1 19.800 20.000 20.200 0.7795 0.7874 0.7953 E3 -- 17.500 -- -- 0.6890 -- e -- 0.500 -- -- 0.0197 -- L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 -- 1.000 -- -- 0.0394 -- k 0.0 3.5 7.0 3.5 0.0 7.0 Tolerance mm inches ccc 0.080 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Doc ID 15131 Rev 7 123/134 Package characteristics 5.2.3 SPC560B54/6x LQFP100 Figure 35. LQFP100 package mechanical drawing 124/134 Doc ID 15131 Rev 7 SPC560B54/6x Table 53. Package characteristics LQFP100 mechanical data inches(1) mm Symbol Min Typ Max Min Typ Max A -- -- 1.600 -- -- 0.0630 A1 0.050 -- 0.150 0.0020 -- 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 -- 0.200 0.0035 -- 0.0079 D 15.800 16.000 16.200 0.6220 0.6299 0.6378 D1 13.800 14.000 14.200 0.5433 0.5512 0.5591 D3 -- 12.000 -- -- 0.4724 -- E 15.800 16.000 16.200 0.6220 0.6299 0.6378 E1 13.800 14.000 14.200 0.5433 0.5512 0.5591 E3 -- 12.000 -- -- 0.4724 -- e -- 0.500 -- -- 0.0197 -- L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 -- 1.000 -- -- 0.0394 -- k 0.0 3.5 7.0 0.0 3.5 7.0 Tolerance mm inches ccc 0.080 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Doc ID 15131 Rev 7 125/134 Package characteristics 5.2.4 SPC560B54/6x LBGA208 Figure 36. LBGA208 package mechanical drawing ddd C Seating plane A A A1 A3 A4 B A2 D D D1 e A F E e E1 F T R P N M L K J H G F E D C B A 1 3 2 5 4 7 6 9 8 A1 corner index area (See note 1) 11 13 15 10 12 14 16 b (208 balls) eee M C A B fff M C Bottom view 1. The terminal A1 corner must be identified on the top surface by using a corner chamfer, ink or metallized markings, or other feature of package body or integral heatslug. A distinguishing feature is allowable on the bottom surface of the package to identify the terminal A1 corner. Exact shape of each corner is optional. 126/134 Doc ID 15131 Rev 7 SPC560B54/6x Table 54. Package characteristics LBGA208 mechanical data inches(1) mm Symbol Notes Min Typ Max Min Typ Max A -- -- 1.70 -- -- 0.0669 (2) A1 0.30 -- -- 0.0118 -- -- -- A2 -- 1.085 -- -- 0.0427 -- -- A3 -- 0.30 -- -- 0.0118 -- -- A4 -- -- 0.80 -- -- 0.0315 -- b 0.50 0.60 0.70 0.0197 0.0236 0.0276 (3) D 16.80 17.00 17.20 0.6614 0.6693 0.6772 -- D1 -- 15.00 -- -- 0.5906 -- -- E 16.80 17.00 17.20 0.6614 0.6693 0.6772 -- E1 -- 15.00 -- -- 0.5906 -- -- e -- 1.00 -- -- 0.0394 -- -- F -- 1.00 -- -- 0.0394 -- -- ddd -- -- 0.20 -- -- 0.0079 eee -- -- 0.25 -- -- 0.0098 (4) fff -- -- 0.10 -- -- 0.0039 (5) 1. Values in inches are converted from mm and rounded to 4 decimal digits. 2. LBGA stands for Low profile Ball Grid Array. - Low profile: The total profile height (Dim A) is measured from the seating plane to the top of the component - The maximum total package height is calculated by the following methodology: A2 (Typ) + A1 (Typ) + (A12 + A32 + A42 tolerance values) - Low profile: 1.20 mm < A < 1.70 mm 3. The typical ball diameter before mounting is 0.60mm. 4. The tolerance of position that controls the location of the pattern of balls with respect to datums A and B. For each ball there is a cylindrical tolerance zone eee perpendicular to datum C and located on true position with respect to datums A and B as defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone. 5. The tolerance of position that controls the location of the balls within the matrix with respect to each other. For each ball there is a cylindrical tolerance zone fff perpendicular to datum C and located on true position as defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone. Each tolerance zone fff in the array is contained entirely in the respective zone eee above. The axis of each ball must lie simultaneously in both tolerance zones. Doc ID 15131 Rev 7 127/134 Ordering information 6 SPC560B54/6x Ordering information Figure 37. Commercial product code structure Example code: SPC56 0 B 64 L3 C 5E0 Y Product identifier Core Family Memory Package Temperature Custom vers. Packing Y = Tray X = Tape and Reel 90 4E0 = 48 MHz EEPROM 5V/3V 6E0 = 64 MHz EEPROM 5V/3V B = 40 to 105C C = 40 to 125C L3 = LQFP100 L5 = LQFP144 L7 = LQFP176 B2 = LBGA2081 64 = 1536 KB 60 = 1024 KB 54 = 768 KB B = Body 0 = e200z0h SPC56 = Power Architecture in 90nm 1. LBGA208 is available only as development package for Nexus2+. 128/134 Doc ID 15131 Rev 7 SPC560B54/6x Abbreviations Appendix A Abbreviations Table 55 lists abbreviations used but not defined elsewhere in this document. Table 55. Abbreviations Abbreviation Meaning CMOS Complementary metal oxide semiconductor CPHA Clock phase CPOL Clock polarity CS Peripheral chip select EVTO Event out MCKO Message clock out MDO Message data out MSEO Message start/end out MTFE Modified timing format enable SCK Serial communications clock SOUT Serial data out TBD To be defined TCK Test clock input TDI Test data input TDO Test data output TMS Test mode select Doc ID 15131 Rev 7 129/134 Revision history SPC560B54/6x Revision history Table 56. Revision history Date Revision 12-Jan-2009 1 Initial release 2 Updated Device Summary-added LBGA208 Part number Updated Features Replaced 27 IRQs in place of 23 ADC features External Ballast resistor support conditions Updated device summary-added 208 BGA details Updated block diagram to include WKUP Updated block diagram to include 5 ch ADC 12 -bit Updated Block summary table Updated LQFP 144, 176 and 100 pinouts. Applied new naming convention for ADC signals as ADCx_P[x] and ADCx_S[x] Section 1, "General description Updated SPC560B54/60/64 device comparison table Updated block diagram-aligned with 512k Updated block summary-aligned with 512k Section 2, "Package pinouts Updated 100,144,176,208 packages according to cut2.0 changes Added Section 3.5.1, "External ballast resistor recommendations Added NVUSRO [WATCHDOG_EN] field description Updated Absolute maximum ratings Updated LQFP thermal characteristics Updated I/O supply segments Updated Voltage regulator capacitance connection Updated Low voltage monitor electrical characteristics Updated Low voltage power domain electrical characteristics Updated DC electrical characteristics Updated Program/Erase specifications Updated Conversion characteristics (10 bit ADC) Updated FMPLL electrical characteristics Updated Fast RC oscillator electrical characteristics-aligned with SPC560B4x/B5x/C4x/C5x Updated On-chip peripherals current consumption Updated ADC characteristics and error definitions diagram Updated ADC conversion characteristics (10 bit and 12 bit) Added ADC characteristics and error definitions diagram for 12 bit ADC 3 Updated Features Updated block diagram to connect peripherals to pad I/O Updated block summary to include ADC 12-bit Updated 144, 176 and 100 pinouts to adjust format issues Table 26 Flash module life-retention value changed from 1-5 to 5 yrs Minor editing changes 07-Dec-2009 23-Feb-2010 130/134 Changes Doc ID 15131 Rev 7 SPC560B54/6x Table 56. Revision history Revision history (continued) Date 13-Sep-2010 Revision Changes 4 Editorial changes and improvements. Cover page: removed LBGA208 package silhouette Updated "Features" section Table 2: updated footnote concerning LBGA208 In the block diagram: - Added "5ch 12-bit ADC" block. - Updated Legend. - Added "Interrupt request with wakeup functionality" as an input to the WKPU block. Figure 2: removed alternate functions Figure 3: removed alternate functions Figure 4: removed alternate functions Table 3: added contents concerning the following blocks: CMU, eDMA, ECSM, MC_ME, MC_PCU, NMI, SSCM, SWT and WKPU Added Section 3.2, Pin muxing Section 4: Electrical characteristics: removed "Caution" note Section 4.2: NVUSRO register: removed "NVUSRO[WATCHDOG_EN] field description" section Table 12: VIN: removed min value in "relative to VDD" row Table 13 - TVDD: contents merged into one row - VDD_BV: changed min value in "relative to VDD" row Section 4.5: Thermal characteristics - Section 4.5.1: External ballast resistor recommendations: added new paragraph about power supply - Table 15: added RJB and RJC rows - Removed "LBGA208 thermal characteristics" table Table 16: rewrote parameter description of WFI and WNFI Section 4.6.5: I/O pad current specification - Removed IDYNSEG information - Updated "I/O supply segments" table Table 23: removed IDYNSEG row Added Table 24 Table 26 - Updated all values - Removed IVREGREF and IVREDLVD12 rows - Added the footnote "The duration of the in-rush current depends on the capacitance placed on LV pins. BV decaps must be sized accordingly. Refer to IMREG value for minimum amount of current to be provided in cc." to the IDD_BV specification. Table 27 - Updated VPORH min/max value - Updated VLVDLVCORL min value Updated Table 28 Table 29 - Tdwprogram: added initial max value - Inserted Teslat row Table 30: removed the "To be confirmed" footnote In the "Crystal oscillator and resonator connection scheme" figure, removed RP. Doc ID 15131 Rev 7 131/134 Revision history Table 56. SPC560B54/6x Revision history (continued) Date Revision Changes Table 40 - Removed gmSXOSC row - ISXOSCBIAS: added min/typ/max value Table 41: - Added fVCO row - Added tSTJIT row Table 42 - IFIRCPWD: removed row for TA = 55 C 13-Sep-2010 4 - Updated TFIRCSU row (continued) (continued) Table 45: Added two rows: IADC0pwd and IADC0run Table 46 - Added two rows: IADC1pwd and IADC1run - Updated values of fADC_1 and tADC1_PU - Updated tADC1_C row Updated Table 47 Updated Table 48 Added Table 55 29-Oct- 2010 12-Sep- 2011 132/134 5 Removed "Preliminary--Subject to Change Without Notice" marking. This data sheet contains specifications based on characterization data. Updated Table 55 Added Table 56 Updated Figure 37 6 Editorial and formatting changes throughout Replaced instances of "e200z0" with "e200z0h" Device family comparision table: - added 1 MB code flash LQFP100 version - added 1.5 MB code flash LQFP144 version - removed 768 KB code flash LQFP176 version - changed LINFlex count for 144-pin LQFP--was `6'; is `8' - changed LINFlex count for 176-pin LQFP--was `8'; is `10' - replaced 105 C with 125 C in footnote 2 SPC560B54/6 block diagram: added GPIO and VREG to legend SPC560B54/6 series block summary: added acronym "JTAGC"; in WKPU function changed "up to 18 external sources" to "up to 27 external sources" LQFP144 pin configuration: for pins 37-72, restored the pin labels that existed prior to 27 July 2010 LQFP176 pin configuration: corrected name of pin 4: was EPC[15]; is PC[15] Added following sections: - Pad configuration during reset phases - Pad configuration during standby mode exit - Voltage supply pins - Pad types - System pins - Functional port pins - Nexus 2+ pins Doc ID 15131 Rev 7 SPC560B54/6x Table 56. Revision history Revision history (continued) Date Revision Changes Section "NVUSRO register": edited content to separate configuration into electrical parameters and digital functionality; updated footnote describing default value of `1' in field descriptions NVUSRO[PAD3V5V] and NVUSRO[OSCILLATOR_MARGIN] Added section "NVUSRO[WATCHDOG_EN] field description" Tables "Absolute maximum ratings" and "Recommended operating conditions (3.3 V)": replaced "VSS_HV_ADC0, VSS_HV_ADC1" with "VDD_HV_ADC0, VDD_HV_ADC1" in VDD_ADC parameter description "Recommended operating conditions (5.0 V)" table: replaced "VSS_HV_ADC0, VSS_HV_ADC1" with "VDD_HV_ADC0, VDD_HV_ADC1" in VDD_ADC parameter description; changed 3.6V to 3.0V in footnote 2 Section "External ballast resistor recommendations": replaced "low voltage monitor" with "low voltage detector (LVD)" "I/O input DC electrical characteristics" table: updated ILKG characteristics "MEDIUM configuration output buffer electrical characteristics" table: changed "IOH = 100 A" to "IOL = 100 A" in VOL conditions I/O weight: updated table (includes replacing instances of bit "SRE" with "SRC") "Reset electrical characteristics" table: updated parameter classification for |IWPU| Updated voltage regulator electrical characteristics Section "Low voltage detector electrical characteristics": changed title (was "Voltage monitor electrical characteristics"); changed "as well as four low voltage detectors" to "as well as five low voltage detectors"; added event status flag names found in RGM chapter of device reference manual to POR module and LVD descriptions; replaced instances of "Low voltage monitor" with "Low voltage detector"; updated values for VLVDLVBKPL and VLVDLVCORL 12-Sep- 2011 6 Updated section "Power consumption" (continued) (continued) Section "Program/erase characteristics": removed table "FLASH_BIU settings vs. frequency of operation" and associated introduction "Program and erase specifications" table: updated symbols PFCRn settings vs. frequency of operation: replaced "FLASH_BIU" with "PFCRn" in table title; updated field names and frequencies "Flash power supply DC electrical characteristics" table: deleted footnote 2 Crystal oscillator and resonator connection scheme: inserted footnote about possibly requiring a series resistor Fast external crystal oscillator (4 to 16 MHz) electrical characteristics: updated parameter classification for VFXOSCOP Slow external crystal oscillator (32 kHz) electrical characteristics: updated footnote 1 Section "ADC electrical characteristics": updated symbols for offset error and gain error Section "Input impedance and ADC accuracy": changed "VA/VA2" to "VA2/VA" in Equation 11 ADC input leakage current: updated ILKG characteristics ADC_0 conversion characteristics table: replaced instances of "ADCx_conf_sample_input" with "INPSAMP"; replaced instances of "ADCx_conf_comp" with "INPCMP ADC_1 characteristic and error definitions: replaced "AVDD" with "VDD_ADC" ADC_1 conversion characteristics table: replaced instances of "ADCx_conf_sample_input" with "INPSAMP"; replaced instances of "ADCx_conf_comp" with "INPCMP" Updated "On-chip peripherals current consumption" table Removed order codes tables. 18-Sep-2013 7 Updated Disclaimer. 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