VN7008AJ High-side driver with CurrentSense analog feedback for automotive applications Datasheet - production data - - - - - Features Max transient supply voltage VCC 40 V Operating voltage range VCC 4 to 28 V Typ. on-state resistance (per Ch) RON 8.5 m Current limitation (typ) ILIMH 96 A Standby current (max) ISTBY 0.5 A * * * * Automotive qualified General - Single channel smart high side driver with CS analog feedback - Very low standby current - Compatible with 3 V and 5 V CMOS outputs CS diagnostic functions - Analog feedback of: load current with high precision proportional current mirror - Overload and short to ground (power limitation) indication - Thermal shutdown indication - OFF-state open-load detection - Output short to VCC detection - Sense enable/ disable Protections - Undervoltage shutdown - Overvoltage clamp March 2016 - Applications * * All types of Automotive resistive, inductive and capacitive loads Specially intended for Automotive Headlamps Description The device is a single channel high-side driver manufactured using ST proprietary VIPower(R) technology and housed in PowerSSO-16 package. The device is designed to drive 12 V automotive grounded loads through a 3 V and 5 V CMOS-compatible interface, and to provide protection and diagnostics. The device integrates advanced protective functions such as load current limitation, overload active management by power limitation and overtemperature shutdown with configurable latch-off. A FaultRST pin unlatches the output in case of fault or disables the latch-off functionality. A sense enable pin allows OFF-state diagnosis to be disabled during the module low-power mode as well as external sense resistor sharing among similar devices. DocID027771 Rev 4 This is information on a product in full production. Load current limitation Self limiting of fast thermal transients Configurable latch-off on overtemperature or power limitation with dedicated fault reset pin Loss of ground and loss of VCC Reverse battery with external components Electrostatic discharge protection 1/42 www.st.com Contents VN7008AJ Contents 1 Block diagram and pin description ................................................ 5 2 Electrical specification.................................................................... 7 3 4 2.1 Absolute maximum ratings ................................................................ 7 2.2 Thermal data ..................................................................................... 8 2.3 Main electrical characteristics ........................................................... 8 2.4 Waveforms ...................................................................................... 16 2.5 Electrical characteristics curves ...................................................... 19 Protections..................................................................................... 23 3.1 Power limitation ............................................................................... 23 3.2 Thermal shutdown........................................................................... 23 3.3 Current limitation ............................................................................. 23 3.4 Negative voltage clamp ................................................................... 23 Application information ................................................................ 24 4.1 GND protection network against reverse battery............................. 24 4.1.1 5 Diode (DGND) in the ground line ..................................................... 25 4.2 Immunity against transient electrical disturbances .......................... 25 4.3 MCU I/Os protection........................................................................ 25 4.4 CS - analog current sense .............................................................. 26 4.4.1 Principle of CurrentSense signal generation .................................... 27 4.4.2 Short to VCC and OFF-state open-load detection ........................... 29 Package and PCB thermal data .................................................... 31 5.1 PowerSSO-16 thermal data ............................................................ 31 6 Maximum demagnetization energy (VCC = 16 V) ........................ 34 7 Package information ..................................................................... 35 8 9 2/42 7.1 PowerSSO-16 package information ................................................ 35 7.2 PowerSSO-16 packing information ................................................. 37 7.3 PowerSSO-16 marking information ................................................. 39 Order codes ................................................................................... 40 Revision history ............................................................................ 41 DocID027771 Rev 4 VN7008AJ List of tables List of tables Table 1: Pin functions ................................................................................................................................. 5 Table 2: Suggested connections for unused and not connected pins ........................................................ 6 Table 3: Absolute maximum ratings ........................................................................................................... 7 Table 4: Thermal data ................................................................................................................................. 8 Table 5: Power section ............................................................................................................................... 8 Table 6: Switching....................................................................................................................................... 9 Table 7: Logic Inputs................................................................................................................................. 10 Table 8: Protections .................................................................................................................................. 10 Table 9: CurrentSense .............................................................................................................................. 11 Table 10: Truth table ................................................................................................................................. 15 Table 11: CurrentSense multiplexer addressing ...................................................................................... 16 Table 12: ISO 7637-2 - electrical transient conduction along supply line................................................. 25 Table 13: CurrentSense pin levels in off-state .......................................................................................... 29 Table 14: PCB properties ......................................................................................................................... 31 Table 15: Thermal parameters ................................................................................................................. 33 Table 16: PowerSSO-16 mechanical data................................................................................................ 35 Table 17: Reel dimensions ....................................................................................................................... 37 Table 18: PowerSSO-16 carrier tape dimensions .................................................................................... 38 Table 19: Device summary ....................................................................................................................... 40 Table 20: Document revision history ........................................................................................................ 41 DocID027771 Rev 4 3/42 List of figures VN7008AJ List of figures Figure 1: Block diagram .............................................................................................................................. 5 Figure 2: Configuration diagram (top view)................................................................................................. 6 Figure 3: Current and voltage conventions ................................................................................................. 7 Figure 4: IOUT/ISENSE versus IOUT....................................................................................................... 13 Figure 5: Current sense accuracy versus IOUT ....................................................................................... 13 Figure 6: Switching times and Pulse skew ............................................................................................... 14 Figure 7: CurrentSense timings (current sense mode) ............................................................................. 14 Figure 8: TDSTKON.................................................................................................................................. 15 Figure 9: Latch functionality - behavior in hard short circuit condition (TAMB << TTSD) ........................ 16 Figure 10: Latch functionality - behavior in hard short circuit condition.................................................... 17 Figure 11: Latch functionality - behavior in hard short circuit condition (autorestart mode + latch off) .... 17 Figure 12: Standby mode activation ......................................................................................................... 18 Figure 13: Standby state diagram ............................................................................................................. 18 Figure 14: OFF-state output current ......................................................................................................... 19 Figure 15: Standby current ....................................................................................................................... 19 Figure 16: IGND(ON) vs Tcase ................................................................................................................ 19 Figure 17: Logic Input high level voltage .................................................................................................. 19 Figure 18: Logic Input low level voltage.................................................................................................... 19 Figure 19: High level logic input current ................................................................................................... 19 Figure 20: Low level logic input current .................................................................................................... 20 Figure 21: Logic Input hysteresis voltage ................................................................................................. 20 Figure 22: FaultRST Input clamp voltage ................................................................................................. 20 Figure 23: Undervoltage shutdown ........................................................................................................... 20 Figure 24: On-state resistance vs Tcase .................................................................................................. 20 Figure 25: On-state resistance vs VCC .................................................................................................... 20 Figure 26: Turn-on voltage slope .............................................................................................................. 21 Figure 27: Turn-off voltage slope .............................................................................................................. 21 Figure 28: Won vs Tcase .......................................................................................................................... 21 Figure 29: Woff vs Tcase .......................................................................................................................... 21 Figure 30: ILIMH vs. Tcase ....................................................................................................................... 21 Figure 31: OFF-state open-load voltage detection threshold ................................................................... 21 Figure 32: Vsense clamp vs. Tcase.......................................................................................................... 22 Figure 33: Vsenseh vs. Tcase .................................................................................................................. 22 Figure 34: Application diagram ................................................................................................................. 24 Figure 35: Simplified internal structure ..................................................................................................... 24 Figure 36: CurrectSense and diagnostic - block diagram ........................................................................ 26 Figure 37: CurrentSense block diagram ................................................................................................... 27 Figure 38: Analogue HSD - open-load detection in off-state ................................................................... 28 Figure 39: Open-load / short to VCC condition ......................................................................................... 29 Figure 40: PowerSSO-16 on two-layers PCB (2s0p to JEDEC JESD 51-5) ............................................ 31 Figure 41: PowerSSO-16 on four-layers PCB (2s2p to JEDEC JESD 51-7) ........................................... 31 Figure 42: Rthj-amb vs PCB copper area in open box free air conditions ............................................... 32 Figure 43: PowerSSO-16 thermal impedance junction ambient single pulse .......................................... 32 Figure 44: Thermal fitting model for PowerSSO-16 .................................................................................. 33 Figure 45: Maximum turn off current versus inductance .......................................................................... 34 Figure 46: PowerSSO-16 package dimensions ........................................................................................ 35 Figure 47: PowerSSO-16 reel 13" ............................................................................................................ 37 Figure 48: PowerSSO-16 carrier tape ...................................................................................................... 38 Figure 49: PowerSSO-16 schematic drawing of leader and trailer tape .................................................. 38 Figure 50: PowerSSO-16 marking information ......................................................................................... 39 4/42 DocID027771 Rev 4 VN7008AJ 1 Block diagram and pin description Block diagram and pin description Figure 1: Block diagram Table 1: Pin functions Name VCC OUTPUT GND INPUT Function Battery connection. Power outputs. All the pins must be connected together. Ground connection. Must be reverse battery protected by an external diode / resistor network. Voltage controlled input pin with hysteresis, compatible with 3 V and 5 V CMOS outputs. It controls output switch state. CS Analog current sense output pin delivers a current proportional to the load current. SEn Active high compatible with 3 V and 5 V CMOS outputs pin; it enables the CS diagnostic pin. FaultRST Active low compatible with 3 V and 5 V CMOS outputs pin; it unlatches the output in case of fault; If kept low, sets the outputs in auto-restart mode. DocID027771 Rev 4 5/42 Block diagram and pin description VN7008AJ Figure 2: Configuration diagram (top view) Pins 9, 10, 11 and 12 are internally connected; Pins 13, 14, 15 and 16 are internally connected; All output pins must be connected together on PCB. Table 2: Suggested connections for unused and not connected pins SEn, Connection / pin CS N.C. Output Input Floating Not allowed X (1) X X To ground Through 1 k resistor X Not allowed Notes: (1)X: 6/42 do not care. DocID027771 Rev 4 FaultRST X Through 15 k Through 15 k resistor resistor VN7008AJ 2 Electrical specification Electrical specification Figure 3: Current and voltage conventions VF = VOUT - VCC during reverse battery condition. 2.1 Absolute maximum ratings Stressing the device above the rating listed in Table 3: "Absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to the conditions in table below for extended periods may affect device reliability. Table 3: Absolute maximum ratings Symbol Parameter Value VCC DC supply voltage 38 -VCC Reverse DC supply voltage 0.3 VCCPK Maximum transient supply voltage (ISO 16750-2:2010 Test B clamped to 40V; RL = 4 ) 40 VCCJS Maximum jump start voltage for single pulse short circuit protection 28 -IGND DC reverse ground pin current 200 IOUT OUTPUT DC output current Internally limited -IOUT Reverse DC output current 35 IIN INPUT DC input current ISEn SEn DC input current IFR FaultRST DC input current VFR ISENSE Unit V mA A -1 to 10 mA FaultRST DC input voltage 7.5 V CS pin DC output current (VGND = VCC and VSENSE < 0 V) 10 CS pin DC output current in reverse (VCC < 0V) -20 DocID027771 Rev 4 mA 7/42 Electrical specification VN7008AJ Symbol Parameter Unit EMAX Maximum switching energy (single pulse) (TDEMAG = 0.4 ms; Tjstart = 150 C) 170 mJ VESD Electrostatic discharge (JEDEC 22A-114F) * INPUT * CS * SEn, FaultRST * OUTPUT * VCC 4000 2000 4000 4000 4000 V V V V V VESD Charge device model (CDM-AEC-Q100-011) 750 V Tj Tstg 2.2 Value Junction operating temperature -40 to 150 Storage temperature -55 to 150 C Thermal data Table 4: Thermal data Symbol Parameter Typ. value Rthj-board Thermal resistance junction-board (JEDEC JESD 51-5 / 51-8)(1) Unit 3.85 Rthj-amb Thermal resistance junction-ambient (JEDEC JESD 51-5)(2) 54.8 Rthj-amb Thermal resistance junction-ambient (JEDEC JESD 51-7)(1) 21 C/W Notes: 2.3 (1)Device mounted on four-layers 2s2p PCB. (2)Device mounted on two-layers 2s0p PCB with 2 cm2 heatsink copper trace. Main electrical characteristics 7 V < VCC < 18 V; -40 C < Tj < 150 C, unless otherwise specified. All typical values refer to VCC = 13 V; Tj = 25C, unless otherwise specified. Table 5: Power section Symbol Parameter VCC Operating supply voltage VUSD Undervoltage shutdown Test conditions Min. Typ. Max. Unit 4 13 4 5 V IOUT = 5 A; Tj = 150 C 17 m IOUT = 5 A; VCC = 4 V; Tj = 25 C 12.75 VUSDReset Undervoltage shutdown reset VUSDhyst Undervoltage shutdown hysteresis 0.3 IOUT = 5 A; Tj = 25 C RON Vclamp 8/42 On-state resistance Clamp voltage 28 8.5 IS = 20 mA; Tj = -40C 38 IS = 20 mA; 25C < Tj < 150C 41 DocID027771 Rev 4 46 52 V VN7008AJ Electrical specification Symbol Parameter Test conditions Supply current in standby at VCC = 13 V (1) ISTBY tD_STBY IS(ON) IGND(ON) IL(off) VF VCC = 13 V; VIN = VOUT = VFR = VSEn = 0 V; Tj = 25 C 0.5 A VCC = 13 V; VIN = VOUT = VFR = VSEn = 0 V; Tj = 85 C (2) 0.5 A VCC = 13 V; VIN = VOUT = VFR = VSEn = 0 V; Tj = 125 C 3 A 300 550 s 3 5 mA 6 mA Standby mode blanking time VCC = 13 V; VIN = 5 V; VSEn = VFR = 0 V; IOUT = 0 A Supply current VCC = 13 V; VSEn = VFR = 0 V; VIN = 5 V; IOUT = 0 A Control stage current consumption in ON state. All channels active. VCC = 13 V; VSEn = 5 V; VFR = 0 V; VIN = 5 V; IOUT = 5 A Off-state output current at VCC = 13 V Output - VCC diode voltage Min. Typ. Max. Unit 60 VIN = VOUT = 0 V; VCC = 13 V; Tj = 25 C 0 VIN = VOUT = 0 V; VCC = 13 V; Tj = 125 C 0 0.01 0.5 A 3 IOUT = -5 A; Tj = 150 C 0.7 V Notes: (1)PowerMOS (2)Parameter leakage included. specified by design; not subject to production test. Table 6: Switching Symbol Parameter Test conditions Min. Typ. Max. Unit VCC = 13 V; -40C < Tj < 150C, unless otherwise specified td(on)(1) Turn-on delay time at Tj = 25C td(off)(1) Turn-off delay time at Tj = 25C (dVOUT/dt)on(1) Turn-on voltage slope at Tj = 25C (dVOUT/dt)off (1) Turn-off voltage slope at Tj = 25C RL = 2.6 RL = 2.6 10 45 120 10 48 100 0.1 0.2 0.7 0.1 0.3 0.7 s V/s WON Switching energy losses at turn-on (twon) RL = 2.6 -- 0.8 1.2(2) mJ WOFF Switching energy losses at turn-off (twoff) RL = 2.6 -- 0.6 1(2) mJ Differential Pulse skew (tPHL - tPLH) RL = 2.6 -65 -15 35 s tSKEW (1) Notes: (1)See Figure 6: "Switching times and Pulse skew". (2)Parameter guaranteed by design and characterization; not subject to production test. DocID027771 Rev 4 9/42 Electrical specification VN7008AJ Table 7: Logic Inputs Symbol Parameter Test conditions Min. Typ. Max. Unit 7 V < VCC < 28 V; -40C < Tj < 150C INPUT characteristics VIL Input low level voltage IIL Low level input current VIH Input high level voltage IIH High level input current VI(hyst) Input hysteresis voltage VICL 0.9 VIN = 0.9 V A 2.1 V VIN = 2.1 V 10 0.2 IIN = 1 mA Input clamp voltage V 1 V 5.3 IIN = -1 mA A 7.5 -0.7 V FaultRST characteristics VFRL Input low level voltage IFRL Low level input current VFRH Input high level voltage IFRH High level input current VFR(hyst) Input hysteresis voltage VFRCL 0.9 VIN = 0.9 V 1 A 2.1 V VIN = 2.1 V 10 0.2 IIN = 1 mA Input clamp voltage V V 5.3 IIN = -1 mA A 7.2 -0.7 V SEn characteristics (7 V < VCC < 18 V) VSEnL Input low level voltage ISEnL Low level input current VSEnH Input high level voltage ISEnH High level input current VSEn(hyst) Input hysteresis voltage VSEnCL 0.9 VIN = 0.9 V A 2.1 V VIN = 2.1 V 10 0.2 IIN = 1 mA Input clamp voltage V 1 V 5.3 IIN = -1 mA A 7.5 -0.7 V Table 8: Protections Symbol Parameter Test conditions Min. Typ. Max. 70 98 140 Unit 7 V < VCC < 18 V; -40C < Tj < 150C ILIMH DC short circuit current ILIML Short circuit current during thermal cycling TTSD Shutdown temperature TR Reset temperature(1) TRS Thermal reset of fault diagnostic indication THYST 10/42 VCC = 13 V 4 V < VCC < 18 V (1) 140 VCC = 13 V; TR < Tj < TTSD VFR = 0 V; VSEn = 5 V; Thermal hysteresis (TTSD - TR)(1) 33 150 175 TRS + 1 TRS + 7 200 C 135 7 DocID027771 Rev 4 A VN7008AJ Electrical specification Symbol Parameter Test conditions Min. Typ. Max. Unit 7 V < VCC < 18 V; -40C < Tj < 150C TJ_SD tLATCH_RST VDEMAG VON Dynamic temperature Tj = -40 C; VCC = 13 V Fault reset time for output unlatch(1) VFR = 5 V to 0 V; VSEn = 5 V; VIN = 5 V 3 IOUT = 2 A; L = 6 mH; Tj = -40 C VCC - 38 V IOUT = 2 A; L = 6 mH; Tj = 25 C to 150 C VCC - 41 VCC - 46 VCC - 52 V 20 mV Turn-off output voltage clamp Output voltage drop limitation 60 IOUT = 0.25 A K 10 20 s Notes: (1)Parameter guaranteed by design and characterization; not subject to production test. Table 9: CurrentSense Symbol Parameter Test conditions Min. Typ. Max. Unit 7 V < VCC < 18 V; -40C < Tj < 150C VSENSE_CL Current sense clamp voltage VSEn = 0 V; ISENSE = 1 mA -17 VSEn = 0 V; ISENSE = -1 mA -12 V 7 V Current Sense characteristics K0 IOUT = 0.9 A; VSENSE = 0.5 V; VSEn = 5 V IOUT/ISENSE dK0/K0(1)(2) Current sense ratio drift K1 IOUT = 1.5 A; VSENSE = 4 V; VSEn = 5 V IOUT/ISENSE dK1/K1(2)(1) Current sense ratio drift K2 IOUT = 6 A; VSENSE = 4 V; VSEn = 5 V IOUT = 18 A; VSENSE = 4 V; VSEn = 5 V IOUT/ISENSE dK3/K3(2)(1) Current sense ratio drift VOUT_MSD(2) IOUT = 1.5 A; VSENSE = 4 V; VSEn = 5 V IOUT = 6 A; VSENSE = 4 V; VSEn = 5 V IOUT/ISENSE dK2/K2(2)(1) Current sense ratio drift K3 IOUT = 0.9 A; VSENSE = 0.5 V; VSEn = 5 V Output Voltage for current sense shutdown IOUT = 18 A; VSENSE = 4 V; VSEn = 5 V; Tj = -40 C to 150 C 3465 6150 9135 20 -20 % 3735 5990 8725 15 -15 % 4410 5890 7360 +10 -10 % 5290 5880 6470 -5 VIN = 5 V; VSEn = 5 V; RSENSE = 2.7 k; IOUT = 5 A 5 5 % V VSENSE_SAT CS saturation voltage VCC = 7 V; RSENSE = 2.7 k; VSEn = 5 V; VIN = 5 V; IOUT = 18 A; Tj = 150C 5 V ISENSE_SAT(2) CS saturation current VCC = 7 V; VSENSE = 4 V; VIN = 5 V; VSEn = 5 V; Tj = 150C 4 mA DocID027771 Rev 4 11/42 Electrical specification Symbol VN7008AJ Parameter Test conditions Min. Typ. Max. Unit 7 V < VCC < 18 V; -40C < Tj < 150C IOUT_SAT(2) Output saturation current VCC = 7 V; VSENSE = 4 V; VIN = 5 V; VSEn = 5 V; Tj = 150C 24 CS disabled: VSEn = 0 V; 0 0.5 -0.5 0.5 CS enabled: VSEn = 5 V; Channel ON; IOUT = 0 A; Diagnostic selected; VIN = 5 V; IOUT = 0 A; 0 2 CS enabled: VSEn = 5 V; Channel OFF; Diagnostic selected: VIN = 0 V 0 2 CS disabled: -1 V < VSENSE < 5 V(2) ISENSE0 Current sense leakage current A A OFF-state diagnostic VOL OFF-state open-load voltage detection threshold VIN = 0 V; VSEn = 5 V 2 IL(off2) OFF-state output sink current VIN = 0 V; VOUT = VOL; Tj = -40C to 125C -100 tDSTKON OFF-state diagnostic delay VIN = 5 V to 0 V; VSEn = 5 V; time from falling edge of INPUT IOUT = 0 A; VOUT = 4 V (see Figure 8: "TDSTKON") tD_OL_V Settling time for valid OFF-state VIN = 0 V; VFR = 0 V; VOUT = 4 V; open load diagnostic indication VSEn = 0 V to 5 V from rising edge of SEn tD_VOL OFF-state diagnostic delay time from rising edge of VOUT 100 VIN = 0 V; VSEn = 5 V; VOUT = 0 V to 4 V 3 350 5 4 V -15 A 700 s 60 s 30 s 6.6 V 30 mA Fault diagnostic feedback (see Table 10: "Truth table") VSENSEH VCC = 13 V; VIN = 0 V; Current sense output voltage in VSEn = 5 V; IOUT = 0 A; fault condition VOUT = 4 V; RSENSE = 1 k 5 ISENSEH Current sense output current in VCC = 13 V; VSENSE = 5 V fault condition 7 20 Current sense timings (current sense mode - see Figure 7: "CurrentSense timings (current sense mode)") tDSENSE1H Current sense settling time from rising edge of SEn VIN = 5 V; VSEn = 0 V to 5 V; RSENSE = 1 k; RL = 2.6 tDSENSE1L Current sense disable delay time from falling edge of SEn VIN = 5 V; VSEn = 5 V to 0 V; RSENSE = 1 k; RL = 2.6 tDSENSE2H Current sense settling time from rising edge of INPUT VIN = 0 V to 5 V; VSEn = 5 V; RSENSE = 1 k; RL = 2.6 Current sense settling time from rising edge of IOUT (dynamic response to a step change of IOUT) VIN = 5 V; VSEn = 5 V; RSENSE = 1 k; ISENSE = 90 % of ISENSEMAX; RL = 2.6 tDSENSE2H 12/42 DocID027771 Rev 4 60 s 5 20 s 100 350 s 150 s VN7008AJ Electrical specification Symbol Parameter Test conditions Min. Typ. Max. Unit 7 V < VCC < 18 V; -40C < Tj < 150C Current sense turn-off delay VIN = 5 V to 0 V; VSEn = 5 V; time from falling edge of INPUT RSENSE = 1 k; RL = 2.6 tDSENSE2L 50 250 s Notes: (1)All values refer to VCC = 13 V; Tj = 25C, unless otherwise specified. (2)Parameter specified by design; not subject to production test. Figure 4: IOUT/ISENSE versus IOUT 10000 9000 Max Min 8000 Typ 7000 K-factor 6000 5000 4000 3000 2000 1000 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 IOUT [A] GAPG1802161551CFT Figure 5: Current sense accuracy versus IOUT 65 60 55 50 45 40 % 35 Current sense uncalibrated precision 30 Current sense calibrated precision 25 20 15 10 5 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 IOUT [A] GAPG1802161558CFT DocID027771 Rev 4 13/42 Electrical specification VN7008AJ Figure 6: Switching times and Pulse skew twon VOUT twoff Vcc 80% Vcc ON OFF dVOUT/dt dVOUT/dt 20% Vcc t INPUT td(off) td(on) tpLH tpHL t GAPG2609141134CFT Figure 7: CurrentSense timings (current sense mode) 14/42 DocID027771 Rev 4 VN7008AJ Electrical specification Figure 8: TDSTKON VINPU T VOU T VOU T > VOL MultiSense TDSTKON GAPG2609141140CFT Table 10: Truth table Mode Stand by Conditions All logic inputs low Nominal load connected; Tj < 150 C Normal Overload Overload or short to GND causing: Tj > TTSD or Tj > Tj_SD INX FR SEn OUTX CurrentSense L L L X H L L L See H (1) H H H L X L H L H H See (1) H X X X L L OFF-state diagnostics Short to VCC L X See H Negative output Inductive loads turn-off voltage X L X See (1) (1) See (1) H <0V Outputs configured for auto-restart Outputs configured for Latch-off See (1) L VCC < VUSD (falling) L Low quiescent current consumption L Undervoltage Open-load Hi-Z Comments Output cycles with temperature hysteresis Output latches-off Hi-Z Hi-Z See (1) Re-start when VCC > VUSD + VUSDhyst (rising) External pull-up See (1) Notes: (1)Refer to Table 11: "CurrentSense multiplexer addressing" DocID027771 Rev 4 15/42 Electrical specification VN7008AJ Table 11: CurrentSense multiplexer addressing CS output SEn MUX channel Nomal mode Overload L H OFF-state diag. (1)(2)(3) Negative output Hi-Z Output diagnostic ISENSE = 1/K * IOUT VSENSE = VSENSEH VSENSE = VSENSEH Hi-Z Notes: (1)Example 2: FR = 1; IN = 0; OUT = latched, VOUT > VOL; MUX channel = channel 0 diagnostic; CS = VSENSEH (2)Example 1: FR = 1; IN = 0; OUT = L (latched); MUX channel = channel 0 diagnostic; CS = 0 (3)In case the output channel corresponding to the selected MUX channel is latched off while the relevant input is low, CS pin delivers feedback according to OFF-State diagnostic. 2.4 Waveforms Figure 9: Latch functionality - behavior in hard short circuit condition (TAMB << TTSD) 16/42 DocID027771 Rev 4 VN7008AJ Electrical specification Figure 10: Latch functionality - behavior in hard short circuit condition Figure 11: Latch functionality - behavior in hard short circuit condition (autorestart mode + latch off) DocID027771 Rev 4 17/42 Electrical specification VN7008AJ Figure 12: Standby mode activation Figure 13: Standby state diagram 18/42 DocID027771 Rev 4 VN7008AJ 2.5 Electrical specification Electrical characteristics curves Figure 14: OFF-state output current Figure 15: Standby current ISTBY [A] Iloff [nA] 1.8 250 0 1.6 Vcc = 13V 200 0 1.4 1.2 Off State Vcc = 13V Vin = Vou t = 0 150 0 1 0.8 100 0 0.6 0.4 500 0.2 0 0 -50 -25 0 25 50 75 100 125 150 -50 175 -25 0 25 50 75 100 125 150 175 T [C] T [C] GAPG2202160912CFT Figure 16: IGND(ON) vs Tcase GAPG2202160917CFT Figure 17: Logic Input high level voltage ViH, VFRH , VSE LH, VSE nH [V] IGND (ON) [mA] 3.5 2 1.8 3.0 1.6 2.5 1.4 Vcc = 13V Iou t = 5A 2.0 1.2 1 1.5 0.8 0.6 1.0 0.4 0.5 0.2 0 0.0 -50 -25 0 25 50 75 100 125 150 -50 175 -25 0 25 50 75 100 125 150 175 T [C] T [C] GAPG2202160918CFT GAPG22021609192CFT Figure 18: Logic Input low level voltage Figure 19: High level logic input current IiH, IFRH , ISE LH, ISE nH [A] VilL VFRL, VSE LL, VSE nL [V] 4 2 1.8 3.5 1.6 3 1.4 2.5 1.2 2 1 0.8 1.5 0.6 1 0.4 0.5 0.2 0 0 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175 T [C] T [C] GAPG2202160920CFT DocID027771 Rev 4 GAPG2202160921CFT 19/42 Electrical specification VN7008AJ Figure 20: Low level logic input current Figure 21: Logic Input hysteresis voltage Vi(hyst), VFR(hyst), VSE L(hyst), VSE n(hyst) [V] IiL, IFRL, ISE LL, ISE nL [A] 1 4 0.9 3.5 0.8 3 0.7 2.5 0.6 2 0.5 0.4 1.5 0.3 1 0.2 0.5 0.1 0 0 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 T [C] 75 100 125 150 175 T [C] GAPG2202160922CFT GAPG220216023CFT Figure 22: FaultRST Input clamp voltage Figure 23: Undervoltage shutdown VUSD [V] VFRC L [V] 8 8 7 7 6 6 Iin = 1mA 5 5 4 4 3 3 2 2 1 Iin = -1mA 1 0 0 -1 -50 -25 0 25 50 75 100 125 150 -50 175 -25 0 25 50 75 100 125 150 175 T [C] T [C] GAPG2202160924CFT GAPG2202160925CFT Figure 24: On-state resistance vs Tcase Figure 25: On-state resistance vs VCC Ron [mOhm] Ron [mOhm] 20 50 45 40 T = 150 C 15 35 T = 125 C Iou t = 5A Vcc = 13V 30 10 25 T = 25 C 20 T = -40 C 15 5 10 5 0 0 -50 -25 0 25 50 75 100 125 150 175 GAPG2202160926CFT 20/42 0 5 10 15 20 25 30 35 40 Vcc [V] T [C] DocID027771 Rev 4 GAPG2202160927CFT VN7008AJ Electrical specification Figure 26: Turn-on voltage slope Figure 27: Turn-off voltage slope (dVou t/dt)On [V/s] (dVou t/dt)Off [V/s] 1 1 0.9 0.9 0.8 0.8 Vcc = 13V Rl = 2.6 0.7 Vcc = 13V Rl = 2.6 0.7 0.6 0.6 0.5 0.5 0.4 0.4 0.3 0.3 0.2 0.2 0.1 0.1 0 0 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 T [C] 75 100 125 150 175 T [C] GAPG2202160928CFT GAPG2202160929CFT Figure 28: Won vs Tcase Figure 29: Woff vs Tcase Woff [mJ] Won [mJ] 1 1.5 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -50 -25 0 25 50 75 100 125 150 -50 175 -25 0 25 50 75 100 125 150 175 T [C] T [C] GAPG2202160930CFT GAPG2202160931CFT Figure 31: OFF-state open-load voltage detection threshold Figure 30: ILIMH vs. Tcase Ilimh [A] VOL [V] 120 4 11 5 3.5 11 0 3 105 2.5 100 2 Vcc = 13V 95 1.5 90 1 85 0.5 80 -50 -25 0 25 50 75 100 125 150 175 0 -50 T [C] GAPG2202160932CFT DocID027771 Rev 4 -25 0 25 50 75 100 125 150 175 T [C] GAPG2202160935CFT 21/42 Electrical specification VN7008AJ Figure 32: Vsense clamp vs. Tcase Figure 33: Vsenseh vs. Tcase VSE NSE _CL [V] VSE NSE H [V] 10 10 9 9 8 8 7 7 6 Iin = 1mA 6 5 5 4 4 3 3 2 2 1 Iin = -1mA 1 0 0 -1 -50 -25 0 25 50 75 100 125 150 175 -50 GAPG2202160938CFT 22/42 -25 0 25 50 75 T [C] T [C] DocID027771 Rev 4 100 125 150 175 VN7008AJ Protections 3 Protections 3.1 Power limitation The basic working principle of this protection consists of an indirect measurement of the junction temperature swing Tj through the direct measurement of the spatial temperature gradient on the device surface in order to automatically shut off the output MOSFET as soon as Tj exceeds the safety level of Tj_SD. According to the voltage level on the FaultRST pin, the output MOSFET switches on and cycles with a thermal hysteresis according to the maximum instantaneous power which can be handled (FaultRST = Low) or remains off (FaultRST = High). The protection prevents fast thermal transient effects and, consequently, reduces thermo-mechanical fatigue. 3.2 Thermal shutdown In case the junction temperature of the device exceeds the maximum allowed threshold (typically 175C), it automatically switches off and the diagnostic indication is triggered. According to the voltage level on the FaultRST pin, the device switches on again as soon as its junction temperature drops to TR (FaultRST = Low) or remains off (FaultRST = High). 3.3 Current limitation The device is equipped with an output current limiter in order to protect the silicon as well as the other components of the system (e.g. bonding wires, wiring harness, connectors, loads, etc.) from excessive current flow. Consequently, in case of short circuit, overload or during load power-up, the output current is clamped to a safety level, ILIMH, by operating the output power MOSFET in the active region. 3.4 Negative voltage clamp In case the device drives inductive load, the output voltage reaches a negative value during turn off. A negative voltage clamp structure limits the maximum negative voltage to a certain value, VDEMAG, allowing the inductor energy to be dissipated without damaging the device. DocID027771 Rev 4 23/42 Application information 4 VN7008AJ Application information Figure 34: Application diagram +5V VDD OUT VCC Rprot OUT FaultRST INPUT Rprot OUT Logic OUT Dld Rprot SEn Rprot SEL OUTPUT Rprot ADC in CS Current mirror GND Cext Rsense OUT R GND GND D GND GND GND GND GND GND GAPGCFT00829 4.1 GND protection network against reverse battery Figure 35: Simplified internal structure 5V Vcc Rprot INPUT Rprot SEn Rprot FaultRST MCU Dld OUTPUT Rprot CS GND Rsense D GND R GND GND 24/42 DocID027771 Rev 4 GAPGCFT00830 VN7008AJ 4.1.1 Application information Diode (DGND) in the ground line A resistor (typ. RGND = 4.7 k) should be inserted in parallel to DGND if the device drives an inductive load. This small signal diode can be safely shared amongst several different HSDs. Also in this case, the presence of the ground network produces a shift (600 mV) in the input threshold and in the status output values if the microprocessor ground is not common to the device ground. This shift does not vary if more than one HSD shares the same diode/resistor network. 4.2 Immunity against transient electrical disturbances The immunity of the device against transient electrical emissions, conducted along the supply lines and injected into the VCC pin, is tested in accordance with ISO7637-2:2011 (E) and ISO 16750-2:2010. The related function performance status classification is shown in Table 12: "ISO 7637-2 electrical transient conduction along supply line". Test pulses are applied directly to DUT (Device Under Test) both in ON and OFF-state and in accordance to ISO 7637-2:2011(E), chapter 4. The DUT is intended as the present device only, without components and accessed through VCC and GND terminals. Status II is defined in ISO 7637-1 Function Performance Status Classification (FPSC) as follows: "The function does not perform as designed during the test but returns automatically to normal operation after the test". Table 12: ISO 7637-2 - electrical transient conduction along supply line Test Pulse 2011(E) Test pulse severity level with Status II functional performance status Minimum number of pulses or test time Burst cycle / pulse repetition time Pulse duration and pulse generator internal impedance Level US(1) 1 III -112V 500 pulses 0,5 s 2a III +55V 500 pulses 0,2 s 5s 50s, 2 3a IV -220V 1h 90 ms 100 ms 0.1s, 50 3b IV +150V 1h 90 ms 100 ms 0.1s, 50 IV -7V 1 pulse 4 (2) min max 2ms, 10 100ms, 0.01 Load dump according to ISO 16750-2:2010 Test B (3) 40V 5 pulse 1 min 400ms, 2 Notes: (1)U S 4.3 is the peak amplitude as defined for each test pulse in ISO 7637-2:2011(E), chapter 5.6. (2)Test pulse from ISO 7637-2:2004(E). (3)With 40 V external suppressor referred to ground (-40C < Tj < 150C). MCU I/Os protection If a ground protection network is used and negative transients are present on the VCC line, the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line both to prevent the microcontroller I/O pins from latching-up and to protect the HSD inputs. DocID027771 Rev 4 25/42 Application information VN7008AJ The value of these resistors is a compromise between the leakage current of microcontroller and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of microcontroller I/Os. Equation VCCpeak/Ilatchup Rprot (VOHC - VIH - VGND) / IIHmax Calculation example: For VCCpeak = -150 V; Ilatchup 20 mA; VOHC 4.5 V 7.5 k Rprot 140 k. Recommended values: Rprot = 15 k 4.4 CS - analog current sense Diagnostic information on device and load status are provided by an analog output pin (CS) delivering the following signals: * Current monitor: current mirror of channel output current Those signals are routed through an analog multiplexer which is configured and controlled by means of SELx and SEn pins, according to the address map in MultiSense multiplexer addressing Table. VCC Figure 36: CurrectSense and diagnostic - block diagram Internal Supply VCC - GND Clamp Undervoltage shut-down Control & Diagnostic VCC - OUT Clamp FaultRST INPUT Gate Driver T SEL1 SEL0 VON Limitation SEn Current Limitation ISE NSE CS Fault Diagnostic MUX RPROT Power Limitation Overtemperature Short to VCC Open-Load in OFF To uC ADC K factor RSENSE Current Sense CURRENT MONITOR Fault IOUT OUT VSE NSE H GND GAPGCFT00831 26/42 DocID027771 Rev 4 VN7008AJ 4.4.1 Application information Principle of CurrentSense signal generation Figure 37: CurrentSense block diagram Current sense This current mode is selected in the MultiSense, this output is capable to provide: * * Current mirror proportional to the load current in normal operation, delivering current proportional to the load according to known ratio named K Diagnostics flag in fault conditions delivering fixed voltage VSENSEH The current delivered by the current sense circuit, ISENSE, can be easily converted to a voltage VSENSE by using an external sense resistor, RSENSE, allowing continuous load monitoring and abnormal condition detection. Normal operation (channel ON, no fault, SEn active) While device is operating in normal conditions (no fault intervention), VSENSE calculation can be done using simple equations Current provided by CS output: ISENSE = IOUT/K Voltage on RSENSE: VSENSE = RSENSE * ISENSE = RSENSE * IOUT/K Where: * * VSENSE is voltage measurable on RSENSE resistor ISENSE is current provided from CS pin in current output mode DocID027771 Rev 4 27/42 Application information * * VN7008AJ IOUT is current flowing through output K factor represents the ratio between PowerMOS cells and SenseMOS cells; its spread includes geometric factor spread, current sense amplifier offset and process parameters spread of the overall circuitry the specifying ratio between IOUT and ISENSE. Failure flag indication In case of power limitation/overtemperature, the fault is indicated by the CS pin which is switched to a "current limited" voltage source, VSENSEH. In any case, the current sourced by the CS in this condition is limited to ISENSEH. The typical behavior in case of overload or hard short circuit is shown in Waveforms section. Figure 38: Analogue HSD - open-load detection in off-state +5V Vbat Vbat 100nF/50V 100nF Rpull-up GND GND Microcontroller VCC VDD FaultRST OUT 15k INPUT External Pull -Up switch OUT Logic 15k SEn OUT SEL 15k OUTPUT OUTPUT CS OUT Current mirror 15k GND ADC in 15k Rsense RGND 4.7k DGND 10nF/100V OUT 15k CEXT GND GND GND GND GND GND GAPG1201151432CFT 28/42 DocID027771 Rev 4 VN7008AJ Application information Figure 39: Open-load / short to VCC condition Table 13: CurrentSense pin levels in off-state Condition Output VOUT > VOL Open-load VOUT < VOL 4.4.2 Short to VCC VOUT > VOL Nominal VOUT < VOL CS SEn Hi-Z L VSENSEH H Hi-Z L 0 H Hi-Z L VSENSEH H Hi-Z L 0 H Short to VCC and OFF-state open-load detection Short to VCC A short circuit between VCC and output is indicated by the relevant current sense pin set to VSENSEH during the device off-state. Small or no current is delivered by the current sense during the on-state depending on the nature of the short circuit. OFF-state open-load with external circuitry Detection of an open-load in off mode requires an external pull-up resistor RPU connecting the output to a positive supply voltage VPU. It is preferable that VPU is switched off during the module standby mode in order to avoid the overall standby current consumption to increase in normal conditions, i.e. when load is connected. DocID027771 Rev 4 29/42 Application information VN7008AJ RPU must be selected in order to ensure VOUT > VOLmax in accordance with the following equation: Equation RPU < 30/42 VPU - 4 IL(off2)min @ 4V DocID027771 Rev 4 VN7008AJ Package and PCB thermal data 5 Package and PCB thermal data 5.1 PowerSSO-16 thermal data Figure 40: PowerSSO-16 on two-layers PCB (2s0p to JEDEC JESD 51-5) Figure 41: PowerSSO-16 on four-layers PCB (2s2p to JEDEC JESD 51-7) Table 14: PCB properties Dimension Value Board finish thickness 1.6 mm +/- 10% Board dimension 77 mm x 86 mm Board Material FR4 Copper thickness (top and bottom layers) 0.070 mm Copper thickness (inner layers) 0.035 mm Thermal vias separation 1.2 mm Thermal via diameter 0.3 mm +/- 0.08 mm Copper thickness on vias 0.025 mm Footprint dimension (top layer) 2.2 mm x 3.9 mm Heatsink copper area dimension (bottom layer) DocID027771 Rev 4 Footprint, 2 cm2 or 8 cm2 31/42 Package and PCB thermal data VN7008AJ Figure 42: Rthj-amb vs PCB copper area in open box free air conditions RTHjamb 90 RTHjamb 80 70 60 50 40 30 0 2 4 6 8 10 RTHj_amb on 4Layer PCB: 20.3C/W GAPG1307151110CFT Figure 43: PowerSSO-16 thermal impedance junction ambient single pulse ZTH (C/W) 100 10 1 0.1 0.01 0.0001 Cu=foot print Cu=2 cm2 Cu=8 cm2 4 Layer 0.001 0.01 0.1 1 Time (s) 10 100 1000 GAPG1307151113CFT Equation: pulse calculation formula ZTH = RTH * + ZTHtp (1 - ) where = tP/T 32/42 DocID027771 Rev 4 VN7008AJ Package and PCB thermal data Figure 44: Thermal fitting model for PowerSSO-16 The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cycling during thermal shutdown) are not triggered. Table 15: Thermal parameters Area/island (cm2) FP 2 8 4L R1 (C/W) 0.3 R2 (C/W) 1 R3 (C/W) 7 7 7 5 R4 (C/W) 16 6 6 4 R5 (C/W) 30 20 10 3 R6 (C/W) 26 20 18 7 C1 (W*s/C) 0.0023 C2 (W*s/C) 0.021 C3 (W*s/C) 0.12 C4 (W*s/C) 0.2 0.3 0.3 0.4 C5 (W*s/C) 0.4 1 1 4 C6 (W*s/C) 3 5 7 18 DocID027771 Rev 4 33/42 Maximum demagnetization energy (VCC = 16 V) 6 VN7008AJ Maximum demagnetization energy (VCC = 16 V) Figure 45: Maximum turn off current versus inductance VN7008AJ - Maximum turn off current versus inductance I (A) 100 10 VN7008AJ - Single Pulse Repetitive pulse Tjstart=100C Repetitive pulse Tjstart=125C 1 0.1 1 10 100 1000 L (mH) VN7008 AJ - Maximum turn off Energy versus Tdemag 10000 VN7008AJ - Single Pulse 1000 Repetitive pulse Tjstart=100C E [mJ] Repetitive pulse Tjstart=125C 100 10 1 0.01 0.1 1 10 100 Tdemag [s] GAPG1503161313CFT Values are generated with RL = 0 . In case of repetitive pulses, Tjstart (at the beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves A and B. 34/42 DocID027771 Rev 4 VN7008AJ 7 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. 7.1 PowerSSO-16 package information Figure 46: PowerSSO-16 package dimensions Table 16: PowerSSO-16 mechanical data Millimeters Symbol Min. Typ. Max. 0 1 0 2 5 15 3 5 15 A 8 1.70 A1 0.00 0.10 A2 1.10 1.60 DocID027771 Rev 4 35/42 Package information VN7008AJ Millimeters Symbol Min. b 0.20 b1 0.20 c 0.19 c1 0.19 D D1 Typ. 0.30 0.25 0.28 0.25 0.20 0.23 4.9 BSC 3.60 4.20 e 0.50 BSC E 6.00 BSC E1 3.90 BSC E2 1.90 2.50 h 0.25 0.50 L 0.40 0.60 L1 1.00 REF N 16 R 0.07 R1 0.07 S 0.20 Tolerance of form and position aaa 36/42 Max. 0.10 bbb 0.10 ccc 0.08 ddd 0.08 eee 0.10 fff 0.10 ggg 0.15 DocID027771 Rev 4 0.85 VN7008AJ 7.2 Package information PowerSSO-16 packing information Figure 47: PowerSSO-16 reel 13" Table 17: Reel dimensions Description Value(1) Base quantity 2500 Bulk quantity 2500 A (max) 330 B (min) 1.5 C (+0.5, -0.2) 13 D (min) 20.2 N 100 W1 (+2 /-0) 12.4 W2 (max) 18.4 Notes: (1)All dimensions are in mm. DocID027771 Rev 4 37/42 Package information VN7008AJ Figure 48: PowerSSO-16 carrier tape P0 4.0 0.1 X 1.55 0.05 0.30 0.05 P2 2.0 0.1 1.75 0.1 B0 W F 1.60.1 Y R 0.5 Typical K1 Y X K0 P1 A0 REF 4.18 REF 0.6 SECTION X - X REF 0.5 SECTION Y - Y GAPG2204151242CFT Table 18: PowerSSO-16 carrier tape dimensions Description Value(1) A0 6.50 0.1 B0 5.25 0.1 K0 2.10 0.1 K1 1.80 0.1 F 5.50 0.1 P1 8.00 0.1 W 12.00 0.3 Notes: (1)All dimensions are in mm. Figure 49: PowerSSO-16 schematic drawing of leader and trailer tape 38/42 DocID027771 Rev 4 VN7008AJ 7.3 Package information PowerSSO-16 marking information Figure 50: PowerSSO-16 marking information Marking area 1 2 3 4 5 6 7 8 Special function digit &: Engineering sample <blank>: Commercial sample PowerSSO-16 TOP VIEW (not in scale) GAPG0401151415CFT Engineering Samples: these samples can be clearly identified by a dedicated special symbol in the marking of each unit. These samples are intended to be used for electrical compatibility evaluation only; usage for any other purpose may be agreed only upon written authorization by ST. ST is not liable for any customer usage in production and/or in reliability qualification trials. Commercial Samples: fully qualified parts from ST standard production with no usage restrictions. DocID027771 Rev 4 39/42 Order codes 8 VN7008AJ Order codes Table 19: Device summary Order codes Package Tape and reel PowerSSO-16 40/42 VN7008AJTR DocID027771 Rev 4 VN7008AJ 9 Revision history Revision history Table 20: Document revision history Date Revision 23-Apr-2015 1 Initial release 2 Updated Table 4: "Thermal data" Table 6: "Switching": * WON, W OFF, tSKEW: updated values Table 7: "Logic Inputs": * VICL, VFRCL, VSEnCL: updated maximum value Table 9: "CurrentSense": * Kx, tDSENSE2H, tDSENSE2H: updated values Updated Section 5.1: "PowerSSO-16 thermal data" 13-Jul-2015 Changes Table 3: "Absolute maximum ratings": * EMAX: updated value Table 6: "Switching": * td(on), td(off), W ON, W OFF, tSKEW: updated values Table 9: "CurrentSense": 22-Feb-2016 3 * K0, K1: updated values Added Figure 4: "IOUT/ISENSE versus IOUT" and Figure 5: "Current sense accuracy versus IOUT" Added Section 2.5: "Electrical characteristics curves" and Section 4: "Application information" Updated Section 5.1: "PowerSSO-16 thermal data" 15-Mar-2016 4 Added Section 6: "Maximum demagnetization energy (VCC = 16 V)" DocID027771 Rev 4 41/42 VN7008AJ IMPORTANT NOTICE - PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST's terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers' products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. (c) 2016 STMicroelectronics - All rights reserved 42/42 DocID027771 Rev 4