VN7008AJ
High-side driver with CurrentSense analog feedback for
automotive applications
Datasheet - product ion data
Features
Max transient supply voltage VCC 40 V
Operating voltage range VCC 4 to 28 V
Typ. on-state resistance (per Ch) RON 8.5 mΩ
Current limitation (typ) ILIMH 96 A
Standby current (max) ISTBY 0.5 µA
• Automotive qualified
• General
− Single channel smart high side driver
with CS analog feedback
− Very low standby current
− Compatible with 3 V and 5 V CMOS
outputs
• CS diagnostic functions
− Analog feedback of: load current with
high precis ion prop or tio na l cur rent
mirror
− Overload and short to ground (power
limitation) indication
− Thermal shutdown indication
− OFF-state open-load detection
− Output short to VCC detection
− Sense enable/ disable
• Protections
− Undervoltage shutdown
− Overvoltage clamp
− Load current limitation
− Self limiting of fast thermal transients
− Configurable latch-off on
overtemperature or power limitation
with dedicated fault reset pin
− Loss of ground and loss of VCC
− Reverse battery with external
components
− Electrostatic discharge protection
Applications
• All types of Automotive resistive, inductive
and capacitive loads
• Specially intended for Automotive
Headlamps
Description
The device is a single channel high-side driver
manufactured using ST proprietary VIPower®
technology and housed in Power SSO -16
package. The device is designed to drive 12 V
automotive grounded loads through a 3 V and
5 V CMOS-compatible interface, and to provide
protection and diagnostics.
The device integrates advanced protective
functions such as load current limitation, overload
active management by power limitati on and
overtemperature shutdown with configurable
latch-off.
A FaultRST pin unlatches the output in case of
fault or disables the latch-off functionality.
A sense enable pin allows OFF-state diagnosis to
be disabled during the module low-power mode
as well as external sense resistor sharing among
similar devices.
March 2016 DocID027771 Rev 4 1/42
This is information on a product in full production. www.st.com
Contents
VN7008AJ
Contents
1 Block diagram and pin des cr iption ................................................ 5
2 Electrical specification .................................................................... 7
2.1 Absolute maxi mu m rati ngs ................................................................ 7
2.2 Thermal dat a ..................................................................................... 8
2.3 Main electrical characteristics ........................................................... 8
2.4 Waveforms ...................................................................................... 16
2.5 Electrical characteristics curves ...................................................... 19
3 Protections..................................................................................... 23
3.1 Power limitation ............................................................................... 23
3.2 Thermal shutdown ........................................................................... 23
3.3 Current limitation ............................................................................. 23
3.4 Negative voltage clamp ................................................................... 23
4 Application information ................................................................ 24
4.1 GND protection network against reverse battery ............................. 24
4.1.1 Diode (DGND) in the ground line ..................................................... 25
4.2 Immunity against transient electrical disturbances .......................... 25
4.3 MCU I/Os protection ........................................................................ 25
4.4 CS - analog current sense .............................................................. 26
4.4.1 Principle of CurrentSense signal generation .................................... 27
4.4.2 Short to VCC and OFF-state open-l oad det ec tio n ........................... 29
5 Package and PCB thermal data .................................................... 31
5.1 PowerSSO-16 thermal data ............................................................ 31
6 Maximum demagnetiza t ion energy (VCC = 16 V) ........................ 34
7 Package information ..................................................................... 35
7.1 PowerSSO-16 package information ................................................ 35
7.2 PowerSSO-16 packing information ................................................. 37
7.3 PowerSSO-16 marki ng in format ion ................................................. 39
8 Order c ode s ................................................................................... 40
9 Revision history ............................................................................ 41
2/42 DocID027771 Rev 4
VN7008AJ
List of tables
List of tables
Table 1: Pin functions ................................................................................................................................. 5
Table 2: Suggested connections for unused and not connected pins ........................................................ 6
Table 3: Absolute maximum ratings ........................................................................................................... 7
Table 4: Thermal data ................................................................................................................................. 8
Table 5: Power section ............................................................................................................................... 8
Table 6: Switching ....................................................................................................................................... 9
Table 7: Logic Inputs................................................................................................................................. 10
Table 8: Protections .................................................................................................................................. 10
Table 9: CurrentSense .............................................................................................................................. 11
Table 10: Truth table ................................................................................................................................. 15
Table 11: CurrentSense multiplexer addressing ...................................................................................... 16
Table 12: ISO 7637-2 - electrical transient conduction along supply line ................................................. 25
Table 13: CurrentSense pin levels in off-state .......................................................................................... 29
Table 14: PCB properties ......................................................................................................................... 31
Table 15: Thermal parameters ................................................................................................................. 33
Table 16: PowerSSO-16 mechanical data................................................................................................ 35
Table 17: Reel dimensions ....................................................................................................................... 37
Table 18: PowerSSO-16 carrier tape dimensions .................................................................................... 38
Table 19: Device summary ....................................................................................................................... 40
Table 20: Document revision history ........................................................................................................ 41
DocID027771 Rev 4 3/42
List of figur es
VN7008AJ
List of figures
Figure 1: Block diagram .............................................................................................................................. 5
Figure 2: Configuration diagram (top view)................................................................................................. 6
Figure 3: Current and voltage conventions ................................................................................................. 7
Figure 4: IOUT /IS ENS E ver sus IOUT ....................................................................................................... 13
Figure 5: Current sense accuracy versus IOUT ....................................................................................... 13
Figure 6: Switching times and Pulse skew ............................................................................................... 14
Figure 7: CurrentSense timings (current sense mode) ............................................................................. 14
Figure 8: TDSTKON .................................................................................................................................. 15
Figure 9: Latch functionality - behavior in hard short circuit condition (TAMB << TTSD) ........................ 16
Figure 10: Latch func t ion al ity - behavior in hard short circuit condition .................................................... 17
Figure 11: Latch func t ion al ity - behavior in hard short circuit condition (autorestart mode + latch off) .... 17
Figure 12: Standby mode activation ......................................................................................................... 18
Figure 13: Stand b y state di agram ............................................................................................................. 18
Figure 14: OFF-state output current ......................................................................................................... 19
Figure 15: Stand b y current ....................................................................................................................... 19
Figure 16: IGND(ON) vs Tcase ................................................................................................................ 19
Figure 17: Logic Input hi gh le vel volt age .................................................................................................. 19
Figure 18: Logic Input lo w level vo ltag e .................................................................................................... 19
Figure 19: High lev el logic input curre nt ................................................................................................... 19
Figure 20: Low leve l logic input current .................................................................................................... 20
Figure 21: Logic Input h yster es is volt age ................................................................................................. 20
Figure 22: FaultRST Input clamp voltage ................................................................................................. 20
Figure 23: Under vo lta ge shut do wn ........................................................................................................... 20
Figure 24: On-state resistance vs Tcase .................................................................................................. 20
Figure 25: On-state resistance vs VCC .................................................................................................... 20
Figure 26: Turn-on volta ge s lope .............................................................................................................. 21
Figure 27: Turn-off voltage slope .............................................................................................................. 21
Figure 28: Won vs Tcase .......................................................................................................................... 21
Figure 29: Woff vs Tcase .......................................................................................................................... 21
Figure 30: ILIMH vs. Tcase ....................................................................................................................... 21
Figure 31: OFF-state open-load voltage detection threshold ................................................................... 21
Figure 32: Vsense clamp vs. Tcase .......................................................................................................... 22
Figure 33: Vsense h vs . Tc ase .................................................................................................................. 22
Figure 34: Appl icati on dia gram ................................................................................................................. 24
Figure 35: Simplified internal structure ..................................................................................................... 24
Figure 36: CurrectSense and diagnostic – block diagram ........................................................................ 26
Figure 37: CurrentSense block diagram ................................................................................................... 27
Figure 38: Anal ogu e HSD – open-load detect ion in of f -state ................................................................... 28
Figure 39: Open-load / short to VCC condition ......................................................................................... 29
Figure 40: Power S SO-16 on two-layers PCB (2s0p to JEDEC JESD 51-5) ............................................ 31
Figure 41: Power S SO-16 on four-layers PCB (2s2p to JEDEC JESD 51-7) ........................................... 31
Figure 42: Rthj-amb vs PCB copper area in open box free air conditions ............................................... 32
Figure 43: Power S SO-16 thermal impedance junction ambient single pulse .......................................... 32
Figure 44: Thermal fitting model for PowerSSO-16 .................................................................................. 33
Figure 45: Maximum turn off current versus inductance .......................................................................... 34
Figure 46: Power S SO-16 package dimensions ........................................................................................ 35
Figure 47: Power S SO-16 reel 13" ............................................................................................................ 37
Figure 48: Power S SO-16 carrier tape ...................................................................................................... 38
Figure 49: Power S SO-16 schematic drawing of leader and trailer tape .................................................. 38
Figure 50: Power S SO-16 marking information ......................................................................................... 39
4/42 DocID027771 Rev 4
VN7008AJ
Block diagram and pin description
1 Block diagram and pin description
Figure 1: Block diagra m
Table 1: Pin functions
Name Function
VCC Battery connection.
OUTPUT Power outputs. All the pins must be connected together.
GND Ground connection. Must be reverse battery protected by an external diode / resistor
network.
INPUT Voltage controlled input pin with hysteresis, compatible with 3 V and 5 V CMOS outputs.
It controls output switch state.
CS Analog current sense output pin delivers a current proportional to the load current.
SEn
Active high compatible with 3 V and 5 V CMOS outputs pin; it enables the CS diagnostic
pin.
FaultRST Active low compatible with 3 V and 5 V CMOS outputs pin; it unlatches the output in
case of fault; If kept low, sets the outputs in auto-restart mod e.
DocID027771 Rev 4 5/42
Block diagram and pin description
VN7008AJ
Figure 2: Configuration diagram (top view)
Pins 9, 10, 11 and 12 are inter nally connected ; Pins 13 , 14, 15 and 16 are
internally connected; All output pins must be connected together on PCB.
Table 2: Suggested connections for unused and not connected pins
Connection / pin CS N.C. Output Input SEn,
FaultRST
Floating Not allowed X (1) X X X
To ground Through 1 kΩ
resistor X Not allowed Through 15 kΩ
resistor Through 15 kΩ
resistor
Notes:
(1)X: do not care.
6/42 DocID027771 Rev 4
VN7008AJ
Electrical specification
2 Electrical specification
Figure 3: Current and voltage conventions
V
F
= V
OUT
- V
CC
during reverse battery condition.
2.1 Absolute m a xi m um rat ings
Stressing the device above the rating listed in Table 3: "Absolute maximum ratings" may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to the conditions in table below for extended
periods may affect device reliability.
Table 3: A bsolut e maximum rat ings
Symbol
Parameter Value Unit
VCC DC supply voltage 38
V
-VCC Reverse DC supply voltage 0.3
VCCPK Maximum transient supply voltage (ISO 16750-2:2010 Test B
clamped to 40V; RL = 4 Ω) 40
VCCJS Maximum jump start voltage for single pulse short circuit protection 28
-IGND DC reverse ground pin current 200 mA
IOUT OUTPUT DC output current Internally limited
A
-IOUT Reverse DC output current 35
IIN INPUT DC input current
-1 to 10 mA ISEn SEn DC input current
IFR FaultRST DC input current
VFR FaultRST DC input voltage 7.5 V
ISENSE CS pin DC output current (VGND = VCC and VSENSE < 0 V) 10 mA
CS pin DC output current in reverse (VCC < 0V) -20
DocID027771 Rev 4 7/42
Electrical specification
VN7008AJ
Symbol
Parameter Value Unit
EMAX Maximum switching en er gy (single pul se)
(TDEMAG = 0.4 ms; Tjstart = 150 °C) 170 mJ
VESD
Electrostatic discharge (JEDEC 22A-114F)
• INPUT
• CS
• SEn, FaultRST
• OUTPUT
• VCC
4000
2000
4000
4000
4000
V
V
V
V
V
VESD Charge device model (CDM-AEC-Q100-011) 750 V
Tj Junction operating temperature -40 to 150 °C
Tstg Storage temperat ure -55 to 150
2.2 Thermal da t a
Table 4: Thermal data
Symbol Parameter Typ. value Unit
Rthj-board T hermal resi stan ce jun cti on-board (JEDEC JESD 51-5 / 51-8)(1) 3.85
°C/W
Rthj-amb Thermal resistan ce jun cti on-ambient (JEDEC JESD 51-5)(2) 54.8
Rthj-amb Thermal resistan ce jun cti on-ambient (JEDEC JESD 51-7)(1) 21
Notes:
(1)Device mounted on four-layers 2s2p PCB.
(2)Device mounted on two-layers 2s0p PCB with 2 cm2 heatsink copper trace.
2.3 Main electrical characteristics
7 V < VCC < 18 V; -40 °C < Tj < 150 °C, unless otherwise specified.
All typical values refer to VCC = 13 V; Tj = 25°C, unless otherwise specified.
Table 5: Power section
Symbol Parameter Test conditions Min. Typ. Max. Unit
VCC Operating supply voltage
4 13 28
V
VUSD Undervoltage shut dow n
4
VUSDReset Undervoltage shutdow n reset
5
VUSDhyst Undervolta ge shut down
hysteresis
0.3
RON On-state resistance
IOUT = 5 A; Tj = 25 °C
8.5
mΩ
IOUT = 5 A; Tj = 150 °C
17
IOUT = 5 A; VCC = 4 V;
Tj = 25 °C
12.75
Vclamp Clamp voltage IS = 20 mA; Tj = -40°C 38
V
IS = 20 mA; 25°C < Tj < 150°C
41 46 52
8/42 DocID027771 Rev 4
VN7008AJ
Electrical specification
Symbol Parameter Test conditions Min. Typ. Max. Unit
ISTBY Supply current in standby at
VCC = 13 V (1)
VCC = 13 V;
VIN = VOUT = VFR = VSEn = 0 V;
Tj = 25 °C 0.5 µA
VCC = 13 V;
VIN = VOUT = VFR = VSEn = 0 V;
Tj = 85 °C (2) 0.5 µA
VCC = 13 V;
VIN = VOUT = VFR = VSEn = 0 V;
Tj = 125 °C 3 µA
tD_STBY Standby mode blanking time VCC = 13 V; VIN = 5 V;
VSEn = VFR = 0 V; IOUT = 0 A 60 300 550 µs
IS(ON) Supply current VCC = 13 V; VSEn = VFR = 0 V;
VIN = 5 V; IOUT = 0 A
3 5 mA
IGND(ON) Control stage curren t
consumption in ON state. All
channels active.
VCC = 13 V; VSEn = 5 V;
VFR = 0 V; VIN = 5 V;
IOUT = 5 A 6 mA
IL(off) Off-state output current at
VCC = 13 V
VIN = VOUT = 0 V; VCC = 13 V;
Tj = 25 °C 0 0.01 0.5 µA
VIN = VOUT = 0 V; VCC = 13 V;
Tj = 125 °C 0
3
VF Output - VCC diode voltage IOUT = -5 A; Tj = 150 °C
0.7 V
Notes:
(1)PowerMOS leakage included.
(2)Parameter specified by design; not subject to production t est.
Table 6: Switchin g
Symbol Parameter Test conditions Min. Typ.
Max. Unit
VCC = 13 V; -40°C < Tj < 150°C, unless otherwise specified
td(on)(1) Turn-on delay time at Tj = 25°C RL = 2.6 Ω 10 45 120 µs
td(off)(1) Turn-off delay time at Tj = 25°C 10 48 100
(dVOUT/dt)on(1) Turn-on voltage slope at Tj = 25°C RL = 2.6 Ω 0.1 0.2 0.7 V/µs
(dVOUT/dt)off(1) Turn-off voltage slope at Tj = 25°C 0.1 0.3 0.7
WON Switching energy losses at turn-on (twon) RL = 2.6 Ω — 0.8 1.2(2) mJ
WOFF Switching energy losses at turn-off (twoff) RL = 2.6 Ω — 0.6 1(2) mJ
tSKEW(1) Differential Pulse skew (tPHL - tPLH) RL = 2.6 Ω -65 -15 35 µs
Notes:
(1)See Figure 6: "Swit ch ing tim es and Pulse skew ".
(2)Parameter guaranteed by design and characterizati on; not subj ect to product i on test.
DocID027771 Rev 4 9/42
Electrical specification
VN7008AJ
Table 7: Logic Inputs
Symbol Parameter Test conditions Min. Typ. Max. Unit
7 V < VCC < 28 V; -40°C < Tj < 150°C
INPUT characteristics
VIL Input low level voltage
0.9 V
IIL Low level input current VIN = 0.9 V 1
µA
VIH Input high level voltage
2.1
V
IIH High level input current VIN = 2.1 V
10 µA
VI(hyst) Input hystere si s voltage
0.2
V
VICL Input clamp voltag e IIN = 1 mA 5.3
7.5 V
IIN = -1 mA
-0.7
FaultRST characteristics
VFRL Input low level voltage
0.9 V
IFRL Low level input current VIN = 0.9 V 1
µA
VFRH Input high level voltage
2.1
V
IFRH High level input current VIN = 2.1 V
10 µA
VFR(hyst) Input hysteresi s volta ge
0.2
V
VFRCL Input clamp voltage IIN = 1 mA 5.3
7.2 V
IIN = -1 mA
-0.7
SEn characteristics (7 V < VCC < 18 V)
VSEnL Input low level voltage
0.9 V
ISEnL Low level input current VIN = 0.9 V 1
µA
VSEnH Input high level voltage
2.1
V
ISEnH High level input current VIN = 2.1 V
10 µA
VSEn(hyst) Input hysteresi s voltage
0.2
V
VSEnCL Input clamp voltage IIN = 1 mA 5.3
7.5 V
IIN = -1 mA
-0.7
Table 8: Protections
Symbol Parameter Test conditions Min. Typ. Max. Unit
7 V < VCC < 18 V; -40°C < Tj < 150°C
ILIMH DC short circuit current VCC = 13 V 70 98 140
A
4 V < VCC < 18 V (1)
140
ILIML Short circuit current
during thermal cycling VCC = 13 V;
TR < Tj < TTSD
33
TTSD Shutdown temperature
150 175 200
°C
TR Reset temperature(1)
TRS + 1 TRS + 7
TRS Thermal reset of fault
diagnostic ind ica tio n VFR = 0 V; VSEn = 5 V; 135
THYST Thermal hysteresis
(TTSD - TR)(1)
7
10/42 DocID027771 Rev 4
VN7008AJ
Electrical specification
Symbol Parameter Test conditions Min. Typ. Max. Unit
7 V < VCC < 18 V; -40°C < Tj < 150°C
ΔTJ_SD Dynamic temperature Tj = -40 °C; VCC = 13 V
60
K
tLATCH_RST
Fault reset time for output
unlatch(1) VFR = 5 V to 0 V;
VSEn = 5 V; VIN = 5 V 3 10 20 µs
VDEMAG Turn-off output voltage
clamp
IOUT = 2 A; L = 6 mH;
Tj = -40 °C VCC - 38
V
IOUT = 2 A; L = 6 mH;
Tj = 25 °C to 150 °C VCC - 41 VCC - 46 VCC - 52
V
VON Output volt age drop
limitation IOUT = 0.25 A
20
mV
Notes:
(1)Parameter guaranteed by design and characterizati on; not subj ect to product i on test.
Table 9: Curr entS ense
Symbol Parameter Test conditions Min.
Typ. Max.
Unit
7 V < VCC < 18 V; -40°C < Tj < 150°C
VSENSE_CL Current sense cla mp volt age VSEn = 0 V; ISENSE = 1 mA -17
-12 V
VSEn = 0 V; ISENSE = -1 mA
7
V
Current Sense characteristics
K0 IOUT/ISENSE IOUT = 0.9 A; VSENSE = 0.5 V;
VSEn = 5 V 3465
6150
9135
dK0/K0(1)(2) Current sense ratio drif t IOUT = 0.9 A; VSENSE = 0.5 V;
VSEn = 5 V -20
20 %
K1 IOUT/ISENSE IOUT = 1.5 A; VSENSE = 4 V;
VSEn = 5 V 3735
5990
8725
dK1/K1(2)(1) Current sense ratio drif t IOUT = 1.5 A; VSENSE = 4 V;
VSEn = 5 V -15
15 %
K2 IOUT/ISENSE IOUT = 6 A; VSENSE = 4 V;
VSEn = 5 V 4410
5890
7360
dK2/K2(2)(1) Current sense ratio drif t IOUT = 6 A; VSENSE = 4 V;
VSEn = 5 V -10
+10 %
K3 IOUT/ISENSE IOUT = 18 A; VSENSE = 4 V;
VSEn = 5 V 5290
5880
6470
dK3/K3(2)(1) Current sense ratio drift IOUT = 18 A; VSENSE = 4 V;
VSEn = 5 V;
Tj = -40 °C to 150 °C -5 5 %
VOUT_MSD(2)
Output Voltage for current
sense shutdown VIN = 5 V; VSEn = 5 V;
RSENSE = 2.7 kΩ; IOUT = 5 A
5
V
VSENSE_SAT CS saturation voltage VCC = 7 V; RSENSE = 2.7 kΩ;
VSEn = 5 V; VIN = 5 V;
IOUT = 18 A; Tj = 150°C 5 V
ISENSE_SAT(2)
CS saturation current VCC = 7 V; VSENSE = 4 V;
VIN = 5 V; VSEn = 5 V;
Tj = 150°C 4 mA
DocID027771 Rev 4 11/42
Electrical specification
VN7008AJ
Symbol Parameter Test conditions Min.
Typ. Max.
Unit
7 V < VCC < 18 V; -40°C < Tj < 150°C
IOUT_SAT(2) Output saturation current VCC = 7 V; VSENSE = 4 V;
VIN = 5 V; VSEn = 5 V;
Tj = 150°C 24 A
ISENSE0 Current sense leakage current
CS disabled: VSEn = 0 V; 0
0.5
µA
CS disabled:
-1 V < VSENSE < 5 V(2) -0.5
0.5
CS enabled: VSEn = 5 V;
Channel ON; IOUT = 0 A;
Diagnostic selected;
VIN = 5 V; IOUT = 0 A;
0 2
CS enabled: VSEn = 5 V;
Channel OFF; Diagnostic
selected: VIN = 0 V 0 2
OFF-state diagnostic
VOL OFF-state open-load voltage
detection threshold VIN = 0 V; VSEn = 5 V 2 3 4 V
IL(off2) OFF-state output sink current VIN = 0 V; VOUT = VOL;
Tj = -40°C to 125°C -100
-15 µA
tDSTKON OFF-state diagnostic delay
time from falling edge of INPUT
(see Figure 8: "TDSTKO N")
VIN = 5 V to 0 V; VSEn = 5 V;
IOUT = 0 A; VOUT = 4 V 100 350 700 µs
tD_OL_V Settling time for valid OFF-
state
open load diagnostic indication
from rising edge of SEn
VIN = 0 V; VFR = 0 V; VOUT = 4
V;
VSEn = 0 V to 5 V 60 µs
tD_VOL OFF-state diagnostic delay
time from rising edge of VOUT VIN = 0 V; VSEn = 5 V;
VOUT = 0 V t o 4 V
5 30 µs
Fault diagnostic feedback (see Table 10: "Truth table")
VSENSEH Current sense output voltage in
fault condit ion
VCC = 13 V; VIN = 0 V;
VSEn = 5 V; IOUT = 0 A;
VOUT = 4 V; RSENSE = 1 kΩ 5 6.6 V
ISENSEH Current sense output current i n
fault condit ion VCC = 13 V; VSENSE = 5 V 7 20 30 mA
Current sense timings (current sense mode - see Figure 7: "CurrentSense timings (current
sense mode)")
tDSENSE1H Current sense settling time
from rising edge of SEn VIN = 5 V; VSEn = 0 V to 5 V;
RSENSE = 1 kΩ; RL = 2.6 Ω
60 µs
tDSENSE1L Current sense disable delay
time from falling edge of SEn VIN = 5 V; VSEn = 5 V to 0 V;
RSENSE = 1 kΩ; RL = 2.6 Ω
5 20 µs
tDSENSE2H Current sense settling time
from rising edge of INPUT VIN = 0 V to 5 V; VSEn = 5 V;
RSENSE = 1 kΩ; RL = 2.6 Ω
100 350 µs
ΔtDSENSE2H
Current sense sett ling time
from rising edge of IOUT
(dynamic response to a step
change of IOUT)
VIN = 5 V; VSEn = 5 V;
RSENSE = 1 kΩ;
ISENSE = 90 % of ISENSEMAX;
RL = 2.6 Ω 150 µs
12/42 DocID027771 Rev 4
VN7008AJ
Electrical specification
Symbol Parameter Test conditions Min.
Typ. Max.
Unit
7 V < VCC < 18 V; -40°C < Tj < 150°C
tDSENSE2L Current sense tur n-off delay
time from falling edge of INPUT VIN = 5 V to 0 V; VSEn = 5 V;
RSENSE = 1 kΩ; RL = 2.6 Ω
50 250 µs
Notes:
(1)All values refer to VCC = 13 V; Tj = 25°C, unless otherwise specified.
(2)Parameter specified by design; not subject to production t est.
Figure 4: IOUT/ISENSE versus IOUT
Figure 5: Current sense accuracy versus IOUT
0
1000
2000
3000
4000
5000
6000
7000
8000
9000
10000
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
K-factor
IOUT [A]
Max
Min
Typ
GAPG1802161551CFT
GAPG1802161558CFT
0
5
10
15
20
25
30
35
40
45
50
55
60
65
0 1 2 3 4 5 6 7 8 9 1011 12 13 14151617 18 19
%
IOUT [A]
Current sense uncalibrated precision
Current sense calibrated precision
DocID027771 Rev 4 13/42
Electrical specification
VN7008AJ
Figure 6: Switching times and Pulse skew
Figure 7: CurrentSense timings (current sense mode)
VOUT
t
Vcc
twon
80% Vcc
20% Vcc
twoff
INPUT
td(on)
tpLH tpHL
td(off)
t
dV
OUT
/dt
ON OFF
dV
OUT
/dt
GAPG2609141134CFT
14/42 DocID027771 Rev 4
VN7008AJ
Electrical specification
Figure 8: TDSTKON
Table 10: Truth table
Mode Conditions INX
FR
SEn
OUTX
CurrentSense
Comments
Stand by All logic inputs low L L L L Hi-Z Low quiescent
current consumption
Normal Nominal load
connected; Tj < 150 °C
L X
See
(1)
L
See (1)
H L H Outputs config ur ed
for auto-restart
H H H Outputs config ur ed
for Latch-off
Overload Overload or short to
GND causing: Tj > TTSD
or ΔTj > ΔTj_SD
L X
See
(1)
L
See (1)
H L H Output cycles with
temperature
hysteresis
H H L Output latches-off
Undervoltage VCC < VUSD (falling) X X X L
L Hi-Z
Hi-Z
Re-start when
VCC > VUSD +
VUSDhyst (rising)
OFF-state
diagnostics Short to VCC L X See
(1) H See (1)
Open-load L X H External pull-up
Negative output
voltage Inductive loads turn-off L X See
(1) < 0 V
See (1)
Notes:
(1)Refer to T able 11: "CurrentSense multiplexer addressing"
TDSTKON
VINPU T
VOUT
MultiSense
VOUT> VOL
GAPG2609141140CFT
DocID027771 Rev 4 15/42
Electrical specification
VN7008AJ
Table 11: Curr entS ense multiplexer addr es sing
SEn
MUX channel CS output
Nomal mode Overload OFF-state diag.
(1)(2)(3) Negative
output
L
Hi-Z
H Output
diagnostic ISENSE =
1/K * IOUT VSENSE =
VSENSEH VSENSE = VSENSEH Hi-Z
Notes:
(1)Example 2: FR = 1; IN = 0; O UT = latched, VOUT > VOL; MUX channel = channel 0 diagnostic; CS = VSENSEH
(2)Example 1: FR = 1; IN = 0; O UT = L (latched); MUX channel = channel 0 diagnostic; CS = 0
(3)In case the output channel correspondi ng to the selected MUX channel is latc hed off while the relevant i nput is
low, CS pin delivers feedback according to OFF-Stat e di agnost ic.
2.4 Waveforms
Figure 9: Latch functionality - behavior in hard short circuit condition (TAMB << TTSD)
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VN7008AJ
Electrical specification
Figure 10: Latch functionality - behavior in hard short circuit condition
Figure 11: Latch functionality - behavior in hard short circuit condition (autorestart mode +
latch off)
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Electrical specification
VN7008AJ
Figure 12: Standby mode activation
Figure 13: Standby state diagram
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