VN7008AJTR - STMICROELECTRONICS

VN7008AJ

High-side driver with CurrentSense analog feedback for

automotive applications

Datasheet - product ion data

Features

Max transient supply voltage VCC 40 V

Operating voltage range VCC 4 to 28 V

Typ. on-state resistance (per Ch) RON 8.5 mΩ

Current limitation (typ) ILIMH 96 A

Standby current (max) ISTBY 0.5 µA

• Automotive qualified

• General

− Single channel smart high side driver

with CS analog feedback

− Very low standby current

− Compatible with 3 V and 5 V CMOS

outputs

• CS diagnostic functions

− Analog feedback of: load current with

high precis ion prop or tio na l cur rent

mirror

− Overload and short to ground (power

limitation) indication

− Thermal shutdown indication

− OFF-state open-load detection

− Output short to VCC detection

− Sense enable/ disable

• Protections

− Undervoltage shutdown

− Overvoltage clamp

− Load current limitation

− Self limiting of fast thermal transients

− Configurable latch-off on

overtemperature or power limitation

with dedicated fault reset pin

− Loss of ground and loss of VCC

− Reverse battery with external

components

− Electrostatic discharge protection

Applications

• All types of Automotive resistive, inductive

and capacitive loads

• Specially intended for Automotive

Headlamps

Description

The device is a single channel high-side driver

manufactured using ST proprietary VIPower®

technology and housed in Power SSO -16

package. The device is designed to drive 12 V

automotive grounded loads through a 3 V and

5 V CMOS-compatible interface, and to provide

protection and diagnostics.

The device integrates advanced protective

functions such as load current limitation, overload

active management by power limitati on and

overtemperature shutdown with configurable

latch-off.

A FaultRST pin unlatches the output in case of

fault or disables the latch-off functionality.

A sense enable pin allows OFF-state diagnosis to

be disabled during the module low-power mode

as well as external sense resistor sharing among

similar devices.

March 2016 DocID027771 Rev 4 1/42

This is information on a product in full production. www.st.com

Contents

VN7008AJ

Contents

1 Block diagram and pin des cr iption ................................................ 5

2 Electrical specification .................................................................... 7

2.1 Absolute maxi mu m rati ngs ................................................................ 7

2.2 Thermal dat a ..................................................................................... 8

2.3 Main electrical characteristics ........................................................... 8

2.4 Waveforms ...................................................................................... 16

2.5 Electrical characteristics curves ...................................................... 19

3 Protections..................................................................................... 23

3.1 Power limitation ............................................................................... 23

3.2 Thermal shutdown ........................................................................... 23

3.3 Current limitation ............................................................................. 23

3.4 Negative voltage clamp ................................................................... 23

4 Application information ................................................................ 24

4.1 GND protection network against reverse battery ............................. 24

4.1.1 Diode (DGND) in the ground line ..................................................... 25

4.2 Immunity against transient electrical disturbances .......................... 25

4.3 MCU I/Os protection ........................................................................ 25

4.4 CS - analog current sense .............................................................. 26

4.4.1 Principle of CurrentSense signal generation .................................... 27

4.4.2 Short to VCC and OFF-state open-l oad det ec tio n ........................... 29

5 Package and PCB thermal data .................................................... 31

5.1 PowerSSO-16 thermal data ............................................................ 31

6 Maximum demagnetiza t ion energy (VCC = 16 V) ........................ 34

7 Package information ..................................................................... 35

7.1 PowerSSO-16 package information ................................................ 35

7.2 PowerSSO-16 packing information ................................................. 37

7.3 PowerSSO-16 marki ng in format ion ................................................. 39

8 Order c ode s ................................................................................... 40

9 Revision history ............................................................................ 41

2/42 DocID027771 Rev 4

VN7008AJ

List of tables

Table 1: Pin functions ................................................................................................................................. 5

Table 2: Suggested connections for unused and not connected pins ........................................................ 6

Table 3: Absolute maximum ratings ........................................................................................................... 7

Table 4: Thermal data ................................................................................................................................. 8

Table 5: Power section ............................................................................................................................... 8

Table 6: Switching ....................................................................................................................................... 9

Table 7: Logic Inputs................................................................................................................................. 10

Table 8: Protections .................................................................................................................................. 10

Table 9: CurrentSense .............................................................................................................................. 11

Table 10: Truth table ................................................................................................................................. 15

Table 11: CurrentSense multiplexer addressing ...................................................................................... 16

Table 12: ISO 7637-2 - electrical transient conduction along supply line ................................................. 25

Table 13: CurrentSense pin levels in off-state .......................................................................................... 29

Table 14: PCB properties ......................................................................................................................... 31

Table 15: Thermal parameters ................................................................................................................. 33

Table 16: PowerSSO-16 mechanical data................................................................................................ 35

Table 17: Reel dimensions ....................................................................................................................... 37

Table 18: PowerSSO-16 carrier tape dimensions .................................................................................... 38

Table 19: Device summary ....................................................................................................................... 40

Table 20: Document revision history ........................................................................................................ 41

DocID027771 Rev 4 3/42

List of figur es

VN7008AJ

List of figures

Figure 1: Block diagram .............................................................................................................................. 5

Figure 2: Configuration diagram (top view)................................................................................................. 6

Figure 3: Current and voltage conventions ................................................................................................. 7

Figure 4: IOUT /IS ENS E ver sus IOUT ....................................................................................................... 13

Figure 5: Current sense accuracy versus IOUT ....................................................................................... 13

Figure 6: Switching times and Pulse skew ............................................................................................... 14

Figure 7: CurrentSense timings (current sense mode) ............................................................................. 14

Figure 8: TDSTKON .................................................................................................................................. 15

Figure 9: Latch functionality - behavior in hard short circuit condition (TAMB << TTSD) ........................ 16

Figure 10: Latch func t ion al ity - behavior in hard short circuit condition .................................................... 17

Figure 11: Latch func t ion al ity - behavior in hard short circuit condition (autorestart mode + latch off) .... 17

Figure 12: Standby mode activation ......................................................................................................... 18

Figure 13: Stand b y state di agram ............................................................................................................. 18

Figure 14: OFF-state output current ......................................................................................................... 19

Figure 15: Stand b y current ....................................................................................................................... 19

Figure 16: IGND(ON) vs Tcase ................................................................................................................ 19

Figure 17: Logic Input hi gh le vel volt age .................................................................................................. 19

Figure 18: Logic Input lo w level vo ltag e .................................................................................................... 19

Figure 19: High lev el logic input curre nt ................................................................................................... 19

Figure 20: Low leve l logic input current .................................................................................................... 20

Figure 21: Logic Input h yster es is volt age ................................................................................................. 20

Figure 22: FaultRST Input clamp voltage ................................................................................................. 20

Figure 23: Under vo lta ge shut do wn ........................................................................................................... 20

Figure 24: On-state resistance vs Tcase .................................................................................................. 20

Figure 25: On-state resistance vs VCC .................................................................................................... 20

Figure 26: Turn-on volta ge s lope .............................................................................................................. 21

Figure 27: Turn-off voltage slope .............................................................................................................. 21

Figure 28: Won vs Tcase .......................................................................................................................... 21

Figure 29: Woff vs Tcase .......................................................................................................................... 21

Figure 30: ILIMH vs. Tcase ....................................................................................................................... 21

Figure 31: OFF-state open-load voltage detection threshold ................................................................... 21

Figure 32: Vsense clamp vs. Tcase .......................................................................................................... 22

Figure 33: Vsense h vs . Tc ase .................................................................................................................. 22

Figure 34: Appl icati on dia gram ................................................................................................................. 24

Figure 35: Simplified internal structure ..................................................................................................... 24

Figure 36: CurrectSense and diagnostic – block diagram ........................................................................ 26

Figure 37: CurrentSense block diagram ................................................................................................... 27

Figure 38: Anal ogu e HSD – open-load detect ion in of f -state ................................................................... 28

Figure 39: Open-load / short to VCC condition ......................................................................................... 29

Figure 40: Power S SO-16 on two-layers PCB (2s0p to JEDEC JESD 51-5) ............................................ 31

Figure 41: Power S SO-16 on four-layers PCB (2s2p to JEDEC JESD 51-7) ........................................... 31

Figure 42: Rthj-amb vs PCB copper area in open box free air conditions ............................................... 32

Figure 43: Power S SO-16 thermal impedance junction ambient single pulse .......................................... 32

Figure 44: Thermal fitting model for PowerSSO-16 .................................................................................. 33

Figure 45: Maximum turn off current versus inductance .......................................................................... 34

Figure 46: Power S SO-16 package dimensions ........................................................................................ 35

Figure 47: Power S SO-16 reel 13" ............................................................................................................ 37

Figure 48: Power S SO-16 carrier tape ...................................................................................................... 38

Figure 49: Power S SO-16 schematic drawing of leader and trailer tape .................................................. 38

Figure 50: Power S SO-16 marking information ......................................................................................... 39

4/42 DocID027771 Rev 4

VN7008AJ

Block diagram and pin description

1 Block diagram and pin description

Figure 1: Block diagra m

Table 1: Pin functions

Name Function

VCC Battery connection.

OUTPUT Power outputs. All the pins must be connected together.

GND Ground connection. Must be reverse battery protected by an external diode / resistor

network.

INPUT Voltage controlled input pin with hysteresis, compatible with 3 V and 5 V CMOS outputs.

It controls output switch state.

CS Analog current sense output pin delivers a current proportional to the load current.

SEn

Active high compatible with 3 V and 5 V CMOS outputs pin; it enables the CS diagnostic

pin.

FaultRST Active low compatible with 3 V and 5 V CMOS outputs pin; it unlatches the output in

case of fault; If kept low, sets the outputs in auto-restart mod e.

DocID027771 Rev 4 5/42

Block diagram and pin description

VN7008AJ

Figure 2: Configuration diagram (top view)

Pins 9, 10, 11 and 12 are inter nally connected ; Pins 13 , 14, 15 and 16 are

internally connected; All output pins must be connected together on PCB.

Table 2: Suggested connections for unused and not connected pins

Connection / pin CS N.C. Output Input SEn,

FaultRST

Floating Not allowed X (1) X X X

To ground Through 1 kΩ

resistor X Not allowed Through 15 kΩ

resistor Through 15 kΩ

resistor

Notes:

(1)X: do not care.

6/42 DocID027771 Rev 4

VN7008AJ

Electrical specification

2 Electrical specification

Figure 3: Current and voltage conventions

= V

OUT

- V

during reverse battery condition.

2.1 Absolute m a xi m um rat ings

Stressing the device above the rating listed in Table 3: "Absolute maximum ratings" may

cause permanent damage to the device. These are stress ratings only and operation of the

device at these or any other conditions above those indicated in the operating sections of

this specification is not implied. Exposure to the conditions in table below for extended

periods may affect device reliability.

Table 3: A bsolut e maximum rat ings

Symbol

Parameter Value Unit

VCC DC supply voltage 38

-VCC Reverse DC supply voltage 0.3

VCCPK Maximum transient supply voltage (ISO 16750-2:2010 Test B

clamped to 40V; RL = 4 Ω) 40

VCCJS Maximum jump start voltage for single pulse short circuit protection 28

-IGND DC reverse ground pin current 200 mA

IOUT OUTPUT DC output current Internally limited

-IOUT Reverse DC output current 35

IIN INPUT DC input current

-1 to 10 mA ISEn SEn DC input current

IFR FaultRST DC input current

VFR FaultRST DC input voltage 7.5 V

ISENSE CS pin DC output current (VGND = VCC and VSENSE < 0 V) 10 mA

CS pin DC output current in reverse (VCC < 0V) -20

DocID027771 Rev 4 7/42

Electrical specification

VN7008AJ

Symbol

Parameter Value Unit

EMAX Maximum switching en er gy (single pul se)

(TDEMAG = 0.4 ms; Tjstart = 150 °C) 170 mJ

VESD

Electrostatic discharge (JEDEC 22A-114F)

• INPUT

• CS

• SEn, FaultRST

• OUTPUT

• VCC

4000

2000

4000

VESD Charge device model (CDM-AEC-Q100-011) 750 V

Tj Junction operating temperature -40 to 150 °C

Tstg Storage temperat ure -55 to 150

2.2 Thermal da t a

Table 4: Thermal data

Symbol Parameter Typ. value Unit

Rthj-board T hermal resi stan ce jun cti on-board (JEDEC JESD 51-5 / 51-8)(1) 3.85

°C/W

Rthj-amb Thermal resistan ce jun cti on-ambient (JEDEC JESD 51-5)(2) 54.8

Rthj-amb Thermal resistan ce jun cti on-ambient (JEDEC JESD 51-7)(1) 21

Notes:

(1)Device mounted on four-layers 2s2p PCB.

(2)Device mounted on two-layers 2s0p PCB with 2 cm2 heatsink copper trace.

2.3 Main electrical characteristics

7 V < VCC < 18 V; -40 °C < Tj < 150 °C, unless otherwise specified.

All typical values refer to VCC = 13 V; Tj = 25°C, unless otherwise specified.

Table 5: Power section

Symbol Parameter Test conditions Min. Typ. Max. Unit

VCC Operating supply voltage

4 13 28

VUSD Undervoltage shut dow n

VUSDReset Undervoltage shutdow n reset

VUSDhyst Undervolta ge shut down

hysteresis

0.3

RON On-state resistance

IOUT = 5 A; Tj = 25 °C

8.5

mΩ

IOUT = 5 A; Tj = 150 °C

IOUT = 5 A; VCC = 4 V;

Tj = 25 °C

12.75

Vclamp Clamp voltage IS = 20 mA; Tj = -40°C 38

IS = 20 mA; 25°C < Tj < 150°C

41 46 52

8/42 DocID027771 Rev 4

VN7008AJ

Electrical specification

Symbol Parameter Test conditions Min. Typ. Max. Unit

ISTBY Supply current in standby at

VCC = 13 V (1)

VCC = 13 V;

VIN = VOUT = VFR = VSEn = 0 V;

Tj = 25 °C 0.5 µA

VCC = 13 V;

VIN = VOUT = VFR = VSEn = 0 V;

Tj = 85 °C (2) 0.5 µA

VCC = 13 V;

VIN = VOUT = VFR = VSEn = 0 V;

Tj = 125 °C 3 µA

tD_STBY Standby mode blanking time VCC = 13 V; VIN = 5 V;

VSEn = VFR = 0 V; IOUT = 0 A 60 300 550 µs

IS(ON) Supply current VCC = 13 V; VSEn = VFR = 0 V;

VIN = 5 V; IOUT = 0 A

3 5 mA

IGND(ON) Control stage curren t

consumption in ON state. All

channels active.

VCC = 13 V; VSEn = 5 V;

VFR = 0 V; VIN = 5 V;

IOUT = 5 A 6 mA

IL(off) Off-state output current at

VCC = 13 V

VIN = VOUT = 0 V; VCC = 13 V;

Tj = 25 °C 0 0.01 0.5 µA

VIN = VOUT = 0 V; VCC = 13 V;

Tj = 125 °C 0

VF Output - VCC diode voltage IOUT = -5 A; Tj = 150 °C

0.7 V

Notes:

(1)PowerMOS leakage included.

(2)Parameter specified by design; not subject to production t est.

Table 6: Switchin g

Symbol Parameter Test conditions Min. Typ.

Max. Unit

VCC = 13 V; -40°C < Tj < 150°C, unless otherwise specified

td(on)(1) Turn-on delay time at Tj = 25°C RL = 2.6 Ω 10 45 120 µs

td(off)(1) Turn-off delay time at Tj = 25°C 10 48 100

(dVOUT/dt)on(1) Turn-on voltage slope at Tj = 25°C RL = 2.6 Ω 0.1 0.2 0.7 V/µs

(dVOUT/dt)off(1) Turn-off voltage slope at Tj = 25°C 0.1 0.3 0.7

WON Switching energy losses at turn-on (twon) RL = 2.6 Ω — 0.8 1.2(2) mJ

WOFF Switching energy losses at turn-off (twoff) RL = 2.6 Ω — 0.6 1(2) mJ

tSKEW(1) Differential Pulse skew (tPHL - tPLH) RL = 2.6 Ω -65 -15 35 µs

Notes:

(1)See Figure 6: "Swit ch ing tim es and Pulse skew ".

(2)Parameter guaranteed by design and characterizati on; not subj ect to product i on test.

DocID027771 Rev 4 9/42

Electrical specification

VN7008AJ

Table 7: Logic Inputs

Symbol Parameter Test conditions Min. Typ. Max. Unit

7 V < VCC < 28 V; -40°C < Tj < 150°C

INPUT characteristics

VIL Input low level voltage

0.9 V

IIL Low level input current VIN = 0.9 V 1

µA

VIH Input high level voltage

2.1

IIH High level input current VIN = 2.1 V

10 µA

VI(hyst) Input hystere si s voltage

0.2

VICL Input clamp voltag e IIN = 1 mA 5.3

7.5 V

IIN = -1 mA

-0.7

FaultRST characteristics

VFRL Input low level voltage

0.9 V

IFRL Low level input current VIN = 0.9 V 1

µA

VFRH Input high level voltage

2.1

IFRH High level input current VIN = 2.1 V

10 µA

VFR(hyst) Input hysteresi s volta ge

0.2

VFRCL Input clamp voltage IIN = 1 mA 5.3

7.2 V

IIN = -1 mA

-0.7

SEn characteristics (7 V < VCC < 18 V)

VSEnL Input low level voltage

0.9 V

ISEnL Low level input current VIN = 0.9 V 1

µA

VSEnH Input high level voltage

2.1

ISEnH High level input current VIN = 2.1 V

10 µA

VSEn(hyst) Input hysteresi s voltage

0.2

VSEnCL Input clamp voltage IIN = 1 mA 5.3

7.5 V

IIN = -1 mA

-0.7

Table 8: Protections

Symbol Parameter Test conditions Min. Typ. Max. Unit

7 V < VCC < 18 V; -40°C < Tj < 150°C

ILIMH DC short circuit current VCC = 13 V 70 98 140

4 V < VCC < 18 V (1)

140

ILIML Short circuit current

during thermal cycling VCC = 13 V;

TR < Tj < TTSD

TTSD Shutdown temperature

150 175 200

°C

TR Reset temperature(1)

TRS + 1 TRS + 7

TRS Thermal reset of fault

diagnostic ind ica tio n VFR = 0 V; VSEn = 5 V; 135

THYST Thermal hysteresis

(TTSD - TR)(1)

10/42 DocID027771 Rev 4

VN7008AJ

Electrical specification

Symbol Parameter Test conditions Min. Typ. Max. Unit

7 V < VCC < 18 V; -40°C < Tj < 150°C

ΔTJ_SD Dynamic temperature Tj = -40 °C; VCC = 13 V

tLATCH_RST

Fault reset time for output

unlatch(1) VFR = 5 V to 0 V;

VSEn = 5 V; VIN = 5 V 3 10 20 µs

VDEMAG Turn-off output voltage

clamp

IOUT = 2 A; L = 6 mH;

Tj = -40 °C VCC - 38

IOUT = 2 A; L = 6 mH;

Tj = 25 °C to 150 °C VCC - 41 VCC - 46 VCC - 52

VON Output volt age drop

limitation IOUT = 0.25 A

Notes:

(1)Parameter guaranteed by design and characterizati on; not subj ect to product i on test.

Table 9: Curr entS ense

Symbol Parameter Test conditions Min.

Typ. Max.

Unit

7 V < VCC < 18 V; -40°C < Tj < 150°C

VSENSE_CL Current sense cla mp volt age VSEn = 0 V; ISENSE = 1 mA -17

-12 V

VSEn = 0 V; ISENSE = -1 mA

Current Sense characteristics

K0 IOUT/ISENSE IOUT = 0.9 A; VSENSE = 0.5 V;

VSEn = 5 V 3465

6150

9135

dK0/K0(1)(2) Current sense ratio drif t IOUT = 0.9 A; VSENSE = 0.5 V;

VSEn = 5 V -20

20 %

K1 IOUT/ISENSE IOUT = 1.5 A; VSENSE = 4 V;

VSEn = 5 V 3735

5990

8725

dK1/K1(2)(1) Current sense ratio drif t IOUT = 1.5 A; VSENSE = 4 V;

VSEn = 5 V -15

15 %

K2 IOUT/ISENSE IOUT = 6 A; VSENSE = 4 V;

VSEn = 5 V 4410

5890

7360

dK2/K2(2)(1) Current sense ratio drif t IOUT = 6 A; VSENSE = 4 V;

VSEn = 5 V -10

+10 %

K3 IOUT/ISENSE IOUT = 18 A; VSENSE = 4 V;

VSEn = 5 V 5290

5880

6470

dK3/K3(2)(1) Current sense ratio drift IOUT = 18 A; VSENSE = 4 V;

VSEn = 5 V;

Tj = -40 °C to 150 °C -5 5 %

VOUT_MSD(2)

Output Voltage for current

sense shutdown VIN = 5 V; VSEn = 5 V;

RSENSE = 2.7 kΩ; IOUT = 5 A

VSENSE_SAT CS saturation voltage VCC = 7 V; RSENSE = 2.7 kΩ;

VSEn = 5 V; VIN = 5 V;

IOUT = 18 A; Tj = 150°C 5 V

ISENSE_SAT(2)

CS saturation current VCC = 7 V; VSENSE = 4 V;

VIN = 5 V; VSEn = 5 V;

Tj = 150°C 4 mA

DocID027771 Rev 4 11/42

Electrical specification

VN7008AJ

Symbol Parameter Test conditions Min.

Typ. Max.

Unit

7 V < VCC < 18 V; -40°C < Tj < 150°C

IOUT_SAT(2) Output saturation current VCC = 7 V; VSENSE = 4 V;

VIN = 5 V; VSEn = 5 V;

Tj = 150°C 24 A

ISENSE0 Current sense leakage current

CS disabled: VSEn = 0 V; 0

0.5

µA

CS disabled:

-1 V < VSENSE < 5 V(2) -0.5

0.5

CS enabled: VSEn = 5 V;

Channel ON; IOUT = 0 A;

Diagnostic selected;

VIN = 5 V; IOUT = 0 A;

0 2

CS enabled: VSEn = 5 V;

Channel OFF; Diagnostic

selected: VIN = 0 V 0 2

OFF-state diagnostic

VOL OFF-state open-load voltage

detection threshold VIN = 0 V; VSEn = 5 V 2 3 4 V

IL(off2) OFF-state output sink current VIN = 0 V; VOUT = VOL;

Tj = -40°C to 125°C -100

-15 µA

tDSTKON OFF-state diagnostic delay

time from falling edge of INPUT

(see Figure 8: "TDSTKO N")

VIN = 5 V to 0 V; VSEn = 5 V;

IOUT = 0 A; VOUT = 4 V 100 350 700 µs

tD_OL_V Settling time for valid OFF-

state

open load diagnostic indication

from rising edge of SEn

VIN = 0 V; VFR = 0 V; VOUT = 4

VSEn = 0 V to 5 V 60 µs

tD_VOL OFF-state diagnostic delay

time from rising edge of VOUT VIN = 0 V; VSEn = 5 V;

VOUT = 0 V t o 4 V

5 30 µs

Fault diagnostic feedback (see Table 10: "Truth table")

VSENSEH Current sense output voltage in

fault condit ion

VCC = 13 V; VIN = 0 V;

VSEn = 5 V; IOUT = 0 A;

VOUT = 4 V; RSENSE = 1 kΩ 5 6.6 V

ISENSEH Current sense output current i n

fault condit ion VCC = 13 V; VSENSE = 5 V 7 20 30 mA

Current sense timings (current sense mode - see Figure 7: "CurrentSense timings (current

sense mode)")

tDSENSE1H Current sense settling time

from rising edge of SEn VIN = 5 V; VSEn = 0 V to 5 V;

RSENSE = 1 kΩ; RL = 2.6 Ω

60 µs

tDSENSE1L Current sense disable delay

time from falling edge of SEn VIN = 5 V; VSEn = 5 V to 0 V;

RSENSE = 1 kΩ; RL = 2.6 Ω

5 20 µs

tDSENSE2H Current sense settling time

from rising edge of INPUT VIN = 0 V to 5 V; VSEn = 5 V;

RSENSE = 1 kΩ; RL = 2.6 Ω

100 350 µs

ΔtDSENSE2H

Current sense sett ling time

from rising edge of IOUT

(dynamic response to a step

change of IOUT)

VIN = 5 V; VSEn = 5 V;

RSENSE = 1 kΩ;

ISENSE = 90 % of ISENSEMAX;

RL = 2.6 Ω 150 µs

12/42 DocID027771 Rev 4

VN7008AJ

Electrical specification

Symbol Parameter Test conditions Min.

Typ. Max.

Unit

7 V < VCC < 18 V; -40°C < Tj < 150°C

tDSENSE2L Current sense tur n-off delay

time from falling edge of INPUT VIN = 5 V to 0 V; VSEn = 5 V;

RSENSE = 1 kΩ; RL = 2.6 Ω

50 250 µs

Notes:

(1)All values refer to VCC = 13 V; Tj = 25°C, unless otherwise specified.

(2)Parameter specified by design; not subject to production t est.

Figure 4: IOUT/ISENSE versus IOUT

Figure 5: Current sense accuracy versus IOUT

1000

2000

3000

4000

5000

6000

7000

8000

9000

10000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

K-factor

IOUT [A]

Max

Min

Typ

GAPG1802161551CFT

GAPG1802161558CFT

0 1 2 3 4 5 6 7 8 9 1011 12 13 14151617 18 19

IOUT [A]

Current sense uncalibrated precision

Current sense calibrated precision

DocID027771 Rev 4 13/42

Electrical specification

VN7008AJ

Figure 6: Switching times and Pulse skew

Figure 7: CurrentSense timings (current sense mode)

VOUT

Vcc

twon

80% Vcc

20% Vcc

twoff

INPUT

td(on)

tpLH tpHL

td(off)

OUT

/dt

ON OFF

OUT

/dt

GAPG2609141134CFT

14/42 DocID027771 Rev 4

VN7008AJ

Electrical specification

Figure 8: TDSTKON

Table 10: Truth table

Mode Conditions INX

SEn

OUTX

CurrentSense

Comments

Stand by All logic inputs low L L L L Hi-Z Low quiescent

current consumption

Normal Nominal load

connected; Tj < 150 °C

L X

See

(1)

See (1)

H L H Outputs config ur ed

for auto-restart

H H H Outputs config ur ed

for Latch-off

Overload Overload or short to

GND causing: Tj > TTSD

or ΔTj > ΔTj_SD

L X

See

(1)

See (1)

H L H Output cycles with

temperature

hysteresis

H H L Output latches-off

Undervoltage VCC < VUSD (falling) X X X L

L Hi-Z

Hi-Z

Re-start when

VCC > VUSD +

VUSDhyst (rising)

OFF-state

diagnostics Short to VCC L X See

(1) H See (1)

Open-load L X H External pull-up

Negative output

voltage Inductive loads turn-off L X See

(1) < 0 V

See (1)

Notes:

(1)Refer to T able 11: "CurrentSense multiplexer addressing"

TDSTKON

VINPU T

VOUT

MultiSense

VOUT> VOL

GAPG2609141140CFT

DocID027771 Rev 4 15/42

Electrical specification

VN7008AJ

Table 11: Curr entS ense multiplexer addr es sing

SEn

MUX channel CS output

Nomal mode Overload OFF-state diag.

(1)(2)(3) Negative

output

Hi-Z

H Output

diagnostic ISENSE =

1/K * IOUT VSENSE =

VSENSEH VSENSE = VSENSEH Hi-Z

Notes:

(1)Example 2: FR = 1; IN = 0; O UT = latched, VOUT > VOL; MUX channel = channel 0 diagnostic; CS = VSENSEH

(2)Example 1: FR = 1; IN = 0; O UT = L (latched); MUX channel = channel 0 diagnostic; CS = 0

(3)In case the output channel correspondi ng to the selected MUX channel is latc hed off while the relevant i nput is

low, CS pin delivers feedback according to OFF-Stat e di agnost ic.

2.4 Waveforms

Figure 9: Latch functionality - behavior in hard short circuit condition (TAMB << TTSD)

16/42 DocID027771 Rev 4

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Electrical specification

Figure 10: Latch functionality - behavior in hard short circuit condition

Figure 11: Latch functionality - behavior in hard short circuit condition (autorestart mode +

latch off)

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Electrical specification

VN7008AJ

Figure 12: Standby mode activation

Figure 13: Standby state diagram

18/42 DocID027771 Rev 4

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Electrical specification

2.5 Electrical characteristics curves

Figure 14: OFF-state output current

Figure 15: Standby current

Figure 16: IGND(ON) vs Tcase

Figure 17: Logic Input high level voltage

Figure 18: Logic Input low level voltage

Figure 19: High level logic input current

GAPG2202160912CFT

500

1000

1500

2000

2500

-50 -25 025 50

75100125150175

T [°C]

Iloff [nA]

Off State

Vcc =13V

Vin= Vout=0

GAPG2202160917CFT

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

-50 -25 0 25 50 75 100125150175

T [°C]

ISTBY[µA]

Vcc =13V

GAPG2202160918CFT

0.0

0.5

1.0

1.5

2.0

2.5

3.0

-50 -25 0 25 50 75 100125150175

T [°C]

IGND(ON)[mA]

Vcc =13V

Iout=5A

GAPG22021609192CFT

0.2

0.4

0.6

0.8

1.2

1.4

1.8

-50 -25 0 25 50 75100125150175

T [°C]

ViH, VFRH,VSE LH,VSE nH [V]

GAPG2202160920CFT

0.2

0.4

0.6

0.8

1.2

1.4

1.8

-50 -25 0 25 50 75 100125150175

T [°C]

VilLVFRL, VSE LL, VSE nL [V]

GAPG2202160921CFT

0.5

1.5

2.5

3.5

-50 -2

5 0 25 50 75 100125150175

T [°C]

IiH, IFRH,ISELH, ISEnH [µA]

DocID027771 Rev 4 19/42

Electrical specification

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Figure 20: Low level logic input current

Figure 21: Logic Input hysteresis voltage

Figure 22: FaultRST Input clamp voltage

Figure 23: Undervoltage shutdown

Figure 24: On-state resistance vs Tcase

Figure 25: On-state resistance vs VCC

GAPG2202160922CFT

0.5

1.5

2.5

3.5

-50 -2

5025 50 75 100125150175

T[°C]

IiL, IFRL, ISELL,ISEnL[µA]

GAPG220216023CFT

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

-50 -25 0 2550 75 100125150175

T [°C]

Vi(hyst),VFR(hyst),VSE L(hyst),VSE n(hyst) [V]

GAPG2202160924CFT

-1

-50 -25 0 25 50

75100125150175

T [°C]

VFRCL [V]

Iin = 1mA

Iin= -1mA

GAPG2202160925CFT

-50 -25 0 25 50 75

100125150175

T [°C]

VUSD [V]

GAPG2202160926CFT

-5

0 -25 0 25 50 75 100125150175

T [°C]

Ron [mOhm]

Iout = 5A

Vcc =13V

GAPG2202160927CFT

0 5 10 15 20 25 30 35

Vcc[V]

Ron [mOhm]

T = -40°C

T= 25°C

T = 125°C

T = 150°C

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Electrical specification

Figure 26: Turn-on voltage slope

Figure 27: Turn-off voltage slope

Figure 28: Won vs Tcase

Figure 29: Woff vs Tcase

Figure 30: ILIMH vs. Tcase

Figure 31: OFF-state open-load voltage

detection threshold

GAPG2202160928CFT

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

-50 -25 0 25 50 75100125150175

T [°C]

(dVout/dt)On [V/µs]

Vcc =13V

Rl =2.6Ω

GAPG2202160929CFT

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

-50 -25 0 25 50 75100125150175

T [°C]

(dVout/dt)Off [V/µs]

Vcc =13V

Rl = 2.6Ω

GAPG2202160930CFT

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.1

1.2

1.3

1.4

1.5

-50 -25 0 25 50 75100125150175

T [°C]

Won [mJ]

GAPG2202160931CFT

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

-50 -25 0 25 50 75100125150175

T [°C]

Woff [mJ]

GAPG2202160932CFT

100

105

110

115

120

-5

0 -25 0 25 50 75 100125150175

T [°C]

Ilimh [A]

Vcc =13V

GAPG2202160935CFT

0.5

1.5

2.5

3.5

-50 -2

5 0 25 50 75 100125150175

T [°C]

VOL [V]

DocID027771 Rev 4 21/42

Electrical specification

VN7008AJ

Figure 32: Vsense clamp vs. Tcase

Figure 33: Vsenseh vs. Tcase

GAPG2202160938CFT

-1

-50-25025 50 75 100125150175

T[°C]

VSE NSE_CL [V]

Iin = 1mA

Iin = -1mA

-50-25 0 25 50

75 100125150175

T [°C]

VSE NSEH[V]

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Protections

3 Protections

3.1 Power limitation

The basic working principle of this protection consists of an indirect measurement of the

junction temperature swing ΔTj through the direct measurement of the spatial temperature

gradient on the device surface in order to automatically shut off the output MOSFET as

soon as ΔTj exceeds the safety level of ΔTj_SD. According to the voltage level on the

FaultRST pin, the output MOSFET switches on and cycles with a thermal hysteresis

according to the maximum instantaneous power which can be handled (FaultRST = Low)

or remains off (FaultRST = High). The protection prevents fast thermal transient effects

and, consequently, reduces thermo-mechanical fatigue.

3.2 Thermal s hut dow n

In case the junction temperature of the device exceeds the maximum allowed threshold

(typically 175°C), it automatically switches off and the diagnostic indication is triggered.

According to the voltage level on the FaultRST pin, the device switches on again as soon

as its junction temperature drops to TR (FaultRST = Low) or remains off (FaultRST = High).

3.3 Current limitation

The device is equipped with an output current limiter in order to protect the silicon as well

as the other components of the system (e.g. bonding wires, wiring harness, connectors,

loads, etc.) from excessive current flow. Consequently, in case of short circuit, overload or

during load power-up, the output current is clamped to a safety level, ILIMH, by operating the

output power MOSFET in the active region.

3.4 Negative voltage clamp

In case the device drives inductive load, the output voltage reaches a negative value during

turn off. A negative voltage clamp structure limits the maximum negative voltage to a

certain value, VDEMAG, allowing the inductor energy to be dissipated without damaging the

device.

DocID027771 Rev 4 23/42

Application informa tion

VN7008AJ

4 Application information

Figure 34: Application diagram

4.1 GND protection network against reverse battery

Figure 35: Simplified internal structure

OUT

ADC in

OUT

GND

GND GND

Logic

OUTPUT

GND

FaultRST

INPUT

SEn

SEL

Current mirror

Rprot

+5V

GND

Rsense

GND

Cext

GND GND

Dld

GAPGCFT00829

MCU

INPUT

SEn

FaultRST

Vcc

OUTPUT

GND

Rprot

Dld

Rsense

RGND DGND

GND GAPGCFT00830

24/42 DocID027771 Rev 4

VN7008AJ

Application information

4.1.1 Diode (DGND) in the ground line

A resistor (typ. RGND = 4.7 kΩ) should be inserted in parallel to DGND if the device drives an

inducti ve load.

This small signal diode can be safely shared amongst several different HSDs. Also in this

case, the presence of the ground network produces a shift (≈600 mV) in the input thres hol d

and in the status output values if the microprocessor ground is not common to the device

ground. This shift does not vary if more than one HSD shares the same diode/resistor

network.

4.2 Immunity against transient electrical disturbances

The immunity of the device against transient electrical emissions, conducted along the

supply lines and injected into the VCC pin, is tested in accordance with ISO7637-2:2011 (E)

and ISO 16750-2:2010.

The related function performance status classification is shown in Table 12: "ISO 7637-2 -

electrical transient conduction along supply line".

Test pulses are applied directly to DUT (Device Under Test) both in ON and OFF-state and

in accordance to ISO 7637-2:2011(E), chapter 4. The DUT is intended as the present

device only, without components and accessed through VCC and GND terminals.

Status II is defined in ISO 7637-1 Function Performance Status Classification (FPSC) as

follows: “The function does not perform as designed during the test but returns

automatically to normal operation after the test”.

Table 12: ISO 7637-2 - ele ctr i cal transient condu ct ion along supply line

Test

Pulse

2011(E)

Test pulse severity

level with Status II

functional performance

status

Minimum

number of

pulses or test

time

Burst cycle / pulse

repetition time P ulse durati on and

pulse generator

internal impedance

Level US(1) min max

1 III -112V 500 pulses 0,5 s

2ms, 10Ω

2a III +55V 500 pulses 0,2 s 5 s 50µs, 2Ω

3a IV -220V 1h 90 ms 100 ms 0.1µs, 50Ω

3b IV +150V 1h 90 ms 100 ms 0.1µs, 50Ω

4 (2) IV -7V 1 pulse

100ms, 0.01Ω

Load dump according to ISO 16750-2:2010

Test B (3)

40V 5 pulse 1 min

400ms, 2Ω

Notes:

(1)US is the peak amplitude as defined for each test pulse in ISO 7637-2:2011(E), chapter 5.6.

(2)Test pulse from ISO 7637-2:2004(E).

(3)With 40 V external suppressor referred to ground (-40°C < Tj < 150°C).

4.3 MCU I/O s prot e ction

If a ground protection network is used and negative transients are present on the VCC line,

the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line both to

prevent the microcontroller I/O pins from latching-up and to protect the HSD inputs.

DocID027771 Rev 4 25/42

Application informa tion

VN7008AJ

The value of these resistors is a compromise between the leakage current of

microcontroller and the current required by the HSD I/Os (Input levels compatibility) with

the latch-up limit of microcontroller I/Os.

Equation

VCCpeak/Ilatchup ≤ Rprot ≤ (VOHµC - VIH - VGND) / IIHmax

Calculat ion example:

For VCCpeak = -150 V; Ilatchup ≥ 20 mA; VOHµC ≥ 4.5 V

7.5 kΩ ≤ Rprot ≤ 140 kΩ.

Recommended values: Rprot = 15 kΩ

4.4 CS - analog c urrent sense

Diagnostic information on device and load status are provided by an analog output pin (CS)

delivering the following signals:

• Current monitor: current mirror of channel output current

Those signals are routed through an analog multiplexer which is configured and controlled

by means of SELx and SEn pins, according to the address map in MultiSense multiplexer

addressing Table.

Figure 36: CurrectSense and diagnostic – block diagram

SEL

SEn

SENSE

PROT

To uC ADC

OUT

Current

Sense

Fault

Diagnostic

SENSEH

MUX

SENSE

OUT

K factor

CURRENT

MONITOR

Gate Driver

VCC– OUT

Clamp

VCC– GND

Clamp

Internal Supply

Undervoltage

shut-down

VON

Limitation

Current

Limitation

Power Limitation

Overtemperature

Short to VCC

Open-Load in OFF

SEL

Control & Diagnostic

GND

VCC

INPUT

FaultRST

GAPGCFT00831

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VN7008AJ

Application information

4.4.1 Principle of CurrentSense signal generation

Figure 37: CurrentSense block diagram

Current sense

This current mode is selected in the MultiSense, this output is capable to provide:

• Current mirror proportional to the load current in normal operation, delivering current

proportional to the load according to known ratio named K

• Diagnostics flag in fault conditions delivering fixed voltage VSENSEH

The current delivered by the current sense circuit, ISENSE, can be easily converted to a

voltage VSENSE by using an external sense resistor, RSENSE, allowing continuous load

monitoring and abnormal condition detection.

Normal operation (channel ON, no fault, SEn active)

While device is operating in normal conditions (no fault intervention), VSENSE calculation can

be done using simple equations

Current provided by CS output: ISENSE = IOUT/K

Voltage on RSENSE: VSENSE = RSENSE · ISENSE = RSENSE · IOUT/K

Where:

• VSENSE is voltage measurable on RSENSE resistor

• ISENSE is current provided from CS pin in current output mode

DocID027771 Rev 4 27/42

Application informa tion

VN7008AJ

• IOUT is current flowing through output

• K factor represents the ratio between PowerMOS cells and SenseMOS cells; its

spread includes geometric factor spread, current sense amplifier offset and process

parameters spread of the overall circuitry the specifying ratio between IOUT and ISENSE.

Failure flag indication

In case of power limitation/overtemperature, the fault is indicated by the CS pin which is

switched to a “current limited” voltage source, VSENSEH.

In any case, the current sourced by the CS in this condition is limited to ISENSEH.

The typical behavior in case of overload or hard short circuit is shown in Waveforms

section.

Figure 38: Analogue HSD – open-load detection in off-state

15k

+5V

GND

4.7k

Vbat

Rsense

15k

OUT

ADC in

GND

OUT

100nF

GND

GND GND GND GND GND

100nF/50V

CEXT

GND

10nF/100V

GND

Microcontroller

OUTPUT

Vbat

Rpull-up

External

Pull-Up

switch

Logic

GND

FaultRST

INPUT

SEn

SEL

Currentmirror

OUTPUT

GAPG1201151432CFT

28/42 DocID027771 Rev 4

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Application information

Figure 39: Open -load / short to VCC condition

Table 13: CurrentSense pin levels in off-state

Condition Output CS SEn

Open-load

VOUT > VOL Hi-Z L

VSENSEH H

VOUT < VOL Hi-Z L

0 H

Short to VCC VOUT > VOL Hi-Z L

VSENSEH H

Nominal VOUT < VOL Hi-Z L

0 H

4.4.2 Short to VCC and OFF-state open-load detection

Short to VCC

A sho rt circuit between VCC and output is indicated by the relevant current sense pin set to

VSENSEH during the de vice off-state. Small or no current is delivered by the current sense

during the on-state depending on the nature of the short circuit.

OFF-state open-load with external circuitry

Detection of an open-load in off mode requires an external pull-up resistor RPU connecting

the output to a positive supply voltage VPU.

It is preferable that VPU is switched off during the module standby mode in order to avoid

the overall standby current consumption to increase in normal conditions, i.e. when load is

connected.

DocID027771 Rev 4 29/42

Application informa tion

VN7008AJ

RPU must be selected in order to ensure VOUT > VOLmax in accordance with the following

equation:

Equation

< V

- 4

IL(off2)min @ 4V

30/42 DocID027771 Rev 4

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Package and PCB thermal data

5 Package and PCB thermal data

5.1 PowerSSO-16 thermal data

Figure 40: PowerSSO-16 on two-layers PCB (2s0p to JEDEC JESD 51-5)

Figure 41: PowerSSO-16 on four-layers PCB (2s2p to JEDEC JESD 51-7)

Table 14: PCB properties

Dimension Value

Board finish thickness 1.6 mm +/- 10%

Board dimension 77 mm x 86 mm

Board Material FR4

Copper thickness (top and bottom layers) 0. 070 m m

Copper thickness (inner layers) 0.035 mm

Thermal vias separation 1.2 mm

Thermal via diamet er 0.3 mm +/- 0.08 mm

Copper thickness on vias 0.025 mm

Footprint dimension (top layer) 2.2 mm x 3.9 mm

Heatsink copper area dimension (bottom layer) Footprint, 2 cm2 or 8 cm2

DocID027771 Rev 4 31/42

Package and PCB thermal data

VN7008AJ

Figure 42: Rthj-a m b vs PCB copper area in open box free air conditions

Figure 43: PowerSSO-16 thermal impedance junction ambient single puls e

Equation: pulse calculation formula

ZTHδ = RTH · δ + ZTHtp (1 - δ)

where δ = tP/T

02 4 6810

RTHjamb

GAPG1307151110CFT

RTHj_amb on 4Layer PCB: 20.3°C/W

GAPG1307151113CFT

0.01

0.1

100

0.0001 0.001 0.010.1 1 10 100 1000

(°C/W)

Time (s)

Cu=foot print

Cu=2 cm2

Cu=8 cm2

4 Layer

32/42 DocID027771 Rev 4

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Package and PCB thermal data

Figure 44: Thermal fitting model for PowerSSO-16

The fitting model is a simplified thermal tool and is valid for transient evolutions

where the embedded protections (power limitation or thermal cycling during

thermal shutdown) are not triggered.

Table 15: Thermal par am eters

Area/island (cm2) FP 2 8 4L

R1 (°C/W) 0.3

R2 (°C/W) 1

R3 (°C/W) 7 7 7 5

R4 (°C/W) 16 6 6 4

R5 (°C/W) 30 20 10 3

R6 (°C/W) 26 20 18 7

C1 (W·s/ ° C) 0.0023

C2 (W·s/ ° C) 0.021

C3 (W·s/ ° C) 0.12

C4 (W·s/ ° C) 0.2 0.3 0.3 0.4

C5 (W·s/ ° C) 0.4 1 1 4

C6 (W·s/ ° C) 3 5 7 18

DocID027771 Rev 4 33/42

Maximum demagnetization energy (VCC = 16 V)

VN7008AJ

6 Maximum demagnetization energy (VCC = 16 V)

Figure 45: Maximum turn off current versus inductance

Values are generated with R

= 0 Ω.

In case of repetitive pulses, Tjstart (at the beginning of each demagnetization) of

every pulse must not exceed the temperature specified above for curves A and B.

100

0.1 1 10 100 1000

I (A)

L (mH)

VN7008AJ - Maximumturn off current versus inductance

VN7008AJ - Single Pulse

Repetitive pulse Tjstart=100°C

Repetitive pulse Tjstart=125°C

100

1000

10000

0.01 0.1 1 10 100

E [mJ]

Tdemag [s]

VN7008AJ - Maximum turn off Energyversus Tdemag

VN7008AJ - Single Pulse

Repetitive pulse Tjstart=100°C

Repetitive pulse Tjstart=125°C

GAPG1503161313CFT

34/42 DocID027771 Rev 4

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Package information

7 Package information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®

specifications, grade definitions and product status are available at: www.st.com.

ECOPACK® is an ST trademark.

7.1 PowerSSO-16 package information

Figure 46: PowerSSO-16 package dimensions

Table 16: Po werSSO-16 mec h anica l data

Symbol Millimeters

Min. Typ. Max.

Θ 0°

8°

Θ1 0°

Θ2 5°

15°

Θ3 5°

15°

1.70

A1 0.00

0.10

A2 1.10

1.60

DocID027771 Rev 4 35/42

Package information

VN7008AJ

Symbol Millimeters

Min. Typ. Max.

b 0.20

0.30

b1 0.20 0.25 0.28

c 0.19

0.25

c1 0.19 0.20 0.23

D 4.9 BSC

D1 3.60

4.20

e 0.50 BSC

E 6.00 BSC

E1 3.90 BSC

E2 1.90

2.50

h 0.25

0.50

L 0.40 0.60 0.85

L1 1.00 REF

N 16

R 0.07

R1 0.07

S 0.20

Tolerance of form and position

aaa 0.10

bbb 0.10

ccc 0.08

ddd 0.08

eee 0.10

fff 0.10

ggg 0.15

36/42 DocID027771 Rev 4

VN7008AJ

Package information

7.2 PowerSSO-16 packing inf orm a ti on

Figure 47: PowerSSO-16 reel 13"

Table 17: Reel dimensions

Description Value(1)

Base quantity 2500

Bulk quantity 2500

A (max) 330

B (min) 1.5

C (+0.5, -0.2) 13

D (min) 20.2

N 100

W1 (+2 /-0) 12.4

W2 (max) 18.4

Notes:

(1)All dimensions are in mm.

DocID027771 Rev 4 37/42

Package information

VN7008AJ

Figure 48: PowerSSO-16 carrier tape

Table 18: Po werSSO-16 carrier tape dimensions

Description Value(1)

A0 6.50 ± 0.1

B0 5.25 ± 0.1

K0 2.10 ± 0.1

K1 1.80 ± 0.1

F 5.50 ± 0.1

P1 8.00 ± 0.1

W 12.00 ± 0.3

Notes:

(1)All dimensions are in mm.

Figure 49: PowerSSO-16 schematic drawing of leader and trailer tape

0.30 ±0.05 1.55 ±0.05

1.6±0.1

R 0.5

Typical

2.0 ±0.1

4.0 ±0.1

1.75 ±0.1

SECTION X - X

SECTION Y - Y

REF 4.18

REF 0.6

REF 0.5

Y Y

GAPG2204151242CFT

38/42 DocID027771 Rev 4

VN7008AJ

Package information

7.3 PowerSSO-16 marking informa ti on

Figure 50: PowerSSO-16 marking information

Engineering Samples: these samples can be clearly identified by a dedicated

special symbol in the marking of each unit. These samples are intended to be

used for electrical compatibility evaluation only; usage for any other purpose may

be agreed only upon written authorization by ST. ST is not liable for any customer

usage in production and/or in reliability qualification trials.

Commercial Samples: fully qualified parts from ST standard production with no

usage restrictions.

GAPG0401151415CFT

1234567 8

Special function digit

&: Engineering sample

<blank>: Commercial sample

PowerSSO-16 TOP VIEW

(not in scale)

Marking area

DocID027771 Rev 4 39/42

Order codes

VN7008AJ

8 Order codes

Table 19: Device summary

Package Order codes

Tape and reel

PowerSSO-16 VN7008AJTR

40/42 DocID027771 Rev 4

VN7008AJ

Revision history

9 Revision history

Table 20: Document revision history

Date Revision Changes

23-Apr-2015 1 Initial release

13-Jul-2015 2

Updated Table 4: "Thermal data"

Table 6: "Switchin g":

• WON, WOFF, tSKEW: updated values

Table 7: "Logic Input s" :

• VICL, VFRCL, VSEnCL: updated maximum value

Table 9: "CurrentS ens e":

• Kx, tDSENSE2H, ΔtDSENSE2H: updated values

Updated Section 5.1: "PowerSSO-16 thermal data"

22-Feb-2016 3

Table 3: "Absolute maximum ratings":

• EMAX: updated value

Table 6: "Switchin g":

• td(on), td(off), WON, WOFF, tSKEW: updated values

Table 9: "CurrentS ens e":

• K0, K1: updated values

Added Figur e 4: "IOUT /ISE NSE versus IOU T" and Figure 5: "C urrent

sense accuracy versus IOUT"

Added Sect ion 2.5: "E le ctri cal chara cteristic s curve s" and Section 4:

"Application information"

Updated Section 5.1: "PowerSSO-16 thermal data"

15-Mar-2016 4 Added Section 6: "Maximum demagnetization energy (VCC = 16 V)"

DocID027771 Rev 4 41/42

VN7008AJ

IMPORTANT NOTICE – PLEAS E READ CAREFULLY

STMic r oe lectron ic s NV a nd its s ubsi dia r i es ( “S T”) r eserv e th e r i ght to m ake chan ges, c o r rec t i on s , enh ancemen ts , m od ific atio ns, and

improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST

produc ts befor e placin g orders . ST produc ts are sold pursuant to ST’s terms and c onditions of sa le in pla ce at the ti me of order acknowledgement.

Purchasers are solely responsible for the choic e, selection, and use of S T produc ts and ST as sumes no li abili ty for appli catio n assistance or th e

design of Purchasers’ pr oduc ts.

No license, express or im pl ied, t o any int ellect ual property right i s granted by ST herei n.

Resale of ST products wit h provisions dif ferent from the informa tion set forth herein shall void any warranty granted by ST for such product.

ST and the S T logo are tr ademarks of ST. Al l other product or s ervice names a r e t h e p ro p erty of t he i r respec tiv e ow ne rs.

Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

42/42 DocID027771 Rev 4