Precision, Very Low Noise, Low Input
Bias Current
Operational Amplifiers
AD8671/AD8672/AD8674
Rev. E
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FEATURES
Very low noise: 2.8 nV/√Hz, 77 nV p-p
Wide bandwidth: 10 MHz
Low input bias current: 12 nA max
Low offset voltage: 75 μV max
High open-loop gain: 120 dB min
Low supply current: 3 mA typ per amplifier
Dual-supply operation: ±5 V to ±15 V
Unity-gain stable
No phase reversal
APPLICATIONS
PLL filters
Filters for GPS
Instrumentation
Sensors and controls
Professional quality audio
GENERAL DESCRIPTION
The AD8671/AD8672/AD8674 are very high precision amplifiers
featuring very low noise, very low offset voltage and drift, low
input bias current, 10 MHz bandwidth, and low power
consumption. Outputs are stable with capacitive loads of over
1000 pF. Supply current is less than 3 mA per amplifier at 30 V.
The AD8671/AD8672/AD8674’s combination of ultralow noise,
high precision, speed, and stability is unmatched. The MSOP
version of the AD8671/AD8672 requires only half the board
space of comparable amplifiers.
Applications for these amplifiers include high quality PLL
filters, precision filters, medical and analytical instrumentation,
precision power supply controls, ATE, data acquisition, and
precision controls as well as professional quality audio.
The AD8671/AD8672 are specified over the extended industrial
temperature range (−40°C to +125°C), and the AD8674 is specified
over the industrial temperature range (−40°C to +85°C).
The AD8671/AD8672 are available in the 8-lead SOIC and
8-lead MSOP packages. The AD8674 is available in 14-lead
SOIC and 14-lead TSSOP packages.
Surface-mount devices in MSOP packages are available in tape
and reel only.
PIN CONFIGURATIONS
NC = NO CONNECT
NC 1
IN 2
+
IN 3
V– 4
NC
V+
OUT
NC
8
7
6
5
03718-B-001
AD8671
TOP VIEW
(Not to Scale)
NC = NO CONNECT
NC
1
IN
2
+
IN
3
V–
4
NC
V+
OUT
NC
8
7
6
5
03718-B-002
AD8671
TOP VIEW
(Not to Scale)
Figure 1. 8-Lead SOIC_N (R-8)
Figure 2. 8-Lead MSOP (RM-8)
OUT A
1
–IN A
2
+IN A
3
V–
4
V+
OUT B
–IN B
+IN B
8
7
6
5
03718-B-003
AD8672
TOP VIEW
(Not to Scale)
OUT A
1
–IN A
2
+IN A
3
V–
4
V+
OUT B
–IN B
+IN B
8
7
6
5
03718-B-004
AD8672
TOP VIEW
(Not to Scale)
Figure 3. 8-Lead SOIC-N (R-8)
Figure 4. 8-Lead MSOP (RM-8)
OUT A
1
–IN A
2
+IN A
3
V+
4
+IN B
5
–IN B
6
OUT B
7
OUT D
–IN D
+IN D
V–
14
13
12
11
+IN C
–IN C
OUT C
10
9
8
03718-B-005
AD8674
TOP VIEW
(Not to Scale)
OUT A
1
–IN A
2
+IN A
3
V+
4
+IN B
5
–IN B
6
OUT B
7
OUT D
–IN D
+IN D
V–
14
13
12
11
+IN C
–IN C
OUT C
10
9
8
03718-B-006
AD8674
TOP VIEW
(Not to Scale)
Figure 5. 14-Lead SOIC_N (R-14)
Figure 6. 14-Lead TSSOP (RU-14)
The AD8671, AD8672, and AD8674 are members of a growing
series of low noise op amps offered by Analog Devices, Inc.
Table 1. Voltage Noise
Package 0.9 nV 1.1 nV 1.8 nV 2.8 nV 3.8 nV
Single AD797 AD8597 ADA4004-1 AD8675 AD8671
Dual AD8599 ADA4004-2 AD8676 AD8672
Quad ADA4004-4 AD8674
AD8671/AD8672/AD8674
Rev. E | Page 2 of 20
TABLE OF CONTENTS
Specifications ..................................................................................... 3
Electrical Characteristics, ±5.0 V ............................................... 3
Electrical Characteristics, ±15 V ................................................ 4
Absolute Maximum Ratings ............................................................ 5
ESD Caution .................................................................................. 5
Typical Performance Characteristics ............................................. 6
Applications ..................................................................................... 11
Power Dissipation Calculations ................................................ 11
Unity-Gain Follower Applications ........................................... 11
Output Phase Reversal ............................................................... 12
Total Noise vs. Source Resistance ............................................. 12
Total Harmonic Distortion (THD) and Noise ....................... 13
Driving Capacitive Loads .......................................................... 13
GPS Receiver ............................................................................... 14
Band-Pass Filter .......................................................................... 14
PLL Synthesizers and Loop Filters ........................................... 14
Outline Dimensions ....................................................................... 15
Ordering Guide .......................................................................... 17
REVISION HISTORY
6/10—Rev. D to Rev. E
Added Table 1 and Preceding Sentence ..................................... 1
12/09—Rev. C to Rev. D
Changes to Features and General Description Sections .......... 1
Changes to Absolute Maximum Ratings Section, Table 3,
and Table 4 ................................................................................ 5
Added Power Dissipation Calculations Section ..................... 11
Updated Outline Dimensions ................................................... 15
Changes to Ordering Guide ...................................................... 17
6/05—Rev. B to Rev. C
Changes to Figure 6 ...................................................................... 1
Updated Outline Dimensions ................................................... 14
Changes to Ordering Guide ...................................................... 16
4/04—Rev. A to Rev. B
Changes to Figure 32 .................................................................. 11
Changes to Figures 36, 37, and 38 ............................................ 12
1/04—Rev. 0 to Rev. A
Added AD8672 and AD8674 parts .............................. Universal
Changes to Specifications ............................................................. 3
Deleted Figure 3 ............................................................................. 6
Changes to Figures 7, 8, and 9 ..................................................... 6
Changes to Figure 37 .................................................................. 12
Added new Figure 32 ................................................................. 10
AD8671/AD8672/AD8674
Rev. E | Page 3 of 20
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS, ±5.0 V
VS = ±5.0 V, VCM = 0 V, TA = 25°C, unless otherwise noted.
Table 2.
Parameter Symbol Conditions Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage VOS 20 75 μV
–40°C < TA < +125°C 30 125 μV
Offset Voltage Drift ∆VOS/∆T –40°C < TA < +125°C
AD8671 0.3 0.5 μV/°C
AD8672/AD8674 0.3 0.8 μV/°C
Input Bias Current IB –12 +3 +12 nA
+25°C < TA < +125°C –20 +5 +20 nA
–40°C < TA < +125°C –40 +8 +40 nA
Input Offset Current IOS –12 +6 +12 nA
+25°C < TA < +125°C –20 +6 +20 nA
–40°C < TA < +125°C –40 +8 +40 nA
Input Voltage Range –2.5 +2.5 V
Common-Mode Rejection Ratio CMRR VCM = –2.5 V to +2.5 V 100 120 dB
Large Signal Voltage Gain AVO R
L = 2 kΩ, VO = –3 V to +3 V 1000 6000 V/mV
Input Capacitance, Common Mode CINCM 6.25 pF
Input Capacitance, Differential Mode CINDM 7.5 pF
Input Resistance, Common Mode RIN 3.5
Input Resistance, Differential Mode RINDM 15
OUTPUT CHARACTERISTICS
Output Voltage High VOH R
L = 2 kΩ, –40°C to +125°C +3.8 +4.0 V
Output Voltage Low VOL R
L = 2 kΩ, –40°C to +125°C –3.9 –3.8 V
Output Voltage High VOH R
L = 600 Ω +3.7 +3.9 V
Output Voltage Low VOL R
L = 600 Ω –3.8 –3.7 V
Output Current IOUT ±10 mA
POWER SUPPLY
Power Supply Rejection Ratio PSRR VS = ±4 V to ±18 V
AD8671/AD8672 110 130 dB
AD8674 106 115 dB
Supply Current/Amplifier ISY V
O = 0 V 3 3.5 mA
–40°C < TA < +125°C 4.2 mA
DYNAMIC PERFORMANCE
Slew Rate SR RL = 2 kΩ 4 V/μs
Settling Time tS To 0.1% (4 V step, G = 1) 1.4 μs
To 0.01% (4 V step, G = 1) 5.1 μs
Gain Bandwidth Product GBP 10 MHz
NOISE PERFORMANCE
Peak-to-Peak Noise en p-p 0.1 Hz to 10 Hz 77 100 nV p-p
Voltage Noise Density en f = 1 kHz 2.8 3.8 nV/√Hz
Current Noise Density in f = 1 kHz 0.3 pA/√Hz
Channel Separation
AD8672/AD8674 CS f = 1 kHz –130 dB
f = 10 kHz –105 dB
AD8671/AD8672/AD8674
Rev. E | Page 4 of 20
ELECTRICAL CHARACTERISTICS, ±15 V
VS = ±15 V, VCM = 0 V, TA = 25°C, unless otherwise noted.
Table 3.
Parameter Symbol Conditions Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage VOS 20 75 μV
–40°C < TA < +125°C 30 125 μV
Offset Voltage Drift ∆VOS/∆T –40°C < TA < +125°C
AD8671 0.3 0.5 μV/°C
AD8672/AD8674 0.3 0.8 μV/°C
Input Bias Current IB –12 +3 +12 nA
+25°C < TA < +125°C –20 +5 +20 nA
–40°C < TA < +125°C –40 +8 +40 nA
Input Offset Current IOS –12 +6 +12 nA
+25°C < TA < +125°C –20 +6 +20 nA
–40°C < TA < +125°C –40 +8 +40 nA
Input Voltage Range –12 +12 V
Common-Mode Rejection Ratio CMRR VCM = –12 V to +12 V 100 120 dB
Large Signal Voltage Gain AVO R
L = 2 kΩ, VO = –10 V to +10 V 1000 6000 V/mV
Input Capacitance, Common Mode CINCM 6.25 pF
Input Capacitance, Differential Mode CINDM 7.5 pF
Input Resistance, Common Mode RIN 3.5
Input Resistance, Differential Mode RINDM 15
OUTPUT CHARACTERISTICS
Output Voltage High VOH R
L = 2 kΩ, –40°C to +125°C +13.2 +13.8 V
Output Voltage Low VOL R
L = 2 kΩ, –40°C to +125°C –13.8 –13.2 V
Output Voltage High VOH R
L = 600 Ω +11 +12.3 V
Output Voltage Low VOL R
L = 600 Ω –12.4 –11 V
Output Current IOUT ±20 mA
Short Circuit Current ISC ±30 mA
POWER SUPPLY
Power Supply Rejection Ratio PSRR VS = ±4 V to ±18 V
AD8671/AD8672 110 130 dB
AD8674 106 115 dB
Supply Current/Amplifier ISY V
O = 0 V 3 3.5 mA
–40°C <TA < +125°C 4.2 mA
DYNAMIC PERFORMANCE
Slew Rate SR RL = 2 kΩ 4 V/μs
Settling Time tS To 0.1% (10 V step, G = 1) 2.2 μs
To 0.01% (10 V step, G = 1) 6.3 μs
Gain Bandwidth Product GBP 10 MHz
NOISE PERFORMANCE
Peak-to-Peak Noise en p-p 0.1 Hz to 10 Hz 77 100 nV p-p
Voltage Noise Density en f = 1 kHz 2.8 3.8 nV/√Hz
Current Noise Density in f = 1 kHz 0.3 pA/√Hz
Channel Separation
AD8672/AD8674 CS f = 1 kHz –130 dB
f = 10 kHz –105 dB
AD8671/AD8672/AD8674
Rev. E | Page 5 of 20
ABSOLUTE MAXIMUM RATINGS
Table 4.1
Parameter Rating
Supply Voltage 36 V
Input Voltage VS– to VS+
Differential Input Voltage ±0.7 V
Output Short-Circuit Duration Indefinite
Storage Temperature Range
All Packages –65°C to +150°C
Operating Temperature Range
8-Lead Packages –40°C to +125°C
14-Lead Packages –40°C to +85°C
Junction Temperature Range
All Packages –65°C to +150°C
Lead Temperature Range (Soldering, 60 sec) 300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
See the Applications section for a related discussion on power.
Table 5. Package Characteristics
Package Type θJA1 θ
JC Unit
8-Lead MSOP (RM) 142 44 °C/W
8-Lead SOIC_N (R) 120 43 °C/W
14-Lead SOIC_N (R) 90 36 °C/W
14-Lead TSSOP (RU) 112 35 °C/W
1 Absolute maximum ratings apply at 25°C, unless otherwise noted.
1 θJA is specified for the worst-case conditions, that is., θJA is specified for the
device soldered on a 4-layer circuit board for surface-mount packages.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
AD8671/AD8672/AD8674
Rev. E | Page 6 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
03718-B-007
FREQUENCY (Hz)
VOLTAGE NOISE DENSITY (nV/Hz)
4
8
12
16
20
24
28
32
00 102030405060708090100
V
S
= ±15V
Figure 7. Voltage Noise Density vs. Frequency
03718-B-008
FREQUENCY (kHz)
VOLTAGE NOISE DENSITY (nV/Hz)
0
4.5
9.0
13.5
18.0
22.5
27.0
31.5
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
VS = ±15V
Figure 8. Voltage Noise Density vs. Frequency
03718-B-009
FREQUENCY (kHz)
VOLTAGE NOISE DENSITY (nV/Hz)
0110234567890
2.5
5.0
7.5
10.0
12.5
15.0
17.5
V
S
= ±15V
Figure 9. Voltage Noise Density vs. Frequency
0
5
10
15
20
25
30
35
40
45
–35
VOS (μV)
NUMBER O F AMPLIF IERS
–25 –5–15 0 45–30 –20 –10 5 10 15 20 25 30 35 40
03718-B-010
VS = ±5V
TA = 25°C
Figure 10. Input Offset Voltage Distribution
0
5
10
15
20
25
30
35
–35
V
OS
(μV)
NUMBER OF AMPLIFIE RS
–25 –5–15 0 5030 –20 –10 5 10 15 20 25 30 35 40
03718-B-011
45
V
S
= ±15V
T
A
= 25°C
Figure 11. Input Offset Voltage Distribution
6
7
8
9
10
11
12
13
14
15
16
V
OS
(
μ
V)
TEMPERATURE (°C)
–40 8525 125
03718-B-012
V
S
= ±15V
V
S
= ±5V
Figure 12. Input Offset Voltage vs. Temperature
AD8671/AD8672/AD8674
Rev. E | Page 7 of 20
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
I
B
(nA)
TEMPERATURE (°C)
–40 8525 125
+I
B
–I
B
03718-B-013
V
S
5V
Figure 13. Input Bias Current vs. Temperature
–1.0
–0.5
0
0.5
1.0
1.5
2.0
2.5
I
B
(nA)
TEMPERATURE (°C)
–40 8525 125
+I
B
–I
B
03718-B-014
V
S
= ±15V
Figure 14. Input Bias Current vs. Temperature
2.4
2.6
2.8
3.0
3.2
3.4
I
SY
(mA)
3.6
3.8
4.0
TEMPERATURE (°C)
–40 8525 125
V
S
= ±15V
V
S
5V
03718-B-015
Figure 15. Supply Current vs. Temperature
10.0
10.5
11.0
11.5
12.0
12.5
13.0
13.5
14.0
14.5
OUTPUT VOLTAGE (V)
TEMPERATURE (°C)
–40 8525 125
R
L
= 600
Ω
R
L
= 2k
Ω
03718-B-016
V
S
= ±15V
Figure 16. Output Voltage High vs. Temperature
–14.5
–14.0
–13.5
–13.0
–12.5
–12.0
–11.5
–11.0
OUTPUT VOLTAGE (V)
TEMPERATURE (°C)
–40 8525 125
R
L
= 600
Ω
R
L
= 2k
Ω
03718-B-017
V
S
= ±15V
Figure 17. Output Voltage Low vs. Temperature
FREQUENCY (Hz)
OPEN-LOOP GAIN (dB)
–10
0
10
100k
03718-B-018
10M
1M
–40
–30
–20
20
30
40
50 V
SY
= ±15V
R
L
= 10kΩ
C
L
= 20pF
Φ
M
= 59°
GAIN
PHASE
OPEN-LOOP PHASE (dB)
–45
45
–180
–135
–90
90
135
180
225
0
60 270
Figure 18. Open-Loop Gain and Phase Shift vs. Frequency
AD8671/AD8672/AD8674
Rev. E | Page 8 of 20
0
5000
10000
15000
20000
25000
30000
A
VO
(V/mV)
TEMPERATURE (°C)
–40 8525 125
±5V
±15V
03718-B-019
Figure 19. Open-Loop Gain vs. Temperature
FREQUENCY (Hz)
1k 1M
CLOSED-LOOP GAIN (dB)
–10
0
10
20
40
50
100k10k 10M
03718-B-020
30
–20
–30
–40
–50 100M
A
V
= 100
A
V
= 10
A
V
= 1
V
SY
= ±15V
V
IN
= 10mV
R
L
=
C
L
= 20pF
Figure 20. Closed-Loop Gain vs. Frequency
FREQUENCY (Hz)
1k 10M
IMP EDANCE (Ω)
40
50
60
70
90
100
100k10k 100M
03718-B-021
80
30
20
10
0
A
VO
= 100
100
A
VO
= 10
A
VO
= 1
1M
Figure 21. Output Impedance vs. Frequency
V
SY
= ±15V
V
IN
= 4V
R
L
= 2k
Ω
03718-B-022
VOLTAGE (1V/DIV)
TIME (100
μ
s/DIV)
Figure 22. Large Signal Transient Response
VSY = ±15V
VIN = 200mV p-p
RL = 2kΩ
03718-B-023
VOLTAGE (50mV/DIV)
TIME (10μs/DIV)
Figure 23. Small Signal Transient Response
CAPACITANCE (pF)
1k
SMALL SIGNAL OVERSHOOT (%)
+OS
0
10
20
30
40
50
60
100 10k
–OS
03718-B-024
VS15
Figure 24. Small Signal Overshoot vs. Load Capacitance
AD8671/AD8672/AD8674
Rev. E | Page 9 of 20
V
IN
V
OUT
0V
V
S
= ±15V
V
IN
= 200mV p-p
A
V
= –100
R
L
= 10kΩ
0V
03718-B-025
VOLTAGE (200mV/DIV)
TIME (4μs/DIV)
Figure 25. Positive Overdrive Recovery
V
IN
V
OUT
V
SY
= ±15V
V
IN
= 200mV p-p
A
V
= –100
R
L
= 10kΩ
0V
0V
03718-B-026
VOLTAGE (200mV/DIV)
TIME (4μs/DIV)
Figure 26. Negative Overdrive Recovery
FREQUENCY (Hz)
1k 1M
CMRR (dB)
40
60
80
100
140
160
100k10k 10M
03718-B-027
120
20
0
–20
–40 100M
V
SY
= ±15V
100
10
Figure 27. CMRR vs. Frequency
FREQUENCY (Hz)
1k 1M
PSRR (dB)
40
60
80
100
140
160
100k10k 10M
03718-B-028
120
20
0
–20
–40
V
SY
= ±15V
100
–PSRR
+PSRR
10
Figure 28. PSRR vs. Frequency
127
128
129
130
131
132
PSRR (dB)
133
134
135
TEMPERATURE (°C)
–40 8525 125
03718-B-029
V
S
= ±2.5V TO ±18V
Figure 29. PSRR vs. Temperature
03718-B-030
V
S
= ±15V
TIME (1μs/DIV)
VOLTAGE NOISE (50nV/DIV)
Figure 30. 0.1 Hz to 10 Hz Input Voltage Noise
AD8671/AD8672/AD8674
Rev. E | Page 10 of 20
FREQUENCY (Hz)
CHANNEL SEPARATION (dB)
100
–120
–40
–20
0
1k 10k 100k 1M
–60
–140
–80
–100
10M 100M
03718-B-031
V
S
= ±15V, ±5V
Figure 31. Channel Separation
AD8671/AD8672/AD8674
Rev. E | Page 11 of 20
APPLICATIONS
POWER DISSIPATION CALCULATIONS
To achieve low voltage noise in a bipolar op amp, the current
must be increased. The emitter-base theoretical voltage noise is
approximately
HznV/
2
109
C
nqI
kTe =
To achieve the low voltage noise of 2.8 nV/√Hz, the input stage
current is higher than most op amps with an equivalent gain
bandwidth product. The thermal noise of a 1 k resistor is
4 nV/√Hz, which is higher than the voltage noise of AD8671
family. Low voltage noise requires using low values of resistors,
so low voltage noise op amps should have good drive capability,
such as a 600  load. This means that the second stage and
output stage are also biased at higher currents. As a result, the
supply current of a single op amp is 3.5 mA maximum at room
temperature.
Junction temperature has a direct affect on reliability. For more
information, visit the following Analog Devices, Inc., website:
http://www.analog.com/en/quality-and-reliability/reliability-
data/content/index.html
MTTF and FIT calculations can be done based on the junction
temperature and IC process. Use the following equation to
determine the junction temperature:
TJ = TA + PD × θJA
For the AD8671 single in the 8-lead MSOP package, the thermal
resistance, θJA, is 142°C/W. If the ambient temperature is 30°C
and the supply voltages are ±12 V, the power dissipation is
24 V × 3.5 mA = 84 mW
Therefore, the rise above ambient temperature is
84 mW × 142°C/W = 12°C
If the ambient temperature is 30°C, the junction temperature is
42°C. The previously mentioned website that details the effect
of the junction temperature on reliability has a calculator that
requires only the part number and the junction temperature to
determine the process technology.
For the AD8674 single in the 14-Lead TSSOP package, the thermal
resistance, θJA, is 112°C/W. Although θJA is lower than it is for the
8-lead package, the four op amps are powered simultaneously. If
the ambient temperature is 50°C and the supply voltages are ±15 V,
the power dissipation is
30 V × 4.2 mA × four op amps = 504 mW
Therefore, the rise above ambient temperature is
504 mW × 112°C/W = 56°C
With an ambient temperature of 50°C, the junction temperature
is 106°C. This is less than the specified absolute maximum junction
temperature, but for systems with long product lifetimes (years),
this should be considered carefully.
Note that these calculations do not include the additional
dissipation caused by the load current on each op amp. Possible
solutions to reduce junction temperature include system level
considerations such as fans, Peltier thermoelectric coolers, and
heat pipes. Board considerations include operation on lower
voltages, such as ±12 V or ±5 V, and using two dual op amps
instead of one quad op amp. If the extremely low voltage noise
and high gain bandwidth is not required, using other quad op
amps, such as ADA4091-4, OP4177, ADA4004-4, OP497, or
AD704 can be considered.
UNITY-GAIN FOLLOWER APPLICATIONS
When large transient pulses (>1 V) are applied at the positive
terminal of amplifiers (such as the OP27, LT1007, OPA227, and
AD8671) with back-to-back diodes at the input stage, the use of
a resistor in the feedback loop is recommended to avoid having
the amplifier load the signal generator. The feedback resistor,
RF, should be at least 500 Ω. However, if large values must be
used for RF, a small capacitor, CF, should be inserted in parallel
with RF to compensate for the pole introduced by the input
capacitance and RF.
Figure 32 shows the uncompensated output response with a
10 kΩ resistor in the feedback and the compensated response
with CF = 15 pF.
03718-B-032
REF1 + OVER
23.23%
CH2 +OV ER
7.885%
VOL TAGE (1V/ DIV)
OUT PUT UNCO MP E NSAT ED
OUTPUT
COMPENSATED
TI M E ( 100n s/DIV )
Figure 32. Transient Output Response
AD8671/AD8672/AD8674
Rev. E | Page 12 of 20
OUTPUT PHASE REVERSAL
Phase reversal is a change of polarity in the amplifier transfer
function that occurs when the input voltage exceeds the supply
voltage. The AD8671/AD8672/AD8674 do not exhibit phase
reversal even when the input voltage is 1 V beyond the supplies.
V
SY
= ±15V
V
IN
V
OUT
03718-B-033
TIME (10μs/DIV)
VOLTAGE (1V/DIV)
Figure 33. Output Phase Reversal
TOTAL NOISE VS. SOURCE RESISTANCE
The low input voltage noise of the AD8671/AD8672/AD8674
makes them a great choice for applications with low source
resistance. However, because they have low input current noise,
they can also be used in circuits with substantial source
resistance.
Figure 34 shows the voltage noise, current noise, thermal noise,
and total rms noise of the AD8671 as a function of the source
resistance.
For RS < 475 Ω, the input voltage noise, en, dominates.
For 475 Ω < RS < 412 kΩ, thermal noise dominates.
For RS > 412 kΩ, the input current noise dominates.
10 1k
TOTAL NOISE (nV/
Hz)
1
10
100
1000
100 10k
03718-B-034
100k 1M
e
n_t
C
AB
e
n
i
n
(4kR
S
T)
1/2
SOURCE RESISTANCE (Ω)
Figure 34. Noise vs. Source Resistance
AD8671/AD8672/AD8674
Rev. E | Page 13 of 20
03718-B-036
VSY = ±15V
RL = 2kΩ
CL = 1nF
VIN = 100mV
AV = +1 CH2 +OVER
39.80%
CH2 –OVER
39.80%
TIME (10μs/DIV)
VOLTAGE (500mV/DIV)
TOTAL HARMONIC DISTORTION (THD) AND NOISE
The AD8671/AD8672/AD8674 exhibit low total harmonic
distortion (THD) over the entire audio frequency range. This
makes them suitable for applications with high closed-loop
gains, including audio applications. Figure 35 shows
approximately 0.0006% of THD + N in a positive unity gain, the
worst-case configuration for distortion.
Hz
100 1k 10k
PERCENTAGE
LT1007
0.0001
0.0002
0.0005
0.0010
0.0020
0.0050
0.0100
0.0200
0.0500
0.1000
5020 500200 5k
2k
AD8671
20k
03718-B-035
V
S
= ±5V
V
IN
= 2.5V
R
L
= 600Ω
Figure 36. AD8671 Capacitive Load Drive
500Ω
R
F
V
CC
220pF
C
F
V
IN
V
EE
R
G
500Ω
10Ω
R
S
1nF
C
L
03718-B-037
2kΩ
R
L
Figure 35. Total Harmonic Distortion and Noise
Figure 37. Recommended Capacitive Load Circuit
DRIVING CAPACITIVE LOADS
The AD8671/AD8672/AD8674 can drive large capacitive loads
without causing instability. However, when configured in unity
gain, driving very large loads can cause unwanted ringing or
instability.
03718-B-038
V
SY
= ±15V
R
L
= 2kΩ
C
L
= 1nF
C
F
= 220p F
V
IN
= 100mV
A
V
= +2 CH2 +OVER
5.051%
CH2 –OVER
6.061%
TIME (10μs/DIV)
VOLTAGE (100mV/DIV)
Figure 36 shows the output of the AD8671 with a capacitive
load of 1 nF. If heavier loads are used in low closed-loop gain or
unity-gain configurations, it is recommended to use external
compensation as shown in the circuit in Figure 37. This
technique reduces the overshoot and prevents the op amp from
oscillation. The trade-off of this circuit is a reduction in output
swing. However, a great added benefit stems from the fact that
the input signal and the op amps noise are filtered, and thus the
overall output noise is kept to a minimum.
Figure 38. Compensated Load Drive
The output response of the circuit is shown in Figure 38.
AD8671/AD8672/AD8674
Rev. E | Page 14 of 20
AD8671
BAND-PASS FILTER
LOW NOISE OP AMP MIXER DEMODULATOR LOW-PASS FILTER VGA
ADC
AD10200
AD831
AD8671
AD630 AD8610 AD8369
CODE GENERATOR
03718-B-039
Figure 39. Simplified Block Diagram of a GPS Receiver
GPS RECEIVER
GPS receivers require low noise to minimize RF effects. The
precision of the AD8671 makes it an excellent choice for such
applications. Its very low noise and wide bandwidth make it
suitable for band-pass and low-pass filters without the penalty
of high power consumption.
Figure 39 shows a simplified block diagram of a GPS receiver.
The next section details the design equations.
BAND-PASS FILTER
Filters are useful in many applications; for example, band-pass
filters are used in GPS systems, as discussed in the previous
section. Figure 40 shows a second-order band-pass KRC filter.
18kΩ
10kΩ
2.25kΩ
R3
R
B
R
A
V
CC
V
EE
2.25kΩ
R2
2.25kΩ
R1
1nF
C2
V
IN
1nF
C2
03718-B-040
Figure 40. Band-Pass KRC Filter
The equal component topology yields a center frequency
R
C
fo π
=2
2
and
K
Q
=4
2
where:
A
B
R
R
K+=1
The band-pass response is shown in Figure 41.
Hz
100k1k100 10k 1M
03718-B-041
10M
V
S
= ±15V
200
μ
V/DIV
Figure 41. Band-Pass Response
PLL SYNTHESIZERS AND LOOP FILTERS
Phase-lock loop filters are used in AM/FM modulation.
Loop filters in PLL design require accuracy and care in their
implementation. The AD8671/AD8672/AD8674 are ideal
candidates for such filter design; the low offset voltage and low
input bias current minimize the output error. In addition to the
excellent dc specifications, the AD8671/AD8672/AD8674 have
a unique performance at high frequencies; the high open-loop
gain and wide bandwidth allow the user to design a filter with a
high closed-loop gain if desirable. To optimize the filter design,
it is recommended to use small value resistors to minimize the
thermal noise. A simple example is shown in Figure 42.
10kΩ
R1
V
CC
V
EE
1nF
03718-B-042
VCO
C1
CHARGE
PUMP
PHASE
DETECTOR
IN
D
Figure 42. PLL Filter Simplified Block Diagram
AD8671/AD8672/AD8674
Rev. E | Page 15 of 20
OUTLINE DIMENSIONS
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLYAND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-AA
012407-A
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099) 45°
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
4
1
85
5.00(0.1968)
4.80(0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2441)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
Figure 43. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
COMPLIANT TO JEDEC STANDARDS MO-187-AA
100709-B
0.80
0.55
0.40
4
8
1
5
0.65 BSC
0.40
0.25
1.10 MAX
3.20
3.00
2.80
COPLANARITY
0.10
0.23
0.09
3.20
3.00
2.80
5.15
4.90
4.65
PIN 1
IDENTIFIER
15° MAX
0.95
0.85
0.75
0.15
0.05
Figure 44. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
AD8671/AD8672/AD8674
Rev. E | Page 16 of 20
CONTROLLING DIMENSIONSARE IN MILLIMETERS; INCH DIMENSIONS
(I N PARENTHESES) ARE ROUNDED-OFF MIL LIM E TER EQUIVALE NTS F OR
REFE RE NCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMP LI ANT TO JE DE C S TANDARDS MS-012-AB
060606-A
14 8
7
1
6.20 ( 0.2441)
5.80 ( 0.2283)
4.00 ( 0.1575)
3.80 ( 0.1496)
8.75 ( 0.3445)
8.55 ( 0.3366)
1.27 ( 0.0500)
BSC
SEATING
PLANE
0.25 ( 0.0098)
0.10 ( 0.0039)
0.51 ( 0.0201)
0.31 ( 0.0122)
1.75 ( 0.0689)
1.35 ( 0.0531)
0.50 ( 0.0197)
0.25 ( 0.0098)
1.27 ( 0.0500)
0.40 ( 0.0157)
0.25 ( 0.0098)
0.17 ( 0.0067)
COPLANARITY
0.10
45°
Figure 45. 14-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-14)
Dimensions shown in millimeters and (inches)
COMP LI ANT TO JEDEC STANDARDS M O-153-AB- 1
061908-A
4.50
4.40
4.30
14 8
7
1
6.40
BSC
PIN 1
5.10
5.00
4.90
0.65 BS C
0.15
0.05 0.30
0.19
1.20
MAX
1.05
1.00
0.80 0.20
0.09 0.75
0.60
0.45
COPLANARITY
0.10
SEATING
PLANE
Figure 46. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
AD8671/AD8672/AD8674
Rev. E | Page 17 of 20
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option Branding
AD8671AR –40°C to +125°C 8-Lead SOIC_N R-8
AD8671AR-REEL –40°C to +125°C 8-Lead SOIC_N R-8
AD8671AR-REEL7 –40°C to +125°C 8-Lead SOIC_N R-8
AD8671ARZ –40°C to +125°C 8-Lead SOIC_N R-8
AD8671ARZ-REEL –40°C to +125°C 8-Lead SOIC_N R-8
AD8671ARZ-REEL7 –40°C to +125°C 8-Lead SOIC_N R-8
AD8671ARMZ –40°C to +125°C 8-Lead MSOP RM-8 A0V
AD8671ARMZ-REEL –40°C to +125°C 8-Lead MSOP RM-8 A0V
AD8672AR –40°C to +125°C 8-Lead SOIC_N R-8
AD8672AR-REEL –40°C to +125°C 8-Lead SOIC_N R-8
AD8672AR-REEL7 –40°C to +125°C 8-Lead SOIC_N R-8
AD8672ARZ –40°C to +125°C 8-Lead SOIC_N R-8
AD8672ARZ-REEL –40°C to +125°C 8-Lead SOIC_N R-8
AD8672ARZ-REEL7 –40°C to +125°C 8-Lead SOIC_N R-8
AD8672ARMZ –40°C to +125°C 8-Lead MSOP RM-8 A0W
AD8672ARMZ-REEL –40°C to +125°C 8-Lead MSOP RM-8 A0W
AD8674AR –40°C to +85°C 14-Lead SOIC_N R-14
AD8674ARZ –40°C to +85°C 14-Lead SOIC_N R-14
AD8674ARZ-REEL –40°C to +85°C 14-Lead SOIC_N R-14
AD8674ARZ-REEL7 –40°C to +85°C 14-Lead SOIC_N R-14
AD8674ARU –40°C to +85°C 14-Lead TSSOP RU-14
AD8674ARUZ –40°C to +85°C 14-Lead TSSOP RU-14
AD8674ARUZ-REEL –40°C to +85°C 14-Lead TSSOP RU-14
1 Z = RoHS Compliant Part.
AD8671/AD8672/AD8674
Rev. E | Page 18 of 20
NOTES
AD8671/AD8672/AD8674
Rev. E | Page 19 of 20
NOTES
AD8671/AD8672/AD8674
Rev. E | Page 20 of 20
NOTES
©2004–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D03718–0–6/10(E)