K10P64M72SF1
K10 Sub-Family
Supports: MK10DX64VLH7,
MK10DX128VLH7, MK10DX256VLH7
Features
•Operating Characteristics
–Voltage range: 1.71 to 3.6 V
– Flash write voltage range: 1.71 to 3.6 V
– Temperature range (ambient): -40 to 105°C
•Clocks
– 3 to 32 MHz crystal oscillator
– 32 kHz crystal oscillator
– Multi-purpose clock generator
•System peripherals
– Multiple low-power modes to provide power
optimization based on application requirements
– 16-channel DMA controller, supporting up to 63
request sources
– External watchdog monitor
– Software watchdog
– Low-leakage wakeup unit
•Security and integrity modules
– Hardware CRC module to support fast cyclic
redundancy checks
– 128-bit unique identification (ID) number per chip
•Human-machine interface
– Low-power hardware touch sensor interface (TSI)
– General-purpose input/output
•Analog modules
– Two 16-bit SAR ADCs
– Programmable gain amplifier (PGA) (up to x64)
integrated into each ADC
– 12-bit DAC
– Three analog comparators (CMP) containing a 6-bit
DAC and programmable reference input
– Voltage reference
•Timers
– Programmable delay block
– Eight-channel motor control/general purpose/PWM
timer
– Two 2-channel quadrature decoder/general purpose
timers
– Periodic interrupt timers
– 16-bit low-power timer
– Carrier modulator transmitter
– Real-time clock
•Communication interfaces
– Controller Area Network (CAN) module
– SPI module
– Two I2C modules
– Three UART modules
– I2S module
Freescale Semiconductor Document Number: K10P64M72SF1
Data Sheet: Technical Data Rev. 3, 11/2012
Freescale reserves the right to change the detail specifications as may be
required to permit improvements in the design of its products.
© 2012 Freescale Semiconductor, Inc.
Table of Contents
1 Ordering parts...........................................................................3
1.1 Determining valid orderable parts......................................3
2 Part identification......................................................................3
2.1 Description.........................................................................3
2.2 Format...............................................................................3
2.3 Fields.................................................................................3
2.4 Example............................................................................4
3Terminology and guidelines......................................................4
3.1 Definition: Operating requirement......................................4
3.2 Definition: Operating behavior...........................................5
3.3 Definition: Attribute............................................................5
3.4 Definition: Rating...............................................................6
3.5 Result of exceeding a rating..............................................6
3.6 Relationship between ratings and operating
requirements......................................................................6
3.7 Guidelines for ratings and operating requirements............7
3.8 Definition: Typical value.....................................................7
3.9 Typical value conditions....................................................8
4Ratings......................................................................................9
4.1 Thermal handling ratings...................................................9
4.2 Moisture handling ratings..................................................9
4.3 ESD handling ratings.........................................................9
4.4 Voltage and current operating ratings...............................9
5General.....................................................................................10
5.1 AC electrical characteristics..............................................10
5.2 Nonswitching electrical specifications...............................10
5.2.1 Voltage and current operating requirements.........10
5.2.2 LVD and POR operating requirements.................11
5.2.3 Voltage and current operating behaviors..............12
5.2.4 Power mode transition operating behaviors..........13
5.2.5 Power consumption operating behaviors..............14
5.2.6 Designing with radiated emissions in mind...........18
5.2.7 Capacitance attributes..........................................18
5.3 Switching specifications.....................................................19
5.3.1 Device clock specifications...................................19
5.3.2 General switching specifications...........................19
5.4 Thermal specifications.......................................................20
5.4.1 Thermal operating requirements...........................20
5.4.2 Thermal attributes.................................................21
6 Peripheral operating requirements and behaviors....................21
6.1 Core modules....................................................................22
6.1.1 Debug trace timing specifications.........................22
6.1.2 JTAG electricals....................................................22
6.2 System modules................................................................25
6.3 Clock modules...................................................................25
6.3.1 MCG specifications...............................................25
6.3.2 Oscillator electrical specifications.........................27
6.3.3 32 kHz Oscillator Electrical Characteristics...........30
6.4 Memories and memory interfaces.....................................30
6.4.1 Flash electrical specifications................................30
6.4.2 EzPort Switching Specifications............................35
6.4.3 Flexbus Switching Specifications..........................36
6.5 Security and integrity modules..........................................39
6.6 Analog...............................................................................39
6.6.1 ADC electrical specifications.................................39
6.6.2 CMP and 6-bit DAC electrical specifications.........47
6.6.3 12-bit DAC electrical characteristics.....................49
6.6.4 Voltage reference electrical specifications............52
6.7 Timers................................................................................53
6.8 Communication interfaces.................................................53
6.8.1 CAN switching specifications................................53
6.8.2 DSPI switching specifications (limited voltage
range)....................................................................54
6.8.3 DSPI switching specifications (full voltage range).55
6.8.4 I2C switching specifications..................................57
6.8.5 UART switching specifications..............................57
6.8.6 I2S/SAI Switching Specifications..........................57
6.9 Human-machine interfaces (HMI)......................................61
6.9.1 TSI electrical specifications...................................61
7 Dimensions...............................................................................62
7.1 Obtaining package dimensions.........................................62
8 Pinout........................................................................................63
8.1 K10 Signal Multiplexing and Pin Assignments..................63
8.2 K10 Pinouts.......................................................................65
9 Revision History........................................................................67
K10 Sub-Family Data Sheet, Rev. 3, 11/2012.
2 Freescale Semiconductor, Inc.
1 Ordering parts
1.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable part
numbers for this device, go to www.freescale.com and perform a part number search for
the following device numbers: PK10 and MK10 .
2 Part identification
2.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
2.2 Format
Part numbers for this device have the following format:
Q K## A M FFF R T PP CC N
2.3 Fields
This table lists the possible values for each field in the part number (not all combinations
are valid):
Field Description Values
Q Qualification status • M = Fully qualified, general market flow
• P = Prequalification
K## Kinetis family • K10
A Key attribute • D = Cortex-M4 w/ DSP
• F = Cortex-M4 w/ DSP and FPU
M Flash memory type • N = Program flash only
• X = Program flash and FlexMemory
Table continues on the next page...
Ordering parts
K10 Sub-Family Data Sheet, Rev. 3, 11/2012.
Freescale Semiconductor, Inc. 3
Field Description Values
FFF Program flash memory size • 32 = 32 KB
• 64 = 64 KB
• 128 = 128 KB
• 256 = 256 KB
• 512 = 512 KB
• 1M0 = 1 MB
R Silicon revision • Z = Initial
• (Blank) = Main
• A = Revision after main
T Temperature range (°C) • V = –40 to 105
• C = –40 to 85
PP Package identifier • FM = 32 QFN (5 mm x 5 mm)
• FT = 48 QFN (7 mm x 7 mm)
• LF = 48 LQFP (7 mm x 7 mm)
• LH = 64 LQFP (10 mm x 10 mm)
• MP = 64 MAPBGA (5 mm x 5 mm)
• LK = 80 LQFP (12 mm x 12 mm)
• LL = 100 LQFP (14 mm x 14 mm)
• MC = 121 MAPBGA (8 mm x 8 mm)
• LQ = 144 LQFP (20 mm x 20 mm)
• MD = 144 MAPBGA (13 mm x 13 mm)
• MJ = 256 MAPBGA (17 mm x 17 mm)
CC Maximum CPU frequency (MHz) • 5 = 50 MHz
• 7 = 72 MHz
• 10 = 100 MHz
• 12 = 120 MHz
• 15 = 150 MHz
N Packaging type • R = Tape and reel
• (Blank) = Trays
2.4 Example
This is an example part number:
MK10DN512ZVMD10
3 Terminology and guidelines
3.1 Definition: Operating requirement
An operating requirement is a specified value or range of values for a technical
characteristic that you must guarantee during operation to avoid incorrect operation and
possibly decreasing the useful life of the chip.
Terminology and guidelines
K10 Sub-Family Data Sheet, Rev. 3, 11/2012.
4 Freescale Semiconductor, Inc.
3.1.1 Example
This is an example of an operating requirement, which you must meet for the
accompanying operating behaviors to be guaranteed:
Symbol Description Min. Max. Unit
VDD 1.0 V core supply
voltage
0.9 1.1 V
3.2 Definition: Operating behavior
An operating behavior is a specified value or range of values for a technical
characteristic that are guaranteed during operation if you meet the operating requirements
and any other specified conditions.
3.2.1 Example
This is an example of an operating behavior, which is guaranteed if you meet the
accompanying operating requirements:
Symbol Description Min. Max. Unit
IWP Digital I/O weak pullup/
pulldown current
10 130 µA
3.3 Definition: Attribute
An attribute is a specified value or range of values for a technical characteristic that are
guaranteed, regardless of whether you meet the operating requirements.
3.3.1 Example
This is an example of an attribute:
Symbol Description Min. Max. Unit
CIN_D Input capacitance:
digital pins
— 7 pF
Terminology and guidelines
K10 Sub-Family Data Sheet, Rev. 3, 11/2012.
Freescale Semiconductor, Inc. 5
3.4 Definition: Rating
A rating is a minimum or maximum value of a technical characteristic that, if exceeded,
may cause permanent chip failure:
•Operating ratings apply during operation of the chip.
•Handling ratings apply when the chip is not powered.
3.4.1 Example
This is an example of an operating rating:
Symbol Description Min. Max. Unit
VDD 1.0 V core supply
voltage
–0.3 1.2 V
3.5 Result of exceeding a rating
40
30
20
10
0
Measured characteristic
Operating rating
Failures in time (ppm)
The likelihood of permanent chip failure increases rapidly as
soon as a characteristic begins to exceed one of its operating ratings.
Terminology and guidelines
K10 Sub-Family Data Sheet, Rev. 3, 11/2012.
6 Freescale Semiconductor, Inc.
3.6 Relationship between ratings and operating requirements
–∞
- No permanent failure
- Correct operation
Normal operating range
Fatal range
Expected permanent failure
Fatal range
Expected permanent failure
∞
Operating rating (max.)
Operating requirement (max.)
Operating requirement (min.)
Operating rating (min.)
Operating (power on)
Degraded operating range Degraded operating range
–∞
No permanent failure
Handling range
Fatal range
Expected permanent failure
Fatal range
Expected permanent failure
∞
Handling rating (max.)
Handling rating (min.)
Handling (power off)
- No permanent failure
- Possible decreased life
- Possible incorrect operation
- No permanent failure
- Possible decreased life
- Possible incorrect operation
3.7 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
• Never exceed any of the chip’s ratings.
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal
operation (for example, during power sequencing), limit the duration as much as
possible.
3.8 Definition: Typical value
A typical value is a specified value for a technical characteristic that:
• Lies within the range of values specified by the operating behavior
• Given the typical manufacturing process, is representative of that characteristic
during operation when you meet the typical-value conditions or other specified
conditions
Typical values are provided as design guidelines and are neither tested nor guaranteed.
Terminology and guidelines
K10 Sub-Family Data Sheet, Rev. 3, 11/2012.
Freescale Semiconductor, Inc. 7
3.8.1 Example 1
This is an example of an operating behavior that includes a typical value:
Symbol Description Min. Typ. Max. Unit
IWP Digital I/O weak
pullup/pulldown
current
10 70 130 µA
3.8.2 Example 2
This is an example of a chart that shows typical values for various voltage and
temperature conditions:
0.90 0.95 1.00 1.05 1.10
0
500
1000
1500
2000
2500
3000
3500
4000
4500
5000
150 °C
105 °C
25 °C
–40 °C
VDD (V)
I(μA)
DD_STOP
TJ
3.9 Typical value conditions
Typical values assume you meet the following conditions (or other conditions as
specified):
Symbol Description Value Unit
TAAmbient temperature 25 °C
VDD 3.3 V supply voltage 3.3 V
Terminology and guidelines
K10 Sub-Family Data Sheet, Rev. 3, 11/2012.
8 Freescale Semiconductor, Inc.
4 Ratings
4.1 Thermal handling ratings
Symbol Description Min. Max. Unit Notes
TSTG Storage temperature –55 150 °C 1
TSDR Solder temperature, lead-free — 260 °C 2
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
4.2 Moisture handling ratings
Symbol Description Min. Max. Unit Notes
MSL Moisture sensitivity level — 3 — 1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
4.3 ESD handling ratings
Symbol Description Min. Max. Unit Notes
VHBM Electrostatic discharge voltage, human body model -2000 +2000 V 1
VCDM Electrostatic discharge voltage, charged-device model -500 +500 V 2
ILAT Latch-up current at ambient temperature of 105°C -100 +100 mA
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body
Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
4.4 Voltage and current operating ratings
Symbol Description Min. Max. Unit
VDD Digital supply voltage –0.3 3.8 V
Table continues on the next page...
Ratings
K10 Sub-Family Data Sheet, Rev. 3, 11/2012.
Freescale Semiconductor, Inc. 9
Symbol Description Min. Max. Unit
IDD Digital supply current — 185 mA
VDIO Digital input voltage (except RESET, EXTAL, and XTAL) –0.3 5.5 V
VAIO Analog1, RESET, EXTAL, and XTAL input voltage –0.3 VDD + 0.3 V
IDMaximum current single pin limit (applies to all digital pins) –25 25 mA
VDDA Analog supply voltage VDD – 0.3 VDD + 0.3 V
VBAT RTC battery supply voltage –0.3 3.8 V
1. Analog pins are defined as pins that do not have an associated general purpose I/O port function.
5 General
5.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
Figure 1. Input signal measurement reference
All digital I/O switching characteristics assume:
1. output pins
• have CL=30pF loads,
• are configured for fast slew rate (PORTx_PCRn[SRE]=0), and
• are configured for high drive strength (PORTx_PCRn[DSE]=1)
2. input pins
• have their passive filter disabled (PORTx_PCRn[PFE]=0)
5.2 Nonswitching electrical specifications
General
K10 Sub-Family Data Sheet, Rev. 3, 11/2012.
10 Freescale Semiconductor, Inc.
5.2.1 Voltage and current operating requirements
Table 1. Voltage and current operating requirements
Symbol Description Min. Max. Unit Notes
VDD Supply voltage 1.71 3.6 V
VDDA Analog supply voltage 1.71 3.6 V
VDD – VDDA VDD-to-VDDA differential voltage –0.1 0.1 V
VSS – VSSA VSS-to-VSSA differential voltage –0.1 0.1 V
VBAT RTC battery supply voltage 1.71 3.6 V
VIH Input high voltage
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
0.7 × VDD
0.75 × VDD
—
—
V
V
VIL Input low voltage
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
—
—
0.35 × VDD
0.3 × VDD
V
V
VHYS Input hysteresis 0.06 × VDD — V
IICDIO Digital pin negative DC injection current — single pin
• VIN < VSS-0.3V -5 — mA
1
IICAIO Analog2, EXTAL, and XTAL pin DC injection current —
single pin
• VIN < VSS-0.3V (Negative current injection)
• VIN > VDD+0.3V (Positive current injection)
-5
—
—
+5
mA
3
IICcont Contiguous pin DC injection current —regional limit,
includes sum of negative injection currents or sum of
positive injection currents of 16 contiguous pins
• Negative current injection
• Positive current injection
-25
—
—
+25
mA
VRAM VDD voltage required to retain RAM 1.2 — V
VRFVBAT VBAT voltage required to retain the VBAT register file VPOR_VBAT — V
1. All 5 V tolerant digital I/O pins are internally clamped to VSS through a ESD protection diode. There is no diode connection
to VDD. If VIN greater than VDIO_MIN (=VSS-0.3V) is observed, then there is no need to provide current limiting resistors at
the pads. If this limit cannot be observed then a current limiting resistor is required. The negative DC injection current
limiting resistor is calculated as R=(VDIO_MIN-VIN)/|IIC|.
2. Analog pins are defined as pins that do not have an associated general purpose I/O port function.
3. All analog pins are internally clamped to VSS and VDD through ESD protection diodes. If VIN is greater than VAIO_MIN
(=VSS-0.3V) and VIN is less than VAIO_MAX(=VDD+0.3V) is observed, then there is no need to provide current limiting
resistors at the pads. If these limits cannot be observed then a current limiting resistor is required. The negative DC
injection current limiting resistor is calculated as R=(VAIO_MIN-VIN)/|IIC|. The positive injection current limiting resistor is
calculated as R=(VIN-VAIO_MAX)/|IIC|. Select the larger of these two calculated resistances.
General
K10 Sub-Family Data Sheet, Rev. 3, 11/2012.
Freescale Semiconductor, Inc. 11
5.2.2 LVD and POR operating requirements
Table 2. VDD supply LVD and POR operating requirements
Symbol Description Min. Typ. Max. Unit Notes
VPOR Falling VDD POR detect voltage 0.8 1.1 1.5 V
VLVDH Falling low-voltage detect threshold — high
range (LVDV=01)
2.48 2.56 2.64 V
VLVW1H
VLVW2H
VLVW3H
VLVW4H
Low-voltage warning thresholds — high range
• Level 1 falling (LVWV=00)
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11)
2.62
2.72
2.82
2.92
2.70
2.80
2.90
3.00
2.78
2.88
2.98
3.08
V
V
V
V
1
VHYSH Low-voltage inhibit reset/recover hysteresis —
high range
— ±80 — mV
VLVDL Falling low-voltage detect threshold — low range
(LVDV=00)
1.54 1.60 1.66 V
VLVW1L
VLVW2L
VLVW3L
VLVW4L
Low-voltage warning thresholds — low range
• Level 1 falling (LVWV=00)
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11)
1.74
1.84
1.94
2.04
1.80
1.90
2.00
2.10
1.86
1.96
2.06
2.16
V
V
V
V
1
VHYSL Low-voltage inhibit reset/recover hysteresis —
low range
— ±60 — mV
VBG Bandgap voltage reference 0.97 1.00 1.03 V
tLPO Internal low power oscillator period — factory
trimmed
900 1000 1100 μs
1. Rising thresholds are falling threshold + hysteresis voltage
Table 3. VBAT power operating requirements
Symbol Description Min. Typ. Max. Unit Notes
VPOR_VBAT Falling VBAT supply POR detect voltage 0.8 1.1 1.5 V
General
K10 Sub-Family Data Sheet, Rev. 3, 11/2012.
12 Freescale Semiconductor, Inc.
5.2.3 Voltage and current operating behaviors
Table 4. Voltage and current operating behaviors
Symbol Description Min. Max. Unit Notes
VOH Output high voltage — high drive strength
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -9mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -3mA
VDD – 0.5
VDD – 0.5
—
—
V
V
Output high voltage — low drive strength
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -2mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -0.6mA
VDD – 0.5
VDD – 0.5
—
—
V
V
IOHT Output high current total for all ports — 100 mA
VOL Output low voltage — high drive strength
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 9mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 3mA
—
—
0.5
0.5
V
V
Output low voltage — low drive strength
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 2mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 0.6mA
—
—
0.5
0.5
V
V
IOLT Output low current total for all ports — 100 mA
IIN Input leakage current (per pin) for full temperature
range
— 1 μA 1
IIN Input leakage current (per pin) at 25°C — 0.025 μA 1
IOZ Hi-Z (off-state) leakage current (per pin) — 1 μA
RPU Internal pullup resistors 20 50 kΩ 2
RPD Internal pulldown resistors 20 50 kΩ 3
1. Measured at VDD=3.6V
2. Measured at VDD supply voltage = VDD min and Vinput = VSS
3. Measured at VDD supply voltage = VDD min and Vinput = VDD
5.2.4 Power mode transition operating behaviors
All specifications except tPOR, and VLLSx→RUN recovery times in the following table
assume this clock configuration:
• CPU and system clocks = 72 MHz
• Bus clock = 36 MHz
• FlexBus clock = 36 MHz
• Flash clock = 24 MHz
General
K10 Sub-Family Data Sheet, Rev. 3, 11/2012.
Freescale Semiconductor, Inc. 13
Table 5. Power mode transition operating behaviors
Symbol Description Min. Max. Unit Notes
tPOR After a POR event, amount of time from the point VDD
reaches 1.71 V to execution of the first instruction
across the operating temperature range of the chip.
— 300 μs 1
• VLLS1 → RUN — 112 μs
• VLLS2 → RUN — 74 μs
• VLLS3 → RUN — 73 μs
• LLS → RUN — 5.9 μs
• VLPS → RUN — 5.8 μs
• STOP → RUN — 4.2 μs
1. Normal boot (FTFL_OPT[LPBOOT]=1)
5.2.5 Power consumption operating behaviors
Table 6. Power consumption operating behaviors
Symbol Description Min. Typ. Max. Unit Notes
IDDA Analog supply current — — See note mA 1
IDD_RUN Run mode current — all peripheral clocks
disabled, code executing from flash
• @ 1.8V
• @ 3.0V
—
—
21.5
21.5
25
30
mA
mA
2
IDD_RUN Run mode current — all peripheral clocks
enabled, code executing from flash
• @ 1.8V
• @ 3.0V
• @ 25°C
• @ 125°C
—
—
—
31
31
32
34
34
39
mA
mA
mA
3, 4
IDD_WAIT Wait mode high frequency current at 3.0 V — all
peripheral clocks disabled
— 12.5 — mA 2
IDD_WAIT Wait mode reduced frequency current at 3.0 V —
all peripheral clocks disabled
— 7.2 — mA 5
IDD_VLPR Very-low-power run mode current at 3.0 V — all
peripheral clocks disabled
— 0.996 — mA 6
IDD_VLPR Very-low-power run mode current at 3.0 V — all
peripheral clocks enabled
— 1.46 — mA 7
Table continues on the next page...
General
K10 Sub-Family Data Sheet, Rev. 3, 11/2012.
14 Freescale Semiconductor, Inc.
Table 6. Power consumption operating behaviors (continued)
Symbol Description Min. Typ. Max. Unit Notes
IDD_VLPW Very-low-power wait mode current at 3.0 V — all
peripheral clocks disabled
— 0.61 — mA 8
IDD_STOP Stop mode current at 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C
—
—
—
0.35
0.384
0.628
0.567
0.793
1.2
mA
mA
mA
IDD_VLPS Very-low-power stop mode current at 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C
—
—
—
5.9
26.1
98.1
32.7
59.8
188
μA
μA
μA
IDD_LLS Low leakage stop mode current at 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C
—
—
—
2.6
10.3
42.5
8.6
29.1
92.5
μA
μA
μA
9
IDD_VLLS3 Very low-leakage stop mode 3 current at 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C
—
—
—
1.9
6.9
28.1
5.8
12.1
41.9
μA
μA
μA
9
IDD_VLLS2 Very low-leakage stop mode 2 current at 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C
—
—
—
1.59
4.3
17.5
5.5
9.5
34
μA
μA
μA
IDD_VLLS1 Very low-leakage stop mode 1 current at 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C
—
—
—
1.47
2.97
12.41
5.4
8.1
32
μA
μA
μA
IDD_VBAT Average current with RTC and 32kHz disabled at
3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C
—
—
—
0.19
0.49
2.2
0.22
0.64
3.2
μA
μA
μA
Table continues on the next page...
General
K10 Sub-Family Data Sheet, Rev. 3, 11/2012.
Freescale Semiconductor, Inc. 15
Table 6. Power consumption operating behaviors (continued)
Symbol Description Min. Typ. Max. Unit Notes
IDD_VBAT Average current when CPU is not accessing RTC
registers
• @ 1.8V
• @ –40 to 25°C
• @ 70°C
• @ 105°C
• @ 3.0V
• @ –40 to 25°C
• @ 70°C
• @ 105°C
—
—
—
—
—
—
0.57
0.90
2.4
0.67
1.0
2.7
0.67
1.2
3.5
0.94
1.4
3.9
μA
μA
μA
μA
μA
μA
10
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See
each module's specification for its supply current.
2. 72MHz core and system clock, 36MHz bus and FlexBus clock, and 24MHz flash clock. MCG configured for FEE mode. All
peripheral clocks disabled.
3. 72MHz core and system clock, 36MHz bus and FlexBus clock, and 24MHz flash clock. MCG configured for FEE mode. All
peripheral clocks enabled.
4. Max values are measured with CPU executing DSP instructions.
5. 25MHz core, system, bus, FlexBus and flash clock. MCG configured for FEI mode.
6. 4 MHz core and system clock, 4 MHz FlexBus and bus clock, and 1 MHz flash clock. MCG configured for BLPE mode. All
peripheral clocks disabled. Code executing from flash.
7. 4 MHz core and system clock, 4 MHz FlexBus and bus clock, and 1 MHz flash clock. MCG configured for BLPE mode. All
peripheral clocks enabled but peripherals are not in active operation. Code executing from flash.
8. 4 MHz core and system clock, 4 MHz FlexBus and bus clock, and 1 MHz flash clock. MCG configured for BLPE mode. All
peripheral clocks disabled.
9. Data reflects devices with 128 KB of RAM.
10. Includes 32kHz oscillator current and RTC operation.
5.2.5.1 Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
• MCG in FBE mode for 50 MHz and lower frequencies. MCG in FEE mode at greater
than 50 MHz frequencies.
• No GPIOs toggled
• Code execution from flash with cache enabled
• For the ALLOFF curve, all peripheral clocks are disabled except FTFL
General
K10 Sub-Family Data Sheet, Rev. 3, 11/2012.
16 Freescale Semiconductor, Inc.
Figure 2. Run mode supply current vs. core frequency
General
K10 Sub-Family Data Sheet, Rev. 3, 11/2012.
Freescale Semiconductor, Inc. 17
Figure 3. VLPR mode supply current vs. core frequency
5.2.6 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
1. Go to www.freescale.com.
2. Perform a keyword search for “EMC design.”
5.2.7 Capacitance attributes
Table 7. Capacitance attributes
Symbol Description Min. Max. Unit
CIN_A Input capacitance: analog pins — 7 pF
CIN_D Input capacitance: digital pins — 7 pF
General
K10 Sub-Family Data Sheet, Rev. 3, 11/2012.
18 Freescale Semiconductor, Inc.
5.3 Switching specifications
5.3.1 Device clock specifications
Table 8. Device clock specifications
Symbol Description Min. Max. Unit Notes
Normal run mode
fSYS System and core clock — 72 MHz
fBUS Bus clock — 50 MHz
FB_CLK FlexBus clock — 50 MHz
fFLASH Flash clock — 25 MHz
fLPTMR LPTMR clock — 25 MHz
VLPR mode1
fSYS System and core clock — 4 MHz
fBUS Bus clock — 4 MHz
FB_CLK FlexBus clock — 4 MHz
fFLASH Flash clock — 0.5 MHz
fERCLK External reference clock — 16 MHz
fLPTMR_pin LPTMR clock — 25 MHz
fLPTMR_ERCLK LPTMR external reference clock — 16 MHz
fFlexCAN_ERCLK FlexCAN external reference clock — 8 MHz
fI2S_MCLK I2S master clock — 12.5 MHz
fI2S_BCLK I2S bit clock — 4 MHz
1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for any
other module.
5.3.2 General switching specifications
These general purpose specifications apply to all signals configured for GPIO, UART,
CAN, CMT, and I2C signals.
Table 9. General switching specifications
Symbol Description Min. Max. Unit Notes
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
1.5 — Bus clock
cycles
1, 2
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter enabled) — Asynchronous path
100 — ns 3
Table continues on the next page...
General
K10 Sub-Family Data Sheet, Rev. 3, 11/2012.
Freescale Semiconductor, Inc. 19
Table 9. General switching specifications (continued)
Symbol Description Min. Max. Unit Notes
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter disabled) — Asynchronous path
16 — ns 3
External reset pulse width (digital glitch filter disabled) 100 — ns 3
Mode select (EZP_CS) hold time after reset
deassertion
2 — Bus clock
cycles
Port rise and fall time (high drive strength)
• Slew disabled
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
• Slew enabled
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
—
—
—
—
12
6
36
24
ns
ns
ns
ns
4
Port rise and fall time (low drive strength)
• Slew disabled
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
• Slew enabled
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
—
—
—
—
12
6
36
24
ns
ns
ns
ns
5
1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In Stop, VLPS, LLS, and VLLSx modes, the synchronizer is bypassed so shorter pulses can be
recognized in that case.
2. The greater synchronous and asynchronous timing must be met.
3. This is the minimum pulse width that is guaranteed to be recognized as a pin interrupt request in Stop, VLPS, LLS, and
VLLSx modes.
4. 75pF load
5. 15pF load
5.4 Thermal specifications
5.4.1 Thermal operating requirements
Table 10. Thermal operating requirements
Symbol Description Min. Max. Unit
TJDie junction temperature –40 125 °C
TAAmbient temperature –40 105 °C
General
K10 Sub-Family Data Sheet, Rev. 3, 11/2012.
20 Freescale Semiconductor, Inc.
5.4.2 Thermal attributes
Board type Symbol Description 64 LQFP Unit Notes
Single-layer (1s) RθJA Thermal
resistance, junction
to ambient (natural
convection)
59 °C/W 1, 2
Four-layer (2s2p) RθJA Thermal
resistance, junction
to ambient (natural
convection)
41 °C/W 1, 3
Single-layer (1s) RθJMA Thermal
resistance, junction
to ambient (200 ft./
min. air speed)
48 °C/W 1,3
Four-layer (2s2p) RθJMA Thermal
resistance, junction
to ambient (200 ft./
min. air speed)
35 °C/W 1,3
— RθJB Thermal
resistance, junction
to board
23 °C/W 4
— RθJC Thermal
resistance, junction
to case
11 °C/W 5
—ΨJT Thermal
characterization
parameter, junction
to package top
outside center
(natural
convection)
3 °C/W 6
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board
thermal resistance.
2. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air) with the single layer board horizontal. For the LQFP, the board meets the
JESD51-3 specification. For the MAPBGA, the board meets the JESD51-9 specification.
3. Determined according to JEDEC Standard JESD51-6, Integrated Circuits Thermal Test Method Environmental
Conditions—Forced Convection (Moving Air) with the board horizontal. For the LQFP, the board meets the JESD51-7
specification.
4. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental
Conditions—Junction-to-Board. Board temperature is measured on the top surface of the board near the package.
5. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate
temperature used for the case temperature. The value includes the thermal resistance of the interface material
between the top of the package and the cold plate.
6. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air).
6 Peripheral operating requirements and behaviors
Peripheral operating requirements and behaviors
K10 Sub-Family Data Sheet, Rev. 3, 11/2012.
Freescale Semiconductor, Inc. 21
6.1 Core modules
6.1.1 Debug trace timing specifications
Table 11. Debug trace operating behaviors
Symbol Description Min. Max. Unit
Tcyc Clock period Frequency dependent MHz
Twl Low pulse width 2 — ns
Twh High pulse width 2 — ns
TrClock and data rise time — 3 ns
TfClock and data fall time — 3 ns
TsData setup 3 — ns
ThData hold 2 — ns
Figure 4. TRACE_CLKOUT specifications
Th
Ts Ts Th
TRACE_CLKOUT
TRACE_D[3:0]
Figure 5. Trace data specifications
6.1.2 JTAG electricals
Table 12. JTAG limited voltage range electricals
Symbol Description Min. Max. Unit
Operating voltage 2.7 3.6 V
Table continues on the next page...
Peripheral operating requirements and behaviors
K10 Sub-Family Data Sheet, Rev. 3, 11/2012.
22 Freescale Semiconductor, Inc.