Useable Gates 2,500 5,000
Macrocells 128 256
Logic array Blocks 816
Max user I/O pins 96 158
Speed Grades -4, -5, -7, -10 -5, -6, -7, -10
100-Pin TQFP 144-Pin TQFP
144-Pin TQFP 208-Pin PQFP
3KA tbl 01A
Feature
CL3128A
CL3256A
Packages
December 2000 Page 1
uLaser Processed Logic Device (LPLD) technology offers
the ultimate combination of performance, flexibility, and
low cost
uFunctionally, architecturally, and electrically compatible
with industry-standard Altera®MAX®3000
uHigh Density
- 2,500 Usable gates
- 128 Macrocells
- 96 Maximum user I/O pins
uLaser fuse technology provides very fast, dense
interconnect routing
uLow current consumption
uSupports 3.3 volt operation
uAlpha particle immune
CL3000 Product Family Overview
CL3128A
Laser Processed Logic Device Family
Key Features
The Clear Logic CL3000 Laser Processed Logic Device (LPLD®)
family offers the ultimate combination of performance,
flexibility, and cost. This family is a system level second source
to Altera MAX®3000A products. For designs not requiring in-
system reprogrammability, design verification can be performed
using the programmable Altera devices, and Clear Logic LPLDs
can be used for low cost, high volume production.
Clear Logics innovative laser-based technology eliminates NRE
costs, test vector development, ordering minimums and long lead
times. No re-simulation or re-layout is required, as the device
uses a cell-based, PLD-like architecture. Clear Logics NoFault®
technology ensures complete test coverage through the use of
specialized testing modes which are transparent to the user.
The Clear Logic CL3000 Laser Processed Logic Device family is
based upon a large array of macrocells. Each macrocell
contains a logic array with five product terms, a product-term
select matrix, and a configurable register. A group of sixteen
macrocells forms a block. Laser-configured metal fuses
implement logical functions and control signal routing.
Laser configuration provides reduced cost and enhanced
performance. These inherent performance benefits include
extremely consistent propagation delays, reduced power
consumption, and improved immunity to noise and upset events.
For further information on designing with the CL3000 LPLD
family (See CL7000), please consult the following documents:
uAN-01: Requesting a First Article. This document provides
instructions on how to submit a bitstream file for
generation of first articles.
uAN-02: Clear Logic Packaging Guide. This document provides
specifications and drawings for packages used by the CL7000
family.
uAN-09: CL7000 Technology White Paper. This document
outlines the technologies employed by the CL7000 LPLD
family.
uAN-10: Calculating CL7000 Power Consumption. This
document provides guidelines for calculating power
consumption based on design characteristics.
uAN-11: CL7000 Test Methodology. This document discribes
how Clear Logic provides 100% stuck-at fault coverage.
Description
CL3128A Laser Processed Logic Devices
Page 2
Additional
Information
CL3128A Laser Processed Logic Devices
Page 3
Block Diagram
INPUT/GCLK1
INPUT/OE2/GCLK2
INPUT/OE1
INPUT/GCLRn
4 to 16 I/O Pins
4 to 16 I/O Pins
4 to 16 I/O Pins
4 to 16 I/O Pins
4 to 16 I/O Pins
4 to 16 I/O Pins
4 to 16 I/O Pins
4 to 16 I/O Pins
I/O
Control
Block
I/O
Control
Block
I/O
Control
Block
I/O
Control
Block
I/O
Control
Block
I/O
Control
Block
I/O
Control
Block
I/O
Control
Block
Block A
Macrocells
1 - 16
Block C
Macrocells
33 - 48
Block E
Macrocells
65 - 80
Block G
Macrocells
97 - 112
Block B
Macrocells
17 - 32
Block D
Macrocells
49 - 64
Block F
Macrocells
81 - 96
Block H
Macrocells
113 - 128
6 Output Enables 6 - 10 Output Enables
4 to 16
4 to 16
16
36
6
4 to 16
4 to 16
16
36
6
4 to 16
4 to 16
16
36
6
4 to 16
4 to 16
16
36
4 to 16
16
36 4 to 16
6
4 to 16
16
36 4 to 16
6
4 to 16
16
36 4 to 16
6
4 to 16
16
36 4 to 16
Laser-Configured Interconnect Array (LIA)
3128A drw 01
uAN-12: CL7000 LPLD Timing and Function Compatability.
This document shows how a seamless conversion from CPLD
to ASIC can be achieve with no additional engineering with
Clear Logic.
CL3128A Laser Processed Logic Devices
Page 4
Macrocell Diagram
Global
Clocks
Global
Clear
Local Array
36 Signals
from LIA 16 Expander
Product Terms
Shared Logic
Expanders
Product
Term
Select
Matrix
Parallel Logic
Expanders
Clear
Select
VCC
Clock/
Enable
Select
Register
Bypass
Fast Input
Select Configurable
Register
to LIA
to I/O
Control
Block
from
I/O pin
PRN
ENA
CLRN
Q
D
2
3K drw 01
CL3128A Laser Processed Logic Devices
Page 5
Pin Configuration
Pin Name 100 pin TQFP 144 pin TQFP
INPUT/GCLK1
87 125
INPUT/GCLRn
89 127
INPUT/OE1
88 126
INPUT/OE2/GCLK2
90 128
TDI
4 4
TMS
15 20
TCK
62 89
TDO
73 104
GNDINT
38, 86 52, 57, 124, 129
GND
11, 26, 33, 43, 53, 59, 65, 74, 78, 95
3, 13, 17, 26, 33, 59, 64, 77, 85, 94,
105, 114, 135
VCCINT
39, 91 51, 58, 123, 130
VCCIO
3, 18, 34, 51, 66, 82 24, 50, 73, 76, 95, 115, 144
NC (No Connect)
-
1, 2, 12, 19, 34, 35, 36, 43, 46, 47, 48,
49, 66, 75, 90, 103, 108, 120, 121, 122
Total user I/O pins 80 96
3128A tbl 01
CL3128A Laser Processed Logic Devices
Page 6
Absolute Maximum Ratings
DC Electrical Specifications
Symbol Parameter Conditions Min Max Unit
VCC Supply voltage With respect to ground -0.5 4.6 V
VIDC input voltage[1] With respect to ground -2.0 5.75 V
IOUT DC output current, per pin -25 25 mA
TSTG Storage temperature No bias -65 150 °C
TAAmbient temperature Under bias -65 135 °C
TJJunction temperature
PQFP, and TPFP
packages, Under bias
135 °C
3KA tbl 03
Symbol Parameter Conditions Min Max Unit
VCCINT Supply voltage, internal logic and input buffers 3.0 3.6 V
VCCIO Supply voltage for output drivers
3.3 volt operation 3.0 3.6 V
2.5 volt operation 2.3 2.7 V
VIInput voltage -0.5 5.75 V
VOOutput voltage 0 VCCIO V
Ambient Operating temperature
Commercial temperature range 0 70 °C
Industrial temperature range -40 85 °C
Ambient Operating temperature
Commercial temperature range 0 90 °C
Industrial temperature range -40 105 °C
tRInput signal rise time 40 ns
tFInput signal fall time 40 ns
TA
3KA tbl 02
TJ
Recommended Operating Conditions
CL3128A Laser Processed Logic Devices
Page 7
Capacitance
DC Electrical Specifications cont.
Symbol Parameter Conditions Min Max Unit
CIN Input Capacitance VIN = 0 V, f = 1.0 MHz 8 pF
COUT Output Capacitance VOUT = 0 V, f = 1.0 MHz 8 pF
3KA tbl 05
DC Electrical Characteristics (over the operating range)
Symbol Parameter Conditions Min Max Unit
VIH High-level input Voltage 1.7 5.75 V
VIL Input LOW Voltage[1] -0.5 0.8 V
3.3-V high-level TTL output Voltage
IOH = -8 mA DC, VCCIO = 3.00 V 2.4 V
3.3-V high-level CMOS output Voltage
IOH = -0.1 mA DC, VCCIO = 3.00 V VCCIO-0.2 V
IOH = -100 mA DC, VCCIO = 2.30 V 2.1 V
IOH = -1 mA DC, VCCIO = 2.30 V 2.0
IOH = -2 mA DC, VCCIO = 2.30 V 1.7
3.3-V high-level TTL output Voltage
IOH = 8 mA DC, VCCIO = 3.00 V 0.45 V
3.3-V high-level CMOS output Voltage
IOH = 0.1 mA DC, VCCIO = 3.00 V 0.2 V
IOH = 100 mA DC, VCCIO = 2.30 V 0.2 V
IOH = 1 mA DC, VCCIO = 2.30 V 0.4 V
IOH = 2 mA DC, VCCIO = 2.30 V 0.7 V
IIN Input Leakage Current VI = VCC or GND -10 10 µA
IOZ Output Leakage Current VO = VCC or GND -10 10 µA
VOH
2.5-V high-level output Voltage
VOL
2.5-V high-level output Voltage
CL3128A Laser Processed Logic Devices
Page 8
Parameter Conditions Min Max Min Max Min Max Unit
tPD1 Input to non-registered output CL = 35 pF 4.5 5.0 6.0 ns
tPD2 I/O input to non-registered output CL = 35 pF 4.5 5.0 6.0 ns
tSU Global clock setup time 3.0 3.2 3.7 ns
tHGlobal clock hold time 0.0 0.0 0.0 ns
tCO1 Global clock to output delay CL = 35 pF 1.0 2.8 1.0 3.0 1.0 3.3 ns
tCH Global clock high time 2.0 2.0 3.0 ns
tCL Global clock low time 2.0 2.0 3.0 ns
tASU Array clock setup time 1.4 1.0 0.8 ns
tAH Array clock hold time 0.8 0.8 1.9 ns
tACO1 Array clock to output delay CL = 35 pF 4.4 5.2 1.0 6.2 ns
tACH Array clock high time 2.0 2.0 3.0 ns
tACL Array clock low time 2.0 2.0 3.0 ns
tCNT Minimum global clock period 5.2 5.5 6.4 ns
fCNT Max. internal global clock frequency 192.3 181.8 156.3 MHz
tACNT Minimum array clock period 5.2 5.5 6.4 ns
fACNT Max. internal array clock frequency 192.3 181.8 156.3 MHz
Symbol
3KA tbl 06A1
Speed: -4
Speed: -5
Speed: -6
AC Electrical Specifications
I/O Element Timing Parameters
CL3128A Laser Processed Logic Devices
Page 9
Parameter Conditions Min Max Min Max Unit
tPD1 Input to non-registered output CL = 35 pF 7.5 10.0 ns
tPD2 I/O input to non-registered output CL = 35 pF 7.5 10.0 ns
tSU Global clock setup time 4.9 6.6 ns
tHGlobal clock hold time 0.0 0.0 ns
tCO1 Global clock to output delay CL = 35 pF 1.0 4.5 1.0 5.9 ns
tCH Global clock high time 3.0 4.0 ns
tCL Global clock low time 3.0 4.0 ns
tASU Array clock setup time 1.6 2.1 ns
tAH Array clock hold time 2.1 3.4 ns
tACO1 Array clock to output delay CL = 35 pF 7.8 10.4 ns
tACH Array clock high time 3.0 4.0 ns
tACL Array clock low time 3.0 4.0 ns
tCNT Minimum global clock period 8.4 11.2 ns
fCNT Max. internal global clock frequency 119.0 89.3 MHz
tACNT Minimum array clock period 8.4 11.2 ns
fACNT Max. internal array clock frequency 119.0 89.3 MHz
Symbol
3KA tbl 06A2
Speed: -7
Speed: -10
External Timing Parameters
AC Electrical Specifications cont.
Parameter Conditions Min Max Min Max Min Max Unit
tiN Input pad and buffer delay 0.3 0.3 0.3 ns
tIO I/O input pad and buffer delay 0.3 0.3 0.3 ns
tSEXP Shared expander delay 1.9 2.4 2.8 ns
tPEXP Parallel expander delay 0.5 0.6 0.5 ns
tLAD Logic array delay 1.9 2.5 2.5 ns
tLAC Logic control array delay 1.8 2.3 2.5 ns
tIOE Internal output enable delay 0.0 0.0 0.2 ns
Output buffer and pad delay
Slow slew rate = off, VCCIO = 5.0 V
Output buffer and pad delay
Slow slew rate = off, VCCIO = 3.3 V
Output buffer and pad delay
Slow slew rate = on,
VCCIO = 5.0 V or 3.3 V
Output buffer enable delay
Slow slew rate = off, VCCIO = 5.0 V
Output buffer enable delay
Slow slew rate = off, VCCIO = 3.3 V
Output buffer enable delay
Slow slew rate = on,
VCCIO = 5.0 V or 3.3 V
tXZ Output buffer disable delay CL = 5 pF[3] 4.0 4.0 4.0 ns
tSU Register setup time 1.4 0.8 1.0 ns
tHRegister hold time 0.8 1.0 1.7 ns
tRD Register delay 1.2 1.4 1.6 ns
tCOMB Combinatorial delay 1.3 1.0 1.6 ns
tIC Array clock delay 1.9 2.3 2.7 ns
tEN Register enable time 1.8 2.3 2.5 ns
tGLOB Global control delay 1.0 0.9 1.1 ns
tPRE Register preset time 2.3 2.6 2.3 ns
tCLR Register clear time 2.3 2.6 2.3 ns
tLIA LIA delay 0.7 0.8 1.3 ns
9.0
ns
3KA tbl 07A1
4.5
ns
tZX3
CL = 35 pF
9.0
9.0
4.0
ns
tZX2
CL = 35 pF
4.5
4.5
5.3
ns
tZX1
CL = 35 pF
4.0
4.0
0.8
ns
tOD3
CL = 35 pF
5.3
5.4
0.3
ns
tOD2
CL = 35 pF
0.8
0.9
0.3
0.4
tOD1
CL = 35 pF
Speed: -4
Speed: -5
Speed: -6
Symbol
CL3128A Laser Processed Logic Devices
Page 10
AC Electrical Specifications cont.
Internal Timing Parameters[4]
Parameter Conditions Min Max Min Max Unit
tiN Input pad and buffer delay 0.4 0.6 ns
tIO I/O input pad and buffer delay 0.4 0.6 ns
tSEXP Shared expander delay 3.6 4.9 ns
tPEXP Parallel expander delay 0.8 1.1 ns
tLAD Logic array delay 3.7 5.0 ns
tLAC Logic control array delay 3.4 4.6 ns
tIOE Internal output enable delay 0.0 0.0 ns
Output buffer and pad delay
Slow slew rate = off, VCCIO = 5.0 V
Output buffer and pad delay
Slow slew rate = off, VCCIO = 3.3 V
Output buffer and pad delay
Slow slew rate = on,
VCCIO = 5.0 V or 3.3 V
Output buffer enable delay
Slow slew rate = off, VCCIO = 5.0 V
Output buffer enable delay
Slow slew rate = off, VCCIO = 3.3 V
Output buffer enable delay
Slow slew rate = on,
VCCIO = 5.0 V or 3.3 V
tXZ Output buffer disable delay CL = 5 pF[3] 4.0 5.0 ns
tSU Register setup time 1.3 1.7 ns
tHRegister hold time 2.4 3.8 ns
tRD Register delay 2.1 2.8 ns
tCOMB Combinatorial delay 1.5 2.0 ns
tIC Array clock delay 3.4 4.6 ns
tEN Register enable time 3.4 4.6 ns
tGLOB Global control delay 1.4 1.8 ns
tPRE Register preset time 3.9 5.2 ns
tCLR Register clear time 3.9 5.2 ns
tLIA LIA delay 1.3 1.7 ns
3KA tbl 07A2
ns
tOD1
tOD2
tOD3
tZX1
tZX2
tZX3
CL = 35 pF
9.0
CL = 35 pF
4.5
5.0
10.0
ns
5.5
ns
CL = 35 pF
4.0
ns
CL = 35 pF
5.6
5.7
ns
ns
CL = 35 pF
1.1
1.2
0.6
0.7
Speed: -10
Symbol
CL = 35 pF
Speed: -7
CL3128A Laser Processed Logic Devices
Page 11
AC Electrical Specifications cont.
Internal Timing Parameters[4]
CL3128A Laser Processed Logic Devices
Page 12
1. During transitions, inputs may undershoot to -2.0V for periods shorter than
20ns. Otherwise, minimum DC input voltage is 0.3V.
2. Typical values are at VCC of 5.0 volts and ambient temperature of 25 ºC.
3. Guaranteed but not tested. Characterized initially, and after any design
changes which may affect these parameters.
4. Internal timing delays are based on characterization, and cannot be explicitly
tested. Internal timing parameters should be used for performance estimation
only.
20 Oct.. 2000: Created preliminary document.
1 Dec. 2000: Updated application note reference.
AC Test Conditions
464 Ω
250 Ω35 pF
V
CCIO
OUTPUT
Includes jig
capacitance
464 Ω
250 Ω5 pF
V
CCIO
OUTPUT
Includes jig
capacitance
(A) (B)
≤ 3ns
≤ 3ns
3.0V 90%
10%
GND
90%
10%
All Input Pulses
3K drw 02
Notes to Tables
Revision History
Part Number Temperature Range Package Type Speed Altera Equivalent
CL3128ATC100-10 Commercial 100-pin Thin QFP -10 EPML3128ATC100-10
CL3128ATC100-7 -7 EPM3128ATC100-7
CL3128ATC100-5 -5 EPM3128ATC100-5
CL3128ATC100-4 -4 N/A
CL3128ATC144-10 144-pin Thin QFP -10 EPM3128ATC144-10
CL3128ATC144-7 -7 EPM3128ATC144-7
CL3128ATC144-5 -5 EPM3128ATC144-5
CL3128ATC144-4 -4 N/A
3128A tbl 02
CL3128A Laser Processed Logic Devices
Page 13
Ordering Information
CL3128A Laser Processed Logic Devices
Page 14