MCP18480 -48V Hot Swap Controller Features Description * Allows safe board removal and insertion from a live backplane * Accurate (<1.5%) internal voltage reference for fault detection and precision timing * Programmable foldback current limiting * Programmable circuit breaker current limiting * Auto restart option for all faults * Adjustable Undervoltage lockout thresholds * Adjustable Overvoltage protection threshold * Adjustable Power Good delay * Configurable Power Good output polarity * Low-side drive of an external N-channel FET The MCP18480 is a Hot Swap controller that allows boards to be safely removed or inserted from an active backplane using -48V. CMOS Technology * High-Voltage Operation * Temperature range: Industrial (I): -40C to +85C Packaging * 20-lead SSOP Package Type SSOP 1 20 OVTH 2 19 ENABLE UVTH 3 18 PWRGOOD UVHYS 4 17 OVO UVD 5 VREFOUT 6 MCP18480 VPOS RESTART 16 DRAINTH 15 VFB VREFIN 7 14 GATE CL 8 13 SENSE ISET 9 12 RDISCH 10 11 VNEG TIMER 2002-2012 Microchip Technology Inc. When PCBs are inserted into a live backplane, highpeak or transient currents from the source are generated due to the charging of the bypass capacitors on the supply. The high transient currents can destroy connectors and capacitors. The high inrush current can pull the input voltage BUS down and reset the system. The MCP18480 solves this problem by controlling the slew rate of the backplane voltage to the board so that these transients are eliminated. This allows boards to be removed and inserted without causing damage to connector pins and input bulk capacitors, in addition to preventing false resets to the other boards on the backplane. The MCP18480 can be used in applications in several areas including: * * * * * * * * Telecom Line Cards Network Switches Network Routers and Servers Base Station Line Cards Power-Over-LAN Power-Over-MDI IP Phone Switches/Routers Mid-Span, Power-Over-MDI Two forms of current limit are provided in the MCP18480. These are: * Foldback * Circuit breaker The foldback current-limiting circuit uses an external sense resistor and a voltage that is proportional to the external MOSFET's drain voltage. These are used to keep the MOSFET in its Safe Operating Area (SOA). If the device remains in current limit for a programmed time period, the external N-channel FET is turned off. The option exists to configure the device to automatically restart after a programmed time delay. A programmable catastrophic current limit threshold shuts down the switch (circuit breaker) if excessive current is sensed due to a short-circuit condition. DS20091C-page 1 MCP18480 Internal comparators are incorporated to add hysteresis for adjusting the Undervoltage Lockout (UVLO) threshold. The external N-channel MOSFET is turned on when the input is below the user-programmable, Overvoltage threshold and above the userprogrammable, Undervoltage threshold. The PWRGOOD pin indicates the status of the MCP18480 and is active when the device has completed power-up and the system is not in an Undervoltage, Overvoltage or current-limit condition. PWRGOOD can be externally configured to either active-high or active-low to accommodate external circuitry (power supplies) that have either enabling logic. A block diagram of the MCP18480 is shown below. MCP18480 Block Diagram VPOS DRAINTH VPOS FET Good (Section 6.8.3) BIAS GATE Drive 12VOUT 5V Reg. OVO Overvoltage (Section 6.8.2) UVTH UVD Undervoltage (Section 6.8.1) VFB SENSE CL ENABLE RESTART Latch (Section 6.8.6) VNEG TIMEOUT UVHYS 5VOUT Current Limit Feedback OVTH SENSE Undervoltage Active Internal Bias Generation Overvoltage Active ISET GATE (Section 6.8.7) 5VOUT VREFOUT VREFIN PWRGOOD (1) 12V Regulator LATCHOFF VNEG PWRGOOD Output Block (Section 6.8.9) (Section 6.8.8) Current Limit (Section 6.8.4) Current Limit Timer Circuit Breaker TIMER Timer (Section 6.8.5) RDISCH MCP18480 Note 1: The PWRGOOD output pin can be either active-high or active-low. This polarity is determined by the voltage (either the level on the VREFIN pin or level on the VNEG pin) on the ISET pin: - Connecting the external RISET resistor to VREFIN configures the PWRGOOD pin as active-low - Connecting the external RISET resistor to VNEG configures the PWRGOOD pin as active-high DS20091C-page 2 2002-2012 Microchip Technology Inc. MCP18480 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Ambient Temperature under bias ........ -40C to +85C Max. Output Current sourced by VREFOUT pin .....5 mA Storage Temperature ........................ -65C to +150C Max. Output Current sourced by any other Output pin...........................................................25 mA Voltage on VPOS with respect to VNEG -0.3V to +15.0V Junction to Ambient, JA (20 pin SSOP Package) Derating ...............108.1C/W Voltage on DVTH, UVTH, VFB, OVO and UVHYS pins with respect to VNEG ..... VNEG - 0.3V to (VPOS + 0.3V) Junction to Case, JC (20 pin SSOP Package) Derating .................32.2C/W Voltage on VREFIN, CL, SENSE, DRAINTH, ENABLE and RESTART pins with respect to VNEG ........................................................ VNEG - 0.3V to 6V. Lead Temperature, Soldering, 10 seconds ........ 300C Total Power Dissipation (Note 1) .................... 800 mW Notice: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Max. Current out of VNEG pin ............................. 80 mA Max. Current into VPOS pin ................................ 50 mA Max. Output Current sunk by Gate pin............... 80 mA Max. Output Current sunk by VREFOUT pin .......... 5 mA Note 1: Power Dissipation is calculated as follows: Max. Output Current sunk by any other Output pin......................................................... 25 mA PDIS = VDD x {IDD - IOH} + {(VDD-VOH) x IOH} + (VOL x IOL) Max. Output Current sourced by Gate pin ........ 200 A DC CHARACTERISTICS Electrical Specifications: Unless otherwise specified, operating temperature: -40C TA +85C (Industrial), Supply Current: 5 mA IPOS 25 mA, RISET = 125 k, CBYP = 2 F. Param. No. Parameter Sym Min Typ (1) Max Units Current into shunt regulator that produces VPOS output voltage that meets MD001A specification IPOS1 5 -- 25 mA 5 -- 25 MD001A Regulated Output Voltage Differential of VPOS to VNEG VPOS 10.4 12.0 13.4 MD002 VREFOUT pin output voltage VREFOUT 2.463 2.5 MD010 VGATE pin output voltage VGATE VPOS - 2 VPOS -1 MD011 Voltage on ISET pin VISET (VREFIN/2) 0.02 MD012A Voltage on SENSE pin to trigger current-limiting VSENSE 7 MD013 Undervoltage Threshold UVTH VREFIN - 0.03 MD014A Overvoltage Threshold rising OVTH VREFIN - 0.05 falling OVTH VDTH MD001 MD012B MD012C MD014B MD015 DRAIN Pin Input Threshold Voltage Conditions ENABLE pin = 5V ENABLE pin = VNEG V See MD001 2.538 V Load = 50 A VPOS V VREFIN/2 (VREFIN/2) +0.02 V 40 50 60 mV VFB = VNEG 25 31.0 40 mV VFB = VNEG + 0.25V 12 17 mV VFB = VNEG + 0.5V VREFIN VREFIN + 0.03 V VREFIN VREFIN + 0.05 V VREFIN = 2.5V VREFIN - 0.035 VREFIN - 0.02 VREFIN - 0.005 V VREFIN = 2.5V 90 100 130 mV Note 1: Data in the Typical ("Typ") column is based on characterization results at +25C. This data is for design guidance only and is not tested. 2: Negative current is defined as current sourced by the pin. 3: All voltages are with respect to the VNEG pin voltage. 2002-2012 Microchip Technology Inc. DS20091C-page 3 MCP18480 DC Characteristics (Continued) Electrical Specification: Unless otherwise specified, operating temperature: -40C TA +85C (Industrial), Supply Current: 5 mA IPOS 25 mA, RISET = 125 kCBYP = 2 F Param. No. Parameter Sym Min Typ (1) Max Units MD020 DRAIN pin current IDRAIN -- -- 0.1 A MD021 SENSE pin current ISENSE -- -- 0.1 A MD022 GATE pin current Pull-up MD022B MD022C MD023 UVD pin current MD024A TIMER pin current MD024B MD025 A VFB = VNEG -30 -50 -75 -9 -17 -33 A 31 49 72 mA Any fault condition VFB = VNEG + 500 mV Pull-down IGATE IUVD -7 -10 -15 A UVTH < VREFIN Pull-up ITIMER -100 -160 -200 A RISET = 125 k, VREFIN = 2.5V 52 78 104 nA RISET = 125 k, VREFIN = 2.5V RDISCH = 1.6 M VISET(MIN) -- VISET(MAX) A See MD011 Pull-down ISET pin current DRAINTH pin = VNEG SENSE pin = VNEG GATE pin = VNEG +4V IGATE MD022A Conditions IISET RISET(MAX) RISET(MIN) Note 1: Data in the Typical ("Typ") column is based on characterization results at +25C. This data is for design guidance only and is not tested. 2: Negative current is defined as current sourced by the pin. 3: All voltages are with respect to the VNEG pin voltage. DS20091C-page 4 2002-2012 Microchip Technology Inc. MCP18480 DC Characteristics (Continued) Electrical Specifications: Unless otherwise specified, operating temperature: -40C TA +85C (Industrial), Supply Current: 5 mA IPOS 25 mA, RISET = 125 k, CBYP = 2 F. Param # Parameter Sym Min Typ Max Units V MD030 Input Low Voltage MD031 ENABLE pin VNEG -- 0.8 MD032 RESTART pin VNEG -- 0.8 MD040 Input High Voltage Conditions VIL VIH MD041 ENABLE pin 2.0 -- 5.0 MD042 RESTART pin 2.0 -- 5.0 V 500 1200 2100 VUVTH < VREFIN, IUVHYS = 30 A 50 100 -- M VUVTH > VREFIN, IUVHYS = 30 A -1 -- +1 A VNEG VPIN 11V, Pin at high-impedance -- -- 1 A VNEG VPIN 5V, Pin at hi-impedance -- 10 30 A IPOS = 5 mA, ENABLE = 0.8V 0 -- 0.4 V IOL = 5 mA IOH = 2 mA, 7 mA IPOS 12 mA MD050 Internal Resistance on UVHYS pin RUVHYS V Input Leakage Current (Notes 2, 3) MD060A OVTH, UVTH, VFB, OVO and UVHYS pins MD060B VREFIN, CL, SENSE, DRAINTH, ENABLE and RESTART pins MD070 Minimum current into ENABLE pin to disable MCP18480 IEN Output Low Voltage VOL MD080 PWRGOOD pin Output High Voltage MD090 PWRGOOD pin MD100 Offset Voltage at the internal comparator input that is connected to the CL pin. IIL -- VOH VCL 0.8 VPOS 0.96 VPOS VPOS V -15 -- +15 mV VFB = 0 Note 1: All voltages are with respect to the VNEG pin voltage. 2: The leakage currents on the ENABLE and RESTART pins are strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as coming out of the pin. 2002-2012 Microchip Technology Inc. DS20091C-page 5 MCP18480 1.1 Timing Parameter Symbology and Load Conditions The timing parameter symbols have been created using one of the following formats: 1.1.1 TIMING CONDITIONS The temperature and voltages specified in Table 1-2 apply to all timing specifications, unless otherwise noted. Figure 1-1 specifies the load conditions for the timing specifications. TABLE 1-1: SYMBOLOGY 1. TppS2ppS 2. TppS T F Frequency E Error T Time Lowercase letters (pp) indicate the device pin. Uppercase letters and their meanings: S F Fall P Period FR Fast Ramp R Rise H High V Valid I Invalid (Hi-impedance) Z Hi-impedance L Low TABLE 1-2: AC TEMPERATURE AND VOLTAGE SPECIFICATIONS AC CHARACTERISTICS DS20091C-page 6 Standard Operating Conditions (unless otherwise stated) Operating temperature: -40C TA +85C (industrial) Operating voltage VDD range as described in DC spec Section 1.0. 2002-2012 Microchip Technology Inc. MCP18480 GND VIN+ VOUT+ RBYPL 51 k RZ RPOS 4 k ROV1 1.74 M CBYP1 + 2 F CBYP2 10 nF 78V Transorb ROV2 59 k DC/DC SRS 24.9 k RUV1 453 k 5V RUVHYS RUV2 280 k 30.9 k CUVD 800 nF RISET 1 VPOS RESTART 20 2 OVTH ENABLE 19 3 UVTH PWRGOOD 18 4 UVHYS 5 UVD 6 VREFOUT 7 VREFIN 8 CL SENSE 13 9 ISET RDISCH 12 124 k VNEG RPG1 110 k 680 RPG4 QPG2 2N5400 36 k Q PG1 MPSA43 RPG5 GOODPWR 36 k ON/OFF VIN- VOUT- QPG3 NTE261 RPG6 1500 VFB 15 GATE 14 VNEG 11 MCP18480 Ctimer 680 nF Fuse 10A OVO 17 SEN Converter Module RPG3 DRAINTH 16 10 TIMER CBYPL 100 F 100 V RDISCH 1.6 M RPG2 7.5 k RSENSE 0.01 RGD 18 k CG1 RG1 100 nF 10 CGD 3.3 nF M1 NTE2388 RFB2 124 k RFB1 1.74 M RDRAIN2 115 k RDRAIN1 ROVO2 ROVO1 1.74 M 59 k FIGURE 1-1: 1.6 M Load Conditions for Device Timing Specifications. 2002-2012 Microchip Technology Inc. DS20091C-page 7 MCP18480 1.2 Timing Diagrams and Specifications > 2.5V UVTH < 2.5V OVTH = 2.5V VREFOUT DRAINTH = 5V (1) GATE MA001B PWRGOOD = 12V MA001A MA002 MA000 Note 1: This voltage is determined by the threshold voltage of the external FET. This voltage needs to ensure the external FET is fully enhanced. FIGURE 1-2: TABLE 1-3: Param. No. MA000 Startup Waveforms. STARTUP TIMING REQUIREMENTS Parameter UVTH/OVTH High (VPOS applied) to DRAINTH falling MA001A DRAINTH falling to PWRGOOD High Sym Min Typ Max Units TUVOVH2DTHF -- 20.2 -- ms TDTHF2GATEPGH -- 19.3 -- ms MA001B DRAINTH falling to GATE Fast Ramp TDTHF2GATEFR -- 13.1 -- ms MA002 TGATEFR2FETE -- 16.1 -- ms Note: GATE Fast Ramp to external FET fully enhanced Conditions Minimum and maximum specifications will be provided in future revisions of this data sheet. DS20091C-page 8 2002-2012 Microchip Technology Inc. MCP18480 ENABLE MA012 GATE (1) MA010 MA011 Note 1: This voltage is determined by the threshold voltage of the external FET. This voltage needs to ensure the external FET is fully enhanced. FIGURE 1-3: TABLE 1-4: Param. No. ENABLE-to-GATE Waveforms. ENABLE-TO-GATE TIMING REQUIREMENTS Parameter MA010 ENABLE Low to GATE Low MA011 ENABLE High to GATE Fast Ramp MA012 GATE Fast Ramp to GATE High Note: Sym Min TENL2GATEL -- Typ Max Units 23.6 -- Conditions s TENH2GATEFR -- 41 -- ms TGATEFR2GATEH -- 17.8 -- ms Minimum and maximum specifications will be provided in future revisions of this data sheet. 2002-2012 Microchip Technology Inc. DS20091C-page 9 MCP18480 VREFIN + VOVO OVTH VREFIN + VOVO - 20 mV GATE(1) MA022 MA020 MA021 Note 1: This voltage is determined by the threshold voltage of the external FET. This voltage needs to ensure the external FET is fully enhanced. FIGURE 1-4: TABLE 1-5: Param. No. MA020 OVTH-to-gate Waveform. OVTH-TO-GATE TIMING REQUIREMENTS Parameter OVTH High to GATE Low Sym Min TOVH2GATEL -- Typ Max Units 58.4 -- s MA021 OVTH Low to GATE Fast Ramp TOVL2GATEFR -- 40.8 -- s MA022 GATE Fast Ramp to GATE High TGATEFR2GATEH -- 17.8 -- ms Note: Conditions Minimum and maximum specifications will be provided in future revisions of this data sheet. DS20091C-page 10 2002-2012 Microchip Technology Inc. MCP18480 UVTH VREFIN - 262 mV VREFIN MA030 GATE(1) MA033 MA032 MA031 Note 1: This voltage is determined by the threshold voltage of the external FET. This voltage needs to ensure the external FET is fully enhanced. FIGURE 1-5: TABLE 1-6: Param. No. MA030 UVTH-to-gate Waveform UVTH-TO-GATE TIMING REQUIREMENTS Parameter UVTH Low to GATE Falling Edge Sym Min Typ(1) TUVL2GATEF -- 108 -- Max Units s MA031 GATE High to GATE Low TGATEH2GATEL -- 25.8 -- s MA032 ENABLE High to GATE Fast Ramp TUVH2GATEFR -- 40.4 -- ms MA033 GATE Fast Ramp to GATE High TGATEFR2GATEH -- 58.4 -- ms Conditions CUVD = 800 nF Note 1: Data in the Typical ("Typ") column is at 5V, 25C, unless otherwise stated. 2: Minimum and maximum specifications will be provided in future revisions of this data sheet. 2002-2012 Microchip Technology Inc. DS20091C-page 11 MCP18480 Foldback Current-Limiting SENSE GATE MA041 Recovery from Foldback Current-Limiting SENSE GATE MA042 Circuit Breaker Current-Limiting SENSE GATE MA043 FIGURE 1-6: TABLE 1-7: Param. No. Sense-to-gate Waveform. SENSE-TO-GATE TIMING REQUIREMENTS Parameter MA041 GATE Current Limit to GATE Off MA042 GATE Current Limit Recovery MA043 SENSE High to GATE Off Note: Sym Min Typ Max Units Conditions TGATECL2GATEO -- 5.5 -- ms CTIMER = 0.68 F RISET = 124 k TGATECL -- 10.2 -- ms CTIMER = 0.68 F RISET = 124 k TSENSEH2GATEO -- 3.6 -- ms Minimum and maximum specifications will be provided in future revisions of this data sheet. DS20091C-page 12 2002-2012 Microchip Technology Inc. MCP18480 External Short Condition On-Board RESTART ENABLE SENSE GATE Timer MA054 MA051 MA053 MA055 MA050 FIGURE 1-7: TABLE 1-8: Param. No. Current Limit Waveform. CURRENT LIMIT TIMING REQUIREMENTS Parameter Sym Min Typ Max Units Conditions TSHORT2TIMERS -- 171 -- mS TTIMERP -- 5.8 -- sec CTIMER = 0.68 F RDISCH = 1.6 M MA050 External Short to Timer period start MA051 Timer period MA053 ENABLE High to Timer period start TENABLEH2TIMERS -- 30.5 -- mS CTIMER = 0.68 F RDISCH = 1.6 M MA054 RESTART Low to Timer period start TRESTARTL2TIMERS -- 30.9 -- mS CTIMER = 0.68 F RDISCH = 11.6 M MA055 External Short removed to Timer off Note 2 TNOSHORT2TIMERO -- 5.8 -- sec CTIMER = 0.68 F RDISCH = 1.6 M Note 1: Minimum and maximum specifications will be provided in future revisions of this data sheet. 2: This is up to one additional timer period because the external short circuit is removed asynchronously to the timer. The timer must time out before normal operation returns. 2002-2012 Microchip Technology Inc. DS20091C-page 13 MCP18480 NOTES: DS20091C-page 14 2002-2012 Microchip Technology Inc. MCP18480 DC CHARACTERISTIC CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. 11.90 TA = +25C Supply Voltage, V POS (V) Supply Voltage, V POS (V) 12.400 TA = +85C TA = -5C 11.900 TA = +70C 11.400 TA = -40C IPOS = 5 mA 11.85 11.80 11.75 11.70 11.65 10.900 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125 2.0 Supply Current, IPOS (mA) Temperature (C) Data taken with the minimum following conditions: Data taken with the minimum following conditions: VREFIN = 2.5V, ISET = 10 A Minimum Supply Current to bring VPOS into regulation FIGURE 2-1: Supply Current (IPOS) vs. Supply Voltage (VPOS). 2002-2012 Microchip Technology Inc. VREFIN = 2.5V, ISET = 10 A FIGURE 2-2: Temperature. Minimum Supply Current vs. DS20091C-page 15 MCP18480 12.0 0.35 Gate Voltage (V) 0.30 TA = +70C 0.25 TA = 0C TA = +25C 0.20 TA = -40C Gate Output Vol (mV) 11.0 TA = +85C 10.0 9.0 8.0 TA = +85C 7.0 TA = +25C 6.0 TA = 0C 5.0 4.0 TA = -40C 3.0 2.0 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0.15 3 5 7 9 11 13 15 17 19 21 23 25 Supply Current (mA) Supply Current (mA) Data taken with the minimum following conditions: Data taken with the minimum following conditions: 3 mA IPOS 30 mA 3 mA IPOS 30 mA VREFIN = 2.5V, ISET = 10 A VREFIN = 2.5V, ISET = 10 A Note 1: Note 1: VUVTH > VVREFIN VOVTH < VVREFIN VSENSE = VVNEG VVFB = VVNEG VDRAINTH = VVNEG VOVO = VVNEG VCL = VVREFIN VENABLE = 5V (open) VRESTART = VVNEG (open) VUVTH > VVREFIN VOVTH < VVREFIN VSENSE = VVNEG VVFB = VVNEG VDRAINTH = VVNEG VOVO = VVNEG VCL = VVREFIN VENABLE = VVNEG VRESTART = VVNEG (open) FIGURE 2-3: GATE Output High-Voltage (VPOS- VGATE) vs. Supply Current (IPOS). DS20091C-page 16 FIGURE 2-4: GATE Output Low-Voltage (VGATE - VNEG) vs. Supply Current (IPOS). 2002-2012 Microchip Technology Inc. MCP18480 60 Gate Current (mA) Gate Pull-up Current (A) 55 50 45 40 35 -40 55 50 45 40 -20 0 20 40 60 80 -40 -20 0 20 40 60 80 Temperature (C) Temperature (C) Data taken with the minimum following conditions: Data taken with the minimum following conditions: IPOS = 5 mA (Enables VPOS at its self-regulating voltage) VREFIN = 2.5V, ISET = 10 A Note 1: VUVTH > VVREFIN VOVTH < VVREFIN VSENSE = VVNEG VVFB = VVNEG VDRAINTH = VVNEG VOVO = VVNEG VCL = VVREFIN VENABLE = 5V (open) FIGURE 2-5: GATE Source (Pull-Up) Current vs. Temperature. 2002-2012 Microchip Technology Inc. IPOS = 5 mA (Enables VPOS at its self-regulating voltage) VREFIN = 2.5V, ISET = 10 A Note 1: VGATE > 0.5V VUVTH > VVREFIN VOVTH < VVREFIN VSENSE = VVNEG VVFB = VVNEG VDRAINTH = VVNEG VOVO = VVNEG VCL = VVREFIN VENABLE = VVNEG VRESTART = VVNEG (open) FIGURE 2-6: GATE Sink (Pull-Down) Current vs. Temperature. DS20091C-page 17 -5 -15 -25 -35 -45 -55 -65 -75 -85 -95 -105 TA = +85C PWRGOOD, VOL (V) Gate Current (uA) MCP18480 TA = +25C TA = -40C -30 -25 -20 -15 -10 -5 0 5 0.26 0.25 0.24 0.23 0.22 0.21 0.20 0.19 0.18 0.17 -40 10 15 20 25 30 ISET Current (uA) -20 0 20 40 60 80 Temperature (C) Data taken with the minimum following conditions: Data taken with the minimum following conditions: -50 A A < IISET < 50 A (IISET 0) IPOS = 5 mA (Enables VPOS at its self-regulating voltage) VREFIN = 2.5V ILOAD = 1 mA IPOS = 5 mA (Enables VPOS at its self-regulating voltage) VREFIN = 2.5V, ISET = 10 A Note 1: VGATE > 0.5V VUVTH > VVREFIN VOVTH < VVREFIN VSENSE = VVNEG VVFB = VVNEG VDRAINTH = VVNEG VOVO = VVNEG VCL = VVREFIN VENABLE = 5V (open) VRESTART = VVNEG (open) FIGURE 2-7: ISET Pin Current. DS20091C-page 18 GATE Source Current vs. Note 1: VUVTH > VVREFIN VOVTH < VVREFIN VSENSE = VVNEG VVFB = VVNEG VDRAINTH = VVNEG VOVO = VVNEG VCL = VVREFIN VENABLE = 5V (open) VRESTART = VVNEG (open) FIGURE 2-8: PWRGOOD Output Low Voltage (VOL) vs. Temperature. 2002-2012 Microchip Technology Inc. MCP18480 PWRGOOD VOH (%VPOS) 97.3 97.0 96.8 96.5 96.3 96.0 95.8 95.5 -40 -20 0 20 40 60 80 Temperature (C) PWRGOOD Output Impedance (Ohms) 245 97.5 235 225 215 205 195 185 175 165 155 -40 Data taken with the minimum following conditions: ILOAD = -1 mA IPOS = 5 mA (Enables VPOS at its self-regulating voltage) VREFIN = 2.5V, ISET = 10 A Note 1: VUVTH > VVREFIN VOVTH < VVREFIN VSENSE = VVNEG VVFB = VVNEG VDRAINTH = VVNEG VOVO = VVNEG VCL = VVREFIN VENABLE = 5V (open) VRESTART = VVNEG (open) FIGURE 2-9: PWRGOOD Output HighVoltage (VOH) vs. Temperature. 2002-2012 Microchip Technology Inc. -20 0 20 40 Temperature (C) 60 80 Data taken with the minimum following conditions: IPOS = 5 mA (Enables VPOS at its self-regulating voltage) VREFIN = 2.5V, ISET = 10 A Note 1: VUVTH > VVREFIN VOVTH < VVREFIN VSENSE = VVNEG VVFB = VVNEG VDRAINTH = VVNEG VOVO = VVNEG VCL = VVREFIN VENABLE = 5V (open) VRESTART = VVNEG (open) FIGURE 2-10: PWRGOOD Output HighImpedance vs. Temperature. DS20091C-page 19 PWRGOOD Output Impedance (Ohms) MCP18480 250 240 230 220 210 200 190 180 -40 -20 0 20 40 60 80 Temperature (C) Data taken with the minimum following conditions: IPOS = 5 mA (Enables VPOS at its self-regulating voltage) VREFIN = 2.5V, ISET = 10 A Note 1: VUVTH > VVREFIN VOVTH < VVREFIN VSENSE = VVNEG VVFB = VVNEG VDRAINTH = VVNEG VOVO = VVNEG VCL = VVREFIN VENABLE = 5V (open) VRESTART = VVNEG (open) FIGURE 2-11: PWRGOOD Output LowImpedance vs. Temperature. DS20091C-page 20 2002-2012 Microchip Technology Inc. MCP18480 2.498 TA = +85C 2.494 TA = 0C 2.492 VREFOUT (V) 2.495 2.493 TA = -40C 2.5 TA = +70C 2.496 TA = 0C 2.0 1.5 TA = +25C 1.0 TA = +70C 0.5 2.491 TA = -40C 3 4 5 TA = +85C 0.0 2.490 6 7 8 9 10 11 12 13 14 15 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5 3.75 4 4.25 4.5 4.75 5 VREFOUT (V) 3.0 TA = +25C 2.497 Supply Current, IPOS (mA) LOAD Current (mA) Data taken with the minimum following conditions: Data taken with the minimum following conditions: 3 mA IPOS 30 mA IPOS = 5 mA (Enables VPOS at its self-regulating voltage) VREFIN = 2.5V, Iset = 10 A VREFIN = 2.5V, ISET = 10 A FIGURE 2-12: (IPOS). VREFOUT vs. Supply Current 2002-2012 Microchip Technology Inc. FIGURE 2-13: VREFOUT vs. LOAD. DS20091C-page 21 MCP18480 0 TA = +85C 2.0 1.8 TA = +25C 1.6 1.4 TA = -40C 1.2 -25 -50 -75 -100 -125 -150 -175 TA = -40C TA = +25C TA = -40C TA = +25C -20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 2 4 6 8 10 12 14 16 18 20 -200 -225 TA = +85C TA = +85C 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1.0 Timer Pin Current (A) Timer Pin Current (uA) 2.2 RDISCH Current (uA) ISET Current (uA) Data taken with the minimum following conditions: Data taken with the minimum following conditions: -50 A < IISET < 50 A (IISET 0) IPOS = 5 mA (Enables VPOS at its self-regulating voltage) VREFIN = 2.5V -50 A < IISET < 50 A (IISET 0) IPOS = 5 mA (Enables VPOS at its self-regulating voltage) VREFIN = 2.5V Note 1: Note 1: VUVTH > VVREFIN VOVTH < VVREFIN VSENSE = VVNEG VVFB = VVNEG VDRAINTH = VVNEG VOVO = VVNEG VCL = VVREFIN VENABLE = 5V (open) VRESTART = VVNEG (open) VUVTH > VVREFIN VOVTH < VVREFIN VSENSE 100mV VVFB = VVNEG VDRAINTH = VVNEG VOVO = VVNEG VCL = VVREFIN VENABLE = 5V (open) VRESTART = VVNEG (open) FIGURE 2-14: TIMER Pin Output Low Current vs. RDISCH Current. DS20091C-page 22 FIGURE 2-15: TIMER Pin Output High Current vs. ISET Current. 2002-2012 Microchip Technology Inc. MCP18480 112 TA = +85C DRAINTH Voltage (mV) UVD Pin Current (A) 0 -10 -20 TA = -40C -30 TA = +70C TA = 0C -40 TA = +85C -50 TA = +25C -60 111 TA = +70C 110 TA = +25C 109 TA = 0C 108 107 TA = -40C 106 105 -50 -40 -30 -20 -10 0 10 20 30 40 50 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Supply Current, IPOS (mA) ISET Pin Current (A) Data taken with the minimum following conditions: Data taken with the minimum following conditions: -50 A < IISET < 50 A (IISET 0) IPOS = 5 mA (Enables VPOS at its self-regulating voltage) VREFIN = 2.5V 3 mA IPOS 30 mA Determined by PWRGOOD signal Note 1: Note 1: VUVTH < VVREFIN VOVTH < VVREFIN VSENSE VVNEG VVFB = VVNEG VDRAINTH = VVNEG VOVO = VVNEG VCL = VVREFIN VENABLE = 5V (open) VRESTART = VVNEG (open) VUVTH > VVREFIN VOVTH < VVREFIN VSENSE = VVNEG VVFB = VVNEG VOVO = VVNEG VCL = VVREFIN VENABLE = 5V (open) VRESTART = VVNEG (open) FIGURE 2-16: Current. UVD Pin Current vs. ISET Pin VREFIN = 2.5V, ISET = 10 A FIGURE 2-18: DRAINTH Threshold Voltage vs. Supply current (IPOS). ISET Pin Voltage (V) 1.35 1.30 TA = +70C 1.25 1.20 TA = +25C TA = 0C TA = -40C 1.15 1.10 1.05 1.00 2.00 TA = +85C 2.10 2.20 2.30 2.40 2.50 2.60 VREFIN Pin Voltage (V) Data taken with the minimum following conditions: IPOS = 5 mA (Enables VPOS at its self-regulating voltage) Iset = 10 A FIGURE 2-17: Pin Voltage. ISET Pin Voltage vs. VREFIN 2002-2012 Microchip Technology Inc. DS20091C-page 23 MCP18480 1.310 TA = -40C 860 850 TA = +25C 840 830 TA = +85C 820 RDISCH Voltage (V) RDISCH Current (nA) 870 1.300 TA = +85C 1.290 1.280 1.270 TA = +25C 1.260 TA = -40C 1.250 5 10 15 20 25 0 5 10 15 20 25 30 35 40 45 50 RDISCH Current (uA) Supply Current, IPOS (mA) Data taken with the minimum following conditions: Data taken with the minimum following conditions: IPOS = 5 mA (Enables VPOS at its self-regulating voltage) VREFIN = 2.5V, ISET = 10 A RDISCH = 16 M IPOS = 5 mA (Enables VPOS at its self-regulating voltage) VREFIN = 2.5V, ISET = 10 A IRDISCH from 100 nA to 10 A (500 nA steps) Note 1: Note 1: VUVTH > VVREFIN VOVTH < VVREFIN VSENSE = VVNEG VVFB = VVNEG VDRAINTH = VVNEG VOVO = VVNEG VCL = VVREFIN VENABLE = 5V (open) VRESTART = VVNEG (open) VUVTH > VVREFIN VOVTH < VVREFIN VSENSE = VVNEG VVFB = VVNEG VDRAINTH = VVNEG VOVO = VVNEG VCL = VVREFIN VENABLE = 5V (open) VRESTART = VVNEG (open) FIGURE 2-19: Current (IPOS). DS20091C-page 24 RDISCH Current vs. Supply FIGURE 2-20: Current. RDISCH Voltage vs. RDISCH 2002-2012 Microchip Technology Inc. MCP18480 Enable/Restart, V IL (V) 1.43 1.42 1.41 1.40 1.39 1.38 1.37 1.36 -40 -20 0 20 40 60 80 Temperature (C) Data taken with the minimum following conditions: IPOS = 5 mA (Enables VPOS at its self-regulating voltage) VREFIN = 2.5V, ISET = 10 A Determined by GATE voltage Note 1: VUVTH > VVREFIN VOVTH < VVREFIN VSENSE = VVNEG VVFB = VVNEG VDRAINTH = VVNEG VOVO = VVNEG VCL = VVREFIN VRESTART = VVNEG (open) FIGURE 2-21: ENABLE/RESTART Pin Trip Point Voltage vs. Temperature. 2002-2012 Microchip Technology Inc. DS20091C-page 25 -152.0 87.0 86.5 86.0 85.5 85.0 84.5 84.0 83.5 83.0 82.5 82.0 -152.3 Timer Current (uA) Timer Current (nA) MCP18480 -152.5 -152.8 -153.0 -153.3 -153.5 -153.8 -154.0 -40 -20 0 20 40 Temperature (C) 60 -40 80 -20 0 20 40 60 80 Temperature (C) Data taken with the minimum following conditions: Data taken with the minimum following conditions: RDISCH = 16 M IPOS = 5 mA (Enables VPOS at its self-regulating voltage) VREFIN = 2.5V, ISET = 10 A 0.1V VTIMER 1.25V RDISCH = 16 M IPOS = 5 mA (Enables VPOS at its self-regulating voltage) VREFIN = 2.5V, ISET = 10 A 0.1V VTIMER 1.25V Note 1: Note 1: VUVTH > VVREFIN VOVTH < VVREFIN VSENSE = VNEG, I into device VNEG + 100mV, I out of device VVFB = VVNEG VDRAINTH = VVNEG VOVO = VVNEG VCL = VVREFIN VENABLE = 5V (open) VRESTART = VVNEG (open) VUVTH > VVREFIN VOVTH < VVREFIN VSENSE = VNEG, I into device VNEG + 100mV, I out of device VVFB = VVNEG VDRAINTH = VVNEG VOVO = VVNEG VCL = VVREFIN VENABLE = 5V (open) VRESTART = VVNEG (open) FIGURE 2-22: vs. Temperature. DS20091C-page 26 TIMER Output Sink Current FIGURE 2-23: TIMER Output Source Current vs. Temperature. 2002-2012 Microchip Technology Inc. 55 1.50 VSENSE = 30 mV SENSE Pin Voltage (mV) CL Pin Offset Voltage, VOS (mV) MCP18480 1.00 0.50 VSENSE = 20 mV 0.00 -0.50 -1.00 VSENSE = 40 mV -1.50 -2.00 50 Vfb = 0V 45 40 Vfb = 0.25V 35 30 25 20 Vfb = 0.5V Vfb = 1V 15 10 -2.50 -40 -20 0 20 40 60 80 -40 -20 0 20 40 60 80 Temperature (C) Temperature (C) Data taken with the minimum following conditions: Data taken with the minimum following conditions: IPOS = 5 mA (Enables VPOS at its self-regulating voltage) VREFIN = 2.5V, ISET = 10 A IPOS = 5 mA (Enables VPOS at its self-regulating voltage) VREFIN = 2.5V, ISET = 10 A Use TIMER pin as indicator Note 1: VUVTH > VVREFIN VOVTH < VVREFIN VSENSE = 25mV VVFB = VVNEG VDRAINTH = VVNEG VOVO = VVNEG VCL = VVREFIN VENABLE = 5V (open) VRESTART = VVNEG (open) FIGURE 2-24: vs. Temperature. CL pin Input Offset Voltage 2002-2012 Microchip Technology Inc. Note 1: VUVTH > VVREFIN VOVTH < VVREFIN VVFB = VNEG, VNEG+ 250mV, VNEG+500mv, VNEG+1V VDRAINTH = VVNEG VOVO = VVNEG VCL = VVREFIN VENABLE = 5V (open) VRESTART = VVNEG (open) FIGURE 2-25: vs. Temperature. SENSE Pin Input Threshold DS20091C-page 27 7.0 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 OVTH Input Low Voltage, VIL (V) OVTH Input High Voltage (V) MCP18480 TA = +85C TA = -40C TA = +70C TA = +25C TA = +0C 0.0 1.0 2.0 3.0 4.0 5.0 OVO Voltage (V) 6.0 7.0 2.480 TA = +85C TA = +70C 2.479 TA = +25C 2.478 2.477 2.476 TA = 0C 2.475 TA = -40C 2.474 0 8.0 1 2 3 4 5 6 7 8 OVO Voltage (V) Data taken with the minimum following conditions: Data taken with the minimum following conditions: IPOS = 5 mA (Enables VPOS at its self-regulating voltage) OVO = VNEG to 8V VREFIN = 2.5V, ISET = 10 A Use PWRGOOD pin as indicator IPOS = 5 mA (Enables VPOS at its self-regulating voltage) OVO = VNEG to 8V VREFIN = 2.5V, ISET= 10 A Use PWRGOOD pin as indicator Note 1: Note 1: VUVTH > VVREFIN VSENSE = VVNEG VVFB = VVNEG VDRAINTH = VVNEG VCL = VVREFIN VENABLE = 5V (open) VRESTART = VVNEG (open) VUVTH > VVREFIN VSENSE = VVNEG VVFB = VVNEG VDRAINTH = VVNEG VCL = VVREFIN VENABLE = 5V (open) VRESTART = VVNEG (open) FIGURE 2-26: vs. OVO Voltage. DS20091C-page 28 OVTH Input Rising Threshold FIGURE 2-27: OVTH Input Falling Threshold vs. OVO Voltage. 2002-2012 Microchip Technology Inc. -9.90 UVD Current (uA) TA = -40C -9.95 TA = 0C -10.00 TA = +25C -10.05 TA = +70C -10.10 TA = +85C -10.15 5 10 15 20 25 UVHYS Pin Impedance (Ohms) MCP18480 45000 40000 35000 30000 25000 20000 15000 OFF 10000 5000 ON 0 -40 30 -20 0 20 40 60 80 Temperature (C) Supply Current, IPOS (mA) Data taken with the minimum following conditions: Data taken with the minimum following conditions: IPOS = 5 mA self regulating voltage) (Enables VPOS at its self-regulating VREFIN = 2.5V, ISET = 10 A IPOS = 5 mA (Enables VPOS at its self-regulating voltage) UVTH < VREFIN, UVTH > VREFIN VREFIN = 2.5V, ISET = 10 A Note 1: VUVTH < VVREFIN VOVTH < VVREFIN VSENSE VVNEG VVFB = VVNEG VDRAINTH = VVNEG VOVO = VVNEG VCL = VVREFIN VENABLE = 5V (open) VRESTART = VVNEG (open) FIGURE 2-28: Current (IPOS). UVD Current vs. Supply 2002-2012 Microchip Technology Inc. Note 1: VOVTH < VVREFIN VSENSE = VVNEG VVFB = VVNEG VDRAINTH = VVNEG VOVO = VVNEG VCL = VVREFIN VENABLE = 5V (open) VRESTART = VVNEG (open) FIGURE 2-29: Temperature. UVHYS Pin Impedance vs. DS20091C-page 29 MCP18480 2.5035 UVTH Falling Threshold (V) UVTH Rising Threshold (V) 2.5034 2.5032 2.5030 2.5028 2.5026 2.5024 2.5022 2.5020 2.5018 -40 -20 0 20 40 60 2.5030 2.5025 2.5020 2.5015 2.5010 80 -40 -20 0 20 40 60 80 Temperature (C) Temperature (C) Data taken with the minimum following conditions: Data taken with the minimum following conditions: IPOS = 5 mA (Enables VPOS at its self-regulating voltage) VREFIN = 2.5V, ISET = 10 A Use PWRGOOD pin as indicator IPOS = 5 mA (Enables VPOS at its self-regulating voltage) VREFIN = 2.5V, ISET = 10 A Use PWRGOOD pin as indicator Note 1: Note 1: VOVTH < VVREFIN VSENSE = VVNEG VVFB = VVNEG VDRAINTH = VVNEG VOVO = VVNEG VCL = VVREFIN VENABLE = 5V (open) VRESTART = VVNEG (open) VOVTH < VVREFIN VSENSE = VVNEG VVFB = VVNEG VDRAINTH = VVNEG VOVO = VVNEG VCL = VVREFIN VENABLE = 5V (open) VRESTART = VVNEG (open) FIGURE 2-30: UVTH Input Rising Threshold vs. Temperature. DS20091C-page 30 FIGURE 2-31: UVTH Input Falling Threshold vs. Temperature. 2002-2012 Microchip Technology Inc. MCP18480 OVTH Falling Threshold (V) OVTH Rising Threshold (V) 2.4805 2.5087 2.5082 2.5077 2.5072 2.5067 2.5062 2.48 2.4795 2.479 2.4785 2.478 2.4775 2.5057 -40 -20 0 20 40 60 -40 80 Temperature (C) -20 0 20 40 60 80 Temperature (C) Data taken with the minimum following conditions: Data taken with the minimum following conditions: IPOS = 5 mA (Enables VPOS at its self-regulating voltage) VREFIN = 2.5V, ISET = 10 A Use PWRGOOD pin as indicator IPOS = 5 mA (Enables VPOS at its self-regulating voltage) VREFIN = 2.5V, ISET = 10 A VUVHYS = VNEG Use PWRGOOD pin as indicator Note 1: VOVTH < VVREFIN VSENSE = VVNEG VVFB = VVNEG VDRAINTH = VVNEG VOVO = VVNEG VCL = VVREFIN VENABLE = 5V (open) VRESTART = VVNEG (open) FIGURE 2-32: vs. Temperature. OVTH Input Rising Threshold 2002-2012 Microchip Technology Inc. Note 1: VOVTH < VVREFIN VSENSE = VVNEG VVFB = VVNEG VDRAINTH = VVNEG VOVO = VVNEG VCL = VVREFIN VENABLE = 5V (open) VRESTART = VVNEG (open) OVTH Input Falling FIGURE 2-33: Threshold vs. Temperature. DS20091C-page 31 MCP18480 NOTES: DS20091C-page 32 2002-2012 Microchip Technology Inc. MCP18480 3.0 PIN DESCRIPTIONS TABLE 3-1: Pin Name MCP18480 PIN DESCRIPTIONS Pin Number Pin Direction Buffer Type I P Description SSOP VPOS 1 Positive supply input. Internal Shunt Regulator connected between VPOS and VNEG limits the potential to 12V between these two pins. A series resistor must be placed on the VPOS pin to limit the current into the device. OVTH 2 I A Overvoltage protection threshold. An external resistor divider network is connected to this input pin to program the overvoltage protection threshold. The selected external resistor values for the OVTH to system ground and OVTH to VNEGresistors should have currents in the 1 mA range. A typical Overvoltage threshold is -76V. Internal hysteresis in the overvoltage input comparator will allow proper operation once VNEG falls below the selected threshold. UVTH 3 I A Undervoltage lockout threshold. An external resistor divider network is connected to this input pin to program the undervoltage lockout threshold. If the voltage on UVTH is less than VNEG + 2.5V, the undervoltage comparator will trip, indicating an Undervoltage condition. An external hysteresis resistor can be used to set the high-to-low (VTHF) threshold below the low-to-high (VTHR) threshold. For telecom network equipment, it is desirable to have shutdown occur at -38.5V and the startup set at -43.0V. UVHYS 4 I A Undervoltage internal comparator hysteresis. An external resistor is connected between this input to the UVTH input pin to adjust the hysteresis of the internal Undervoltage comparator. Since it is desirable to shut down at -38.5V and restart at -43.0V in telecom switch equipment. UVD 5 I/O A Undervoltage event delay. An external capacitor is connected to this input pin to set the delay between when the UVTH pin drops below the trip point specified by the voltage on the VREFIN pin and when the system shutdown occurs (causing the PWRGOOD pin to be driven to an inactive level and the GATE pin to be pulled to the VNEG pin voltage level). The UVD pin sources a current equivalent to the IISET (in typical applications, the IISET current equals 10 A), which charges this external capacitor while an internal comparator compares this voltage on the UVD pin to |VREFIN|/2. Typically, for telecom equipment, the system is expected to shut down when the input voltage falls below -38.5V (1.0V DC) for greater than 100 ms. Legend: TTL = TTL compatible input I = Input P = Power A = Analog 2002-2012 Microchip Technology Inc. ST = Schmitt Trigger input with CMOS levels O = Output CMOS = CMOS-compatible input D = Digital DS20091C-page 33 MCP18480 TABLE 3-1: Pin Name MCP18480 PIN DESCRIPTIONS (CONTINUED) Pin Number Pin Direction Buffer Type O A Description SSOP VREFOUT 6 Reference output. Internal reference output voltage (typically 2.5V). Usually tied back to the VREFIN pin unless an external high-precision reference voltage is desired. VREFIN 7 I A Reference input. This pin allows a high-precision reference voltage for the following functions: * * * * Undervoltage Comparator Overvoltage Comparator DRAIN Comparator Current Limit Timer If the precision of the VREFOUT output voltage is acceptable, tie the VREFOUT pin to the VREFIN pin. CL 8 I A Current Limit. Input used to set the maximum current limit threshold allowed by the system via a resistor divider network (with the resistor RCL1 between the VREFIN pin and the CL pin and resistor RCL between the VNEG pin and the CL pin). If the voltage across the sense resistor exceeds the voltage on the CL pin, it implies that there is excessive current over the allowed limit and forces the GATE pin to the VNEG pin voltage level without delay. ISET 9 I A Current source set. Establishes the internal ISOURCE for the following: * Undervoltage Delay * Current Limit Timer * GATE Pin Source Current An external resistor RISET from the ISET pin must be connected to either the VNEG pin or the VREFIN pin to set IBIAS, which will then establish the current sources throughout the device. The IBIAS current is the same for either connection. Connecting the RISET resistor to the VNEG pin will establish the PWRGOOD pin output polarity to be active-high. Connecting the RISET resistor to the VREFIN pin will establish the PWRGOOD pin output polarity to be active-low. Legend: TTL = TTL compatible input I = Input P = Power A = Analog DS20091C-page 34 ST = Schmitt Trigger input with CMOS levels O = Output CMOS = CMOS-compatible input D = Digital 2002-2012 Microchip Technology Inc. MCP18480 TABLE 3-1: Pin Name MCP18480 PIN DESCRIPTIONS (CONTINUED) Pin Number Pin Direction Buffer Type I A Description SSOP TIMER 10 Current Limit Timer. The value of the external capacitor (CTIMER) connected to the TIMER pin sets the two time periods used during a current-limit event. These are: * The time that the GATE pin will limit the current through the external FET * The time that the GATE pin will disable the external FET During current limit, a pull-up current source charges up the external capacitor. Until the voltage on the TIMER pin reaches VREFIN/2, the GATE pin is driven to maintain a reduced current flow determined by the VDS of the external FET. While the capacitor is being discharged by the pull-down current (pullup current is off), the GATE pin is at VNEG and the PWRGOOD pin is deasserted. When the TIMER voltage falls below approximately 100 mV, the GATE pin turns on, if the RESTART pin is low, to reset the internal fault latch. If the RESTART pin is high, the GATE pin remains off until the ENABLE pin is forced low. It is then forced high or the RESTART pin is forced low (asserted). The PWRGOOD pin reasserts after the voltages on the DRAINTH and GATE pins meet the appropriate conditions. The TIMER pin pull-up current is proportioned to the IISET current (approximately a multiple of 16). VNEG 11 I P Negative supply input. The negative voltage applied to the board by the backplane (typically the most negative voltage in the system). RDISCH 12 I A External MOSFET activation delay. An external resistor (RRDISCH) is connected between the RDISCH pin and the VNEG pin and is used to set the delay between the deactivation and activation of the external pass MOSFET during a current-limit event. The delay is set by the values of the external capacitor (CTIMER) and the external resistor (RRDISCH). The formulas are: TDEACT = (CTIMER x RISET) / 16 TACT = (9.2 x RRDISCH x CTIMER) Legend: TTL = TTL compatible input I = Input P = Power A = Analog 2002-2012 Microchip Technology Inc. ST = Schmitt Trigger input with CMOS levels O = Output CMOS = CMOS-compatible input D = Digital DS20091C-page 35 MCP18480 TABLE 3-1: Pin Name MCP18480 PIN DESCRIPTIONS (CONTINUED) Pin Number Pin Direction Buffer Type I A Description SSOP SENSE 13 Over-current sense. The voltage on the SENSE input pin is used to detect over-current conditions in the load connected to the external MOSFET. This pin is directly connected to the source of the MOSFET, with an external resistor (RSENSE) (typically a low resistance) connected between the source of the MOSFET and VNEG. GATE 14 O A MOSFET gate driver. The GATE output pin attaches to the gate of the external MOSFET. The voltage on the GATE pin is pulled to the voltage on the VNEG pin whenever the voltage on the UVTH pin is less than the voltage on the VREFIN pin, or the voltage on the OVTH pin is greater than the voltage on the VREFIN pin. The GATE pin is also pulled to the voltage on the VNEG pin when the ENABLE input pin is low. When current limit is reached, the voltage on the GATE pin is adjusted to maintain a constant voltage across the RSENSE resistor while the CTIMER capacitor starts to charge. When the voltage on CTIMER exceeds VREFIN/2, the GATE pin is pulled to VNEG to turn off the external MOSFET. A RC network can be added from the GATE pin to the drain of the external MOSFET, along with a capacitor from the GATE pin to the VNEG pin, to control the slew rate of the GATE pin. The GATE pin pull-up current is proportioned to the IISET current. VFB 15 I A External MOSFET drain monitor. The VFB input pin monitors the voltage at the drain of the external power MOSFET switch with respect to the voltage on the VNEG pin for use by the internal foldback circuitry. An external resistor divider network (RFB1 and RFB2) is attached between the drain of this external MOSFET and the VNEG pin (RFB1 is connected between the drain of the external MOSFET and the VFB pin, while RFB2 is connected between the VFB pin and the VNEG pin). This prevents high-voltage breakdown of the VFB input. DRAINTH 16 I A MOSFET drain comparator threshold. This pin is used during the power-up sequence of the inserted board, and after any fault condition that `turns off' the GATE pin drive. The voltage on the pin indicates when the external FET is fully enhanced by comparing the pin voltage to an internal reference voltage (approximately 100 mV derived from the internal band gap reference). An external resistor divider network (RDRAIN1 and RDRAIN2) is attached between the drain of this external MOSFET and the VNEG pin (RDRAIN1 is connected between the drain of the external MOSFET and the DRAINTH pin while RDRAIN2 is connected between the DRAINTH pin and the VNEG pin). Legend: TTL = TTL compatible input I = Input P = Power A = Analog DS20091C-page 36 ST = Schmitt Trigger input with CMOS levels O = Output CMOS = CMOS-compatible input D = Digital 2002-2012 Microchip Technology Inc. MCP18480 TABLE 3-1: Pin Name MCP18480 PIN DESCRIPTIONS (CONTINUED) Pin Number Pin Direction Buffer Type I A Description SSOP OVO 17 Overvoltage detect. Typically for normal operation. This pin is tied to VNEG. This feature allows the overvoltage detection input to monitor an overvoltage condition across the power module. The voltage is sensed at the drain of the external MOSFET. The voltage across the load is internally determined based upon: * The voltage difference between system ground and the voltage on the VNEG pin * The voltage difference between the drain of the external FET and the voltage on the VNEG pin An external resistor divider network (ROVO1 and ROVO2) is attached between the drain of the external MOSFET and the VNEG pin (ROVO1 is connected between the drain of the external MOSFET and the OVO pin, while ROVO2 is connected between the OVO pin and the VNEG pin). When the voltage across the external MOSFET (source-to-drain) equals system ground voltage (- VNEG +), the maximum desired load voltage, the GATE pin is forced to the voltage on the VNEG pin (disabling the external MOSFET). To detect Overvoltage on the board (instead of the load) directly, connect the OVO pin to the VNEG pin. PWRGOOD 18 O D Power Good indicator. This state of the output is determined by four conditions. These are: * * * * Undervoltage Overvoltage Current Limit External FET is fully-enhanced (from DRAINTH pin on power-up) PWRGOOD is a CMOS logic voltage (VNEG or VNEG+12V). PWRGOOD is active when the device has completed power-up and the system is neither in an Undervoltage or Overvoltage condition. Connecting the RISET pin to the VNEG pin configures the PWRGOOD pin to be active high. Connecting the RISET pin to the VREF pin configures the PWRGOOD pin to be active low. ENABLE 19 I TTL Enable Gate driver. Used to enable the GATE pin and assert the PWRGOOD pin. The ENABLE pin is active-high and is internally pulled up to 5V. This pin is pulled low by the user to clear the current limit latch when a currentlimit fault occurs with RESTART high, or to disable the GATE pin. H = Enable the GATE and PWRGOOD pins. L = Disables the GATE pin, deasserts the PWRGOOD pin and clears current limit latch. When the ENABLE pin is high, fault conditions will disable the GATE pin and deasserts the PWRGOOD pin. Legend: TTL = TTL compatible input I = Input P = Power A = Analog 2002-2012 Microchip Technology Inc. ST = Schmitt Trigger input with CMOS levels O = Output CMOS = CMOS-compatible input D = Digital DS20091C-page 37 MCP18480 TABLE 3-1: Pin Name MCP18480 PIN DESCRIPTIONS (CONTINUED) Pin Number Pin Direction Buffer Type I TTL Description SSOP RESTART 20 Auto-restart enable. Enables the auto-restart feature of the device after an over-current fault. L = The internal fault latch is reset and the device attempts to restart with a frequency determined by the values of the external components CTIMER and RDISCH. H = The auto-restart is disabled, allowing the GATE pin to remain at the VNEG pin voltage after an over-current fault. Internally pulled down to the VNEG pin voltage. Legend: TTL = TTL compatible input I = Input P = Power A = Analog DS20091C-page 38 ST = Schmitt Trigger input with CMOS levels O = Output CMOS = CMOS-compatible input D = Digital 2002-2012 Microchip Technology Inc. MCP18480 4.0 APPLICATIONS INFORMATION For active-high DC/DC converter modules, the MCP18480 should be programmed for a low active PWRGOOD output. Connecting RISET to the VREFIN pin will enable an active-low PWRGOOD output. Refer to Figure 4-1 and Figure 4-2 for schematics. The MCP18480 can be programmed to have the PWRGOOD signal be either active-high or active-low via the ISET pin and the connection of the external RISET resistor (see Section 6.8.8, "Bias Block"). If the RISET resistor is connected between ISET and VNEG, the PWRGOOD output pin is an active-high signal. If the RISET resistor is connected between ISET and VREFIN, the PWRGOOD output pin is an active-low signal. Figure 4-1 shows a typical telecom application circuit where the DC/DC module is active-high. Figure 4-2 shows a typical telecom application circuit where the DC/DC module is active-low. The polarity of the MCP18480's PWRGOOD pin (active-high or activelow) is dependant on the state of the ISET pin. For systems using an active-low-enabled DC/DC converter module, the MCP18480 should be programmed for a high-active PWRGOOD output. Tying the RISET resistor to the VNEG pin configures the PWRGOOD to be an active-high signal. The active-high PWRGOOD switches on the external NPN and the collector of the external NPN (labeled as GOODPWR) is pulled to VNEG, enabling a low-active GOODPWR and resulting in enabling the DC/DC module. GND VIN+ VOUT+ RBYPL 51 k RZ RPOS ROV1 4 k 1.74 M CBYP1 + 2 F CBYP2 10 nF 78V Transorb ROV2 59 k RUV2 5V RUVHYS 280 k 30.9 k CUVD 800 nF RISET 124 k Fuse 10A VNEG 1 VPOS RESTART 20 2 OVTH ENABLE 19 3 UVTH PWRGOOD 18 4 UVHYS 5 UVD 6 VREFOUT 7 VREFIN 8 CL SENSE 13 9 ISET RDISCH 12 Ctimer 680 nF OVO 17 SEN RPG1 110 k RPG3 680 RPG4 QPG2 2N5400 GOODPWR 36 k Q PG1 MPSA43 RPG5 36 k ON/OFF VIN- VOUT- QPG3 NTE261 RPG6 DRAINTH 16 10 TIMER DC/DC Converter Module SRS 24.9 k RUV1 453 k CBYPL 100 F 100 V 1500 VFB 15 GATE 14 VNEG 11 MCP18480 RDISCH 1.6 M RGD 18 k RPG2 7.5 k RSENSE 0.01 CG1 RG1 100 nF 10 CGD 3.3 nF M1 NTE2388 RFB2 RFB1 124 k 1.74 M RDRAIN2 RDRAIN1 115 k 1.6 M FIGURE 4-1: Typical Operating Circuit for Telecom Applications with Active-High power Module foldback current limit enabled. 2002-2012 Microchip Technology Inc. DS20091C-page 39 MCP18480 GND VIN+ VOUT+ RBYPL 51 k RZ ROV1 RPOS 4 k 1.74 M CBYP1 + 2 F CBYP2 10 nF 78V Transorb ROV2 59 k 453 k RUV2 5V RUVHYS 280 k 30.9 k CUVD 800 nF RISET VPOS 2 OVTH ENABLE 19 3 UVTH PWRGOOD 18 4 UVHYS 5 UVD 6 VREFOUT 7 VREFIN 8 CL SENSE 13 9 ISET RDISCH 12 124 k Fuse 10A VNEG RESTART 20 1 Ctimer 680 nF OVO 17 SEN RPG1 RPG3 680 RPG4 36 k 110 k QPG2 2N5400 GOODPWR QPG1 MPSA43 RPG5 36 k VFB 15 ON/OFF VIN- VOUT- QPG3 NTE261 RPG6 1500 DRAINTH 16 10 TIMER DC/DC Converter Module SRS 24.9 k RUV1 CBYPL 100 F 100 V GATE 14 VNEG 11 MCP18480 RDISCH 1.6 M RPG2 7.5 k RSENSE 0.01 RGD 18 k CG1 RG1 100 nF 10 CGD 3.3 nF M1 NTE2388 RFB2 RFB1 124 k 1.74 M RDRAIN2 RDRAIN1 115 k 1.6 M FIGURE 4-2: Typical operating circuit for telecom applications with Active-Low power Module foldback current limit enabled. DS20091C-page 40 2002-2012 Microchip Technology Inc. MCP18480 The MCP18480 can typically be implemented in a backplane system in one of two methods. Figure 4-3 shows a system where the backplane integrates the MCP18480 for every slot. Figure 4-4 shows a system where the backplane does not integrate the MCP18480s and each card that will be inserted into any slot is required to integrate the MCP18480. Card #n Card #2 Card #1 MCP18480 MCP18480 MCP18480 FIGURE 4-3: Backplane System Block Diagram #1. Card # n MCP18480 Card # 2 Card # 1 MCP18480 MCP18480 FIGURE 4-4: Backplane System Block Diagram #2. 2002-2012 Microchip Technology Inc. DS20091C-page 41 MCP18480 NOTES: DS20091C-page 42 2002-2012 Microchip Technology Inc. MCP18480 5.0 POWER-UP 5.1 VPOS and VNEG Connection 6.0 INTERNAL SIGNAL DESCRIPTIONS For proper system operation, it is required that the system ground and the VNEG pin have a solid connection before voltages are applied to any logic on the board. The figure on page 2 illustrates a block diagram of the MCP18480. Between the functional blocks, there are some signals that have been named. These signals are briefly explained in Section 6.1 thru Section 6.7. 5.2 6.1 The Board Circuitry After the MCP18480 has "good" voltages on the VPOS and VNEG pins, the board may have voltages applied to any of the other signals (a "good" voltage on VPOS indicates a "good" voltage on the system ground). The MCP18480 will start to source a small current to the external MOSFET to begin powering the board. This will turn on the MOSFET starting to power the external circuitry (load) of the board. The current from the GATE pin (into the external MOSFET) increases as the VDS of the MOSFET decreases. When the VDS of the MOSFET is below the voltage determined by the two resistors on the DRAINTH pin (RDRAIN1 and RDRAIN2), and the voltage on the GATE pin is greater than 8V, the PWRGOOD pin is active. Undervoltage Active A signal that indicates (when low) that System Ground - VNEG is less then the minimum voltage. 6.2 Overvoltage Active A signal that indicates (when low) that System Ground -VNEG is greater then the maximum voltage. 6.3 LATCHOFF A signal that controls the GATE pin due to a timeout of the current-limiting timer. 6.4 Current Limit TIMER A signal that controls the reduction of source current on the GATE pin and starts the voltage ramp of the current limit timer. 6.5 Current Limit Feedback A voltage that is proportional to the VDS of the external MOSFET to set a trip point for current-limiting. 6.6 TIMEOUT A signal that indicates the completion of the foldback time and is used to start the latchoff time. 6.7 Circuit Breaker A signal that immediately causes the GATE pin output to be driven to VNEG upon the detection of excessive current in the external FET. 2002-2012 Microchip Technology Inc. DS20091C-page 43 MCP18480 6.8 DESCRIPTION OF INTERNAL BLOCKS The internal blocks shown in the MCP18480 Block Diagram on page 2 are discussed in Section 6.8.1 through Section 6.8.8. Note: 6.8.1 Voltage levels discussed are with respect to external component values selected in Figure 4-1. UV (UNDERVOLTAGE) BLOCK The Undervoltage lockout circuit monitors the input voltage by comparing a centertap voltage on an external resistor divider to a 2.5V reference. The centertap voltage is fed into the UVTH input pin. If the voltage on the UVTH pin is below the internal 2.5V reference, the absolute magnitude of the supply voltage is too low for proper system operation, resulting in the external MOSFET being turned off. If the voltage on the UVTH pin is greater than VNEG + 2.5V, the supply voltage is above the minimal operating voltage as set by the external resistor divider network. In telecom network applications, it is common to shut down the DC/DC converter supply when the input voltage falls below -38.5V (tolerance of 1.0V) for greater than 100 ms. The system will not restart until the voltage exceeds -43.0V (tolerance of 0.5V). This voltage difference is produced by an open-drain NMOS output (the UVHYS pin) that connects an external resistor in parallel with the lower of the two resistors in the external UV divider network until the supply ramps down to -43V. When the UVTH pin exceeds VNEG + 2.5V, the internal NMOS transistor is turned off, disconnecting the external resistor connected to the UVHYS pin. The voltage at the UVTH pin increases to 2.79V. The supply voltage would have to decrease to -38.5V in order to assert the internal "Undervoltage Active" signal. If the supply voltage dips below the programmed threshold, the input comparator trips the other way. The timing capacitor is released to ramp-up at the previously described rate and the Undervoltage block switches when the capacitor voltage reaches 1.25V. When the input comparator goes to a low level, the hysteresis FET is turned on and the trip point for reassertion of good VNEG reverts to -43V. While the Undervoltage Active signal is low (includes Undervoltage input filter), the GATE pin driver for the external MOSFET is disabled, the GATE pin is pulled to the voltage of the VNEG pin with a 60 mA current sink and the PWRGOOD output pin is deasserted to indicate that the input voltage is out of range. EQUATION 6-2: UNDERVOLTAGE HYSTERESIS R UV1 RUVHYS = --------------------------------------------------V UVD R UV1 ----------------- - ------------- - 1 V REFIN R UV2 EQUATION 6-3: UNDERVOLTAGE CONDITION V NEG RUV2 VREFIN ------------------------------------ R UV1 + R UV2 An internal 10 A current source and an external capacitor connected to the UVD pin adjusts the delay between the input fault and the notification of this fault to the system. This is usually 100 ms for -48V telecomtype equipment. For customized adjustments, the time delay can be expressed as Equation 6-1. EQUATION 6-1: T DELAY INPUT FAULT DELAY REFIN V ------------------ C UVD 2 = -------------------------------------------10A CUV is the capacitor connected between the UVD pin and the VNEG pin. A value of 1 F would provide a delay of about 100 ms. DS20091C-page 44 2002-2012 Microchip Technology Inc. MCP18480 6.8.2 OV (OVERVOLTAGE) BLOCK The overvoltage block behaves similarly to the undervoltage block in that it monitors an input voltage by comparing a centertap voltage on an external voltage divider (on the OVTH pin) to the VREFIN pin voltage. If the centertap voltage is below the reference, the input voltage is not excessive. If the centertap voltage is greater than the VNEG + VREFIN pin voltages, the supply voltage is higher than the programmed acceptable maximum voltage limit. An internal flag is then activated to inform the MCP18480 that the input voltage has exceeded the preset limit. The "Overvoltage Active" signal deasserts when the input voltage drops back below the threshold determined by the external resistors (ROV1 and ROV2). EQUATION 6-4: OVERVOLTAGE VOLTAGE CONDITION VNEG R OV2 VREFIN ------------------------------------ ROV1 + ROV2 2002-2012 Microchip Technology Inc. 6.8.3 FET-GOOD BLOCK The FET-good block monitors the voltage between the drain of the external MOSFET and on the VNEG pin at power-up. It delays assertion of PWRGOOD until the drain-to-source voltage of the external FET is acceptably low and the voltage at the GATE pin is about 8V. The comparator operation is similar to Undervoltage and Overvoltage blocks. To prevent applying excessive voltages to the gates of the FETs in the Undervoltage circuit, a resistive voltage divider is employed between ground and the VNEG pin. Similarly, the drain of the external MOSFET can be exposed to voltages at around VNEG during normal operation and as high as ground (typically 48V above VNEG). The FET good block also monitors the GATE pin. When the GATE pin becomes >VNEG +8V and the DRAINTH pin is within its programmed range, the output of the FET good block is active. The internal FET good signal goes high and remains active until a fault condition (Undervoltage, Overvoltage or Current Limit) is detected. Any of these conditions hold the PWRGOOD signal deasserted until the fault condition is removed and the external FET gate and drain voltages are acceptable. DS20091C-page 45 MCP18480 6.8.4 6.8.5 CURRENT LIMIT BLOCK An excessive current flowing through the external FET is sensed as a voltage across an external resistor connected between the FET's source and VNEG. The drain voltage is sensed with a resistor divider network, as shown in Figure 4-1 and Figure 4-2. The voltage tap is applied to a circuit whose output is 50 mV above VNEG when the drain of the external FET is at VNEG. The output is 12 mV when the VFB pin is VNEG +0.5VThis output voltage is the Current Limit Feedback (CLFB) signal to the gate driver block for use in the fold-back current-limiting. The CLFB voltage serves as the reference for a comparator whose other input monitors the voltage across the current limit sense resistor in series with the source of the external FET. When the SENSE pin exceeds the voltage on CLFB, a comparator output goes high to start the timer (see Section 6.8.5). The VDS dependent threshold for the current limit helps keep the FET within its safe operating area. Another comparator in the current-limiting block watches the SENSE pin for potentially catastrophic over-current conditions, which require immediate termination of conduction in the pass MOSFET. The output of this comparator trips a comparator used in the TIMER block to skip the first part of the timeout cycle and go straight to the "off" period. In some cases, the user may want to program the system to shut off immediately if there is a short-circuit condition that exceeds a desired level. To use this feature, connect a divider between the VREFIN pin and the VNEG pin, with its centertap at the CL input pin. The circuit breaker current that would trigger this mode is given by Equation 6-5. EQUATION 6-5: I CAT CIRCUIT BREAKER THRESHOLD TIMER BLOCK Since the external FET can survive brief over-current episodes, it is unnecessary to turn off the FET instantly when the current rises too high (see external FET data sheet). The timer circuit uses the output of the comparator in the current-limiting block to begin charging an external capacitor with 16 * IRISET (typically 160 A) when an over-current condition is detected. When the voltage on the capacitor ramps up to 1.25V, a comparator output goes high. This output goes to another block that tells the gate driver to turn the external FET off and deassert the PWRGOOD pin. The complementary output of the timer changes the state of a hysteresis circuit that drops the reference input of the comparator to VNEG + 100 mV ( 10 mV). When the FET is off, the current through it drops to zero, so that the voltage across the current sense resistor also goes to zero and the current limit signal to the timer block goes away. The timer capacitor starts to discharge at a rate set by the external resistor, RDISCH. Equation 6-7 shows the equations used to calculate the current at the TIMER pin. This current is used for other calculations. EQUATION 6-7: ITIMER = 16 I RISET Typical ITIMER = 10 I RISET Minimum ITIMER = 20 I RISET Maximum Legend: IRISET is the current through the external RISET resistor The delay between the inception of the over-current condition and the deactivation of the FET is given by Equation 6-8. V REFIN ------------------------------ R CL2 R CL1 + RCL2 = ------------------------------------------------------R SENSE EQUATION 6-8: If this function is not needed in a particular application, it can be disabled by connecting the CL pin to the VREFIN pin. Equation 6-6 shows the current of the CL pin during current-limiting. V SENSE I CL = -----------------R SENSE EQUATION 6-9: 12 mV VSENSE 50 mV VDS RFB2 = 0.76 0.05V - ------------------------------ + 0.012V R +R FB1 FB2 for VFB > 0.5V, VSENSE = 0.012V DS20091C-page 46 CTIMER T CLD1 = ------------------- 1.25 I TIMER The time required to reset the timer and reactivate the gate driver is given by Equation 6-9. > 0.5V 0V V SENSE OVER-CURRENT FAULT DELAY CL PIN CURRENT VFB EQUATION 6-6: TIMER PIN CURRENT CALCULATIONS OVER-CURRENT REACTIVATION DELAY T CLD2 = 9.2 C TIMER R DISCH As described above, the timer circuit operates as a free-running, multi-vibrator, if RESTART is low. 2002-2012 Microchip Technology Inc. MCP18480 6.8.6 LATCH BLOCK A current limit latch circuit determines whether, following the timeout period resulting from an over-current condition, the external FET should be latched-off until reactivated by an external signal, or be allowed to restart automatically following the timer cycle. If the RESTART input is low, the part will restart and the gate drive to the external MOSFET will be restored automatically. If the RESTART pin is high, a current limit event will turn the FET off after the programmed delay and maintain an off condition until the ENABLE pin or RESTART pin is pulled low momentarily. 6.8.7 GATE DRIVE BLOCK The GATE drive block sources a current equal to the voltage at CLFB divided by 1 k to the gate of the external MOSFET. So the current sourced from the GATE pin is determined by the VDS of the external FET. This current, and the external capacitors around the FET, control the slew rate of the drain of the external FET, limiting the current that would otherwise have to be diverted from other boards on the backplane. In the event of a problem (Overvoltage, Undervoltage or current limit), the gate of the external FET is pulled down with 60 mA. During normal operation, the GATE pin ramps up to about 12V, sending the external FET deeply into the triode region. If the drain current becomes excessive while the drain-to-source voltage is high, the inverting input of the op amp is driven to the CLFB voltage by the current-limiting block, causing a reduction in the drive to the external FET to reduce the current through it. This foldback current-limit remains active until the voltage on CTIMER reaches VREFIN/2, after which the GATE output pin is pulled to VNEG for the duration of the timeout period, or until ENABLE is cycled low momentarily. For applications in which it is undesirable to have the drain current track the VDS of the external pass FET in current limit, the user can tie the VFB pin to the VREF or VNEG pin. This will make the MCP18480 try to force the drain current to 12 mV/RSENSE or 50 mV/RSENSE, respectively, until the TIMER block times out. If foldback current-limiting is not desired at all, set the divider associated with the CL pin to detect the desired current in order to shut off the GATE immediately. 6.8.8 BIAS BLOCK The internal voltage generation or bias block generates the biasing currents for all internal blocks. It also provides a 2.5V reference voltage that is brought out to the VREFOUT pin. This output pin is usually fed back into the VREFIN pin. However, an externally-generated 2.5V reference voltage may be directly connected to the VREFIN pin, while leaving the VREFOUT pin unconnected. A VREFIN/2 voltage is generated within the bias block, which is used as reference in the other blocks. A internal shunt regulator limits the internal circuitry to 12V. An external current-limiting resistor in series with VPOS absorbs the excess voltage. The resulting regulated 12V source is used in the gate drive block and PWRGOOD output circuit. The 12V source is also stepped-down to generate a 5V regulated source. Most of the other circuitry and blocks operate with the internally-generated 5V. EQUATION 6-10: EXTERNAL RISET CURRENT I RISET Note: 6.8.9 REFIN V ----------------2 = -----------------------R ISET The direction of the current is dependant on where the external RISET resistor is connected (the ISET pin to either the VNEG pin or the VREFIN pin). POWER GOOD BLOCK The "power good" block monitors the state of the OV active, the UV active, the current limit circuitry, and output of the FET good block to generate the PWRGOOD output signal. A voltage on the GATE pin higher than about 8V is one condition for the PWRGOOD pin to be asserted. Any fault condition that causes the GATE pin voltage to be pulled to VNEG deasserts the PWRGOOD pin. On startup, a NMOS transistor with a resistor pulling its gate up holds the GATE pin down until the MCP18480 is properly biased. 2002-2012 Microchip Technology Inc. DS20091C-page 47 MCP18480 NOTES: DS20091C-page 48 2002-2012 Microchip Technology Inc. MCP18480 7.0 PACKAGING INFORMATION 7.1 Package Marking Information Example: 20-Lead SSOP MCP18480 I/SS XXXXXXXXXXX XXXXXXXXXXX 0348058 YYWWNNN Legend: Note: * XX...X YY WW NNN Customer specific information* Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. Standard marking consists of Microchip part number, year code, week code, and traceability code. 2002-2012 Microchip Technology Inc. DS20091C-page 49 MCP18480 20-Lead Plastic Shrink Small Outline (SS) - 209 mil, 5.30 mm (SSOP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 p D B 2 1 n c A2 A L A1 Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Foot Length Lead Thickness Foot Angle Lead Width Mold Draft Angle Top Mold Draft Angle Bottom A A2 A1 E E1 D L c B MIN .068 .064 .002 .299 .201 .278 .022 .004 0 .010 0 0 INCHES* NOM 20 .026 .073 .068 .006 .309 .207 .284 .030 .007 4 .013 5 5 MAX .078 .072 .010 .322 .212 .289 .037 .010 8 .015 10 10 MILLIMETERS NOM 20 0.65 1.73 1.85 1.63 1.73 0.05 0.15 7.59 7.85 5.11 5.25 7.06 7.20 0.56 0.75 0.10 0.18 0.00 101.60 0.25 0.32 0 5 0 5 MIN MAX 1.98 1.83 0.25 8.18 5.38 7.34 0.94 0.25 203.20 0.38 10 10 * Controlling Parameter Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MO-150 Drawing No. C04-072 DS20091C-page 50 2002-2012 Microchip Technology Inc. MCP18480 APPENDIX A: REVISION HISTORY Revision A This is a new data sheet Revision B * Add device characterization information * Enhanced functional description Revision C * Added note to the package outline drawing. 2002-2012 Microchip Technology Inc. DS20091C-page 51 MCP18480 NOTES: DS20091C-page 52 2002-2012 Microchip Technology Inc. MCP18480 APPENDIX B: MCP18480 SCHEMATICS This appendix contains the schematics for the MCP18480 Evaluation Board. 2002-2012 Microchip Technology Inc. DS20091C-page 53 VIN+ VOUT+ RBYPL 51 k RZ ROV1 RPOS 4 k 1.74 M CBYP1 + 2 F 78V Transorb 24.9 k RUV1 453 k CBYP2 10 nF ROV2 59 k RUVHYS RUV2 280 k 30.9 k CUVD 800 nF RISET 124 k Fuse 10A VNEG SRS MCP18480 1 2 3 4 5 6 7 8 9 10 VPOS OVTH UVTH UVHYS UVD VREFOUT VREFIN CL ISET TIMER CTIMER 680 nF RESTART ENABLE PWRGOOD OVO DRAINTH VFB GATE SENSE RDISCH VNEG 20 19 18 17 16 15 14 13 12 11 SEN RPG1 110 k R 5V PG3 QPG2 680 RPG4 2N5400 36 k Q RPG5 PG1 MPSA43 36 k RPG6 1500 RDISCH 1.6 M RPG2 7.5 k RSENSE 0.01 CBYPL 100 F 100 V DC/DC Converter Module ON/OFF VIN- VOUT- QPG3 NTE261 RGD 18 k CG1 RG1 100 nF 10 CGD 3.3 nF M1 NTE2388 2002-2012 Microchip Technology Inc. FIGURE B-1: RFB2 124 k RFB1 1.74 M RDRAIN2 115 k RDRAIN1 1.6 M ROVO2 59 k ROVO1 1.74 M Typical Operating Circuit for Telcom Applications with Active-High Power Module - Foldback Current Limit Enabled. MCP18480 DS20091C-page 54 GND 2002-2012 Microchip Technology Inc. GND VIN+ VOUT+ RBYPL 51 k RZ ROV1 RPOS 4 k 1.74 M CBYP1 + 2 F 78V Transorb CBYP2 10 nF ROV2 59 k RUVHYS RUV2 280 k 30.9 k CUVD 800 nF RISET 124 k Fuse 10A VNEGA 1 24.9 k RUV1 453 k SRS MCP18480 1 2 3 4 5 6 7 8 9 10 VPOS OVTH UVTH UVHYS UVD VREFOUT VREFIN CL ISET TIMER CTIMER 680 nF RESTART ENABLE PWRGOOD OVO DRAINTH VFB GATE SENSE RDISCH VNEG 20 19 18 17 16 15 14 13 12 11 SEN RPG1 110 k R 5V PG3 QPG2 680 RPG4 2N5400 36 k Q RPG5 PG1 MPSA43 36 k RPG6 1500 RDISCH 1.6 M RPG2 7.5 k RSENSE 0.01 CBYPL 100 F 100 V DC/DC Converter Module ON/OFF VIN- VOUT- QPG3 NTE261 RGD 18 k CG1 RG1 100 nF 10 CGD 3.3 nF M1 NTE2388 RFB1 1.74 M RDRAIN2 115 k RDRAIN1 1.6 M ROVO2 59 k ROVO1 1.74 M Typical Operating Circuit for Telcom Applications with Active-Low Power Module - Foldback Current Limit Enabled. MCP18480 DS20091C-page 55 FIGURE B-2: RFB2 124 k RPOS 4 k ROV1 1.74 M CBYP1 + 2 F CBYP2 10 nF ROV2 59 k RUV1 453 k RUV2 30.9 k CUVD 800 nF SRS MCP18480 RUVHYS 280 k 1 2 3 4 5 6 7 8 9 10 VPOS OVTH UVTH UVHYS UVD VREFOUT VREFIN CL ISET TIMER RISET 124 k C TIMER 680 nF RESTART ENABLE PWRGOOD OVO DRAINTH VFB GATE SENS RDISCH VNEG 20 19 18 17 16 15 14 13 12 11 5V SEN RPG1 110 k RPG3 680 RPG4 36 k Q PG1 MPSA43 RPG2 7.5 k RSENSE 0.01 VNEG 2002-2012 Microchip Technology Inc. FIGURE B-3: QPG2 2N5400 RPG5 36 k RPG6 1500 RDISCH 1.6 M CBYPL RLOAD 100 F 75 QPG3 NTE261 RGD 18 k CG1 RG1 100 nF 10 CGD 3.3 nF M1 NTE2388 Evaluation Board Schematic (Active-Low Power Module - Foldback Current Limit Enabled). RFB2 124 k RFB1 1.74 M RDRAIN2 115 k RDRAIN1 1.6 M ROVO2 59 k ROVO1 1.74 M MCP18480 DS20091C-page 56 RBYPL 51 k RZ 24.9 k 2002-2012 Microchip Technology Inc. RBYPL 51 k RZ 24.9 k RPOS 4 k ROV1 1.74 M CBYP1 + 2 F CBYP2 10 nF ROV2 59 k RUV1 453 k RUV2 30.9 k SRS MCP18480 RUVHYS 280 k CUVD 800 nF RISET 124 k 1 2 3 4 5 6 7 8 9 10 VPOS OVTH UVTH UVHYS UVD VREFOUT VREFIN CL ISET TIMER CTIMER 680 nF RESTART ENABLE PWRGOOD OVO DRAINTH VFB GATE SENS RDISCH VNEG 20 19 18 17 16 15 14 13 12 11 5V SEN RPG1 110 k RPG3 680 RPG4 36 k Q PG1 MPSA43 RPG2 7.5 k RSENSE 0.01 VNEG RPG5 36 k QPG3 NTE261 RGD 18 k CG1 RG1 100 nF 10 CGD 3.3 nF M1 NTE2388 Evaluation Board Schematic (Active-High Power Module - Foldback Current Limit Enabled). RFB2 124 k RFB1 1.74 M RDRAIN2 115 k RDRAIN1 1.6 M ROVO2 59 k ROVO1 1.74 M MCP18480 DS20091C-page 57 FIGURE B-4: QPG2 2N5400 RPG6 1500 RDISCH 1.6 M CBYPL RLOAD 100 F 75 RPOS 4 k ROV1 1.74 M CBYP1 + 2 F CBYP2 10 nF ROV2 59 k RUV1 453 k RUVHYS RUV2 30.9 k 280 k CUVD 800 nF RCL1 (Note) 210 k RCL2 (Note) 40.2 k VNEG 2002-2012 Microchip Technology Inc. FIGURE B-5: SRS MCP18480 1 2 3 4 5 6 7 8 9 10 VPOS OVTH UVTH UVHYS UVD VREFOUT VREFIN CL ISET TIMER RISET 124 k C TIMER 680 nF RESTART ENABLE PWRGOOD OVO DRAINTH VFB GATE SENS RDISCH VNEG 20 19 18 17 16 15 14 13 12 11 5V SEN RPG1 110 k RPG3 680 RPG4 36 k Q PG1 MPSA43 QPG2 2N5400 RPG5 36 k RPG6 1500 RDISCH 1.6 M RPG2 7.5 k RSENSE 0.01 CBYPL RLOAD 100 F 75 QPG3 NTE261 RGD 18 k CG1 RG1 100 nF 10 CGD 3.3 nF M1 NTE2388 Evaluation Board Schematic (Active-Low Power Module - Circuit Breaker Current Limit Enabled). RDRAIN2 115 k RDRAIN1 1.6 M ROVO2 59 k ROVO1 1.74 M MCP18480 DS20091C-page 58 RBYPL 51 k RZ 24.9 k 2002-2012 Microchip Technology Inc. RBYPL 51 k RZ 24.9 k RPOS 4 k ROV1 1.74 M CBYP1 + 2 F CBYP2 10 nF ROV2 59 k RUV1 453 k RUVHYS RUV2 30.9 k 280 k CUVD 800 nF RCL1 (Note) 210 k RCL2 (Note) RISET 40.2 k 124 k VNEG 1 2 3 4 5 6 7 8 9 10 VPOS OVTH UVTH UVHYS UVD VREFOUT VREFIN CL ISET TIMER CTIMER 680 nF RESTART ENABLE PWRGOOD OVO DRAINTH VFB GATE SENS RDISCH VNEG 20 19 18 17 16 15 14 13 12 11 5V SEN RPG1 110 k RPG3 680 RPG4 36 k Q PG1 MPSA43 QPG2 2N5400 RPG5 36 k RPG6 1500 RDISCH 1.6 M RPG2 7.5 k RSENSE 0.01 QPG3 NTE261 RGD 18 k CG1 RG1 100 nF 10 CGD 3.3 nF M1 NTE2388 Evaluation Board Schematic (Active-High Power Module - Circuit Breaker Current Limit Enabled). RDRAIN2 115 k RDRAIN1 1.6 M ROVO2 59 k ROVO1 1.74 M MCP18480 DS20091C-page 59 FIGURE B-6: SRS MCP18480 CBYPL RLOAD 100 F 75 MCP18480 NOTES: DS20091C-page 60 2002-2012 Microchip Technology Inc. MCP18480 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X /XX Temperature Range Package Device MCP18480: MCP18480T: Temperature Range I Package SS = Plastic SSOP (209 mil, Body), 20-lead Examples: a) MCP18480-I/SS = Industrial Temp., SSOP package b) MCP18480T-I/SS = Tape and Reel, Industrial Temp., SSOP package -48V Hot Swap Controller -48V Hot Swap Controller (Tape and Reel) = -40C to +85C Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. 3. Your local Microchip sales office The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products. 2002-2012 Microchip Technology Inc. DS20091C-page 61 MCP18480 NOTES: DS20091C-page 62 2002-2012 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: * Microchip products meet the specification contained in their particular Microchip Data Sheet. * Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. * There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. * Microchip is willing to work with the customer who is concerned about the integrity of their code. * Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MTP, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. Analog-for-the-Digital Age, Application Maestro, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O, Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA and Z-Scale are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. GestIC and ULPP are registered trademarks of Microchip Technology Germany II GmbH & Co. & KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. (c) 2002-2012, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 9781620767283 QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 == 2002-2012 Microchip Technology Inc. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 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