2002-2012 Microchip Technology Inc. DS20091C-page 1
MCP18480
Features
• Allows safe board removal and insertion from a
live backplane
• Accura te (< 1.5%) internal voltage r eference for
fault detection and precision timing
• Programmable foldback current limiting
• Programmable circuit breaker current limiting
• Auto restart option for all faults
• Adjustable Undervoltage lockout thresholds
• Adjustable Overvoltage protection threshold
• Adjustable Power Go od del ay
• Configurable Power Good output polarity
• Low-side drive of an external N-channel FET
CMOS Technology
• High-Volta ge Op era tion
• Temperature range: Industrial (I): -40°C to +85°C
Packaging
• 20-lead SSOP
Package Type
Description
The MCP18480 is a Hot Swap controller that allows
boards to be saf ely re moved o r in se rted fro m an ac tiv e
backplane using -48V.
When PCBs are inserted into a live backplane, high-
peak or transient currents from the source are gener-
ated due to the charging of the bypass capacitors on
the supply. The high transient currents can destroy
connec tors and cap acitors. The hig h inrush curren t can
pull the input voltage BUS down and reset the system.
The MCP18480 solves this problem by controlling the
slew rate of the backplane voltage to the board so that
these transients are eliminated. This allows boards to
be removed and inserted without causing damage to
connector pins and input bulk capacitors, in addition to
preventing false resets to the other boards on the
backplane.
The MCP18480 can be used in applications in several
areas including:
• Telecom Line Cards
• Network Sw itches
• Network R oute rs and Servers
• Base Station Line Cards
• Power-Over-LAN
• Power-Over-MDI
• IP Phone Switch es/R out ers
• Mid-Span, Power-Ov er-MDI
Two forms of current limit are provided in the
MCP18480. These are:
• Foldback
• Circuit breaker
The foldback current-limiting circuit uses an external
sense resistor and a voltage that is proportional to the
external MOSFET’s drain voltage. These are used to
keep the MOSFET in its Safe Operating Area (SOA).
If the device remains in current limit for a programmed
time period, the external N-channel FET is turned off.
The option exists to configure the device to automati-
cally restart af ter a program med time del ay . A pro gram-
mable catastrophic current limit threshold shuts down
the switch (circuit breaker) if excessive current is
sensed due to a short-circuit condition.
2
3
4
5
6
7
8
9
10
1
19
18
16
15
14
13
12
11
17
20
ENABLE
RESTART
UVD
VREFIN
OVO
VFB
PWRGOOD
DRAINTH
SENSE
GATE
CL
ISET
TIMER
RDISCH
VNEG
OVTH
UVTH
UVHYS
VREFOUT
VPOS
MCP18480
SSOP
-48V Hot Swap Controller
MCP18480
DS20091C-page 2 2002-2012 Microchip Technology Inc.
Internal comparators are incorporated to add hystere-
sis for adjusting the Undervoltage Lockout (UVLO)
threshold. The external N-channel MOSFET is turned
on when the input is below the user-programmable,
Overvoltage threshold and above the user-
program mable, Undervoltage thres hold.
The PWRGOOD pin indicates the status of the
MCP18480 and is active when the device has com-
pleted po wer-up and the s ystem is not in an Undervolt-
age, Overvoltage or current-limit condition.
PWRGOOD can be externally configured to either
active-high or active-low to accommodate external cir-
cuitry (power supplies) that have either enabling logic.
A block diagram of the MCP18480 is shown below.
MCP18480 Block Diagram
VPOS
UVTH
UVD
OVTH
VNEG
GATE
VFB
MCP18480
UVHYS
VREFOUT
VREFIN
SENSE TIMER
RDISCH
LATCHOFF
ISET
PWRGOOD
(1)
DRAINTH
12V
Regulator
12VOUT
5V
Reg. 5VOUT
5VOUT
Latch
Undervoltage Active
Overvoltage Active
Current Limit Timer
ENABLE
RESTART
CL
VPOS
OVO
PWRGOOD
Output Block
VNEG
BIAS
Undervoltage
Overvoltage
Current Limit
GATE
Drive
Timer
FET G o o d
Circuit Breaker
TIMEOUT
Current Limit Feedback
SENSE
Internal
Bias
Generation
Note 1: The PWRGOOD output pin can be either active-high or active-low. This polarity is determined by the
voltage (either the level on the VREFIN pin or level on the VNEG pin) on the ISET pin:
-Connecting the external RISET resistor to VREFIN configures the PWRGOOD pin as active-low
-Connecting the external RISET resistor to VNEG configures the PWRGOOD pin as active-high
(Section 6.8.3)
(Section 6.8.8)
(Section 6.8.2)
(Section 6.8.1)
(Section 6.8.4)
(Section 6.8.9)
(Section 6.8.5)
(Section
6.8.6)
(Section 6.8.7)
2002-2012 Microchip Technology Inc. DS20091C-page 3
MCP18480
1.0 ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings†
Ambient Temperature under bias........–40°C to +85°C
Storage Temperature ........................–65°C to +150°C
Voltage on VPOS with respect to VNEG -0.3V to +15.0V
Voltage on DVTH, UVTH, VFB, OVO and UVHYS pins
with respect to VNEG .....VNEG – 0.3V to (VPOS + 0.3V)
Voltage on VREFIN, CL, SENSE, DRAINTH, ENABLE
and RESTART pins with respect to VNEG
........................................................VNEG - 0.3V to 6V.
Total Power Dissipation (Note 1) ....................800 mW
Max. Current out of VNEG pin.............................80 mA
Max. Current into VPOS pin................................50 mA
Max. Output Current sunk by Gate pin...............80 mA
Max. Output Current sunk by VREFOUT pin..........5 mA
Max. Output Current sunk by any other
Output pin.........................................................25 mA
Max. Output Current sourced by Gate pin........200 µA
Max. Output Current sourced by VREFOUT pin.....5 mA
Max. Output Current sourced by any other
Output pin...........................................................25 mA
Junction to Ambient, JA
(20 pin SSOP Package) Derating ...............108.1C/W
Junction to Case, JC
(20 pin SSOP Package) Derating .................32.2C/W
Lead Temperature, Soldering, 10 seconds ........300C
† Notice: Stresses above those listed under "Maximum
Ratings" may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
operation listings of this specification is not implied. Exposure
to maximum rating conditions for extended periods may affect
device reliability.
Note 1: Power Dissipation is ca lculated as follows:
PDIS = VDD x {I DD - IOH} + {(VDD-VOH) x IOH} + (VOL x IOL)
DC CHARACTERISTICS
Electrical Specifications: Unless otherwise specified, operating temperature: –40C TA +85C (Industrial),
Supply Current: 5 mA IPOS 25 mA, RISET = 125 k, CBYP = 2 µF.
Param.
No. Parameter Sym Min Typ (1) Max Units Conditions
MD001 Current into shunt regulator
that produces VPOS output volt-
age that meets MD001A speci-
fication
IPOS1 5 — 25 mA ENABLE pin = 5V
5 — 25 ENABLE pin = VNEG
MD001A Regulated Output Voltage
Differential of VPOS to VNEG
VPOS 10.4 12.0 13.4 V See MD001
MD002 VREFOUT pin output voltage VREFOUT 2.463 2.5 2.538 V Load = 50 µA
MD010 VGATE pin output voltage VGATE VPOS - 2 VPOS -1 VPOS V
MD011 Voltage on ISET pin VISET (VREFIN/2) -
0.02 VREFIN/2 (VREFIN/2)
+0.02 V
MD012A Voltage on SENSE pin to
trigger current-limiting VSENSE 40 50 60 mV VFB = VNEG
MD012B 25 31.0 40 mV VFB = VNEG + 0.25V
MD012C 7 12 17 mV VFB = VNEG + 0.5V
MD013 Undervoltage Threshold UVTH VREFIN
- 0.03 VREFIN VREFIN
+ 0.03 V
MD014A Overvoltage
Threshold rising OVTH VREFIN
- 0.05 VREFIN VREFIN
+ 0.05 VV
REFIN = 2.5V
MD014B falling OVTH VREFIN
- 0.035 VREFIN
- 0.02 VREFIN
- 0.005 VV
REFIN = 2.5V
MD015 DRAIN Pin Input Threshold
Voltage VDTH 90 100 130 mV
Note 1: Data in the Typical (“Typ”) column is based on characterization results at +25C. This dat a is for design guidance only
and is not tested.
2: Negative current is defined as current sourced by the pin.
3: All voltages are with respect to the VNEG pin voltage.
MCP18480
DS20091C-page 4 2002-2012 Microchip Technology Inc.
DC Characteristics (Continued)
Electrical Specification: Unless otherwise specified, operating temperature: –40C TA +85C (Industrial),
Supply Current: 5 mA IPOS 25 mA, RISET = 125 kCBYP = 2 µF
Param.
No. Parameter Sym Min Typ (1) Max Units Conditions
MD020 DRAIN pin current IDRAIN — — 0.1 µA DRAINTH pin = VNEG
MD021 SENSE pin current ISENSE ——0.1µA
MD022 GATE pin current Pull-up IGATE SENSE pin = VNEG
GAT E pin = VNEG +4V
MD022A -30 -50 -75 µA VFB = VNEG
MD022B -9 -17 -33 µA VFB = VNEG + 500 mV
MD022C Pull-down IGATE 31 49 72 mA Any fault condition
MD023 UVD pin current IUVD -7 -10 -15 µA UVTH < V REFIN
MD024A TIMER pin current Pull-up ITIMER -100 -160 -200 µA RISET = 125 k,
VREFIN = 2.5V
MD024B Pull-down 52 78 104 nA RISET = 125 k,
VREFIN = 2.5V
RDISCH = 1.6 M
MD025 ISET pin current IISET VISET(MIN) —V
ISET(MAX) ASee MD011
RISET(MAX) RISET(MIN)
Note 1: Data in the Typical (“Ty p”) colum n is based on characterization results at +25C. This data is for design guidance only
and is not tested.
2: Negative current is defined as current sourced by the pin.
3: All voltages are with respect to the VNEG pin voltage.
2002-2012 Microchip Technology Inc. DS20091C-page 5
MCP18480
DC Characteristics (Continued)
Electrical Specifications: Unless otherwise specified, operating temperature: –40C TA +85C (Industrial),
Supply Current: 5 mA IPOS 25 mA, RISET = 125 k, CBYP = 2 µF.
Param # Parameter Sym Min Typ Max Units Conditions
MD030 Input Low Voltage VIL
MD031 ENABLE pin VNEG —0.8V
MD032 RESTART pin VNEG —0.8
MD040 Input High Voltage VIH
MD041 ENABLE pin 2.0 — 5.0 V
MD042 RESTART pin 2.0 — 5.0 V
MD050 Internal Resistance on UVHYS pin RUVHYS 500 1200 2100 VUVTH < VREFIN,
IUVHYS = 30 µA
50 100 — M V
UVTH > VREFIN,
IUVHYS = 30 µA
Input Leakage Current
(Notes 2, 3)
MD060A OVTH, UVTH, VFB, OVO and UVHYS
pins IIL -1 — +1 µA VNEG VPIN 11V, Pin
at high-impedance
MD060B VREFIN, CL, SENSE, DRAINTH,
ENABLE and RESTART pins ——±1µAV
NEG VPIN 5V,
Pin at hi-impedance
MD070 Minimum current into ENABLE pin
to disable MCP18480 IEN —1030µAI
POS = 5 mA,
ENABLE = 0.8V
Output Low V oltage VOL
MD080 PWRGOOD pin 0 — 0.4 V IOL = 5 mA
Output High Voltage VOH —
MD090 PWRGOOD pin 0.8 VPOS 0.96 VPOS VPOS VI
OH = 2 m A,
7mA IPOS 12 mA
MD100 Offset Voltage at the internal
comparator input that is connected
to the CL pin.
VCL -15 — +15 mV VFB = 0
Note 1: All voltages are with respect to the VNEG pin voltage.
2: The leakage currents on the ENABLE and REST AR T pins are strongly dependent on the applied voltage level. The spec-
ified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as coming out of the pin.
MCP18480
DS20091C-page 6 2002-2012 Microchip Technology Inc.
1.1 Timing Parameter Symbology and Load Conditions
The timing parameter symbols have been created using one of the following formats:
1.1.1 TIMING CONDITIONS
The temperature and voltages specified in Table 1-2 apply to all timing specifications, unless otherwise noted.
Figure 1-1 specifies the load conditions for the timing specifications.
TABLE 1- 1: SYMBOLOGY
TABLE 1-2: AC TEMPERATURE AND VOLTAGE SPECIFICATIONS
1. TppS2ppS 2. TppS
TF Frequency T Time
E Error
Lowercas e lette rs (pp) ind ic ate the dev ic e pin.
Uppercase letters and their meanings:
SFFall P Period
FR Fast Ramp R Rise
HHigh V Valid
I Invalid (Hi-impedance) Z Hi-impedance
LLow
AC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)
Operating temperature: –40C TA +85C (industrial)
Operating voltage VDD range as described in DC spec Section 1.0.
2002-2012 Microchip Technology Inc. DS20091C-page 7
MCP18480
FIGURE 1-1: Load Conditions for Device Timing Specifications.
+
RUV1
ROV2 RUV2
CUVD
RISET
Ctimer
RDISCH
RUVHYS
RPOS
CBYP2
RSENSE
ROVO1
ROVO2
RDRAIN1
RDRAIN2
RFB1
RFB2
CGD
RGD
RG1
CG1
QPG2
QPG3
RPG2
RPG6
M1
CBYPL
RBYPL
VNEG
RPG1 RPG5
4k
2µF 10nF
1.74 M453 k
280 k
59 k30.9 k
800 nF
124 k
680 nF
1.6 M
0.01
7.5 k
110 kMPSA43
100 nF 103.3 nF
18 k
680
36 k
36 k
1500
100 µF
51 k
2N5400
NTE261
124 k
115 k
59 k
1.74 M
1.6 M
1.74 M
NTE2388
RZ
24.9 k
5V RPG3
RPG4
QPG1
RESTART
ENABLE
PWRGOOD
VPOS
OVTH
UVTH
UVHYS
UVD
VREFIN
VREFOUT
CL
ISET
TIMER
OVO
DRAINTH
VFB
GATE
SENSE
VNEG
RDISCH
1
2
3
4
5
6
7
8
9
10 11
12
13
14
15
16
17
18
19
20
DC/DC
Converter
Module
VIN+
VIN-
VOUT+
VOUT-
ON/OFF
100 V
78V
Fuse 10A
GND
Transorb
CBYP1
ROV1
GOODPWR
MCP18480
SRS
SEN
MCP18480
DS20091C-page 8 2002-2012 Microchip Technology Inc.
1.2 Timing Diagrams and Specifications
FIGURE 1-2: Startup Waveforms.
TABLE 1-3: STARTUP TIMING REQUIREMENTS
Param.
No. Parameter Sym Min Typ Max Units Conditions
MA000 UVTH/OVTH High (VPOS applied) to
DRAINTH fall ing TUVOVH2DTHF—20.2—ms
MA001A DRAINTH falling to PWRGOOD High TDTHF2GATEPGH — 19.3 — ms
MA001B DRAINTH falling to GATE Fast Ramp TDTHF2GATEFR — 13.1 — ms
MA002 GATE Fast Ramp to external FET
fully enhanc ed TGATEFR2FETE—16.1— ms
Note: Minimum and maximum specifications will be provided in future revisions of this data sheet.
PWRGOOD
UVTH
OVTH
VREFOUT
< 2.5V
= 2.5V
> 2.5V
DRAINTH
MA000
MA001A
GATE = 5V (1)
= 12V
MA002
Note 1: This voltage is determined by the threshold voltage of the external FET.
This voltage needs to ensure the external FET is fully enhanced.
MA001B
2002-2012 Microchip Technology Inc. DS20091C-page 9
MCP18480
FIGURE 1-3: ENABLE-to-GATE Waveforms.
TABLE 1-4: ENABLE-TO-GATE TIMING REQUIREMENTS
Param.
No. Parameter Sym Min Typ Max Units Conditions
MA010 ENABLE Low to GATE Low TENL2GATEL—23.6—µs
MA011 ENABLE High to GA TE Fas t Ramp TENH2GATEFR — 41 — ms
MA012 GATE Fast Ramp to GATE High TGATEFR2GATEH—17.8— ms
Note: Minimum and maximum specifications will be provided in future revisions of this data sheet.
ENABLE
MA012
GATE (1)
MA010
MA011
Note 1: This voltage is determined by the threshold voltage of the external FET.
This voltage needs to ensure the external FET is fully enhanced.
MCP18480
DS20091C-page 10 2002-2012 Microchip Technology Inc.
FIGURE 1-4: OVTH-to-gate Waveform.
TABLE 1-5: OVTH-TO-GATE TIMING REQUIREMENTS
Param.
No. Parameter Sym Min Typ Max Units Conditions
MA020 OVTH High to GATE Low TOVH2GATEL—58.4—µs
MA021 OVTH Low to GATE Fast Ramp TOVL2GATEFR — 40.8 — µs
MA022 GATE Fast Ramp to GATE High TGATEFR2GATEH—17.8— ms
Note: Minimum and maximum specifications will be provided in future revisions of this data sheet.
OVTH
MA022
GATE(1)
MA020 MA021
VREFIN + VOVO - 20 mV
VREFIN + VOVO
Note 1: This voltage is determined by the threshold voltage of the external FET.
This voltage needs to ensure the external FET is fully enhanced.
2002-2012 Microchip Technology Inc. DS20091C-page 11
MCP18480
FIGURE 1-5: UVTH-to-gate Waveform
TABLE 1-6: UVTH-TO-GATE TIMING REQUIREMENTS
Param.
No. Parameter Sym Min Typ(1) Max Units Conditions
MA030 UVTH Low to GATE Falling Edge TUVL2GATEF—108—µsC
UVD = 800 nF
MA031 GATE High to GATE Low TGATEH2GATEL— 25.8 — µs
MA032 ENABLE High to GATE Fast Ramp TUVH2GATEFR — 40.4 — ms
MA033 GATE Fast Ramp to GATE High TGATEFR2GATEH— 58.4 — ms
Note 1: Data in the Typical (“Typ”) column is at 5V, 25C, unless otherwise stated.
2: Minimum and maximum specifications will be provided in future revisions of this data sheet.
UVTH
MA033
GATE(1) MA030
MA032
VREFIN - 262 mV VREFIN
MA031
Note 1: This voltage is determined by the threshold voltage of the ex ternal FET.
This voltage needs to ensure the external FET is fully enhanced.
MCP18480
DS20091C-page 12 2002-2012 Microchip Technology Inc.
FIGURE 1-6: Sense-to-gate Waveform.
TABLE 1-7: SENSE-TO-GATE TIMING REQUIREMENTS
Param.
No. Parameter Sym Min Typ Max Units Conditions
MA041 GATE Current Limit to GATE Off TGATECL2GATEO—5.5— msC
TIMER = 0.68 µF
RISET = 124 k
MA042 GATE Current Limit Recovery TGATECL — 10.2 — ms CTIMER = 0.68 µF
RISET = 124 k
MA043 SENSE High to GATE Off TSENSEH2GATEO—3.6— ms
Note: Minimum and maximum specifications will be provided in future revisions of this data sheet.
GATE
SENSE
MA041
Foldback Current-Limiting
Recovery from Foldback Current-Limiting
GATE
SENSE
MA042
Circuit Breaker Current-Limiting
GATE
SENSE
MA043
2002-2012 Microchip Technology Inc. DS20091C-page 13
MCP18480
FIGURE 1-7: Current Limit Waveform.
TABLE 1-8: CURRENT LIMIT TIMING REQUIREMENTS
Param.
No. Parameter Sym Min Typ Max Units Conditions
MA050 External Short to Timer period start TSHORT2TIMERS—171—mS
MA051 Timer period TTIMERP—5.8—secC
TIMER = 0.68 µF
RDISCH = 1.6 M
MA053 ENABLE High to Timer period st art TENABLEH2TIMERS—30.5—mSC
TIMER = 0.68 µF
RDISCH = 1.6 M
MA054 RESTART Low to Timer period
start TRESTARTL2TIMERS—30.9—mSC
TIMER = 0.68 µF
RDISCH = 11.6 M
MA055 External Short remov ed to T i me r off
Note 2 TNOSHORT2TIMERO—5.8—secC
TIMER = 0.68 µF
RDISCH = 1.6 M
Note 1: Minimum and maximum specifications will be provided in future revisions of this data sheet.
2: This is up to one additional timer period because the external short circuit is removed asynchronously to
the timer. The timer must time out before normal operation returns.
Timer
GATE
SENSE
MA051
ENABLE
RESTART
MA053 MA055
External Short Condition On-Board
MA054
MA050
MCP18480
DS20091C-page 14 2002-2012 Microchip Technology Inc.
NOTES:
2002-2012 Microchip Technology Inc. DS20091C-page 15
MCP18480
2.0 DC CHARACTERISTIC CURVES
FIGURE 2-1: Supply Current (IPOS) vs.
Supply Voltage (VPOS). FIGURE 2-2: Minimum Supply Current vs.
Temperature.
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Dat a t aken with the min im um fol lowi ng c onditions:
VREFIN = 2.5V, ISET = 10 µA
10.900
11.400
11.900
12.400
3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0
Supply Current, IPOS (mA )
Supply Voltage, VPOS (V)
TA = -40°C
TA = +25°C TA = +85°C
TA = -5°C
TA = +70°C
Dat a t aken with the min im um fol lowing conditions:
Minimum Supply Current to bring VPOS into
regulation
VREFIN = 2.5V, ISET = 10 µA
11.65
11.70
11.75
11.80
11.85
11.90
-45
-35
-25
-15
-5
5
15
25
35
45
55
65
75
85
95
105
115
125
Temperature (°C)
Supply Voltage, VPOS (V)
IPOS = 5 mA
MCP18480
DS20091C-page 16 2002-2012 Microchip Technology Inc.
FIGURE 2-3: GATE Ou tput High-Voltage
(VPOS- VGATE) vs. Supply Current (IPOS). FIGURE 2-4: GATE Output Low-Voltage
(VGATE - VNEG) vs. Supply Current (IPOS).
Dat a t aken with the min im um fol lowi ng c onditions:
3mA IPOS 30 mA
VREFIN = 2.5V, ISET = 10 µA
Note 1:
VUVTH > VVREFIN
VOVTH < VVREFIN
VSENSE = VVNEG
VVFB = VVNEG
VDRAINTH = VVNEG
VOVO = VVNEG
VCL = VVREFIN
VENABLE = 5V (open)
VRESTART = VVNEG (open)
0.15
0.20
0.25
0.30
0.35
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Supply Current (mA)
Gate Voltage (V)
TA = -40°C
TA = 0°C
TA = + 85°C
TA = +70°C
TA = +25°C
Dat a t aken with the min im um fol lowing conditions:
3mA IPOS 30 mA
VREFIN = 2.5V, ISET = 10 µA
Note 1:
VUVTH > VVREFIN
VOVTH < VVREFIN
VSENSE = VVNEG
VVFB = VVNEG
VDRAINTH = VVNEG
VOVO = VVNEG
VCL = VVREFIN
VENABLE = VVNEG
VRESTART = VVNEG (open)
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
11.0
12.0
3 5 7 9 1113151719212325
Supply Current (mA)
Gate Output Vol (mV)
TA = -40°C
TA = 0°C
TA = +85°C
TA = +25°C
2002-2012 Microchip Technology Inc. DS20091C-page 17
MCP18480
FIGURE 2-5: GATE Source (Pull-Up)
Current vs. Tempe ratur e. FIGURE 2-6: GATE Sink (Pull-Down)
Current vs. Temperature.
Dat a t aken with the min im um fol lowi ng c onditions:
IPOS = 5 mA
(Enables VPOS at its se lf-re gulating voltag e)
VREFIN = 2.5V, ISET = 10 µA
Note 1:
VUVTH > VVREFIN
VOVTH < VVREFIN
VSENSE = VVNEG
VVFB = VVNEG
VDRAINTH = VVNEG
VOVO = VVNEG
VCL = VVREFIN
VENABLE = 5V (open)
35
40
45
50
55
-40-200 20406080
Tem perature (°C)
Gate Pull-up Current (µA)
Dat a t aken with the min im um fol lowing conditions:
IPOS = 5 mA
(Enables VPOS at its self-re gulating volt age)
VREFIN = 2.5V, ISET = 10 µA
Note 1:
VGATE > 0.5V
VUVTH > VVREFIN
VOVTH < VVREFIN
VSENSE = VVNEG
VVFB = VVNEG
VDRAINTH = VVNEG
VOVO = VVNEG
VCL = VVREFIN
VENABLE = VVNEG
VRESTART = VVNEG (open)
40
45
50
55
60
-40-200 20406080
Temperature (°C)
Gate Current (mA)
MCP18480
DS20091C-page 18 2002-2012 Microchip Technology Inc.
FIGURE 2-7: GAT E Sou rce Cur r ent vs.
ISET Pin Current. FIGURE 2-8: PWRGOOD Output Low
Voltage (VOL) vs. Temperature.
Dat a t aken with the min im um fol lowi ng c onditions:
-50 µA µA < IISET < 50 µA (IISET 0)
IPOS = 5 mA
(Enables VPOS at its se lf-re gulating voltag e)
VREFIN = 2.5V
Note 1:
VGATE > 0.5V
VUVTH > VVREFIN
VOVTH < VVREFIN
VSENSE = VVNEG
VVFB = VVNEG
VDRAINTH = VVNEG
VOVO = VVNEG
VCL = VVREFIN
VENABLE = 5V (open)
VRESTART = VVNEG (open)
-105
-95
-85
-75
-65
-55
-45
-35
-25
-15
-5
-30-25-20-15-10-5 0 5 1015202530
ISET Current (uA)
Gate Current (uA)
TA = + 25°C
TA = +85°C
TA = -40°C
Dat a t aken with the min im um fol lowing conditions:
ILOAD = 1 mA
IPOS = 5 mA
(Enables VPOS at its self-re gulating volt age)
VREFIN = 2.5V, ISET = 10 µA
Note 1:
VUVTH > VVREFIN
VOVTH < VVREFIN
VSENSE = VVNEG
VVFB = VVNEG
VDRAINTH = VVNEG
VOVO = VVNEG
VCL = VVREFIN
VENABLE = 5V (open)
VRESTART = VVNEG (open)
0.17
0.18
0.19
0.20
0.21
0.22
0.23
0.24
0.25
0.26
-40-200 20406080
Temperature (°C)
PWRGOOD, VOL (V)
2002-2012 Microchip Technology Inc. DS20091C-page 19
MCP18480
FIGURE 2-9: PWRGOOD Output High-
Voltage (VOH) vs. Temperature. FIGURE 2-10: PWRGOOD Output High-
Impedance vs. Temperature.
Dat a t aken with the min im um fol lowi ng c onditions:
ILOAD = -1 mA
IPOS = 5 mA
(Enables VPOS at its se lf-re gulating voltag e)
VREFIN = 2.5V, ISET = 10 µA
Note 1:
VUVTH > VVREFIN
VOVTH < VVREFIN
VSENSE = VVNEG
VVFB = VVNEG
VDRAINTH = VVNEG
VOVO = VVNEG
VCL = VVREFIN
VENABLE = 5V (open)
VRESTART = VVNEG (open)
95.5
95.8
96.0
96.3
96.5
96.8
97.0
97.3
97.5
-40-200 20406080
Temp erature (°C )
PWRGOOD VOH (%VPOS)
Dat a t aken with the min im um fol lowing conditions:
IPOS = 5 mA
(Enables VPOS at its self-re gulating volt age)
VREFIN = 2.5V, ISET = 10 µA
Note 1:
VUVTH > VVREFIN
VOVTH < VVREFIN
VSENSE = VVNEG
VVFB = VVNEG
VDRAINTH = VVNEG
VOVO = VVNEG
VCL = VVREFIN
VENABLE = 5V (open)
VRESTART = VVNEG (open)
155
165
175
185
195
205
215
225
235
245
-40-200 20406080
Temperature (°C)
PWRGOOD Output I m pedance
(Ohms)
MCP18480
DS20091C-page 20 2002-2012 Microchip Technology Inc.
FIGURE 2-11: PWRGOOD Output Low-
Impedance vs. Temperature.
Dat a t aken with the min im um fol lowi ng c onditions:
IPOS = 5 mA
(Enables VPOS at its se lf-re gulating voltag e)
VREFIN = 2.5V, ISET = 10 µA
Note 1:
VUVTH > VVREFIN
VOVTH < VVREFIN
VSENSE = VVNEG
VVFB = VVNEG
VDRAINTH = VVNEG
VOVO = VVNEG
VCL = VVREFIN
VENABLE = 5V (open)
VRESTART = VVNEG (open)
180
190
200
210
220
230
240
250
-40-200 20406080
Temperature (°C)
PWRGOOD Output Impedance
(Ohms)
2002-2012 Microchip Technology Inc. DS20091C-page 21
MCP18480
FIGURE 2-12: VREFOUT vs. Supply Current
(IPOS). FIGURE 2-13: VREFOUT vs. LOAD .
Dat a t aken with the min im um fol lowi ng c onditions:
3mA IPOS 30 mA
VREFIN = 2.5V, ISET = 10 µA
2.490
2.491
2.492
2.493
2.494
2.495
2.496
2.497
2.498
3456789101112131415
Supply Current, IPOS (mA)
VREFOUT (V)
TA = -40°C
TA = 0°C
TA = + 85°C
TA = +70°C
TA = +25°C
Dat a t aken with the min im um fol lowing conditions:
IPOS = 5 mA
(Enables VPOS at its self-re gulating volt age)
VREFIN = 2.5V, Iset = 10 µA
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.25
0.5
0.75
1
1.25
1.5
1.75
2
2.25
2.5
2.75
3
3.25
3.5
3.75
4
4.25
4.5
4.75
5
LOAD Current (mA )
VREFOUT (V)
TA = -40°C
TA = 0°C
TA = +85°C
TA = +70°C
TA = +25°C
MCP18480
DS20091C-page 22 2002-2012 Microchip Technology Inc.
FIGURE 2-14: TIMER Pin Output Low
Current vs. RDISCH Current. FIGURE 2-15: TIMER Pin Output High
Current vs. ISET Current.
Dat a t aken with the min im um fol lowi ng c onditions:
-50 µA < IISET < 50 µA (IISET 0)
IPOS = 5 mA
(Enables VPOS at its se lf-re gulating voltag e)
VREFIN = 2.5V
Note 1:
VUVTH > VVREFIN
VOVTH < VVREFIN
VSENSE = VVNEG
VVFB = VVNEG
VDRAINTH = VVNEG
VOVO = VVNEG
VCL = VVREFIN
VENABLE = 5V (open)
VRESTART = VVNEG (open)
1.0
1.2
1.4
1.6
1.8
2.0
2.2
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
RDISCH Current (u A )
Timer Pin Current (uA)
TA = -40°C
TA = + 85°C
TA = + 25°C
Dat a t aken with the min im um fol lowing conditions:
-50 µA < IISET < 50 µA (IISET 0)
IPOS = 5 mA
(Enables VPOS at it s self-re gulating vol tage)
VREFIN = 2.5V
Note 1:
VUVTH > VVREFIN
VOVTH < VVREFIN
VSENSE 100mV
VVFB = VVNEG
VDRAINTH = VVNEG
VOVO = VVNEG
VCL = VVREFIN
VENABLE = 5V (open)
VRESTART = VVNEG (open)
-225
-200
-175
-150
-125
-100
-75
-50
-25
0
-20
-18
-16
-14
-12
-10
-8
-6
-4
-2
0
2
4
6
8
10
12
14
16
18
20
ISET Current (uA)
Timer Pin Current (µA)
TA = -40°C
TA = +85°C
TA = +25°C
TA = -40°C
TA = +85°C
TA = +25°C
2002-2012 Microchip Technology Inc. DS20091C-page 23
MCP18480
FIGURE 2-16: UVD Pin Current vs. ISET Pin
Current.
FIGURE 2-17: ISET P in Voltage vs. VREFIN
Pin Voltage.
FIGURE 2-18: DRAINTH Threshold Voltage
vs. Supply current (IPOS).
Dat a t aken with the min im um fol lowi ng c onditions:
-50 µA < IISET < 50 µA (IISET 0)
IPOS = 5 mA
(Enables VPOS at its se lf-re gulating voltag e)
VREFIN = 2.5V
Note 1:
VUVTH < VVREFIN
VOVTH < VVREFIN
VSENSE VVNEG
VVFB = VVNEG
VDRAINTH = VVNEG
VOVO = VVNEG
VCL = VVREFIN
VENABLE = 5V (open)
VRESTART = VVNEG (open)
-60
-50
-40
-30
-20
-10
0
-50 -40 -30 -20 -10 0 10 20 30 40 50
ISET Pin Current (µA)
UVD Pin Current (µA)
TA = -40°C TA = +70°C
TA = +25°C
TA = 0°C
TA = +85°C
Dat a t aken with the min im um fol lowi ng c onditions:
IPOS = 5 mA
(Enables VPOS at its se lf-re gulating voltag e)
Iset = 10 µA
1.00
1.05
1.10
1.15
1.20
1.25
1.30
1.35
2.00 2.10 2.20 2.30 2.40 2.50 2.60
VREFIN Pin Voltage (V)
ISET Pin Voltage (V)
TA = -40°C
TA = +70°C
TA = +25°C
TA = +85°C
TA = 0°C
Dat a t aken with the min im um fol lowing conditions:
3mA IPOS 30 mA
VREFIN = 2.5V, ISET = 10 µA
Determined by PWRGOOD signal
Note 1:
VUVTH > VVREFIN
VOVTH < VVREFIN
VSENSE = VVNEG
VVFB = VVNEG
VOVO = VVNEG
VCL = VVREFIN
VENABLE = 5V (open)
VRESTART = VVNEG (open)
105
106
107
108
109
110
111
112
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Supply Current, IPOS (mA)
DRAINTH Voltage (mV)
TA = -40°C
TA = +70°C
TA = +25°C
TA = 0°C
TA = +85°C
MCP18480
DS20091C-page 24 2002-2012 Microchip Technology Inc.
FIGURE 2-19: RDISCH Current vs. Supply
Current (IPOS). FIGURE 2-20: RDISCH Voltage vs. RDISCH
Current.
Dat a t aken with the min im um fol lowi ng c onditions:
IPOS = 5 mA
(Enables VPOS at its se lf-re gulating voltag e)
VREFIN = 2.5V, ISET = 10 µA
RDISCH = 16 M
Note 1:
VUVTH > VVREFIN
VOVTH < VVREFIN
VSENSE = VVNEG
VVFB = VVNEG
VDRAINTH = VVNEG
VOVO = VVNEG
VCL = VVREFIN
VENABLE = 5V (open)
VRESTART = VVNEG (open)
820
830
840
850
860
870
5 10152025
Supply Current, IPOS (mA)
RDISCH Current (nA)
TA = -40°C
TA = +25°C
TA = +85°C
Dat a t aken with the min im um fol lowing conditions:
IPOS = 5 mA
(Enables VPOS at its self-re gulating volt age)
VREFIN = 2.5V, ISET = 10 µA
IRDISCH from 100 nA to 10 µA (500 nA steps)
Note 1:
VUVTH > VVREFIN
VOVTH < VVREFIN
VSENSE = VVNEG
VVFB = VVNEG
VDRAINTH = VVNEG
VOVO = VVNEG
VCL = VVREFIN
VENABLE = 5V (open)
VRESTART = VVNEG (open)
1.250
1.260
1.270
1.280
1.290
1.300
1.310
0 5 10 15 20 25 30 35 40 45 50
RDISCH Current (uA)
RDISCH Voltage (V)
TA = -40°C
TA = +25°C
TA = +85°C
2002-2012 Microchip Technology Inc. DS20091C-page 25
MCP18480
FIGURE 2-21: ENABLE/RESTART Pin T rip
Point Voltage vs. Temperature.
Dat a t aken with the min im um fol lowi ng c onditions:
IPOS = 5 mA
(Enables VPOS at its se lf-re gulating voltag e)
VREFIN = 2.5V, ISET = 10 µA
Determined by GATE voltage
Note 1:
VUVTH > VVREFIN
VOVTH < VVREFIN
VSENSE = VVNEG
VVFB = VVNEG
VDRAINTH = VVNEG
VOVO = VVNEG
VCL = VVREFIN
VRESTART = VVNEG (open)
1.36
1.37
1.38
1.39
1.40
1.41
1.42
1.43
-40-200 20406080
Temperature (°C)
Enable/Restart, VIL (V)
MCP18480
DS20091C-page 26 2002-2012 Microchip Technology Inc.
FIGURE 2-22: TIMER Output Sink Current
vs. Temperature. FIGURE 2-23: TIMER Output Source
Current vs. Temperature.
Dat a t aken with the min im um fol lowi ng c onditions:
RDISCH = 16 M
IPOS = 5 mA
(Enables VPOS at its self -regulating voltage)
VREFIN = 2.5V, ISET = 10 µA
0.1V VTIMER 1.25V
Note 1:
VUVTH > VVREFIN
VOVTH < VVREFIN
VSENSE = VNEG, I into device
VNEG + 100mV, I out of devi ce
VVFB = VVNEG
VDRAINTH = VVNEG
VOVO = VVNEG
VCL = VVREFIN
VENABLE = 5V (open)
VRESTART = VVNEG (open)
82.0
82.5
83.0
83.5
84.0
84.5
85.0
85.5
86.0
86.5
87.0
-40-200 20406080
Temper a t ure ( °C)
Timer Current (nA)
Dat a t aken with the min im um fol lowing conditions:
RDISCH = 16 M
IPOS = 5 mA
(Enables VPOS at its self-re gulating volt age)
VREFIN = 2.5V, ISET = 10 µA
0.1V VTIMER 1.25V
Note 1:
VUVTH > VVREFIN
VOVTH < VVREFIN
VSENSE = VNEG, I into device
VNEG + 100mV, I out of devi ce
VVFB = VVNEG
VDRAINTH = VVNEG
VOVO = VVNEG
VCL = VVREFIN
VENABLE = 5V (open)
VRESTART = VVNEG (open)
-154.0
-153.8
-153.5
-153.3
-153.0
-152.8
-152.5
-152.3
-152.0
-40-200 20406080
Temperature (°C)
Timer Current (uA)
2002-2012 Microchip Technology Inc. DS20091C-page 27
MCP18480
FIGURE 2-24: CL pin Input Offset Voltage
vs. Temperature. FIGURE 2-25: SENSE Pin Input Threshold
vs. Temperature.
Dat a t aken with the min im um fol lowi ng c onditions:
IPOS = 5 mA
(Enables VPOS at its se lf-re gulating voltag e)
VREFIN = 2.5V, ISET = 10 µA
Note 1:
VUVTH > VVREFIN
VOVTH < VVREFIN
VSENSE = 25mV
VVFB = VVNEG
VDRAINTH = VVNEG
VOVO = VVNEG
VCL = VVREFIN
VENABLE = 5V (open)
VRESTART = VVNEG (open)
-2.50
-2.00
-1.50
-1.00
-0.50
0.00
0.50
1.00
1.50
-40-200 20406080
Temperature (°C)
CL Pin Offset Vol t age, VOS (mV)
VSENSE = 20 mV
VSENSE = 30 mV
VSENSE = 40 mV
Dat a t aken with the min im um fol lowing conditions:
IPOS = 5 mA
(Enables VPOS at its self-re gulating volt age)
VREFIN = 2.5V, ISET = 10 µA
Use TIMER pin as indicator
Note 1:
VUVTH > VVREFIN
VOVTH < VVREFIN
VVFB = VNEG, VNEG+ 250mV,
VNEG+500mv, VNEG+1V
VDRAINTH = VVNEG
VOVO = VVNEG
VCL = VVREFIN
VENABLE = 5V (open)
VRESTART = VVNEG (open)
10
15
20
25
30
35
40
45
50
55
-40-200 20406080
Temperature (°C)
SENSE Pin Voltage (mV)
Vfb = 0V
Vfb = 1VVfb = 0.5V
Vfb = 0.25V
MCP18480
DS20091C-page 28 2002-2012 Microchip Technology Inc.
FIGURE 2-26: OVTH Input Rising Threshold
vs. OVO Voltage. FIGURE 2-27: OVTH Input Falling
Threshold vs. OVO Voltage.
Dat a t aken with the min im um fol lowi ng c onditions:
IPOS = 5 mA
(Enables VPOS at its se lf-re gulating voltag e)
OVO = VNEG to 8V
VREFIN = 2.5V, ISET = 10 µA
Use PWRGOOD pin as indicator
Note 1:
VUVTH > VVREFIN
VSENSE = VVNEG
VVFB = VVNEG
VDRAINTH = VVNEG
VCL = VVREFIN
VENABLE = 5V (open)
VRESTART = VVNEG (open)
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
0.01.02.03.04.05.06.07.08.0
OVO Voltage (V)
OVTH Input High Voltage (V)
TA = -40°C
TA = +70°C
TA = +85°C
TA = + 0 °C
TA = +25°C
Dat a t aken with the min im um fol lowing conditions:
IPOS = 5 mA
(Enables VPOS at it s self-re gulating vol tage)
OVO = VNEG to 8V
VREFIN = 2.5V, ISET= 10 µA
Use PWRGOOD pin as indicator
Note 1:
VUVTH > VVREFIN
VSENSE = VVNEG
VVFB = VVNEG
VDRAINTH = VVNEG
VCL = VVREFIN
VENABLE = 5V (open)
VRESTART = VVNEG (open)
2.474
2.475
2.476
2.477
2.478
2.479
2.480
012345678
OVO Voltage (V)
OVTH Input Low Voltage, VIL (V)
TA = -40°C
TA = +70°C
TA = +25°C
TA = 0°C
TA = +85°C
2002-2012 Microchip Technology Inc. DS20091C-page 29
MCP18480
FIGURE 2-28: UVD Current vs. Supply
Current (IPOS). FIGURE 2-29: UVHYS Pin Impedance vs.
Temperature.
Dat a t aken with the min im um fol lowi ng c onditions:
IPOS = 5 mA
(Enables VPOS at its self regu lating volt age)
VREFIN = 2.5V, ISET = 10 µA
Note 1:
VUVTH < VVREFIN
VOVTH < VVREFIN
VSENSE VVNEG
VVFB = VVNEG
VDRAINTH = VVNEG
VOVO = VVNEG
VCL = VVREFIN
VENABLE = 5V (open)
VRESTART = VVNEG (open)
-10.15
-10.10
-10.05
-10.00
-9.95
-9.90
5 1015202530
Supply Current, IPOS (mA)
UVD Current (uA)
TA = -40°C
TA = +70°C
TA = +25°C
TA = 0°C
TA = +85°C
Dat a t aken with the min im um fol lowi ng c onditions:
IPOS = 5 mA
(Enables VPOS at its se lf-regulating voltage)
VREFIN = 2.5V, ISET = 10 µA
Note 1:
VUVTH < VVREFIN
VOVTH < VVREFIN
VSENSE VVNEG
VVFB = VVNEG
VDRAINTH = VVNEG
VOVO = VVNEG
VCL = VVREFIN
VENABLE = 5V (open)
VRESTART = VVNEG (open)
Dat a t aken with the min im um fol lowing conditions:
IPOS = 5 mA
(Enables VPOS at its self-re gulating volt age)
UVTH < VREFIN, UVTH > VREFIN
VREFIN = 2.5V, ISET = 10 µA
Note 1:
VOVTH < VVREFIN
VSENSE = VVNEG
VVFB = VVNEG
VDRAINTH = VVNEG
VOVO = VVNEG
VCL = VVREFIN
VENABLE = 5V (open)
VRESTART = VVNEG (open)
0
5000
10000
15000
20000
25000
30000
35000
40000
45000
-40-200 20406080
Temperature (°C)
UVHYS Pin Impedance (Ohms)
ON
OFF
MCP18480
DS20091C-page 30 2002-2012 Microchip Technology Inc.
FIGURE 2-30: UVTH Input Rising
Threshold vs. Temperature. FIGURE 2-31: UVTH Input Falling
Threshold vs. Temperature.
Dat a t aken with the min im um fol lowi ng c onditions:
IPOS = 5 mA
(Enables VPOS at its se lf-re gulating voltag e)
VREFIN = 2.5V, ISET = 10 µA
Use PWRGOOD pin as indicator
Note 1:
VOVTH < VVREFIN
VSENSE = VVNEG
VVFB = VVNEG
VDRAINTH = VVNEG
VOVO = VVNEG
VCL = VVREFIN
VENABLE = 5V (open)
VRESTART = VVNEG (open)
2.5018
2.5020
2.5022
2.5024
2.5026
2.5028
2.5030
2.5032
2.5034
-40-200 20406080
Temperature (°C)
UVTH Rising Threshold (V)
Dat a t aken with the min im um fol lowing conditions:
IPOS = 5 mA
(Enables VPOS at its self-re gulating volt age)
VREFIN = 2.5V, ISET = 10 µA
Use PWRGOOD pin as indicator
Note 1:
VOVTH < VVREFIN
VSENSE = VVNEG
VVFB = VVNEG
VDRAINTH = VVNEG
VOVO = VVNEG
VCL = VVREFIN
VENABLE = 5V (open)
VRESTART = VVNEG (open)
2.5010
2.5015
2.5020
2.5025
2.5030
2.5035
-40-200 20406080
Temperature (°C)
UVTH Falling Threshold (V)
2002-2012 Microchip Technology Inc. DS20091C-page 31
MCP18480
FIGURE 2-32: OVTH Input Rising Threshold
vs. Temperature. FIGURE 2-33: OVTH Input Falling
Threshold vs. Temperature.
Dat a t aken with the min im um fol lowi ng c onditions:
IPOS = 5 mA
(Enables VPOS at its se lf-re gulating voltag e)
VREFIN = 2.5V, ISET = 10 µA
Use PWRGOOD pin as indicator
Note 1:
VOVTH < VVREFIN
VSENSE = VVNEG
VVFB = VVNEG
VDRAINTH = VVNEG
VOVO = VVNEG
VCL = VVREFIN
VENABLE = 5V (open)
VRESTART = VVNEG (open)
2.5057
2.5062
2.5067
2.5072
2.5077
2.5082
2.5087
-40-200 20406080
Temperature (°C)
OVTH Rising Threshold (V)
Dat a t aken with the min im um fol lowing conditions:
IPOS = 5 mA
(Enables VPOS at its self-re gulating volt age)
VREFIN = 2.5V, ISET = 10 µA
VUVHYS = VNEG
Use PWRGOOD pin as indicator
Note 1:
VOVTH < VVREFIN
VSENSE = VVNEG
VVFB = VVNEG
VDRAINTH = VVNEG
VOVO = VVNEG
VCL = VVREFIN
VENABLE = 5V (open)
VRESTART = VVNEG (open)
2.4775
2.478
2.4785
2.479
2.4795
2.48
2.4805
-40-200 20406080
Temperature (°C)
OVTH Falling Threshold (V)
MCP18480
DS20091C-page 32 2002-2012 Microchip Technology Inc.
NOTES:
2002-2012 Microchip Technology Inc. DS20091C-page 33
MCP18480
3.0 PIN DESCRIPTIONS
TABLE 3-1: MCP18480 PIN DES CRIP TIONS
Pin Name
Pin
Number Pin
Direction Buffer
Type Description
SSOP
VPOS 1 I P Positive supply input.
Internal Shunt Regula tor connected betwee n VPOS and VNEG limits the
potential to 12V between these two pins. A series resistor must be
placed on the VPOS pin to limit the current into the device.
OVTH 2 I A Overvoltage protection threshold.
An external resistor divider network is connected to this input pin to
program the overvoltage protection threshold. The selected external
resisto r values for the OVTH to system ground and OVTH to VNEGresis-
torsshould have currents in the 1 mA range. A typical Overvoltage
thr e sh ol d is -76V. In te r n al hy ste r es is in th e o v er vo l tage inp u t com par -
ator will allow proper operation once VNEG falls below the selected
threshold.
UVTH 3 I A Undervoltage lockout threshold.
An external resistor divider network is connected to this input pin to
program the undervoltage lockout threshold. If the voltage on UVTH is
less th an VNEG + 2.5V, the underv oltage com parator w ill trip, indica ting
an Undervoltage condition.
An external hysteresis resistor can be used to set the high-to-low
(VTHF) threshold below the low-to-high (VTHR) threshold. For telecom
network equipment, it is desirable to have shutdown occur at -38.5V
and the startup set at - 43.0V.
UVHYS 4 I A Undervoltage internal comparator hysteresis.
An externa l res is tor is co nne cte d bet w een this input to the UVTH input
pin to adjust the hysteresis of the internal Undervoltage comparator.
Since it is desirable to shut down at -38.5V and restart at -43.0V in
telecom switch equipment.
UVD5 I/O A Undervoltage event delay.
An external capacitor is connected to this input pin to set the delay
betwe en when the UVTH pin drop s below th e trip point spe cified by the
voltage on the VREFIN pin and when the system shutdown occurs
(causing the PWRGOOD pin to be driven to an inactive level and the
GATE pin to be pulled to the VNEG pin voltage level). The UVD pin
sources a current equivalent to the IISET (in typical applications, the
IISET current equals 10 µA), which charges this external capacitor
while an internal comparator compares this voltage on the UVD pin to
|VREFIN|/2.
Typic all y, for telecom e quipment, the sy ste m is expected to shu t do w n
when the input voltage falls below -38.5V (±1.0V DC) for greater than
100 ms.
Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels
I = Input O = Output
P = Power CMOS = CMOS-compatible input
A = Analog D = Digital
MCP18480
DS20091C-page 34 2002-2012 Microchip Technology Inc.
VREFOUT 6 O A Reference output.
Internal reference output voltage (typically 2.5V). Usually tied back to
the VREFIN pin unless an external high-precision reference voltage is
desired.
VREFIN 7 I A Reference input.
This pin allows a high-precision reference voltage for the following
functions:
• Undervoltage Comparator
• Overvoltage Comparator
• DRAIN Comparator
• Current Limit Timer
If the precision of the VREFOUT output voltage is acceptable, tie the
VREFOUT pin to the VREFIN pin.
CL 8 I A Current Limit.
Input used to set the maximum current limit threshold allowed by the
system via a resistor divider network (with the resistor RCL1 betwe en
the VREFIN pin and the CL pin and resistor RCL between the VNEG pin
and t he CL p in). If th e voltage acro ss th e sens e resis tor exceeds the
volt age on the CL pin , it implies that th ere is excessiv e current over the
allowed limit and forces the GATE pin to the VNEG pin voltage level
without delay.
ISET 9 I A Curre nt sou rce set.
Establishes the internal ISOURCE for the following:
• Undervoltage Delay
• Current Limit Timer
• GATE Pin Source Current
An external resistor RISET from the ISET pin must be connected to
either the VNEG pin or the VREFIN pin to set IBIAS, whi ch will then est ab-
lish the current so urces throu ghout th e devic e. The IBIAS current is th e
same for either connection.
Connecting the RISET resistor to the VNEG pin will establish the
PWRGOO D pin output polarity to be active-high . Connecti ng the RISET
resistor to the VREFIN pin will establish the PWRGOOD pin output
polarity to be active-low.
TABLE 3-1: MCP18480 PIN DES CRIP TIONS (CONTINUED)
Pin Name
Pin
Number Pin
Direction Buffer
Type Description
SSOP
Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels
I = Input O = Output
P = Power CMOS = CMOS-compatible input
A = Analog D = Digital
2002-2012 Microchip Technology Inc. DS20091C-page 35
MCP18480
TIMER 10 I A Current Limit Timer.
The value of the external capacitor (CTIMER) connected to the TIMER
pin se ts t he tw o ti me p eri od s us ed d uri ng a cur ren t -li mi t ev e nt. T he se
are:
• The time that the GATE pin will limit the current through the
ext ernal FET
• The time that the GATE pin will disable the external FET
Duri ng curre nt limit , a pull- up curre nt sour ce charge s up the external
capacitor. Until the voltage on the TIMER pin reaches VREFIN/2, the
GAT E pin is driv en to main ta in a reduc ed curren t flow determi ned by
the VDS of the external FET.
While the capacit or is being discharg ed b y th e pu ll -dow n cu rrent ( pul l-
up current is off), the GATE pin is at VNEG and the PW RGOOD pi n is
deasserted. When the TIMER voltage falls below approximately
100 mV, the GATE pin turns on , if the RESTART pin is low, to reset the
internal fault latch. If the RESTART pin is high, the GATE pin remains
off until the ENABLE pin is forced low. It is then forced high or the
RESTART pin is forced low (asserted).
The PWRGOOD pin reasserts after the voltages on the DRAINTH and
GATE pins meet the appropriate conditions.
The TIMER pin pull-up current is proportioned to the IISET current
(approximately a multiple of 16).
VNEG 11 I P Negative supply input.
The negative voltage applied to the board by the backplane (typically
the most negative voltage in the system).
RDISCH 12 I A External MOSFET activation delay.
An external resistor (RRDISCH) is connected between the RDISCH pin
and the VNEG pin and is used to set t he delay bet ween the dea ctivation
and activation of the external pass MOSFET during a current-limit
event. Th e dela y is set by the values of the external cap acitor (CTIMER)
and the external resistor (RRDISCH). The formulas are:
TDEACT = (CTIMER x RISET) / 16
TACT = (9.2 x RRDISCH x CTIMER)
TABLE 3-1: MCP18480 PIN DES CRIP TIONS (CONTINUED)
Pin Name
Pin
Number Pin
Direction Buffer
Type Description
SSOP
Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels
I = Input O = Output
P = Power CMOS = CMOS-compatible input
A = Analog D = Digital
MCP18480
DS20091C-page 36 2002-2012 Microchip Technology Inc.
SENSE 13 I A Over-current sense.
The volt age on the SENSE input pin is used to detect over-curre nt con-
ditions in the load connected to the external MOSFET. This pin is
directly connected to the source of the MOSFET, with an external
resistor (RSENSE) (typically a low resistance) connected between the
source of the MOSFET and VNEG.
GATE 14 O A MOSFET gate driver.
The GATE output pin attaches to the gate of the external MOSFET.
The voltage on the GATE pin is pulled to the voltage on the VNEG pin
whenever the voltage on the UVTH pin is less than the voltage on the
VREFIN pin, or the voltage on the OVTH pin is greater than the voltage
on the VREFIN pin.
The GATE pin is also pulled to the voltage on the VNEG pin when the
ENABLE input pin is low.
When cu rren t limi t is rea ched, the vo lta ge on th e GATE pin is adju sted
to maintain a constant voltage across the RSENSE resistor while the
CTIMER capacitor starts to charge. When the voltage on CTIMER
exceeds VREFIN/2, the GATE pin is p ulled to V NEG to turn off the ext er-
nal MOSFET. A RC network can be added from the GATE pin to the
drain of the external MOSFET, along with a capacitor from the GATE
pin to the VNEG pin, to control the slew rate of the GATE pin.
The GATE pin pull-up current is proportioned to the IISET current .
VFB 15 I A External MOSFET drain monitor.
The VFB input pin monitors the voltage at the drain of the external
power MO SFET switch with re spe ct to the vo ltage on the VNEG pin for
use by the internal foldback circuitry. An external resistor divider net-
work (RFB1 and RFB2) is attached between the drain of this external
MOSFET and the VNEG pin (RFB1 is connected between the drain of
the external MOSFET and the VFB pin, while RFB2 is connected
between the VFB pin and the VNEG pin). This prevents high-voltage
breakdown of the VFB input.
DRAINTH 16 I A MOSFET drain comparator threshold.
This pin is used during the power-up sequence of the inserted board,
and after any fault condition that ‘turns off’ the GATE pin drive. The
voltage on the pin indicates when the external FET is fully enhanced
by comparing the pin voltage to an internal reference voltage
(approxima tely 10 0 mV derived fro m the intern al band g ap reference ).
An extern al resistor di vider netwo rk (RDRAIN1 and RDRAIN2) is attached
between the drain of this external MOSFET and the VNEG pin (RDRAIN1
is connected between the drain of the external MOSFET and the
DRAINTH pin while RDRAIN2 is connected between the DRAINTH pin
and the VNEG pin).
TABLE 3-1: MCP18480 PIN DES CRIP TIONS (CONTINUED)
Pin Name
Pin
Number Pin
Direction Buffer
Type Description
SSOP
Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels
I = Input O = Output
P = Power CMOS = CMOS-compatible input
A = Analog D = Digital
2002-2012 Microchip Technology Inc. DS20091C-page 37
MCP18480
OVO 17 I A Overvoltage detect.
Typical l y for normal operation. This pin is tied to VNEG.
This fe ature allows the o verv ol t age detection in put to monitor an over-
voltage condition across the power module. The voltage is sensed at
the drai n of the e xternal M OSFET. The volt age ac ross the load is int er-
nally determined based upon:
• The voltage difference between system ground and the voltage
on the VNEG pin
• The volt age dif fere nce between th e drain of the ex ternal FET and
the voltage on the VNEG pin
An external resistor divider network (ROVO1 and ROVO2) is attached
between the drain of the external MOSFET and the VNEG pin (ROVO1
is con necte d betwee n the dr ain of the externa l MOSFET a nd the OVO
pin, while ROVO2 is connected between the OVO pin and the VNEG
pin).
When the voltage across the external MOSFET (source-to-drain)
equals system ground voltage (- VNEG +), the maximum desired load
voltage, the GATE pin is forced to the voltage on the VNEG pin
(disabling the external MOSFET).
To detect Overvoltage on the board (instead of the load) directly,
connect the OVO pin to the VNEG pin.
PWRGOOD 18 O D Power Good indicator.
This state of the output is determined by four conditions. These are:
• Undervoltage
• Overvoltage
• Current Limit
• External FET is fully-enhanced (from DRAINTH pin on power-up)
PWRGOOD is a CMOS logic voltage (VNEG or VNEG+12V).
PWRGOOD is active when the device has completed power-up and
the system is neither in an Undervoltage or Ov ervoltage condition.
Connecting the RISET pin to the VNEG pin configures the PWRGOOD
pin to be active high. Connecting the RISET pin to the VREF pin con fig-
ures the PWRGOOD pin to be active low.
ENABLE 19 I TTL Enable Gate driver.
Used to enable the GATE pin and assert the PWRGOOD pin. The
ENABLE pin is activ e-high a nd is int erna lly pul led up to 5V. This pin i s
pulled low by the user to clear the current limit latch when a current-
limit fault occurs with RESTART high, or to disable the GATE pin.
H = Enable the GATE and PWRGOOD pins.
L = Di sables the GATE pin, deas serts the PWRGOOD pin and clears
current limit latch.
When the ENABLE pin is high, fault conditions will disable the GATE
pin and deasserts the PWRGOOD pin.
TABLE 3-1: MCP18480 PIN DES CRIP TIONS (CONTINUED)
Pin Name
Pin
Number Pin
Direction Buffer
Type Description
SSOP
Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels
I = Input O = Output
P = Power CMOS = CMOS-compatible input
A = Analog D = Digital
MCP18480
DS20091C-page 38 2002-2012 Microchip Technology Inc.
RESTART 20 I TTL Auto-restart enable.
Enables the auto-restart feature of the device after an over-current
fault.
L = The internal fault latch is reset and the device attempts to restart
with a freq uency det ermined by the va lues of the ex ternal com ponent s
CTIMER and RDISCH.
H = The auto-restart is disabled, allowing the GATE pin to remain at
the VNEG pin vo ltage afte r a n o ve r-cu rrent fault. Internall y pul led do wn
to the VNEG pin volta ge.
TABLE 3-1: MCP18480 PIN DES CRIP TIONS (CONTINUED)
Pin Name
Pin
Number Pin
Direction Buffer
Type Description
SSOP
Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels
I = Input O = Output
P = Power CMOS = CMOS-compatible input
A = Analog D = Digital
2002-2012 Microchip Technology Inc. DS20091C-page 39
MCP18480
4.0 APPLICATIONS INFORMATION
The MCP18480 can be programmed to have the
PWRGOOD signal be either active-high or active-low
via the ISET pin and the connection of the external
RISET resistor (see Section 6.8.8, “Bias Block”). If the
RISET re sistor is connected between ISET and VNEG, the
PWRGOOD output pin is an active-high signal. If the
RISET resistor is connected between ISET and VREFIN,
the PWRGOOD output pin is an active-low signal.
For systems using an ac tive-low-enabled DC/DC con-
verter module, the MCP18480 should be programmed
for a high-active PWRGOOD output. Tying the RISET
resistor to the VNEG pin configures the PWRGOOD to
be an active-high signal. The active-high PWRGOOD
switches on the external NPN and the collector of the
external NPN (labeled as GOODPWR) is pulled to
VNEG, enabling a low -active GOODPWR and resulting
in enabling the DC/DC module.
For active-high DC/DC converter modules, the
MCP18480 should be programmed for a low active
PWRGOOD output. Connecting RISET to the VREFIN
pin wi ll e na ble an active-low PWR G OOD ou tpu t. R ef er
to Figure 4-1 and Figure 4-2 for schematics.
Figure 4-1 shows a typical telecom application circuit
where the DC/DC module is active-high. Figure 4-2
shows a typical telecom application circuit where the
DC/DC module is active-low. The polarity of the
MCP18480’s PWRGOOD pin (active-high or active-
low) is dependant on the state of the ISET pin.
FIGURE 4-1: Typical Operating Circuit for Telecom Applications with Active-High power Module -
foldback current limit enabled.
+
RUV1
ROV2 RUV2
CUVD
RISET
Ctimer
RDISCH
RUVHYS
RPOS
CBYP2
RSENSE
RDRAIN1
RDRAIN2
RFB1
RFB2
CGD
RGD
RG1
CG1
QPG2
QPG3
RPG2
RPG6
M1
CBYPL
RBYPL
VNEG
RPG1 RPG5
4k
2µF 10nF
1.74 M453 k
280 k
59 k30.9 k
800 nF
124 k
680 nF
1.6 M
0.01
7.5 k
110 kMPSA43
100 nF 103.3 nF
18 k
680
36 k
36 k
1500
100 µF
51 k
2N5400
NTE261
124 k
115 k
1.74 M
1.6 M
NTE2388
RZ
24.9 k
5V RPG3
RPG4
QPG1
RESTART
ENABLE
PWRGOOD
VPOS
OVTH
UVTH
UVHYS
UVD
VREFIN
VREFOUT
CL
ISET
TIMER
OVO
DRAINTH
VFB
GATE
SENSE
VNEG
RDISCH
1
2
3
4
5
6
7
8
9
10 11
12
13
14
15
16
17
18
19
20
DC/DC
Converter
Module
VIN+
VIN-
VOUT+
VOUT-
ON/OFF
100 V
78V
Fuse 10A
GND
Transorb
CBYP1
ROV1
GOODPWR
MCP18480
SRS
SEN
MCP18480
DS20091C-page 40 2002-2012 Microchip Technology Inc.
FIGURE 4-2: Typical operating circuit for telecom applications with Active-Low power Module -
foldback current limit enabled.
+
RUV1
ROV2 RUV2
CUVD
RISET
Ctimer
RDISCH
RUVHYS
RPOS
CBYP2
RSENSE
RDRAIN1
RDRAIN2
RFB1
RFB2
CGD
RGD
RG1
CG1
QPG2
QPG3
RPG2
RPG6
M1
CBYPL
RBYPL
VNEG
RPG1 RPG5
4k
2µF 10nF
1.74 M453 k
280 k
59 k30.9 k
800 nF
124 k
680 nF
1.6 M
0.01
7.5 k
110 kMPSA43
100 nF 103.3 nF
18 k
680
36 k
36 k
1500
100 µF
51 k
2N5400
NTE261
124 k
115 k
1.74 M
1.6 M
NTE2388
RZ
24.9 k
5V RPG3
RPG4
QPG1
RESTART
ENABLE
PWRGOOD
VPOS
OVTH
UVTH
UVHYS
UVD
VREFIN
VREFOUT
CL
ISET
TIMER
OVO
DRAINTH
VFB
GATE
SENSE
VNEG
RDISCH
1
2
3
4
5
6
7
8
9
10 11
12
13
14
15
16
17
18
19
20
DC/DC
Converter
Module
VIN+
VIN-
VOUT+
VOUT-
ON/OFF
100 V
78V
Fuse 10A
GND
Transorb
CBYP1
ROV1
GOODPWR
MCP18480
SRS
SEN
2002-2012 Microchip Technology Inc. DS20091C-page 41
MCP18480
The MCP18480 can typically be implemented in a
backplane system in one of two methods. Figure 4-3
shows a system where the backplane integrates the
MCP18480 for every slot. Figure 4-4 shows a system
where the backplane does not integrate the
MCP18480s and each card that will be inserted into
any slot is required to integrate the MCP18480.
FIGURE 4-3: Backplane System Block Diagram #1.
FIGURE 4-4: Backplane System Block Diagram #2.
Card
#2
Card
#n
Card
#1
MCP18480
MCP18480
MCP18480
Card # n
MCP18480
Card # 2
MCP18480
Card # 1
MCP18480
MCP18480
DS20091C-page 42 2002-2012 Microchip Technology Inc.
NOTES:
2002-2012 Microchip Technology Inc. DS20091C-page 43
MCP18480
5.0 POWER-UP
5.1 VPOS and VNEG Connection
For prope r sys tem opera tion, i t is re quired that th e sys-
tem ground and the VNEG pin have a solid connection
before voltages are applied to any logic on the board.
5.2 The Board Circuitry
After the MCP18480 has “good” voltages on the VPOS
and VNEG pins, the bo ard may have volt ages applie d to
any of th e oth er sig nals (a “go od” v olt age o n VPOS indi-
cates a “good” voltage on the system ground). The
MCP18480 will start to source a small current to the
external MOSFET to begin powering the board. This
will turn on the MOSFET starting to power the external
circuit ry (load) of the board. The c urrent from the GATE
pin (into the external MOSFET) increases as the VDS of
the MOSFET decreases. When the VDS of the MOS-
FET is below the voltage determined by the two resis-
tors on the DRAINTH pin (RDRAIN1 and RDRAIN2), and
the voltage on the GATE pin is greater than 8V, the
PWRGOOD pin is active.
6.0 INTERNAL SIGNAL
DESCRIPTIONS
The figure on page 2 illustrates a block diagram of the
MCP18480. Between the functional blocks, there are
some signals th at have b een named. These signals are
briefl y exp la ine d in Secti on 6.1 thru Section 6.7.
6.1 Undervol tage Active
A signal that indicates (when low) that System Ground
- VNEG is less then the minimum voltage.
6.2 Overvoltage Active
A signal that indicates (when low) that System Ground
-VNEG is greater then the maximum voltage.
6.3 LATCHOFF
A signal that controls the GATE pin due to a timeout of
the current-limiting timer.
6.4 Current Limit TIMER
A signal that controls th e reduction o f source current o n
the GATE pin and s tarts the vol tage ra mp of the current
limit timer.
6.5 Current Limit Feedback
A voltage that is proportion al to the VDS of the external
MOSFET to set a trip point for current-limiting.
6.6 TIMEOUT
A signal that indicates the completion of the foldback
time and is used to start the latchoff time.
6.7 Ci rcuit Breaker
A signal that immediately causes the GATE pin output
to be driven to VNEG upon the detection of excessive
current in the external FET.
MCP18480
DS20091C-page 44 2002-2012 Microchip Technology Inc.
6.8 DESCRIPTION OF INTERNAL
BLOCKS
The int ernal blocks s hown in the MCP184 80 Block Dia-
gram on p age 2 are d iscus sed in Sec tion 6.8.1 throug h
Section 6.8.8.
6.8.1 UV (UNDERVOLTAGE) BLOCK
The Undervoltage lockout circuit monitors the input
voltage by comparing a centertap voltage on an exter-
nal resistor divider to a 2.5V reference. The centertap
voltage is fed into the UVTH input pin.
If the volt age on the UVTH pin is belo w the in ternal 2.5V
reference, the absolute magnitude of the supply volt-
age is too low for proper system operation, resulting in
the ext ernal MOSFET bei ng turned of f. If the v oltage on
the UVTH pin is greater than VNEG + 2.5V, the supply
voltage is above the minimal operating voltage as set
by the external res istor divider network.
In telecom network applications, it is common to shut
down the DC/DC converter supply when the input volt-
age falls below -38.5V (tolerance of ±1.0V) for greater
than 100 ms. The system will not restart until the volt-
age exceeds -43.0V (tolerance of ±0.5V). This voltage
difference is produced by an open-drain NMOS output
(the UVHYS pin) that connects an external resistor in
parallel with the lower of the two resistors in the exter-
nal UV di vider network until the supply ramps down to
-43V. When the UVTH pin exceeds VNEG + 2.5V, the
internal NMOS transistor is turned off, disconnecting
the external resistor connected to the UVHYS pin. The
volt age at th e UVTH pin incr eases to 2.79 V. The supply
voltage would have to decrease to -38.5V in order to
assert the internal “Undervoltage Active” signal.
An internal 10 µA current source and an external
capacitor connected to the UVD pin adjusts the delay
between the input fault and the notification of this fault
to the s ystem. T his i s usu ally 100 ms for -48V te lecom-
type equipment. For customized adjustments, the time
delay can be expressed as Equation 6-1.
EQUATION 6-1: INPUT FAULT DELAY
CUV is the capacitor connected between the UVD pin
and the VNEG pin. A value of 1 µF would provide a
delay of about 100 ms.
If the supply voltage dips below the programmed
threshol d, the input c omparator tri ps the oth er way . Th e
timing capacitor is released to ramp-up at the previ-
ously described rate and the Undervoltage block
switches when the capacitor voltage reaches 1.25V.
When the input co mparator goes to a low level, the hys-
teresis FET is turned on and the trip point for
reassertion of good VNEG reverts to -43V.
While the Undervoltage Active signal is low (includes
Undervoltage input filter), the GATE pin driver for the
external MOSFET is disa bled, the GA TE pin is pulle d to
the voltage of the VNEG pin with a 60 mA current si nk
and the PWRGOOD output pin is deasserted to indi-
cate that the input voltage is out of range.
EQUATION 6-2: UNDERVOLT A GE
HYSTERESIS
EQUATION 6-3: UNDERVOLT A GE
CONDITION
Note: Voltage levels discussed are with respect
to external component values selected in
Figure 4-1.
TDELAY
VREFIN
2
------------------


CUVD
10A
--------------------------------------------
=
RUVHYS RUV1
VUVD
VREFIN
------------------


RUV1
RUV2
-------------1––
----------------------------------------------------
=RUVHYS RUV1
VUVD
VREFIN
------------------


RUV1
RUV2
-------------1––
----------------------------------------------------
=
VREFIN VNEG RUV2
RUV1 RUV2
+
-------------------------------------
2002-2012 Microchip Technology Inc. DS20091C-page 45
MCP18480
6.8.2 OV (OVERVOLTAGE) BLOCK
The overvoltage block behaves similarly to the under-
voltage block in that it monitors an input voltage by
comparing a centertap voltage on an external voltage
divider (o n the OVTH pin) to the VREFIN pin volt a ge.
If the cent ertap voltage is below the reference, the input
voltage is not excessive. If the centertap voltage is
greater than the VNEG + VREFIN pin voltages, t he supply
voltage is higher than the programmed acceptable
maximum voltage limit. An internal flag is then acti-
vated to inform the MCP18480 that the input voltage
has exceeded the preset limit.
The “Overvoltage Active” signal deasserts when the
input voltage drops back below the threshold
determined by the external resistors (ROV1 and ROV2).
EQUATION 6-4: OVERVOLTAGE VOLTAGE
CONDITION
6.8.3 FET-GOOD BLOCK
The FET-good block monitors the voltage between the
drain of the external MOSFET and on the VNEG pin at
power-up. It delays assertion of PWRGOOD until the
drain-to-source voltage of the external FET is accept-
ably low and the voltage at the GATE pin is about 8V.
The comparator operation is similar to Undervoltage
and Overvoltage blocks.
To prevent applying excessiv e voltages to the gates of
the FETs in the Un dervolt age circu it, a resisti ve volt age
divide r is emplo yed bet ween ground and the VNEG pin.
Similarly, the drain of the external MOSFET can be
exposed to voltages at around VNEG during normal
operation and as high as ground (typically 48V above
VNEG).
The FET goo d block also monitors the GA TE pin. When
the GATE pin becomes >VNEG +8V and the DRAINTH
pin is within its programmed range, the output of the
FET good block is active.
The internal FET good signal goes high and remains
active until a fault condition (Undervoltage, Overvolt-
age or Current Limit) is detected. Any of these condi-
tions hold the PWRGOOD signal deasserted until the
fault condition is removed and the external FET gate
and drain voltages are acceptable.
MCP18480
DS20091C-page 46 2002-2012 Microchip Technology Inc.
6.8.4 CURRENT LIMIT BLOCK
An excessive current flowing through the external FET
is sensed as a voltage across an external resistor
connected between the FET’s source and VNEG.
The drain voltage is sensed with a resistor divider net-
work, as shown in Figure 4-1 and Figure 4-2. The volt-
age tap is applied to a circuit whose output is 50 mV
above VNEG when the drain of the external FET is at
VNEG. The output is 12 mV when the VFB pin is
VNEG +0.5VThis output voltage is the Current Limit
Feedbac k (CLFB) signal to the gate dri ver block fo r use
in the fold-back current-limiting.
The CLFB voltage serves as the reference for a com-
parator whose other input monitors the voltage across
the curren t limit sens e resistor in series with the source
of the e xt erna l F E T. Whe n the SENSE p in ex ce eds th e
voltage on CLFB, a comparator output goes high to
start the t im er (s ee Se cti on 6.8.5). The VDS depe ndent
threshol d for the current limi t help s keep the FET within
its safe operating area.
Another comparator in the current-limiting block
watches the SENSE pin for potentially catastrophic
over-current conditions, which require immediate ter-
minat ion of conduct ion in t he pass MOSF ET. T he out-
put of this comparator trips a comparator used in the
TIMER block to skip the first part of the timeout cycle
and go straight to the “off” period. In some cases, the
user may want t o progra m the sy stem to s hut of f imme-
diately if there is a short-circuit condition that exceeds
a desired level. To use this feature, connect a divider
betwee n th e VREFIN pin and the VNEG pin, wit h it s ce n-
tertap at the CL input pin. The circuit breaker current
that would trigger this mode is given by Equation 6-5.
EQUATION 6-5: CIRCUIT BREAKER
THRESHOLD
If this function is not needed in a particular application,
it can be disabled by connecting the CL pin to the
VREFIN pin. Equation 6-6 shows the current of the CL
pin during current-limiting.
EQUATION 6-6: CL PIN CURRENT
6.8.5 TIMER BLOCK
Since the external FET can survive brief over-current
episode s, it i s unne cess ary to tu rn of f the FET ins ta ntly
when the cu rrent rise s to o hig h (s ee ex te rnal FE T data
sheet). T he tim er circ uit uses the ou tput of the co mp ar-
ator in the current-limiting block to begin charging an
external capacitor with 16 • IRISET (typically 160 µA)
when a n over-c urrent conditio n is dete cted. Whe n the
voltage on the capacitor ramps up to 1.25V, a compar-
ator output goes high. This output goes to another
block that tells the gate driver to turn the external FET
of f and deasse rt the PWRG OOD pin. The comple men-
tary output of the timer changes the state of a hystere-
sis circuit that drops the reference input of the
comp ara tor to VNEG + 100 m V (± 10 mV).
When the FET is off, the current through it drops to
zero, so that the voltage across the curren t sense resis-
tor also goes to zero and the current limit signal to the
timer block goes away. The timer capacitor starts to
discha rge at a rate s et by t he ext erna l resi stor, RDISCH.
Equation 6-7 shows the equations used to calculate the
current a t th e TIMER pin. This cu rrent is used for oth er
calculations.
EQUATION 6-7: TIMER PIN CURRENT
CALCULATIONS
The delay between the inception of the over-current
condition and the deactivation of the FET is given by
Equation 6-8.
EQUATION 6-8: OVER-CURRENT FAULT
DELAY
The time required to reset the timer and reactivate the
gate driver is giv en by Equati on 6-9.
EQUATION 6-9: OVER-CURRENT
REACTIVATION DELAY
As described above, the timer circuit operates as a
free-running, multi-vibrator, if RESTART is low.
ICAT
VREFIN
RCL1 RCL2
+
-------------------------------


RCL2
RSENSE
-------------------------------------------------------
=
VFB
0V
> 0.5V
50 mV
12 mV
VSENSE
for VFB > 0.5V, VSENSE = 0.012V
ICL VSENSE
RSENSE
------------------
=
VSENSE 0.76 0.05V VDS RFB2
RFB1 RFB2
+
-------------------------------
–


0.012V+=
Legend: IRISET is the current through the external
RISET resistor
ITIMER 16 IRISET
=Typical
ITIMER 10 IRISET
=Minimum
ITIMER 20 IRISET
=Maximum
TCLD1 CTIMER
ITIMER
-------------------1.25=
TCLD2 9.2 CTIMER
RDISCH
=
2002-2012 Microchip Technology Inc. DS20091C-page 47
MCP18480
6.8.6 LATCH BLOCK
A current limit latch circuit determines w hether, follow-
ing the timeout period resulting from an over-current
condition, the external FET should be latched-off until
reactivated by an external signal, or be allowed to
restart automatically following the timer cycle.
If the RESTART input is low , the part will restart and the
gate drive to the external MOSFET will be restored
automatically. If the RESTART pin is high, a current
limit event will turn the FET off after the programmed
delay and maintain an off condition until the ENABLE
pin or RESTART pin is pulled low momentarily.
6.8.7 GATE DRIVE BLOCK
The GATE drive block sources a current equal to the
voltage at CLFB divided by 1 k to the gate of the
external MOSFET. So the current sourced from the
GATE pin is de termined by the V DS of the externa l FET.
This current, and the external capacitors around the
FET, control the slew rate of the drain of the external
FET, limiting the current that would otherwise have to
be diverted from other boards on the backplane. In the
event of a problem (Overvoltage, Undervoltage or cur-
rent limit), the gate of the external FET is pulled down
with 60 mA. During normal operation, the GATE pin
ramps up to about 12V, sending the external FET
deeply into the triode region. If the drain current
becomes excessive while the dra in-to-source vol tage is
high, the inverting input of the op amp is driven to the
CLFB voltage by the current-limiting block, causing a
reductio n i n t he drive to the ext erna l F E T to red uc e th e
current through it. This foldback current-limit remains
active until the voltage on CTIMER reaches VREFIN/2,
after which the GATE output pin is pulled to VNEG for
the duration of the timeout period, or until ENABLE is
cycled low m omentar ily.
For applications in which it is undesirable to have the
drain current track the VDS of the external pass FET in
current li mit, the user ca n tie the V FB pin to the VREF or
VNEG pin. Thi s will m ake the M CP18480 try to forc e the
drain current to 12 mV/RSENSE or 50 mV/RSENSE,
respectively, until the TIMER block times out. If fold-
back current-limiting is not desired at all, set the divider
associate d with the CL pin t o detect t he desire d current
in order to shut off the GATE immediately.
A voltage on the GATE pin higher than about 8V is one
condition for the PWRGOOD pin to be asserted. Any
fault condition that causes the GATE pin voltage to be
pulled to VNEG deasserts the PWRGOOD pin. On
startup, a NMOS transistor with a resistor pulling its
gate up holds the GATE pin down until the MCP18480
is properly biased.
6.8.8 BIAS BLOCK
The intern al voltag e generation or b ias block ge nerates
the biasing currents for all internal blocks. It also pro-
vides a 2.5V reference voltage th at is brought out to the
VREFOUT pin. This output pin is usually fed back in to the
VREFIN pin. However, an externally-generated 2.5V
reference voltage may be directly connected to the
VREFIN pin, while leaving the VREFOUT pin uncon-
nected. A VREFIN/2 volt age is generated with in the bias
block, which is used as reference in the other blocks.
A internal shunt regulator limits the internal circuitry to
12V. An external current-limiting resistor in series with
VPOS absorbs the excess voltage. The resulting regu-
lated 12V source is used in the gate drive block and
PWRGOOD output circuit.
The 12V s ource is also st epped-d own to gen erate a 5V
regulate d sou rce . Most of the o ther c ircuit ry and bloc ks
operate with the internally-generated 5V.
EQUATION 6-10: EXTERNAL RISET
CURRENT
6.8.9 POWER GOOD BLOCK
The “power good” block monitors the state of the OV
active , the UV active, th e current l imit circuit ry, and out-
put of t he FE T goo d bl oc k to generate the PWRGOO D
output signal.
IRISET
VREFIN
2
------------------


RISET
------------------------=
Note: The direction of the current is depen-
dant on w here the ex ternal RISET resi s-
tor is connected (the ISET pin to either
the VNEG pin or the VREFIN pin).
MCP18480
DS20091C-page 48 2002-2012 Microchip Technology Inc.
NOTES:
2002-2012 Microchip Technology Inc. DS20091C-page 49
MCP18480
7.0 PACKAGING INFORMATION
7.1 Package Marking Information
Legend: XX...X Customer specific information*
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Note: In the event th e full Mi crochi p pa rt numbe r cannot be ma rked on on e line, it will
be carried ov er to the ne xt li ne thus lim iti ng th e nu mb er of av ai lab le c hara ct ers
for customer specific information.
*Standard marking cons ists of Microchip part number, year code, week code, and traceability code.
20-Lead SSOP Example:
XXXXXXXXXXX
XXXXXXXXXXX
YYWWNNN
MCP18480
I/SS
0348058
MCP18480
DS20091C-page 50 2002-2012 Microchip Technology Inc.
20-Lead Plasti c Shrink Small Outline (SS) – 209 mil, 5.30 mm (SSOP)
10501050
Mold Draft Angle Bottom 10501050
Mold Draft Angle Top 0.380.320.25.015.013.010BLead Width 203.20101.600.00840
Foot Angle 0.250.180.10.010.007.004
c
Lead Thickness 0.940.750.56.037.030.022LFoot Length 7.347.207.06.289.284.278DOverall Length 5.385.255.11.212.207.201E1Molded Package Width 8.187.857.59.322.309.299EOverall Width 0.250.150.05.010.006.002A1Standoff § 1.831.731.63.072.068.064
A2
Molded Package Thickness 1.981.851.73.078.073.068AOverall Height 0.65.026
p
Pitch 20
20
n
Number of Pins MAXNOMMINMAXNOMMINDimension Limits MILLIMETERSINCHES*Units
2
1
D
p
n
B
E
E1
L
c
A2
A
A1
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-150
Drawing No. C04-072
§ Significant Characteristic
Note: For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging
2002-2012 Microchip Technology Inc. DS20091C-page 51
MCP18480
APPENDIX A: REVISION HISTORY
Revision A
This is a new data sheet
Revision B
• Add device characterization information
• Enhanced functional description
Revision C
• Added note to the package outline drawing.
MCP18480
DS20091C-page 52 2002-2012 Microchip Technology Inc.
NOTES:
2002-2012 Microchip Technology Inc. DS20091C-page 53
MCP18480
APPENDIX B: MCP18480 SCHEMATICS
This appendix contains the schematics for the MCP18480 Evaluation Board.
MCP18480
DS20091C-page 54 2002-2012 Microchip Technology Inc.
FIGURE B-1: Typical Operating Circuit for Telcom Applications with Active-High Power Module - Foldback Current Limit Enabled.
MCP18480
+
RUV1
ROV2 RUV2
CUVD
RISET
CTIMER
RDISCH
RUVHYS
RPOS
CBYP2
RSENSE
ROVO1
ROVO2
RDRAIN1
RDRAIN2
RFB1
RFB2
CGD
RGD
RG1
CG1
QPG2
QPG3
RPG2
RPG6
M1
CBYPL
RBYPL
VNEG
RPG1 RPG5
4k
2µF 10nF
1.74 M453 k
280 k
59 k30.9 k
800 nF
124 k
680 nF
1.6 M
0.01
7.5 k
110 kMPSA43
100 nF 103.3 nF
18 k
680
36 k
36 k
1500
100 µF
51 k
2N5400
NTE261
124 k
115 k
59 k
1.74 M
1.6 M
1.74 M
NTE2388
RZ
24.9 k
5V RPG3
RPG4
QPG1
RESTART
ENABLE
PWRGOOD
VPOS
OVTH
UVTH
UVHYS
UVD
VREFIN
VREFOUT
CL
ISET
TIMER
OVO
DRAINTH
VFB
GATE
SENSE
VNEG
RDISCH
1
2
3
4
5
6
7
8
9
10 11
12
13
14
15
16
17
18
19
20
DC/DC
Converter
Module
VIN+
VIN-
VOUT+
VOUT-
ON/OFF
100 V
78V
Fuse 10A
GND
Transorb
CBYP1
ROV1 SRS
SEN
2002-2012 Microchip Technology Inc. DS20091C-page 55
MCP18480
FIGURE B-2: Typical Operating Circuit for Telcom Applications with Active-Low Power Module - Foldback Current Limit Enabled.
RISET
124 k
MCP18480
+
RUV1
ROV2 RUV2
CUVD
CTIMER
RDISCH
RUVHYS
RPOS
CBYP2
RSENSE
ROVO1
ROVO2
RDRAIN1
RDRAIN2
RFB1
RFB2
CGD
RGD
RG1
CG1
QPG2
QPG3
RPG2
RPG6
M1
CBYPL
RBYPL
VNEGA 1
RPG1 RPG5
4k
2µF 10nF
1.74 M453 k
280 k
59 k30.9 k
800 nF
680 nF
1.6 M
0.01
7.5 k
110 kMPSA43
100 nF 103.3 nF
18 k
680
36 k
36 k
1500
100 µF
51 k
2N5400
NTE261
124 k
115 k
59 k
1.74 M
1.6 M
1.74 M
NTE2388
RZ
24.9 k
5V RPG3
RPG4
QPG1
RESTART
ENABLE
PWRGOOD
VPOS
OVTH
UVTH
UVHYS
UVD
VREFIN
VREFOUT
CL
ISET
TIMER
OVO
DRAINTH
VFB
GATE
SENSE
VNEG
RDISCH
1
2
3
4
5
6
7
8
9
10 11
12
13
14
15
16
17
18
19
20
DC/DC
Converter
Module
VIN+
VIN-
VOUT+
VOUT-
ON/OFF
100 V
78V
Fuse 10A
GND
Transorb
CBYP1
ROV1 SRS
SEN
MCP18480
DS20091C-page 56 2002-2012 Microchip Technology Inc.
FIGURE B-3: Evaluation Board Schematic (Active-Low Power Module - Foldback Current Limit Enabled).
MCP18480
+
RUV1
ROV1
ROV2 RUV2
CUVD
RISET
CTIMER
RDISCH
RUVHYS
RPOS
CBYP1 CBYP2
RSENSE
ROVO1
ROVO2
RDRAIN1
RDRAIN2
RFB1
RFB2
CGD
RGD
RG1
CG1
QPG2
QPG3
RPG2
RPG6
M1
CBYPL
VNEG
RPG1 RPG5
RLOAD
SRS
SEN
4k
2µF 10nF
1.74 M453 k
280 k
59 k30.9 k
800 nF
124 k
680 nF
1.6 M
0.01
7.5 k
110 kMPSA43
100 nF 103.3 nF
18 k
680
36 k
36 k
1500
75
100 µF
2N5400
NTE261
124 k
115 k
59 k
1.74 M
1.6 M
1.74 M
NTE2388
RZ24.9 k
5V RPG3
RPG4
QPG1
RESTART
ENABLE
PWRGOOD
VPOS
OVTH
UVTH
UVHYS
UVD
VREFIN
VREFOUT
CL
ISET
TIMER
OVO
DRAINTH
VFB
GATE
SENS
VNEG
RDISCH
1
2
3
4
5
6
7
8
9
10 11
12
13
14
15
16
17
18
19
20
RBYPL
51 k
2002-2012 Microchip Technology Inc. DS20091C-page 57
MCP18480
FIGURE B-4: Evaluation Board Schematic (Active-High Power Module - Foldback Current Limit Enabled).
RISET
124 k
MCP18480
+
RUV1
ROV1
ROV2 RUV2
CUVD
CTIMER
RDISCH
RUVHYS
RPOS
CBYP1 CBYP2
RSENSE
ROVO1
ROVO2
RDRAIN1
RDRAIN2
RFB1
RFB2
CGD
RGD
RG1
CG1
QPG2
QPG3
RPG2
RPG6
M1
CBYPL
VNEG
RPG1 RPG5
RLOAD
SRS
SEN
4k
2µF 10nF
1.74 M453 k
280 k
59 k30.9 k
800 nF
680 nF
1.6 M
0.01
7.5 k
110 kMPSA43
100 nF 103.3 nF
18 k
680
36 k
36 k
1500
75
100 µF
2N5400
NTE261
124 k
115 k
59 k
1.74 M
1.6 M
1.74 M
NTE2388
RZ24.9 k
5V RPG3
RPG4
QPG1
RESTART
ENABLE
PWRGOOD
VPOS
OVTH
UVTH
UVHYS
UVD
VREFIN
VREFOUT
CL
ISET
TIMER
OVO
DRAINTH
VFB
GATE
SENS
VNEG
RDISCH
1
2
3
4
5
6
7
8
9
10 11
12
13
14
15
16
17
18
19
20
RBYPL
51 k
MCP18480
DS20091C-page 58 2002-2012 Microchip Technology Inc.
FIGURE B-5: Evaluation Board Schematic (Active-Low Power Module - Circuit Breaker Current Limit Enabled).
RCL1 (Note)
210 k
RCL2 (Note)
40.2 k
MCP18480
+
RUV1
ROV1
ROV2 RUV2
CUVD
RISET
CTIMER
RDISCH
RUVHYS
RPOS
CBYP1 CBYP2
RSENSE
ROVO1
ROVO2
RDRAIN1
RDRAIN2
CGD
RGD
RG1
CG1
QPG2
QPG3
RPG2
RPG6
M1
CBYPL
VNEG
RPG1 RPG5
RLOAD
SRS
SEN
4k
2µF 10nF
1.74 M453 k
280 k
59 k30.9 k
800 nF
124 k
680 nF
1.6 M
0.01
7.5 k
110 kMPSA43
100 nF 103.3 nF
18 k
680
36 k
36 k
1500
75
100 µF
2N5400
NTE261
115 k
59 k
1.6 M
1.74 M
NTE2388
RZ24.9 k
5V RPG3
RPG4
QPG1
RESTART
ENABLE
PWRGOOD
VPOS
OVTH
UVTH
UVHYS
UVD
VREFIN
VREFOUT
CL
ISET
TIMER
OVO
DRAINTH
VFB
GATE
SENS
VNEG
RDISCH
1
2
3
4
5
6
7
8
9
10 11
12
13
14
15
16
17
18
19
20
RBYPL
51 k
2002-2012 Microchip Technology Inc. DS20091C-page 59
MCP18480
FIGURE B-6: Evaluation Board Schematic (Active-High Power Module - Circuit Breaker Current Limit Enabled).
RISET
124 k
RCL1 (Note )
210 k
RCL2 (Note)
40.2 k
MCP18480
+
RUV1
ROV1
ROV2 RUV2
CUVD
CTIMER
RDISCH
RUVHYS
RPOS
CBYP1 CBYP2
RSENSE
ROVO1
ROVO2
RDRAIN1
RDRAIN2
CGD
RGD
RG1
CG1
QPG2
QPG3
RPG2
RPG6
M1
CBYPL
VNEG
RPG1 RPG5
RLOAD
SRS
SEN
4k
2µF 10nF
1.74 M453 k
280 k
59 k30.9 k
800 nF
680 nF
1.6 M
0.01
7.5 k
110 kMPSA43
100 nF 103.3 nF
18 k
680
36 k
36 k
1500
75
100 µF
2N5400
NTE261
115 k
59 k
1.6 M
1.74 M
NTE2388
RZ24.9 k
5V RPG3
RPG4
QPG1
RESTART
ENABLE
PWRGOOD
VPOS
OVTH
UVTH
UVHYS
UVD
VREFIN
VREFOUT
CL
ISET
TIMER
OVO
DRAINTH
VFB
GATE
SENS
VNEG
RDISCH
1
2
3
4
5
6
7
8
9
10 11
12
13
14
15
16
17
18
19
20
RBYPL
51 k
MCP18480
DS20091C-page 60 2002-2012 Microchip Technology Inc.
NOTES:
2002-2012 Microchip Technology Inc. DS20091C-page 61
MCP18480
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Sales and Support
PART NO. X/XX
PackageTemperature
Range
Device
Device MCP18480: -48V Hot Swap Controller
MCP18480T: -48V Hot Swap Controller
(Tape and Ree l)
Temperature Range I = -40°C to +85°C
Package SS = Plastic SSOP (209 mil, Body), 20-lead
Examples:
a) MCP18480-I/SS = Industrial Temp.,
SSOP package
b) MCP18480T-I/SS = Tape and Reel,
Indust rial Temp., SSOP package
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-
mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the fo llowing:
1. Your local Microc hip sales office
2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277
3. The Microchip Wor ldwide Site (www.micr ochip.c om)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
MCP18480
DS20091C-page 62 2002-2012 Microchip Technology Inc.
NOTES:
2002-2012 Microchip Technology Inc. DS20091C-page 63
Information contained in this publication regarding device
applications a nd the lik e is provided only f or yo ur convenience
and may be supers ed ed by u pda t es . It is y our responsibil it y to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
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arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTA RT, PI C32 logo, rfPIC, SST, SST Logo, SuperFlash
and UNI/O are registered trademarks of Microchip T echnology
Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MTP, SEEVAL and The Em bedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
Analog-for-the-Digital Age, Application Maestro, BodyCom,
chipKIT, chipKIT logo, CodeGuard, dsPICDEM ,
dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONIT OR, FanSense, HI-TIDE, In-Circuit Serial
Programm ing, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,
Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA
and Z-Scale are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip T echnology Incorporated
in the U.S.A.
GestIC and ULPP are registered trademarks of Microchip
Tec hnolo gy Germ any II GmbH & Co . & KG, a subsidiary of
Microchip Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2002-2012, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 9781620767283
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that it s family of products is one of the most secure families of it s kind on the market t oday, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is c onstantly evolving. We a t Microc hip are co m mitted to continuously improving the code prot ect ion featur es of our
products. Attempts to break Microchip’ s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperiph erals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITY MANAGEMENT S
YSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
DS20091C-page 64 2002-2012 Microchip Technology Inc.
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Worldwide Sales and Service
10/26/12