CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
3.3V 4K/8K/16K x 16/18 Dual-Port
Static RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose
,
CA 95134-1709 • 408-943-2600
Document #: 38-06052 Rev. *J Revised December 10, 2008
Features
■
True dual-ported memory cells which enable si multaneous
access of the same memory location
■
4, 8 or 16K × 16 organization
■
(CY7C024AV/024BV
[1]
/ 025AV/026AV)
■
4 or 8K × 18 organization (CY7C0241AV/0251AV)
■
16K × 18 organization (CY7C036AV)
■
0.35 micron CMOS for optimum speed and power
■
High speed access: 20 and 25 ns
■
Low operating power
❐
Active: I
CC
= 115 mA (typical)
❐
Standby: I
SB3
= 10 μA (typical)
■
Fully asynchronous operation
■
Automatic power down
■
Expandable data bus to 32 bits, 36 bits or more using Master
and Slave chip select when using more than one device
■
On chip arbitration logic
■
Semaphores included to permit software handshaking
between ports
■
INT flag for port-to-port communication
■
Separate upper byte and lower byte control
■
Pin select for Master or Slave (M/S)
■
Commercial and industrial temp erature ranges
■
Available in 100-pin Pb-free TQFP and 100-pin TQFP
Notes
1. CY7C024AV and CY7C024BV are functionally identical.
2. IO
8
–IO
15
for x16 devices; IO
9
–IO
17
for x18 devices.
3. IO
0
–IO
7
for x16 devices; IO
0
–IO
8
for x18 devices.
4. A
0
–A
11
for 4K devices; A
0
–A
12
for 8K devices; A
0
–A
13
for 16K devices.
5. BUSY is an output in master mode and an input in slave mode.
R/W
L
OE
L
IO
8/9L
–IO
15/17L
IO
Control
Address
Decode
A
0L
–A
11/12/13L
CE
L
OE
L
R/W
L
BUSY
L
IO
Control
CE
L
Interrupt
Semaphore
Arbitration
SEM
L
INT
L
M/S
UB
L
LB
L
IO
0L
–IO
7/8L
R/W
R
OE
R
IO
8/9L
–IO
15/17R
CE
R
UB
R
LB
R
IO
0L
–IO
7/8R
UB
L
LB
L
A
0L
–A
11/1213L
T rue Dual-Ported
RAM Array
A
0R
–A
11/12/13R
CE
R
OE
R
R/W
R
BUSY
R
SEM
R
INT
R
UB
R
LB
R
Address
Decode A
0R
–A
11/12/13R
[2] [2]
[3] [3]
[5] [5]
12/13/14
8/9
8/9
12/13/14
8/9
8/9
12/13/14 12/13/14
[4]
[4]
[4]
[4]
Logic Block Diagram
[+] Feedback
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
Document #: 38-06052 Rev. *J Page 2 of 19
Pin Configurations
Figure 1. 100- P in TQ FP (Top View)
Notes
6. A
12L
on the CY7C025AV.
7. A
12R
on the CY7C025AV.
100 99 9798 96
2
3
1
4241
59
60
61
12
13
15
14
16
4
5
40
39
95 94
17
26
9
10
8
7
6
11
27 28 3029 31 32 3534 36 37 3833
67
66
64
65
63
62
68
69
70
75
73
74
72
71
89 88 8687 8593 92 84
NC
NC
NC
NC
A
5L
A
4L
INT
L
A
2L
A
0L
BUSY
L
GND
INT
R
A
0R
A
1L
NC
NC
NC
NC
IO
10L
IO
11L
IO
15L
V
CC
GND
IO
1R
IO
2R
V
CC
9091
A
3L
M/S
BUSY
R
IO
14L
GND
IO
12L
IO
13L
A
1R
A
2R
A
3R
A
4R
NC
NC
NC
NC
IO
3R
IO
4R
IO
5R
IO
6R
NC
NC
NC
NC
18
19
20
21
22
23
24
25
83 82 81 80 79 78 77 76
58
57
56
55
54
53
52
51
43 44 45 46 4748 49 50
IO
9L
IO
8L
IO
7L
IO
6L
IO
5L
IO
4L
IO
3L
IO
2L
GND
IO
1L
IO
0L
OE
L
SEM
L
V
CC
CE
L
UB
L
LB
L
NC
A
11L
A
10L
A
9L
A
8L
A
7L
A
6L
IO
0R
IO
7R
IO
8R
IO
9R
IO
10R
IO
11R
IO
12R
IO
13R
IO
14R
GND
IO
15R
Œ
R
R\W
R
GND
SEM
R
CE
R
UB
R
LB
R
NC
A
11R
A
10R
A
9R
A
8R
A
7R
A
6R
A
5R
CY7C024AV/024BV (4K × 16)
R/
W
L
[6]
[7]
CY7C025AV (8K × 16)
[+] Feedback
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
Document #: 38-06052 Rev. *J Page 3 of 19
Figure 2. 100- P in TQ FP (Top View)
Notes
8. A
12L
on the CY7C0251AV.
9. A
12R
on the CY7C0251AVC.
Pin Configurations
(continued)
100 99 9798 96
2
3
1
4241
59
60
61
12
13
15
14
16
4
5
40
39
95 94
17
26
9
10
8
7
6
11
27 28 3029 31 32 3534 36 37 3833
67
66
64
65
63
62
68
69
70
75
73
74
72
71
89 88 8687 8593 92 84
NC
NC
NC
NC
A
5L
A
4L
INT
L
A
2L
A
0L
BUSY
L
GND
INT
R
A
0R
A
1L
NC
NC
IO
11L
IO
12L
IO
16L
V
CC
GND
IO
1R
IO
2R
V
CC
9091
A
3L
M/
S
BUSY
R
IO
15L
GND
IO
13L
IO
14L
A
1R
A
2R
A
3R
A
4R
NC
NC
NC
NC
IO
3R
IO
4R
IO
5R
IO
6R
NC
NC
18
19
20
21
22
23
24
25
83 82 81 80 79 78 77 76
58
57
56
55
54
53
52
51
43 44 45 46 47 48 49 50
IO
9L
IO
7L
IO
6L
IO
5L
IO
4L
IO
3L
IO
2L
IO
10L
GND
IO
1L
IO
0L
OE
L
SEM
L
V
CC
CE
L
UB
L
LB
L
NC
A
11L
A
10L
A
9L
A
8L
A
7L
A
6L
IO
0R
IO
7R
IO
16R
IO
9R
IO
10R
IO
11R
IO
12R
IO
13R
IO
14R
GND
IO
15R
OE
R
R/
W
R
GND
SEM
R
CE
R
UB
R
LB
R
NC
A
11R
A
10R
A
9R
A
8R
A
7R
A
6R
A
5R
CY7C0241AV (4K × 18)
IO
8L
IO
17L
IO
8R
IO
17R
R/
W
L
[9] [8]
1
3
2
92 91 90 848587 868889 83 82 81 7678 77798093949596979899100
59
60
61
67
66
64
65
63
62
68
69
70
75
73
74
72
71
NC
NC
NC
A6L
A5L
A4L
INT
L
A2L
A0L
GND
M/
S
A0R
A1R
A1L
A3L
BUSY
R
INT
R
A2R
A3R
A4R
A5R
NC
NC
NC
BUSY
L
58
57
56
55
54
53
52
51
CY7C026AV (16K × 16)
NC
NC
NC
NC
IO10L
IO11L
IO15L
IO13L
IO14L
GND
IO0R
VCC
IO3R
GND
IO12L
IO1R
IO2R
IO4R
IO5R
IO6R
NC
NC
NC
NC
VCC
17
16
15
9
10
12
11
13
14
8
7
6
4
5
18
19
20
21
22
23
24
25
IO9L
IO8L
IO7L
IO6L
IO5L
IO4L
IO0L
IO2L
IO1L
VCC
R/
WL
UB
L
LB
L
GND
IO3L
SEM
L
CE
L
A13L
A12L
A11L
A10L
A9L
A8L
A7L
OE
L
34 35 36 424139 403837 43 44 45 5048 494746
A6R
A7R
A8R
A9R
A10R
A11R
CE
R
A13R
UB
R
GND
R/
WR
GND
IO14R
LB
R
A12R
OE
R
IO15R
IO13R
IO12R
IO11R
IO10R
IO9R
IO8R
IO7R
SEM
R
3332313029282726
CY7C0251AV (8K × 18)
[+] Feedback
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
Document #: 38-06052 Rev. *J Page 4 of 19
Figure 3. 100- P in TQ FP (Top View)
Pin Configurations
(continued)
100 99 9798 96
2
3
1
4241
59
60
61
12
13
15
14
16
4
5
4039
95 94
17
26
9
10
8
7
6
11
27 28 3029 31 32 3534 36 37 3833
67
66
64
65
63
62
68
69
70
75
73
74
72
71
89 88 8687 8593 92 84
NC
NC
NC
A
5L
A
4L
INT
L
A
2L
A
0L
BUSY
L
GND
INT
R
A
0R
A
1L
NC
NC
IO
11L
IO
12L
IO
16L
V
CC
GND
IO
1R
IO
2R
V
CC
9091
A
3L
M/S
BUSY
R
IO
15L
GND
IO
13L
IO
14L
A
1R
A
2R
A
3R
A
4R
NC
NC
NC
IO
3R
IO
4R
IO
5R
IO
6R
NC
NC
18
19
20
21
22
23
24
25
83 82 81 80 79 78 77 76
58
57
56
55
54
53
52
51
43 44 45 46 4748 49 50
IO
9L
IO
7L
IO
6L
IO
5L
IO
4L
IO
3L
IO
2L
IO
10L
GND
IO
1L
IO
0L
OE
L
SEM
L
V
CC
CE
L
UB
L
LB
L
A
11L
A
10L
A
9L
A
8L
A
7L
A
6L
IO
0R
IO
7R
IO
16R
IO
9R
IO
10R
IO
11R
IO
12R
IO
13R
IO
14R
GND
IO
15R
OE
R
R/W
R
GND
SEM
R
CE
R
UB
R
LB
R
A
11R
A
10R
A
9R
A
8R
A
7R
A
6R
A
5R
IO
8L
IO
17L
IO
8R
IO
17R
R/W
L
CY7C036AV (16K × 18)
A
13L
A
13R
A
12L
A
12R
Selection Guide
Parameter CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
-20
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
-25 Unit
Maximum Access T i me 20 25 ns
Typical Operating Current 120 115 mA
Typical S tandby Current for I
SB1
(Both ports TTL Level) 35 30 mA
Typical S tandby Current for I
SB3
(Both ports CMOS Level) 10 10 μA
[+] Feedback
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
Document #: 38-06052 Rev. *J Page 5 of 19
Architecture
The CY7C024AV/024BV/025AV/026AV and
CY7C0241AV/0251AV/036AV consist of an array of 4K, 8K, and
16K words of 16 and 18 bits each of dual-port RAM cells, IO and
address lines, and control signals (CE, OE, RW). These control pins
permit independent access for reads or writes to any location in
memory. To handle simultaneous writes and reads to the same
location, a BUSY pin is provided on each port. Two Interrupt (INT)
pins can be u sed for port to port communication. Two Semaphore
(SEM) control pins are used for allocating shared resources. With
the M/S pin, the devices can function as a master (BUSY pin s a re
outputs) or as a slave (BUSY pins are inputs). They also have an
automatic power down feature contro lled by CE . Each port has its
own output enable control (OE), which enables data to be read from
the device.
Functional Description
The CY7C024AV/024BV/025AV/026AV and
CY7C0241AV/0251AV/036AV are low power CMOS 4K, 8K, and
16K ×16/18 dual port static RAMs. Various arbitration schemes are
included on the devices to handle situations when multiple
processors access the same piece of data. There are two ports
permitting independent, asynchronous access for reads and writes
to any location in memory . The devices can be used as standalone
16 or18-bit dual port static RAMs or multiple devices can be
combined to function as a 32 or 36-bit or wider master and slave
dual port static RAM. An M/S pin is provided for implementing 32 or
36-bit or wider memory applications. It does not need separate
master and slave devices or additional discrete logic. Application
areas include interprocessor/multiprocessor designs, communica-
tions status buffering, and dual port video and graphics memory.
Each port has independent control pins: Chip Enable (CE), Read
or Write Enable (R/W), and Output Enable (OE ). Two flags are
provided on ea ch port (BUSY and INT). BUSY signals that the
port is trying to access the same location currently being
accessed by the other port. The Interrupt flag (INT) permits
communication between ports or systems by means of a mail
box. The semaphores are used to pass a flag, or token, from one
port to the other to indicate that a shared resource is in use. The
semaphore logic has eight shared latches. Only one side can
control the latch (semaphore) at any time. Control of a
semaphore indicates that a shared resource is in use. An
automatic power down feature is controlled independently on
each port by a Chip Select (CE) pin.
The CY7C024AV/024BV/025AV/026AV and
CY7C0241AV0251AV/036AV are available in 100-pin Pb-free Thin
Quad Flat Pack (TQFP) and 100-pin TQFP.
Write Operation
Data must be set up for a duration of t
SD
before the rising edge
of RW to guarantee a valid write. A write operation is controlled
by either the R W pin (see Figure 8 on page 12) or the CE pin (see
Figure 9 on p age 12). Required inputs for non-contention opera-
tions are summarized in Table 1 on page 7.
If a location is being written to by one port and the opposite port
tries to read that location, there must be a port to port flowthrough
delay before the data is read on the output; otherwise the data
read is not deterministic. Data is valid o n the port t
DDD
after the
data is presented on the other port.
Read Operation
When reading the device, the user must assert both the OE and
CE pins. Data is available t
ACE
after CE or t
DOE
after OE is
asserted. If the user wants to access a semaphore flag, then the
SEM pin and OE must be asserted.
Interrupts
The upper two me mory locations are for messa ge passing. The
highest memory location (FFF for the
CY7C024AV/024BV/41AV/1FFF for the CY7C025AV/51AV,
Pin Definitions
Left Port Right Port Description
CE
L
CE
R
Chip Enable
R/W
L
R/W
R
Read and Write Enable
OE
L
OE
R
Output Enable
A
0L
–A
13L
A
0R
–A
13R
Address (A
0
–A
11
for 4K devices; A
0
–A
12
for 8K devices; A
0
–A
13
for 16K)
IO
0L
–IO
17L
IO
0R
–IO
17R
Data Bus Input and Output
SEM
L
SEM
R
Semaphore Enab l e
UB
L
UB
R
Upper Byte Select (IO
8
–IO
15
for x16 devices; IO
9
–IO
17
for x18 devices)
LB
L
LB
R
Lower Byte Select (IO
0
–IO
7
for x16 devices; IO
0
–IO
8
for x18 devices)
INT
L
INT
R
Interrupt Flag
BUSY
L
BUSY
R
Busy Flag
M/S Master or Slave Select
V
CC
Power
GND Ground
NC No Connect
[+] Feedback
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
Document #: 38-06052 Rev. *J Page 6 of 19
3FFF for the CY7C026AV/36AV) is the mailbox for the right port
and the second highest memory location (FFE for the
CY7C024AV/024BV/41AV/1FFE for the CY7C025AV/51AV,
3FFE for the CY7C02 6AV/36AV) is the mailb ox for the left port.
When one port writes to the ot her port’s mailbox, an inte rrupt is
generated to the owner. The interrupt is reset when the owner
reads the contents of the mailbox. The message is user defined.
Each port can read the other port’s mailbox without resetting the
interrupt. The active state of the busy signal (to a port) prevents
the port from setting the interrupt to the winning port. Also, an
active busy to a port prevents that port from reading its own
mailbox and, thus, resetting th e interrupt to it.
If an application does not require message passing, do not
connect the interrupt pin to the processor’s interrupt request
input pin.
The operation of the interrupts and their interaction with Busy are
summarized in Table 2 on page 7.
Busy
The CY7C024AV/024BV/025AV/026AV and
CY7C0241A V/0251A V/036A V provide on-chip arbitration to resolve
simultaneous memory location access (contention). If both ports’
CEs are asserted and an address match occurs within t
PS
of each
other, the busy logic determines which port has access. If t
PS
is
violated, one port definitely gains permission to the location, but it is
not predictable which port gets that permission. BUSY is asserted
t
BLA
after an address match or t
BLC
after CE is taken LOW .
Master/Slave
A M/S pin helps to expand the word width by configuring the
device as a master or a slave. The BUSY output of the master is
connected to the BUSY input of the slave. This enables the
device to interface to a master device with no external compo-
nents. Writing to slave devices must be delayed until after the
BUSY input has settled (t
BLC
or t
BLA
). Otherwise, the slave chip
may begin a write cycle during a contention situation. When tied
HIGH, the M/S pin enables the device to be used as a master
and, therefore, the BUSY line is an output. BUSY can then be
used to send the arbitration outcome to a slave.
Semaphore Operation
The CY7C024AV/024BV/025AV/026AV and
CY7C0241AV/0251AV/036AV provide eight semaphore latches,
which are separate from the dual port memory locations.
Semaphores are used to reserve resources that are shared
between the two ports. The state of the semaphore indicates that
a resource is in use. For example, if the left port wants to request
a given resource, it sets a latch by writing a zero to a semaphore
location. The left port then verifies its success in setting the latch
by reading it. After writing to the semaphore, SEM or OE must
be deasserted for t
SOP
before attempting to read the semaphore.
The semaphore value is available t
SWRD
+ t
DOE
after the rising
edge of the semaphore write. If the left port was successful
(reads a zero), it assumes control of the shared resource.
Otherwise (reads a one), it assumes the right port has control
and continues to poll the semaphore. When the right side has
relinquished control of the semaphore (by writing a one), the left
side succeeds in gaining control of the semaphore. If the left side
no longer requires the semapho re, a one is written to cancel its
request.
Semaphores are accessed by asserting SEM LOW. The SEM
pin functions as a chip select for the semaphore latches (CE
must remain HIGH during SEM LOW). A
0–2
represents the
semaphore address. OE and RW are used in the same manne r
as a normal memory access. When writing or reading a
semaphore, the other address pins have no effect.
When writing to the semaphore, only IO
0
is used. If a zero is
written to the left port of an available semaphore, a one appears
at the same semaphore address on the right port. That
semaphore can now only be modi fied by the side showing zero
(the left port in this case). If the left port now relinquishes control
by writing a one to the semapho re, the semaphore is set to one
for both sides. However, if the right port had requested the
semaphore (written a zero) while the left port had control, the
right port would immediately own the semaphore as soon as the
left port released it. Table 3 on page 7 shows sample semaphore
operations.
When reading a semapho re, all 16 and 18 data lines output the
semaphore value. The read value is latched in an output register
to prevent the semaphore from changing state during a write
from the other port. If both ports attempt to access the
semaphore within t
SPS
of each other , the semaphore is definitely
obtained by one of them. But there is no guarantee which side
controls the semaphore.
[+] Feedback
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
Document #: 38-06052 Rev. *J Page 7 of 19
Table 1. Non-Contending Read/Write
Inputs Outputs Operation
CE R/W OE UB LB SEM IO
9
–IO
17
IO
0
–IO
8
H X X X X H High Z High Z Deselected: Power Down
X X X H H H High Z High Z Deselected: Power Down
L L X L H H Data In High Z Write to Upper Byte Only
L L X H L H High Z Data In Write to Lower Byte Only
L L X L L H Data In Data In Write to Both Bytes
L H L L H H Data Out High Z Read Up pe r Byte Only
L H L H L H High Z Data Out Read Lower Byte Only
L H L L L H Data Out Data Out Read Both Bytes
X X H X X X High Z High Z Outputs Disabled
H H L X X L Data Out Data Out Read Data in Semaphore Flag
X H L H H L Data Out Data Out Read Data in Semaphore Flag
H X X X L Data In Data In Write D
IN0
into Semaphore Flag
X X H H L Data In Data In Write D
IN0
into Semaphore Flag
L X X L X L Not Allowed
L X X X L L Not Allowed
Table 2. Interrupt Operation Example (assumes BUSY
L
= BUSY
R
= HIGH)
[10]
Left Port Right Port
Function R/W
L
CE
L
OE
L
A
0L–13L
INT
L
R/W
R
CE
R
OE
R
A
0R–13R
INT
R
Set Right INT
R
Flag L L X FFF
[13]
XXXX X L
[12]
Reset Right INT
R
Flag X X X X X X L L FFF (or 1/3FFF) H
[11]
Set Left INT
L
Flag XXX X L
[11]
L L X 1FFE (or 1/3FFE) X
Reset Left INT
L
Flag X L L 1FFE
[13]
H
[12]
XXX X X
Table 3. Semaphore Operation Example
Function IO
0
–IO
17
Left IO
0
–IO
17
Right Status
No action 1 1 Semaphore-free
Left port writes 0 to semaphore 0 1 Left Port has semaphore token
Right port writes 0 to semaphore 0 1 No change. Right side has no write access to semaphore
Left port writes 1 to semaphore 1 0 Right port obtains semaphore token
Left port writes 0 to semaphore 1 0 No change. Left port has no write access to semaphore
Right port writes 1 to semaphore 0 1 Left port obtains semaphore token
Left port writes 1 to semaphore 1 1 Semaphore-free
Right port writes 0 to semaphore 1 0 Right port has semaphore token
Right port writes 1 to semaphore 1 1 Semaphore free
Left port writes 0 to semaphore 0 1 Left port has semaphore token
Left port writes 1 to semaphore 1 1 Semaphore-free
Notes
10.See Functional Description on page 5 for specific highest memory locations by device.
1 1. If BUSY
R
=L, then no chan ge.
12.If BUSY
L
=L, then no change.
13.See Functional Description on page 5 for specific addresses by device.
[+] Feedback
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
Document #: 38-06052 Rev. *J Page 8 of 19
Maximum Ratings
Exceeding maximum ratings
[14]
may shorten the useful life of the
device. User guidelines are not te sted.
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied ............................................–55°C to +125°C
Supply Voltage to Ground Potential............... –0.5V to +4.6V
DC Voltage Applied to
Outputs in High-Z State .........................–0.5V to V
CC
+ 0.5V
DC Input Voltage
[15]
...............................–0.5V to V
CC
+ 0.5V
Output Current into Output s (LO W).............. ... ............20 mA
Static Discharge Voltage.......................................... > 2001V
Latch-up Current.................................................... > 200 mA
Operating Range
Range Ambient Temperature V
CC
Commercial 0°C to +70°C 3.3V ± 300 mV
Industrial
[16]
–40°C to +85°C 3.3V ± 300 mV
Electrical Characteristics
Over the Operating Range
Parameter Description
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV Unit
-20 -25
Min Typ Max Min Typ Max
V
OH
Output HIGH Voltage (V
CC
=3.3V) 2.4 2.4 V
V
OL
Output LOW Voltage 0.4 0.4 V
V
IH
Input HIGH Voltage 2.0 2.0 V
V
IL
Input LOW Voltage –0.3
[17]
0.8 0.8 V
I
OZ
Output Leakage Current –10 10 –10 10 μA
I
IX
Input Leakage Current –10 10 –10 10 μA
I
CC
Operating Current (V
CC
= Max.,
I
OUT
= 0 mA) Outputs Disabled Com’l. 120 175 115 165 mA
Ind.
[16]
135 185 mA
I
SB1
Standby Curre nt (Both Ports TTL Level)
CE
L
& CE
R
≥ V
IH
, f = f
MAX
Com’l. 35 45 30 40 mA
Ind.
[16]
40 50 mA
I
SB2
Standby Current (One Port TTL Level)
CE
L
| CE
R
≥ V
IH
, f = f
MAX
Com’l. 75 110 65 95 mA
Ind.
[16]
75 105 mA
I
SB3
Standby Current (Both Ports CMOS Level)
CE
L
& CE
R
≥ V
CC
−0.2V, f = 0 Com’l. 10 500 10 500 μA
Ind.
[16]
10 500 μA
I
SB4
Standby Current (One Port CMOS Level)
CE
L
| CE
R
≥ V
IH
, f = f
MAX[18]
Com’l. 70 95 60 80 mA
Ind.
[16]
70 90 mA
Capacitance
Parameter
[19]
Description Test Conditions Max Unit
C
IN
Input Capacitance T
A
= 25
°
C, f = 1 MHz,
V
CC
= 3.3V 10 pF
C
OUT
Output Capacitance 10 pF
Notes
14.The voltage on any input or IO pin cannot exceed the power pin during power up.
15.Pulse width < 20 ns.
16.Industrial parts are available in CY7C026AV and CY7C036AV only.
17.VIL > –1.5V for pulse width less than 10ns.
18.f
MAX
= 1/t
RC
= All inputs cycling at f = 1/t
RC
(except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level
standb y I
SB3
.
19.Tested initially and after any design or process changes that may affect t hese parameters.
[+] Feedback
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
Document #: 38-06052 Rev. *J Page 9 of 19
Figure 4. AC Test Load s an d Waveforms
3.0V
GND 90% 90%
10%
3ns 3ns
10%
ALL INPUTPULSES
(a) Normal Load (Load 1)
R1 = 590Ω
3.3V
OUTPUT
R2 = 435Ω
C= 30pF
V
TH
=1.4V
OUTPUT
C= 30pF
(b) Thévenin Equivalent (Load 1) (c) Three-State Delay (Load 2)
R1 = 590Ω
R2 = 435Ω
3.3V
OUTPUT
C= 5pF
R
TH
= 250Ω
≤≤
including scope and jig)
(Used for t
LZ
, t
HZ
, t
HZWE
, and t
LZWE
Switching Characteristics
Over the Operating Range
[20]
Parameter Description
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV Unit
-20 -25
Min Max Min Max
Read Cycle
t
RC
Read Cycle Time 20 25 ns
t
AA
Address to Data Valid 20 25 ns
t
OHA
Output Hold From Address Change 3 3 ns
t
ACE[21]
CE LOW to Data Valid 20 25 ns
t
DOE
OE LOW to Data Valid 12 13 ns
t
LZOE[22, 23, 24]
OE Low to Low Z 3 3 ns
t
HZOE[22, 23, 24]
OE HIGH to High Z 12 15 ns
t
LZCE[22, 23, 24]
CE LOW to Low Z 3 3 ns
t
HZCE[22, 23, 24]
CE HIGH to High Z 12 15 ns
t
PU[24]
CE LOW to Power Up 0 0 ns
t
PD[24]
CE HIGH to Power Down 20 25 ns
t
ABE[21]
Byte Enable Access Time 20 25 ns
Write Cycle
t
WC
Write Cycle Time 20 25 ns
t
SCE[21]
CE LOW to Write End 15 20 ns
t
AW
Address Valid to Write End 15 20 ns
t
HA
Address Hold From Write End 0 0 ns
t
SA[21]
Address Setup to Write Start 0 0 ns
Notes
20.Test conditio ns assume signal transiti on time of 3 ns or less, timi ng reference leve ls of 1.5V, input pulse levels of 0 to 3.0V, and output loa ding of the spe ci fie d I
OI
/I
OH
and 30 pF load capacitance.
21.To access RAM, CE = L, UB = L, SEM = H . To access semaphore, CE = H an d SEM = L. Either condition must be valid for the entire t
SCE
time.
22.At any given temperature and voltage condition for any gi ven device, t
HZCE
is less than t
LZCE
and t
HZOE
is less than t
LZOE
.
23.Test conditions used are Load 3.
24.This parameter is guaranteed but not tested. For information on port to port delay through RAM cells from writing port to reading port, refer to Figure 12.
[+] Feedback
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
Document #: 38-06052 Rev. *J Page 10 of 19
Data Retention Mode
The CY7C024AV/024BV/025AV/026AV and
CY7C0241AV/0251AV/036AV are designed for battery backup.
Data retention voltage and supply current are guaranteed over
temperature. The following rules ensure data retention:
1. Chip Enable (CE) must be held HIGH during data retention,
within V
CC
to V
CC
– 0.2V.
2. CE must be kept between V
CC
– 0.2V and 70 percent of V
CC
during the power up and power down transitions.
3. The RAM can begin operation >t
RC
after V
CC
reaches the
minimum operating voltage (3.0V).
Notes
25.For information on port to port delay through RAM cells from writing port to reading port, refer to Figure 12.
26.Test conditions used are Load 2.
27.t
BDD
is a calculated paramet er and is the greater of t
WDD
– t
PWE
(actual) or t
DDD
– t
SD
(actual).
28.CE = V
CC
, V
in
= GND to V
CC
, T
A
= 25°C. This parameter is guaranteed but not tested.
t
PWE
Write Pulse Width 15 20 ns
t
SD
Data Setu p to Write End 15 15 ns
t
HD
Data Hold From Write End 0 0 ns
t
HZWE[23, 24 ]
R/W LOW to High Z 12 15 ns
t
LZWE[23, 24]
R/W HIGH to Low Z 3 0 ns
t
WDD[25]
Write Pulse to Data Delay 45 50 ns
t
DDD[25]
Write Data Valid to Read Data Valid 30 35 ns
Busy Timing
[26]
t
BLA
BUSY LOW from Address Match 20 20 ns
t
BHA
BUSY HIGH from Address Mismatch 20 20 ns
t
BLC
BUSY LOW from CE LOW 20 20 ns
t
BHC
BUSY HIGH from CE HIGH 17 17 ns
t
PS
Port Setup for Priority 5 5 ns
t
WB
R/W HIGH after BUSY (Slave) 0 0 ns
t
WH
R/W HIGH after BUSY HIGH (Slave) 15 17 ns
t
BDD[27]
BUSY HIGH to Data Valid 20 25 ns
Interrupt Timing
[26]
t
INS
INT Set Ti me 20 20 ns
t
INR
INT Reset Time 20 20 ns
Semaphore Timing
t
SOP
SEM Flag Update Pulse (OE or SEM)1012ns
t
SWRD
SEM Flag Write to Read Time 5 5 ns
t
SPS
SEM Flag Contention Window 5 5 ns
t
SAA
SEM Address Access Time 20 25 ns
Switching Characteristics
Over the Operating Range (continued)
[20]
Parameter Description
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV Unit
-20 -25
Min Max Min Max
Timing
Parameter Test Conditions
[28]
Max Unit
ICC
DR1
at VCC
DR
= 2V 50 μA
Data Retention Mode
3.0V 3.0V
V
CC
> 2.0V
V
CC
to V
CC
–0.2V
V
CC
CE
t
RC
VIH
[+] Feedback
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
Document #: 38-06052 Rev. *J Page 11 of 19
Switching Waveforms
Notes
29.R/W is HIGH for read cycles.
30.Device is continuously selected CE = V
IL
and UB or LB = V
IL
. This waveform cann ot be used for semaph ore reads.
31.OE = V
IL
.
32.Address valid prior to or coincident with CE transition LOW .
33.To access RAM, CE = V
IL
, UB or LB = V
IL
, SEM = V
IH
. To access semaphore, CE = V
IH
, SEM = V
IL
.
t
RC
t
AA
t
OHA
DATA VALIDPREVIOUS DATA VA LID
DATA OUT
ADDRESS
t
OHA
Figure 5. Read Cycle No. 1 (Either Port Address Access)
[29, 30, 31]
t
ACE
t
LZOE
t
DOE
t
HZOE
t
HZCE
DATA VALID
t
LZCE
t
PU
t
PD
I
SB
I
CC
DATA OUT
OE
CE and
LB or UB
CURRENT
Figure 6. Read Cycle No. 2 (Either Port CE/OE Access)
[29, 32, 33]
UB or LB
DATAOUT
t
RC
ADDRESS
t
AA
t
OHA
CE
t
LZCE
t
ABE
t
HZCE
t
HZCE
t
ACE
t
LZCE
Figure 7. Read Cycle No. 3 (Either Port)
[29, 31, 32, 33]
[+] Feedback
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
Document #: 38-06052 Rev. *J Page 12 of 19
Notes
34.R/W or CE must be HIGH during all address transitions.
35.A write occurs during the overlap (t
SCE
or t
PWE
) of a LOW CE or SEM and a LOW UB or LB.
36.t
HA
is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.
37.If OE is LOW during a R/W controlled write cycle, the write pulse width must be t he larger of t
PWE
or (t
HZWE
+ t
SD
) to enable the IO drivers to turn off and
data to be pl aced on the bus for the required t
SD
. If OE is HIGH during an R/W controll ed write cycle, this requi rement does not ap ply and the write pulse can
be as short as the specified t
PWE
.
38.To access RAM, CE = V
IL
, SEM = V
IH
.
39.To access upper byte, CE = V
IL
, UB = V
IL
, SEM = V
IH
.
To access lower byte, CE = V
IL
, LB = V
IL
, SEM = V
IH
.
40.Transition is measured ±500 mV from steady state with a 5 pF load (including scope and jig). This parameter is sampled and not 100 percent tested.
41.During this period, the IO pins are in the output state, and input signals must not be applied.
42.If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high impedance state.
Switching Waveforms
(continued)
t
AW
t
WC
t
PWE
t
HD
t
SD
t
HA
CE
R/W
OE
DATAOUT
DATA IN
ADDRESS
t
HZOE
t
SA
t
HZWE
t
LZWE
Figure 8. Write Cycle No. 1: R/W Controlled Timing
[34, 35, 36, 37]
[40]
[40]
[37]
[38, 39]
NOTE 41 NOTE 41
t
AW
t
WC
t
SCE
t
HD
t
SD
t
HA
CE
R/W
DATA IN
ADDRESS
t
SA
Figure 9. Write Cycle No. 2: CE Controlle d Timing
[34, 35, 36, 42 ]
[38, 39]
[+] Feedback
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
Document #: 38-06052 Rev. *J Page 13 of 19
Notes
43.CE = HIGH for the duration of the above timing (both write and read cycle).
44.IO
0R
= IO
0L
= LOW (request semaphore); CE
R
= CE
L
= HIGH.
45.Semaphores are reset (available to both ports) at cycle start.
46.If t
SPS
is violated, the semaphore is definitely obtained by one side or the other, but which side gets the semaphore is unpredictable.
Switching Waveforms
(continued)
t
SOP
t
SAA
VALID ADRESS VALID ADRESS
t
HD
DATA
IN
VALID DATA
OUT
VALID
t
OHA
t
AW
t
HA
t
ACE
t
SOP
t
SCE
t
SD
t
SA
t
PWE
t
SWRD
t
DOE
WRITE CYCLE READ CYCLE
OE
R/W
IO
0
SEM
A
0
–A
2
Figure 10. Semaphore Read After Write Tim ing, Eith er Side
[43]
MATCH
t
SPS
A
0L
–A
2L
MATCH
R/W
L
SEM
L
A
0R
–A
2R
R/W
R
SEM
R
Figure 11. Timing Diagram of Semaphore Contention
[44, 45, 46]
[+] Feedback
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
Document #: 38-06052 Rev. *J Page 14 of 19
Note
47.CE
L
= CE
R
= LOW.
Switching Waveforms
(continued)
VALID
t
DDD
t
WDD
MATCH
MATCH
R/W
R
DATA IN
R
DATA
OUTL
t
WC
ADDRESS
R
t
PWE
VALID
t
SD
t
HD
ADDRESS
L
t
PS
t
BLA
t
BHA
t
BDD
BUSY
L
Figure 12. Timing Diagram of Read with BUSY (M/S=HIGH)
[47]
t
PWE
R/W
BUSY t
WB
t
WH
Figure 13. Write Timing with Busy Input (M/S=LOW)
[+] Feedback
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
Document #: 38-06052 Rev. *J Page 15 of 19
Note
48.If t
PS
is violated, the busy signal is asserted on one side or the other, but there is no guarantee to which side BUSY is asserted.
Switching Waveforms
(continued)
ADDRESS MATCH
t
PS
t
BLC
t
BHC
ADDRESS MATCH
t
PS
t
BLC
t
BHC
CE
R
ValidFirst:
ADDRESS
L,R
BUSY
R
CE
L
CE
R
BUSY
L
CE
R
CE
L
ADDRESS
L,R
Figure 14. Busy Timing Diagram No.1 (CE Arbitration)
[48]
CE
L
Valid First
ADDRESS MATCH
t
PS
ADDRESS
L
BUSY
R
ADDRESS MISMATCH
t
RC
or t
WC
t
BLA
t
BHA
ADDRESS
R
ADDRESS MATCH ADDRESS MISMATCH
t
PS
ADDRESS
L
BUSY
L
t
RC
or t
WC
t
BLA
t
BHA
ADDRESS
R
Right AddressValid First:
Figure 15. Busy Timing Diagram No.2 (Address Arbitration)
[48]
Left Address Valid First:
[+] Feedback
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CY7C0241AV/0251AV/036AV
Document #: 38-06052 Rev. *J Page 16 of 19
Notes
49.t
HA
depends on which enable pin (CE
L
or R/W
L
) is deasserted fir s t.
50.t
INS
or t
INR
depends on which enable pin (CE
L
or R/W
L
) is assert ed last.
Switching Waveforms
(continued)
WRITE 1FFF (OR 1/3FFF)
t
WC
Right SideClears INT
R
:
t
HA
READ 7FFF
t
RC
t
INR
WRITE 1FFE (OR 1/3FFE)
t
WC
Right SideSets INT
L
:
Left Side Sets INT
R
:
Left SideClears INT
L
:
READ 7FFE
t
INR
t
RC
ADDRESS
R
CE
L
R/W
L
INT
L
OE
L
ADDRESS
R
R/W
R
CE
R
INT
L
ADDRESS
R
CE
R
R/W
R
INT
R
OE
R
ADDRESS
L
R/W
L
CE
L
INT
R
t
INS
t
HA
t
INS
(OR 1/3FFF)
OR 1/3FFE)
[49]
[50]
[50]
[50]
[49]
[50]
Figure 16. Interrupt Timing Diagram
[+] Feedback
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
Document #: 38-06052 Rev. *J Page 17 of 19
Ordering Information
4K x16 3.3V Asynchronous Dual-Port SRAM
Speed
(ns) Orderin g Code Package
Diagram Package Type Operating
Range
15 CY7C024AV-15AI 5 1-85048 100-Pin Thin Quad Flat Pack Industrial
CY7C024BV-15AXI 51-85048 100-Pin Pb-Free Thin Quad Flat Pack
20 CY7C024AV-20AC 51-85048 100-Pin Thin Quad Flat Pack Commercial
CY7C024AV-20AXC 51-85048 100-Pin Pb-Free Thin Quad Flat Pack
CY7C024AV-20AI 5 1-85048 100-Pin Thin Quad Flat Pack Industrial
CY7C024AV-20AXI 51-85048 100-Pin Pb-Free Thin Quad Flat Pack
25 CY7C024AV-25AC 51-85048 100-Pin Thin Quad Flat Pack Commercial
CY7C024AV-25AXC 51-85048 100-Pin Pb-Free Thin Quad Flat Pack
CY7C024AV-25AI 51-85048 100-Pin Thin Quad Flat Pack Industrial
CY7C024AV-25AXI 51-85048 100-Pin Pb-Free Thin Quad Flat Pack
8K x16 3.3V Asynchronous Dual-Port SRAM
Speed
(ns) Orderin g Code Package
Name Package Type Operating
Range
20 CY7C025AV-20AC 51-85048 100-Pin Thin Quad Flat Pack Commercial
CY7C025AV-20AXC 51-85048 100-Pin Pb-Free Thin Quad Flat Pack
CY7C025AV-20AXI 51-85048 100-Pin Pb-Free Thin Quad Flat Pack Industrial
25 CY7C025AV-25AC 51-85048 100-Pin Thin Quad Flat Pack Commercial
CY7C025AV-25AXC 51-85048 100-Pin Pb-Free Thin Quad Flat Pack
CY7C025AV-25AI 5 1-85048 100-Pin Thin Quad Flat Pack Industrial
CY7C025AV-25AXI 51-85048 100-Pin Pb-Free Thin Quad Flat Pack
16K x16 3.3V Asynchronous Dual-Port SRAM
Speed
(ns) Orderin g Code Package
Name Package Type Operating
Range
20 CY7C026AV-20AC 51-85048 100-Pin Thin Quad Flat Pack Commercial
CY7C026AV-20AXC 51-85048 100-Pin Pb-Free Thin Quad Flat Pack
CY7C026AV-20AXI 51-85048 100-Pin Pb-Free Thin Quad Flat Pack Industrial
25 CY7C026AV-25AC 51-85048 100-Pin Thin Quad Flat Pack Commercial
CY7C026AV-25AXC 51-85048 100-Pin Pb-Free Thin Quad Flat Pack
CY7C026AV-25AI 51-85048 100-Pin Thin Quad Flat Pack Industrial
CY7C026AV-25AXI 51-85048 100-Pin Pb-Free Thin Quad Flat Pack
4K x18 3.3V Asynchronous Dual-Port SRAM
Speed
(ns) Orderin g Code Package
Name Package Type Operating
Range
20 CY7C0241AV-20AC 51-85048 100-Pin Thin Quad Flat Pack Commercial
25 CY7C0241AV-25AC 51-85048 100-Pin Thin Quad Flat Pack Commercial
8K x18 3.3V Asynchronous Dual-Port SRAM
Speed
(ns) Orderin g Code Package
Name Package Type Operating
Range
20 CY7C0251AV-20AC 51-85048 100-Pin Thin Quad Flat Pack Commercial
25 CY7C0251AV-25AC 51-85048 100-Pin Thin Quad Flat Pack Commercial
[+] Feedback
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
Document #: 38-06052 Rev. *J Page 18 of 19
Package Diagram
Figure 17. 100-Pin Pb-Free Thin Plastic Quad Flat Pack (TQFP) A100
16K x18 3.3V Asynchronous Dual-Port SRAM
Speed
(ns) Orderin g Code Package
Name Package Type Operating
Range
20 CY7C036AV-20AC 51-85048 100-Pin Thin Quad Flat Pack Commercial
25 CY7C036AV-25AC 51-85048 100-Pin Thin Quad Flat Pack Commercial
CY7C036AV-25AXC 51-85048 100-Pin Pb-free Thin Quad Flat Pack
CY7C036AV-25AI 51-85048 100-Pin Thin Quad Flat Pack Industrial
51-85048 *C
[+] Feedback
Document #: 38-06052 Rev. *J Revised December 10, 2008 Page 19 of 19
All products and company names mentioned in this document may be the trademarks o f t heir respect i ve holders.
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
© Cypress Semicondu ctor Corpor ation, 2001-200 8. The informati on cont ained herein is subject to change witho ut notice. Cypr ess Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypres s pro duc ts are n ot warr ant ed nor int e nd ed to be used fo r
medical, life supp or t, l if e savi n g, cr it ical control or safety ap pl ic at ions, unless pursuant to a n express written agre ement with Cypress. Furth erm or e, Cyp ress doe s not auth or i ze i t s pr o ducts for use as
critical components in life-support systems where a malfunction or failur e may reasonably be expected to result in significant injury to the user. The inclusion of Cypress product s in life-support syst ems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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Document Title: CY7C024A V/024BV/025A V/026A V , CY7C0241A V/0251AV/036AV 3.3V 4K/8K/16K x 16/18 Dual-Port Static RAM
Document Number: 38-06052
Rev. ECN No. Orig. of
Change Submission
Date Description of Chang e
** 110204 SZV 11/11/01 Change from Spec number: 38-00838 to 38-06052
*A 122302 RBI 12/27/02 Power up requirements added to Maximum Ratings Information
*B 128958 JFU 9 /03/03 Added CY7C025AV-25AI to Ordering Information
*C 237622 YDT See ECN Removed cross information from fe atures section
*D 241968 WWZ See ECN Added CY7C024AV-25AI to Ordering Information
*E 276451 SPN See ECN Corrected x18 for 026AV to x16
*F 279452 RUY See ECN Added Pb-free packaging information
Corrected pin A113L to A13L on CY7C026AV pin list
Added minimum V
IL
of 0.3V and note 16
*G 373580 RUY See ECN Corrected CY7C024AC-25AXC to CY7C024A V -25AXC in Ordering Information
*H 380476 PCX See ECN Added to Part Ordering information:
CY7C024AV-15AI, CY7C024AV-15AXI, CY7C024 AV-20AI,
CY7C024AV-20AXI, CY7C025AV- 20AXI, CY7C026AV-20AXI
*I 2543577 NXR/AESA 07/25/08 Updated note number 33 on page 12 from “R/W must be HIGH during all
address transitions” to “R/W or CE must be HIGH during all address transitions”
*J 2623540 VKN/PYRS 12/17/08 Added CY7C024BV part
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