The SN74LS16 is obsolete and is no longer supplied. SDLS020E - MAY 1990 - REVISED FEBRUARY 2004 D Convert TTL Voltage Levels to MOS Levels D High Sink-Current Capability D Input Clamping Diodes Simplify System D D SN54LS06 . . . J PACKAGE SN74LS06, SN74LS16 . . . D, DB, N, OR NS PACKAGE (TOP VIEW) Design Open-Collector Driver for Indicator Lamps and Relays Inputs Fully Compatible With Most TTL Circuits 1A 1Y 2A 2Y 3A 3Y GND description/ordering information These hex inverter buffers/drivers feature high-voltage open-collector outputs to interface with high-level circuits (such as MOS), or for driving high-current loads, and also are characterized for use as inverter buffers for driving TTL inputs. The 'LS06 devices have a rated output voltage of 30 V, and the SN74LS16 has a rated output voltage of 15 V. The maximum sink current for the SN54LS06 is 30 mA, and for the SN74LS06 and SN74LS16 it is 40 mA. 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 6A 6Y 5A 5Y 4A 4Y 1Y 1A NC VCC 6A SN54LS06 . . . FK PACKAGE (TOP VIEW) 2A NC 2Y NC 3A 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 6Y NC 5A NC 5Y 3Y GND NC 4Y 4A These devices are compatible with most TTL families. Inputs are diode-clamped to minimize transmission effects, which simplifies design. Typical power dissipation is 175 mW, and average propagation delay time is 8 ns. 4 NC - No internal connection ORDERING INFORMATION PDIP - N 0C 0 C to 70 70C C ORDERABLE PART NUMBER PACKAGE TA TOP-SIDE MARKING Tube SN74LS06N Tube SN74LS06D Tape and reel SN74LS06DR SOP - NS Tape and reel SN74LS06NSR 74LS06 SSOP - DB Tape and reel SN74LS06DBR LS06 Tube SN54LS06J SN54LS06J Tube SNJ54LS06J SNJ54LS06J Tube SNJ54LS06FK SNJ54LS06FK SOIC - D CDIP - J -55C -55 C to 125 125C C LCCC - FK SN74LS06N LS06 Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2004, Texas Instruments Incorporated !"#$%&" ' ()##*& %' "! +),-(%&" .%&*/ #".)(&' ("!"#$ &" '+*(!(%&"' +*# &0* &*#$' "! *1%' '&#)$*&' '&%.%#. 2%##%&3/ #".)(&" +#"(*''4 ."*' "& *(*''%#-3 (-).* &*'&4 "! %-- +%#%$*&*#'/ +#".)(&' ("$+-%& &" 5676 %-- +%#%$*&*#' %#* &*'&*. )-*'' "&0*#2'* "&*./ %-- "&0*# +#".)(&' +#".)(&" +#"(*''4 ."*' "& *(*''%#-3 (-).* &*'&4 "! %-- +%#%$*&*#'/ POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 The SN74LS16 is obsolete and is no longer supplied. SDLS020E - MAY 1990 - REVISED FEBRUARY 2004 logic diagram (positive logic) 1A 2A 3A 4A 5A 6A 1 2 1Y 3 4 2Y 5 6 9 8 11 10 13 12 3Y 4Y 5Y 6Y Pin numbers shown are for the D, DB, J, N, and NS packages. schematic (each gate) VCC 9 k 2.5 k 15 k 1 k Output 2.5 k Input 2 k 2 k GND Resistor values shown are nominal. 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 The SN74LS16 is obsolete and is no longer supplied. SDLS020E - MAY 1990 - REVISED FEBRUARY 2004 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Output voltage, VO (see Notes 1 and 2): SN54LS06, SN74LS06 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 V SN74LS16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V Package thermal impedance, JA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values are with respect to GND. 2. This is the maximum voltage that should be applied to any output when it is in the off state. 3. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 4) SN74LS06 SN74LS16 SN54LS06 VCC VIH Supply voltage VIL Low-level input voltage High-level input voltage NOM MAX MIN NOM MAX 4.5 5 5.5 4.75 5 5.25 2 2 'LS06 VOH High-level output voltage IOL TA Low-level output current 0.8 0.8 30 30 15 30 -55 125 V V SN74LS16 Operating free-air temperature UNIT MIN 0 V V 40 mA 70 C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) MIN VIK VCC = MIN, SN74LS06 SN74LS16 SN54LS06 TEST CONDITIONS PARAMETER TYP II = -12 mA IOH VCC = MIN, VIL = 0.8 V 'LS06, VOH = 30 V SN74LS16, VOH = 15 V VOL VCC = MIN, VIH = 2 V IOL = 16 mA IOL = 30 mA IOL = 40 mA MAX MIN TYP UNIT MAX -1.5 -1.5 0.25 0.25 0.25 0.25 0.4 0.25 V mA 0.4 0.7 V 0.7 II IIH VCC = MAX, VCC = MAX, VI = 7 V VI = 2.4 V 1 1 20 20 A IIL ICCH VCC = MAX, VCC = MAX VI = 0.4 V -0.2 -0.2 mA 18 18 mA 60 mA ICCL VCC = MAX 60 For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. All typical values are at VCC = 5 V, and TA = 25C. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 mA 3 The SN74LS16 is obsolete and is no longer supplied. SDLS020E - MAY 1990 - REVISED FEBRUARY 2004 switching characteristics, VCC = 5 V, TA = 25C (see Figure 1) 4 PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL A Y POST OFFICE BOX 655303 TEST CONDITIONS RL = 110 , * DALLAS, TEXAS 75265 CL = 15 pF MIN MAX 7 15 10 20 UNIT ns The SN74LS16 is obsolete and is no longer supplied. SDLS020E - MAY 1990 - REVISED FEBRUARY 2004 PARAMETER MEASUREMENT INFORMATION VCC Test Point VCC RL (see Note B) From Output Under Test CL (see Note A) High-Level Pulse 1.3 V S2 LOAD CIRCUIT FOR 3-STATE OUTPUTS 3V Timing Input 1.3 V 5 k Test Point LOAD CIRCUIT FOR OPEN-COLLECTOR OUTPUTS LOAD CIRCUIT FOR 2-STATE TOTEM-POLE OUTPUTS S1 (see Note B) CL (see Note A) RL CL (see Note A) RL From Output Under Test VCC From Output Under Test Test Point 1.3 V 0V tw Low-Level Pulse 1.3 V tsu 0V In-Phase Output (see Note D) 3V 1.3 V 1.3 V 0V tPZL tPLZ tPHL VOH 1.3 V 1.3 V Waveform 1 (see Notes C and D) VOL tPZH tPLH VOH 1.3 V 1.3 V VOL Waveform 2 (see Notes C and D) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES 1.5 V 1.3 V VOL tPHL Out-of-Phase Output (see Note D) 1.3 V 0V Output Control (low-level enabling) 1.3 V tPLH 1.3 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V 1.3 V 3V Data Input 1.3 V VOLTAGE WAVEFORMS PULSE DURATIONS Input th VOL + 0.5 V tPHZ VOH 1.3 V VOH - 0.5 V 1.5 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance. B. All diodes are 1N3064 or equivalent. C. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL. E. Phase relationships between inputs and outputs have been chosen arbitrarily for these examples. F. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO 50 , tr 1.5 ns, tf 2.6 ns. G. The outputs are measured one at a time, with one input transition per measurement. Figure 1. Load Circuits and Voltage Waveforms POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 PACKAGE OPTION ADDENDUM www.ti.com 15-Oct-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 5962-9861701Q2A ACTIVE LCCC FK 20 1 TBD 5962-9861701QCA ACTIVE CDIP J 14 1 TBD Lead/Ball Finish MSL Peak Temp (3) POST-PLATE N / A for Pkg Type A42 N / A for Pkg Type N / A for Pkg Type SN54LS06J ACTIVE CDIP J 14 1 TBD A42 SN74LS06D ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU SN74LS06DBLE OBSOLETE SSOP DB 14 SN74LS06DBR ACTIVE SSOP DB 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LS06DBRG4 ACTIVE SSOP DB 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LS06DE4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LS06DG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LS06DR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LS06DRE4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LS06DRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LS06N ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN74LS06NE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN74LS06NSR ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LS06NSRE4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LS06NSRG4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TBD Call TI Level-1-260C-UNLIM Call TI SN74LS16D OBSOLETE SOIC D 14 TBD Call TI Call TI SN74LS16DR OBSOLETE SOIC D 14 TBD Call TI Call TI Call TI Call TI SN74LS16N OBSOLETE PDIP N 14 SNJ54LS06FK ACTIVE LCCC FK 20 1 TBD TBD SNJ54LS06J ACTIVE CDIP J 14 1 TBD POST-PLATE N / A for Pkg Type A42 N / A for Pkg Type (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 15-Oct-2009 Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SN74LS06DBR SSOP SN74LS06DR SN74LS06NSR SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 6.6 2.5 12.0 16.0 Q1 DB 14 2000 330.0 16.4 8.2 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LS06DBR SSOP DB 14 2000 346.0 346.0 33.0 SN74LS06DR SOIC D 14 2500 346.0 346.0 33.0 SN74LS06NSR SO NS 14 2000 346.0 346.0 33.0 Pack Materials-Page 2 MECHANICAL DATA MSSO002E - JANUARY 1995 - REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0-8 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MECHANICAL DATA MLCC006B - OCTOBER 1996 FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER 28 TERMINAL SHOWN 18 17 16 15 14 13 NO. OF TERMINALS ** 12 19 11 20 10 A B MIN MAX MIN MAX 20 0.342 (8,69) 0.358 (9,09) 0.307 (7,80) 0.358 (9,09) 28 0.442 (11,23) 0.458 (11,63) 0.406 (10,31) 0.458 (11,63) 21 9 22 8 44 0.640 (16,26) 0.660 (16,76) 0.495 (12,58) 0.560 (14,22) 23 7 52 0.739 (18,78) 0.761 (19,32) 0.495 (12,58) 0.560 (14,22) 24 6 68 0.938 (23,83) 0.962 (24,43) 0.850 (21,6) 0.858 (21,8) 84 1.141 (28,99) 1.165 (29,59) 1.047 (26,6) 1.063 (27,0) B SQ A SQ 25 5 26 27 28 1 2 3 4 0.080 (2,03) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25) 0.020 (0,51) 0.010 (0,25) 0.055 (1,40) 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.045 (1,14) 0.035 (0,89) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) 4040140 / D 10/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold plated. 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