●Point-of-Load
Regulators
●Set-Top Boxes
●LCD TV Secondary
Supplies
●Switches/Routers
●Power Modules
●DSP Power Supplies
General Description
The MAX15023 dual, synchronous step-down controller
operates from a 5.5V to 28V or 5V ±10% input voltage
range and generates two independent output voltages.
Each output is adjustable from 85% of the input voltage
down to 0.6V and supports loads of 12A or higher. Input
voltage ripple and total RMS input ripple current are
reduced by interleaved 180° out-of-phase operation.
The MAX15023 offers the ability to adjust the switching
frequency from 200kHz to 1MHz with an external resis-
tor. The MAX15023’s adaptive synchronous rectification
eliminates the need for external freewheeling Schottky
diodes. The device also utilizes the external low-side
MOSFET’s on-resistance as a current-sense element,
eliminating the need for a current-sense resistor. This pro-
tects the DC-DC components from damage during output
overloaded conditions or output short-circuit faults without
requiring a current-sense resistor. Hiccup-mode current
limit reduces power dissipation during short-circuit con-
ditions. The MAX15023 includes two independent pow-
er-good outputs and two independent enable inputs with
precise turn-on/turn-off thresholds, which can be used for
supply monitoring and for power sequencing.
Additional protection features include cycle-by-cycle,
low-side, sink peak current limit, and thermal shutdown.
Cycle-by-cycle, low-side, sink peak current limit prevents
reverse inductor current from reaching dangerous levels
when the device is sinking current from the output. The
MAX15023 also allows prebiased startup without dis-
charging the output and features adaptive internal digital
soft-start. This new proprietary feature enables monotonic
charging of externally large output capacitors at startup,
and achieves good control of the peak inductor current
during hiccup-mode short-circuit protection.
The MAX15023 is available in a space-saving and ther-
mally enhanced 4mm x 4mm, 24-pin TQFN-EP package.
The device operates over the -40°C to +85°C extended
temperature range.
Applications
Features
●5.5V to 28V or 5V ±10% Input Supply Range
●0.6V to (0.85 x VIN) Adjustable Outputs
●Adjustable 200kHz to 1MHz Switching Frequency
●Guaranteed Monotonic Startup into a Prebiased Load
●Lossless, Cycle-by-Cycle, Low-Side, Source
Peak Current Limit with Adjustable, Temperature-
Compensated Threshold
●Cycle-by-Cycle, Low-Side, Sink Peak Current-Limit
Protection
●Proprietary Adaptive Internal Digital Soft-Start
●±1% Accurate Voltage Reference
●Internal Boost Diodes
●Adaptive Synchronous Rectification Eliminates
External Freewheeling Schottky Diodes
●Hiccup-Mode Short-Circuit Protection and Thermal
Shutdown
●Power-Good Outputs and Analog Enable Inputs for
Power Sequencing
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
/V denotes an automotive qualified package.
PART TEMP RANGE PIN-PACKAGE
MAX15023ETG+ -40°C to +85°C 24 TQFN-EP*
MAX15023ETG/V+ -40°C to +85°C 24 TQFN-EP*
19-4219; Rev 3; 4/15
23
24
22
21
*EP
*EXPOSED PAD (CONNECT TO GROUND).
8
7
9
EN1
PGOOD1
DL1
PGND1
10
FB1
FB2
PGOOD2
DL2
COMP2
PGND2
1 2
LIM2
4 5 6
1718 16 14 13
LIM1
COMP1
DH2
DH1
BST1
LX1
MAX15023
EN2 VCC
3
15
IN
20
+
11 BST2
SGND
19 12 LX2
RT
TQFN
TOP VIEW
MAX15023 Wide 4.5V to 28V Input,
Dual-Output Synchronous Buck Controller
Pin Conguration
Ordering Information
EVALUATION KIT AVAILABLE
24 TQFN-EP
Junction-to-Ambient Thermal Resistance (θJA) ........+36°C/W
Junction-to-Case Thermal Resistance (θJC) ...............+8°C/W
IN to SGND............................................................ -0.3V to +30V
BST_ to VCC ......................................................... -0.3V to +30V
LX_ to SGND............................................................ -1V to +30V
EN_ to SGND .......................................................... -0.3V to +6V
PGOOD_ to SGND................................................ -0.3V to +30V
BST_ to LX_ ............................................................ -0.3V to +6V
DH_ to LX_ ........................................ ….-0.3V to (VBST_ + 0.3V)
DL_ to PGND_ ..........................................-0.3V to (VCC + 0.3V)
SGND to PGND_................................................. -0.3V to +0.3V
VCC to SGND ............. -0.3V to the lower of +6V or (VIN + 0.3V)
All Other Pins to SGND ..............................-0.3V to (VCC + 0.3V
VCC Short Circuit to SGND ......................................... Continuou
VCC Input Current (IN = VCC, internal LDO not used) ..... 600mA
PGOOD_ Sink Current ....................................................... 20mA
Continuous Power Dissipation (TA = +70°C)(Note 1)
24-Pin TQFN-EP (derate 27.8mW/°C above +70°C) .. 2222.2mW
Operating Temperature Range ............................ -40°C to +85°C
Junction Temperature ...................................................... +150°C
Storage Temperature Range ............................. -60°C to +150°C
Lead Temperature (soldering, 10s) .................................. +300°C
Soldering Temperature (reow) ....................................... +260°C
(VIN = 12V, RT = 33kΩ, CVCC = 4.7µF, CIN = 1µF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)
(Note 3)
Electrical Characteristics
Note 1: These power limits are due to the thermal characteristics of the package, absolute maximum junction temperature (150°C),
and the JEDEC 51-7 defined setup. Maximum power dissipation could be lower, limited by the thermal shutdown protection
included in this IC.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
GENERAL
Input Voltage Range VIN
5.5 28 V
VIN = VCC 4.5 5.5
Quiescent Supply Current IIN VFB1 = VFB2 = 0.9V, no switching 4.5 6 mA
Standby Supply Current IIN_SBY VEN1 = VEN2 = VSGND 0.21 0.35 mA
VCC REGULATOR
Output Voltage VCC
6V < VIN < 28V, ILOAD = 5mA 5.00 5.2 5.50 V
VIN = 6V, 1mA < ILOAD < 100mA
VCC Regulator Dropout ILOAD = 100mA 0.07 V
VCC Short-Circuit Output Current VIN = 5V 150 250 mA
VCC Undervoltage Lockout VCC_UVLO VCC falling 3.6 3.8 4 V
VCC Undervoltage Lockout
Hysteresis 430 mV
ERROR AMPLIFIER (FB_, COMP_)
FB_ Input Voltage Set-Point VFB_594 600 606 mV
FB_ Input Bias Current IFB_VFB_ = 0.6V -250 +250 nA
MAX15023 Wide 4.5V to 28V Input,
Dual-Output Synchronous Buck Controller
www.maximintegrated.com Maxim Integrated
│
2
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Note 2: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to http://www.maximintegrated.com/thermal-tutorial.
Package Thermal Characteristics (Note 2)
Absolute Maximum Ratings
(VIN = 12V, RT = 33kΩ, CVCC = 4.7µF, CIN = 1µF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)
(Note 3)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
FB to COMP
Transconductance gmICOMP = ±40µA 650 1200 1900 µS
Amplifier Open-Loop Gain No load 80 dB
Amplifier Unity-Gain Bandwidth 10 MHz
COMP_ Swing (High) 2.4 V
COMP_ Swing (Low) No load at COMP_ 0.6 V
COMP_ Source/Sink Current ICOMP_| ICOMP_ |, VCOMP_ = 1.5V 45 80 120 µA
ENABLE (EN_)
EN_ Input High VEN_HEN_ rising 1.15 1.20 1.25 V
EN_ Input Hysteresis VEN_HYS 150 mV
EN_ Input Leakage Current ILEAK_EN_-250 +250 nA
OSCILLATOR
Switching Frequency fSW Each converter 460 500 540 kHz
Switching Frequency
Adjustment Range (Note 4) 200 1000 kHz
PWM Ramp Peak-to-Peak
Amplitude VRAMP 1.42 V
PWM Ramp Valley VVALLEY 0.72 V
Phase Shift Between Channels From DH1 to DH2 rising edges 180 Degrees
Minimum Controllable On-Time 60 100 ns
Maximum Duty Cycle 86 87.5 %
OUTPUT DRIVERS
DH_ On-Resistance Low, sinking 100mA, VBST_ - VLX_ = 5V 1 Ω
High, sourcing 100mA, VBST_ - VLX_ = 5V 1.2
DL_ On-Resistance Low, sinking 100mA, VCC = 5.2V 0.75 Ω
High, sourcing 100mA, VCC = 5.2V 1.4
DH_ Peak Current CLOAD = 10nF Sinking 3 A
Sourcing 2
DL_ Peak Current CLOAD = 10nF Sinking 3 A
Sourcing 2
DH_, DL_ Break-Before-Make
Time (Dead Time) 15 ns
SOFT-START
Soft-Start Duration 2048 Switching
cycles
Reference Voltage Steps 64 Steps
MAX15023 Wide 4.5V to 28V Input,
Dual-Output Synchronous Buck Controller
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3
Electrical Characteristics (continued)
(VIN = 12V, RT = 33kΩ, CVCC = 4.7µF, CIN = 1µF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)
(Note 3)
Electrical Characteristics (continued)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
CURRENT LIMIT/HICCUP
Cycle-by-Cycle, Low-Side, Source
Peak Current-Limit Threshold
Adjustment Range
Source peak limit = VLIM_/10 30 300 mV
LIM_ Reference Current ILIM_VLIM_ = 0.3V to 3V, TA = +25°C 45 50 55 µA
LIM_ Reference Current TC VLIM_ = 0.3V 2400 ppm/°C
Number of Consecutive Current-
Limit Events to Hiccup 7 Events
Hiccup Timeout Out of soft-start 7936 Switching
cycles
Cycle-by-Cycle, Low-Side,
Sink Peak Current-Limit Sense
Voltage
VLIM_/
20 V
BOOST
Boost Switch Resistance VIN = VCC = 5.2V, IBST_ = 10mA 4.5 8 Ω
POWER-GOOD OUTPUTS
PGOOD_ Threshold VFB_ rising 88.5 92.5 96.5 %
VFB(NOMINAL)
VFB_ falling 85.5 89.5 93.5
PGOOD_ Output Leakage ILEAK_PGDVPGOOD_ = 28V, VEN_ = 5V, VFB_
= 0.8V 1 µA
PGOOD_ Output Low Voltage VPGOOD_LIPGOOD_ = 2mA, EN_ = SGND 0.4 V
THERMAL SHUTDOWN
Thermal Shutdown Threshold +150 °C
Thermal Shutdown Hysteresis Temperature falling 20 °C
MAX15023 Wide 4.5V to 28V Input,
Dual-Output Synchronous Buck Controller
www.maximintegrated.com Maxim Integrated
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TSW
24806 1
R (k ) (24806 has a unit).
(f (kHz))1.0663 farad
Ω=
Note 3: All Electrical Characteristics limits over temperature are 100% tested at room tempture and guaranteed by design over the
specified temperature range.
Note 4: Select RT as
EFFICIENCY
vs. LOAD CURRENT
MAX15023 toc01
LOAD CURRENT (A)
EFFICIENCY (%)
101
35
40
45
50
55
60
65
70
75
80
85
90
95
30
0.1 100
VIN = 12V
VOUT1 = 1.2V
VOUT1 = 3.3V
EFFICIENCY
vs. LOAD CURRENT
MAX15023 toc02
LOAD CURRENT (A)
EFFICIENCY (%)
101
35
40
45
50
55
60
65
70
75
80
85
90
95
100
30
0.1 100
VOUT1 = 1.2V
VOUT1 = 3.3V
VIN = VCC = 5V
LOAD CURRENT (A)
OUTPUT VOLTAGE CHANGE
vs. LOAD CURRENT
.
MAX15023 toc03
LO
OUTPUT VOLTAGE CHANGE (%)
108642
99.2
99.4
99.6
99.8
100.0
100.2
100.4
100.6
100.8
101.0
99.0
0 12
OUT1
VCC VOLTAGE
vs. LOAD CURRENT
MAX15023 toc04
LOAD CURRENT (mA)
SUPPLY VOLTAGE (V)
13512015 30 45 75 9060 105
5.05
5.10
5.15
5.20
5.25
5.30
5.35
5.40
5.00
0 150
VCC VOLTAGE
vs. IN VOLTAGE
MAX15023 toc05
IN VOLTAGE (V)
VCC VOLTAGE (V)
242016128
4.15
4.30
4.45
4.60
4.75
4.90
5.05
5.20
5.35
5.50
4.00
4 28
ILOAD = 5mA
ILOAD = 50mA
VCC VOLTAGE
vs. TEMPERATURE
MAX15023 toc06
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
303510-15
5.05
5.10
5.15
5.20
5.25
5.30
5.35
5.40
5.45
5.50
5.00
-40 85
ILOAD = 5mA
SWITCHING FREQUENCY
vs. RT
MAX15023 toc07
RT (kΩ)
SWITCHING FREQUENCY (kHz)
807050 6030 4020
200
300
400
500
600
700
800
900
1000
1100
1200
1300
100
10 90
SWITCHING FREQUENCY
vs. TEMPERATURE
MAX15023 toc08
TEMPERATURE (ºC)
SWITCHING FREQUENCY (kHz)
603510-15
250
300
350
400
450
500
550
600
650
700
750
800
200
-40 85
RT = 22.1kΩ
RT = 33.2kΩ
RT = 66.5kΩ
IIN CURRENT
vs. SWITCHING FREQUENCY
MAX15023 toc09
SWITCHING FREQUENCY (kHz)
IIN CURRENT (mA)
900800700600500400300
30
60
90
120
150
180
210
0
200 1000
VIN = 12V
CDL = CDH = 10nF
CDL = CDH = 4.7nF
CDL = CDH = 1nF
CDL = CDH = 0nF
(Supply = IN = 12V, unless otherwise noted. See Typical Application Circuit of Figure 6.)
MAX15023 Wide 4.5V to 28V Input,
Dual-Output Synchronous Buck Controller
Maxim Integrated
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Typical Operating Characteristics
(Supply = IN = 12V, unless otherwise noted. See Typical Application Circuit of Figure 6.)
LOAD TRANSIENT ON OUT2
MAX15023 toc16
10µs/div
VOUT2 (AC-COUPLED)
200mV/div
VOUT1 (AC-COUPLED)
100mV/div
IOUT2
2A/div
LOAD TRANSIENT ON OUT1
MAX15023 toc15
10µs/div
VOUT1 (AC-COUPLED)
100mV/div
VOUT2 (AC-COUPLED)
50mV/div
IOUT1
5A/div
MAX15023 toc14
RLIM (kΩ)
CURRENT-LIMIT THRESHOLD (mV)
555040 4515 20 25 30 3510
30
60
90
120
150
180
210
240
270
300
0
5 60
SOURCE CURRENT LIMIT
SINK CURRENT LIMIT
CURRENT-LIMIT THRESHOLD
vs. RLIM
SHUTDOWN CURRENT
vs. TEMPERATURE
MAX15023 toc13
TEMPERATURE (ºC)
SHUTDOWN CURRENT (µA)
603510-15
205
210
215
220
225
230
200
-40 85
LIM_ CURRENT
vs. TEMPERATURE
MAX15023 toc12
TEMPERATURE (C)
LIM_ CURRENT (µA)
603510-15
40
42
44
46
48
50
52
54
56
58
60
38
-40 85
ILIM2
ILIM1
EN_ TURN-ON AND TURN-OFF THRESHOLD
vs. TEMPERATURE
MAX15023 toc11
TEMPERATURE (C)
EN_ TURN-ON AND TURN-OFF THRESHOLDS
603510-15
1.025
1.050
1.075
1.100
1.125
1.150
1.175
1.200
1.225
1.250
1.000
-40 85
EN_ RISING
EN_ FALLING
IIN + IVCC CURRENT
vs. SWITCHING FREQUENCY
MAX15023 toc10
SWITCHING FREQUENCY (kHz)
IIN + IVCC CURRENT (mA)
900800700600500400300
30
60
90
120
150
180
210
0
200 1000
VIN = VCC = 5V
CDL_ = CDH_ = 10nF
CDL_ = CDH_ = 4.7nF
CDL_ = CDH_ = 1nF
CDL = CDH = 0nF
MAX15023 Wide 4.5V to 28V Input,
Dual-Output Synchronous Buck Controller
Maxim Integrated
│
6
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Typical Operating Characteristics (continued)
(Supply = IN = 12V, unless otherwise noted. See Typical Application Circuit of Figure 6.)
STARTUP INTO PREBIASED OUTPUT
(0.5V PREBIASED)
MAX15023 toc22
2ms/div
VOUT1
500mV/div
0V
STARTUP AND TURN-OFF FROM IN
MAX15023 toc21
4ms/div
VIN
10V/div
VOUT2
2V/div
VPGOOD2
5V/div
IOUT2 = 500mA
STARTUP AND TURN-OFF FROM IN
MAX15023 toc20
4ms/div
VIN
10V/div
VOUT1
1V/div
VPGOOD1
5V/div
EN1 = EN2 = VCC
IOUT1 = 1.2A
STARTUP AND DISABLE FROM EN
MAX15023 toc19
2ms/div
VEN2
5V/div
VIN
10V/div
VOUT2
2V/div
VPGOOD2
5V/div
IOUT2 = 500mA
STARTUP AND DISABLE FROM EN
MAX15023 toc18
2ms/div
VEN1
5V/div
VIN
10V/div
VOUT1
500mV/div
VPGOOD1
5V/div
IOUT1 = 1.2A
LINE-TRANSIENT RESPONSE
MAX15023 toc17
2ms/div
VIN
5V/div
VOUT1
(AC-COUPLED)
50mV/div
VOUT2
(AC-COUPLED)
100mV/div
MAX15023 Wide 4.5V to 28V Input,
Dual-Output Synchronous Buck Controller
Maxim Integrated
│
7
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Typical Operating Characteristics (continued)
(Supply = IN = 12V, unless otherwise noted. See Typical Application Circuit of Figure 6.)
STARTUP INTO PREBIASED OUTPUT
(1V PREBIASED)
MAX15023 toc23
2ms/div
VOUT1
500mV/div
0V
STARTUP INTO PREBIASED OUTPUT
(1.5V PREBIASED)
MAX15023 toc24
2ms/div
VOUT1
500mV/div
0V
DH_ AND DL_ DISOVERLAP
MAX15023 toc25
20ns/div
VDH1
10V/div
VDL1
5V/div
VLX1
10V/div
IOUT1 = 5A
DH_ AND DL_ DISOVERLAP
MAX15023 toc26
20ns/div
VDH1
10V/div
VDL1
5V/div
VLX1
10V/div
IOUT1 = 5A
OUT-OF-PHASE SWITCHING FORMS
MAX15023 toc27
1µs/div
VLX1
10V/div
VLX2
10V/div
ILX1
5A/div
ILX2
2A/div
IOUT1 = 5A
IOUT2 = 2.5A
SINK CURRENT-LIMIT WAVEFORMS
MAX15023 toc28
100µs/div
VOUT1
200mV/div
VLX1
20V/div
ILX1
2A/div
1.5V PREBIASED
MAX15023 Wide 4.5V to 28V Input,
Dual-Output Synchronous Buck Controller
Maxim Integrated
│
8
www.maximintegrated.com
Typical Operating Characteristics (continued)
PIN NAME FUNCTION
1 FB1 Feedback Input for Regulator 1. Connect FB1 to a resistive divider between Output 1 and SGND to adjust
the output voltage between 0.6V and (0.85 x input voltage (V)). See the Setting the Output Voltage section.
2 EN1
Active-High Enable Input for Regulator 1. When the voltage at EN1 exceeds 1.2V (typ), the controller begins
regulating OUT1. When the voltage falls below 1.05V (typ), the regulator is turned off. The EN1 input can be
used for power sequencing and as a secondary UVLO. Connect EN1 to VCC for always-on applications.
3 EN2
Active-High Enable Input for Regulator 2. When the voltage at EN2 exceeds 1.2V (typ), the controller begins
regulating OUT2. When the voltage falls below 1.05V (typ), the regulator is turned off. The EN2 input can be
used for power sequencing and as a secondary UVLO. Connect EN2 to VCC for always-on applications.
4 PGOOD1 Power-Good Output (Open Drain) for Channel 1. To obtain a logic signal, pull up PGOOD1 with an external
resistor connected to a positive voltage below 28V.
5 DL1 Low-Side Gate-Driver Output for Regulator 1. DL1 swings from VCC to PGND1. DL1 is low before VCC
reaches the UVLO rising threshold voltage.
6 PGND1 Low-Side Gate-Driver Supply Return (Regulator 1). Connect to the source of the low-side MOSFET of
Regulator 1.
7 LX1
External Inductor Connection for Regulator 1. Connect LX1 to the switched side of the inductor. LX1
serves as the lower supply rail for the DH1 high-side gate driver and as sensing input of the synchronous
MOSFET’s VDS drop (drain terminal).
8 BST1 Boost Flying-Capacitor Connection for Regulator 1. Connect a ceramic capacitor with a minimum value of
100nF between BST1 and LX1.
9 DH1 High-Side Gate-Driver Output for Regulator 1. DH1 swings from LX1 to BST1. DH1 is low before VCC
reaches the UVLO rising threshold voltage.
10 DH2 High-Side Gate-Driver Output for Regulator 2. DH2 swings from LX2 to BST2. DH2 is low before VCC
reaches the UVLO rising threshold voltage.
11 BST2 Boost Flying-Capacitor Connection for Regulator 2. Connect a ceramic capacitor with a minimum value of
100nF between BST2 and LX2.
12 LX2
External Inductor Connection for Regulator 2. Connect LX2 to the switched side of the inductor. LX2
serves as the lower supply rail for the DH2 high-side gate driver and as sensing input of the synchronous
MOSFET’s VDS drop (drain terminal).
MAX15023 Wide 4.5V to 28V Input,
Dual-Output Synchronous Buck Controller
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9
Pin Description
PIN NAME FUNCTION
13 PGND2 Low-Side Gate-Driver Supply Return (Regulator 2). Connect to the source of the low-side MOSFET of
Regulator 2.
14 DL2 Low-Side Gate-Driver Output for Regulator 2. DL2 swings from VCC to PGND2. DL2 is low before VCC
reaches the UVLO rising threshold voltage.
15 PGOOD2 Power-Good Output (Open Drain) for Channel 2. To obtain a logic signal, pull up PGOOD2 with an external
resistor connected to a positive voltage below 28V.
16 VCC
Internal 5.2V Linear Regulator Output and the Device’s Core Supply. When using the internal regulator,
bypass VCC to SGND with a 4.7µF minimum low-ESR ceramic capacitor. If VCC is connected to IN for 5V
operation, then a 2.2µF ceramic capacitor is adequate for decoupling (see the Typical Application Circuits).
17 FB2 Feedback Input for Regulator 2. Connect FB2 to a resistive divider between output 2 and SGND to adjust the
output voltage between 0.6V and (0.85 x input voltage (V)). See the Setting the Output Voltage section.
18 COMP2 Compensation Pin for Regulator 2. See the Compensation section.
19 RT Oscillator-Timing Resistor Input. Connect a resistor from RT to SGND to set the oscillator frequency from
200kHz to 1MHz (see the Setting the Switching Frequency section).
20 SGND Signal Ground. Connect SGND to the SGND plane. SGND also serves as sensing input of the synchronous
MOSFET’s VDS drop (source terminals) for both channels.
21 IN Internal VCC Regulator Input. Bypass IN to SGND with a 1µF minimum ceramic capacitor when the internal
linear regulator (VCC) is used. When operating in the 5V ±10% range, connect IN to VCC.
22 LIM2
Current-Limit Adjustment for Regulator 2. Connect a resistor (RLIM2) from LIM2 to SGND to adjust the
current-limit threshold (VITH2) from 30mV (RLIM2 = 6kΩ) to 300mV (RLIM2 = 60kΩ). See the Setting the
Cycle-by-Cycle Low-Side Source Peak Current Limit section.
23 LIM1
Current-Limit Adjustment for Regulator 1. Connect a resistor (RLIM1) from LIM1 to SGND to adjust the
current-limit threshold (VITH1) from 30mV (RLIM1 = 6kΩ) to 300mV (RLIM1 = 60kΩ). See the Setting the
Cycle-by-Cycle Low-Side Source Peak Current Limit section.
24 COMP1 Compensation Pin for Regulator 1. See the Compensation section.
— EP Exposed Paddle. Connect EP to a large copper plane at SGND potential to improve thermal dissipation. Do
not use as the main IC’s SGND ground connection.
MAX15023 Wide 4.5V to 28V Input,
Dual-Output Synchronous Buck Controller
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│
10
Pin Description (continued)
OSCILLATOR
ENABLE
LOGIC
VREF
RT
EN1
ENABLE1
COMPARATOR
THERMAL
SHUTDOWN
BANDGAP
REFERENCE
STARTUP
BIAS
VREF
VREF = 0.6V
VREF
EN2
SGND
IN
LIM2
LIM1
VCC
ENABLE2
COMPARATOR
IN
UVLO
VCC
UVLO
INTERNAL
VOLTAGE
REGULATOR
LIM
CURRENT
GENERATOR
MAX15023 GEN
VREF
CK2
CK1
ENABLE1 ENABLE2
VREF
CK2
LIM2
SGND LIM1
CK1
ENABLE1
ENABLE1
gM
VREF
ENABLE2
DC-DC CONVERTER 2
DC-DC CONVERTER 1
SOFT-START/
STOP LOGIC
AND
HICCUP LOGIC
COMP2 BST2 DH2 PGND2
PGOOD2 FB2 DL2 LX2
MAX15023
VREF
0.925 x VREF
CK1
FB1
DAC_VREF
PWM
COMPARATOR
RAMP
GENERATOR
BOOST
DRIVER
LOW-SIDE DRIVER
SINK
CURRENT-LIMIT
COMPARATOR
PGOOD
COMPARATOR
SOURCE
CURRENT-LIMIT
COMPARATOR
HIGH-
SIDE
DRIVER
PWM
PWM
CONTROL
LOGIC
RAMP
GATEP
HICCUP TIMEOUT
HICCUP
HICCUP
VCC
LIM1/20
LIM1/10
HICCUP
TIMEOUT
COMP1
BST1
DH1
LX1
DL1
PGND1
FB1
PGOOD1
MAX15023 Wide 4.5V to 28V Input,
Dual-Output Synchronous Buck Controller
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Functional Diagram
Detailed Description
The MAX15023 dual, synchronous, step-down controller
operates from a 5.5V to 28V or 5V ±10% input voltage
range and generates two independent output voltages.
As long as the controller’s input bias voltage is within the
specified range, the input power bus can also be lower
than 4.5V and step-down conversion from a 3.3V rail
is also possible. Both output voltages can be set from
0.6V to 85% of regulator’s input voltage. Each output can
support loads of 12A or higher. The switching sequence
of the regulators is interleaved with 180° out-of-phase
operation, so that input voltage ripple and total RMS input
ripple current are reduced.
Enable inputs with precise turn-on/off threshold (±4.2%)
allow accurate external UVLO settings. Power-good
(PGOOD) open-drain outputs can be used for supply
sequencing.
The MAX15023’s capability to provide low output voltag-
es (down to 0.6V) and high output current (in excess of
12A) makes it ideal for applications where a 5V or 12V
bus is postregulated to deliver low voltages and high cur-
rents, such as in set-top boxes.
The switching frequency is adjustable from 200kHz to
1MHz using an external resistor. The MAX15023’s adap-
tive synchronous rectification eliminates the need for
external freewheeling Schottky diodes.
The MAX15023 utilizes voltage-mode control and exter-
nal compensation. The device also utilizes cycle-by-cycle
low-side source peak current limit for overcurrent pro-
tection, where the external low-side MOSFET’s on-re-
sistance is used as a current-sense element during the
inductor freewheeling time, eliminating the need for a
current-sense resistor. The current-limit threshold voltage
is resistor adjustable independently on each regulator
from 30mV to 300mV and is temperature compensated,
so that the effects of the MOSFET’s RDS(ON) variation
over temperature are reduced. Hiccup-mode current limit
reduces average current and power dissipation during a
prolonged short-circuit condition.
The MAX15023 also features a proprietary adaptive inter-
nal digital soft-start and allows prebias startup without
discharging the output. Adaptive digital soft-start, by act-
ing on the loop voltage reference, automatically prolongs
the soft-start time, if the current-limit threshold is reached
during the soft-start sequence. This increases the ability
to smoothly bring up a large, unknown amount of out-
put capacitance. Also, since soft-start is invoked during
hiccup-mode short-circuit protection, the same voltage
reference rollback algorithm achieves good control of the
peak inductor current during steady short-circuit or over-
load conditions.
An additional protection feature (cycle-by-cycle low-side
sink peak current limit) prevents the regulators from sink-
ing excessive amount of current if the prebias voltage
exceeds the programmed steady-state regulation level,
or if another voltage source is trying to force the output
above that. This way, the synchronous rectifier MOSFET
and the body diode of the high-side MOSFET do not
experience dangerous levels of current stress while the
regulator is sinking current from the output.
Thermal shutdown protects the MAX15023 from exces-
sive power dissipation.
DC-DC PWM Controller
The MAX15023 step-down controller uses a PWM volt-
age-mode control scheme (see the Functional Diagram)
for each channel. Control loop compensation is external
for providing maximum flexibility in choosing the oper-
ating frequency and output LC filter components. An
internal transconductance error amplifier produces an
integrated error voltage at COMP_ that helps provide
higher DC accuracy. The voltage at COMP_ sets the duty
cycle using a PWM comparator and a ramp generator. On
the rising edge of its internal clock, the high-side n-chan-
nel MOSFET of each regulator turns on and remains on
until either the appropriate duty cycle or the maximum
duty cycle is reached. During the high-side MOSFET’s
on-time, the inductor current ramps up. During the sec-
ond-half of the switching cycle, the high-side MOSFET
turns off and the low-side n-channel MOSFET turns on.
Now the inductor releases the stored energy as its cur-
rent ramps down, providing current to the output. Under
overload conditions, when the inductor current exceeds
the selected cycle-by-cycle low-side source peak cur-
rent-limit threshold (see the Current-Limit Circuit (LIM_)
section), the high-side MOSFET does not turn on at the
subsequent clock rising edge and the low-side MOSFET
remains on to let the inductor current ramp down.
Interleaved Out-of-Phase Operation
The two independent regulators in the MAX15023 oper-
ate 180° out-of-phase to reduce input filtering require-
ments, reduce electromagnetic interference (EMI), and
improve efficiency. This effectively lowers component
cost and saves board space, making the MAX15023 ideal
for cost-sensitive applications.
MAX15023 Wide 4.5V to 28V Input,
Dual-Output Synchronous Buck Controller
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The internal oscillator frequency is divided down to obtain
separated clock signals for each regulator. The phase dif-
ference of the two clock signals is 180°, so that the high-
side MOSFETs turn on out-of-phase. The instantaneous
input current peaks of both regulators no longer overlap,
resulting in reduced RMS ripple current and input voltage
ripple. As a result, this allows an input capacitor with a
lower ripple-current rating to be used or allows the use
of fewer or less expensive capacitors, as well as reduces
EMI filtering and shielding requirements.
Internal 5.2V Linear Regulator
The MAX15023’s internal functions and MOSFET drivers
are designed to operate from a 5V ±10% supply voltage.
If the available supply voltage exceeds 5.5V, a 5.2V inter-
nal low-dropout linear regulator is used to power internal
functions and the MOSFET drivers at VCC. If an external
5V ±10% supply voltage is available, then IN and VCC can
be tied to the 5V supply. The maximum regulator input
voltage (VIN) is 28V. The regulator’s input (IN) must be
bypassed to SGND with a 1µF ceramic capacitor when
the regulator is used. Bypass the regulator’s output (VCC)
with a 4.7µF ceramic capacitor to SGND. The VCC drop-
out voltage is typically 70mV, so when VIN is greater than
5.5V, VCC is typically 5.2V. The MAX15023 also employs
a UVLO circuit that disables both regulators when VCC
falls below 3.8V (typ). The 430mV UVLO hysteresis pre-
vents chattering on power-up/power-down.
The internal VCC linear regulator can source up to 100mA
to supply the IC, power the low-side gate drivers, recharge
the external boost capacitors, and supply small external
loads. The current available for external loads depends
on the current consumed for the MOSFET gate drive.
For example, when switched at 600kHz, a single MOSFET
with 18nC total gate charge (at VGS = 5V) requires 18nC
x 600kHz ≅ 11mA. Since four MOSFETs are driven and
6mA (max) is used by the internal control functions, the
current available for external loads is:
(100 – (4 x 11) – 6)mA ≅ 50mA
MOSFET Gate Drivers (DH_, DL_)
The DH_ and DL_ drivers are optimized for driving large
size n-channel power MOSFETs. Under normal operating
conditions and after startup, the DL_ low-side drive wave-
form is always the complement of the DH_ high-side drive
waveform (with controlled dead time to prevent cross-con-
duction or shoot-through). On each channel, an adaptive
dead-time circuit monitors the DH and DL outputs and
prevents the opposite-side MOSFET from turning on until
the other MOSFET is fully off. Thus, the circuit allows the
high-side driver to turn on only when the DL_ gate driver has
been turned off. Similarly, it prevents the low-side (DL_) from
turning on until the DH_ gate driver has been turned off.
The adaptive driver dead time allows operation without
shoot-through with a wide range of MOSFETs, minimiz-
ing delays, and maintaining efficiency. There must be a
low-resistance, low-inductance path from the DL_ and
DH_ drivers to the MOSFET gates for the adaptive dead-
time circuits to work properly. Otherwise, because of the
stray impedance in the gate discharge path, the sense
circuitry could interpret the MOSFET gates as off while
the VGS of the MOSFET is still high. To minimize stray
impedance, use very short, wide traces (50 mils to 100
mils wide if the MOSFET is 1in from the driver).
Synchronous rectification reduces conduction losses in the
rectifier by replacing the normal low-side Schottky catch
diode with a low-resistance MOSFET switch. The internal
pulldown transistor that drives DL_ low is robust, with a
0.75Ω (typ) on-resistance. This low on-resistance helps
prevent DL_ from being pulled up during the fast rise time
of the LX_ node, due to capacitive coupling from the drain
to the gate of the low-side synchronous rectifier MOSFET.
High-Side Gate-Drive Supply (BST_)
and Internal Boost Switches
The high-side MOSFET is turned on by closing an inter-
nal switch between BST_ and DH_. This provides the
necessary gate-to-source voltage to turn on the high-side
MOSFET, an action that boosts the gate drive signal
above VIN. The boost capacitor connected between
BST_ and LX_ holds up the voltage across the gate driver
during the high-side MOSFET on-time.
The charge lost by the boost capacitor for delivering the
gate charge is refreshed when the high-side MOSFET is
turned off and LX_ node swings down to ground. When
the corresponding LX_ node is low, an internal high-volt-
age switch connected between VCC and BST_ recharges
the boost capacitor to the VCC voltage. The need for
external boost diodes is negated. See the Boost Flying-
Capacitor Selection section in the Design Procedure sec-
tion to choose the right size of the boost capacitor.
Enable Inputs (EN_),
Adaptive Soft-Start and Soft-Stop
The MAX15023 can be used regulate two independent
outputs. Each of the two outputs can be turned on and
off independently of one another by controlling the enable
input of each phase (EN1 and EN2).
A logic-high on each enable pin turns on the correspond-
ing channel. Then, the soft-start sequence is initiated by
step-wise increasing the reference voltage of the error
MAX15023 Wide 4.5V to 28V Input,
Dual-Output Synchronous Buck Controller
www.maximintegrated.com Maxim Integrated
│
13
the inductor current around its limit value, rather than the
output voltage. The soft-start time can be prolonged up to
4096 clock cycles (twice the normal soft-start duration).
This implementation allows the soft-start time to be auto-
matically adapted to the time necessary to keep the LX
current below the limit while charging the output capacitor.
Since soft-start is invoked by the hiccup-mode short-cir-
cuit protection, also see the Hiccup Mode Overcurrent
Protection section for additional details.
Power-Good Outputs (PGOOD_)
The MAX15023 includes two power-good comparators
to monitor the regulators’ output voltages and detect the
power-good threshold, fixed at 92.5% of the nominal FB
voltage. The PGOOD_ outputs are open-drain and should
be pulled up with an external resistor to the supply volt-
age of the logic input they drive. This voltage should not
exceed 28V. They can sink up to 2mA of current while low.
amplifier. The duration of the soft-start ramp is 204witch-
ing cycles and the resolution is 1/64 of the steady-state
regulation voltage. This allows a smooth increase of the
output voltage. A logic-low on each EN_ initiates a soft-
stop sequence by stepping down the reference voltage
of the error amplifier. After the soft-stop sequence is
completed, the MOSFET drivers are both turned off. See
Figure 1 for more detail.
Connect EN1 and EN2 to VCC for always-on operation.
Owing to their accurate turn-on and turn–off thresholds,
EN1 and EN2 can be used as a UVLO adjustment input
and for power sequencing together with the PGOOD_
outputs. (See the Setting the Enable Input (EN_) section).
The adaptive action in the soft-start becomes visible if
the cycle-by-cycle, low-side, source peak current limit
is reached during the soft-start ramping sequence. In
this case, the rate-of-rise of the internal reference is
decreased, so that the PWM controller tries to regulate to
Figure 1. MAX15023 Detailed Power-On/-Off Sequencing
VCC
BC D E
2048 CLK
CYCLES
2048 CLK
CYCLES
FGH IA
UVLO
EN_
VOUT_
DAC_VREF_
DH_
DL_
UVLO Undervoltage threshold value is provided in
the
Electrical Characteristics
table.
Internal 5.2V linear regulator output.
Active-high enable input.
Regulator output voltage.
Regulator internal soft-start and soft-stop signal.
Regulator high-side gate-driver output.
Regulator low-side gate-driver output.
VCC rising while below the UVLO threshold.
EN_ is low.
VCC
EN_
VOUT_
DAC_VREF_
DH_
DL_
A
SYMBOL
DEFINITION
BVCC is higher than the UVLO threshold. EN_ is low.
EN is pulled high. DH_ and DL_ start switching.
Normal operation.
VCC drops below UVLO.
VCC goes above UVLO threshold. DH_ and DL_
start switching. Normal operation.
EN_ is pulled low. VOUT_ enters soft-stop.
EN_ is pulled high. DH_ and DL_ start switching.
Normal operation.
VCC drops below UVLO.
C
D
E
F
G
H
I
SYMBOL DEFINITION
DEFINITION
MAX15023 Wide 4.5V to 28V Input,
Dual-Output Synchronous Buck Controller
www.maximintegrated.com Maxim Integrated
│
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cycle, low-side, source peak current-limit threshold during
the low-side MOSFET on-time, the controller does not ini-
tiate a new PWM cycle and lets the inductor current decay
in the next cycle. Since cycle-by-cycle, low-side, source
peak current sensing is employed, the actual peak current
is greater than the current-limit threshold by an amount
equal to the inductor ripple current. Therefore, the exact
current-limit characteristic and maximum load capability
are functions of the low-side MOSFET’s on-resistance,
current-limit threshold, inductor value, and input voltage.
Cycle-by-cycle, low-side, sink peak current limit is also
implemented by monitoring the voltage drop across the
low-side MOSFET, but with opposite polarity (drain more
positive than source). If this drop exceeds 1/20 the volt-
age at the corresponding LIM_ pin at any time during
the low-side MOSFET on-time, the low-side MOSFET is
turned off and the inductor current flows from the output
through the high-side MOSFET back. If the cycle-by-cy-
cle, low-side, sink peak current limit is activated, the DH_
and DL_ switching sequence is no longer complementary.
Hiccup Mode Overcurrent Protection
Hiccup mode overcurrent protection reduces power dis-
sipation during prolonged short-circuit or deep overload
conditions.
After the soft-start sequence has been completed, on
each switching cycle where the cycle-by-cycle, low-side,
source peak current-limit threshold is reached, a 3-bit
counter is incremented. The counter is decremented on
each switching cycle where the threshold is not reached,
and stopped at zero (000).
If the cycle-by-cycle, low-side, source peak current-lim-
it condition persists, the counter fills up reaching 111
(= 7 events). Then, the controller stops both DL_ and
DH_ drivers and waits for 7936 switching cycles (hiccup
timeout delay). After this delay, the controller initiates a
new soft-start sequence.
If cycle-by-cycle low-side, source peak current-limit events
occur during theft-start time, turn-on cycles are still
skipped to control the inductor current, but the fill-up of the
3-bit counter does not terminate the soft-start sequence.
Rather, the soft-start ramp is slowed down or rolled
back based on the cycle-by-cycle, low-side, source peak
current-limit events occurrences, so that the PWM con-
troller tries to regulate the inductor current around its limit
value, rather than the output voltage.
This proprietary technique prevents the duty cycle from
saturating, and limits the on-time and thus, the peak
inductor current is reached every time the high-side
MOSFET is turned on.
Each PGOOD_ goes high (high impedance) when the
corresponding regulator output increases above 92.5%
of its nominal regulated voltage. Each PGOOD_ goes
low when the corresponding regulator output voltage
drops typically below 89.5% of its nominal regulated volt-
age. PGOOD_ can be used as power-on-reset or power
sequencing for the two regulators.
PGOOD_ asserts low during the hiccup timeout pod.
Startup into a Prebiased Output
When the controller starts into a prebiased output, the
DH_/DL_ complementary switching sequence is inhibit-
ed until the PWM comparator commands its first PWM
pulse. Until then, DH_ and DL_ are kept off so that the
converter does not sink current from the output. The first
PWM pulse occurs when the ramping reference voltage
increases above the FB_ voltage or the internal soft-start
time is over.
Current-Limit Circuit (LIM_)
The current-limit circuit employs a cycle-by-cycle low-
side source peak and sink current-sensing algorithm that
uses the on-resistance of the low-side MOSFET as a
current-sensing element, so that costly sense resistors
are not required. The current-limit circuit is also tempera-
ture compensated to track the MOSFET’s on-resistance
variation over temperature. The current limit is adjustable
on each channel with an external resistor at LIM_ (see
the Typical Application Circuits), and accommodates
MOSFETs with a wide range of on-resistance character-
istics (see the Design Procedure section). The adjustment
range is from 30mV to 300mV for the cycle-by-cycle,
low-side, source peak current limit, corresponding to
resistor values of 6kΩ to 60kΩ. The cycle-by-cycle, low-
side, source peak current-limit threshold across the low-
side MOSFET is precisely 1/10 the voltage seen LIM_,
while the cycle-by-cycle, low-side, sink peak current-limit
threshold is 1/20 the voltage seen at LIM_.
The MAX15023 uses SGND to sense the voltage of the
source terminals of the low-side MOSFETs for both chan-
nels, and LX_ to sense the drain voltage of each low-side
MOSFET. Carefully observe the PCB Layout Guidelines
section to ensure that noise and systematic errors do not
corrupt the current-sense signals seen by LX_ and SGND
on each channel.
Cycle-by-cycle, low-side, source peak current limit acts
when the inductor current flows in the normal direction,
and the drain (LX_) is more negative than source (sensed
by SGND) during the low-side MOSFET on-time. If the
magnitude of current-sense signal exceeds the cycle-by-
MAX15023 Wide 4.5V to 28V Input,
Dual-Output Synchronous Buck Controller
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│
15
The maximum voltage conversion ratio is limited by the
maximum duty cycle (Dmax):
OUT max DROP2 max DROP1
max
IN IN
V D V (1 D ) V
D
VV
−
−
×+ ×
<
where VDROP1 is the sum of the parasitic voltage drops in
the inductor discharge path, including synchronous rectifi-
er, inductor, and PCB resistances. VDROP2 is the sum of
the voltage drops in the charging path, including high-side
switch, inductor, and PCB resistances. In practice, the
above condition should be met with adequate margin for
good load-transient response.
Setting the Enable Input (EN_)
Each controller has an enable input referenced to an
analog voltage (1.2V). When the voltage exceeds 1.2V,
the regulator is enabled. To set a specific turn-on thresh-
old that can act as a secondary UVLO, a resistive divider
circuit can be used (see Figure 2)
Select R2 (EN_ to SGND resistor) to a value lower than
200kΩ. Calculate R1 (VMON to EN_ resistor) with the
following equation:
MON
12
EN_H_
V
RR 1
V−
=
where VEN_H_ = 1.2V (typical).
In case of a nonideal short circuit applied at the output,
the out voltage equals the output impedance times the
limited inductor current during this phase. Ar reaching the
maximum allowable limit of the soft-start duration (twice
the normal soft-start ti, the controller remains off for 7936
clock cycles before trying to soft-start again.
Undervoltage Lockout
The MAX15023 has an internal undervoltage lockout
(UVLO) circuit to monitor the voltage on VCC. The UVLO
circuit prevents the MAX15023 from operating if the volt-
ages for the MOSFET drivers or for the internal control
functions are too low. The VCC falling threshold is 3.8V
(typ), with 430mV hysteresis to prevent chattering on
the rising/falling edge of the supply voltage. Before VCC
reaches UVLO rising threshold voltage, DL_ and DH_
stay low to inhibit switching.
Thermal-Overload Protection
Thermal-overload protection limits total power dissipation
in the MAX15023. When the device’s die-junction tem-
perature exceeds TJ = +150°C, an on-chip thermal sensor
shuts down the device, forcing DL_ and DH_ low, allow-
ing the IC to cool. The thermal sensor turns the device
on again after the junction temperature cools by 20°C.
During thermal shutdown, the regulators shut down, and
soft-start is reset. Thermal-overload protection can be
triggered by power dissipation in the LDO regulator, by
excessive driving losses, or by both. Therefore, careful-
ly evaluate the total power dissipation (see the Power
Dissipation section) to avoid unwanted triggering of the
thermal-overload protection in normal operation.
Design Procedure
Effective Input Voltage Range
Although the MAX15023 controllers can operate from
input supplies up to 28V and regulate down to 0.6V, the
minimum voltage conversion ratio (VOUT/VIN) might be
limited by the minimum controllable on-time. For proper
fixed-frequency PWM operation, the voltage conversion
ratio should obey the following condition:
OUT ON(MIN) SW
IN
Vtf
V
>×
where tON(MIN) is 100ns (max) and fSW is the switching
frequency in Hertz. If the desired voltage conversion
does not meet the above condition, then pulse skipping
occurs to decrease the effective duty cycle. To avoid
this, decrease the switching frequency or lower the input
voltage VIN.
Figure 2. Adjustable Enable Voltage
EN_
R1
VMON
R2
MA15023
MAX15023 Wide 4.5V to 28V Input,
Dual-Output Synchronous Buck Controller
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│
16
T1.0663
SW
24806
R
(f )
=
Inductor Selection
Three key inductor parameters must be specified for oper-
ation with the MAX15023: inductance value (L), inductor
saturation current (ISAT), and DC resistance (RDC). To
select inductance value, the ratio of inductor peak-to-peak
AC current to DC average current (LIR) must be selected
first. A good compromise between size and loss is a 30%
peak-to-peak ripple current to average-current ratio (LIR
= 0.3). The switching frequency, input voltage, output
voltage, and selected LIR then determine the inductor
value as follows:
OUT IN OUT
IN SW OUT
V (V V )
LV f I LIR
−
=
where VIN, VOUT, and IOUT are typical values (so that
efficiency is optimum for typical conditions). The switch-
ing frequency is set by RT (see the Setting the Switching
Frequency section). The exact inductor value is not critical
and can be adjusted in order to make trade-offs among
size, cost, efficiency, and transient response require-
ments. Lower inductor values minimize size and cost, but
also improve transient response and reduce efficiency
due to higher peak currents. On the other hand, higher
inductance increases efficiency by reducing the RMS
current, but requires more output capacitance to meet
load-transient specifications.
Find a low-loss inductor having the lowest possible DC
resistance that fits in the allotted dimensions. The induc-
tor’s saturation rating (ISAT) must be high enough to
ensure that saturation can occur only above the maximum
current-limit value, given the tolerance of the low- side
MOSFET’s on-resistance and of the LIM_ reference cur-
rent (ILIM). On the other hand, these tolerances should
not prevent the converter from delivering the rated load
current (ILOAD(MAX)). Combining these conditions, the
inductor saturation current (ISAT) should be such that:
DS(ON,MAX)
DS(ON,TYP)
R
SAT LOAD(MAX)
R
LIR
I 1I
2
> ×+ ×
where RDS(ON,MAX) and RDS(ON,TYP) are the maximum
and typical on-resistance of the low-side MOSFET. For
a given inductor type and value, choose the LIR corre-
sponding to the worst-case inductor tolerance.
For LIR = 0.4, and a +25% on the low-side MOSFET’s
RDS(ON,MAX), the inductor saturation current should be
about 50% greater than the converter’s maximum load
current. A variety of inductors from different manufactur-
ers can be chosen to meet this requirement (for example,
Coilcraft MSS1278 series).
Setting the Output Voltage
Set the MAX15023 output voltage on each channel by
connecting a resistive divider from the output to FB_ to
SGND (Figure 3). Select R2 (FB_ to SGND resistor) less
than or equal to 16kΩ. Calculate R1 (OUT_ to FB_ resis-
tor) with the following equation:
OUT_
12 FB_
V
RR 1
V−
=
where VFB_ = 0.6V (typ) (see the Electrical Characteristics
table) and VOUT_ can range from 0.6V to (0.85 x VIN).
Resistor R1 also plays a role in the design of the Type III
compensation network. If a Type III compensation net-
work is used, make sure to review the values of R1 and
R2 according to the Type III Compensation Network (See
Figure 5) section.
Setting the Switching Frequency
The switching frequency, fSW, for each channel is set by
a resistor (RT) connected from RT to SGND. The relation-
ship between fSW and RT is:
where fSW is in kHz, RT is in kΩ, and 24806 is in 1/
farad. For example, a 600kHz switching frequency is set
with RT = 27.05kΩ. Higher frequencies allow designs
with lower inductor values and less output capacitance.
Consequently, peak currents and I2R losses are lower
at higher switching frequencies, but core losses, gate-
charge currents, and switching losses increase.
Figure 3. Adjustable Output Voltage
FB_
R1
OUT_
R2
MA15023
MAX15023 Wide 4.5V to 28V Input,
Dual-Output Synchronous Buck Controller
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ITH DS(ON,MAX) LOAD(MAX)
LIR
VR I 1
2
−
> ××
OUT IN OUT
RMS LOAD(MAX)
IN
V (V V )
II V
−
=
IRMS has a maximum value when the input voltage equals
twice the output voltage (VIN = 2VOUT), so IRMS(MAX) =
ILOAD(MAX)/2.
Choose an input capacitor that exhibits less than +10°C
temperature rise at the RMS input current for optimal
long-term reliability.
The input voltage ripple is composed of ∆VQ (caused
by the capacitor discharge) and ∆VESR (caused by the
ESR of the capacitor). Use low-ESR ceramic capacitors
with high ripple current capability at the input. Assume
the contribution from the ESR and capacitor discharge
are equal to 50%. Calculate the input capacitance and
ESR required for a specified input voltage ripple using the
following equations:
ESR
IN L
OUT
V
ESR I
I
2
∆
=∆
+
where:
IN OUT OUT
L
IN SW
(V V ) V
IVf L
−
×
∆= ××
and:
OUT
IN Q SW
I D(1 D)
CVf
−×
=∆×
where:
OUT
IN
V
DV
=
All equations listed above are valid under the assumption
that the input ports of both converters can be merged in
the physical layout, so that only one input capacitor truly
serves both converters. If this is not the case, additional
low-ESR, low-ESL ceramic capacitors should be locally
placed on each converter’s input port, connected between
the drain of the high-side MOSFET and the source of the
low-side MOSFET.
Output Capacitor
The key selection parameters for the output capacitor
are capacitance value, ESR, and voltage rating. These
parameters affect the overall stability, output ripple volt-
age, and transient response. The output ripple has two
components: variations in the charge stored in the output
capacitor, and the voltage drop across the capacitor’s
ESR caused by the current flowing into and out of the
capacitor:
RIPPLE ESR Q
V VV
∆ ≅∆ +∆
Setting the Cycle-by-Cycle, Low-Side, Source
Peak Current Limit
The minimum current-limit threshold must be high enough
to support the maximum expected load current with the
worst-case low-side MOSFET on-resistance value since
the low-side MOSFET’s on-resistance is used as the cur-
rent-sense element. The inductor’s cycle-by-cycle, low-
side, source peak current occurs at ILOAD(MAX) minus
half the ripple current. The ripple current is maximum
when the inductor value is at the lower limit of its specified
tolerance. The minimum value of the current-limit thresh-
old voltage (VITH) should be greater than the voltage on
the low-side MOSFET during the ripple-current valley:
where RDS(ON) is the on-resistance of the low-side
MOSFET in ohms. Use the maximum value for RDS(ON)
from the low-side MOSFET’s data sheet.
To adjust the current-limit threshold, connect a resistor
(RLIM_) from LIM_ to SGND. The relationship between
the current-limit threshold (VITH_) and RLIM_ is:
ITH_
LIM_
10 V
50 A
×
where RLIM_ is in kΩ and VITH_ is in mV.
An RLIM_ resistance range of 6kΩ to 60kΩ corresponds
to a current-limit threshold of 30mV to 300mV. When
adjusting the current limit, use 1% tolerance resistors to
minimize errors in the current-limit threshold setting.
Input Capacitor
The input filter capacitor reduces peak currents drawn
from the power source and reduces noise and voltage
ripple on the input caused by the circuit’s switching. The
two converters of the MAX15023 run 180° out-of-phase,
thereby, effectively doubling the switching frequency at
the input and lowering the input RMS current.
The input ripple waveform would be unsymmetrical due
to the difference in load current and duty cycle between
converter 1 and converter 2. In fact, the worst-case input
RMS current occurs when only one controller is operating.
The converter delivering the highest output power (VOUT
x IOUT) must be used in the formulas below:
The input capacitor RMS current requirement (IRMS) is
defined by the following equation:
MAX15023 Wide 4.5V to 28V Input,
Dual-Output Synchronous Buck Controller
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ESR
STEP
STEP RESPONSE
OUT Q
ESL STEP
STEP
RESPONSE
O
V
ESR I
It
CV
Vt
ESL I
1
t3f
∆
=
×
=∆
∆×
=
≅×
Compensation
Each channel of the MAX15023 provides an internal
transconductance amplifier with its inverting input and
its output available to the user for external frequency
compensation. The flexibility of external compensation
for each converter offers wide selection of output filter-
ing components, especially the output capacitor. For
cost-sensitive applications, use low-ESR aluminum elec-
trolytic capacitors; for component-size sensitive appli-
cations, use low-ESR tantalum, polymer, or ceramic
capacitors at the output. The high switching frequency of
the MAX15023 allows use of ceramic capacitors at the
output. Choose the small-signal components for the error
amplifier to achieve the desired closed-loop bandwidth
and phase margin.
To choose the appropriate compensation network type,
the power-supply poles and zeros, the zero crossover
frequency, and the type of the output capacitor must be
determined.
In a buck converter, the LC filter in the output stage intro-
duces a pair of complex poles at the following frequency:
PO
OUT OUT
1
f2L C
=π× ×
The output capacitor and its ESR also introduce a zero
at:
ZO
OUT
1
f2 ESR C
=π× ×
The loop-gain crossover frequency (fO, where the loop
gain equals 1 (0dB)) should be set below 1/10 the switch-
ing frequency:
SW
O
f
f
10
≤
Choosing a lower crossover frequency might also help
in reducing the effects of noise pickup into the feedback
loop, such as jittery duty cycle.
In order to maintain a stable system, two stability criteria
must be met:
1) The phase shift at the crossover frequency fO, must be
less than 180°. In other words, the phase margin of the
loop must be greater than zero.
2) The gain at the frequency where the phase shift is
-180° (gain margin) must be less than 1.
The output voltage ripple as a consequence of the ESR
and the output capacitance is:
ESR L
L
QOUT SW
IN OUT OUT
L
IN SW
V I ESR
I
V8C f
(V V ) V
IVf L
−
∆ =∆×
∆
∆=
××
×
∆= ××
where ∆IL is the peak-to-peak inductor current ripple (see
the Inductor Selection section). These equations are suit-
able for initial capacitor selection, but final values should
be verified by testing in a prototype or evaluation circuit.
As a general rule, a smaller inductor ripple current results
in less output ripple voltage. The output capacitor must
be also checked against load-transient response require-
ments. The allowable deviation of the output voltage
during fast load transients also determines the output
capacitance, its ESR, and its equivalent series inductance
(ESL). The output capacitor supplies the load current
during a load step until the controller responds with a
greater duty cycle. The response time (tRESPONSE)
depends on the closed-loop bandwidth of the convert-
er (see the Compensation section). The resistive drop
across the output capacitor’s ESR, the drop across the
capacitor’s ESL (∆VESL), and the capacitor discharge
causes a voltage droop during the load step.
Use a combination of low-ESR tantalum/aluminum elec-
trolytic or polymer and ceramic capacitors for better tran-
sient load and voltage ripple performance. Non-leaded
capacitors and capacitors in parallel help reduce the ESL.
Keep the maximum output voltage deviation below the
tolerable limits of the load. Use the following equations to
calculate the required ESR, ESL, and capacitance value
during a load step:
where ISTEP is the load step, tSTEP is the rise time of the
load step, tRESPONSE is the response time of the control-
ler, and fO is the closed-loop crossover frequency.
MAX15023 Wide 4.5V to 28V Input,
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The total loop gain as the product of the modulator gain
and the error amplifier gain at fO should equal 1. So:
MOD EA
Gain Gain 1
×=
Therefore:
IN FB
mF
OSC O OUT OUT
VV
ESR
gR1
V (2 f L ) V
× × ××=
π× ×
Solving for RF:
( )
OSC O OUT OUT
FFB IN m
V 2f L V
RV V g ESR
× π× × ×
=× ××
2) Set a midband zero (fZ1) at 0.75 x fPO (to cancel one
of the LC poles):
Z1 PO
FF
1
f 0.75 f
2R C
= = ×
π× ×
Solving for CF:
F
F PO
1
C2 R f 0.75
=π× × ×
3) Place a high-frequency pole at fP1 = 0.5 x fSW (to
attenuate the ripple at the switching frequency, fSW)
and calculate CCF using the following equation:
CF
F SW
F
1
C1
Rf C
−
=
π× ×
It is recommended to have a phase margin around +50°
to +60° to maintain a robust loop stability and well-be-
haved transient response.
If an electrolytic or large-ESR tantalum output capacitor
is used, the capacitor ESR zero fZO typically occurs
between the LC poles and the crossover frequency fO
(fPO < fZO < fO). In this case, use a Type II (PI or propor-
tional-integral) compensation network.
If a ceramic or low-ESR tantalum output capacitor is
used, the capacitor ESR zero typically occurs above the
desired crossover frequency fO, that is fPO < fO < fZO. In
this situation, choose a Type III (PID or proportional-inte-
gral-derivative) compensation network.
Type II Compensation Network (See Figure 4)
If fZO is lower than fO and close to fPO, the phase lead
of the capacitor ESR zero almost cancels the phase loss
of one of the complex poles of the LC filter around the
crossover frequency. Therefore, a Type II compensation
network with a midband zero and a high-frequency pole
can be used to stabilize the loop. In Figure 4, RF and CF
introduce a midband zero (fZ1). RF and CCF in the Type II
compensation network also provide a high-frequency pole
(fP1), which mitigates the effects of the output high-fre-
quency ripple.
To calculate the component values for Type II compensa-
tion network in Figure 4, follow the instruction below:
1) Calculate the gain of the modulator (GainMOD)—
composed of the regulator’s pulse-width modulator,
LC filter, feedback divider, and associated circuitry at
crossover frequency:
( )
IN FB
MOD
OSC O OUT OUT
VV
ESR
Gain V 2f L V
=××
π× ×
where VIN is the regulator’s input voltage, VOSC is the
amplitude of the ramp in the pulse-width modulator, VFB
is the FB_ input voltage set-point (0.6V typically, see
Electrical Characteristics table), and VOUT is the desired
output voltage.
The gain of the error amplifier (GainEA) in midband fre-
quencies is:
EA m F
Gain g R= ×
where gm is the transconductance of the error amplifier.
Figure 4. Type II Compensation Network
VREF
R1
VOUT
R2gm
RF
COMP
CFCCF
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2) The gain of the modulator (GainMOD)—composed of
the regulator’s pulse-width modulator, LC filter, feed-
back divider, and associated circuitry at crossover
frequency is:
IN
MOD 2
OSC
O OUT OUT
V1
Gain V(2 f ) L C
= × π× × ×
The gain of the error amplifier (GainEA) in midband fre-
quencies is:
EA O I F
Gain 2 f C R= π× × ×
The total loop gain as the product of the modulator gain
and the error amplifier gain at fO should be equal to 1.
So:
MOD EA
Gain Gain 1×=
Therefore:
IN
OIF
2
OSC O OUT OUT
V1
2 f CR 1
V(2 f ) C L
× × π× × × =
π× × ×
Solving for CI:
( )
OSC O OUT OUT
IIN F
V 2f L C
CVR
× π× × ×
=×
3) If fPO < fO < fZO < fSW/2, the second pole (fP2) should
be used to cancel fZO. This way, the Bode plot of the
loop gain plot does not flatten out soon after the 0dB
crossover, and maintains its -20dB/decade slope up
to 1/2 the switching frequency. This is likely to occur if
the output capacitor is a low-ESR tantalum or polymer.
Then set:
fP2 = fZO
If a ceramic capacitor is used, then the capacitor ESR
zero, fZO, is likely to be located even above 1/2 the
switching frequency, that is, fPO < fO< fSW/2 < fZO. In this
case, the frequency of the second pole (fP2) should be
placed high enough in order not to significantly erode the
phase margin at the crossover frequency. For example, it
can be set at 5 x fO, so that its contribution to phase loss
at the crossover frequency, fO, is only about 11°:
fP2 = 5 x fO
Once fP2 is known, calculate RI:
IP2 I
1
R
2f C
=π× ×
Type III Compensation Network
(See Figure 5)
If the output capacitor used is a low-ESR tantalum or
ceramic type, the ESR-induced zero frequency is usually
above the targeted zero crossover frequency (fO). In this
case, Type III compensation is recommended. Type III
compensation provides three poles and two zeros at the
following frequencies:
Z1 FF
Z2
I 1I
1
f2R C
1
f2 C (R R )
=π× ×
=π× × +
Two midband zeros (fZ1 and fZ2) cancel the pair of com-
plex poles introduced by the LC filter:
fP1 = 0
fP1 introduces a pole at zero frequency (integrator) for
nulling DC output voltage errors:
P2
II
1
f
2 RC
=π× ×
Depending on the location of the ESR zero (fZO), fP2 can
be used to cancel it, or to provide additional attenuation
of the high-frequency output ripple:
P3 F CF
F
F CF
1
fCC
2R CC
=×
π× × +
fP3 attenuates the high-frequency output ripple.
The locations of the zeros and poles should be such that
the phase margin peaks around fO.
Ensure that RF>>2/gm (1/gm(MIN) = 1/600µS = 1.67kΩ)
and the parallel resistance of R1, R2, and RI is greater
than 1/gm. Otherwise, a 180° phase shift is introduced to
the response and will make it unstable.
The following procedure is recommended:
1) With RF ≥ 10kΩ, place the first zero (fZ1) at 0.5 x fPO:
Z1 PO
FF
1
f 0.5 f
2R C
= = ×
π× ×
so:
F PO
2 R 0.5 fπ× × ×
MAX15023 Wide 4.5V to 28V Input,
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DRIVE IN G_TOTAL SW
P VQ f=××
All four n-channel MOSFETs must be a logic-level type
with guaranteed on-resistance specifications at VGS
= 4.5V. For maximum efficiency, choose a high-side
MOSFET (NH_) that has conduction losses equal to the
switching losses at the typical input voltage. Ensure that
the conduction losses at minimum input voltage do not
exceed MOSFET package thermal limits, or violate the
overall thermal budget. Also, ensure that the conduction
losses plus switching losses at the maximum input volt-
age do not exceed package ratings or violate the overall
thermal budget. Ensure that the MAX15023 DL_ gate
drivers can drive a low-side MOSFET (NL_). In particular,
check that the dV/dt caused by NH_ turning on does not
pull up the NL_ gate through NL_’s drain-to-gate capac-
itance. This is the most frequent cause of cross-conduc-
tion problems.
Gate-charge losses are dissipated by the driver and do
not heat the MOSFET. Therefore, if the drive current is
taken from the internal LDO regulator, the power dissipa-
tion due to drive losses must be checked. All MOSFETs
must be selected so that their total gate charge is low
enough; therefore, VCC can power all four drivers without
overheating the IC:
where QG_TOTAL is the sum of the gate charges of all
four MOSFETs.
Power Dissipation
Device’s maximum power dissipation depends on the
thermal resistance from the die to the ambient environ-
ment and the ambient temperature. The thermal resis-
tance depends on the device package, PCB copper area,
other thermal mass, and airflow.
The power dissipated into the package (PT) depends
on the supply configuration (see the Typical Application
Circuits). It can be calculated using the following equation:
PT = VIN x IIN
For the circuits of Figures 7 and 8:
PT = VCC x (IIN + IVCC)
where VIN and VCC are the voltages at the respective
pins, IIN is the current at the input of the internal LDO (IIN
is practically zero for the circuits of Figures 7 and 8), IVCC
is the current consumed by the internal core and drivers
when the internal regulator is unused for 5V supply opera-
tion (IN = VCC). See the corresponding Typical Operating
Characteristics for the typical curves of IIN and IVCC cur-
rent consumption vs. operating frequency at various load
capacitance values.
4) Place the second zero (fZ2) at 0.2 x fO or at fPO,
whichever is lower and calculate R1 using the follow-
ing equation:
1I
Z2 I
1
RR
2f C
−=π× ×
5) Place the third pole (fP3) at half the switching frequen-
cy and calculate CCF:
( )
F
CF
SW F F
C
C2 0.5 f R C 1
−
=π× × × ×
6) Calculate R2 as:
FB
21
OUT FB
V
RR
VV−
= ×
MOSFET Selection
The MAX15023’s step-down controller drives two exter-
nal logic-level n-channel MOSFETs as the circuit switch
elements. The key selection parameters to choose these
MOSFETs include:
● On-resistance (RDS(ON) )
● Maximum drain-to-source voltage (VDS(MAX) )
● Minimum threshold voltage (VTH(MIN) )
● Total gate charge (Qg)
● Reverse transfer capacitance (CRSS)
●Power dissipation
Figure 5. Type III Compensation Network
VREF
gm
R1
R2
VOUT
RI
COMP
CI
CCF
RFCF
MAX15023 Wide 4.5V to 28V Input,
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Applications Information
PCB Layout Guidelines
Make the controller ground connections as follows: create
a small analog ground plane near the IC or use a dedicat-
ed internal plane. Connect this plane to SGND and use
this plane for the ground connection for the IN bypass
capacitor, compensation components, feedback dividers,
RT resistor, and LIM_ resistors.
If possible, place all power components on the top side of
the board, and run the power stage currents (especially
the one having large high-frequency components) using
traces or copper fills on the top side only, without adding
vias.
On the top side, lay out a large PGND copper area for
the output of channels 1 and 2, and connect the bottom
terminals of the high-frequency input capacitors, output
capacitors, and the source terminals of the low-side
MOSFETs to that area.
Then, make a star connection of the SGND plane to the
top copper PGND area with few vias in the vicinity of
the source terminal sensing. Do not connect PGND and
SGND anywhere else. Refer to the MAX15023 Evaluation
Kit data sheet for guidance.
Keep the power traces and load connections short, espe-
cially at the ground terminals. This practice is essential for
high efficiency and jitter-free operation. Use thick copper
PCBs (2oz vs. 1oz) to enhance efficiency.
Place the controller IC adjacent to the synchronous
rectifier MOSFETs (NL_) and keep the connections for
LX_, PGND_, DH_, and DL_ short and wide. Use multi-
ple small vias to route these signals from the top to the
bottom side. The gate current traces must be short and
wide, measuring 50 mils to 100 mils wide if the low-side
MOSFET is 1in from the controller IC. Connect each
PGND trace from the IC close to the source terminal of
the respective low-side MOSFET.
Route high-speed switching nodes (BST_, LX_, DH_, and
DL_) away from the sensitive analog areas (RT, COMP_,
LIM_, and FB_). Group all SGND-referred and feedback
components close to the IC. Keep the FB_ and compen-
sation network nets as small as possible to prevent noise
pickup.
To estimate the temperature rise of the die, use the fol-
lowing equation:
TJ = TA + (PT x θJA)
where θJA is the junction-to-ambient thermal resistance
of the package, PT is power dissipated in the device, and
TA is the ambient temperature. The θJA is 36°C/W for
the 24-pin TQFN package on multilayer boards, with the
conditions specified by the respective JEDEC standards
(JESD51-5, JESD51-7). If actual operating conditions
significantly deviate from those described in the JEDEC
standards, then an accurate estimation of the junction
temperature requires a direct measurement of the case
temperature (TC). Then, the junction temperature can be
calculated using the following equation:
TJ = TC + (PT x θJC)
Use 3°C/W as θJC thermal resistance for the 24-pin
TQFN package. The case-to-ambient thermal resistance
(θCA) is dependent on how well the heat is transferred
from the PCB to the ambient. Therefore, solder the
exposed pad of the TQFN package to a large copper area
to spread heat through the board surface, minimizing the
case-to-ambient thermal resistance. Use large copper
areas to keep the PCB temperature low.
Boost Flying-Capacitor Selection
The MAX15023 uses a bootstrap circuit to generate the
necessary gate-to-source voltage to turn on the high-side
MOSFET. The selected n-channel high-side MOSFET
determines the appropriate boost capacitance values
(CBST_in Typical Application Circuits) according to the
following equation:
BST_
BST_
Qg
CV
=∆
where Qg is the total gate charge of the high-side
MOSFET and ∆VBST_ is the voltage variation allowed
on the high-side MOSFET driver after turn-on. Choose
∆VBST_ such that the available gate drive voltage is not
significantly degraded (e.g., ∆VBST_ = 100mV to 300mV)
when determining CBST_. The boost flying-capacitor
should be a low-ESR ceramic capacitor. A minimum value
of 100nF is recommended.
MAX15023 Wide 4.5V to 28V Input,
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Figure 6. Application Diagram (Operation from a Single-Supply Rail, VIN = 9V to 16V)
3300pF
390pF
33pF
MAX15023
Q3
FDS8880
Q2
FDS8880
Q5
FDS6982AS-Q2
Q4
FDS6982AS-Q1
Q1
FDS8880
2EN1
8BST1
9DH1
15 PGOOD2
19
RT
18
COMP2
16
VCC
11
BST2
10
DH2
17
FB2
7
LX1
12
LX2
5
DL1
6
PGND1
14
DL2
13
PGND2
24
COMP1
23
LIM1
21
IN
1
FB1
1F
16.2k
47k
200k
30.1k
20k
2200pF
1.5
RT
33k
10F
25V
2200pF
3300pF
22pF
CBST1
0.22F
CBST2
0.22F
4.7F
10F
25V
20
SGND
22
LIM2
12.1k
12.1k
EN1
VOUT1
VOUT2
VCC
PGOOD2
VCC
VIN
VIN
9V TO 16V
3EN2
4PGOOD1
47k
200k
22.1k
10k
45.3k
1.62k
EN2
DL1
PGOOD1
VOUT1
VCC
0.8H 3.3H
VIN
22F
6.3V
1500F
2.5V
22F
6.3V
22F
6.3V
22F
6.3V
10F
25V
1.5
VOUT2
MAX15023 Wide 4.5V to 28V Input,
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Typical Application Circuits
Figure 7. Application Diagram (Operation with VIN = VCC = 5V ±10%)
MAX15023
22
DH1 LIM2
9
BST2 SGND
11
20
DH2 IN
10
21
LX2 RT
12
19
BST1 LIM1
8
23
LX1 COMP1
7
24
5 14DL1 DL2
4 15PGOOD1 PGOOD2
6 13PGND1 PGND2
3 16VCC
EN2
2 17FB2
EN1
1 18COMP2
VIN
4.5V TO 5.5V
PGOOD2
VOUT2
L2
VIN
FB1
C8
R6
C6
Q1
Q2
C2
CIN2
C3
C5
C5
R2
R4
RPU1
R8
R7
R1
R10 R9 RT
R5
EN1
PGOOD1
VOUT1
L1
EN2
CIN1
CBST1 CBST2
COUT1
C4 R3
RPU2
Q3
VIN
Q4 COUT2
MAX15023 Wide 4.5V to 28V Input,
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Typical Application Circuits (continued)
MAX15023
22
DH1 LIM2
9
BST2 SGND
11
20
DH2 IN
10
21
LX2 RT
12
19
BST1 LIM1
8
23
LX1 COMP1
7
24
5 14DL1 DL2
4 15PGOOD1 PGOOD2
6 13PGND1 PGND2
3 16VCC
EN2
2 17FB2
EN1
1 18COMP2
VAUX
4.5V TO 5.5V
PGOOD2
VOUT2
L2
VIN
3.3V
FB1
C8
R6
C6
Q1
Q2
C2
CIN2
C3
C5
C5
R2
R4
RPU1
R8
VIN
3.3V
R7
R1
R10 R9 RT
R5
EN1
PGOOD1
VOUT1
L1
EN2
CIN1
CBST1 CBST2
COUT1
C4 R3
RPU2
Q3
Q4 COUT2
Figure 8. Application Diagram (Operation with Auxiliary 5V Supply and 3.3V Bus)
MAX15023 Wide 4.5V to 28V Input,
Dual-Output Synchronous Buck Controller
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Typical Application Circuits (continued)
PACKAGE
TYPE
PACKAGE
CODE OUTLINE NO. LAND
PATTERN NO.
24 TQFN-EP T2444+4 21-0139 90-0022
MAX15023 Wide 4.5V to 28V Input,
Dual-Output Synchronous Buck Controller
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Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages.
Note that a “+”, “#”, or “-” in the package code indicates
RoHS status only. Package drawings may show a different
suffix character, but the drawing pertains to the package
regardless of RoHS status.
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 7/08 Initial release —
1 2/09 Updated Electrical Characteristics, Current-Limit Circuit (LIM_), and
Setting the Enable Input (EN_) sections. 4, 15, 16
2 3/11 Added automotive part MAX5023ETG/V+ 1, 2, 13, 27
3 4/15 Added automotive designation footnote 1
MAX15023 Wide 4.5V to 28V Input,
Dual-Output Synchronous Buck Controller
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. © 2015 Maxim Integrated Products, Inc.
│
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Revision History
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
