STIPNS2M50T-H SLLIMMTM-nano small low-loss intelligent molded module IPM, 3-phase inverter, 2 A, 1.7 max., 500 V MOSFET Datasheet - production data Applications 16 17 1 26 Description NSDIP-26L Features 3-phase inverters for small power motor drives Dish washers, refrigerator compressors, heating systems, air-conditioning fans, draining and recirculation pumps IPM 2 A, 500 V, RDS(on) = 1.7 , 3-phase MOSFET inverter bridge including control ICs for gate driving Optimized for low electromagnetic interference 3.3 V, 5 V, 15 V CMOS/TTL input comparators with hysteresis and pulldown/pull-up resistors Undervoltage lockout Internal bootstrap diode Interlocking function Comparator for fault protection against overtemperature and overcurrent Op-amp for advanced current sensing Optimized pinout for easy board layout NTC for temperature control (UL 1434 CA 2 and 4) Moisture sensitivity level (MSL) 3 This SLLIMM (small low-loss intelligent molded module) nano provides a compact, high performance AC motor drive in a simple, rugged design. It is composed of six MOSFETs and three half-bridge HVICs for gate driving, providing low electromagnetic interference (EMI) characteristics with optimized switching speed. The package is optimized for thermal performance and compactness in built-in motor applications, or other low power applications where assembly space is limited. This IPM includes an operational amplifier, completely uncommitted, and a comparator that can be used to design a fast and efficient protection circuit. SLLIMMTM is a trademark of STMicroelectronics. Table 1: Device summary Order code Marking Package Packing STIPNS2M50T-H IPNS2M50T-H NSDIP-26L Tape and reel January 2018 DocID030525 Rev 2 This is information on a product in full production. 1/24 www.st.com Contents STIPNS2M50T-H Contents 1 Internal schematic diagram and pin configuration ....................... 3 2 Electrical ratings ............................................................................. 6 3 2.1 Absolute maximum ratings ................................................................ 6 2.2 Thermal data ..................................................................................... 6 Electrical characteristics ................................................................ 7 3.1 Inverter part ....................................................................................... 7 3.2 Control part ....................................................................................... 9 3.2.1 3.3 NTC thermistor ................................................................................. 11 Waveform definitions....................................................................... 14 4 Smart shutdown function ............................................................. 15 5 Application circuit example .......................................................... 17 5.1 6 Package information ..................................................................... 20 6.1 7 2/24 Guidelines ....................................................................................... 18 NSDIP-26L package information ..................................................... 20 Revision history ............................................................................ 23 DocID030525 Rev 2 STIPNS2M50T-H 1 Internal schematic diagram and pin configuration Internal schematic diagram and pin configuration Figure 1: Internal schematic diagram (26)NW GND(1) T/SD/OD(2) NTC (25)W,OUTW GND VccW(3) HVG OUT HinW(4) (24)VbootW VCC HIN LVG SD/OD LinW(5) LIN Vboot OP+(6) (23)NV OPOUT(7) GND OP+ OPOUT OP-(8) OP- HVG (22)V,OUTV OUT VCC VccV(9) HIN LVG SD/OD HinV(10) LIN Vboot (21)VbootV LinV(11) Cin(12) (20)NU GND CIN HVG VccU(13) OUT (19)U,OUTU VCC HinU(14) HIN LVG SD/OD LIN Vboot (18)P T/SD/OD(15) LinU(16) (17)VbootU GIPD120120170806S A DocID030525 Rev 2 3/24 Internal schematic diagram and pin configuration STIPNS2M50T-H Table 2: Pin description 4/24 Pin Symbol Description 1 GND 2 /OD T/SD 3 VCC W Low-voltage power supply W phase 4 HIN W High-side logic input for W phase 5 LIN W Low-side logic input for W phase 6 OP+ 7 OPOUT 8 OP- Ground NTC thermistor terminal / shutdown logic input (active low) / open-drain (comparator output) Op-amp non inverting input Op-amp output Op-amp inverting input 9 VCC V Low-voltage power supply V phase 10 HIN V High-side logic input for V phase 11 LIN V Low-side logic input for V phase 12 CIN 13 VCC U Low-voltage power supply for U phase 14 HIN U High-side logic input for U phase 15 /OD T/SD 16 LIN U 17 VBOOT U 18 P 19 U, OUTU 20 NU Negative DC input for U phase 21 VBOOT V Bootstrap voltage for V phase 22 V, OUTV V phase output Comparator input NTC thermistor terminal / shutdown logic input (active low) / open-drain (comparator output) Low-side logic input for U phase Bootstrap voltage for U phase Positive DC input U phase output 23 NV Negative DC input for V phase 24 VBOOT W Bootstrap voltage for W phase 25 W, OUTW W phase output 26 NW Negative DC input for W phase DocID030525 Rev 2 STIPNS2M50T-H Internal schematic diagram and pin configuration Figure 2: Pin layout (top view) (*) (*) PIN #1 ID (*) Dummy pin internally connected to P (positive DC input). DocID030525 Rev 2 5/24 Electrical ratings STIPNS2M50T-H 2 Electrical ratings 2.1 Absolute maximum ratings Table 3: Inverter part Symbol Parameter Value Unit 500 V VDSS MOSFET blocking voltage (or drain-source voltage) for each MOSFET (VIN(1)= 0) ID Continuous current each MOSFET 2 A IDP(2) Peak drain current each MOSFET (less than 1 ms) 4 A 10.4 W PTOT Each MOSFET total dissipation at TC = 25 C Notes: (1)Applied (2)Pulse among HINi, LINi and GND for i = U, V, W. width limited by max. junction temperature. Table 4: Control part Symbol Parameter Min. Max. Unit VOUT Output voltage applied among OUTU, OUTV, OUTW - GND Vboot - 21 Vboot + 0.3 V VCC Low voltage power supply - 0.3 21 V VCIN Comparator input voltage - 0.3 VCC + 0.3 V Vop+ Op-amp non-inverting input - 0.3 VCC + 0.3 V Vop- Op-amp inverting input - 0.3 VCC + 0.3 V Vboot Bootstrap voltage - 0.3 620 V Logic input voltage applied among HIN, LIN and GND - 0.3 15 V / / Open-drain voltage - 0.3 15 V VOUT/dT Allowed output slew rate 50 V/ns Value Unit 1000 V VIN Table 5: Total system Symbol VISO 2.2 Parameter Isolation withstand voltage applied between each pin and heatsink plate (AC voltage, t = 60 s) Tj Power chip operating junction temperature -40 to 150 C TC Module case operation temperature -40 to 125 C Thermal data Table 6: Thermal data Symbol Rth(j-c) 6/24 Parameter Thermal resistance junction-case DocID030525 Rev 2 Value Unit 12 C/W STIPNS2M50T-H Electrical characteristics 3 Electrical characteristics 3.1 Inverter part TJ = 25 C unless otherwise specified Table 7: Static Symbol Parameter Test conditions Min. Typ. Max. Unit IDSS Zero-gate voltage drain current VDS = 500 V, VCC = 15 V, VBoot = 15 V 1 mA V(BR)DSS Drain-source breakdown voltage VCC= Vboot = 15 V, VIN(1) = 0 V, ID = 1 mA RDS(on) Static drain-source turn-on resistance VCC = Vboot = 15 V, VIN(1)= 0 - 5 V, ID = 1.2 A 1.5 1.7 VSD Drain-source diode forward voltage VIN(1) = 0 "logic state", ID = 2 A 0.9 1.6 V Min. Typ. Max. Unit - 267 - - 153 - - 265 - - 46 - - 192 - - 61 - - 4 - 500 V Notes: (1)Applied among HINx, LINx and GND for x = U, V, W. Table 8: Inductive load switching time and energy Symbol ton (1) tc(on)(1) toff (1) tc(off)(1) trr Parameter Test conditions Turn-on time Crossover time (on) Turn-off time Crossover time (off) Reverse recovery time Eon Turn-on switching energy Eoff Turn-off switching energy VDD = 300 V, VCC = Vboot = 15 V, VIN(2) = 0 - 5 V, IC = 1.2 A (see Figure 4: "Switching time definition") ns J Notes: (1)t ON and tOFF include the propagation delay time of the internal drive. t C(ON) and tC(OFF) are the switching time of MOSFET itself under the internally given gate driving conditions. (2)Applied among HINx, LINx and GND for x = U, V, W. DocID030525 Rev 2 7/24 Electrical characteristics STIPNS2M50T-H Figure 3: Switching time test circuit 5V Input 0V Ic Vboot LIN +Vcc RSD + SD/OD +5V HIN Vboot>Vcc HVG - L VCC OUT + LVG + Vds Vdd C - - GND GIPD161120151702RV Figure 4: Switching time definition 100% ID 100%ID t rr ID VDS VDS ID VIN VIN t ON t OFF t C(OFF) t C(ON) VIN(ON) 10% ID 90%ID 10%VDS (a) turn-on VIN(OFF) 10%VDS (b) turn-off Figure 4: "Switching time definition" refers to HIN, LIN inputs (active high). 8/24 DocID030525 Rev 2 10%ID AM09223V2 STIPNS2M50T-H 3.2 Electrical characteristics Control part VCC = 15 V unless otherwise specified Table 9: Low voltage power supply Symbol Parameter Test conditions Min. Typ. Max. Unit VCC_hys VCC UV hysteresis 1.2 1.5 1.8 V VCC_thON VCC UV turn-ON threshold 11.5 12 12.5 V VCC_thOFF VCC UV turn-OFF threshold 10 10.5 11 V Iqccu Undervoltage quiescent supply current /OD = 5 V; VCC = 10 V, T/SD LIN = 0 V; HIN = 0, CIN = 0 150 A Iqcc Quiescent current /OD = 5 V; Vcc = 15 V, T/SD LIN = 0 V; HIN = 0, CIN = 0 1 mA Vref Internal comparator (CIN) reference voltage 0.5 0.54 0.58 V Min. Typ. Max. Unit Table 10: Bootstrapped voltage Symbol Parameter Test conditions VBS_hys VBS UV hysteresis 1.2 1.5 1.8 V VBS_thON VBS UV turn-ON threshold 11.1 11.5 12.1 V VBS_thOFF VBS UV turn-OFF threshold 9.8 10 10.6 V 70 110 A 300 A IQBSU Undervoltage VBS quiescent current /OD = 5 V; VBS < 9 V T/SD LIN = 0 V and HIN = 5 V; CIN = 0 IQBS VBS quiescent current /OD = 5 V; VBS = 15 V T/SD LIN = 0 V and HIN = 5 V; CIN = 0 200 Bootstrap driver onresistance LVG ON 120 RDS(on) Table 11: Logic inputs Symbol Parameter Vil Low logic level voltage Vih High logic level voltage Test conditions HIN logic "1" input bias current HIN = 15 V IHINI HIN logic "0" input bias current HIN = 0 V ILINI LIN logic "1" input bias current LIN = 15 V ILINh LIN logic "0" input bias current LIN = 0 V logic "0" input bias = 15 V SD SD Typ. Max. Unit 0.8 V 2.25 IHINh ISDh Min. 20 20 220 V 40 40 295 100 A 1 A 100 A 1 A 370 A 3 A current ISDI SD logic "1" input bias SD = 0 V current Dt Dead time See Figure 9: "Dead time and interlocking waveform definitions" DocID030525 Rev 2 180 ns 9/24 Electrical characteristics STIPNS2M50T-H Table 12: Op-amp characteristics Parameter Symbol Vio Input offset voltage Iio Input offset current Iib Input bias current (1) Test conditions Min. Typ. Vic = 0 V, Vo = 7.5 V Vic = 0 V, Vo = 7.5 V Max. Unit 6 mV 4 40 nA 100 200 nA 75 150 mV VOL Low level output voltage RL = 10 k to VCC VOH High level output voltage RL = 10 k to GND 14 14.7 V Output short-circuit current Source, Vid = +1 V; Vo = 0 V 16 30 mA Sink, Vid = -1 V; Vo = VCC 50 80 mA Slew rate Vi = 1 - 4 V; CL = 100 pF; unity gain 2.5 3.8 V/s GBWP Gain bandwidth product Vo = 7.5 V 8 12 MHz Avd Large signal voltage gain RL = 2 k 70 85 dB Supply voltage rejection ratio vs. VCC 60 75 dB 55 70 dB Min. Typ. Io SR SVR Common mode rejection ratio CMRR Notes: (1)The direction of the input current is out of the IC. Table 13: Sense comparator characteristics Symbol Iib Parameter Test conditions Unit Input bias current VCIN = 1 V 1 A Vod Open-drain low level output voltage Iod = 3 mA 0.5 V RON_OD Open-drain low level output resistance Iod = 3 mA RPD_SD pull-down resistor (1) SD td_comp Comparator delay /OD pulled to 5 V T/SD through 100 k resistor 90 SR Slew rate CL = 180 pF; Rpu = 5 k 60 tsd Shutdown to high- / low-side driver propagation delay VOUT = 0, Vboot = VCC, VIN = 0 to 3.3 V 50 125 200 tisd Comparator triggering to high/ low-side driver turn-off propagation delay Measured applying a voltage step from 0 V to 3.3 V to pin CIN 50 200 250 Notes: (1)Equivalent 10/24 Max. values are as a result of the resistances of three drivers in parallel. DocID030525 Rev 2 166 125 k 130 ns V/s ns STIPNS2M50T-H Electrical characteristics Table 14: Truth table Logic input (VI) Conditions Output /OD T/ LIN HIN LVG HVG Shutdown enable half-bridge tri-state L X(1) X(1) L L Interlocking half-bridge tri-state H H H L L 0 "logic state" half-bridge tri-state H L L L L 1 "logic state" low-side direct driving H H L H L 1 "logic state" high-side direct driving H L H L H Notes: (1)X: 3.2.1 do not care. NTC thermistor Figure 5: Internal structure of and NTC Vbias R SD LIN VT/SD/OD Vboot SD/OD C SD NTC HIN HVG VCC OUT RPD_SD LVG GND CIN RPD_SD: equivalent value as result of resistances of three drivers in parallel. DocID030525 Rev 2 11/24 Electrical characteristics STIPNS2M50T-H Figure 6: Equivalent resistance (NTC//RPD_SD) Figure 7: Equivalent resistance (NTC//RPD_SD) zoom 12/24 DocID030525 Rev 2 STIPNS2M50T-H Electrical characteristics /OD pin according to NTC temperature Figure 8: Voltage of T/ DocID030525 Rev 2 13/24 Electrical characteristics 3.3 STIPNS2M50T-H Waveform definitions Figure 9: Dead time and interlocking waveform definitions 14/24 DocID030525 Rev 2 STIPNS2M50T-H 4 Smart shutdown function Smart shutdown function The device integrates a comparator for fault sensing purposes. The comparator has an internal voltage reference VREF connected to the inverting input, while the non-inverting input on pin (CIN) can be connected to an external shunt resistor for the overcurrent protection. When the comparator triggers, the device is set to the shutdown state and both of its outputs are set to low level, causing the half-bridge to enter a tri-state. In common overcurrent protection architectures, the comparator output is usually connected to the shutdown input through an RC network so to provide a mono-stable circuit which implements a protection time following to a fault condition. Our smart shutdown architecture immediately turns off the output gate driver in case of overcurrent through a preferential path for the fault signal which directly switches off the outputs. The time delay between the fault and output shutdown no longer depends on the RC values of the external network connected to the shutdown pin. At the same time, the /OD) is turned on by the internal logic, DMOS connected to the open-drain output (pin T/SD which holds it on until the shutdown voltage is well below the minimum value of logic input threshold (Vil). Besides, the smart shutdown function allows the real disable time to be increased without rising the constant time of the external RC network. An NTC thermistor for temperature monitoring is internally connected in parallel to the SD pin. To avoid undesired shutdown, keep the voltage / / higher than the high-level logic threshold by setting the pull-up resistor to 1 k or 2.2 k for 3.3 V or 5 V MCU power supplies respectively. DocID030525 Rev 2 15/24 Smart shutdown function STIPNS2M50T-H Figure 10: Smart shutdown timing waveforms com p Vref C P+ H IN /LIN PROTECTION H VG/LVG SD /OD open-drain gate (internal) disable tim e Fast shutdown: the driver outputs are set to the SD state as soon as the com parator triggers even if the SD signal hasn't reached the low est input threshold An approximation of the disable time is given by: SHUTDOW N CIRCUIT Vbias R SD T/SD/ O D V T/SD/OD SMART SD C SD NTC RPD_SD RON_OD LOGIC GIPG080920140931FSR Please refer to Table 13: "Sense comparator characteristics" for internal propagation delay time details. 16/24 DocID030525 Rev 2 DocID030525 Rev 2 RS 5V/3.3 V R2 + - Vcc CSD RSD Cvc c R1 R3 HIN W 5V/3.3 V R1 R1 LinU(16) C OP OP-(8 ) VccV(9) C1 C1 VccW(3 ) HinW(4 ) LinW(5 ) OP+(6 ) OPOUT(7 ) C1 HinV(10) C1 LinV(11) CSF Cin(12 ) VccU(13) C1 HinU(14 ) T/SD/OD(15 ) C1 DZ1 SGN_GND GND(1 ) T/SD/OD(2 ) RSF C2 ADC R5 R4 R1 R1 SD Temp. Monitoring MICROCONTROLLER LIN W ADC HIN V LIN V R1 HIN U RS R1 NTC LIN GND VCC HIN SD/OD LIN GND OPOUT OP- VCC HIN SD/OD LIN GND VCC HIN SD/OD LVG OUT HVG Vboot OP+ LVG OUT HVG Vboot CIN LVG OUT HVG Vboot Cboot U RS (26)NW (25)W,OUT W Cboot W (24)VbootW (23)N V (22)V,OUT V Cboot V (21)Vboot V (20)N U (19)U,OUT U (18)P (17)Vboot U C3 C3 C3 DZ2 DZ2 DZ2 PWR_GND Rshun t M C4 VDC Cvd c + - 5 LIN U STIPNS2M50T-H Application circuit example Application circuit example Figure 11: Application circuit example GADG100620160912FSR Application designers are free to use a different scheme according to the device specifications. 17/24 Application circuit example 5.1 STIPNS2M50T-H Guidelines Input signals HIN, LIN are active high logic. A 375 k (typ.) pull-down resistor is builtin for each input. To prevent input signal oscillations, the wiring of each input should be as short as possible and the use of RC filters (R1, C1) on each input signal is suggested. The filters should be within a time constant of about 100 ns and placed as close as possible to the IPM input pins. The use of a bypass capacitor CVCC (aluminum or tantalum) can help to reduce the transient circuit demand on the power supply. Besides, to reduce high frequency switching noise distributed on the power lines, a decoupling capacitor C2 (100 to 220 nF, with low ESR and low ESL) should be placed as close as possible to the V cc pin and in parallel with the bypass capacitor. The use of an RC filter (RSF, CSF) for circuit malfunction protection is recommended. The time constant (RSF x CSF) should be set to 1 s and the filter must be placed as close as possible to the CIN pin. The SD is an input/output pin (open-drain type if used as output). A built-in thermistor NTC is internally connected between the SD pin and GND. The VSD-GND voltage decreases as the temperature increases, due to the RSD pull-up resistor. In order to keep the voltage always higher than the high level logic threshold, the pull-up resistor is suggested to be set to 1 k or 2.2 k for an MCU power supply of 3.3 V or 5 V should be fixed no higher than 3.3 respectively. The CSD capacitor of the filter on SD activation time of 1 500 ns and the filter should be nF in order to assure an SD pin. placed as close as possible to the SD The decoupling capacitor C3 (from 100 to 220 nF, ceramic with low ESR and low ESL), in parallel with each Cboot, filters high frequency disturbance. Both Cboot and C3 (if present) should be placed as close as possible to the U, V, W and Vboot pins. Bootstrap negative electrodes should be connected to the U, V, W terminals directly and separated from the main output wires. To prevent overvoltage on the Vcc pin, a Zener diode (Dz1) can be used. Similarly, a Zener diode (Dz2) can be placed on the Vboot pin in parallel with each Cboot. The use of decoupling capacitor C4 (100 to 220 nF, with low ESR and low ESL) in parallel with the electrolytic capacitor Cvdc is useful to prevent surge destruction. Both capacitors C4 and Cvdc should be placed as close as possible to the IPM (C4 has priority over Cvdc). By integrating an application-specific type HVIC inside the module, direct coupling to the MCU terminals without an optocoupler is possible. Use low inductance shunt resistors for phase leg current sensing. In order to avoid malfunctions, the wiring on N pins, the shunt resistor and PWR_GND should be as short as possible. The connection of SGN_GND to PWR_GND to one point only (close to the shunt resistor terminal) can help to reduce the impact of power ground fluctuation. These guidelines ensure the device specifications for application designs. For further details, please refer to the relevant application note. 18/24 DocID030525 Rev 2 STIPNS2M50T-H Application circuit example Table 15: Recommended operating conditions Symbol Parameter Test conditions Min. VPN Supply voltage Applied among P-Nu, Nv, Nw VCC Control supply voltage Applied to VCC-GND VBS High-side bias voltage Applied to VBOOTi-OUTi for i = U, V, W 13 tdead Blanking time to prevent arm-short For each input signal 1 fPWM PWM input signal -40 C < Tc < 100 C -40 C < Tj < 125 C TC Case operation temperature DocID030525 Rev 2 13.5 Typ. Max. Unit 300 400 V 15 18 V 18 V s 25 kHz 100 C 19/24 Package information 6 STIPNS2M50T-H Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK (R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. 6.1 NSDIP-26L package information Figure 12: NSDIP-26L package outline 20/24 DocID030525 Rev 2 STIPNS2M50T-H Package information Table 16: NSDIP-26L package mechanical data mm Dim. Min. Typ. A Max. 3.45 A1 0.10 0.25 A2 3.00 3.10 3.20 A3 1.70 1.80 1.90 b 0.47 b1 0.45 b2 0.63 0.67 c 0.47 0.57 c1 0.45 0.50 0.55 D 29.05 29.15 29.25 D1 0.70 D2 0.45 D3 0.90 0.57 0.50 D4 0.55 29.65 E 12.35 12.45 12.55 E1 16.70 17.00 17.30 E2 0.35 e 1.70 1.80 1.90 e1 2.40 2.50 2.60 L 1.24 1.39 1.54 L1 1.00 1.15 1.30 L2 0.25 BSC L3 2.275 REF R1 0.25 0.40 0.55 R2 0.25 0.40 0.55 0.39 0.55 S 0 1 2 8 3 BSC 10 DocID030525 Rev 2 12 14 21/24 Package information STIPNS2M50T-H Figure 13: NSDIP-26L recommended footprint (dimensions are in mm) 22/24 DocID030525 Rev 2 STIPNS2M50T-H 7 Revision history Revision history Table 17: Document revision history Date Revision 19-Apr-2017 1 Initial release 2 Datasheet status promoted from preliminary to production data. Updated features on cover page. Updated Table 3: "Inverter part", Table 5: "Total system", Table 6: "Thermal data" and Table 13: "Sense comparator characteristics". Updated Section 6.1: "NSDIP-26L package information". 04-Jan-2018 Changes DocID030525 Rev 2 23/24 STIPNS2M50T-H IMPORTANT NOTICE - PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST's terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers' products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. (c) 2018 STMicroelectronics - All rights reserved 24/24 DocID030525 Rev 2