January 2018
DocID030525 Rev 2
1/24
This is information on a product in full production.
www.st.com
STIPNS2M50T-H
SLLIMM™-nano small low-loss intelligent molded module IPM,
3-phase inverter, 2 A, 1.7 Ω max., 500 V MOSFET
Datasheet - production data
Features
IPM 2 A, 500 V, RDS(on) = 1.7 Ω, 3-phase
MOSFET inverter bridge including control
ICs for gate driving
Optimized for low electromagnetic
interference
3.3 V, 5 V, 15 V CMOS/TTL input
comparators with hysteresis and pull-
down/pull-up resistors
Undervoltage lockout
Internal bootstrap diode
Interlocking function
Comparator for fault protection against
overtemperature and overcurrent
Op-amp for advanced current sensing
Optimized pinout for easy board layout
NTC for temperature control (UL 1434
CA 2 and 4)
Moisture sensitivity level (MSL) 3
Applications
3-phase inverters for small power motor
drives
Dish washers, refrigerator compressors,
heating systems, air-conditioning fans,
draining and recirculation pumps
Description
This SLLIMM (small low-loss intelligent molded
module) nano provides a compact, high
performance AC motor drive in a simple, rugged
design. It is composed of six MOSFETs and three
half-bridge HVICs for gate driving, providing low
electromagnetic interference (EMI) characteristics
with optimized switching speed. The package is
optimized for thermal performance and
compactness in built-in motor applications, or
other low power applications where assembly
space is limited. This IPM includes an operational
amplifier, completely uncommitted, and a
comparator that can be used to design a fast and
efficient protection circuit. SLLIMM™ is a
trademark of STMicroelectronics.
Table 1: Device summary
Order code
Package
Packing
STIPNS2M50T-H
IPNS2M50T-H
NSDIP-26L
Tape and reel
NSDIP-26L
1
16
17
26
Contents
STIPNS2M50T-H
2/24
DocID030525 Rev 2
Contents
1 Internal schematic diagram and pin configuration ....................... 3
2 Electrical ratings ............................................................................. 6
2.1 Absolute maximum ratings ................................................................ 6
2.2 Thermal data ..................................................................................... 6
3 Electrical characteristics ................................................................ 7
3.1 Inverter part ....................................................................................... 7
3.2 Control part ....................................................................................... 9
3.2.1 NTC thermistor ................................................................................. 11
3.3 Waveform definitions ....................................................................... 14
4 Smart shutdown function ............................................................. 15
5 Application circuit example .......................................................... 17
5.1 Guidelines ....................................................................................... 18
6 Package information ..................................................................... 20
6.1 NSDIP-26L package information ..................................................... 20
7 Revision history ............................................................................ 23
STIPNS2M50T-H
Internal schematic diagram and pin
configuration
DocID030525 Rev 2
3/24
1 Internal schematic diagram and pin configuration
Figure 1: Internal schematic diagram
NTC
GND(1)
T/SD/OD(2)
VccW(3)
HinW(4)
LinW(5)
OP+(6)
OPOUT(7)
OP-(8)
VccV(9)
HinV(10)
LinV(11)
Cin(12)
VccU(13)
HinU(14)
T/SD/OD(15)
LinU(16) (17)VbootU
(18)P
(19)U,OUTU
(20)NU
(21)VbootV
(22)V,OUTV
(23)NV
(24)VbootW
(25)W,OUTW
(26)NW
GND
LIN
VCC
HVG
CIN
SD/OD
OUT
LVG
Vboot
HIN
GND
OPOUT
LIN
VCC
HVG
OP+
OP-
SD/OD
OUT
LVG
Vboot
HIN
GND
LIN
VCC
HVG
SD/OD
OUT
LVG
Vboot
HIN
GIPD120120170806SA
Internal schematic diagram and pin
configuration
STIPNS2M50T-H
4/24
DocID030525 Rev 2
Table 2: Pin description
Pin
Symbol
Description
1
GND
Ground
2
T/SD
/OD
NTC thermistor terminal / shutdown logic input (active low) / open-drain
(comparator output)
3
VCC W
Low-voltage power supply W phase
4
HIN W
High-side logic input for W phase
5
LIN W
Low-side logic input for W phase
6
OP+
Op-amp non inverting input
7
OPOUT
Op-amp output
8
OP-
Op-amp inverting input
9
VCC V
Low-voltage power supply V phase
10
HIN V
High-side logic input for V phase
11
LIN V
Low-side logic input for V phase
12
CIN
Comparator input
13
VCC U
Low-voltage power supply for U phase
14
HIN U
High-side logic input for U phase
15
T/SD
/OD
NTC thermistor terminal / shutdown logic input (active low) / open-drain
(comparator output)
16
LIN U
Low-side logic input for U phase
17
VBOOT U
Bootstrap voltage for U phase
18
P
Positive DC input
19
U, OUTU
U phase output
20
NU
Negative DC input for U phase
21
VBOOT V
Bootstrap voltage for V phase
22
V, OUTV
V phase output
23
NV
Negative DC input for V phase
24
VBOOT W
Bootstrap voltage for W phase
25
W, OUTW
W phase output
26
NW
Negative DC input for W phase
STIPNS2M50T-H
Internal schematic diagram and pin
configuration
DocID030525 Rev 2
5/24
Figure 2: Pin layout (top view)
(*) (*)
(*) Dummy pin internally connected toP (positive DC input).
PIN #1 ID
Electrical ratings
STIPNS2M50T-H
6/24
DocID030525 Rev 2
2 Electrical ratings
2.1 Absolute maximum ratings
Table 3: Inverter part
Symbol
Parameter
Value
Unit
VDSS
MOSFET blocking voltage (or drain-source voltage) for each MOSFET
(VIN(1)= 0)
500
V
± ID
Continuous current each MOSFET
2
A
± IDP(2)
Peak drain current each MOSFET (less than 1 ms)
4
A
PTOT
Each MOSFET total dissipation at TC = 25 °C
10.4
W
Notes:
(1)Applied among HINi, LINi and GND for i = U, V, W.
(2)Pulse width limited by max. junction temperature.
Table 4: Control part
Symbol
Parameter
Min.
Max.
Unit
VOUT
Output voltage applied among OUTU, OUTV, OUTW - GND
Vboot - 21
Vboot + 0.3
V
VCC
Low voltage power supply
- 0.3
21
V
VCIN
Comparator input voltage
- 0.3
VCC + 0.3
V
Vop+
Op-amp non-inverting input
- 0.3
VCC + 0.3
V
Vop-
Op-amp inverting input
- 0.3
VCC + 0.3
V
Vboot
Bootstrap voltage
- 0.3
620
V
VIN
Logic input voltage applied among HIN, LIN and GND
- 0.3
15
V
𝑉𝑇/𝑆𝐷
/𝑂𝐷
Open-drain voltage
- 0.3
15
V
∆VOUT/dT
Allowed output slew rate
50
V/ns
Table 5: Total system
Symbol
Parameter
Value
Unit
VISO
Isolation withstand voltage applied between each pin and heatsink
plate (AC voltage, t = 60 s)
1000
V
Tj
Power chip operating junction temperature
-40 to 150
°C
TC
Module case operation temperature
-40 to 125
°C
2.2 Thermal data
Table 6: Thermal data
Symbol
Parameter
Value
Unit
Rth(j-c)
Thermal resistance junction-case
12
°C/W
STIPNS2M50T-H
Electrical characteristics
DocID030525 Rev 2
7/24
3 Electrical characteristics
3.1 Inverter part
TJ = 25 °C unless otherwise specified
Table 7: Static
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
IDSS
Zero-gate voltage drain current
VDS = 500 V, VCC = 15 V,
VBoot = 15 V
1
mA
V(BR)DSS
Drain-source breakdown
voltage
VCC= Vboot = 15 V,
VIN(1) = 0 V, ID = 1 mA
500
V
RDS(on)
Static drain-source turn-on
resistance
VCC = Vboot = 15 V,
VIN(1)= 0 - 5 V, ID = 1.2 A
1.5
1.7
Ω
VSD
Drain-source diode forward
voltage
VIN(1) = 0 “logic state”,
ID = 2 A
0.9
1.6
V
Notes:
(1)Applied among HINx, LINx and GND for x = U, V, W.
Table 8: Inductive load switching time and energy
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
ton(1)
Turn-on time
VDD = 300 V,
VCC = Vboot = 15 V,
VIN(2) = 0 - 5 V, IC = 1.2 A
(see Figure 4: "Switching time
definition")
-
267
-
ns
tc(on)(1)
Crossover time (on)
-
153
-
toff(1)
Turn-off time
-
265
-
tc(off)(1)
Crossover time (off)
-
46
-
trr
Reverse recovery time
-
192
-
Eon
Turn-on switching energy
-
61
-
µJ
Eoff
Turn-off switching energy
-
4
-
Notes:
(1)tON and tOFF include the propagation delay time of the internal drive. tC(ON) and tC(OFF) are the switching time of
MOSFET itself under the internally given gate driving conditions.
(2)Applied among HINx, LINx and GND for x = U, V, W.
Electrical characteristics
STIPNS2M50T-H
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DocID030525 Rev 2
Figure 3: Switching time test circuit
Figure 4: Switching time definition
Figure 4: "Switching time definition" refers to HIN, LIN inputs (active high).
+5V
+Vcc
Input
Vdd
C
L
Vboot>Vcc
5V
0V
+
-
Vds
Ic
+
-
RSD
GND
LIN
VCC
LVG
SD/OD
OUT
HVG
Vboot
HIN
+
-
GIPD161120151702RV
VDS IDID
VIN
tON tC(ON)
VIN(ON) 10% ID90%ID10%VDS
(a) turn-on (b) turn-off
trr
100% ID100%ID
VIN
VDS
tOFF tC(OFF)
VIN(OFF) 10%VDS 10%ID
AM09223V2
STIPNS2M50T-H
Electrical characteristics
DocID030525 Rev 2
9/24
3.2 Control part
VCC = 15 V unless otherwise specified
Table 9: Low voltage power supply
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
VCC_hys
VCC UV hysteresis
1.2
1.5
1.8
V
VCC_thON
VCC UV turn-ON threshold
11.5
12
12.5
V
VCC_thOFF
VCC UV turn-OFF threshold
10
10.5
11
V
Iqccu
Undervoltage quiescent
supply current
VCC = 10 V, T/SD
/OD = 5 V;
LIN = 0 V; HIN = 0, CIN = 0
150
µA
Iqcc
Quiescent current
Vcc = 15 V, T/SD
/OD = 5 V;
LIN = 0 V; HIN = 0, CIN = 0
1
mA
Vref
Internal comparator (CIN)
reference voltage
0.5
0.54
0.58
V
Table 10: Bootstrapped voltage
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
VBS_hys
VBS UV hysteresis
1.2
1.5
1.8
V
VBS_thON
VBS UV turn-ON threshold
11.1
11.5
12.1
V
VBS_thOFF
VBS UV turn-OFF threshold
9.8
10
10.6
V
IQBSU
Undervoltage VBS quiescent
current
VBS < 9 V T/SD
/OD = 5 V;
LIN = 0 V and HIN = 5 V;
CIN = 0
70
110
µA
IQBS
VBS quiescent current
VBS = 15 V T/SD
/OD = 5 V;
LIN = 0 V and HIN = 5 V;
CIN = 0
200
300
µA
RDS(on)
Bootstrap driver on-
resistance
LVG ON
120
Ω
Table 11: Logic inputs
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
Vil
Low logic level voltage
0.8
V
Vih
High logic level voltage
2.25
V
IHINh
HIN logic “1” input bias current
HIN = 15 V
20
40
100
µA
IHINI
HIN logic “0” input bias current
HIN = 0 V
1
µA
ILINI
LIN logic “1” input bias current
LIN = 15 V
20
40
100
µA
ILINh
LIN logic “0” input bias current
LIN = 0 V
1
µA
ISDh
SD logic “0” input bias
current
SD
= 15 V
220
295
370
µA
ISDI
SD logic “1” input bias
current
SD
= 0 V
3
µA
Dt
Dead time
See Figure 9: "Dead time
and interlocking
waveform definitions"
180
ns
Electrical characteristics
STIPNS2M50T-H
10/24
DocID030525 Rev 2
Table 12: Op-amp characteristics
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
Vio
Input offset voltage
Vic = 0 V, Vo = 7.5 V
6
mV
Iio
Input offset current
Vic = 0 V, Vo = 7.5 V
4
40
nA
Iib
Input bias current (1)
100
200
nA
VOL
Low level output voltage
RL = 10 kΩ to VCC
75
150
mV
VOH
High level output voltage
RL = 10 kΩ to GND
14
14.7
V
Io
Output short-circuit current
Source, Vid = +1 V;
Vo = 0 V
16
30
mA
Sink, Vid = -1 V; Vo = VCC
50
80
mA
SR
Slew rate
Vi = 1 - 4 V; CL = 100 pF;
unity gain
2.5
3.8
V/µs
GBWP
Gain bandwidth product
Vo = 7.5 V
8
12
MHz
Avd
Large signal voltage gain
RL = 2 kΩ
70
85
dB
SVR
Supply voltage rejection ratio
vs. VCC
60
75
dB
CMRR
Common mode rejection
ratio
55
70
dB
Notes:
(1)The direction of the input current is out of the IC.
Table 13: Sense comparator characteristics
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
Iib
Input bias current
VCIN = 1 V
1
µA
Vod
Open-drain low level output
voltage
Iod = 3 mA
0.5
V
RON_OD
Open-drain low level output
resistance
Iod = 3 mA
166
Ω
RPD_SD
SD
pull-down resistor (1)
125
kΩ
td_comp
Comparator delay
T/SD
/OD pulled to 5 V
through 100 kΩ resistor
90
130
ns
SR
Slew rate
CL = 180 pF; Rpu = 5 kΩ
60
V/µs
tsd
Shutdown to high- / low-side
driver propagation delay
VOUT = 0, Vboot = VCC,
VIN = 0 to 3.3 V
50
125
200
ns
tisd
Comparator triggering to high-
/ low-side driver turn-off
propagation delay
Measured applying a
voltage step from 0 V to
3.3 V to pin CIN
50
200
250
Notes:
(1)Equivalent values are as a result of the resistances of three drivers in parallel.
STIPNS2M50T-H
Electrical characteristics
DocID030525 Rev 2
11/24
Table 14: Truth table
Conditions
Logic input (VI)
Output
T/𝐒𝐃
/OD
LIN
HIN
LVG
HVG
Shutdown enable half-bridge tri-state
L
X(1)
X(1)
L
L
Interlocking half-bridge tri-state
H
H
H
L
L
0 “logic state” half-bridge tri-state
H
L
L
L
L
1 “logic state” low-side direct driving
H
H
L
H
L
1 “logic state” high-side direct driving
H
L
H
L
H
Notes:
(1)X: do not care.
3.2.1 NTC thermistor
Figure 5: Internal structure of 𝐒𝐃
and NTC
RPD_SD: equivalent value as result of resistances of three drivers in parallel.
T/SD/OD
V
Vbias
RPD_SD
NTC
LIN
HIN
VCC
GND CIN
LVG
OUT
HVG
Vboot
SD/OD
R SD
C SD
Electrical characteristics
STIPNS2M50T-H
12/24
DocID030525 Rev 2
Figure 6: Equivalent resistance (NTC//RPD_SD)
Figure 7: Equivalent resistance (NTC//RPD_SD) zoom
STIPNS2M50T-H
Electrical characteristics
DocID030525 Rev 2
13/24
Figure 8: Voltage of T/𝐒𝐃
/OD pin according to NTC temperature
Electrical characteristics
STIPNS2M50T-H
14/24
DocID030525 Rev 2
3.3 Waveform definitions
Figure 9: Dead time and interlocking waveform definitions
STIPNS2M50T-H
Smart shutdown function
DocID030525 Rev 2
15/24
4 Smart shutdown function
The device integrates a comparator for fault sensing purposes. The comparator has an
internal voltage reference VREF connected to the inverting input, while the non-inverting
input on pin (CIN) can be connected to an external shunt resistor for the overcurrent
protection.
When the comparator triggers, the device is set to the shutdown state and both of its
outputs are set to low level, causing the half-bridge to enter a tri-state.
In common overcurrent protection architectures, the comparator output is usually
connected to the shutdown input through an RC network so to provide a mono-stable
circuit which implements a protection time following to a fault condition.
Our smart shutdown architecture immediately turns off the output gate driver in case of
overcurrent through a preferential path for the fault signal which directly switches off the
outputs. The time delay between the fault and output shutdown no longer depends on the
RC values of the external network connected to the shutdown pin. At the same time, the
DMOS connected to the open-drain output (pin T/SD
/OD) is turned on by the internal logic,
which holds it on until the shutdown voltage is well below the minimum value of logic input
threshold (Vil).
Besides, the smart shutdown function allows the real disable time to be increased without
rising the constant time of the external RC network.
An NTC thermistor for temperature monitoring is internally connected in parallel to the SD
pin. To avoid undesired shutdown, keep the voltage 𝑉𝑇/𝑆𝐷
/𝑂𝐷 higher than the high-level
logic threshold by setting the pull-up resistor 𝑅𝑆𝐷
to 1 kΩ or 2.2 kΩ for 3.3 V or 5 V MCU
power supplies respectively.
Smart shutdown function
STIPNS2M50T-H
16/24
DocID030525 Rev 2
Figure 10: Smart shutdown timing waveforms
Please refer to Table 13: "Sense comparator characteristics" for internal propagation delay
time details.
SHUTDOWN CIRCUIT
An approximation of the disable time is given by:
HIN/LIN
HVG/LVG
open-drain gate
(internal)
comp Vref
CP+
PROTECTION
Fast shutdown:
the driver outputs are set to the SD state as soon as the comparator
triggers even if the SD signal hasn’t reached the low est input threshold
disable time
SD/OD
GIPG080920140931FSR
T/SD/OD
V
SMART SD
LOGIC
T/SD/ OD
RPD_SD
C SD
R SD
Vbias
NTC RON_OD
STIPNS2M50T-H
Application circuit example
DocID030525 Rev 2
17/24
5 Application circuit example
Figure 11: Application circuit example
Application designers are free to use a different scheme according to the device
specifications.
RS
RS
RS
ADC
M
PWR_GND
SGN_GND
GND(1)
T/SD/OD(15)
HinW(4)
VccW(3)
OP+(6)
LinW(5)
VccV(9)
OP-(8)
OPOUT(7)
Cin(12)
LinV(11)
HinV(10)
HinU(14)
VccU(13)
LinU(16)
T/SD/OD(2 )
(17)VbootU
(18)P
(19)U,OUTU
(20)NU
(21)VbootV
(22)V,OUTV
(23)NV
(24)VbootW
(26)NW
(25)W,OUTW
R1
R1
R1
R1
R1
R1
R1 R2
R3
R4
R5
RSD
RSF
Rshun t
C1
C1
C1
C1
C1
C1
C3
C3
C3
C4
CSF
COP
CSD
CbootU
Cboot V
Cboot W
Cvdc
VDC
VccDZ1
DZ2
DZ2
DZ2
5V/3.3V
5V/3.3V
Cvcc C2
GND
LIN
VCC
LVG
SD/OD
OUT
HVG
Vboot
HIN
MICROCONTROLLER
Temp.
Monitoring
HIN U
LIN U
LIN V
HIN V
LIN W
HIN W
SD
ADC
NTC
+
-
+
-
GND
LIN
VCC
LVG
CIN
SD/OD
OUT
HVG
Vboot
HIN
GND
OPOUT
LIN
VCC
LVG
OP+
OP-
SD/OD
OUT
HVG
Vboot
HIN
GADG100620160912FSR
Application circuit example
STIPNS2M50T-H
18/24
DocID030525 Rev 2
5.1 Guidelines
Input signals HIN, LIN are active high logic. A 375 kΩ (typ.) pull-down resistor is built-
in for each input. To prevent input signal oscillations, the wiring of each input should
be as short as possible and the use of RC filters (R1, C1) on each input signal is
suggested. The filters should be within a time constant of about 100 ns and placed as
close as possible to the IPM input pins.
The use of a bypass capacitor CVCC (aluminum or tantalum) can help to reduce the
transient circuit demand on the power supply. Besides, to reduce high frequency
switching noise distributed on the power lines, a decoupling capacitor C2 (100 to 220
nF, with low ESR and low ESL) should be placed as close as possible to the Vcc pin
and in parallel with the bypass capacitor.
The use of an RC filter (RSF, CSF) for circuit malfunction protection is recommended.
The time constant (RSF x CSF) should be set to 1 μs and the filter must be placed as
close as possible to the CIN pin.
The SD
is an input/output pin (open-drain type if used as output). A built-in thermistor
NTC is internally connected between the SD
pin and GND. The VSD-GND voltage
decreases as the temperature increases, due to the RSD pull-up resistor. In order to
keep the voltage always higher than the high level logic threshold, the pull-up resistor
is suggested to be set to 1 kΩ or 2.2 kΩ for an MCU power supply of 3.3 V or 5 V
respectively. The CSD capacitor of the filter on SD
should be fixed no higher than 3.3
nF in order to assure an SD
activation time of τ1 ≤ 500 ns and the filter should be
placed as close as possible to the SD
pin.
The decoupling capacitor C3 (from 100 to 220 nF, ceramic with low ESR and low
ESL), in parallel with each Cboot, filters high frequency disturbance. Both Cboot and C3
(if present) should be placed as close as possible to the U, V, W and Vboot pins.
Bootstrap negative electrodes should be connected to the U, V, W terminals directly
and separated from the main output wires.
To prevent overvoltage on the Vcc pin, a Zener diode (Dz1) can be used. Similarly, a
Zener diode (Dz2) can be placed on the Vboot pin in parallel with each Cboot.
The use of decoupling capacitor C4 (100 to 220 nF, with low ESR and low ESL) in
parallel with the electrolytic capacitor Cvdc is useful to prevent surge destruction. Both
capacitors C4 and Cvdc should be placed as close as possible to the IPM (C4 has
priority over Cvdc).
By integrating an application-specific type HVIC inside the module, direct coupling to
the MCU terminals without an optocoupler is possible.
Use low inductance shunt resistors for phase leg current sensing.
In order to avoid malfunctions, the wiring on N pins, the shunt resistor and PWR_GND
should be as short as possible.
The connection of SGN_GND to PWR_GND to one point only (close to the shunt
resistor terminal) can help to reduce the impact of power ground fluctuation.
These guidelines ensure the device specifications for application designs. For further
details, please refer to the relevant application note.
STIPNS2M50T-H
Application circuit example
DocID030525 Rev 2
19/24
Table 15: Recommended operating conditions
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
VPN
Supply voltage
Applied among P-Nu, Nv,
Nw
300
400
V
VCC
Control supply voltage
Applied to VCC-GND
13.5
15
18
V
VBS
High-side bias voltage
Applied to VBOOTi-OUTi for
i = U, V, W
13
18
V
tdead
Blanking time to prevent
arm-short
For each input signal
1
µs
fPWM
PWM input signal
-40 °C < Tc < 100 °C
-40 °C < Tj < 125 °C
25
kHz
TC
Case operation temperature
100
°C
Package information
STIPNS2M50T-H
20/24
DocID030525 Rev 2
6 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
6.1 NSDIP-26L package information
Figure 12: NSDIP-26L package outline
STIPNS2M50T-H
Package information
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Table 16: NSDIP-26L package mechanical data
Dim.
mm
Min.
Typ.
Max.
A
3.45
A1
0.10
0.25
A2
3.00
3.10
3.20
A3
1.70
1.80
1.90
b
0.47
0.57
b1
0.45
0.50
0.55
b2
0.63
0.67
c
0.47
0.57
c1
0.45
0.50
0.55
D
29.05
29.15
29.25
D1
0.70
D2
0.45
D3
0.90
D4
29.65
E
12.35
12.45
12.55
E1
16.70
17.00
17.30
E2
0.35
e
1.70
1.80
1.90
e1
2.40
2.50
2.60
L
1.24
1.39
1.54
L1
1.00
1.15
1.30
L2
0.25 BSC
L3
2.275 REF
R1
0.25
0.40
0.55
R2
0.25
0.40
0.55
S
0.39
0.55
ϴ
0°
8°
ϴ1
3° BSC
ϴ2
10°
12°
14°
Package information
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Figure 13: NSDIP-26L recommended footprint (dimensions are in mm)
STIPNS2M50T-H
Revision history
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7 Revision history
Table 17: Document revision history
Date
Revision
Changes
19-Apr-2017
1
Initial release
04-Jan-2018
2
Datasheet status promoted from preliminary to production data.
Updated features on cover page.
Updated Table 3: "Inverter part", Table 5: "Total system", Table 6:
"Thermal data" and Table 13: "Sense comparator characteristics".
Updated Section 6.1: "NSDIP-26L package information".
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