Features
·Floating channel designed for bootstrap operation
Fully operational up to +200V
Tolerant to negative transient voltage, dV/dt immune
·Gate drive supply range from 10V to 20V
·Independent low and high side channels
·Input logicHIN/LIN active high
·Undervoltage lockout for both channels
·3.3V and 5V input logic compatible
·CMOS Schmitt-triggered inputs with pull-down
·Matched propagation delay for both channels
·Also available LEAD-FREE (PbF)
Packages
HIGH AND LOW SIDE DRIVER
Product Summary
VOFFSET 200V max.
IO+/- 1.0A /1.0A typ.
VOUT 10 - 20V
ton/off 80 & 60 ns typ.
Delay Matching 20 ns max.
IR2011(S) & (PbF)
www.irf.com 1
Typical Connection
(Refer to Lead Assignments for correct configuration). This/These diagram(s) show electrical connections only. Please
refer to our Application Notes and DesignTips for proper circuit board layout.
Data Sheet No.PD60217 revB
Applications
·Audio Class D amplifiers
·High power DC-DC SMPS converters
·Other high frequency applications
Description
The IR2011 is a high power, high speed power MOSFET driver with independent high
and low side referenced output channels, ideal for Audio Class D and DC-DC converter
applications. Logic inputs are compatible with standard CMOS or LSTTL output, down
to 3.0V logic. The output drivers feature a high pulse current buffer stage designed for
minimum driver cross-conduction. Propagation delays are matched to simplify use in
high frequency applications. The floating channel can be used to drive an N-channel
power MOSFET in the high side configuration which operates up to 200 volts. Propri-
etary HVIC and latch immune CMOS technologies enable ruggedized monolithic con-
struction.
8-Lead SOIC
IR2011S
200V
TO
LOAD
VCC
COM
LIN
HIN VS
VB
HO
HIN
COM
VCC
LIN
LO 18
45
8-Lead PDIP
IR2011
2www.irf.com
IR2011(S) & (PbF)
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param-
eters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured
under board mounted and still air conditions.
Symbol Definition Min. Max. Units
VBHigh side floating supply voltage -0.3 225
VSHigh side floating supply offset voltage VB - 25 VB + 0.3
VHO High side floating output voltage VS - 0.3 VB + 0.3
VCC Low side fixed supply voltage -0.3 25
VLO Low side output voltage -0.3 VCC +0.3
VIN Logic input voltage (HIN & LIN) -0.3 VCC +0.3
dVs/dt Allowable offset supply voltage transient (figure 2) 50 V/ns
PDPackage power dissipation @ TA £ +25°C(8-lead DIP) 1.0
(8-lead SOIC) 0.625
RTHJA Thermal resistance, junction to ambient (8-lead DIP) 125
(8-lead SOIC) 200
TJJunction temperature 150
TSStorage temperature -55 150
TLLead temperature (soldering, 10 seconds) 300
°C/W
W
V
°C
Note 1: Logic operational for VS of -4 to +200V. Logic state held for VS of -4V to -VBS.
Symbol Definition Min. Max. Units
VBHigh side floating supply absolute voltage VS + 10 VS + 20
VSHigh side floating supply offset voltage Note 1 200
VHO High side floating output voltage VSVB
VCC Low side fixed supply voltage 10 20
VLO Low side output voltage 0 VCC
VIN Logic input voltage (HIN & LIN) COM 5.5
T
AAmbient temperature -40 125 °C
Recommended Operating Conditions
For proper operation the device should be used within the recommended conditions. The VS and COM offset ratings
are tested with all supplies biased at 15V differential.
V
www.irf.com 3
IR2011(S) & (PbF)
Symbol Definition Min. Typ.Max.UnitsTest Conditions
VIH Logic 1 input voltage 2.2
VIL Logic 0 input voltage 0.7
VOH High level output voltage, VBIAS - VO 2.0 IO = 0A
VOL Low level output voltage, VO 0.2 20mA
ILK Offset supply leakage current 50 VB=VS = 200V
IQBS Quiescent V
BS supply current 90 210 VIN = 0V or 3.3V
IQCC Quiescent V
CC supply current 140 230 VIN = 0V or 3.3V
IIN+ Logic 1 input bias current 7.0 20 VIN = 3.3V
IIN- Logic 0 input bias current 1.0 VIN = 0V
VBSUV+ VBS supply undervoltage positive going 8.2 9.0 9.8
threshold
VBSUV- VBS supply undervoltage negative going 7.4 8.2 9.0
threshold
VCCUV+ VCC supply undervoltage positive going 8.2 9.0 9.8
threshold
VCCUV- VCC supply undervoltage negative going 7.4 8.2 9.0
threshold
IO+ Output high short circuit pulsed current 1.0 VO = 0V,
PW £ 10 µs
IO- Output low short circuit pulsed current 1.0 VO = 15V,
PW £ 10 µs
V
µA
V
A
Static Electrical Characteristics
VBIAS (VCC, VBS) = 15V, and TA = 25°C unless otherwise specified. The VIN, VTH and IIN parameters are referenced to
COM and are applicable to all logic input leads: HIN and LIN. The VO and IO parameters are referenced to COM and are
applicable to the respective output leads: HO or LO.
VCC = 10V - 20V
Dynamic Electrical Characteristics
VBIAS (VCC, VBS) = 15V, CL = 1000 pF, TA = 25°C unless otherwise specified. Figure 1 shows the timing definitions.
Symbol Definition Min. Typ.Max.UnitsTest Conditions
ton Turn-on propagation delay 80 VS = 0V
toff Turn-off propagation delay 75 VS = 200V
trTurn-on rise time 35 50
tfTurn-off fall time 20 35
DM1 Turn-on delay matching | ton (H) - ton (L) | 20
DM2 Turn-off delay matching | toff (H) - toff (L) | 20
ns
4www.irf.com
IR2011(S) & (PbF)
Functional Block Diagram
Lead Definitions
SymbolDescription
8-Lead PDIP 8-Lead SOIC
IR2011 IR2011S
Part Number
Lead Assignments
HIN Logic input for high side gate driver output (HO), in phase
LIN Logic input for low side gate driver output (LO), in phase
VBHigh side floating supply
HO High side gate drive output
VSHigh side floating supply return
VCC Low side supply
LO Low side gate drive output
COM Low side return
VB
LIN
UV
DETECT
DELAY
VCC
UV
DETECT
LO
VS
COM
S
R
UV Q
HIN
HO
LEVEL
SHIFT
CIRCUIT
LOW
VOLTAGE
LEVEL
SHIFT
3V S-TRIGGER
3V S-TRIGGER
HIGH
VOLTAGE
BUFFER
LOW
VOLTAGE
LEVEL
SHIFT
VS
VB
HO
HIN
COM
VCC
LIN
LO 1
8
4
5
6
7
3
2
VS
VB
HO
HIN
COM
VCC
LIN
LO 1
8
4
5
6
7
3
2
www.irf.com 5
IR2011(S) & (PbF)
Figure 1. Timing Diagram
50% 50%
10%
90%
10%
90%
10%
90%
HIN / LIN
HO
LO
trise tfall
ton(H)
ton(L)
toff(H)
toff(L)
DM1 DM2
6www.irf.com
IR2011(S) & (PbF)
0
100
200
300
400
500
-50 -25 0 25 50 75 100 125
Temperature (oC)
Turn-on Propagation Delay (ns)
Typ.
Figure 2A. Turn-on Propagation Delay
vs. Temperature
0
100
200
300
400
500
10 12 14 16 18 20
Supply Voltage (V)
Turn-on Propagation Delay (ns )
Figure 2B. Turn-on Propagation Delay
vs. Supply Voltage
Typ.
0
100
200
300
400
500
-50 -25 0 25 50 75 100 125
Temperature (oC)
Turn-off Propagation Delay (ns)
Typ.
Figure 3A. Turn-off Propagation Delay
vs. Temperature
0
100
200
300
400
500
10 12 14 16 18 20
Supply Voltage (V)
T ur n-off Propagation Delay (ns )
Figure 3B. Turn-off Propagation Delay
vs. Supply Voltage
Typ.
www.irf.com 7
IR2011(S) & (PbF)
0
20
40
60
80
100
-50 -25 0 25 50 75 100 125
Temperature (oC)
Turn-on Rise Time ( ns)
Typ.
Max.
Figure 4A. Turn-on Rise Time vs. Temperature
0
20
40
60
80
100
10 12 14 16 18 20
Supply Voltage (V)
Turn-on Rise Time (ns)
Figure 4B. Turn-on Rise Time vs. Supply Voltage
Typ.
Max.
0
10
20
30
40
50
-50 -25 0 25 50 75 100 125
Temperature (oC)
Turn-off Fall Time (ns)
Typ.
Max.
Figure 5A. Turn-off Fall Time vs. Temperature
0
10
20
30
40
50
10 12 14 16 18 20
Supply Voltage (V)
Turn-off F all Time (ns )
Figure 5B. Turn-off Fall Time vs. Supply Voltage
Typ.
Max.
8www.irf.com
IR2011(S) & (PbF)
0
10
20
30
40
50
-50 -25 0 25 50 75 100 125
Temperature (oC)
Delay Matching Time (ns)
Figure 6A. Turn-on Delay Matching Time
vs. Temperature
Typ.
Max.
0
10
20
30
40
50
10 12 14 16 18 20
Supply Voltage (V)
De aly Matching Time (ns)
Figure 6B. Turn-on Delay Matching Time
vs. Supply Voltage
Typ.
Max.
0
10
20
30
40
50
-50 -25 0 25 50 75 100 125
Temperature (oC)
Delay Matching Time (ns)
Figure 7A. Turn-off Delay Matching Time
vs. Temperature
Typ.
Max.
0
10
20
30
40
50
10 12 14 16 18 20
Supply Voltage (V)
De aly Matching Time (ns)
Figure 7B. Turn-off Delay Matching Time
vs. Supply Voltage
Typ.
Max.
www.irf.com 9
IR2011(S) & (PbF)
0
1
2
3
4
5
-50 -25 0 25 50 75 100 125
Temperature (oC)
Logic "1" Input Voltage (V)
Min.
Figure 8A. Logic "1" Input Voltage
vs. Temperature
0
1
2
3
4
5
10 12 14 16 18 20
Supply Voltage (V)
Logic "1" Input Voltage (V)
Figure 8B. Logic "1" Input Voltage
vs. Supply Voltage
Min.
0
1
2
3
4
5
-50 -25 0 25 50 75 100 125
Temperature (oC)
Logic "0" Input Voltage (V)
Max.
Figure 9A. Logic "0" Input Voltage
vs. Temperature
0
1
2
3
4
5
10 12 14 16 18 20
Supply Voltage (V)
Logic "0" Input Voltage (V)
Figure 9B. Logic "0" Input Voltage
vs. Supply Voltage
Max.
10 www.irf.com
IR2011(S) & (PbF)
0
1
2
3
4
5
-50 -25 0 25 50 75 100 125
Temperature (oC)
High Level Output (V)
Max.
Figure 10A. High Level Output vs.Temperature
0
1
2
3
4
5
10 12 14 16 18 20
Supply Voltage (V)
High Level Output (V)
Figure 10B. High Level Output vs. Supply Voltage
Max.
0.0
0.1
0.2
0.3
0.4
0.5
-50 -25 0 25 50 75 100 125
Temperature (oC)
Low Level Output (V)
Max.
Figure 11A. Low Level Output vs. Temperature
0.0
0.1
0.2
0.3
0.4
0.5
10 12 14 16 18 20
Supply Voltage (V)
Low Lev el O utput (V)
Figure 11B. Low Level Output vs. Supply Voltage
Max.
www.irf.com 11
IR2011(S) & (PbF)
0
100
200
300
400
500
-50 -25 0 25 50 75 100 125
Temperature (oC)
Offset Supply Leakage Current (
m
A)
Max.
Figure 12A. Offset Supply Leakage Current
vs. Temperature
0
100
200
300
400
500
50 80 110 140 170 200
VB Boost Voltage (V)
Offset Supply Leakage Current (
m
A)
Max.
0
100
200
300
400
500
600
-50 -25 0 25 50 75 100 125
Temperature (oC)
VBS Supply Current (
m
A)
Typ.
Max.
0
100
200
300
400
500
600
10 12 14 16 18 20
VBS Floating Supply Voltage (V)
VBS Supply Current (
m
A)
Typ.
Max.
12 www.irf.com
IR2011(S) & (PbF)
0
100
200
300
400
500
600
-50 -25 0 25 50 75 100 125
Temperature (oC)
VCC Supply Current (
m
A)
Figure 14A. VCC Supply Current
vs. Temperature
Typ.
Max.
0
100
200
300
400
500
600
10 12 14 16 18 20
VCC Supply Voltage (V)
VCC Supply Current (
m
A)
Figure 14B. VCC Supply Current
vs. VCC Supply Voltage
Typ.
Max.
0
20
40
60
80
100
-50 -25 0 25 50 75 100 125
Temperature (oC)
Logic "1" Input Bias Current (
m
A)
Figure 15A. Logic "1" Input Bias Current
vs. Temperature
Typ.
Max.
0
20
40
60
80
100
10 12 14 16 18 20
Supply Voltage (V)
Logic "1" Input Bias Current (
m
A)
Typ.
Max.
www.irf.com 13
IR2011(S) & (PbF)
0
1
2
3
4
5
-50 -25 0 25 50 75 100 125
Temperature (oC)
Logic "0" Input Bias Current (
m
A)
Figure 16A. Logic "0" Input Bias Current
vs. Temperature
Max.
0
1
2
3
4
5
10 12 14 16 18 20
Supply Voltage (V)
Logic "0" Input Bias Current (
m
A)
Figure 16B. Logic "0" Input Bias Current
vs. Supply Voltage
Max.
7
8
9
10
11
12
-50 -25 0 25 50 75 100 125
Temperature (oC)
V
CC
and V
BS
UV Threshold (+) (V)
Min.
Figure 17. VCC and V BS Undervoltage Threshold (+)
vs. Temperature
Typ.
Max.
7
8
9
10
11
12
-50 -25 0 25 50 75 100 125
Temperature (oC)
VC C and VBS UV Threshold (-) (V)
Min.
Figure 18. VCC and V BS Undervoltage Threshold (-)
vs. Temperature
Typ.
Max.
14 www.irf.com
IR2011(S) & (PbF)
0
1
2
3
4
5
-50 -25 0 25 50 75 100 125
Temperature (oC)
O utput Source Current (A)
Figure19A. Output Source Current
vs. Temperature
Typ.
0
1
2
3
4
5
10 12 14 16 18 20
Supply Voltage (V)
O utput Sourc e Current (A)
Figure 19B. Output Source Current
vs. Supply Voltage
Typ.
0
1
2
3
4
5
-50 -25 0 25 50 75 100 125
Temperature (oC)
Output Sink Current (A)
Figure 20A. Output Sink Current
vs. Temperature
Typ.
0
1
2
3
4
5
10 12 14 16 18 20
Supply Voltage (V)
Output Sink C urrent ( A)
Figure 20B. Output Sink Current
vs. Supply Voltage
Typ.
www.irf.com 15
IR2011(S) & (PbF)
-15
-12
-9
-6
-3
0
10 12 14 16 18 20
VBS Floating Supply Voltage (V)
Maximum V
S Negativ e Offset (V)
Figure 21. Maximum VS Negative Offset
vs. VBS Floating Supply Voltage
Typ.
16 www.irf.com
IR2011(S) & (PbF)
01-6014
01-3003 01 (MS-001AB)
8-Lead PDIP
Case outlines
01-6027
01-0021 11 (MS-012AA)
8-Lead SOIC
8 7
5
6 5
D B
E
A
e
6X
H
0.25 [.010] A
6
431 2
4. OUTLINE CONFORMS TO JEDEC OUTLINE MS-012AA.
NOTES:
1. DIMENSIONING & TOLERANCING PER ASME Y14.5M-1994.
2. CONTROLLING DIMENSION: MILLIMETER
3. DIMENSIONS ARE SHOWN IN MILLIMETERS [INCHES].
7
K x 4
8X L 8X c
y
FOOTPRINT
8X 0.72 [.028]
6.46 [.255]
3X 1.27 [.050] 8X 1.78 [.070]
4. OUTLINE CONFORMS TO JEDEC OUTLINE MS-012AA.
5 DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS.
6 DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS.
MOLD PROTRUSIONS NOT TO EXCEED 0.25 [.010].
7 DIMENSION IS THE LENGTH OF LEAD FOR SOLDERING TO
A SUBSTRATE.
MOLD PROTRUSIONS NOT TO EXCEED 0.15 [.006].
0.25 [.010] CAB
e1 A
A1
8X b
C
0.10 [.004]
e1
D
E
y
b
A
A1
H
K
L
.189
.1497
.013
.050 BASIC
.0532
.0040
.2284
.0099
.016
.1968
.1574
.020
.0688
.0098
.2440
.0196
.050
4.80
3.80
0.33
1.35
0.10
5.80
0.25
0.40
1.27 BASIC
5.00
4.00
0.51
1.75
0.25
6.20
0.50
1.27
MIN MAX MILLIMETERSINCHES MIN MAX
DIM
e
c.0075 .0098 0.19 0.25
.025 BASIC 0.635 BASIC
www.irf.com 17
IR2011(S) & (PbF)
ORDER INFORMATION
Basic Part (Non-Lead Free)
8-Lead PDIP IR2011 order IR2011
8-Lead SOIC IR2011S order IR2011S
Leadfree Part
8-Lead PDIP IR2011 order IR2011PbF
8-Lead SOIC IR2011S order IR2011SPbF
This product has been designed and qualified for the industrial market.
Qualification Standards can be found on IRs Web Site http://www.irf.com/.
Data and specifications subject to change without notice
WORLD HEADQUARTERS: 233 Kansas Street, El Segundo, California 90245 Tel: (310) 252-7105
3/4/2008
LEADFREE PART MARKING INFORMATION
Lead Free Released
Non-Lead Free
Released
Part number
Date code
IRxxxxxx
YWW?
?XXXX
Pin 1
Identifier
IR logo
Lot Code
(Prod mode - 4 digit SPN code)
Assembly site code
Per SCOP 200-002
P
?MARKING CODE