19-0172; Rev 6; 2/97 +5V, Low-Power, Voltage-Output, Serial 12-Bit DACs The MAX531/MAX538/MAX539 are low-power, voltageoutput, 12-bit digital-to-analog converters (DACs) specified for single +5V power-supply operation. The MAX531 can also be operated with 5V supplies. The MAX538/MAX539 draw only 140A, and the MAX531 (with internal reference) draws only 260A. The MAX538/MAX539 come in 8-pin DIP and SO packages, while the MAX531 comes in 14-pin DIP and SO packages. All parts have been trimmed for offset voltage, gain, and linearity, so no further adjustment is necessary. The MAX538's buffer is fixed at a gain of +1 and the MAX539's buffer at a gain of +2. The MAX531's internal op amp may be configured for a gain of +1 or +2, as well as for unipolar or bipolar output voltages. The MAX531 can also be used as a four-quadrant multiplier without external resistors or op amps. For parallel data inputs, see the MAX530 data sheet. ___________________________Features Operate from Single +5V Supply Buffered Voltage Output Internal 2.048V Reference (MAX531) 140A Supply Current (MAX538/MAX539) INL = 1/2LSB (max) Guaranteed Monotonic over Temperature Flexible Output Ranges: 0V to VDD (MAX531/MAX539) VSS to VDD (MAX531) 0V to 2.6V (MAX531/MAX538) 8-Pin SO/DIP (MAX538/MAX539) Power-On Reset Serial Data Output for Daisy-Chaining _______________________Applications Battery-Powered Test Instruments Digital Offset and Gain Adjustment ______________Ordering Information TEMP. RANGE Battery-Operated/Remote Industrial Controls MAX531ACPD 0C to +70C 14 Plastic DIP 1/2 Machine and Motion Control Devices MAX531BCPD MAX531ACSD MAX531BCSD MAX531BC/D 0C to +70C 0C to +70C 0C to +70C 0C to +70C 14 Plastic DIP 14 SO 14 SO Dice* 1 1/2 1 1 Cellular Telephones ________________Functional Diagram (MAX531 ONLY) REFIN REFOUT 2.048V REFERENCE (MAX531 ONLY) (MAX531 ONLY) BIPOFF MAX531 MAX538 MAX539 PIN-PACKAGE ERROR (LSB) PART Ordering Information continued at end of data sheet. *Dice are specified at TA = +25C only. _________________Pin Configurations RFB (MAX531 ONLY) TOP VIEW VOUT DAC AGND CLR (MAX531 ONLY) CS SCLK DIN VDD POWER-UP RESET DGND (MAX531 ONLY) VSS (MAX531 ONLY) DAC REGISTER (12 BITS) CONTROL LOGIC SHIFT REGISTER (12 BITS) (MSB) (LSB) 4 BITS DOUT DIN 1 8 VDD SCLK 2 7 VOUT 6 REFIN 5 AGND CS 3 MAX538 MAX539 DOUT 4 DIP/SO Pin Configurations continued at end of data sheet. ________________________________________________________________ Maxim Integrated Products 1 For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800 MAX531/MAX538/MAX539 _______________General Description MAX531/MAX538/MAX539 +5V, Low-Power, Voltage-Output Serial 12-Bit DACs ABSOLUTE MAXIMUM RATINGS Continuous Power Dissipation (TA = +70C) 8-Pin Plastic DIP (derate 9.09mW/C above +70C)....727mW 8-Pin SO (derate 5.88mW/C above +70C) ................471mW 14-Pin Plastic DIP (derate 10.00mW/C above +70C)...800mW 14-Pin SO (derate 8.33mW/C above +70C) ..............667mW Operating Temperature Ranges MAX53_ _C_ _ .....................................................0C to +70C MAX53_ _E_ _ ..................................................-40C to +85C Storage Temperature Range .............................-65C to +165C Lead Temperature (soldering, 10sec) .............................+300C VDD to DGND and VDD to AGND ................................-0.3V, +6V VSS to DGND and VSS to AGND .................................-6V, +0.3V VDD to VSS .................................................................-0.3V, +12V AGND to DGND........................................................-0.3V, +0.3V Digital Input Voltage to DGND ......................-0.3V, (VDD + 0.3V) REFIN ..................................................(VSS - 0.3V), (VDD + 0.3V) REFOUT to AGND .........................................-0.3V, (VDD + 0.3V) RFB .....................................................(VSS - 0.3V), (VDD + 0.3V) BIPOFF ................................................(VSS - 0.3V), (VDD + 0.3V) VOUT (Note 1) ................................................................VSS, VDD Continuous Current, Any Pin................................-20mA, +20mA Note 1: The output may be shorted to VDD, VSS, or AGND if the package power dissipation limit is not exceeded. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS--Single +5V Supply (VDD = +5V 10%, VSS = 0V, AGND = DGND = 0V, REFIN = 2.048V (external), RFB = BIPOFF = VOUT (MAX531), CREFOUT = 33F (MAX531), RL = 10k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC PERFORMANCE Resolution N 12 MAX53_AC/E 0.5 MAX53_BC/E 1 Relative Accuracy (Note 2) INL Differential Nonlinearity DNL Guaranteed monotonic Unipolar Offset Error VOS MAX53_ _C/E Unipolar Offset Tempco Gain Error (Note 2) 0 TCVOS GE LSB 8 LSB ppm/C 1 1 PSRR 4.5V VDD 5.5V 0.4 LSB 1 3 MAX53_ _C/E Gain-Error Tempco Power-Supply Rejection Ratio (Note 3) Bits LSB ppm/C 1 LSB/V VOLTAGE OUTPUT (VOUT) Output Voltage Range Output Load Regulation Short-Circuit Current MAX531 (G = +1), MAX538 0 VDD - 2 MAX531 (G = +2), MAX539 0 VDD - 0.4 VOUT = 2V, RL = 2k 1 ISC 12 V LSB mA REFERENCE INPUT (REFIN) Voltage Range 0 Input Resistance Code dependent, minimum at code 555 hex 40 Input Capacitance Code dependent (Note 4) 10 AC Feedthrough REFIN = 1kHz, 2Vp-p 2 VDD - 2 V k 50 -80 _______________________________________________________________________________________ pF dB +5V, Low-Power, Voltage-Output, Serial 12-Bit DACs MAX531/MAX538/MAX539 ELECTRICAL CHARACTERISTICS--Single +5V Supply (continued) (VDD = +5V 10%, VSS = 0V, AGND = DGND = 0V, REFIN = 2.048V (external), RFB = BIPOFF = VOUT (MAX531), CREFOUT = 33F (MAX531), RL = 10k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX TA = +25C 2.024 2.048 MAX531BC 2.017 2.079 MAX531BE 2.013 2.083 UNITS REFERENCE OUTPUT (REFOUT--MAX531 only) Reference Output Voltage Temperature Coefficient Resistance VDD = 5.0V TCREFOUT RREFOUT Power-Supply Rejection Ratio Noise Voltage PSRR en Minimum Required External Capacitor MAX531AC/AE/AM/BM 30 MAX531BC/BE 30 (Note 5) 0.5 4.5V VDD 5.5V 0.1Hz to 10kHz CMIN 2.072 50 V ppm/C 2 300 V/V 400 Vp-p 3.3 F DIGITAL INPUTS (DIN, SCLK, CS, CLR) Input High VIH Input Low VIL Input Current IIN Input Capacitance CIN 2.4 V VIN = 0V or VDD 0.8 V 1 A 8 pF DIGITAL OUTPUT (DOUT) Output High Output Low VOH VOL ISOURCE = 2mA ISINK = 2mA VDD - 1 0.4 V V DYNAMIC PERFORMANCE Voltage-Output Slew Rate Voltage-Output Settling Time Digital Feedthrough Signal-to-Noise plus Distortion SR SINAD TA = +25C To 1/2LSB, VOUT = 2V CS = VDD, DIN = 100kHz 0.15 REFIN = 1kHz, 2Vp-p (G = +1 or +2), code = FFF hex 0.25 25 5 V/s s nV-s 68 dB POWER SUPPLY Positive Supply Voltage Power-Supply Current VDD IDD 4.5 All inputs = 0V or VDD, MAX531 output = no load MAX538, MAX539 260 140 5.5 400 300 V A SWITCHING CHARACTERISTICS CS Setup Time tCSS 20 ns SCLK Fall to CS Fall Hold Time tCSH0 15 ns SCLK Fall to CS Rise Hold Time tCSH1 0 ns tCH 35 ns SCLK Low Width tCL 35 ns DIN Setup Time tDS 45 ns DIN Hold Time tDH 0 DOUT Valid Propagation Delay tDO SCLK High Width CL = 50pF ns 80 ns CS High Pulse Width tCSW 20 ns CLR Pulse Width tCLR 25 ns CS Rise to SCLK Rise Setup Time tCS1 50 ns _______________________________________________________________________________________ 3 MAX531/MAX538/MAX539 +5V, Low-Power, Voltage-Output, Serial 12-Bit DACs ELECTRICAL CHARACTERISTICS--Dual Supplies (MAX531 Only) (VDD = +5V 10%, VSS = -5V 10%, AGND = DGND = 0V, REFIN = 2.048V (external), RFB = BIPOFF = VOUT, CREFOUT = 33F, RL = 10k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL Resolution CONDITIONS N MIN TYP MAX 12 UNITS Bits MAX531AC/E 0.5 MAX531BC/E 1 Relative Accuracy INL Tested at VDD = 5V, VSS = -5V Differential Nonlinearity DNL Guaranteed monotonic 1 LSB Bipolar Offset Error VOS BIPOFF = REFIN, MAX531_C/E 8 LSB Bipolar Offset Tempco TCVOS Gain Error (Unipolar or Bipolar) GEU BIPOFF = REFIN 3 MAX531_C/E ppm/C 1 Gain-Error Tempco 1 Power-Supply Rejection Ratio (Note 3) PSRR 4.5V VDD 5.5V, -5.5V VSS -4.5V 0.4 LSB LSB ppm/C 1 LSB/V VDD - 2 V REFERENCE INPUT (REFIN) Voltage Range VSS + 2 Input Resistance Code dependent, minimum at code 555 hex 40 Input Capacitance Code dependent (Note 4) 10 AC Feedthrough REFIN = 1kHz, 2.0Vp-p k 50 -80 pF dB REFERENCE OUTPUT (REFOUT--MAX531 only) Reference Output Voltage Temperature Coefficient VDD = 5.0V TCREFOUT Resistance Power-Supply Rejection Ratio Noise Voltage Minimum Required External Capacitor RREFOUT PSRR en TA = +25C 2.024 MAX531BC 2.017 2.048 2.079 MAX531BE 2.013 2.083 MAX531AC/AE/AM/BM 30 MAX531BC/BE 30 (Note 5) 0.5 4.5V VDD 5.5V 0.1Hz to 10kHz 2.072 50 3.3 Input High VIH 2.4 Input Low VIL ppm/C 2 300 V/V 400 CMIN V Vp-p F DIGITAL INPUTS (DIN, SCLK, CS) Input Current IIN Input Capacitance CIN V VIN = 0V or VDD 0.8 V 1 A 8 pF DIGITAL OUTPUT (DOUT) Output High VOH ISOURCE = 2mA Output Low VOL ISINK = 2mA 4 VDD - 1 _______________________________________________________________________________________ V 0.4 V +5V, Low-Power, Voltage-Output, Serial 12-Bit DACs (VDD = +5V 10%, VSS = -5V 10%, AGND = DGND = 0V, REFIN = 2.048V (external), RFB = BIPOFF = VOUT, CREFOUT = 33F, RL = 10k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS VOLTAGE OUTPUT (VOUT) Output Voltage Range Output Load Regulation Short-Circuit Current MAX531 (G = +1) VSS + 2 VDD - 2 MAX531 (G = +2) VSS + 0.4 VDD - 0.4 VOUT = 2V, RL = 2k 1 ISC V LSB 12 mA 0.25 V/s 25 s nV-s DYNAMIC PERFORMANCE Voltage-Output Slew Rate SR 0.15 Voltage-Output Settling Time To 1/2LSB, VOUT = 2V Digital Feedthrough Step 000 hex to FFF hex 5 REFIN = 1kHz, 2Vp-p, (G = +1) 68 REFIN = 1kHz, 2Vp-p, (G = +2) 68 Signal-to-Noise plus Distortion SINAD dB POWER SUPPLY Positive Supply Voltage VDD 4.5 5.5 Negative Supply Voltage VSS -5.5 0 V V Positive Supply Current IDD All inputs = 0V or VDD, no load 260 400 A Negative Supply Current ISS All inputs = 0V or VDD, no load -120 -200 A SWITCHING CHARACTERISTICS CS Setup Time tCSS 20 ns SCLK Fall to CS Fall Hold Time tCSH0 15 ns SCLK Fall to CS Rise Hold Time tCSH1 0 ns SCLK High Width tCH 35 ns SCLK Low Width tCL 35 ns DIN Setup Time tDS 45 ns DIN Hold Time tDH 0 DOUT Valid Propagation Delay tDO CL = 50pF ns 80 ns CS High Pulse Width tCSW 20 ns CLR Pulse Width tCLR 25 ns CS Rise to SCLK Rise Setup Time tCS1 50 ns Note 2: Note 3: Note 4: Note 5: In single-supply operation, INL and GE calculated from code 11 to code 4095. Tested at VDD = +5V. This specification applies to both gain-error power-supply rejection ratio and offset-error power-supply rejection ratio. Guaranteed by design. Tested at IOUT = 100A. The reference can typically source up to 5mA (see Typical Operating Characteristics). _______________________________________________________________________________________ 5 MAX531/MAX538/MAX539 ELECTRICAL CHARACTERISTICS--Dual Supplies (MAX531 Only) (continued) __________________________________________Typical Operating Characteristics (VDD = +5V, VREFIN = 2.048V, TA = +25C, unless otherwise noted.) INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE (ALL CODES) -0.25 -0.50 SINGLE SUPPLY -0.75 -1.00 -1.25 2 6 4 10 8 12 10 8 6 4 2 0 0 0 512 1024 1536 2048 2560 3072 3584 4095 0.2 0.8 0.6 0.4 1.0 DIGITAL INPUT CODE (DECIMAL) OUTPUT PULL-DOWN VOLTAGE (V) OUTPUT SOURCE CAPABILITY vs. OUTPUT PULL-UP VOLTAGE ANALOG FEEDTHROUGH vs. FREQUENCY MAX531 REFERENCE VOLTAGE vs. TEMPERATURE 2 3 4 5 6 7 2.055 -90 -80 -70 -60 -50 -40 -30 MAX531-6 CODE = 000 hex REFERENCE VOLTAGE (V) 1 -100 MAX531-5 MAX531-4 -110 ANALOG FEEDTHROUGH (dB) 2.050 -20 -10 2.045 0 8 VDD-4 VDD-3 VDD-2 VDD-1 1 VDD-0 10 100 1k 10k 100k -60 -40 -20 1M 0 20 40 60 80 100 OUTPUT PULL-UP VOLTAGE (V) FREQUENCY (Hz) TEMPERATURE (C) SUPPLY CURRENT vs. TEMPERATURE MAX531 GAIN vs. FREQUENCY MAX531 AMPLIFIER SIGNAL-TO-NOISE RATIO 280 REFIN = 4Vp-p 2 0 MAX531 240 GAIN (dB) -2 220 200 180 -4 -6 -8 160 -10 MAX538/MAX539 140 -20 0 20 40 TEMPERATURE (C) 60 80 100 60 50 40 30 20 0 -14 -60 -40 REFIN = 4Vp-p 70 10 -12 120 80 MAX531-9 4 MAX531-7 300 SIGNAL-TO-NOISE RATIO (dB) VDD-5 MAX531-8 OUTPUT SOURCE CAPABILITY (mA) 12 14 DIGITAL INPUT CODE (DECIMAL) 0 6 0 -0.25 0 260 OUTPUT SINK CAPABILITY (mA) 0 INTEGRAL NONLINEARITY (LSB) DUAL SUPPLIES 16 0.25 MAX531-1 INTEGRAL NONLINEARITY (LSB) 0.25 OUTPUT SINK CAPABILITY vs. OUTPUT PULL-DOWN VOLTAGE MAX531-3 INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE (FIRST 12 CODES) SUPPLY CURRENT (A) MAX531/MAX538/MAX539 +5V, Low-Power, Voltage-Output, Serial 12-Bit DACs 1 100 1k FREQUENCY (Hz) 10k 100k 10 1k 100 FREQUENCY (Hz) _______________________________________________________________________________________ 10k 100k +5V, Low-Power, Voltage-Output, Serial 12-Bit DACs MAX531 REFERENCE OUTPUT VOLTAGE vs. REFERENCE LOAD CURRENT RFB CONNECTED TO AGND (G=2) RFB CONNECTED TO VOUT (G=1) 2.0515 0 0 PHASE -10 REFERENCE OUTPUT (V) GAIN PHASE (degrees) GAIN (dB) 10 2.0520 180 MAX531-14 20 MAX531-10 MAX531 GAIN AND PHASE vs. FREQUENCY -20 2.0510 2.0505 2.0500 2.0495 -180 -30 1 10 100 2.0490 800 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 FREQUENCY (kHz) REFERENCE LOAD CURRENT (mA) DIGITAL FEEDTHROUGH A B 2s/div CS = HIGH A: DIN = 4Vp-p, 100kHz B: VOUT, 10mV/div NEGATIVE SETTLING TIME (MAX531) POSITIVE SETTLING TIME (MAX531) A A B B 5s/div VDD = 5V, VREFIN = 2V, BIPOLAR CONFIGURATION A: CS RISING EDGE, 5V/div B: VOUT, NO LOAD, 1V/div 5s/div VDD = 5V, VREFIN = 2V, BIPOLAR CONFIGURATION A: CS RISING EDGE, 5V/div B: VOUT, NO LOAD, 1V/div _______________________________________________________________________________________ 7 MAX531/MAX538/MAX539 ____________________________Typical Operating Characteristics (continued) (VDD = +5V, VREFIN = 2.048V, TA = +25C, unless otherwise noted.) MAX531/MAX538/MAX539 +5V, Low-Power, Voltage-Output Serial 12-Bit DACs ____________________Pin Description _______________Detailed Description General DAC Discussion PIN NAME FUNCTION MAX531 MAX538 MAX539 1 -- BIPOFF 2 1 DIN Serial Data Input 3 -- CLR Clear. Asynchronously sets DAC register to 000 hex. 4 2 SCLK 5 3 CS Chip Select, active low 6 4 DOUT Serial Data Output for daisy-chaining 7 -- DGND Digital Ground Bipolar Offset/Gain Resistor Serial Clock Input The MAX531/MAX538/MAX539 use an "inverted" R-2R ladder network with a single-supply CMOS op amp to convert 12-bit digital data to analog voltage levels (see Functional Diagram). The term "inverted" describes the ladder network because the REFIN pin in current-output DACs is the summing junction, or virtual ground, of an op amp. However, such use would result in the output voltage being the inverse of the reference voltage. The MAX531/MAX538/MAX539's topology makes the output the same polarity as the reference input. An internal reset circuit forces the DAC register to reset to 000 hex on power-up. Additionally, a clear CLR pin, when held low, sets the DAC register to 000 hex. CLR operates asynchronously and independently from the chip-select (CS) pin. Buffer Amplifier 8 5 AGND Analog Ground 9 6 REFIN Reference Input 10 -- REFOUT 11 -- VSS 12 7 VOUT 13 8 VDD Positive Power Supply 14 -- RFB Feedback Resistor Reference Output, 2.048V Negative Power Supply DAC Output The output buffer is a unity-gain stable, rail-to-rail output, BiCMOS op amp. Input offset voltage and CMRR are trimmed to achieve better than 12-bit performance. Settling time is 25s to 0.01% of final value. The settling time is considerably longer when the DAC code is initially set to 000 hex, because at this code the op amp is completely debiased. Start from code 001 hex if necessary. The output is short-circuit protected and can drive a 2k load with more than 100pF load capacitance. CS tCSH0 tCSW tCH tCSS tCL tCSH1 SCLK tDH tCS1 tDS DIN tDO DOUT Figure 1. Timing Diagram 8 _______________________________________________________________________________________ +5V, Low-Power, Voltage-Output, Serial 12-Bit DACs REFOUT TOTAL REFERENCE NOISE CS CREFOUT REFERENCE NOISE (VRMS) 1.6 250 CREFOUT = 3.3F 1.4 200 1.2 1.0 150 0.8 100 0.6 0.4 50 CREFOUT = 47F 0 0.1 1 10 100 REFERENCE NOISE (mVp-p) 1.8 SINGLE-POLE ROLLOFF MAX531-FIG02 TEK 7A22 300 0.2 0 1000 FREQUENCY (kHz) Figure 2. Reference Noise vs. Frequency Internal Reference (MAX531 only) The on-chip reference is lesser trimmed to generate 2.048V at REFOUT. The output stage can source and sink current, so REFOUT can settle to the correct voltage quickly in response to code-dependent loading changes. Typically, source current is 5mA and sink current is 100A. REFOUT connects the internal reference to the R-2R DAC ladder at REFIN. The R-2R ladder draws 50A maximum load current. If any other connection is made to REFOUT, ensure that the total load current is less than 100A to avoid gain errors. For applications requiring very low-noise performance, connect a 33F capacitor from REFOUT to AGND. If noise is not a concern, a lower value capacitor (3.3F min) may be used. To reduce noise further, insert a buffered RC filter between REFOUT and REFIN (Figure 2). The reference bypass capacitor, CREFOUT, is still required for reference stability. In applications not requiring the reference, connect REFOUT to VDD or use the MAX538 or MAX539 (no internal reference). External Reference An external reference in the range (VSS + 2V) to (VDD - 2V) may be used with the MAX531 in dual-supply operation. With the MAX538/MAX539 or the MAX531 in single-supply use, the reference must be positive and may not exceed VDD - 2V. The reference voltage determines the DAC's fullscale output. The DAC input resistance is code dependent and is minimum (40k) at code 555 hex and virtually infi- nite at code 000 hex. REFIN's input capacitance is also code dependent and has a 50pF maximum value at several codes. Because of the code-dependent nature of reference input impedances, a high-quality, low-output-impedance amplifier (such as the MAX480 low-power, precision op amp) should be used. If an upgrade to the internal reference is required, the 2.5V MAX873A is suitable: 15mV initial accuracy, TCVOUT = 7ppm/C (max). Logic Interface The MAX531/MAX538/MAX539 logic inputs are designed to be compatible with TTL or CMOS logic levels. However, to achieve the lowest power dissipation, drive the digital inputs with rail-to-rail CMOS logic. With TTL logic levels, the power requirement increases by a factor of approximately 2. Serial Clock and Update Rate Figure 1 shows the MAX531/MAX538/MAX539 timing. The maximum serial clock rate is given by 1 / (tCH + tCL), approximately 14MHz. The digital update rate is limited by the chip-select period, which is 16 x (tCH + tCL) + tCSW. This equals a 1.14s, or 877kHz, update rate. However, the DAC settling time to 12 bits is 25s, which may limit the update rate to 40kHz for full-scale step transitions. ____________Applications Information Refer to Figures 3a and 3b for typical operating connections. Serial Interface The MAX531/MAX538/MAX539 use a three-wire serial interface that is compatible with SPITM, QSPITM (CPOL = CPHA = 0), and MicrowireTM standards as shown in Figures 4 and 5. The DAC is programmed by writing two 8-bit words (see Figure 1 and the Functional Diagram). Sixteen bits of serial data are clocked into the DAC MSB first with the MSB preceded by four fill (dummy) bits. The four dummy bits are not normally needed. They are required only when DACs are daisy-chained. Data is clocked in on SCLK's rising edge while CS is low. The serial input data is held in a 16-bit serial shift register. On CS's rising edge, the 12 least significant bits are transferred to the DAC register and update the DAC. With CS high, data cannot be clocked into the MAX531/MAX538/MAX539. The MAX531/MAX538/MAX539 input data in 16-bit blocks. The SPI and Microwire interfaces output data in 8-bit blocks, thereby requiring two write cycles to input data to the DAC. The QSPI interface allows variable data input from eight to 16 bits, and can be loaded into the DAC in one write cycle. SPI and QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corp. _______________________________________________________________________________________ 9 MAX531/MAX538/MAX539 RS MAX531/MAX538/MAX539 +5V, Low-Power, Voltage-Output, Serial 12-Bit DACs DIN DOUT SCLK CS CLR DIN REFIN VOUT INVERTED R-2R DAC REFOUT 2.048V AGND DGND 33F MAX531 VDD VSS 0.1F 0.1F +5V CS DOUT REFIN VOUT INVERTED R-2R DAC 2R 2R SCLK 2R RFB BIPOFF CONNECT BIPOFF TO VOUT FOR G = 1, TO AGND FOR G = 2, OR TO REFIN FOR BIPOLAR GAIN 2R MAX538 MAX539 AGND VDD 0V TO -5V MAX539 ONLY +5V 0.1F Figure 3a. MAX531 Typical Operating Circuit Daisy-Chaining Devices The serial output, DOUT, allows cascading of two or more DACs. The data at DIN appears at DOUT, delayed by 16 clock cycles plus one clock width. For low power, DOUT is a CMOS output that does not require an external pull-up resistor. DOUT does not go into a high-impedance state when CS is high. DOUT changes on SCLK's falling edge when CS is low. When CS is high, DOUT remains in the state of the last data bit. Any number of MAX531/MAX538/MAX539 DACs can be daisy-chained by connecting the DOUT of one device to the DIN of the next device in the chain. For proper timing, ensure that tCL (CS low to SCLK high) is greater than tDO + tDS. Unipolar Configuration The MAX531 is configured for a gain of +1 (0V to VREFIN unipolar output) by connecting BIPOFF and RFB to VOUT (Figure 6). The converter operates from either single or dual supplies in this configuration. See Table 1 for the DAC-latch contents (input) vs. the analog VOUT (output). In this range, 1LSB = V REFIN (2 -12 ). The MAX538 is internally configured for unipolar gain = +1 operation. A gain of +2 (0V to 2VREFIN unipolar output) is set up by connecting BIPOFF to AGND and RFB to VOUT (Figure 7). Table 2 shows the DAC-latch contents vs. VOUT. The MAX531 operates from either single or dual 10 Figure 3b. MAX538/MAX539 Typical Operating Circuit supplies in this mode. In this range, 1LSB = (2)(VREFIN) (2-12) = (VREFIN)(2-11). The MAX539 is internally configured for unipolar gain = +2 operation. Bipolar Configuration A bipolar range is set up by connecting BIPOFF to REFIN and RFB to VOUT, and operating from dual (5V) supplies (Figure 8). Table 3 shows the DAC-latch contents (input) vs. VOUT (output). In this range, 1LSB = VREFIN (2-11). Four-Quadrant Multiplication The MAX531 can be used as a four-quadrant multiplier by connecting BIPOFF to REFIN and RFB to VOUT, using (1) an offset binary digital code, (2) bipolar power supplies, using dual power supplies, and (3) a bipolar analog input at REFIN within the range VSS + 2V to VDD - 2V, as shown in Figure 9. In general, a 12-bit DAC's output is (D) (VREFIN) (G), where "G" is the gain (+1 or +2) and "D" is the binary representation of the digital input divided by 2 12 or 4096. This formula is precise for unipolar operation. However, for bipolar, offset binary operation, the MSB is really a polarity bit. No resolution is lost, as there are the same number of steps. The output voltage, however, has been shifted from a range of, for example, 0V to 4.096V (G = +2) to a range of -2.048V to +2.048V. Keep in mind that when using the DAC as a four-quadrant multiplier, the scale is skewed. Negative full scale is -VREFIN, while positive full scale is +VREFIN - 1LSB. ______________________________________________________________________________________ +5V, Low-Power, Voltage-Output, Serial 12-Bit DACs SK DIN SO CS I/O MAX531 MAX538 MAX539 DOUT SCLK MICROWIRE PORT MAX531 MAX538 MAX539 SCK DIN MOSI CS I/O DOUT SI MAX531/MAX538/MAX539 SCLK SPI PORT MISO CPOL = 0, CPHA = 0 THE DOUT-SI CONNECTION IS NOT REQUIRED FOR WRITING TO THE DEVICE, BUT MAY BE USED FOR VERIFYING DATA TRANSFER . Figure 4. Microwire Connection THE DOUT-MISO CONNECTION IS NOT REQUIRED FOR WRITING TO THE DEVICE, BUT MAY BE USED FOR VERIFYING DATA TRANSFER . Figure 5. SPI/QSPI Connection +5V +5V VDD REFIN REFIN BIPOFF REFOUT VDD REFOUT 33F 33F AGND MAX531 BIPOFF RFB MAX531 RFB AGND DGND VOUT VOUT VSS VOUT DGND VSS G = +1 0V TO -5V VOUT G = +2 0V TO -5V Figure 6. Unipolar Configuration (0V to +2.048V Output) Figure 7. Unipolar Configuration (0V to +4.096V Output) Table 1. Unipolar Binary Code Table (0V to VREFIN Output), Gain = +1 Table 2. Unipolar Binary Code Table (0V to 2VREFIN Output), Gain = +2 INPUT OUTPUT INPUT OUTPUT 1111 1111 1111 (VREFIN) 4095 4096 1111 1111 1111 +2 (VREFIN) 4095 4096 1000 0000 0001 (VREFIN) 2049 4096 1000 0000 0001 +2 (VREFIN) 2049 4096 1000 0000 0000 1000 0000 0000 +2 (VREFIN) 2048 = +VREFIN 4096 0111 1111 1111 (VREFIN) 2047 4096 0111 1111 1111 +2 (VREFIN) 2047 4096 0000 0000 0001 (VREFIN) 1 4096 0000 0000 0001 +2 (VREFIN) 1 4096 0000 0000 0000 0000 0000 0000 (VREFIN) 2048 = +VREFIN / 2 4096 OV OV ______________________________________________________________________________________ 11 MAX531/MAX538/MAX539 +5V, Low-Power, Voltage-Output, Serial 12-Bit DACs Table 3. Bipolar (Offset Binary) Code Table (-VREFIN to +VREFIN Output) +5V BIPOFF REFOUT 33F OUTPUT INPUT REFIN 1111 1111 1111 (+VREFIN) 2047 2048 1000 0000 0001 (+VREFIN) 1 2048 1000 0000 0000 0111 1111 1111 (-VREFIN) 1 2048 0000 0000 0001 (-VREFIN) 2047 2048 0000 0000 0000 (-VREFIN) 2048 = -VREFIN 2048 MAX531 RFB AGND DGND VOUT VOUT 0V -5V Figure 8. Bipolar Configuration (-2.048V to +2.048V Output) Single-Supply Linearity As with any amplifier, the MAX531/MAX538/MAX539's output buffer can be positive or negative. When the offset is positive, it is easily accounted for (Figure 10). However, when the offset is negative, the buffer output cannot follow linearly when there is no negative supply. In that case, the amplifier output (VOUT) remains at ground until the DAC voltage is sufficient to overcome the offset and the output becomes positive. Normally, linearity is measured after accounting for zero error and gain error. Since, in single-supply operation, the actual value of a negative offset is unknown, it cannot be accounted for during test. Additionally, the output buffer amplifier exhibits a nonlinearity near-zero output when operating with a single supply. To account for this nonlinearity in the MAX531/MAX538/MAX539, linearity and gain error are measured from code 11 to code 4095. The output buffer's offset and nonlinear behavior do not affect monotonicity, and these DACs are guaranteed monotonic starting with code zero. In dual-supply operation, linearity and gain error are measured from code 0 to 4095. Power-Supply Bypassing and Ground Management Best system performance is obtained with printed circuit boards that use separate analog and digital ground planes. Wire-wrap boards are not recommended. The two ground planes should be connected together at the low-impedance power-supply source. 12 DGND and AGND should be connected together at the chip. For the MAX531 in single-supply applications, connect VSS to AGND at the chip. The best ground connection may be achieved by connecting the DAC's DGND and AGND pins together and connecting that point to the system analog ground plane. If the DAC's DGND is connected to the system digital ground, digital noise may get through to the DAC's analog portion. Bypass V DD (and V SS in dual-supply mode) with a 0.1F ceramic capacitor, connected between VDD and AGND (and between VSS and AGND). Mount with short leads close to the device. Ferrite beads may also be used to further isolate the analog and digital power supplies. Figures 11a and 11b illustrate the grounding and bypassing scheme described. Saving Power When the DAC is not being used by the system, minimize power consumption by setting the appropriate code to minimize load current. For example, in bipolar mode, with a resistive load to ground, set the DAC code to mid-scale (Table 3). If there is no output load, minimize internal loading on the reference by setting the DAC to all 0s (on the MAX531, use CLR). Under this condition, REFIN is high impedance and the op amp operates at its minimum quiescent current. Due to these low current levels, the output settling time for an input code close to 0 typically increases to 60s (no more than 100s). ______________________________________________________________________________________ +5V, Low-Power, Voltage-Output, Serial 12-Bit DACs REFOUT VDD MAX531/MAX538/MAX539 CS CLR DIN DOUT VSS SIGNAL IN REFIN VOUT INVERTED R-2R DAC 2R MAX531 2R RFB BIPOFF OUTPUT (LSB) POSITIVE OFFSET 2.048V 4 NEGATIVE OFFSET 3 2 1 0 1 2 3 4 5 6 7 8 DAC CODE (LSB) Figure 9. MAX531 Connected as Four-Quadrant Multiplier. The unused REFOUT is connected to VDD. Figure 10. Single-Supply Offset AC Considerations Digital Feedthrough High-speed serial data at any of the digital input or output pins may couple through the DAC package and cause internal stray capacitance to appear at the DAC output as noise, even though CS is held high (see Typical Operating Characteristics). This digital feedthrough is tested by holding CS high, transmitting 555 hex from DIN to DOUT. Analog Feedthrough Because of internal stray capacitance, higher frequency analog input signals may couple to the output as shown in the Analog Feedthrough vs. Frequency graph in the Typical Operating Characteristics. It is tested by holding CS high, setting the DAC code to all 0s, and sweeping REFIN. ANALOG GROUND PLANE 0.1F 1 14 2 13 3 12 4 11 5 10 6 9 7 8 0.1F (a) MAX531 BYPASSING 1 8 2 7 3 6 4 5 0.1F (b) MAX538/MAX539 BYPASSING Figure 11. Power-Supply Bypassing ______________________________________________________________________________________ 13 MAX531/MAX538/MAX539 +5V, Low-Power, Voltage-Output, Serial 12-Bit DACs __Ordering Information (continued) PART MAX531AEPD MAX531BEPD MAX531AESD MAX531BESD MAX538ACPA MAX538BCPA MAX538ACSA MAX538BCSA MAX538BC/D MAX538AEPA MAX538BEPA MAX538AESA MAX538BESA MAX539ACPA MAX539BCPA MAX539ACSA MAX539BCSA MAX539BC/D MAX539AEPA MAX539BEPA MAX539AESA MAX539BESA TEMP. RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C -40C to +85C -40C to +85C -40C to +85C -40C to +85C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C -40C to +85C -40C to +85C -40C to +85C -40C to +85C PIN-PACKAGE 14 Plastic DIP 14 Plastic DIP 14 SO 14 SO 8 Plastic DIP 8 Plastic DIP 8 SO 8 SO Dice* 8 Plastic DIP 8 Plastic DIP 8 SO 8 SO 8 Plastic DIP 8 Plastic DIP 8 SO 8 SO Dice* 8 Plastic DIP 8 Plastic DIP 8 SO 8 SO ERROR (LSB) 1/2 1 1/2 1 1/2 1 1/2 1 1 1/2 1 1/2 1 1/2 1 1/2 1 1 1/2 1 1/2 1 ____Pin Configurations (continued) TOP VIEW BIPOFF 1 DIN 2 CLR 3 14 RFB 13 VDD MAX531 SCLK 4 12 VOUT 11 VSS CS 5 10 REFOUT DOUT 6 9 REFIN DGND 7 8 AGND DIP/SO ___________________Chip Topography DIN (BIPOFF) (RFB) (CLR) VDD VOUT *Dice are specified at TA = +25C only. 0.120" (3.048mm) SCLK (VSS) CS (REFOUT) DOUT REFIN (DGND) AGND 0.080" (2.032mm) ( ) ARE FOR MAX531 ONLY. TRANSISTOR COUNT: 922 SUBSTRATE CONNECTED TO VDD 14 ______________________________________________________________________________________ +5V, Low-Power, Voltage-Output, Serial 12-Bit DACs PDIPN.EPS ______________________________________________________________________________________ 15 MAX531/MAX538/MAX539 ________________________________________________________Package Information __________________________________________Package Information (continued) SOICN.EPS MAX531/MAX538/MAX539 +5V, Low-Power, Voltage-Output, Serial 12-Bit DACs Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 16 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 (c) 1997 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.