IRFP1405PBF - INFINEON TECHNOLOGIES AG

HEXFET® Power MOSFET

VDSS = 55V

RDS(on) = 5.3mΩ

ID = 95A

08/18/10

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This HEXFET® Power MOSFET utilizes the latest

processing techniques to achieve extremely low

on-resistance per silicon area. Additional features

of this design are a 175°C junction operating

temperature, fast switching speed and improved

repetitive avalanche rating. These features

combine to make this design an extremely efficient

and reliable device for use in a wide variety of

applications.

Description

Advanced Process Technology

Ultra Low On-Resistance

175°C Operating Temperature

Fast Switching

Repetitive Avalanche Allowed up to Tjmax

Lead-Free

Features

HEXFET® is a registered trademark of International Rectifier.

* Rθ is measured at TJ approximately 90°C

IRFP1405PbF

Absolute Maximum Ratin

Parameter Units

ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Silicon Limited)

ID @ TC = 100°C Continuous Drain Current, VGS @ 10V A

ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Package Limited

)

IDM

d D

urren

PD @TC = 25°C Power Dissipation W

Linear Derating Factor W/°C

VGS Gate-to-Source Volta

e V

EAS (Thermally limited)

anc

ner

EAS (Tested )

anc

ner

gy T

d V

IAR

anc

urren



EAR

epe

titi

anc

ner

TJ Operatin

Junction and

TSTG Stora

e Temperature Ran

e°C

Soldering Temperature, for 10 seconds

Mounting Torque, 6-32 or M3 screw

Thermal Resistance

Parameter Typ. Max. Units

RθJC Junction-to-Case * ––– 0.49

Rθcs Case-to-Sink, Flat, Greased Surface 0.24 ––– °C/W

RθJA Junction-to-Ambient * ––– 40

1060

530

See Fig.12a, 12b, 15, 16

310

2.0

± 20

Max.

160

110

640

-55 to + 175

300 (1.6mm from case )

10 lbf

in (1.1N

PD - 95509A

TO-247AC

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Electrical Characteristics @ TJ = 25°C (unless otherwise specified)

Parameter Min. Typ. Max. Units

V(BR)DSS Drain-to-Source Breakdown Voltage 55 ––– ––– V

∆V(BR)DSS

∆TJ Breakdown Voltage Temp. Coefficient ––– 0.058 ––– V/°C

RDS(on) Static Drain-to-Source On-Resistance ––– 4.2 5.3 mΩ

VGS(th) Gate Threshold Voltage 2.0 ––– 4.0 V

gfs Forward Transconductance 77 ––– ––– S

IDSS Drain-to-Source Leakage Current ––– ––– 20 µA

––– ––– 250

IGSS Gate-to-Source Forward Leakage ––– ––– 200 nA

Gate-to-Source Reverse Leakage ––– ––– -200

QgTotal Gate Charge ––– 120 180

Qgs Gate-to-Source Charge ––– 30 ––– nC

Qgd Gate-to-Drain ("Miller") Charge ––– 53 –––

td(on) Turn-On Delay Time ––– 12 –––

trRise Time ––– 160 –––

td(off) Turn-Off Delay Time ––– 140 ––– ns

tfFall Time ––– 150 –––

LDInternal Drain Inductance ––– 5.0 ––– Between lead,

nH 6mm (0.25in.)

LSInternal Source Inductance ––– 13 ––– from package

and center of die contact

Ciss Input Capacitance ––– 5600 –––

Coss Output Capacitance ––– 1310 –––

Crss Reverse Transfer Capacitance ––– 350 ––– pF

Coss Output Capacitance ––– 6550 –––

Coss Output Capacitance ––– 920 –––

Coss eff. Effective Output Capacitance ––– 1750 –––

Source-Drain Ratin

s and Characteristics

Parameter Min. Typ. Max. Units

ISContinuous Source Current ––– ––– 95

(Body Diode) A

ISM Pulsed Source Current ––– ––– 640

(Body Diode)

c

VSD Diode Forward Voltage ––– ––– 1.3 V

trr Reverse Recovery Time ––– 70 110 ns

Qrr Reverse Recovery Charge ––– 170 260 nC

ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz

VGS = 0V, VDS = 44V, ƒ = 1.0MHz

VGS = 0V, VDS = 0V to 44V

VGS = 10V

VDD = 28V

ID = 95A

RG = 2.6 Ω

TJ = 25°C, IS = 95A, VGS = 0V

TJ = 25°C, IF = 95A, VDD = 28V

di/dt = 100A/

Conditions

VGS = 0V, ID = 250µA

Reference to 25°C, ID = 1mA

VGS = 10V, ID = 95A

VDS = VGS, ID = 250µA

VDS = 55V, VGS = 0V

VDS = 55V, VGS = 0V, TJ = 125°C

MOSFET symbol

showing the

integral reverse

p-n junction diode.

VDS = 25V, ID = 95A

ID = 95A

VDS = 44V

Conditions

VGS = 10V

VGS = 0V

VDS = 25V

ƒ = 1.0MHz

VGS = 20V

VGS = -20V

 Repetitive rating; pulse width limited by

max. junction temperature. (See fig. 11).

 Limited by TJmax, starting TJ = 25°C, L = 0.12mH

RG = 25Ω, IAS = 95A, VGS =10V. Part not

recommended for use above this value.

 Pulse width ≤ 1.0ms; duty cycle ≤ 2%.

Notes:

 Coss eff. is a fixed capacitance that gives the same charging time

as Coss while VDS is rising from 0 to 80% VDSS .

 Limited by TJmax , see Fig.12a, 12b, 15, 16 for typical repetitive

avalanche performance.

 This value determined from sample failure population. 100%

tested to this value in production.

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Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics

Fig 3. Typical Transfer Characteristics Fig 4. Typical Forward Transconductance

Vs. Drain Current

0 1 10 100

0.1 110 100

VDS, Drain-to-Source Voltage (V)

100

1000

ID, Drain-to-Source Current (A)

≤ 60µs PULSE WIDTH

Tj = 175°C

4.5V

VGS

TOP 15V

10V

8.0V

7.0V

6.0V

5.5V

5.0V

BOTTOM 4.5V

4.0 5.0 6.0 7.0 8.0 9.0 10.0

VGS, Gate-to-Source Voltage (V)

100

1000

ID, Drain-to-Source Current (Α)

VDS = 25V

≤ 60µs PULSE WIDTH

TJ = 25°C

TJ = 175°C

0.1 110 100

VDS, Drain-to-Source Voltage (V)

100

1000

ID, Drain-to-Source Current (A)

≤ 60µs PULSE WIDTH

Tj = 25°C

4.5V

VGS

TOP 15V

10V

8.0V

7.0V

6.0V

5.5V

5.0V

BOTTOM 4.5V

0 20406080100

ID, Drain-to-Source Current (A)

100

120

140

Gfs, Forward Transconductance (S)

TJ = 25°C

TJ = 175°C

VDS = 10V

380µs PULSE WIDTH

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Fig 8. Maximum Safe Operating Area

Fig 6. Typical Gate Charge Vs.

Gate-to-Source Voltage

Fig 5. Typical Capacitance Vs.

Drain-to-Source Voltage

Fig 7. Typical Source-Drain Diode

Forward Voltage

110 100

VDS, Drain-to-Source Voltage (V)

2000

4000

6000

8000

10000

C, Capacitance (pF)

Coss

Crss

Ciss

VGS = 0V, f = 1 MHZ

Ciss = C gs + Cgd, C ds SHORTED

Crss = Cgd

Coss = Cds + Cgd

0 40 80 120 160 200

QG Total Gate Charge (nC)

VGS, Gate-to-Source Voltage (V)

VDS= 44V

VDS= 28V

ID= 95A

FOR TEST CIRCUIT

SEE FIGURE 13

0.2 0.6 1.0 1.4 1.8 2.2

VSD, Source-toDrain Voltage (V)

0.1

1.0

10.0

100.0

1000.0

ISD, Reverse Drain Current (A)

TJ = 25°C

TJ = 175°C

VGS = 0V

1 10 100 1000

VDS , Drain-toSource Voltage (V)

0.1

100

1000

10000

ID, Drain-to-Source Current (A)

Tc = 25°C

Tj = 175°C

Single Pulse

1msec

10msec

OPERATION IN THIS AREA

LIMITED BY R DS(on)

100µsec

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Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case

Fig 9. Maximum Drain Current Vs.

Case Temperature

Fig 10. Normalized On-Resistance

Vs. Temperature

25 50 75 100 125 150 175

TC , Case Temperature (°C)

100

150

200

ID , Drain Current (A)

LIMITED BY PACKAGE

-60 -40 -20 020 40 60 80 100 120 140 160 180

TJ , Junction Temperature (°C)

0.5

1.0

1.5

2.0

2.5

RDS(on) , Drain-to-Source On Resistance

(Normalized)

ID = 95A

VGS = 10V

1E-006 1E-005 0.0001 0.001 0.01 0.1

t1 , Rectangular Pulse Duration (sec)

0.0001

0.001

0.01

0.1

Thermal Response ( Z thJC )

0.20

0.10

D = 0.50

0.02

0.01

0.05

SINGLE PULSE

( THERMAL RESPONSE ) Notes:

1. Duty Factor D = t1/t2

2. Peak Tj = P dm x Zthjc + Tc

Ri (°C/W) τi (sec)

0.2529 0.00080

0.2368 0.014283

τJ

τ1

τ2

R1R2

τC

Ci i/Ri

Ci= τi/Ri

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Charge

10 V

Fig 13b. Gate Charge Test Circuit

Fig 13a. Basic Gate Charge Waveform

Fig 12c. Maximum Avalanche Energy

Vs. Drain Current

Fig 12b. Unclamped Inductive Waveforms

Fig 12a. Unclamped Inductive Test Circuit

(BR)DSS

Fig 14. Threshold Voltage Vs. Temperature

0.01

Ω

D.U.T

VDS

-V

DRIVER

15V

20V

VGS

25 50 75 100 125 150 175

Starting TJ, Junction Temperature (°C)

500

1000

1500

2000

EAS, Single Pulse Avalanche Energy (mJ)

I D

TOP 16A

20A

BOTTOM 95A

-75 -50 -25 025 50 75 100 125 150 175

TJ , Temperature ( °C )

1.5

2.0

2.5

3.0

3.5

4.0

VGS(th) Gate threshold Voltage (V)

ID = 250µA

VCC

DUT

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Fig 15. Typical Avalanche Current Vs.Pulsewidth

Fig 16. Maximum Avalanche Energy

Vs. Temperature

Notes on Repetitive Avalanche Curves , Figures 15, 16:

(For further info, see AN-1005 at www.irf.com)

1. Avalanche failures assumption:

Purely a thermal phenomenon and failure occurs at a

temperature far in excess of Tjmax. This is validated for

every part type.

2. Safe operation in Avalanche is allowed as long asTjmax is

not exceeded.

3. Equation below based on circuit and waveforms shown in

Figures 12a, 12b.

4. PD (ave) = Average power dissipation per single

avalanche pulse.

5. BV = Rated breakdown voltage (1.3 factor accounts for

voltage increase during avalanche).

6. Iav = Allowable avalanche current.

7. ∆T = Allowable rise in junction temperature, not to exceed

Tjmax (assumed as 25°C in Figure 15, 16).

tav = Average time in avalanche.

D = Duty cycle in avalanche = tav ·f

ZthJC(D, tav) = Transient thermal resistance, see figure 11)

PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC

Iav = 2DT/ [1.3·BV·Zth]

EAS (AR) = PD (ave)·tav

1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01

tav (sec)

100

1000

10000

Avalanche Current (A)

0.05

Duty Cycle = Single Pulse

0.10

Allowed avalanche Current vs

avalanche pulsewidth, tav

assuming ∆Tj = 25°C due to

avalanche losses. Note: In no

case should Tj be allowed to

exceed Tjmax

0.01

25 50 75 100 125 150 175

Starting TJ , Junction Temperature (°C)

100

200

300

400

500

600

EAR , Avalanche Energy (mJ)

TOP Single Pulse

BOTTOM 1% Duty Cycle

ID = 95A

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Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel

HEXFET® Power MOSFETs

Circuit Layout Considerations

• Low Stray Inductance

• Ground Plane

• Low Leakage Inductance

Current Transformer

P.W. Period

di/dt

Diode Recovery

dv/dt

Ripple ≤5%

Body Diode Forward Drop

Re-Applied

Voltage

Reverse

Recovery

Current

Body Diode Forward

Current

VGS=10V

VDD

ISD

Driver Gate Drive

D.U.T. ISD Waveform

D.U.T. VDS Waveform

Inductor Curent

D = P. W .

Period

* VGS = 5V for Logic Level Devices







RGVDD

• dv/dt controlled by RG

• Driver same type as D.U.T.

• ISD controlled by Duty Factor "D"

• D.U.T. - Device Under Test

D.U.T



VDS

90%

10%

VGS

d(on)

d(off)

VDS

Pulse Width ≤ 1 µs

Duty Factor ≤ 0.1 %

VGS

D.U.T.

10V

VDD

Fig 18a. Switching Time Test Circuit

Fig 18b. Switching Time Waveforms

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Data and specifications subject to change without notice.

This product has been designed and qualified forIndustrial market.

Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105

TAC Fax: (310) 252-7903

Visit us at www.irf.com for sales contact information.08/2010

TO-247AC Part Marking Information

EXAMPLE:

AS SEMBLED ON WW 35, 2000

LOT CODE 5657

WITH ASSEMBLY

THIS IS AN IRFPE30

IN THE ASSEMBLY LINE "H" 035H

LOGO

INT E RNAT IONAL

RECTIF IER IRF PE30

LOT CODE

ASSEMBLY

56 57

PART NUMBER

DAT E CODE

YEAR 0 = 2000

WEEK 35

LINE H

Note: "P" in assembly line

position indicates "Lead-Free"

TO-247AC Package Outline

Dimensions are shown in millimeters (inches)

TO-247AC packages are not recommended for Surface Mount Application.

Notes:

1. For an Automotive Qualified version of this part please seehttp://www.irf.com/product-info/auto/

2. For the most current drawing please refer to IR website at http://www.irf.com/package/