KSZ8463FMLI - MICROCHIP TECHNOLOGY

KSZ8463ML/RL/FML/FRL

IEEE 1588 Precision Tim e Proto co l-

Enabled, Three -Port, 10/100-Managed

Switch with MII or RMI I

Revision 1.0

ETHERSYNCH is a trademark of Micrel, Inc.

LinkMD is a registered trademark of Micrel, Inc.

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com

June 11, 2014

Revision 1.0

General Description

The KSZ8463 ETHERSYNCH™ product line consists of

IEEE 1588v2 enabled Ethernet switches, providing

integrated communications and synchronization for a

range of Industrial Ethernet applications.

The KSZ8463 ETHERSYNCH product line enables

distributed, daisy-chained topologies preferred for

Industrial Ethernet networks. Conventional centralized

(i.e., star-wired) topologies are also supported for dual-

homed, fault-tolerant arrangements.

A flexible set of standard MAC interfaces is provided to

interface to external host processors with embedded

Ethernet MACs :

• KSZ8463ML: Media Independent Interface (MII)

• KSZ8463RL: Reduced Media Independent Interface

(RMII)

• KSZ8463FML: MII, supports 100BASE-FX fiber in

addition to 10/100BASE-TX copper

• KSZ8463FRL: RMII, supports 100BASE-FX fiber in

addition to 10/100BASE-TX copper

The KSZ8463 devices incorporate the IEEE 1588v2

protocol. Sub-m icros econd s ynchronization is av ailable v ia

the use of hardware-based time-stam ping and transparent

clocks making it the ideal solution for time synchronized

Layer 2 communication in critical industrial applications.

Extensive general purpose I/O (GPIO) capabilities are

available to use with the IEEE 1588v2 PTP to efficiently

and accurately interface to locally connected devices.

Complementing the industry’s most-integrated IEEE

1588v2 device is a precision timing protocol (PTP) v2

software stack that has been pre-qualified with the

KSZ84xx product family. The PTP stack has been

optimized around the KSZ84xx chip architecture, and is

available in source code format along with Micrel’s chip

driver.

ETHERSYNCH™

The KSZ8463 product line is built upon Micrel’s industry-

leading Ethernet technology, with features designed to

offload host processing and streamline your overall design.

• Wire-speed Ethernet switching fabric with extensive

filtering

• Two integrated 10/100BASE-TX PHY transceivers,

featuring the industry’s lowest power consumption

• Full-featured quality-of-service (QoS) support

• Flexible management options that support common

standard inter f ac es

The wire-speed, store-and-forward switching fabric

provides a full com plement of QoS and congestion control

features optimized for real-time Ethernet.

A robust assortment of power-management features

including energy-efficient Ethernet (EEE) have been

designed in to satis fy energy effic ient en viro nments.

Datasheets and support documentation are available on

Micrel’s web site at: www.micrel.com.

Functional Diagram

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

2 Revision 1.0

Functional Diagram

KSZ8463ML/RL/FML/FRL Functional Diagram

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

3 Revision 1.0

Features

Management Capabilities

• The KSZ8463ML/RL/FML/FRL includes all the functions

of a 10/100BASE-T/TX/FX switch system which

combines a switch engine, frame buffer management,

address look-up table, queue management, MIB

counters, media access controllers (MAC) and PHY

transceivers

• Non-blocking store-and-forward switch fabric assures

fast packet delivery by utilizing 1024 entry forwarding

table

• Port mirroring/monitoring/sniffing: ingress and/or egress

traffic to any port

• MIB counters for fully-compliant statistics gathering −

34 counters per port

• Loopback modes for remote failure diagnostics

• Rapid spanning tree protocol support (RSTP) for

topology management and ring/linear recovery

• Bypass mode, which ensure continuity even when a

Host is disabled or fails

Robust PHY Ports

• Two integrated IEEE 80 2.3/ 802. 3u-c ompliant Etherne t

transceivers supporting 10BASE-T and 100BASE-TX

• Copper and 100BASE-FX fiber mode support in the

KSZ8463FML and KSZ8463FRL

• Copper mode support in the KSZ8463ML and

KSZ8463RL

• On-chip termination resistors and internal biasing for

differential pairs to reduce power

• HP Auto MDI/MDI-X crossover support eliminating the

need to differentiate between straight or crossover

cables in applications

MAC Ports

• Three internal media access control (MAC) units

• MII or RMII interface support on MAC port 3

• 2Kbyte jumbo packet support

• Tail tagging mode (one byte added before FCS) support

at port 3 to inform the processor which ingress port

receives the pack et and its prior ity

• Supports r ed uced media independe nt inter f ac e (RMII)

with 50MHz reference clock input or output

• Support Media Independent Interface (MII) in either PHY

mode or MAC mode on port 3

• Programmable MAC addresses for port 1 and port 2 and

self-address filtering support

• MAC filtering function to filter or forward unknown

unicast packets

• Port 1 and port 2 MACs programmable as either E2E or

P2P transparent clock (TC) ports for 1588 support

• Port 3 MAC programmable as slave or master of

ordinary clock (OC) port for 1588 support

• Micrel Link MD ® cable diagnostic capabilities for

determining cable opens, shorts, and length

Advanced Switch Capabilities

• Non-blocking store-and-forward switch fabric assures

fast packet delivery by utilizing 1024 entry forwarding

table

• IEEE 802.1Q VLAN for up to 16 groups with full range of

VLAN IDs

• IEEE 802.1p/Q tag insertion or removal on a per port

basis (egress) and support double-tagging

• VLAN ID tag/untag options on per port basis

• Fully compliant with IEEE 802.3/802.3u standards

• IEEE 802.3x full-duplex with force-mode option and half-

duplex backpressure collision flow control

• IEEE 802.1w rapid spanning tree protocol support

• IGMP v1/v2/v3 snooping for multicast packet filtering

• QoS/CoS packets prioritization support: 802.1p,

DiffServ-based and re-mapping of 802.1p priority field

per-port basis on four priority levels

• IPv4/IPv6 QoS support

• IPv6 multicast listener discovery (MLD) snooping

support

• Programmable rate limiting at the ingress and egress

ports

• Broadcast storm protection

• Bypass mode to sustain the switch function between

port 1 and port 2 when CPU (port 3) goes into sleep

mode

• 1K entry forwarding table with 32K frame buffer

• Four priority queues with dynamic packet mapping for

IEEE 802.1p, IPv4 TOS (DIFFSERV), IPv6 Traffic

Class, etc.

• Source address filtering for implementing ring topologies

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

4 Revision 1.0

Comprehensive Configuration Registers Access

• High-speed SPI (4-wire, up to 50 MHz) Interface to

access all internal registers

• MII Management (MIIM, MDC/MDIO 2-wire) Interface to

access all PHY registers per clause 22.2.4.5 of the IEEE

802.3 specification

• I/O pin strapping facility to set certain register bits from

I/O pins at reset time

• Control registers configurable on-the-fly

IEEE 1588v2 PTP and Clock Synchronization

• Fully compliant with the I E EE 158 8v2 precision time

protocol

• One-step or two-step transparent clock (TC) timing

corrections

• E2E (end-to-end) or P2P (peer-to-peer) transparent

clock (TC)

• Grandmaster, master, slave, ordinary clock (OC)

support

• IEEE1588v2 PTP Multicast and Unicas t frame support

• Transports of PTP over IPv4/IPv6 UDP and IEEE 802.3

Ethernet

• Delay request-response and peer delay mechanism

• Ingress/egress packet timestamp capture/recording and

checksum update

• Correction field update with residence time and link

delay

• IEEE1588v2 PTP packet filtering unit to reduce host

processor overhead

• A 64-bit adjustable system precision clock

• Twelve trigger output units and twelve timestamp input

units available for flexible IEEE1588v2 control of twelve

programmable GPIO[11:0] pins synchronized to the

precision time clock

• GPIO pin usage for 1 PPS generation, frequency

generator, control bit streams, event monitoring,

precision pulse generation, complex waveform

generation

Power and Power Management

• Single 3.3V power supply with optional VDD I/O for

1.8V, 2.5V or 3.3V

• Integrated low voltage (~1.3V) low-noise regulator

(LDO) output for digital and analog core power

• Supports IEEE P802.3az™ energy-efficient Eth er net

(EEE) to reduce power consumption in transceivers in

LPI state

• Full-chip hardware or software power-down (all registers

value are not saved and strap-in valu e will re-strap after

release the pow er-down)

• Energ y detect power -down (EDPD), which disables the

PHY transceiver when cables are removed

• Dynamic clock tree control to reduce clocking in areas

not in use

• Power consumption less than 0.5W

Additional Features

• Single 25MHz ±50ppm reference clock requirement for

MII mode

• Selectable 25MHz or 50MHz inputs for RMII mode

• Comprehensive programmable two LED indicators

support for link, activity, full/half duplex and 10/100

speed.

• LED pins direct l y contro llab le.

• Industrial temperature range: –40°C to +85°C

• 64-pin (10mm x 10mm) lead free (ROHS) LQFP

package

• 0.11μm technology for lower power consumption

Applications

• Industrial Ethernet applications that employ IEEE 802.3-

compliant MACs. (Ethernet/IP, Profinet, MODBUS TCP,

etc)

• Real-time Ethernet networks requiring sub-microsecond

synchronization over standard Ethernet

• IEC 61850 networks supporting power substation

automation

• Networked measurement and control systems

• Industrial automation and motion control systems

• Test and measurement equipment

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

5 Revision 1.0

Ordering Information

Part Number Temperature Range Package Lead Finish Description

KSZ8463MLI –40

C to +85

C 64-Pin LQFP Pb-Free Industrial Temperature Device with MII Interface

KSZ8463FMLI –40oC to +85oC 64-Pin LQFP Pb-Free Industrial Temperature Device with MII Interface

and Fiber (100BASE-FX) suppo rt

KSZ8463RLI –40oC to +85oC 64-Pin LQFP Pb-Free Industrial Temperature Device with RMII Interface

KSZ8463FRLI –40oC to +85oC 64-Pin LQFP Pb-Free Industrial Temperature Device with RMII Interface

and Fiber (100BASE-FX) suppo rt

KSZ8463MLI-EVAL Evaluation Board with KSZ8463MLI. Also supports KSZ8463FMLI, KSZ8463RLI and KSZ8463FRLI.

Revision History

Revision

Date

Summary of Changes

1.0 6/11/14 Initial release of product − S. Thompson

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

6 Revision 1.0

Contents

List of Figures ........................................................................................................................................................................ 15

List of Tables ......................................................................................................................................................................... 16

Acronyms .............................................................................................................................................................................. 17

Pin Configuration ................................................................................................................................................................... 20

Pin Description ...................................................................................................................................................................... 21

Strapping Options ................................................................................................................................................................. 27

Functional Description ........................................................................................................................................................... 28

Physical (PHY) Block ............................................................................................................................................................ 28

100BASE-TX Transmit ...................................................................................................................................................... 28

100BASE-TX Receive ....................................................................................................................................................... 28

Scrambler/De-Scrambler (100BASE-TX Only) .................................................................................................................. 28

PLL Clock Synthesizer (Recovery) .................................................................................................................................... 28

100BASE-FX Operation .................................................................................................................................................... 29

100BASE-FX Signal Detection .......................................................................................................................................... 29

100BASE-FX Far-End Fault .............................................................................................................................................. 29

10BASE-T Transmit ........................................................................................................................................................... 29

10BASE-T Receive ............................................................................................................................................................ 29

MDI/MDI-X Auto Crossover ............................................................................................................................................... 30

Straight Cab le .................................................................................................................................................................... 30

Crossover Cable ................................................................................................................................................................ 31

Auto-Negotiation ................................................................................................................................................................ 31

LinkMD® Cable Diagnos tic s ............................................................................................................................................... 32

Access............................................................................................................................................................................ 32

Usage ............................................................................................................................................................................. 32

On-Chip Termination Resistors ......................................................................................................................................... 33

Loopback Support ............................................................................................................................................................. 33

Far-End Loopbac k ......................................................................................................................................................... 33

Near-End (Remote) Loopback ....................................................................................................................................... 33

MAC (Media Access Controller) Block .................................................................................................................................. 35

MAC Operation .................................................................................................................................................................. 35

Address Lookup ................................................................................................................................................................. 35

Learning ............................................................................................................................................................................. 35

Migration ............................................................................................................................................................................ 35

Aging .................................................................................................................................................................................. 35

Forwarding ......................................................................................................................................................................... 35

Inter-Packet Gap (IPG) ...................................................................................................................................................... 37

Back-Off Algorithm ............................................................................................................................................................ 37

Late Collis ion ..................................................................................................................................................................... 37

Legal Packet Size .............................................................................................................................................................. 37

Flow Control....................................................................................................................................................................... 38

Half-Duplex Backpressure ................................................................................................................................................. 38

Broadcast Storm Protection ............................................................................................................................................... 39

Port Individual MAC Address and Source Port Filtering ................................................................................................... 39

Switch Block .......................................................................................................................................................................... 40

Switching Engine ............................................................................................................................................................... 40

Spanning Tree Support ..................................................................................................................................................... 40

Rapid Spanning Tree Support ........................................................................................................................................... 41

Discarding State ............................................................................................................................................................. 41

Learning State ................................................................................................................................................................ 41

Forwardi ng Stat e ............................................................................................................................................................ 41

Tail Tagging Mode ............................................................................................................................................................. 41

IGMP Support .................................................................................................................................................................... 42

“IGMP” Snooping ........................................................................................................................................................... 42

“Multicast Address Insertion” in the Static MAC Table .................................................................................................. 42

IPv6 MLD Snooping ........................................................................................................................................................... 42

Port Mirroring Support ....................................................................................................................................................... 43

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

7 Revision 1.0

“Receive Only” Mirror-on-a-Port .................................................................................................................................... 43

“Transmit Only” Mirror-on-a-Port ................................................................................................................................... 43

“Receive and Transmit” Mirror-on-Two-Ports ................................................................................................................ 43

IEEE 802.1Q VLAN Support .......................................................................................................................................... 43

Quality-of-Service (QoS) Priority Support ......................................................................................................................... 44

Port-Bas ed Priority ............................................................................................................................................................ 44

802.1p-Bas ed Priority ........................................................................................................................................................ 44

802.1p Priority Field Re-Mapping ...................................................................................................................................... 45

DiffServ-Based Priority ...................................................................................................................................................... 45

Rate Limiting Support ........................................................................................................................................................ 45

MAC Address Filtering Function ........................................................................................................................................ 46

IEEE 1588 Precision Time Protocol (PTP) Block .................................................................................................................. 47

IEEE 1588 PTP Clock Types ............................................................................................................................................. 48

IEEE 1588 PTP One-Step or Two-Step Clock Operation ................................................................................................. 48

IEEE 1588 PTP Best Master Clock Selection ................................................................................................................... 48

IEEE 1588 PTP System Time Clock ................................................................................................................................. 48

Updating the System Time Clock ...................................................................................................................................... 50

Directly Setting or Reading the Time ............................................................................................................................. 50

Step-Time Adjustment ................................................................................................................................................... 50

Continuous Time Adjustment ......................................................................................................................................... 50

Temporary Time Adjustment ......................................................................................................................................... 50

PTP Clock Initialization .................................................................................................................................................. 51

IEEE 1588 PTP Message Processing ............................................................................................................................... 51

IEEE 1588 PTP Ingress Packet Processing .................................................................................................................. 51

IEEE 1588 PTP Egress Packet Processing ................................................................................................................... 51

IEEE 1588 PTP Event Triggering and Timestamping ....................................................................................................... 52

IEEE 1588 PTP Trigger Output ..................................................................................................................................... 52

IEEE 1588 PTP Event Timestamp Input ........................................................................................................................ 52

IEEE 1588 PTP Event Interrupts ................................................................................................................................... 53

IEEE 1588 GPIO ............................................................................................................................................................ 53

General Purpose and IEEE 1588 Input/Output (GPIO) ........................................................................................................ 54

Overview ............................................................................................................................................................................ 54

GPIO Pin Functionality Control.......................................................................................................................................... 54

GPIO Pin Control Register Layout..................................................................................................................................... 55

GPIO Trigger Output Unit and Timestamp Unit Interrupts ................................................................................................ 57

Using the GPIO Pins with the Trigger Output Units .............................................................................................................. 59

Creating a Low-Going Pulse at a Specific Time ................................................................................................................ 59

Creating a High-Going Pulse at a Specific Time ............................................................................................................... 59

Creating a Free Running Clock Source ............................................................................................................................. 60

Creating Finite Length Periodic Bit Streams at a Specific Time ........................................................................................ 61

Creating Finite Length Non-Uniform Bit Streams at a Specific Time ................................................................................ 61

Creating Complex Waveforms at a Specific Time ............................................................................................................. 62

Using the GPIO Pins with the Timestamp Input Units .......................................................................................................... 64

Device Clocks........................................................................................................................................................................ 66

GPIO and IEEE 1588-Related Clocking ............................................................................................................................ 67

Power .................................................................................................................................................................................... 68

Internal Low Voltage LDO Regulator ................................................................................................................................. 69

Power Manag ement .............................................................................................................................................................. 70

Normal Operation Mode .................................................................................................................................................... 70

Energy-Detect Mode .......................................................................................................................................................... 70

Global Soft Power-Down Mode ......................................................................................................................................... 71

Energy-Efficient Ethernet (EEE) ........................................................................................................................................ 71

Transmit Direction Control for MII Mode ........................................................................................................................... 72

Receive Direction Control for MII Mode ............................................................................................................................ 72

Register s Ass ociate d with EE E ......................................................................................................................................... 72

Interrupt Generation on Power Management-Related Events .............................................................................................. 72

Interfaces ............................................................................................................................................................................... 73

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

8 Revision 1.0

Configuration Interface ...................................................................................................................................................... 73

SPI Slave Serial Bus Conf i gur ation ................................................................................................................................... 73

SPI Register Access Operation Timing ............................................................................................................................. 74

MII Management (MIIM) Interface ..................................................................................................................................... 76

Media Independent Interface (MII) .................................................................................................................................... 76

Reduced Media Independent Interface (RMII) .................................................................................................................. 78

Device Registers ................................................................................................................................................................... 80

Register Map of CPU Accessible I/O Registers .................................................................................................................... 82

I/O Registers ...................................................................................................................................................................... 82

Internal I/O Register Space Mapping for Switch Control and Configuration (0x000 – 0x0FF) ...................................... 82

Internal I/O Register Space Mapping for Interrupts and Global Reset (0x100 − 0x1FF) .............................................. 88

Internal I/O Register Space Mapping for PTP Trigger Output (12 Units, 0x200 − 0x3FF) ............................................ 89

Internal I/O Register Space Mapping for PTP Timestamp Inputs (12 Units, 0x400 – 0x5FF) ....................................... 98

Internal I/O Register Space Mapping for PTP 1588 Clock and Global Control (0x600 – 0x7FF) ............................... 110

Register Bit Definitions ........................................................................................................................................................ 114

Internal I/O Register Space Mapping for Switch Control and Configuration (0x000 – 0x0FF) ....................................... 114

Chip ID and Enable Register (0x000 – 0x001): CIDER ............................................................................................... 114

Switch Global Control Register 1 (0x002 − 0x003): SGCR1 ........................................................................................... 114

Switch Global Control Register 2 (0x004 – 0x0 05) : SG C R2 ........................................................................................... 116

Switch Global Control Register 3 (0x006 – 0x0 07) : SG C R3 ........................................................................................... 117

0x008 – 0x00B: Reserv ed ............................................................................................................................................... 117

Switch Global Control Register 6 (0x00C – 0x00D): SGCR6 .......................................................................................... 118

Switch Global Control Register 7 (0x00E – 0x 00F) : SG CR7 .......................................................................................... 119

MAC Address Registers ...................................................................................................................................................... 120

MAC Address Register 1 (0x010 – 0x011): MACAR1 ..................................................................................................... 120

MAC Address Register 2 (0x012 – 0x013): MACAR2 ..................................................................................................... 120

MAC Address Register 3 (0x014 – 0x015): MACAR3 ..................................................................................................... 120

TOS Priority Control Registers ............................................................................................................................................ 121

TOS Priority Control Register 1 (0x016 – 0x017): TOSR1 .............................................................................................. 121

TOS Priority Control Register 2 (0x018 – 0x019): TOSR2 .............................................................................................. 122

TOS Priority Control Register 3 (0x01A – 0x01B): TOSR3 ............................................................................................. 123

TOS Priority Control Register 4 (0x01C – 0x1D): TOSR4 .............................................................................................. 123

TOS Priority Control Register 5 (0x01E – 0x1F): TOSR5 ............................................................................................... 124

TOS Priority Control Register 6 (0x020 – 0x021): TOSR6 .............................................................................................. 125

TOS Priority Control Register 7 (0x022 – 0x023): TOSR7 .............................................................................................. 125

TOS Priority Control Register 8 (0x024 – 0x025): TOSR8 .............................................................................................. 126

Indirect Acc ess Data Reg ister s ........................................................................................................................................... 127

Indirect Access Data Register 1 (0x026 – 0x027): IADR1 .............................................................................................. 127

Indirect Access Data Register 2 (0x028 – 0x029): IADR2 .............................................................................................. 127

Indirect Access Data Register 3 (0x02A – 0x02B): IADR3 ............................................................................................. 127

Indirect Access Data Register 4 (0x02C – 0x02D): IADR4 ............................................................................................. 127

Indirect Access Data Register 5 (0x02E – 0x02F): IADR5 .............................................................................................. 128

Indirect Access Control Register (0x030 – 0x031): IACR ............................................................................................... 128

Power Management Control and Wake-Up Event Status ................................................................................................... 129

Power Management Control and Wake-Up Event Status (0x032 – 0x033) : PM CTRL ................................................... 129

(0x034 – 0x035): Reserved ............................................................................................................................................. 129

Go Sleep Time and Clock Tree Power-Down Control Registers ........................................................................................ 130

Go Sleep Time Register (0x036 – 0x037): GST.............................................................................................................. 130

Clock Tree Power-Down Control Register (0x038 – 0x039): CTPDC ............................................................................. 130

0x03A – 0x04B: Reserved ............................................................................................................................................... 130

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

9 Revision 1.0

PHY and MII Basic Control Registers ................................................................................................................................. 131

PHY 1 and MII Basic Control Register (0x04C – 0x04D ): P1MBCR ............................................................................... 131

PHY 1 and MII Basic Status Register (0x04E – 0x04F): P1MBSR ................................................................................. 132

PHY 1 PHYID Low Register (0x050 – 0x051): PHY1ILR ................................................................................................ 133

PHY 1 PHYID High Register (0x052 – 0x053): PHY1IHR .............................................................................................. 133

PHY 1 Auto-Negotiation Advertisement Register (0x054 – 0x0 55) : P1 ANA R ................................................................ 134

PHY 1 Auto-Negot iation Link Partner Ability Register (0x056 – 0x057): P1ANLPR ....................................................... 135

PHY 2 and MII Basic Control Register (0x058 – 0x059): P2MBCR ................................................................................ 136

PHY 2 and MII Basic Status Register (0x05A – 0x05B): P2MBSR ................................................................................. 137

PHY 2 PHYID Low Register (0x05C – 0x 05D) : PH Y2IL R ............................................................................................... 138

PHY 2 PHYID High Register (0x05E – 0x05F): PHY2IHR .............................................................................................. 138

PHY 2 Auto-Negotiation Advertisement Register (0x060 – 0x0 61) : P2 ANA R ................................................................ 139

PHY 2 Auto-Negotiation Link Partner Ability Register (0x062 – 0x063): P2ANLPR ....................................................... 140

0x064 – 0x065: Reserved ................................................................................................................................................ 140

PHY1 Special Control and Status Register (0x066 – 0x067): P1PHYCTRL .................................................................. 141

0x068 – 0x069: Reserved ................................................................................................................................................ 141

PHY 2 Special Control and Status Register (0x06A – 0x06B) : P2PHYCT R L ................................................................. 142

Port 1 Control Registers ...................................................................................................................................................... 143

Port 1 Control Register 1 (0x06C – 0x 06D) : P1CR 1 ....................................................................................................... 143

Port 1 Control Register 2 (0x06E – 0x06F ): P1CR2........................................................................................................ 145

Port 1 VID Control Register (0x070 – 0x071): P1VIDCR ................................................................................................ 146

Port 1 Control Register 3 (0x072 – 0x073): P1CR3 ........................................................................................................ 147

Port 1 Ingress Rate Control Register 0 (0x074 – 0x075): P1IRCR0 ............................................................................... 147

Port 1 Ingress Rate Control Register 1 (0x076 – 0x077): P1IRCR1 ............................................................................... 148

Port 1 Egress Rate Control Register 0 (0x078 – 0x079): P1ERCR0 .............................................................................. 149

Port 1 Egress Rate Control Register 1 (0x07A – 0x07B): P1ERCR1 ............................................................................. 149

Port 1 PHY Special Control/Status, LinkMD (0x07C – 0x07D): P1SCSLMD .................................................................. 150

Port 1 Control Register 4 (0x07E – 0x07F ): P1CR4........................................................................................................ 150

Port 1 Status Register (0x080 – 0x 081): P1 SR ............................................................................................................... 152

0x082 – 0x083: Reserved ................................................................................................................................................ 153

Port 2 Control Registers ...................................................................................................................................................... 154

Port 2 Control Register 1 (0x084 – 0x085): P2CR1 ........................................................................................................ 154

Port 2 Control Register 2 (0x086 – 0x087): P2CR2 ........................................................................................................ 155

Port 2 VID Control Register (0x088 – 0x089): P2VIDCR ................................................................................................ 157

Port 2 Control Register 3 (0x08A – 0x08 B) : P2CR 3 ....................................................................................................... 157

Port 2 Ingress Rate Control Register 0 (0x08C – 0x08D): P2IRCR0 .............................................................................. 158

Port 2 Ingress Rate Control Register 1 (0x08E – 0x08F): P2IRCR1 .............................................................................. 158

Port 2 Egress Rate Control Register 0 (0x090 – 0x091): P2ERCR0 .............................................................................. 159

Port 2 Egress Rate Control Register 1 (0x092 – 0x093): P2ERCR1 .............................................................................. 159

Port 2 PHY Special Control/Status, LinkMD® (0x094 – 0x095): P2SCS LMD ................................................................. 160

Port 2 Control Register 4 (0x096 – 0x097): P2CR4 ........................................................................................................ 160

Port 2 Status Register (0x098 – 0x099): P2SR ............................................................................................................... 162

0x09A – 0x09B: Reserved ............................................................................................................................................... 163

Port 3 Control Registers ...................................................................................................................................................... 164

Port 3 Control Register 1 (0x09C – 0x09D): P3CR 1 ....................................................................................................... 164

Port 3 Control Register 2 (0x09E – 0x09F ): P3CR2........................................................................................................ 165

Port 3 VID Control Register (0x0A0 – 0x0A1 ): P3 VID C R ............................................................................................... 166

Port 3 Control Register 3 (0x0A2 – 0x0 A3) : P3CR 3 ....................................................................................................... 167

Port 3 Ingress Rate Control Register 0 (0x0A4 – 0x0A5): P3IRCR0 .............................................................................. 168

Port 3 Ingress Rate Control Register 1 (0x0A6 – 0x0A7): P3IRCR1 .............................................................................. 168

Port 3 Egress Rate Control Register 0 (0x0A8 – 0x0A9): P3ERCR0 ............................................................................. 169

Port 3 Egress Rate Control Register 1 (0x0AA – 0x0AB): P3ERCR1 ............................................................................. 169

Switch Global Control Registers ......................................................................................................................................... 170

Switch Global Control Register 8 (0x0AC – 0x 0AD): SGCR8 ......................................................................................... 170

Switch Global Control Register 9 (0x0AE – 0x 0AF) : S GC R9 ......................................................................................... 171

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

10 Revision 1.0

Source Address Filtering MAC Address Registers ............................................................................................................. 172

Source Address Filtering MAC Address 1 Register Low (0x0B0 – 0x 0 B1) : S AF M AC A 1L ............................................. 172

Source Address Filtering MAC Address 1 Register Middle (0x0B2 – 0x0 B3) : S AFMACA1M ........................................ 172

Source Address Filtering MAC Address 1 Register High (0x0B4 – 0x0B5): SAFMACA1H ............................................ 172

Source Addr ess Filtering MAC Address 2 Register Low (0x0B6 – 0x 0 B7) : S AF M AC A 2L ............................................. 172

Source Address Filtering MAC Address 2 Register Middle (0x0B8 – 0x 0 B9 ): S AF M AC A2 M ........................................ 172

Source Address Filtering MAC Address 2 Register High (0x0BA – 0x0B B) : SAFMACA2H ........................................... 173

0x0BC – 0x0C7: Reserved .............................................................................................................................................. 173

TXQ Rate Control Registers ............................................................................................................................................... 174

Port 1 TXQ Rate Control Register 1 (0x0C8 – 0x0 C9): P1TX QRCR1 ............................................................................ 174

Port 1 TXQ Rate Control Register 2 (0x0CA – 0x0CB): P1TXQRCR2 ........................................................................... 174

Port 2 TXQ Rate Control Register 1 (0x0CC – 0x0CD): P2TXQRCR1 ........................................................................... 175

Port 2 TXQ Rate Control Register 2 (0x0CE – 0x0CF): P2TXQRCR2 ........................................................................... 175

Port 3 TXQ Rate Control Register 1 (0x0D0 – 0x0 D1): P3TX QRCR1 ............................................................................ 176

Port 3 TXQ Rate Control Register 2 (0x0D2 – 0x0 D3): P3TX QRCR2 ............................................................................ 176

0x0D4 – 0x0D5: Reserved .............................................................................................................................................. 176

Input and Output Multiplex Selection Register .................................................................................................................... 177

Input and Output Multiplex Selection Register (0x0D6 – 0x0D7): IO MXS EL .................................................................. 177

Configuration Status and Serial Bus Mode Register........................................................................................................... 178

Configuration Status and Serial Bus Mode Register (0x0D8 – 0x0D9): CFGR .............................................................. 178

0x0DA – 0x0DB: Reserved .............................................................................................................................................. 178

Port 1 Auto-Ne got iat ion Re gis ters ....................................................................................................................................... 179

Port 1 Auto-Negotiation Next Page Transmit Register (0x0DC – 0x0D D) : P1 AN PT ...................................................... 179

Port 1 Auto-Negotiation Link Partner Received Next Page Register (0x0DE – 0x0DF): P1ALPRNP ............................ 180

Port 1 EEE Registers .......................................................................................................................................................... 181

Port 1 EEE and Link Partner Advertisement Register (0x0E0 – 0x 0 E1) : P1 EEEA ......................................................... 181

Port 1 EEE Wake Error Count Register (0x0E2 – 0x0E3): P1EEEWEC ........................................................................ 182

Port 1 EEE Control/ Stat us and Aut o-Neg oti ati on Ex pa nsion Reg is ter (0x0 E4 – 0x0E5): P1EEEC S ............................. 182

Port 1 LPI Recovery Time Counter Register ....................................................................................................................... 184

Port 1 LPI Recovery Time Counter Register (0x0E6): P1LPIRTC .................................................................................. 184

Buffer Load-to-LPI Control 1 Register ................................................................................................................................. 184

Buffer Load to LPI Control 1 Register (0x0E7): BL2LPIC1 ............................................................................................. 184

Port 2 Auto-Ne got iat ion Re gis ters ....................................................................................................................................... 185

Port 2 Auto-Negotiation Next Page Transmit Register (0x0E8 – 0x0E9 ): P2 AN PT ........................................................ 185

Port 2 Auto-Negotiation Link Partner Received Next Page Register (0x0EA – 0x0EB) : P2ALPRNP ............................ 186

Port 2 EEE Registers .......................................................................................................................................................... 187

Port 2 EEE and Link Partner Advertisement Register (0x0EC – 0x0ED): P2EEEA ....................................................... 187

Port 2 EEE Wake Error Count Register (0x0EE – 0x0EF): P2EEEWEC ........................................................................ 188

Port 2 EEE Control/ Stat us and Aut o-Neg oti ati on Ex pa nsion Reg is ter (0x0F0 – 0x0F1): P2EEECS ............................. 188

Port 2 LPI Recovery Time Counter Register ....................................................................................................................... 190

Port 2 LPI Recovery Time Counter Register (0x0F2): P2LPIRTC .................................................................................. 190

PCS EEE Control Register .................................................................................................................................................. 190

PCS EEE Control Register (0x0F3): PCSEEEC ............................................................................................................. 190

Empty TXQ-to-LPI Wait Time Control Register .................................................................................................................. 190

Empty TXQ to LPI Wait Time Control Register (0x0F4 – 0x 0F5) : ET LWTC ................................................................... 190

Buffer Load-to-LPI Control 2 Register ................................................................................................................................. 191

Buffer Load to LPI Control 2 Register (0x0F6 – 0x0F7): BL2LPIC2 ............................................................................... 191

0x0F8 – 0x0FF: Reserved ............................................................................................................................................... 191

Internal I/O Register Space Mapping for Interrupts and Global Reset (0x100 – 0x1FF) .................................................... 192

0x100 – 0x123: Reserved ................................................................................................................................................ 192

Memory BIST Info Register (0x124 – 0x125): MBIR ....................................................................................................... 192

Global Reset Register (0x126 – 0x127): GRR ................................................................................................................ 193

0x128 – 0x18F: Reserved ............................................................................................................................................... 193

Interrupt Enable Register (0x190 – 0x191): IER ............................................................................................................. 193

Interrupt Status Register (0x192 – 0x193): ISR .............................................................................................................. 194

0x194 – 0x1FF: Reserved ............................................................................................................................................... 194

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

11 Revision 1.0

Internal I/O Register Space Mapping for Trigger Output Units (12 Units, 0x200 – 0x3FF) ................................................ 195

Trigger Error Register (0x200 – 0x201): TRIG_ERR ...................................................................................................... 195

Trigger Active Register (0x202 – 0x203): TRIG_ACTIVE ............................................................................................... 195

Trigger Done Register (0x204 – 0x205): TRIG_DONE ................................................................................................... 195

Trigger Enable Register (0x206 – 0x207): TRIG_EN ...................................................................................................... 196

Trigger Software Reset Register (0x208 – 0x209): TRIG_SW_RST .............................................................................. 196

Trigger Output Unit 12 Output PP S Puls e-Width Register (0x20A – 0x20B): TRIG12_PPS_WIDTH ............................ 196

0x20C – 0x 21F: R eser v ed ............................................................................................................................................... 196

Trigger Output Unit 1 Target Time in Nanoseconds Low-Word Register (0x220 – 0x221): TRIG1_TGT_NSL ............. 197

Trigger Output Unit 1 Target Time in Nanoseconds High-Word Register (0x222 – 0x223): TRIG1_TGT_NSH ............ 197

Trigger Output Unit 1 Target Time in Seconds Low-Word Register (0x224 – 0x225): TRIG1_TGT_SL ........................ 197

Trigger Output Unit 1 Target Time in Seconds High-Word Register (0x226 – 0x227): TRIG1_TGT_SH ....................... 197

Trigger Output Unit 1 Configuration and Control Register 1 (0x228 – 0x229): TRIG1_CFG_1 ...................................... 197

Trigger Output Un it 1 Confi gurati on and Control Register 2 (0x22A – 0x22B): TRIG1_CFG_2 ..................................... 199

Trigger Output Unit 1 Configuration and Control Register 3 (0x22C – 0x22D): TRIG1_CFG_3 .................................... 199

Trigger Output Unit 1 Configuration and Control Register 4 (0x22E – 0x22F): TRIG1_CFG_4 ..................................... 199

Trigger Output Unit 1 Configuration and Control Register 5 (0x230 – 0x231): TRIG1_CFG_5 ...................................... 199

Trigger Output Unit 1 Configuration and Control Register 6 (0x232 – 0x233): TRIG1_CFG_6 ...................................... 200

Trigger Output Unit 1 Configuration and Control Register 7 (0x234 – 0x235): TRIG1_CFG_7 ...................................... 200

Trigger Output Unit 1 Configuration and Control Register 8 (0x236 – 0x237): TRIG1_CFG_8 ...................................... 200

0x238 – 0x23F: Reserved ............................................................................................................................................... 200

Trigger Output Unit 2 Target Time and Output Configuration/Control Registers (0x240 – 0x257) ................................. 200

Trigger Output Unit 2 Configuration and Control Register 1 (0x248 – 0x249): TRIG2_CFG_1 ...................................... 201

0x258 – 0x25F: Reserved ............................................................................................................................................... 201

Trigger Output Unit 3 Target Time and Output Configuration/Control Registers (0x260 – 0x277) ................................. 201

0x278 – 0x27F: Reserved ............................................................................................................................................... 201

Trigger Output Unit 4 Target Time and Output Configuration/Control Registers (0x280 – 0x297) ................................. 201

0x298 – 0x29F: Reserved ............................................................................................................................................... 201

Trigger Output Unit 5 Target Time and Output Configuration/Control Registers (0x2A0 – 0x2B7) ................................ 201

0x2B8 – 0x2BF: Reserved ............................................................................................................................................... 201

Trigger Output Unit 6 Target Time and Output Configuration/Control Registers (0x2C0 – 0x2D7) ................................ 201

0x2D8 – 0x 2DF: Res erv ed .............................................................................................................................................. 201

Trigger Output Unit 7 Target Time and Output Configuration/Control Registers (0x2E0 – 0x2F7) ................................ 202

0x2F8 – 0x2FF: Reserved ............................................................................................................................................... 202

Trigger Output Unit 8 Target Time and Output Configuration/Control Registers (0x300 – 0x317) ................................. 202

0x318 – 0x31F: Reserved ............................................................................................................................................... 202

Trigger Output Unit 9 Target Time and Output Configuration/Control Registers (0x320 – 0x337) ................................. 202

0x338 – 0x33F: Reserved ............................................................................................................................................... 202

Trigger Output Unit 10 Target Time and Output Configuration/Control Registers (0x340 – 0x357) ............................... 202

0x358 – 0x35F: Reserved ............................................................................................................................................... 202

Trigger Output Unit 11 Target Time and Output Configuration/Control Registers (0x360 – 0x377) ............................... 202

0x378 – 0x37F: Reserved ............................................................................................................................................... 202

Trigger Output Unit 12 Target Time and Output Configuration/Control Registers (0x380 – 0x397) ............................... 202

0x398 – 0x3FF: Reserved ............................................................................................................................................... 202

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

12 Revision 1.0

Internal I/O Register Space Mapping for PTP Timestamp Inputs (12 Units, 0x400 − 0x5FF) ........................................... 203

Timestamp Enable Register (0x402 – 0x403): TS_EN ................................................................................................... 203

Timestamp Software Reset Register (0x404 – 0x 4 05): TS_SW _RST ............................................................................ 203

0x406 – 0x41F: Reserved ............................................................................................................................................... 203

Timestamp Unit 1 Status Register (0x420 – 0x421): TS1_STATUS............................................................................... 204

Timestamp Unit 1 Configuration and Control Register (0x422 – 0x423): TS1_CFG ...................................................... 204

Timestamp Unit 1 Input 1st Sample Time in Nanoseconds Low-Word Register (0x424 – 0x425): TS1_SMPL1_NSL . 205

Timestamp Unit 1 Input 1st Sample Time in Nanoseconds High-Word Register (0x426 – 0x427): TS1_SMPL1_NSH 205

Timestamp Unit 1 Input 1st Sample Time in Seconds Low-Word Register (0x428 – 0x429): TS1_SMPL1_SL ............ 205

Timestamp Unit 1 Input 1st Sample Time in Seconds High-Word Register (0x42A – 0x42B): TS1_SMPL1_SH .......... 205

Timestamp Unit 1 Input 1st Sample Time in Sub-Nanoseconds Register (0x42C – 0x42D): TS1_SMPL1_SUB_NS .... 206

0x42E – 0x4 33: R eser v ed ............................................................................................................................................... 206

Timestamp Unit 1 Input 2nd Sample Time in Nanoseconds Low-Word Register (0x434 – 0x435): TS1_SMPL2_NSL .. 206

Timestamp Unit 1 Input 2nd Sample Time in Nanoseconds High-Word Register (0x436 – 0x437): TS1_SMPL2_NSH 206

Timestamp Unit 1 Input 2nd Sample Time in Seconds Low-Word Register (0x438 – 0x439): TS1_SMPL2_SL ............ 206

Timestamp Unit 1 Input 2nd Sample Time in Seconds High-Word Register (0x43A – 0x43B): TS1_SMPL2_SH .......... 207

Timestamp Unit 1 Input 2nd Sample Time in Sub-Nanoseconds Register (0x43C – 0x43D): TS1_SMPL2_SUB_NS ... 207

0x43E – 0x43F: Reserved ............................................................................................................................................... 207

Timestamp Unit 2 Status/Configuration/Control and Input 1st Sample Time Registers (0x440 – 0x44D)....................... 207

0x44E – 0x4 53: R eser v ed ............................................................................................................................................... 207

Timestamp Unit 2 Input 2nd Sample Time Registers (0x454 – 0x45D) ........................................................................... 207

0x45E – 0x45F: Reserved ............................................................................................................................................... 207

Timestamp Unit 3 Status/Configuration/Control and Input 1st Sample Time Registers (0x460 – 0x46D)....................... 207

0x46E – 0x4 73: R eser v ed ............................................................................................................................................... 207

Timestamp Unit 3 Input 2nd Sample Time Registers (0x474 – 0x47D) ........................................................................... 207

0x47E – 0x47F: Reserved ............................................................................................................................................... 208

Timestamp Unit 4 Status/Configuration/Control and Input 1st Sample Time Registers (0x480 – 0x48D)....................... 208

0x48E – 0x4 93: R eser v ed ............................................................................................................................................... 208

Timestamp Unit 4 Input 2nd Sample Time Registers (0x494 – 0x49D) ........................................................................... 208

0x49E – 0x49F: Reserved ............................................................................................................................................... 208

Timestamp Unit 5 Status/Configuration/Control and Input 1st Sample Time Registers (0x4A0 – 0x4AD) ...................... 208

0x4AE – 0x4B3: Reserved .............................................................................................................................................. 208

Timestamp Unit 5 Input 2nd Sample Time Registers (0x4B4 – 0x4BD)........................................................................... 208

0x4BE – 0x 4BF: R eser v ed .............................................................................................................................................. 208

Timestamp Unit 6 Status/Configuration/Control and Input 1st Sample Time Registers (0x4C0 – 0x4CD) ..................... 208

0x4CE – 0x4D3: Reserved .............................................................................................................................................. 208

Timestamp Unit 6 Input 2nd Sample Time Registers (0x4D4 – 0x4DD) .......................................................................... 208

0x4DE – 0x4DF: Reserved .............................................................................................................................................. 208

Timestamp Unit 7 Status/Configuration/Control and Input 1st Sample Time Registers (0x4E0 – 0x4ED) ...................... 208

0x4EE – 0x4F3: Reserved ............................................................................................................................................... 209

Timestamp Unit 7 Input 2nd Sample Time Registers (0x4F4 – 0x4FD) ........................................................................... 209

0x4FE – 0x4FF: Reserved ............................................................................................................................................... 209

Timestamp Unit 8 Status/Configuration/Control and Input 1st Sample Time Registers (0x500 – 0x50D)....................... 209

0x50E – 0x5 13: R eser v ed ............................................................................................................................................... 209

Timestamp Unit 8 Input 2nd Sample Time Registers (0x514 – 0x51D) ........................................................................... 209

0x51E – 0x51F: Reserved ............................................................................................................................................... 209

Timestamp Unit 9 Status/Configuration/Control and Input 1st Sample Time Registers (0x520 – 0x52D)....................... 209

0x52E – 0x5 33: R eser v ed ............................................................................................................................................... 209

Timestamp Unit 9 Input 2nd Sample Time Registers (0x534 – 0x53D) ........................................................................... 209

0x53E – 0x53F: Reserved ............................................................................................................................................... 209

Timestamp Unit 10 Status/Configuration/Control and Input 1st Sample Time Registers (0x540 – 0x54D)..................... 209

0x54E – 0x5 53: R eser v ed ............................................................................................................................................... 209

Timestamp Unit 10 Input 2nd Sample Time Registers (0x554 – 0x55D) ......................................................................... 209

0x55E – 0x55F: Reserved ............................................................................................................................................... 210

Timestamp Unit 11 Status/Configuration/Control and Input 1st Sample Time Registers (0x560 – 0x56D)..................... 210

0x56E – 0x5 73: R eser v ed ............................................................................................................................................... 210

Timestamp Unit 11 Input 2nd Sample Time Registers (0x574 – 0x57D) ......................................................................... 210

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

13 Revision 1.0

0x57E – 0x57F: Reserved ............................................................................................................................................... 210

Timestamp Unit 12 Status/Configuration/Control and Input 1st Sample Time Registers (0x580 – 0x58D)..................... 210

0x58E – 0x5 93: R eser v ed ............................................................................................................................................... 210

Timestamp Unit 12 Input 2nd Sample Time Registers (0x594 – 0x59D) ......................................................................... 210

0x59E – 0x5A3: Reserved ............................................................................................................................................... 210

Timestamp Unit 12 Input 3rd Sample Time Registers (0x5A4 – 0x5AD) ......................................................................... 210

0x5AE – 0x5B3: Reserved .............................................................................................................................................. 210

Timestamp Unit 12 Input 4th Sample Time Registers (0x5B4 – 0x5BD) ......................................................................... 210

0x5BE – 0x 5C3: R eser v ed .............................................................................................................................................. 210

Timestamp Unit 12 Input 5th Sample Time Registers (0x5C4 – 0x5CD) ......................................................................... 210

0x5CE – 0x5D3: Reserved .............................................................................................................................................. 211

Timestamp Unit 12 Input 6th Sample Time Registers (0x5D4 – 0x5DD) ......................................................................... 211

0x5DE – 0x5E3: Reserv ed .............................................................................................................................................. 211

Timestamp Unit 12 Input 7th Sample Time Registers (0x5E4 – 0x5ED) ......................................................................... 211

0x5EE – 0x5F3: Reserved ............................................................................................................................................... 211

Timestamp Unit 12 Input 8th Sample Time Registers (0x5F4 – 0x5FD) .......................................................................... 211

0x5FE – 0x5FF: Reserved ............................................................................................................................................... 211

Internal I/O Registers Space Mapping for PTP 1588 Clock and Global Control (0x600 – 0x7FF) .................................... 212

PTP Clock Control Register (0x600 – 0x601): PTP_CLK_CTL ...................................................................................... 212

0x602 – 0x603: Reserved ................................................................................................................................................ 213

PTP Real Time Clock in Nanoseconds Low-Word Register (0x604 – 0x605): PTP_RTC_NSL .................................... 213

PTP Real Time Clock in Nanoseconds High-Word Register (0x606 – 0x607): PTP_RTC_NSH ................................... 213

PTP Real Time Clock in Seconds Low-Word Register (0x608 – 0x609): PTP_RTC_SL ............................................... 213

PTP Real Time Clock in Seconds High-Word Register (0x60A – 0x 60B): PT P_ RTC_SH ............................................. 213

PTP Real Time Clock in Phase Register (0x60C – 0x60D): PTP_RTC_PHASE ........................................................... 214

0x60E – 0x60F: Reserved ............................................................................................................................................... 214

PTP Rate in Su b -Nanoseconds Low-Word Register (0x610 – 0x611): PTP_SNS_RATE_L ......................................... 214

PTP Rate in Su b -Nanoseconds High-Word and Control Register (0x612 – 0x613): PTP_SNS_RATE_H .................... 215

PTP Temporary Adjustment Mode Duration in Low-Word Register (0x614 – 0x615): PTP_TEMP_ADJ_DURA_L ...... 215

PTP Temporary Adjustment Mode Duration in High-Word Register (0x616 – 0x617): PTP_TEMP_ADJ_DURA_H ..... 215

0x618 – 0x61F: Reserved ............................................................................................................................................... 215

PTP Message Configuration 1 Register (0x620 – 0x621): PTP_MSG_CFG_1 .............................................................. 216

PTP Message Configuration 2 Register (0x622 – 0x623): PTP_MSG_CFG_2 .............................................................. 217

PTP Domain and Version Register (0x624 – 0x6 25): PTP_DOMA IN_ VER ................................................................... 218

0x626 – 0x63F: Reserved ............................................................................................................................................... 218

PTP Port 1 Receive Latency Register (0x640 – 0x641): PTP_P1_RX_LATENCY ........................................................ 218

PTP Port 1 Transmit Latency Register (0x642 – 0x643): PTP_P1_TX_LATENCY ........................................................ 219

PTP Port 1 Asymmetry Correction Register (0x644 – 0x645): PTP_P1_ASYM_COR ................................................... 219

PTP Port 1 Link Delay Register (0x646 – 0x647): PTP_P1_LINK_DLY ......................................................................... 219

PTP Port 1 Egress Timestamp Low-Word Register for Pdelay_Req and Delay_Req (0x648 – 0x649):

P1_XDLY_REQ_TSL ...................................................................................................................................................... 219

PTP Port 1 Egress Timestamp High-Word Register for Pdelay_Req and Delay_Req (0x64A – 0x64B):

P1_XDLY_REQ_TSH ...................................................................................................................................................... 220

PTP Port 1 Egress Timestamp Low-Word Register for Sync (0x64C – 0x64D): P1_SYNC_TSL .................................. 220

PTP Port 1 Egress Timestamp High-Word Register for Sync (0x64E – 0x64F): P1_SYNC_TSH ................................. 220

PTP Port 1 Egress Timestamp Low-Word Register for Pdelay_Resp (0x650 – 0x651): P1_PDLY_RESP_TSL .......... 220

PTP Port 1 Egress Timestamp High-Word Register for Pdelay_Resp (0x652 – 0x653): P1_PDLY_RESP_TSH ......... 220

0x654 – 0x65F: Reserved ............................................................................................................................................... 220

PTP Port 2 Receive Latency Register (0x660 – 0x661): PTP_P2_RX_LATENCY ........................................................ 221

PTP Port 2 Transmit Latency Register (0x662 – 0x663): PTP_P2_TX_LATENCY ........................................................ 221

PTP Port 2 Asymmetry Correction Register (0x664 – 0x665): PTP_P2_ASYM_COR ................................................... 221

PTP Port 2 Link Delay Register (0x666 – 0x667): PTP_P2_LINK_DLY ......................................................................... 221

PTP Port 2 Egress Timestamp Low-Word Register for Pdelay_Req and Delay_Req (0x668 – 0x669):

P2_XDLY_REQ_TSL ...................................................................................................................................................... 221

PTP Port 2 Egress Timestamp High-Word Register for Pdelay_Req and Delay_Req (0x66A – 0x66B):

P2_XDLY_REQ_TSH ...................................................................................................................................................... 222

PTP Port 2 Egress Timestamp Low-Word Register for Sync (0x66C – 0x66D): P2_SYNC_TSL .................................. 222

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

14 Revision 1.0

PTP Port 2 Egress Timestamp High-Word Register for Sync (0x66E – 0x66F): P2_SYNC_TSH ................................. 222

PTP Port 2 Egress Timestamp Low-Word Register for Pdelay_Resp (0x670 – 0x671): P2_PDLY_RESP_TSL .......... 222

PTP Port 2 Egress Timestamp High-Word Register for Pdelay_Resp (0x672 – 0x673): P2_PDLY_RESP_TSH ......... 222

0x674 – 0x67F: Reserved ............................................................................................................................................... 222

GPIO Monitor Register (0x680 – 0x681): GPIO_MONITOR ........................................................................................... 223

GPIO Output Enable Register (0x682 – 0x683): GPIO_OEN ......................................................................................... 223

0x684 – 0x687: Reserved ................................................................................................................................................ 223

PTP Trigger Unit Interrupt Status Register (0x688 – 0x689): PTP_TRIG_IS ................................................................. 223

PTP Trigger Unit Interrupt Enable Register (0x68A – 0 x 68B): PT P_TRIG_IE ............................................................... 223

PTP Timestamp Unit Interrupt Status Register (0x68C – 0x68D): PTP_TS_IS .............................................................. 224

PTP Timestamp Unit Interrupt Enable Register (0x68E – 0x68F): PT P_T S_IE ............................................................. 225

0x690 – 0x733: Reserved ................................................................................................................................................ 225

DSP Control 1 Register (0x734 – 0x735): DSP_CNTRL_6 ............................................................................................ 225

0x736 – 0x747: Reserved ................................................................................................................................................ 225

Analog Control 1 Register (0x748 – 0x749): ANA_CNTRL_1 ......................................................................................... 226

0x74A – 0x74B: Reserved ............................................................................................................................................... 226

Analog Control 3 Register (0x74C – 0x74D): ANA_CNTRL_3 ....................................................................................... 226

0x74E – 0x7F F: Res er ved ............................................................................................................................................... 226

MII Management (MIIM) Registers...................................................................................................................................... 227

PHY1 (PHYAD = 0x1) and PHY2 (PHYAD = 0x2): Register 0 (REGAD = 0x0) -> MII Basic Control ............................ 228

PHY1 (PHYAD = 0x1) and PHY2 (PHYAD = 0x2): Register 1 (REGAD = 0x1) -> MII Basic Status .............................. 229

PHY1 (PHYAD = 0x1) and PHY2 (PHYAD = 0x2): Register 2 (REGAD = 0x2) -> PHYID High .................................... 230

PHY1 (PHYAD = 0x1) and PHY2 (PHYAD = 0x2): Register 3 (REGAD = 0x3) -> P HYI D Lo w ..................................... 230

PHY1 (PHYAD = 0x1) and PHY2 (PHYAD = 0x2): Reg. 4 (REGAD = 0x4) -> Auto-Negotiation Advertisement Ability 230

PHY1 (PHYAD = 0x1) and PHY2 (PHYAD = 0x2): Reg. 5 (REGAD = 0x5) -> Auto-Negotiation Link Partner Ability .... 231

PHY1 (PHYAD = 0x1) and PHY2 (PHYAD = 0x2): Reg. 29 (REGAD = 0x1D) -> LinkMD Control and Status .............. 232

PHY1 (PHYAD = 0x1) and PHY2 (PHYAD = 0x2): Reg. 31 (REGAD = 0x1F) -> P H Y Special Control and Sta tus ...... 232

Management Information Base (MIB) Counters ................................................................................................................. 233

Additional MIB Information .............................................................................................................................................. 235

Static MAC Address Table .................................................................................................................................................. 236

Static MAC Table Lookup Examples: .............................................................................................................................. 237

Dynamic MAC Address Table ............................................................................................................................................. 238

Dynamic MAC Address Lookup Example ....................................................................................................................... 238

VLAN Table ......................................................................................................................................................................... 239

VLAN Table Lookup Examples........................................................................................................................................ 239

Absolute Maximum Ratings ................................................................................................................................................ 240

Operating Ratings ............................................................................................................................................................... 240

Electrical Characteristics ..................................................................................................................................................... 240

Timing Specifications .......................................................................................................................................................... 244

MII Transmit Timing in MAC Mode .................................................................................................................................. 244

MII Receive Timing in MAC Mode ................................................................................................................................... 245

MII Receive Timing in PHY Mode.................................................................................................................................... 246

MII Transmit Timing in PHY Mode .................................................................................................................................. 247

Reduced MII (RMII) Timing ............................................................................................................................................. 248

MIIM (MDC/MDIO) Timing ............................................................................................................................................... 249

SPI Input and Output Timing ........................................................................................................................................... 250

Auto-Negotiation Timing .................................................................................................................................................. 251

Trigger Output Unit and Timestamp Input Unit Timing .................................................................................................... 252

Reset and Power Sequence Timing ................................................................................................................................ 254

Reset Circuit Guidelines ...................................................................................................................................................... 255

Reference Clock – Connection and Selection .................................................................................................................... 256

Selection of Reference Crystal............................................................................................................................................ 256

Selection of Isolation Transformers..................................................................................................................................... 257

Package Information and Recommended Landing Pattern ................................................................................................ 258

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

15 Revision 1.0

List of Figures

Figure 1. Typical Straight Cable Connection ........................................................................................................................ 30

Figure 2. Typical Crossover Cable Connection .................................................................................................................... 31

Figure 3. Auto-Nego tia ti on and Par a llel Op erat ion ............................................................................................................... 32

Figure 4. Near-End and Far-End Loopback .......................................................................................................................... 34

Figure 5. Destination Address Lookup Flow Chart in Stage One ......................................................................................... 36

Figure 6. Destination Address Resolution Flow Chart in Stage Two .................................................................................... 37

Figure 7. Tail Tag Frame Format .......................................................................................................................................... 41

Figure 8. 802.1p Priority Field Format .................................................................................................................................. 44

Figure 9. PTP System Clock Overview ................................................................................................................................. 49

Figure 10. Trigger Output Unit Organization and Associated Registers ............................................................................... 56

Figure 11. Timestamp Input Unit Organization and Associated Registers ........................................................................... 57

Figure 12. Trigger Unit Interrupts .......................................................................................................................................... 58

Figure 13. Timestamp Unit Interrupts ................................................................................................................................... 58

Figure 14. Complex Waveform Generation Using Cascade Mode ....................................................................................... 63

Figure 15. Recom mended Low-V olt age Po wer Conne c tion using an Extern al Lo w -Voltage Regulator .............................. 68

Figure 16. Rec om mended Lo w-Voltage Power Connection using the Internal Low-Voltage Regulator .............................. 69

Figure 17. Traffic Activity and EEE ....................................................................................................................................... 71

Figure 18. SPI Regis ter Read Operatio n − Low-Speed Mode .............................................................................................. 75

Figure 19. SPI Regis ter Read Operatio n − High-Speed Mode ............................................................................................. 75

Figure 20. SPI Register Write Operation Timing ................................................................................................................... 75

Figure 21. Interface and Register Mapping ........................................................................................................................... 80

Figure 22. MII Trans mit Timing in MAC Mode .................................................................................................................... 244

Figure 23. MII Receive Timing in MAC Mode ..................................................................................................................... 245

Figure 24. MII Receive Timing in PHY Mode ...................................................................................................................... 246

Figure 25. MII Trans mit Timing in PHY Mode ..................................................................................................................... 247

Figure 26. RMII Transmit Timing......................................................................................................................................... 248

Figure 27. RMII Receive Tim ing.......................................................................................................................................... 248

Figure 28. MIIM (MDC/MDIO) Timing ................................................................................................................................. 249

Figure 29. SPI Interface Data Input Timing ......................................................................................................................... 250

Figure 30. SPI Interface Data Output Timing ...................................................................................................................... 250

Figure 31. Auto-Negotiation Timing .................................................................................................................................... 251

Figure 32. Trigger Output Unit and Timestamp Input Unit Timing ...................................................................................... 252

Figure 33. Reset and Po we r Sequence T iming .................................................................................................................. 254

Figure 34. Simple Reset Circuit .......................................................................................................................................... 255

Figure 35. Recommended Reset Circuit for Interfacing with a CPU/FPGA Output ............................................................ 255

Figure 36. Input Reference Clock Connection Options ...................................................................................................... 256

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

16 Revision 1.0

List of Tables

Table 1. MDI/MDI-X Pin Definitions ...................................................................................................................................... 30

Table 2. Spanning Tree States ............................................................................................................................................. 40

Table 3. Tail Tag Rules ......................................................................................................................................................... 42

Table 4. FID + DA Lookup in VLAN Mode ............................................................................................................................ 43

Table 5. FID + SA Lookup in VLAN Mode ............................................................................................................................ 44

Table 6. GPIO Pin Reference ............................................................................................................................................... 54

Table 7. Trigger Output Units and Timestamp Input Units Summary ................................................................................... 55

Table 8. GPIO Registers Affecting Either All or Specific Units ............................................................................................. 55

Table 9. Device Clocks and Related Pins ............................................................................................................................. 66

Table 10. Voltage Options and Requirements ...................................................................................................................... 68

Table 11. Power Management and Internal Blocks .............................................................................................................. 70

Table 12. Available Interfaces ............................................................................................................................................... 73

Table 13. SPI Connection ..................................................................................................................................................... 73

Table 14. Register Access using the SPI Interface............................................................................................................... 74

Table 15. MII Management Interface Frame Format ............................................................................................................ 76

Table 16. MII Interface Signal and Pin Associations............................................................................................................. 77

Table 17. RMII Clock Settings ............................................................................................................................................... 78

Table 18. RMII Signal Descriptions ....................................................................................................................................... 78

Table 19. RMII PHY-to-MAC and MAC-to-MAC Signa l Connections ................................................................................... 79

Table 20. Mapping of Functional Areas within the Address Space ...................................................................................... 81

Table 21. Ingress or Egress Data Rate Limits .................................................................................................................... 148

Table 22. PHY Register Mapping using the MII Interface ................................................................................................... 227

Table 23. Format of Per-Port MIB Counters ....................................................................................................................... 233

Table 24. Port 1 MIB Counters − Indirect Memory Offset ................................................................................................... 234

Table 25. "All Ports Dropped Packet" MIB Counter Format ............................................................................................... 235

Table 26. "All Ports Dropped Packet" MIB Counters − Indirect Memory Offsets ................................................................ 235

Table 27. Static MAC Table Format (8 Entries) .................................................................................................................. 236

Table 28. Dynamic MAC Address Table Format (1024 Entries) ......................................................................................... 238

Table 29. VLAN Table Format (16 Entries) ......................................................................................................................... 239

Table 30. MII Transmit Timing Parameters in MAC Mode .................................................................................................. 244

Table 31. MII Receive Timing Parameters In MAC Mode .................................................................................................. 245

Table 32. MII Receive Timing Parameters IN PHY Mode .................................................................................................. 246

Table 33. MII Transmit Timing Parameters in PHY Mode .................................................................................................. 247

Table 34. RMII Timing Parameters ..................................................................................................................................... 248

Table 35. MDC/MDIO Timing Parameters .......................................................................................................................... 249

Table 36. SPI Timing Parameters ....................................................................................................................................... 250

Table 37. Auto-Negotiation Timing Parameters .................................................................................................................. 251

Table 38. Trigger Output Unit and Timestamp Input Unit Timing Parameters ................................................................... 253

Table 39. Reset and Power Sequence Timing Parameters ................................................................................................ 254

Table 40. Typical Reference Crystal Characteristics .......................................................................................................... 256

Table 41. Transformer Selection Criteria ............................................................................................................................ 257

Table 42. Qualified Single Port Magnetics .......................................................................................................................... 257

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

17 Revision 1.0

Acronyms

BIU Bus Interface Unit The host interface function that perform s code conversion , buffering,

and the like required for communications to and from a network.

BPDU Bridge Protocol Data Unit A packet containing ports, address es, etc . to make sure data being

passed through a bridged network arrives at its proper destination.

CMOS Complementary Metal Oxide

Semiconductor A common semiconductor manufacturing technique in which positive

and negative types of transistors are combined to form a current gate

that in turn forms an effective means of controlling electrical current

through a chip.

CRC Cyclic Redundancy Check A common technique for detecting data transmission errors. CRC for

Ethernet is 32 bits long.

CUT-THROUGH SWITCH A switch typically processes received packets by reading in the full

packet (storing), then processing the packet to determine where it

needs to go, then forwarding it. A cut-through switch simply reads in

the first bit of an incoming packet and forwards the packet. Cut-

through switches do not store the packet.

DA Destination Address The address to send packets.

EMI Electro-M agnetic Interference A naturally occurring phenomena when the electromagnetic field of

one device disrupts, impedes or degrades the electromagnetic field

of another device by coming into proximity with it. In computer

technology, computer devices are susceptible to EMI because

electromagnetic fields are a byproduct of passing electri city through

a wire. Data lines that have not been properly shielded are

susceptible to data corruption by EMI.

FCS Frame Check Sequence See CRC.

FID Frame or Filter ID Specifies the frame identifier. Alternately is the filter identi fier.

GPIO General Purpose Input/Output General Purpose Input/Output pins are signal pins that can be

controlled or monitored by hardware and software to perform specific

tasks.

IGMP Internet Group Management

Protocol The protocol defined by RFC 1112 for IP multicast transmissions.

IPG Inter-Packet Gap A time delay between successive data packets mandated by the

network standard for protocol reasons. In Ethernet, the medium has

to be "silent" (i.e., no data tr an sfer) f or a short per iod of time before a

node can consider the network idl e and start to transmit. IPG is used

to correct timing differences between a transmitter and receiver.

During the IPG, no data is transferred, and information in the gap can

be discarded or additions inserted without impact on data integrity.

ISI Inter-Symbol Interference The disruption of transmitted code caused by adjacent pulses

affecting or interfering with each other.

ISA Industry Standard Architecture A bus architecture used in the IBM PC/XT and PC/AT.

Jumbo Packet A packet larger than the standard Ethernet packet (1500 bytes).

Large packet size s allow for more effic ient use of bandw idth, lower

overhead, less processing, etc.

MAC Media Access Controller a functional block responsible for implementing the media access

control layer which is a sub layer of the data link layer.

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

18 Revision 1.0

Acronyms (Continued)

MDI Medium Dependent Interface An Ethernet port connection that allows network hubs or

switches to connect to other hubs or switches without a

null-modem, or crossover, cable. MDI provides the

standard interface to a particular media (copper or fiber)

and is therefore “media dependent”.

MDI-X Medium Dependent Interface Crossover An Ethernet port connection that allows networked end

stations (i.e., PCs or workstations) to connect to each

other using a null-modem, or crossover, cable. For 10/100

full-duplex networks, an end point (such as a computer)

and a switch are wired so that each transmitter connects

to the far end receiver. When connecting two computers

together, a cable that crosses the TX and RX is required

to do this. With auto MDI-X, the PHY senses the correct

TX and RX roles, eliminating any cable confusion.

MIB M anagement Inf or mat ion B ase The MIB comprises the management portion of network

devices. This can include things like monitoring traffic

levels and faults (statistical), and can also change

operating para met er s in netw or k nodes (stat ic forw arding

addresses).

MII Media Independent Interface The MII accesses PHY registers as defined in the IEEE

802.3 specific atio n.

NIC Network Interface Card An expansion board inserted into a computer to allow it to

be connected to a network. Most NICs are designed for a

particular type of network, protocol, and media, although

some can serve multiple networks.

NPVID Non-Port VLAN ID The port VLAN ID value is used as a VLAN reference.

NRZ Non-Return to Zero A type of signal data encoding whereby the signal does

not return to a zero state in between bits.

PHY A device or functional block which performs the physical

layer interface function in a network.

PLL Phase-Locked Loop An electronic circuit that controls an oscillator so that it

maintains a constant phase angle (i.e., lock) on the

frequency of an input, or reference, signal. A PLL ensures

that a communicat ion sig nal is locked on a specifi c

frequency and can also be used to generate, modulate,

and demodulate a signal and divide a frequency.

PTP Precision Time Protocol A protocol, IEEE 1588 as applied to this device, for

synchroniz ing the cloc ks of dev ices attache d to a specifi c

network.

SA Source Address The address from which information has been sent.

TDR Time Domain Reflectometry TDR is used to pinpoint flaws and problems in

underground and aerial wire, cabling, and fiber optics.

They send a signal down the conductor and measure the

time it takes for the signal -- or part of the signal -- to

return.

TSU Timestamp Input Unit The functional block which captures signals on the GPIO

pins and assigns a time to the specific event.

TOU Trigger Output Unit The functional block which generates user configured

waveforms on a specified GPIO pin at a specific trigger

time.

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

19 Revision 1.0

Acronyms (Continued)

UTP Unshielded Twisted Pair Commonly a cable containing 4 twisted pairs of wires. The

wires are twisted in such a manner as to cancel electrical

interference generated in each wire, therefore shielding is

not required.

VLAN Virtual Local Area Network A configuration of comput ers that acts as if all computers

are connected by the same physical network but which

may be located virtually anywhere.

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

20 Revision 1.0

Pin Configuration

64-Pin LQFP

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

21 Revision 1.0

Pin Description

Pin Number Pin Name Type Pin Function

1 RXM1 I/O Port 1 physical receive (MDI) or transmit (MDIX) signal (- differential).

2 RXP1 I/O Port 1 physical receive (MDI) or transmit (MDIX) signal (+ differential).

3 AGND GND Analog Ground.

4 TXM1 I/O Port 1 physical transmit (MDI) or receive (MDIX) signal (– differential).

5 TXP1 I/O Port 1 physical transmit (MDI) or receive (MDI X) signal (+ differential).

6 VDD_AL P This pin is used as an input for the Low Voltage analog power. Its source should have

appropriate filtering with a ferrite bead and capacitors.

7 ISET O Set physical transmits output current.

Pull-down this pin with a 6.49KΩ (1%) resistor to ground.

8 AGND GND Analog Ground.

9 VDD_A3.3 P 3.3V analog VDD input power supply (Must be well decoupled).

10 RXM2 I/O Port 2 physical receive (MDI) or transmit (MDIX) signal (- differential).

11 RXP2 I/O Port 2 physical receive (MDI) or transmit (MDIX) signal (+ differential).

12 AGND GND Analog Ground.

13 TXM2 I/O Port 2 physical transmit (MDI) or receive (MDIX) signal (– differential).

14 TXP2 I/O Port 2 physical transmit (MDI) or receive (MDIX) signal (+ differential).

15 FXSD2 I Fiber signal dete ct inpu t for port 2 in 100BASE-FX fiber mode. When in copper mode,

this input is unused and should be pulled to GND.

Note: This functio nal ity is avail able only on the KSZ8463FML/FRL devices.

16 VDD_COL P This pin is used as a second input for the low-voltage analog power. Its source sh ould

have appropriate filtering with a ferrite bead and capacitors .

17 PWRDN IPU

Full-Chip Power-Down.

Active Low (Low = Power-down; High or floating = Normal operation).

While this pin is asserted low, all I/O pins will be tri-stated. All registers will be set to

their default stat e. While this pin is asserted, power consumption will be minimal.

When the pin is de-asserted, power consumption will climb to nominal and the device

will be in the same state as having been reset by the reset pin (RSTN, pin 63).

Legend:

P = Power supply GND = Ground.

I/O = Bi-directional: I = Input, O = Output.

IPD = Input with internal pull-down (58K ±30%).

IPU = Input with internal pull-up (58K ±30%).

OPD = Output with internal pull-down (58K ±30%).

OPU = Output with internal pull-up (58K ±30%).

IPU/O = Input with internal pull-up (58K ±30%) during power-up/reset; output pin otherwise.

IPD/O = Input with internal pull-down (58K ±30%) during power-up/reset; output pin otherwise.

I/O (PD) = Bi-directi onal input/ out put with internal pull-down (58K ±30%).

I/O (PU) = Bi-directi onal input/ out put with internal pull-up (58K ±30%).

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

22 Revision 1.0

Pin Description (Continued)

Pin Number Pin Name Type Pin Function

18 X1 I 25MHz Crystal or Oscillator Clock Connection.

Pins (X1, X2) connect to a crystal. If an oscillator is used, X1 connects to a VDD_IO

voltage tolerant oscillator and X2 is a no connect. This clock requirement is ±50ppm.

The KSZ8463RL has the opti on to use REFCLK_I (50MHz) as its primary clock input

instead of X1 and X2. This is determined by the state of pin 41 (SPI_DO) at power-

up/reset time. See Strapping O ption s section for details. (Applies to the

KSZ8463RL/FRL devices only)

19 X2 O

20 DGND GND Digital Ground.

21 VDD_IO P 3.3V, 2.5V, or 1.8V digital VDD input power pin for IO logic and the internal low-

voltage regulator.

22 TX_EN IPD

(8463ML, 8463FML) – MII Mode:

Transmit Enable. Active high input indicates there is valid transmit data on TXD[3:0].

(8463RL, 8463FRL)

−

RMII Mode:

Transmit Enable. Active high indicates there is valid transmit data on TXD[1:0].

23 TXD3/

EN_REFCLKO IPD

(8463ML, 8463FML)

−

MII Mode:

Transmit data input bit[3]. This data is synchronous to the TX_CLK (2.5 MHz in 10BT

mode or 25MHz in 100BT mode)

(8463RL, 8463FRL)

−

RMII Mode:

EN_REFCLKO is used to enable REFCLK_O output on pin 32. If pulled up, the

REFCLK_O output is enabled. If pulled down to disable, the REFCLK_O output is

disabled.

24 TXD2/NC IPD

(8463ML, 8463FML)

−

MII Mode:

Transmit data input bit[2]. This data is synchronous to TX_CLK (2.5MHz in 10BT

mode or 25MHz in 100BT mode).

(8463RL, 8463FRL)

−

RMII Mode:

No connect. Is not used.

25 TXD1 IPD

(8463ML, 8463FML)

−

MII Mode:

Transmit data input bit[1]. This data is synchronous to TX_CLK (2.5MHz in 10BT

mode or 25MHz in 100BT mode).

(8463RL, 8463FRL)

−

RMII Mode:

Transmit data input bit[1]. This data is synchronous to REFCLK (50MHz).

26 TXD0 IPD

(8463ML, 8463FML)

−

MII Mode:

Transmit data input bit[0]. This data is synchronous to TX_CLK (2.5MHz in 10BT

mode or 25MHz in 100BT mode).

(8463RL, 8463FRL)

−

RMII Mode:

Transmit data input bit[0]. This data is synchronous to REFCLK (50MHz).

27 TX_CLK/

REFCLK_I I/O(PD)

(8463ML, 8463FML)

−

MII Mode:

Transmit cloc k. This is the out put clo ck in PHY MII mode and input clock in MAC MII

mode (2.5MHz in 10BT mode or 25MHz in 100BT mode).

(8463RL, 8463FRL)

−

RMII Mode:

Reference input clock (50MHz).

28 TX_ER/

MII_BP IPD

(8463ML, 8463FML)

−

MII Mode:

Transmit error input in MII MAC mode.

In MII PHY mode:

1 = Disable the MII PHY mode link and enable the bypass mode.

0 = Set MII PHY mode in normal operation.

(8463RL, 8463FRL)

−

RMII Mode:

No connect. Not used.

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

23 Revision 1.0

Pin Description (Continued)

Pin Number Pin Name Type Pin Function

29 DGND GND Digital Ground.

30 VDD_IO P 3.3V, 2.5V, or 1.8V digital VDD input power pin for IO logic and the internal low-

voltage regulator.

31 RX_DV IPU/O

(8463ML, 8463FML)

−

MII Mode:

Receive data valid, active high indicates that receive data on RXD[3:0] is valid.

(8463RL, 8463FRL)

−

RMII Mode:

Receive data valid, active high indicates that receive data on RXD[1:0] is valid.

Config Mode:

This pin is pulled up or down and its value is latched during the power-up / reset to

select either PHY MII mode or MAC MII mode. See Strapping Options section for

details.

32 RXD3/

REFCLK_O IPD/O

(8463ML, 8463FML)

−

MII Mode:

Receive data output bit[3]. This data is synchronous to RX_CLK (2.5MHz in 10BT

mode or 25MHz in 100BT mode)

(8463RL, 8463FRL)

−

RMII Mode:

REFCLK_O (50MHz) output when EN_REFCLKO (pin 23) is pulled-up. ( 16 ma. drive)

33 RXD2 IPU/O

(8463ML, 8463FML)

−

MII Mode:

Receive data output bit[2]. This data is synchronous to RX_CLK (2.5MHz in 10BT

mode or 25MHz in 100BT mode)

(8463RL, 8463FRL)

−

RMII Mode:

Not used.

Config Mode:

This pin is pulled up or down via an external resistor and its value is latched during

power-up/reset to select either high-speed SPI or low-speed SPI mode. See

Strapping Options sect ion f or detai ls.

34 RXD1 IPU/O

(8463ML, 8463FML)

−

MII Mode:

Receive data output bit[1]. This data is synchronous to RX_CLK (2.5MHz in 10BT

mode or 25MHz in 100BT mode)

(8463RL, 8463FRL)

−

RMII Mode:

Receive data output bit[1]. This data is synchronous to REFCLK (50MHz).

Config Mode:

This pin is pulled up or down via an external resistor and its value is latched during

power-up/reset to select serial bus mode. See Strapping Options section for details.

35 RXD0 IPD/O

(8463ML, 8463FML)

−

MII Mode:

Receive data output bit[0]. This data is synchronous to RX_CLK (2.5MHz in 10BT

mode or 25MHz in 100BT mode)

(8463RL, 8463FRL)

−

RMII Mode:

Receive data output bit[0]. This data is synchronous to REFCLK (50MHz).

Config Mode:

This pin is pulled up or down via an external resistor and its value is latched during

power-up/reset to select serial bus mode. See Strapping Options section for details.

36 CRS/

GPIO9_RLI I/O(PD)

(8463ML, 8463FML)

−

MII Mode:

Carrier Sense. This is an output signal in PHY MII mode and an input signal in MAC

MII mode.

(8463RL, 8463FRL)

−

RMII Mode:

This is GPIO9 while in RMII mode. (Refer to GPIO0 pin 48 descripti on).

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

24 Revision 1.0

Pin Description (Continued)

Pin Number Pin Name Type Pin Function

37 COL/

GPIO10_RLI I/O(PD)

(8463ML, 8463FML)

−

MII Mode:

Collision Detect. This is an output signal in PHY MII mode and an input signal in MAC

MII mode.

(8463RL, 8463FRL)

−

RMII Mode:

This is GPIO10 while in RMII Mode. (Refer to GPIO0 pin 48 des cript ion).

38 RX_CLK/

GPIO7_RLI I/O(PD)

(8463ML, 8463FML)

−

MII Mode:

Receive Clock. This is an output clock in PHY MII mode and an input clock in MAC

MII mode (2.5MHz in 10BT mode or 25MHz in 100BT mode).

(8463RL, 8463FRL)

−

RMII Mode:

This is GPIO7 while in RMII mode. (Refer to GPIO0 pin 48 d escr ipti on) .

39 DGND GND Digital Ground

40 VDD_L P This pin can be used in two ways; as the pin to input a low voltage to the device if the

internal low-voltage regulator is not used, or as the low-voltage output if the internal

low-voltage regulator is used.

41 SPI_DO IPU/O

Serial Data Output in SPI Slave Mode.

Config Mode:

This pin pull-up/pull-down value is latched to select clock input either 25MHz from

X1/X2 or 50MHz from REFCLK_I during power-up/reset. See Strapping Options

section for detail.

The REFCLK_I (50MHz) option is available only on the KSZ8463RL and

KSZ8463FRL. For the KSZ8463ML and KSZ8463FML, this pin must NOT be pulled

down at power-up/reset.

42 SPI_CSN IPD

Chip Select (active low) in SPI Slave Mode.

When SPI_CSN is high, the device is deselected and SPI_DO is held in a high-

impedance state. A high-to-low transition is used to initiate the SPI data transfer.

Note: An exter nal 4.7K pull-up is needed on this pin when it is in use.

43 INTRN OPU Interrupt Output.

This is an active low signal going to the host CPU to indicate an interrupt status bit is

set. This pin needs an external 4.7KΩ pull-up resistor.

44 SPI_SCLK/

MDC IPU Serial Clock input in SPI (SPI_SCLK) slave mode.

MIIM (MDC) mode is clock input.

45 SPI_DI/

MDIO I/O(PU) Serial Data Input in SPI (SPI_DI) Slave Mode.

Serial Data input/output in MIIM (MDIO) mode.

This pin needs an external 4.7KΩ pull-up resistor.

46 GPIO8 I/O(PD) This pin is GPIO8 (refer to GPIO0 pin 48 description).

47 GPIO11 I/O(PU) This pin is GPIO11 (refer to GPIO0 pin 48 description).

48 GPIO0 I/O(PU)

General Purpose Input/Output [0]

This pin can be used as an input or output pin for use by the IEEE 1588 event trigger

or timestamp capture units. It will be synchronized to the internal IEEE 1588 clock.

The host processor can also directly drive or read this GPIO pin.

49 GPIO1 I/O(PU) This pin is GPIO1 (refer to GPIO0 pin 48 description).

50 DGND GND Digital Ground.

51 VDD_L P This pin can be used in two ways; as the pin to input a low voltage to the device if the

internal low-voltage regulator is not used, or as the low-voltage output if the internal

low-voltage regulator is used.

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

25 Revision 1.0

Pin Description (Continued)

Pin Number Pin Name Type Pin Function

52 GPIO2 I/O(PU) This pin is GPIO2 (refer to GPIO0 pin 48 description).

53 GPIO3 I/O(PD) This pin is GPIO3 (refer to GPIO0 pin 48 description).

54 GPIO4 I/O(PD) This pin is GPIO4 (refer to GPIO0 pin 48 description).

55 GPIO5 I/O(PD) This pin is GPIO5 (refer to GPIO0 pin 48 description).

56 VDD_IO P 3.3V, 2.5V, or 1.8V digital VDD input power pin for IO logic and the internal low-

voltage regulator.

57 DGND GND Digital ground.

58 GPIO6 I/O(PU) This pin is GPIO6 (refer to GPIO0 pin 48 description).

59 P1LED1/

GPIO7_MLI I/O(PU)

Programmable LED Output to Indicate Port 1 and Port 2 Activity /Status.

The LED is ON (active) when output is low; the LED is OFF (inactive) when output is

high.

The port 1 LED pins outputs are determ ined by the table below if Reg. 0x06C –

0x06D, bits [14:12] are set to ‘000’. Otherwi s e, the port 1 LED pins are controlled via

the processor by setting Reg. 0x06C – 0x06D, bits [14:12] to a non-zero value.

The port 2 LED pins outputs are determ ined by the table below if Reg. 0x084 – 0x085,

bits [14:12] are set to ‘000’. Otherwise, the port 2 LED pins are controlled via the

processor by setting Reg. 0x084 – 0x085, bits [14:12] to a non-zero value.

Automatic port 1 and port 2 indicators are defined as follows:

Two bits [9:8] in SGCR7 Control Register

(Default) 01

10 11

P1LED1/P2LED1 Speed ACT Duplex Duplex

P1LED0/P2LED0 LINK/ACT LINK LINK/ACT LINK

LINK = LED ON ACT = LED Blink LINK/ACT = LED

On/Blink

Speed = LED ON (100BT) LED OFF (10BT)

Duplex = LED ON (Full duplex) LED OFF (Half duplex)

(8463ML, 8463FML)

−

MII Mode:

Functionality is controlled by IOMXSEL register D6h.

Pin 59 is P1LED1 (default) or GPIO7.

Pin 60 is P1LED0.

Pin 61 is P2LED1 (default) or GPIO9.

Pin 62 is P2LED0 (defa ult) or GPIO10.

(8463RL, 8463FRL)

−

RMII Mode:

Pin 59 is P1LED1.

Pin 60 is P1LED0.

Pin 61 is P2LED1.

Pin 62 is P2LED0.

60 P1LED0 I/O(PU)

61 P2LED1/

GPIO9_MLI I/O(PU)

62 P2LED0/

GPIO10_MLI I/O(PU)

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

26 Revision 1.0

Pin Description (Continued)

Pin Number Pin Name Type Pin Function

63 RSTN IPU Hardware reset input (active low). This reset input is required to be low for a minimum

of 10ms after supply voltages VDD_IO and 3.3V are stable.

64 FXSD1 I Fiber Signal Detect input for port 1 in 100BASE-FX fiber mode. When in copper

mode, this input is unused and should be pulled to GND.

Note: This functionality is available only on the KSZ8463FML/FRL devices.

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

27 Revision 1.0

Strapping Options

Pin Number Pin Name Type Pin Function

31 RX_DV IPU/O

PHY Mode or MAC Mode Select During Power-Up/Reset:

Pull-up (default) or No Connect = PHY MII mode.

Pull-down = MAC MII mode.

Note: There is no equivalent strapping pin for RMII mode.

33 RXD2 IPU/O High-Speed SPI or Low-Speed SPI Select During Power-Up/Reset:

Pull-up (default) or No Connect = High-speed SPI mode (up to 50MHz).

Pull-down = Low-speed SPI mode (up to 12.5MHz).

34 RXD1 IPU/O Serial Bus Mode Selection to Access the KSZ8463 Internal Registers During Power-

Up / Reset:

Note: SPI Slave Mode is required for access to all registers, and for implementing the

IEEE1588 proto co l.

[RXD1, RXD0] = [0, 0] — Reserved

[RXD1, RXD0] = [0, 1] — Reserved

[RXD1, RXD0] = [1, 0] — SPI Slave Mode (Default)

Interface Signals Type Description

SPI_DO (pin 41) O SPI data out

SPI_SCLK (pin 44) I SPI clock

SPI_DI (pin 45) I SPI data In

SPI_CSN (pin 42) I SPI chip select

[RXD1, RXD0] = [1, 1] – MIIM-Mode

In MIIM mode, the KSZ8463 provides access to its 16-bit MIIM registers through its MDC

(pin 44) and MDIO (pin 45).

35 RXD0 IPD/O

41 SPI_DO IPU/O

25MHz / 50MHz Input Clock Select for X1/X2 REFCLK_I On Power-Up / Reset:

Pull-up (default) or No Connect = 25MHz input from X1/X2. (Both RMII and MII mode)

Pull-down = 50MHz input from REFCLK_I (EN_REFCLK = “0”). (Only RMII mode) This

option is available only on the KSZ8463RL and KSZ8463FRL. For the KSZ8463ML and

KSZ8463FML, this pin must NOT be pulled down at power-up/reset time.

Legend:

IPU/O = Input with internal pull-up (58K ±30%) during power-up/reset; output pin otherwise.

IPD/O = Input with internal pull-down (58K ±30%) during power-up/reset; output pin otherwise.

All strap-in pins are latched at the end of the power-up or reset cycle. They are also latched when powering-up from a hardware or software power-down

or hardware reset state.

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Functional Description

The KSZ 8463 is a hi ghl y-integrated network ing de vice that i ncorpor ates a L ayer-2 s witch, t wo 1 0BT/10 0BT phys ical la yer

transceivers (PHYs) and associated MAC units, one MII/RMII interface on a third accessible MAC unit, and contains k ey

IEEE 1588 precision time protocol (PTP) features.

The KSZ8463 oper at es in a managed m ode. In m anag ed mode, a host pr oc ess or can acc ess and c ontr ol all PH Y, S witch ,

MAC, and IEEE 1588 related registers in the KSZ8463 via the high-speed SPI bus, or partial control via the MIIM

(MDC/MDIO) int erface.

Physical signal transmission and reception are enhanced through the use of analog circuits in the PHY that make the

design m ore eff icient and a llow for lo w pow er cons umption. Both p ower m anage m ent and energ y-eff icient Ethernet ( EEE)

are designed to save more power while the device is in idle state.

The KSZ8463 is fully compliant to IEEE802.3u standards.

Physical (PHY) Block

100BASE-TX Transmit

The 100BASE-TX transmit function performs parallel-to-serial conversion, 4B/5B coding, scrambling, NRZ-to-NRZI

conversi on, and MLT3 encoding and transmission.

The cir cuitry starts with a p arallel-to-serial convers ion, which c onverts the MII dat a from the MAC into a 1 25MH z seria l bit

stream . The data and control st ream is then converte d into 4B/5B codi ng, followed b y a scram bler. T he serialized data is

further converted from NRZ-to-NRZI format, and then transmitted in MLT3 current output. An external 6.49KΩ (1%)

resistor for the 1:1 transformer ratio sets the output current.

The output signal has a typical rise/fall time of 4ns and complies with the ANSI TP-PMD standard regarding amplitude

balance, o vers ho ot, a nd t i ming jitter. T he wave-s ha p ed 10 BA S E-T output dr i ver is als o i ncor porated into the 100 BA SE-TX

driver.

100BASE-TX Receive

The 100BASE-TX receiver function performs adaptive equalization, DC restoration, MLT3-to-NRZI conversion, data and

clock recovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding, and serial-to-parallel conversion.

The rec eiving s ide starts with the equal ization filter to c om pensate for inter -symbol interf erence (ISI) over th e twisted pair

cable. Since the amplitude loss and phase distortion is a function of the cable length, the equalizer has to adjust its

characteristics to optimize performance. In this design, the variable equalizer makes an initial estimation based on

compar isons of i ncoming s ignal str ength ag ainst som e known c able char acteristic s, and th en tunes itself f or optim ization.

This is an ongoing process and self-adjusts against environmental changes such as temperature variations.

Next, th e equ alized signal goes thr ough a DC r estorat ion an d data con versi on bloc k . The DC res tor ation c ircuit is use d to

compensate for the effect of baseline wander and to improve the dynamic range. The differential data conversion circuit

converts the MLT3 format back to NRZI. The slicing threshold is also adaptive.

The clock rec over y circ uit e xtr ac ts t he 125MH z cloc k from the edges of the N RZI sign al. T his rec overed c lock is then used

to convert the NRZI signal into the NRZ format. This signal is sent through the de-scrambler followed by the 4B/5B

decoder. Finally, the NRZ serial data is converted to an MII format and provided as the input data to the MAC.

Scrambler/De-Scramble r (100BASE-TX Only)

The purpos e of the scram bler is to s pread th e power s pectrum of the s ignal to reduce e lectrom agnetic inter ference ( EMI)

and baselin e wander.

Transmitted data is scrambled through the use of an 11-bit wide linear feedback shift register (LFSR). The scrambler

generates a 2047-bit non-repetitive s equence. T hen the receiver d e-scrambles the i ncoming data str eam using the s ame

sequence as at the transmitter.

PLL Clock Synthesizer (Recovery)

The device i ncorporates an interna l PLL clock synthesizer f or data recover y as well as for generating vario us clock s used

in the device. Refer to the Device Clocks section for details of this area.

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100BASE-FX Operation

Fiber Mode is available only on the KSZ8463FML and KSZ8463FRL devices.

100BASE-FX operation is similar to 100BASE-TX operation except that the scrambler/de-scrambler and MLT3

encoder/decoder are bypassed on transmission and reception. In this fiber mode, the auto-negotiation feature is bypassed

and auto MD I/MDIX is disa bled since there is no stan dard that s upports f iber aut o-negotiati on and aut o MDI /MDIX m ode.

The fiber port must be forced to either full-duplex or half-duplex mode.

All KSZ8463 devices are in copper mode (10BASE-T / 100BASE-TX) when reset or powered on. Fiber m ode is enabled

by clearing bits [7:6] in the CFGR register (0x0D8-0x0D9). Each port is individually configurable. Bit[13] in the

DSP_CNTRL_6 register (0x734-0x735) should also be cleared if either (or both) ports are set to fiber mode.

100BASE-FX Signal Detection

In 100BASE-FX operation, the fiber signal detect inputs FXSD1 and FXSD2 are usually connected to the signal detect

(SD) output pin of the fiber transceiver. When FXSD is low, no fiber signal is detected and a far-end fault (FEF) is

generated. When FXSD is high, the fiber signal is detected. To ensure proper operation, a resistive voltage divider is

recommended to adjust the fiber transceiver SD output voltage swing to match the FXSD pin’s input voltage threshold.

Alternat ively, the user m ay choose not t o implem ent th e FEF f eatur e. In t his cas e, the F XSD input pin is tied high to for ce

100BASE-FX mode.

In copper mode, and on the KSZ8463ML and KSZ8463RL, the FXSD pins are unused and should be pulled low.

100BASE-FX Far-End Fault

A Far-E nd Fault (FEF) oc curs when the signal detec tion is logica lly false on the receive side of the fiber tra nsceiver. T he

KSZ8463FML/FRL detects an FEF when its FXSD input is below the fiber signal detect threshold. When an FEF is

detected, the K SZ 8 463F ML /F RL s igna ls its f iber link par tner that a FEF has oc c urr ed b y sendin g 84 1’s followed b y a zero

in the i dle p eriod b etwe en f ram es. B y default, FEF is e nabled. FEF can be dis abled t hrough r egister s etting in P1C R4[12]

and P2CR4[1 2].

10BASE-T Transmit

The 10BASE-T driver is incorporated with the 100BASE-TX driver to allow for transmission using the same magnetics.

The y are inter nall y wave-shaped and pre-emphasi zed into ou tput s w ith typical 2.3 V amplitude. T he har monic contents ar e

at least 27dB below the fundamental freque ncy when driven b y an all-ones Manchester -encoded signal.

10BASE-T Receive

On the receive side, input buffers and level detecting squelch circuits are employed. A differential input receiver circuit and

a phase-locked loop (PLL) perform the decoding function.

The Manchester-encoded data stream is separated into clock signal and NRZ data. A squelch circuit rejects signals with

levels les s than 400m V or with short puls e widths to pr event noise at the RX P1 or RXM1 in put from falsel y trigger ing the

decoder. W hen the input exceeds the squelch limit, the PLL locks onto the incom ing signal and the KSZ8463 decodes a

data frame. The receiver clock is maintained active during idle periods in between data reception.

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MDI/MDI-X Auto Crossover

To eliminate the need for crossover cables between similar devices, the KSZ8463 supports HP-Auto MDI/MDI-X and

IEEE 802.3u standard MDI/MDI-X auto crossover. HP-Auto MDI/MDI-X is the default.

The auto-s ense f unc tio n de tec ts rem ot e trans mit and recei ve pa irs and c orrectl y as s igns the tr ansmit and receive pa irs f or

the KSZ8463. This feature is extremely useful when end users are unaware of cable types in addition to saving on an

additional uplink configurat ion connection. T he auto-crossover feature can be disabled through t he port control registers.

The IEEE 802.3u standard MDI and MDI-X definitions are as in T able 1:

Table 1. MDI/MDI-X Pin Definitions

MDI MDI-X

RJ45 Pins Signals RJ45 Pins Signals

1 TD+ 1 RD+

2 TD- 2 RD-

3 RD+ 3 TD+

6 RD- 6 TD-

Strai g h t Cable

A straight cable connects an MDI device to an MDI-X device or an MDI-X device to an MDI device. Figure 1 shows a

typical straight cable connection between a network interface card (NIC) and a switch, or hub (MDI-X).

Figure 1. Typical Straight Cable Connection

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Crossover Cab le

A cross over cable conn ects an MDI de vice to anoth er MDI device, or an MDI -X device to an other MDI -X devic e. Figure 2

shows a typical crossover cable connection between two chips or hubs (two MDI-X devices).

Figure 2. Typical Crossover Cable Connection

Auto-Negotiation

The KSZ8463 conforms to the auto-negotiation protocol as described by IEEE 802.3. It allows each port to operate at

either 10BASE-T or 100BASE-TX. Auto-negotiation allows unshielded twisted pair (UTP) link partners to select the best

common mode of operation. In auto-negotiation, the link partners advertise capabilities across the link to each other and

then compare their own capabilities with those they received from their link partners. The highest speed and duplex

setting that is common to the two link partners is selected as the mode of operation. Auto-negotiation is also used to

negotiate support for Energy Efficient Ethernet (EEE). Auto-negotiation is only supported on ports in copper mode, not

fiber mode.

The following list shows the speed and duplex operation mode from highest to lowest.

• Highest: 100BASE-TX, full-duplex

• High: 100BASE-TX, half-duplex

• Low: 10BASE-T, full-duplex

• Lowest: 10BASE-T, half-duplex

If auto-negotiation is not supported or the link partner to the KSZ8463 is forced to bypass auto-negotiation, the mode is

automat ically set b y obser ving the sign al at the rece iver . This is known as parallel m ode because while the trans mitter is

sending auto-negotiation advertisements, the receiver is listening for advertisements or a fixed signal protocol.

The link setup is shown in Figure 3.

Receive Pair Receive Pair

T r ansmit P air

10/ 100 E thernet

Media Dependent Int er face 10/ 100 E thernet

Media Dependent Int er face

Modular Connector ( RJ - 45)

HUB

(Repeater or S witch)

Modular Connector ( RJ - 45)

HUB

(Repeater or S witch)

Crossover

Cable

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Figure 3. Auto-Negotiation and Parallel Operation

LinkMD® Cable Diagnostics

The KSZ8463 LinkMD uses time domain reflectometry (TDR) to analyze the cabling plant for common cabling problems

such as open circuits, short circuits, and impedance mismatches.

LinkMD wor k s by sending a puls e of k nown am plitude and duratio n down the MD I and MDI -X pairs and t hen anal yzes the

shape of the reflected signal. Timing the pulse duration gives an indication of the distance to the cabling fault with a

maximum distance of 200m and an accuracy of ±2m. Internal circuitry displays the TDR information in a user-readable

digital format in register P1SCSLMD[8:0] or P2SCSLMD[8:0].

Note: Cable diagnostics are only valid for copper connections. Fiber-optic operation is not supported.

Access

LinkMD is initiated by accessing register P1SCSLMD (0x07C) or P2SCSLMD (0x094), the PHY special control/status &

LinkMD register.

Usage

Before init iating Link MD, the value 0x8 008 must be wr itten to the AN A_CNTRL_3 Reg ister (0x74C – 0x74D) . This needs

to be done once (after power-n reset), but does not need to be repeated for each initiation of LinkMD. Auto-MDIX must

also be disabled before using LinkMD. To disable Auto-MDIX, write a ‘1’ to P1CR4[10] or P2CR4[10] to enable manual

control o ver t he pair us ed t o tr ans mit the L inkMD pulse. T he s elf-cleari ng cabl e d iag nos tic test e nab le b it, P 1SCSLM D[12]

or P2SCSLMD[12], is set to ‘1’ to start the test on this pair.

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When bit P1SCSLMD[12] or P2SCSLMD[12] returns to ‘0’, the test is completed. The test result is returned in bits

P1SCSLMD[14:13] or P2SCSLMD[14:13] and the distance is returned in bits P1SCSLMD[8:0] or P2SCSLMD[8:0]. The

cable diagnostic test results are as follows:

• 00 = Valid test, normal condition\

• 01 = Valid test, open circuit in cable

• 10 = Valid test, short circuit in cable

• 11 = Invalid test, LinkMD® failed

If P1SCSLMD[14:13] or P2SCSLMD[14:13] is “11”, this indicates an invalid test. T his occurs when the KSZ8463 is unable

to shut do wn the l ink partner . In this instance, th e test is not run, as it is not poss ible for the KSZ8463 t o determine if the

detected signal is a reflection of the signal generated or a signal from another source.

Cable distance can be approximated by utilizing the following formula:

• P1SCSLMD[8:0] x 0.4m for port 1 cable distance

• P2SCSLMD[8:0] x 0.4m for port 2 cable distance

This c onstant (0.4m ) may be c alibrate d for diff erent cabling c ondit ions , includ ing cabl es with a veloc ity of propagatio n that

varies significantly from the norm.

On-Chip Termination Resistors

Using the KSZ8463 reduces board cost and simplifies board layout by using on-chip termination resistors for the RX/TX

differ ential pairs , e liminati ng the ne ed for exter nal ter mination res istors in co pper m ode. The in ternal ch ip term ination and

biasing provides significant power savings when compared with using external biasing and termination resistors.

Loopback Support

The KSZ8463 prov ides two loopback modes. O ne is near-end (rem ote) loopback to support rem ote diagnosi ng of failures

on line side, and the other is far-end loopback to support local diagnosing of failures through all blocks of the device. In

loopback mode, the speed of the PHY port will be set to 100BASE-TX full-duplex mode.

Far-End Loopback

Far-end loop back is conducted bet ween the KSZ8463’s t wo PHY ports. T he loopbac k path s tarts at the “originating” PH Y

port’s receive inputs (RXP/RXM), wraps around at the “loopback” PHY port’s PMD/PMA (Physical Media

Dependent/Physical Media Attachment) , and ends at the “Originating” PHY port’s transmit outputs (TXP/TXM).

Bit[8] of r egister s P1C R4 a nd P2CR4 is use d t o e nab l e f ar -end loopback for ports 1 a nd 2, r es p ecti ve l y. As an a lternativ e,

bit[14] of registers P1MBCR and P2MBCR can be used to enable far-end loopback. The far-end loopback path is

illustrated in the F igur e 4.

Near-End (Remote) L o o pback

Near-end (rem ote) loopback is conduc ted at either PH Y port 1 or PHY port 2 of the KSZ8463. T he loopb ack path starts at

the PHY port’s receive inputs (RXPx/RXMx), wraps around at the same PHY port’s PMD/PMA, and ends at the same

PHY port’s transmit outputs (TXPx/TXMx). Bit[1] of registers P1PHYCTRL and P2PHYCTRL is used to enable near-end

loopback f or ports 1 and 2, res pecti vely. As a n altern ativ e, bit[9] of regist ers P1SC SLMD and P 2SCSL MD c an be us ed to

enable near-end loopback. The near-end loopback paths for port 1 and port 2 are il lustr ate d in Figur e 4.

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Figure 4. Near-E nd and Far-End Loopback

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MAC (Media Access Controller) Block

MAC Operation

The KSZ8463 strictly abides by IEEE 802.3 standards to maximize compatibility. Additionally, there is an added MAC

filtering f unc tion t o f ilter unicast packets. The MAC f ilter ing f unc tion is us ef ul in ap plic a tio ns s uc h as VoI P wh ere r es tric ting

certain packets reduces congestion and thus improves performance.

Address Lookup

The interna l D ynamic MAC Addres s lo okup table stor e s MAC ad dr ess es and th eir as s ociated inf or mation. It conta ins a 1 K

entry unicast address learning table plus switching information.

The KSZ8463 is guaranteed to learn 1K addresses and distinguishes itself from hash-based lookup tables, which,

depending o n th e operating env ironment and proba bi lit ies, ma y not guarante e th e abs ol ute n umber of address es they can

learn.

Learning

The internal lookup engine updates the Dynamic MAC Address table with a new entry if the following conditions are met:

• The received packet's source address (SA) does not exist in the lookup table.

• The received packet has no rec ei ving er r ors , and t he pac ket size is of legal le ngt h.

The lookup engine inserts the qualified SA into the table, along with the port number and time stamp. If the table is full, the

oldest entry of the table is deleted to make room for the new entry.

Migration

The internal lookup engine also monitors whether a station has moved. If a station has moved, it updates the table

accordingly. Migration happens when the following conditions are met:

• The received packet's SA is in the table but the associated source port information is different.

• The received packet has no rec ei ving er r ors , and t he pac ket size is of leg al lengt h.

The lookup engine updates the existing record in the table with the new source port information.

Aging

The lookup engine updates the time stamp information of a record whenever the corresponding SA appears. The time

stam p is used in the aging pr ocess. If a rec ord is not updated for a per iod of time, the look up engine rem oves the record

from the table. The lookup engine constantly performs the aging process and continuously removes aging records. The

aging period is about 300 seconds (±75 seconds). This feature can be enabled or disabled through global register

SGCR1[10].

Forwarding

The KSZ84 63 forwards pack ets using the algor ithm that is depicted in the foll owing flowchar ts. Figure 5 s hows stag e one

of the forwarding algorithm where the search engine looks up the VLAN ID, static table, and dynamic table for the

destination address , and com es up with “port to f orward 1” (PTF1). PT F1 is then further modified b y spanning tree, IG MP

snooping, port m irror ing, and port VLAN pr oc esses to com e up with “por t-to-f orw ard 2” (PT F2) , as sho wn in Figure 6. T he

packet is sent to PTF2.

The KSZ8463 will not forward the following packets:

• Error packets: These include framing errors, frame check sequence (FCS) errors, alignment errors, and illegal size

packet errors.

• IEEE802.3x PAUSE frames: KSZ8463 intercepts these packets and performs full duplex flow control accordingly.

"Local" pac kets: Bas ed on des tination addr ess (DA) look up. If the dest ination port from the lookup ta ble mat ches the port

from which the packet originated, the packet is defined as "local."

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Figure 5. Destination Address Lookup Flow Chart in Stage One

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Figure 6. Destination Address Resolution Flow Chart in Stage Two

Inter-Packet Gap (IPG)

If a frame is successfully transmitted, then the minimum 96-bit time for IPG is measured between two consecutive

packets. If the current packet is experiencing collisions, the minimum 96-bit time for IPG is measured from carrier sense

(CRS) to the next transmit packet.

Back-Off Algorithm

The KSZ8463 implements the IEEE standard 802.3 binary exponential back-off algorithm in half-duplex mode. After 16

collisions, the packet is dropped.

Late Collision

If a transmit packet experiences collisions after 512 bit times of the transmission, the packet is dropped.

Legal Packet Size

The KSZ8463 discards packets less than 64 bytes and can be programmed to accept packet sizes up to 1536 bytes in

SGCR2[1]. The KSZ8463 can also be programmed for special applications to accept packet sizes up to 2000 bytes in

SGCR1[4].

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Flow Control

The KSZ8463 supports standard 802.3x flow control frames in both the transmit and receive directions.

In the receive direction, if a PAUSE control fram e is received on an y port, the KSZ8463 will not transmit the next norm al

frame on that port until the timer, specified in the PAUSE control frame, expires. If another PAUSE frame is received

before the current timer expires, the timer will then update with the new value in the second PAUSE frame. During this

period (while it is flow controlled), only flow control packets from the KSZ8463 are transmitted.

In the trans mit direction, th e KSZ8 463 h as inte llige nt a nd efficient wa ys to det ermine when to invoke flow contr ol and s en d

PAUSE frames. The flow control is based on availability of the system resources, including available buffers, available

transmit queues and available receive queues.

The KSZ8463 issues a PAUSE frame containing the maximum pause time defined in IEEE standard 802.3x. Once the

resource is freed up, the KSZ8463 sends out another flow control frame with zero pause time to turn off the flow control

(turn on transmission to the port). A hysteresis feature is provided to prevent the flow control mechanism from being

constant l y activat ed and de ac tivate d.

Half-Duplex Backpressure

A half-duplex backpressure option (non-IEEE 802.3 standards) is also provided. The activation and deactivation

conditions are the same as in full-duplex mode. If backpressure is required, the KSZ8463 sends preambles to defer the

other stations' transmission (carrier sense deference).

To avoid jabber and excessive deference (as defined in the 802.3 standard), after a certain time, the KSZ8463

discontinues the carrier sense and then raises it again quickly. This short silent time (no carrier sense) prevents other

stations from sending out pack ets thus keeping other stations in a carrier sens e deferred stat e. If the port h as packets to

send during a backpressure situation, the carrier sense type backpressure is interrupted and those packets are

transmitted instead. If there are no additional packets to send, carrier sense type backpressure is reactivated again until

chip resources free up. If a collision occurs, the binary exponential back-off algorithm is skipped and carrier sense is

generated immediately, thus reducing the chance of further collision and carrier sense is maintained to prevent packet

reception.

To ensure no packet loss in 10BASE-T or 100BASE-TX half-duplex mode, the user must enable the following bits:

• Aggressive back off (bit [8] in SGCR1)

• No excessive collision drop (bit [3] in SGCR2)

• Back pressure flow control enable (bit [11] in P1CR2/P2CR2)

Note: These bits are not set in default, since this is not the IEEE standard.

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Broadcast Storm Protection

The KSZ8463 has an intelligent option to protect the switch system from receiving too many broadcast packets. As the

broadcast p ack ets are for warded to all p orts ex cept th e sourc e port, an exc essiv e num ber of switch r esource s ( bandwidth

and available space in transmit queues) may be utilized. The KSZ8463 has the option to include “multicast packets” for

storm control. The broadcast storm rate parameters are programmed globally, and can be enabled or disabled on a per

port bas is in P1C R1[7] and P2CR1[ 7]. The ra te is b ased on a 6 7m s interval for 100BT an d a 670m s interv al for 10BT . At

the beginning of each interval, the counter is cleared to zero and the rate limit mechanism starts to count the number of

bytes during the interval. The rate definition is described in SGCR3[2:0][15:8]. The default setting is 0x63 (99 decimal).

This is equal to a rate of 1%, calculated as follows:

148,800 frames/sec × 67ms/interval × 1% = 99 frames/interval (approx.) = 0x63

Note: 148,800 frames/sec is based on 64-byte block of packets in 100BASE-T with 12 bytes of IPG and 8 bytes of

preamble between two packets.

Port Individual MAC Addr ess an d Source Port Filtering

The KSZ8463 can provide individual MAC addresses for port 1 and port 2. They can be set at registers 0x0B0h-0x0B5h

and 0x0B6-0x 0BB. R ece i ve d pac kets can be f ilt er ed (d r oppe d) if their so ur c e addr es s m atc hes t he M AC a ddr es s of port 1

or port 2. This f eature can be enabled b y setting bits [ 11:10] in the P1CR 1 or P2CR1 regis ters. One exam ple of usage is

that a packet will be dropped after it completes a full round trip within a ring network.

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Switch Block

Switching Engine

The KSZ8463 features a high-performance switching engine to move data to and from the MAC’s packet buffers. It

operates in store and forward mode, while the efficient switching mechanism reduces overall latency. The switching

engine has a 32 KByte inter nal f r ame buff er . This res our ce is s hared bet w een al l the por ts . T her e ar e a to ta l of 256 buf f er s

available. Each buffer is sized at 128 Bytes.

Spanning Tree Support

To suppor t s pann in g tree, the hos t port is t he d es ig nat ed port for the pr oc ess or . T he other ports (port 1 and port 2) can be

configured in one of the five spanning tree states via “transmit enable”, “receive enable” and “learning disable” register

settings in registers P1CR2 and P2CR2 for ports 1 and 2, respectively. Table 2 shows the setting and software actions

taken for each of the five spanning tree states.

Table 2. Spann ing Tree Stat es

Disable State Port Setting Software Action

The port should not

forward or receive any

packets. Learning is

disabled.

xmit enable = “0”, receive

enable = “0”, learning disable

= “1”

The processor should not send any packets to the port. The switch may

still send specific packets to the processor (packets that match some

entries in the “Static MAC Table” with “overriding bit” set) and the

processor should discard those packets. Address learning is disabled on

the port in this state.

Blocking State Port Setting Software Action

Only packets to the

processor are

forwarded.

xmit enable = “0”, receive

enable = “0”, learning disable

= “1”

The processor should not send any packets to the port(s) in this state. The

processor should program the “Static MAC Table” with the entries that it

needs to receive (for example, BPDU packets). The “overriding” bit should

also be set so that the switch will forward those specific packets to the

processor. Address learning is disabled on the port in this state.

Listening State Port Setting Software Action

Only packets to and

from the processor

are forwarded.

Learning is disabl ed.

xmit enable = “0”, receive

enable = “0”, learning disable

= “1”

The processor should program the “Static MAC Table” with the entries that

it needs to receive (for example, BPDU packets). The “overriding” bit

should be set so that the switch wi ll forward those specific packets to the

processor. The processor may send packets to the port(s) in this state.

Address learn ing is disabled on the port in this state.

Learning State Port Setting Software Action

Only packets to and

from the processor

are forwarded.

Learning is enabled.

xmit enable = “0”, receive

enable = “0”, learning disable

= “0”

The processor should program the “Static MAC Table” with the entries that

it needs to receive (for example, BPDU packets). The “overriding” bit

should be set so that the switch wil l forward those specific packets to the

processor. The processor may send packets to the port(s) in this state.

Address learn ing is enab led o n the port in this state.

Forwarding State Port Setting Software Action

Packets are forwarded

and received

normally. Learning is

enabled.

xmit enable = “1”, receive

enable = “1”, learning disable

= “0”

The processor programs the “Static MAC Table” with the entries that it

needs to receive (for example, BPDU packets). The “overriding” bit is set

so that the switch forwards those specific packets to the processor. The

processor can send packets to the port(s) in this state. Address learning is

enabled on the port in this state.

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Rapid Spanni n g Tree Support

There are three operational states assigned to each port for RSTP (Discarding, Learning, and Forwarding):

• Discarding ports do not participate in the active topology and do not learn MAC addresses.

• Discarding state: the state includes three states of the disable, blocking and listening of STP.

• Port setting: xmit enable = “0”, receive enable = “0”, learning disable = “1”.

Discarding State

Software ac ti on: T he host p roc es sor s hould not se nd a ny packets to the port. The switc h may still send specific packets to

the processor (packets that match some entries in the static table with “overriding bit” set) and the processor should

discard those packets. When the port’s learning capability (learning disable = ’1’) is disabled, setting bits [10:9] in the

SGCR8 register will rapidly flush the port related entries in the dynamic MAC table and static MAC table.

The processor is connected to port 3 via the host interface. Address learning is disabled on the port in this state.

Learning State

Ports in “learning states” learn MAC addresses, but do not forward user traffic.

Learning State: Only packets to and from the processor are forwarded. Learning is enabled.

Port setting for Learning State: transmit enable = “0”, receive enable = “0”, learning disable = “0”.

Software action: T he proc essor s hould progr am the s tatic MAC table with the entries that it needs to receive ( e.g., BPDU

packets). The “overriding” bit should be set so that the switch will forward those specific packets to the processor. The

process or may send packets to the por t(s ) in th is s tate ( s ee “Tail Tagging M ode” sub-sectio n f or detai ls). Addr es s learni ng

is enabled on the port in this state.

Ports in “forwarding states” fully participate in both data forwarding and MAC learning.

Forwarding State

Forwarding state: Packets are forwarded and received normally. Learning is enabled.

Port setting: transmit enable = “1”, receive enable = “1”, learning disable = “0”.

Software ac tion: The pr ocess or should pro gram the static MAC tabl e with the ent ries that it needs to receive (e.g., B PDU

packets). The “overriding” bit should be set so that the switch will forward those specific packets to the processor. The

process or may send packets to the port( s) in th is s tate ( s ee “ T ail T agging M ode” sub-sec tio n f or detai ls ). Addr es s learni ng

is enabled on the port in this state.

RSTP uses only one t ype of BPDU called RST P BPDU s. The y are similar t o STP conf iguration B PDUs with the exc eption

of a type field set to “version 2” for RSTP and “version 0” for STP, and a flag field carryi ng additional information.

Tail Tagging Mode

The tail t ag is only seen an d us ed by the port 3 host in ter f ac e, which s ho ul d be c o nnec te d to a pr oces s or. It is an ef f ec tive

way to retrieve th e i ngres s port i nf ormation for s pann in g tr ee pr otoc o l, IG M P snoopin g, an d ot her applicat ions. Bits [1:0] in

the o ne byte tail ta gging are us ed to indicate the sourc e/destination por t in port 3. Bits[3:2] are used f or priorit y setti ng of

the ingress frame in port 3. Other bits are not used. The tail tag feature is enabled by setting bit[8] in the SGCR8 register.

Figure 7. Tail Tag Frame Format

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Table 3. Tail Tag Rules

Ingress to Port 3 (Host -

KSZ8463)

Bit[1:0] Destination Port

00 Normal (Address Look up)

01 Port 1

10 Port 2

11 Port 1 and Port 2

Bit[3:2]

Frame Priority

00 Priority 0

01 Priority 1

10 Priority 2

11 Priority 3

Egress from Port 3 (KSZ8463 -> Host)

Bit[0] Source Port

0 Port 1

1 Port 2

IGMP Suppor t

For Internet Group Management Protocol (IGMP) support in Layer 2, the KSZ8463 provides two components:

“IGMP” Snoop ing

The KSZ8463 traps IGMP packets and forwards them only to the processor (host port). The IGMP packets are identified

as IP packets (either Ethernet IP packets, or IEEE 802.3 SNAP IP packets) with IP version = 0x4 and protocol version

number = 0x2.

“Multicast Address Insertion” in the Static MAC Table

Once the multicast address is programmed in the Static MAC Address Table, the multicast session is trimmed to the

subscribed ports, instead of broadcasting to all ports.

To enable IGMP support, set bit[14] to ‘1’ in the SGCR2 register. Also, Tail Tagging Mode needs to be enabled, so that

the process or knows which por t the IGMP pack et was rec eived on. T his is achieved b y sett ing bit [8] to ‘1’ in the SGCR8

IPv6 MLD Snooping

The KSZ846 3 traps IP v6 Mult icast Listen er Dis cov ery (MLD ) pack ets and f orward s them only to the proces sor ( host port) .

MLD snooping is controlled by SGCR2, bit[13] (MLD snooping enable) and SGCR2 bit[12] (MLD option).

Setting SGCR2 bit[13] causes the KSZ8463 to trap packets that meet all of the following conditions:

• IPv6 multicast packets

• Hop count limit = “1”

• IPv6 next header = “1”or “58” (or = “0” with hop-by-hop next header = “1” or “58”)

• If SGCR2[12] = “1”, IPv6 next header = “43”, “44”, “50”, “51”, or “60” (or = “0” with hop-by-hop next header = “43”, “44”,

“50”, “51”, or “60”)

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Port Mirroring Support

KSZ8463 supports “port mirroring” comprehensively as:

“Receive Only” Mirror-on-a-Port

All the packets received on the port are mirrored on the sniffer port. For example, 1 is programmed to be “receive sniff”

and the host port is programmed to be the “sniffer”. A packet received on port 1 is destined to port 2 after the internal

lookup. The KSZ8463 forwards the packet to both port 2 and the host port. The KSZ8463 can optionally even forward

“bad” received packets to the “sniffer port”.

“Transmi t Only” Mirror-on-a-Port

All the pack ets tr ansm itted on t he port ar e m irr ored on the snif fer port. F or exam ple, port 1 is progr amm ed to be “ transm it

sniff” and the host port is programmed to be the “sniffer port”. A packet received on port 2 is destined to port 1 after the

internal lookup. The KSZ8463 forwards the packet to both port 1 and the host port.

“Receive and Transmit” Mirror-on-Two-Ports

All the p ac k ets r eceived on port A and tr ans mitted on port B are mirrored o n th e s nif f er port. To turn on t he “AND ” f eatur e ,

set register SGCR2, bit 8 to “1”. For example, port 1 is programmed to be “receive sniff”, port 2 is programmed to be

“transm it sniff”, and the h ost port is pro grammed to be the “sniff er port”. A packet rec eived on port 1 is des tined to port 2

after the internal lookup. The KSZ8463 forwards the packet to both port 2 and the host port.

Multiple ports can be selected as “receive sniff” or “transmit sniff”. In addition, any port can be selected as the “sniffer

port”. All these per port features can be selected through registers P1CR2, P2CR2, and P3CR2 for ports 1, 2, and the

host port, respectively.

IEEE 802.1Q VLAN Support

The KSZ8463 supports 16 active VLANs out of the 4096 possible VLANs specified in the IEEE 802.1Q specification.

KSZ8463 provides a 16-entry VLAN table, which converts the 12-bits VLAN ID (VID) to the 4-bits Filter ID (FID) for

address lookup. If a non-tagged or null-VID-tagged packet is received, the ingres s port default VID is used for lookup. In

VLAN mode, the lookup process starts with VLAN table lookup to determine whether the VID is valid. If the VID is not

valid, the packet is dropped and its address is not learned. If the VID is valid, the FID is retrie ved for further lookup. The

FID + Desti nation Ad dres s (FID +DA) are us ed to deter m ine the dest ination port. T he FID + Source Address (FID+ SA) are

used for address learning (see Table 4 and T able 5).

Advanced VLAN features are also supported in the KSZ8463, such as “VLAN ingress filtering” and “discard non PVID”

defined in bits [14:13] of P1CR2, P2CR2 and P3CR2 registers. These features can be controlled on per port basis.

Table 4. FID + DA Lookup in VLAN Mode

DA found in

Static MAC

Table? Use FID Flag? FID Match? DA+FID found in

Dynamic MAC

Table? Action

No Don’t Care Don’t Care No Broadcast to the membership ports defi ned in t he VLAN

Table bits [18:16].

No Don’t Care Don’t Care Yes Send to the destination port defined in the Dynamic MAC

Address Table bits [53:52] .

Yes 0 Don’t Care Don’t care Send to the destination port(s) defined in the Static MAC

Address Table bits [50:48].

Yes 1 No No Broadcast to the membership ports defined in the VLAN

Table bits [18:16].

Yes 1 No Yes Send to the destination port defined in the Dyn amic MAC

Address Table bits [53:52] .

Yes 1 Yes Don’t Care Send to the destination port(s) defined in the Static MAC

Address Table bits [50:48].

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Table 5. FID + SA Lookup in VLAN Mode

FID+SA found in Dynamic MAC Address Table? Action

No Learn and add FID+SA to the Dynamic MAC Address Table.

Yes Update time stamp.

Quality-of-Service (QoS) Priority Support

The KSZ8463 pro vi des qualit y-of-s er vice (Q o S) for applications suc h as V oI P an d video c o nf er enc in g. T he KSZ8463 offer

1, 2, and 4 pri ority queues opti on per port. T his is controlled by bit[0] a nd b it[8 ] i n P1CR1, P2CR 1 an d P 3C R 1 r egist er s as

shown below:

• Bit[0], bit[8] = “00” egress port is a single output queue as default.

• Bit[0], bit[8] = “01” egress port can be split into two priority transmit queues. (Q0 and Q1)

• Bit[0], bit[8] = “10” egress port can be split into four priority transmit queues. (Q0, Q1, Q2 and Q3)

The f our priority trans mit queues is a new feat ure in t he KSZ8463. Qu eue 3 is t he highest pr iority queu e and Queue 0 is

the lowest pr iority queue. If a port's trans mit queue is not spl it, high priorit y and low priorit y pack ets have equa l priorit y in

the transmit queue.

There is an ad dit ion al option f or ever y port via bits[15, 7] in t he P1ITXQRCR1, P1TXQRCR2, P2TXQRCR1, P2T XQ RCR2,

P3TXQ RCR1, a nd P3T XQ RCR2 Register s to selec t either alw a ys to del iver h igh priorit y pack ets f irst or use weighte d fair

queuing for the four priority queues scale by 8:4:2:1.

Port-Based Priority

With port-based priority, each ingress port is individually classified as a specific priority level. All packets received at the

high-pr iorit y receiving port are mark ed as high priori ty and are s ent to the hig h-pri ority trans m it queue if the cor responding

transmit queue is split. bits[ 4:3] of r egister s P1C R1, P2 CR1, and P3CR 1 ar e used to enable port-bas ed pr ior it y for ports 1,

2, and the host port, respectively.

802.1p-Based Priority

For 802.1p-based priority, the KSZ8463 examines the ingress (incoming) packets to determine whether they are tagged. If

tagged, the 3-b it priorit y field in the V LAN tag is retrieved and us ed to look up the “pr iorit y mapping” va lue, as s pecified b y

the register SGCR6. The “priority mapping” value is programmable.

Figure 8 illustrates how the 802.1p priority field is embedded in the 802.1Q VLAN tag.

Figure 8. 802.1p Priority Field Format

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802.1p-based priority is enabled by bit[5] of registers P1CR1, P2CR1, and P3CR1 for ports 1, 2, and the host port,

respectively.

The KSZ8463 provides the option to insert or remove the priority tagged frame's header at each individual egress port.

This head er, consis ting of the 2 b ytes VLAN protoco l ID (VPID) and the 2 bytes t ag contr ol inform ation fie ld (TC I), is also

referred to as the 802.1Q VLAN tag.

Tag insertion is ena bl ed b y bit[ 2] of register s P1C R1, P2CR 1, and P3C R1 for ports 1, 2, and the host port, respectively. At

the egress port, untagged packets are tagged with the ingress port’s default tag. The default tags are programmed in

add tags to already tagged packets.

Tag removal is ena bl ed b y bit[ 1] of reg is ters P 1CR1, P 2CR1, and P3CR 1 for ports 1, 2, an d t he hos t port, re spec tively. At

the egress port, tagged packets will have their 802.1Q VLAN tags removed. The KSZ8463 will not modify untagged

packets.

The CRC is recalculated for both tag insertion and tag removal.

802.1p Priority Field Re-Mapping

This is a Qo S feat ure that allo ws the KSZ846 3 to s et the “ User Pri orit y Ceiling” at an y ingr ess port. If the ing ress pac k et’s

priority field has a higher priority value than the default tag’s priority field of the ingress port, the packet’s priority field is

replaced with the default tag’s priority field. The “User Priority Ceiling” is enabled by bit[3] of registers P1CR2, P2CR2,

and P3CR2 for ports 1, 2, and the host port, respectively.

DiffServ-Based Priority

DiffServ-based priority uses the ToS registers shown in the TOS Priority Control Registers. The ToS priority control

registers im plement a fully dec ode d, 12 8-bit d if f er entiat ed ser vices code point (D S CP) r egister to d eter mine pack et pr iorit y

from the 6-bit ToS f ield i n the IP header. W hen the m ost sig nificant 6 bits of the T oS field are full y decoded, the resul tant

of the 64 possibilities is compared with the corresponding bits in the DSCP register to determine priority.

Rate Limiting Support

The KSZ8463 supports hardware rate limiting from 64Kbps to 99Mbps (refer to Ingress or Egress Data Rate Limits),

independently on the “receive side” and on the “transmit side” as per port basis. For 10-BASET, a rate setting above

10Mbps means the rate is not limited. On the receive side, the data receive rate for each priority at each port can be

limited by setting up ingress rate control registers. On the transmit side, the data transmit rate for each priority queue at

each port can be limited by setting up egress rate control registers. The size of each frame has options to include

minimum interframe gap (IFG) or preamble byte, in addition to the data field (from packet DA to FCS).

For ingr ess rate lim iting, K SZ8463 prov ides opt ions to select ivel y choose fram es fr om all types, m ulticast, broadcast, and

flooded unicast frames. The KSZ8463 counts the data rate from those selected type of frames. Packets are dropped at

the ingress port when the data rate exceeds the specified rate limit.

For egress rate lim iting, the leak y buck et algorithm is applied to e ach output priorit y queue for s haping output traff ic. Inter

frame gap is stretched on a per frame base to generate smooth, non-burst egress traffic. The throughput of each output

priority queue is limited by the egress rate specified.

If any egress queue receives more traffic than the specified egress rate throughput, packets may be accumulated in the

output queue and packet mem ory. After the m emory of the queue or the port is used up, packet dropping or flow control

will be triggered. As a result of congestion, the actual egress rate may be dominated by flow control/dropping at the

ingress end, and may be therefore slightly less than the specified egress rate.

To reduce congestion, it is a good practice to make sure the egress bandwidth exceeds the ingress bandwidth.

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MAC Address Filtering Function

W hen a packet is rec eived, the des t in ati on M AC a ddr e s s is look ed up i n bot h t h e s tatic an d dynamic MAC addres s tables.

If the address is not found in either of these tables, then the destination MAC address is “unknown”. By default, an

unknown unicast packet is forwarded to all ports except the port at which it was received. An optional feature makes it

possible to specify the port or ports to which to forward unknown unicast packets. It is also possible to specify no ports,

meaning that unknown unicast packets will be discarded. This feature is enabled by setting bit[7] in SGCR7.

The unicast M AC addres s f ilterin g func tion is us eful in prevent ing the broadc ast of unicast pack ets that could degra de the

quality of this port in applications such as voice over Internet Protocol (VoIP).

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IEEE 1588 Precision Time Protocol (PTP) Block

The IEEE 1588 precision time protocol (PTP) provides a method for establishing synchronized time across nodes in an

Ethernet networking environment. The KSZ8463 implements V2 (2008) of the IEEE 1588 PTP specification.

The KSZ84 63 3-port s witch implem ents the IEEE 1588 PTP Vers ion 2 protoco l. Port 1 and port 2 can be pr ogramm ed as

either end-to-end (E2E) or peer-to-peer (P2P) transparent clock (TC) ports. In addition, port 3 can be programmed as

either slave or master ordinary clock (OC) port. Ingress timestamp capture, egress timestamp recording, correction field

update with residence time and link delay, delay turn-around time insertion, egress timestamp insertion, and checksum

update ar e supported. PT P f ram e filtering is im plem ented to en hance overa ll s ystem perf ormance. Del ay adj ustm ents are

implemented to fine tune the synchronization. Versatile event trigger outputs and timestamp capture inputs are

implemented to meet various real time application requirements through GPIO pins.

The key features of the KSZ8463 implementation are as follows:

• Both one-step and two-step transparent clock (TC) operations are supported

• Implementation of precision time clock per specification

− Upper 16 bits of the second clock not implemented due to practical values of time

• Both E2E and P2P TC are supported on port 1 and port 2

• Both slave and master OC are supported on port 3

• PTP multicast and unicast frame are supported

• Transports of PTP over IPv4/IPv6 UDP and IEEE 802.3/Ethernet are supported

• Both path delay request-response and peer delay mechanism are supported

• Precision time stamping of input signals on the GPIO pins

• Creation and delivery of clocks, pulses, or other unique serial bit streams on the GPIO pins with respect to the precision

time clock time.

IEEE 1588 defines two essential functions: The measurement of link and residence (switching) delays by using the

Delay_Req/Resp or Pdelay_Req/Resp messages, and the distribution of time information by using the Sync/Follow_Up

messages. The 1588 PTP event messages are periodically sent from the grandmaster in the network to all slave clock

devices. Link delays are measured by each slave node to all its link partners to compensate for the delay of PTP

messages sent through the network.

The 1588 PTP Announce messages are periodically sent from the grandmaster(s) in the network to all slave clock

devices. This information is used by each node to select a master clock using the “best master clock” algorithm.

1588 PTP (Version 2) defines two types of messages: event and general messages. These are summarized below and

are supported by the KSZ8463:

• Event Messages (an accurate timestamp is generated at egress and ingress):

• Sync (from master to slave)

• Delay_Req (from slave to master)

• Pdelay_Req (between link partners for peer delay measurement)

• Pdelay_Resp (between link partners for peer delay measurement)

General Messages:

• Follow_Up (from Master to Slave)

• Delay_Resp (from Master to Slave)

• Pdelay_Resp_Follow_Up (between link partners for peer delay measurement)

• Announce

• Management

• Signaling

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IEEE 1588 PTP Clock Types

The KSZ8463 supports the following clock types:

• Ordinary Clock (OC) is defined as a PTP clock with a single PTP port in a PTP domain. It may serve as a source of

time such as a master clock, or it may be a slave clock which synchronizes to another master clock.

• End-to-End Transparent Clock (E2E TC) is defined as a transparent clock that supports the use of the end-to-end delay

measurement mechanism between a slave clock and the master clock. In this method, the E2E TC intermediate

devices do not need to be synchronized to the master clock and the end slave node is directly synchronized to the

master clock. The E2E TC/SC slave intermediate devices can also be synchronized to the master clock. Note that the

transparent clock is not a real clock that can be viewed on an oscilloscope but rather it is a mechanism by which delay

are accounted for when transporting information across and through physical network nodes.

• Peer-to-Peer Transparent Clock (P2P TC for Version 2) is defined as a transparent clock, in addition to providing PTP

event transit time information. P2P TC also provides corrections for the propagation delay between nodes (link

partners) by using Pdelay_Req (Peer Delay Request) and Pdelay_Resp (Peer Delay Response). In this method, the

P2P TC intermediate devices can be synchronized to the master clock. A transparent clock (TC) is not part of the

master-slave hierarchy. Instead, it measures the resident time which is the time taken for a PTP message to traverse

the node. The P2P TC then provides this information to the clock receiving the PTP message. In addition, the P2P TC

measures and passes on the link delay of the receiving PTP message. Note that the transparent clock is not a real

clock that can be viewed on an oscilloscope but rather it is a mechanism by which delay are accounted for when

transporting information across and through physical network nodes.

• Master clock is defined as a clock which is used as the reference clock for the entire system. The KSZ8463 can

operate as a master clock if needed. However, the quality of the clock signal will be limited by the quality of the crystal

or oscillator used to clock the device.

Note: P2P and E2E TCs cannot be mixed on the same communication path.

IEEE 1588 PTP One-Step or Two-Step Clock Operatio n

The KSZ8463 supports either 1-step or 2-step clock operation.

• One-Step Clock Operation: A PTP message (Sync) exchange that provides time information using a single event

message which eliminates the need for a Follow_Up message to be sent. This one-step operation will eliminate the

need for software to read the timestamp and to send a Follow_Up message.

• Two-Step Clock Operation: A PTP messages (Sync/Follow_Up) that provides time information using the combination of

an event message and a subsequent general message. The Follow_Up message carries a precise estimate of the time

the sync message was placed on the PTP communication path by the sending node.

IEEE 1588 PTP Best Master Clock Selection

The IEEE 1588 PTP specification defines an algorithm based on the characteristics of the clocks and system topology

called b est master c lock (BMC) algorithm. BMC uses announc e messages to es tabl ish the s ynchronization hierar c hy. The

algorithm compares data from two clocks to determine the better clock. Each clock device continuously monitors the

announce messages issued by the current master and compares the dataset to itself. The software controls this process.

IEEE 1588 PTP System Time Clock

The system time clock (STC) in KSZ8463 is a readable or writable time source for all IEEE 1588 PTP-related functions

and conta ins three c ounter s: a 32-bit co unter for s econds, a 30-bit cou nter for nanoseconds and a 32-bit c ounter f or sub-

nanoseconds (units of 2-32ns). Figure 9 shows the PTP Clock.

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Figure 9. PTP System Clock Overview

The STC is clocked (incremented by 40ns or updated with sub ns carry info) every 40ns by a derivative of the 125MHz

derived c lock. T he 30-bit nanosec ond cou nter will be numeric ally increm ented by 40ns e ver y 40ns. There is another 3-bit

phase counter that is designed to indicate one of the five sub phases (0ns, 8ns, 16ns, 24ns, or 32ns) within the 40ns

period. This provides finer resolution for the various messages and timestamps. The overflow for the 30-bit nanosecond

counter is 0x3B9ACA00 (109) and the overflow for the 32-bit Sub-nanosecond counter is 0xFFFFFFFF.

The system time clock does not support the upper 16-bits of the seconds field as defined by the IEEE 1588 PTP Version 2

which s pecif ies a 4 8-bit s ec onds f ie ld. If the 32-bit sec onds c o unter o ver f lo ws, it will have to be han dled b y soft ware. Note

that an overflow of the seconds field only occurs every 136 years.

The sec onds value is kept trac k of in the PT P_RTC _SH and PT P_RTC_SL re gisters (0x608 – 0x 60B). T he nanoseco nds

value is kept track of in the PTP_RT C_NSH and PTP_RT C _NSL regis ters (0x604 – 0x607).

The PTP_RTC_PHASE clock register (0x60C – 0x60D) is initialized to zero whenever the local processor writes to the

PTP_RTC_NSL, PTP_RTC_NSH, PTP_RTC_SL, and PTP_RTC_SH registers.

During normal operation when the STC clock is keeping synchronized real time, and not while it is undergoing any

initialization manipulation by the processor to get it close to the real time, the PTP_RTC_PHASE clock register will be

reset to zer o at the begin ning of the curr ent 40ns STC cloc k update interval. It will start count ing at zero at the begin ning

of the 40ns p eriod and eve ry 8 ns it w ill b e incremented. T he information pr ovided b y the PT P_RTC_PHA SE re gister will

increase the accuracy of the various timestamps and STC clock readings.

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Updating the System Time Clock

The KSZ8463 provides four mechanisms for updating the system time clock:

• Directly set the time

• Step time adjustment

• Continuous time adjustment

• Temporary time adjustment

Directly Setting or Reading the Time

Directly setting the system time clock to a value is accomplished by setting a new time in the real time clock registers

(PTP_RTC_SH/L, PTP_RTC_NSH/L and PTP_RTC_PHASE) and then setting the load PTP 1588 clock bit

(PTP_LOAD_CLK).

Directly reading the system time clock is accomplished by setting the read PTP 1588 clock bit (PTP_READ_CLK). To

avoid lo wer bits overf lowin g dur ing read ing th e s ystem time c lock, a s napshot r egister techn ique is used. T he value in the

system tim e clock will be saved into a snapshot register by setting the PTP_READ_CLK bit in PTP_CLK_CTL, and then

subseque nt reads fr om PTP_RT C_S, PTP_RT C_NS, and PT P_RT C_PHAS E will return th e s ystem tim e c lock value. T he

CPU will add the PT P_RT C_PHASE value to PT P_RTC_S and PTP_RTC_NS to get the exact real time.

Step-Time Adjustment

The s ystem time clock can be incremented in steps if desired. T he nanosecond value (PTP_RT C_NSH/L) can be added

or subtracted when the PTP_STEP_ADJ_CLK bit is set. The value will be added to the system time clock if this action

occurs while the PTP_STEP_DIR bit = “1”. The value will be subtracted from the system time clock if this action occurs

while the PTP_STEP_DIR bit = “0”. The PTP_STEP_ADJ_CLK bit is self-clearing.

Continuous Ti m e Adjustment

The system can be set up to perform continuous time adjustment to the 1588 PTP clock. This is the mode that is

anticipated to be used the most. This mode is overseen by the local processor and provides a method of periodically

adjusting the count of the PTP clock to match the time of the master clock as best as possible. The rate registers

(PTP_SNS_RATE_H and PTP_SNS_RATE_L) (0x610 – 0x613) are used to provide a value by which the sub-

nanosecond Portion of the clock is adjusted on a periodic basis. While continuous adjustment mode

(PTP_CON TINU_ADJ_C LK = “1”) is s elected ever y 40ns the sub-nanosec ond valu e of the clock will be adjusted in eith er

a positive or negative direction as determined by the PTP_RATE_DIR bit. The value will be positively adjusted if

PTP_RATE_DIR = “0” or negatively adjusted if PTP_RATE_DIR = “1”. The rate adjustment allows for correction with

resolution of 2-32ns for every 40ns ref erence cloc k cycle, and it will be adde d to or subtr acted from the system tim e clock

on every reference clock cycle right after the write to PTP_SNC_RATE_L is done. To stop the continuous time

adjustment, one can either set the PTP_CONTINU_ADJ_CLK = “0” or the PTP_SNS_RATE_H/L value to zero.

Temporary T ime Adjustment

This m ode allows f or the co ntinuous tim e adjus tment to t ake plac e over a s pecifie d period of tim e only. The p eriod of tim e

is specif ied in the PTP_AD J_DURA_H/ L regist ers. This mode is enab led b y setting th e PT P_TEMP_ADJ _CLK bit to one.

Once the duration is reached, the increment or decrement will cease. When the tem porary time adjustment is done, the

internal duration counter register (PTP_ADJ_DURA_H/L) will stay at zero, which will disable the time adjustment. The

local proc essor needs to s et the PTP_TEMP_ ADJ_CLK to one aga in to start another temporar y tim e adjustment with the

reloaded value into the internal rate and duration registers. The PTP_ADJ_DURA_L register needs to be programmed

before PTP_ADJ_DURA_H register. The PTP_ADJ_DURA_L, PTP_ADJ_DURA_H and PTP_SNS_RATE_L registers

need to be programmed before the PTP_SNS_RATE_H register. The temporary time adjustment will start after the

PTP_T EMP_ADJ_C LK bit is set to one. T his bit is s elf-c leared when the adjustm ent is com pleted. Sof tware c an read this

bit to check whether the adjustment is still in progress.

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PTP Clock Initialization

During software initialization when the device is powering up, the PTP clock needs to be initialized in preparation for

synchron i zing to the mast er c lock. The s ugges te d ord er of tasks is to r es et the PT P 15 88 c l ock (RESET_PTP_CLK = “0”),

load the PTP 1588 clock (PTP_LOAD_CLK = “1”) with a value then enable the PTP 1588 clock (EN_PTP_CLK = “1”).

During the initial synchro nization attem pt, the system time clock m ay be a little f ar apart from the PTP master cloc k, so it

most likely will require a step-time adjustment to get it closer. After that, the continuous time adjustment method or

temporary time adjustment method may be the best options when the system time clock is close to being synchronized

with the master clock.

More details on the 1588 PTP system time clock controls and functions can be found in the register descriptions for

registers 0x600 to 0x617.

IEEE 1588 PTP Message Processing

The KSZ846 3 supports IEEE 1588 PTP time synchro nization when 1 588 PTP mode and m essage detection ar e enabled

in the PTP_MSG_CFG_1 register (0x620 – 0x621). Different operations will be applied to PTP packet processing based

on the setting of P2P or E2E in transparent clock mode for port 1 a nd port 2, master or slave in ordinar y clock mode f or

port 3 (host port), one-step or two-step clock mode, and if the domain checking is enabled. For the IPv4/UDP egress

packet, the checksum can be updated by either re-calculating the two-bytes or by setting it to zero. For the IPv6/UDP

egress packet, the checksum is always updated. All these 1588 PTP configuration bits are in the PTP_MSG_CFG_1/2

registers (0x620 – 0x623).

For a more detailed description of the 1588 PTP message processing control and function, please refer to the register

descriptions in the register map at locations 0x620 to 0x68F.

IEEE 1588 PTP Ingress Packet Processing

The KSZ8463 can detect all IEEE 802.3 Ethernet 1588 PTP packets, IPv4/UDP 1588 PTP pack ets, and IPv6/UDP 1588

PTP packets b y enabling th es e f eatur es in the PTP_MSG_C FG _1 re gis ter ( 0x 62 0 – 0x621). Up on detection of receiving a

1588 PTP packet, the device will capture the receive timestamp at the time when the start-of-frame delimiter (SFD) is

detected. Adjusting the receive timestamp with the receive latency or asymmetric delay is the responsibility of the

software. The hardware only takes these values into consideration when it updates the correction field in the PTP

message header. Likewise, the software needs to adjust the transmit timestamp with the transmit latency. Both the

ingress timestamp and the ingress port number will be embedded in the reserved fields of the 1588 PTP header. The

embedded information will be used by the host to designate the destination port in the response egress packet, identify

the direction of the master port, and to calculate the link delay and offset.

The 1588 PTP packet will be discarded if the 1588 PTP domain field does not match the domain number in the

PTP_DOMAIN_VER register (0x624 – 0x625) or if the 1588 PTP version number does not match version number (either 1

or 2) in the PT P_DOMA IN_VER r egister (0x62 4 – 0x6 25). Pack ets with a v ersion num ber of one will al wa ys be forward ed

to port 1 or port 2, and not to port 3.

The 1588 PT P pack ets that are not as socia ted with p ack et m essages in pairs (Pd ela y_ Req with P dela y_Res p, Sync w ith

Follow_U p, Delay_Re q with Dela y_Resp) can be filtered and not forwarded to port 3 if the c orresponding enable b its are

set in th e PTP_MSG_C FG_2 regis ter (0x0622 – 0x 623). The 1588 PTP versio n-1 packet will be forwarded without be ing

modified.

IEEE 1588 PTP Egress Packet Processing

The ingres s times tamp, the transport t ype of the 1 588 PTP pac ket, the pac ket type ( tagged or unta gged), an d the type of

correction fie ld update on the e gress s ide are in the fram e header and are acc essible f or m odification b y the egress l ogic

in local switch packet memory. The 1588 PTP packet will be put in the egress queue of highest priority. From the 1588

PTP frame header inside the switch packet memory, the egress logic will get the correction field update instruction. The

residence t ime, link dela y in the PT P_P1/2_LINK _DLY register s (0x646 – 0x 647 and 0x666 – 0x66 7) or turn-aroun d time

might be added to the correction field depending upon the type of 1588 PTP egress packet. The 1588 PTP packet

received from port 3 (host port) has the destination port information to forward as well as the timestamp information that

will be used for updating the correction field in one-step clock operation.

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This embedded infor mation ( in the res er ved fields of 1 588 PTP frame header) wi ll be zeroed o ut bef or e t he e gr es s pac ket

is sent out to conform to the 1588 PTP standard.

For one-step operation, the original timestamp will be inserted into the sync packet. The egress timestamp of the Sync

packet will be latched in the P1/2_SYNC_TS registers (0x64C – 0x64F and 0x66C – 0x66F), the egress timestamps of

Delay_Req, Pdelay_Req and Pdelay_Resp will be latched in the P1/2_XDLY_REQ_TS (0x648 – 0x64B and 0x668 –

0x6B) and P1/2_PDLY_RESP_TS registers (0x650 – 0x653 and 0x670 – 0x673). These latched egress timestamps will

generate an interrupt to the host CPU and set the interrupt status bits in the PTP_TS_IS register (0x68C – 0x68D) if the

interrupt enable is set in the PTP_TS_IE register (0x68E – 0x68F). These captured egress timestamps will be used by

the 1588 PTP software for link delay measurement, offset adjustment, and time calculation.

The transmit delay value from the port 1 or port 2 timestamp reference point to the network connection point in the

PTP_P1/2_TX_LATENCY registers (0x640 – 0x643) will be added to these value in the P1/2_SYNC_TS,

P1/2_XDLY_REQ_TS and P1/2_PDLY_RESP_TS registers to get the egress timestamp with reference point to the

network connection point. For transmit Delay_Req or Pdelay_Req packets, the value in the PTP_P1/2_ASYM_COR

registers (0x644 – 0x645 and 0x664 – 0x665) will be subtracted from the correction field.

IEEE 1588 PTP Event Triggering and Timestamping

An event trigger output signal can be generated when the target and activation time matches the IEEE1588 PTP system

clock tim e. Likewise, an e vent t imestam p input can be c aptur ed f rom an ext ernal event i npu t s ignal an d the corres pond ing

time on the IEEE1588 PTP system clock will be captured.

Up to 12 GPIO p ins c an b e c onf igured as e ith er out put s igna l whe n tri gger tar get t ime is matc hing IE EE 158 8 PT P system

clock time or monitoring input signal for external event timestamp. All event trigger outputs are generated by comparing

the system clock time with trigger target time continuously to make sure time synchronization is always on-going.

IEEE 1588 PTP Trigger Output

The KSZ846 3 supports up to 12 event tr igger units which can outp ut to an y one of the 12 GPIO pins b y setti ng bits[3:0] i n

TRIG[1:12]_CFG_1 registers. Multiple trigger units can be assigned to a single GPIO pin at the same time as logical

OR’ed function allowing generation of more complex waveforms. Also multiple trigger units can be cascaded (one Unit

only at any time) to drive a single GPIO pin to generate a long and repeatable bit sequence. Each trigger unit that is

cascaded can be any signal type (edge, pulse, periodic, register-bits, and clock output).

Each trigger unit can be programmed to generate one time rising or falling edge (toggle mode), a single positive or

negative pulse of programmable width, a periodic signal of programmable width, cycle time, bit-patterns to shift out from

TRIG[1:12]_CFG_[1:8] registers, and each trigger Unit can be programmed to generate interrupt of trigger output Unit

done and status in PTP_TRIG_IE/IS registers. For each trigger Unit, the host CPU programs the desired output

waveform, GPIO pins, target time in TRIG[1:12]_TGT_NS and TRIG[1:12]_TGT_S registers that the activity is to occur,

and enable the trigger output Unit in TRIG_EN register, then the trigger output signal will be generated on the GPIO pin

when the internal IEEE 1588 PTP system time matches the desired target time. The device can be programmed to

generate a pulse-per-second (PPS) output signal. The maximum trigger output signal frequency is up to 12.5MHz.

For a more detailed description of the 1588 PTP event trigger output control, configuration and function, please refer to

the registers description in the register map from 0x200 to 0x397 locations.

IEEE 1588 PTP Event Timestamp Input

External e vent in puts on the G PIO pins can be monito red and tim es tamped with the r esoluti on of 8ns . The e xter nal signa l

event can be monitored and detected as either rising edge, falling edge, positive pulse, or negative pulse by setting

bits[7:6] in TS[1:12]_CFG registers. Multiple timestamp units can be cascaded or chained together to associate with a

single GPIO pin to d etect a s eries of events. When event is de tected , the tim es tam p will be captur ed in thre e fields : 32-bit

second f ield in T S[1: 12]_S MPL1/2 _SH/L re gisters , 30 -bit nanoseco nd fie ld in TS[1:12] _SMP L1/2_N SH/L regis ters, an d 3-

bit phase field in TS[1:12]_SMPL1/2_SUB_NS registers. Second and nanosecond fields are updated every 25MHz clock

cycle. T he 3-bit phase field is updated ever y 125M Hz clock c ycl e and indica tes one of the f ive 8ns /125MHz clock cycles.

The bit [14] in TS[1:12]_SMPL1/2_NSH registers indicates the event timestamp input is either falling edge or rising edge.

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The KSZ8463 supports up to twelve timestamp input units which can input from any one of the twelve GPIO pins by

setting bits[11:8] in TS[1:12]_CFG registers. The enable bits [11:0] in TS_EN register are used to enable the timestamp

units. The last timestamp unit (Unit 12) can support up to eight timestamps for multiple event detection and up to four

pulses can be detected. The rest of the units (units 1 − 11) have two timestamps to support single edge or pulse

detection. Pulse width can be m easured by the time diff erence between cons ecutive timestam ps. W hen an input event is

detected, one of the bits [11:0] in TS_RDY register is asserted and will generate a timestamp interrupt if the PTP_T S_IE

bit is set. The host CPU is also expected to read the timestamp status in the TS[1:12]_STATUS registers to report the

number of detected event (either rising or falling edge) counts and overflow. In single mode, it can detect up to fifteen

events at an y single Unit. I n cas cade m ode, it can d et ect up to t wo events at units 1 − 11 or up t o e ight e vents at Unit 12,

and it can detect up to fifteen events for any unit as a tai l unit. Pulses or edges can be detected up to 25MHz.

For more details on 1588 PTP event timestamp input control, configuration and function, please refer to the register

descriptions for locations 0x400 to 0x5FD in the register map.

IEEE 1588 PTP Event Interrupts

All IEEE 1588 PTP event trigger and tim estamp interrupts are located in the PTP_T RIG_IE/PTP_TS_IE enable registers

and the PTP_TRIG_IS/PTP_TS_IS status registers. These interrupts are fully maskable via their respective enable bits

and shared with other interrupts that use the INTRN interrupt pin.

These twelve event trigger output status interrupts are logical OR’ed together and connected to bit[10] in the ISR register.

These twelve event trigger output enable interrupts are logical OR’ed together and connected to bit[10] in the IER register.

These twelve timestamp status interrupts are logical OR’ed together with the rest of bits in this register and the logical

OR’ed output is connected to bit[12] in the ISR register.

These twelve timestamp enable interrupts are logical OR’ed together with the rest of bits in this register and the logical

OR’ed output is connected to bit[12] in the IER register.

IEEE 1588 GPIO

The KSZ846 3 supports t welve GPIO pins that can be used f or general I/O or c an be configured to ut ilize the tim ing of the

IEEE 1588 protocol. These GPIO pins can be used for input event monitoring, outputting pulses, outputting clocks, or

outputting unique serial bit streams. The GPIO output pins can be co nfigured to initiate their output upon the occurrence

of a spec ific tim e which is bein g k ept by the onboar d prec ision tim e clock . Likewis e, the specif ic tim e of arrival of an input

event can be captured and recorded with respect to the precision time clock. Refer to the General Purpose and IEEE

1588 Input/Output (GPIO) section for details on the operation of the GPIO pins.

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General Purpose and IEEE 1588 Input/Output (GPIO)

Overview

The KSZ8463 devices incorporate a set of general purpose input/output (GPIO) pins that are configurable to meet the

needs of many applications. The input and output signals on the GPIO pins can be directly controlled via a local processor

or they can be set up to work closely with the IEEE 1588 protocol to create and/or monitor precisely tim ed signals which

are synchronous to the precision time clock. Some GPIO pins are dedicated, while others are dual function pins. Dual

function pins are managed by the IOMXSEL register. Table 6 provides a convenient summary of available GPIO

resources in the KSZ8463 devices.

Table 6. GPIO Pin Reference

KSZ8463ML and KSZ8463FML KSZ8463RL and KSZ8463FML

GPIO Pin # Function GPIO Pin # Function

GPIO_0 48 GPIO0 GPIO_0 48 GPIO0

GPIO_1 49 GPIO1 GPIO_1 49 GPIO1

GPIO_2 52 GPIO2 GPIO_2 52 GPIO2

GPIO_3 53 GPIO3 GPIO_3 53 GPIO3

GPIO_4 54 GPIO4 GPIO_4 54 GPIO4

GPIO_5 55 GPIO5 GPIO_5 55 GPIO5

GPIO_6 58 GPIO6 GPIO_6 58 GPIO6

GPIO_7 59 P1LED1/GPIO7_MLI GPIO_7 38 GPIO7_RLI

GPIO_8 46 GPIO8 GPIO_8 46 GPIO8

GPIO_9 61 P2LED1/GPIO9_MLI GPIO_9 36 GPIO9_RLI

GPIO_10 62 P2LED0/GPIO10_MLI GPIO_10 37 GPIO10_RLI

GPIO_11 47 GPIO11 GPIO_11 47 GPIO11

GPIO Pin Functionality Control

The GPIO_OEN register is used to configure each GPIO as an input or an output. Each GPIO pin has a set of registers

associated with it that are configured to determine its functionality, and any relationship it has with other GPIO pins or

registers. Each GPIO pin can be configured to output a binary signal state or a serial sequence of bits. Each GPIO pin can

output a single serial bit pattern or it can be programmed to continuously loop and output the pattern until stopped. The

duration of the hi gh a nd l o w perio ds within the s e que ntia l b it pa tterns c an be programmed to m eet the requirements of the

applicat ion. The output c an be triggere d to occur at an y time by the loca l processor writ ing to the corr ect register or it can

be triggered by the local IEEE precision timing protocol clock being equal to an exact time. The local processor can

interrogate an y GPIO pin at an y tim e or the val ue of th e IEEE precisio n tim e pr otocol clock c an be captur ed and r ecorde d

when the specified event occurs on any of the GPIO pins. The control and output of the GPIO pins can be cascaded to

create com plex digital outp ut seque nces and wavef orms . Last ly, the units can be program m ed to generate a n interru pt on

specific conditions.

The contr ol structure for the twelve GPIO p ins are organized in to two separat e units called t he trigger outp ut units (TOU)

and the timestamp input units (TSU). There are twelve T OUs and twelve TSUs which can be used with any of the GPIO

pins. Ther e are 32 contro l b ytes for each of the t wo units to c ontrol t he functiona lit y. The depth of c ontrol is sum marized in

Table 7.

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Table 7. Trigger Output Units and Timestamp Input Units Summary

Trigger Output Units Timestamp Input Units

32 Bytes of Parameters 32 Bytes of Parameters

Trigger Patterns: Detection:

Negative Edge, Positive Edge, Negative Pulse, Positive Pulse,

Negative Period, Positive Period, Register Output Shift Negative or Positive Edges

Negative or Positive Pulses

Pulse Width: Two Edge/One Pulse (Two Timestamps) Detection Capability

(Timestamp Units 10:0)

16-Bit Counter @ 8ns Each (524288 ns, maximum)

Cycle Width: Eight Edge/Four Pulse (Eight Timestamps) Detection

(Timestamp Unit 11)

32-Bit Counter @ 1ns Each (4.29 seconds, maximum)

Cycle Count: Cascadable to Detect Multiple Edges

16-Bit Counter (0 = Infinite Loop)

Total Cascade Mode Cycle Time:

32-Bit Counter @ 1ns Each

Shift Register:

16-Bits (only for register shift output mode)

Cascadable to Generate Complex Waveforms

GPIO Pin Contro l Register Layout

Most of the registers used to control the timestamp units and the trigger output units are duplicated for each GPIO pin.

There ar e a few regis ters which are assoc iated with all the ov erall functional ity of all the GPIO pins or only specific GPIO

pins. These are summarized in Table 8.

Table 8. GPIO Registers Affecting Either All or Specific Units

or Timestamping Units

Trigger Error Register − TRIG_ERR 0x200 − 0x201 All trigger output units.

Trigger Active Register − TRIG_ACTIVE 0x202 − 0x203 All trigger output units.

Trigger Done Register − TRIG_DONE 0x204 − 0x205 All trigger out p ut units.

Trigger Enable Register − TRIG_EN 0x206 − 0x207 All trigger outp ut units.

Trigger SW Reset Register − TRIG_SW_RST 0x208 − 0x209 All trigger output units.

Trigger Unit 12 Output PPS Pulse-Width Register −

TRIG12_PPS_WIDTH 0x20A − 0x20B Trigger output Unit 1, 12.

Timestamp Ready Register − TS_RDY 0x400 − 0x401 All trigger output units.

Timestamp Enable Register − TS_EN 0x402 − 0x403 All trigger output units.

Timestamp Software Reset Register − TS_SW_RST 0x404 − 0x405 All trigger output units.

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Figure 10. Trigger Output Unit Organization and Associated Registers

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Figure 11. Timestamp Input Unit Organization and Associated Registers

GPIO Trigger Output Unit and Timestamp Unit Interrupts

The trigger output units and the tim estamp units c an be programm ed to generate interrupts when s pecified events oc cur.

The interrupt control structure is shown in Figure 12 and Figure 13.

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Figure 12. Trigger Unit Interrupts

Figure 13. Timestamp Unit Interrupts

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Using the GPIO Pins with the Trigger Output Units

The twelve trigger output units (TOU) can be used to generate a variety of pulses, clocks, waveforms, and data streams at

user-selec table GP IO pins. T he TOUs will generate t he us er-s pecified o utput s tarting at a s pecif ic tim e with r espect to th e

IEEE 1588 precision time clock. This section provides some information on configuring the TOUs to generate specific

types of output. In the information below, the value “x” represents one of the twelve TOUs. Since this area of the device is

very flexible and powerful, please reference application note ANLAN203 for additional information on creating specific

types of waveforms and utilizing this feature.

When using a single TOU to control multiple GPIO pins, there are several details of functionality that must be taken into

account. When s witching b etween GPIO pi ns , the o ut put v alu e on th os e pins c an be af f ec ted. If a TOU changes the G PIO

pin level to a high value, writing to this units configuration register to change the addressed GPIO pin to a different one will

cause the hardware to dro p the level in th e previous G PIO pin and set t he new GPIO pi n to a high valu e. To prevent the

second GPIO pin from going high immediately, the TOU must be reset prior to programming in a different GPIO pin value.

Creating a Low-Going Pulse at a Specific Time

Specifying the Time

The desired trigger time will be set in TRIGx_TGT_NSH, TRIGx_TGT_NSL, TRIGx_TGT_SH, and TRIGx_TGT_SL

registers.

Specifying the Pulse Parameters

TRIGx_CFG_1[6:4] = “010” for negative pulse generation.

TRIG x_C FG _2[15:0] = Puls e width where each Unit is 8ns.

Associate this Trigger Output Unit to a Specific GPIO Pin

TRIGx_CFG_1[3:0] = Selects GPIO pin to use.

Set Up Interrupts if Needed

If it is desired to get notification that the trigger output event occurred set up the following registers.

TRIGx_CFG_1, bit[8] (Trigger Notify) = “1” is one requirement for enabling interrupt on done or error.

Set the corresponding trigger Unit interrupt enable bit in the PTP_TRIG_IE register.

Enabling the Trigger Output Unit

Set the corresponding trigger Unit enable bit in the TRIG_EN register.

Notes: Be awar e that for a lo w-goin g pulse in non-cascaded m ode (s ingle m ode), the output will be drive n by the unit to a

high level when the trigger unit is enabled. in cascade mode, the output will be driven by the unit to the high state 8ns

prior to the programmed trigger time.

Creating a High-Going Pulse at a Specific Time

Specifying the Time

The desired trigger time will be set in TRIGx_TGT_NSH, TRIGx_TGT_NSL, TRIGx_TGT_SH, and TRIGx_TGT_SL

registers.

Specifying the Pulse Parameters

TRIGx_CFG_1[6:4] = “011” for positive pulse generation.

TRIG x_C FG _2[15:0] = Pulse width where each Unit is 8ns.

Associate this Trigger Output Unit to a Specific GPIO Pin

TRIGx_CFG_1[3:0] = Selects GPIO pin to use.

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Set Up Interrupts if Needed

If it is desired to get notification that the trigger output event occurred set up the following registers.

TRIGx_CFG_1, bit[8] (Trigger Notify) = “1” is one requirement for enabling interrupt on done or error.

Set the corresponding trigger Unit interrupt enable bit in the PTP_TRIG_IE register.

Enabling the Trigger Output Unit

Set the corresponding trigger Unit enable bit in the TRIG_EN register.

Notes: Be aware that for a high-go ing pulse in non-cascaded m ode (sin gle m ode), the out put will be driven by the unit to

a low level when the trigger unit is enabled. in cascade mode, the output will be driven by the unit to the low state 8ns

prior to the programmed trigger time.

Creating a Free Running Clock Source

Specifying the Time

T ypically ther e is no n ee d to set up a des ir ed tri gg er ti me with respect to a f r ee r u nning c loc k . T her e are t wo wa ys that th e

free running clock can be started.

Set up a desired trigger time in the TRIGx_TGT_NSH, TRIGx_TGT_NSL, TRIGx_TGT_SH, and TRIGx_TGT_SL

registers.

After parameters have been set up, start the clock by setting the Trigger Now bit, bit[9], in the TRIGx_CFG_1 register.

Specifying the Clock Parameters

TRIGx_CFG_1[6:4] = “101” for generating a positive periodic signal.

High part of cycle defined by bits[15:0] in the TRIGx_CFG_2 register. Each Unit is 8 ns.

Cycle width defined by bits[15:0] in TRIGx_CFG_3 and TRIGx_CFG_4 registers. Each Unit is 1ns.

Continuous clock by setting TRIGx_CFG_5, bits[15:0] = “0”.

Associate this Trigger Output Unit to a Specific GPIO Pin

TRIGx_CFG_1[3:0] = Selects GPIO pin to use.

Set Up Interrupts if Needed

If it is desired to get notification that the trigger output event occurred set up the following registers.

TRIGx_CFG_1, bit[8] (Trigger Notify) = “1” is one requirement for enabling interrupt on done or error.

Set the corresponding trigger Unit interrupt enable bit in the PTP_TRIG_IE register.

Enabling the Trigger Output Unit

Set the corresponding trigger Unit enable bit in the TRIG_EN register.

Note: Because the fr equencies to be generat ed are b ased on t he per iod of the 125MHz c lock, t here are so me lim itations

that the user must be aware of. Certain frequencies can be created with unvarying duty cycles. However, other

frequencies may incur some variation in duty cycle. There are methods of utilizing the trigger Unit 2 clock edge output

select bit (bit[7] in of Reg. 0x248 – 0x249) and GPIO1 to control and minimize the variances.

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Creating Finite Length Period ic Bit Streams at a Specific Time

This example implies that a uniform clock will be generated for a specific number of clock cycles:

Specifying the Time

The desired trigger time will be set in TRIGx_TGT_NSH, TRIGx_TGT_NSL, TRIGx_TGT_SH, and TRIGx_TGT_SL

registers.

Specifying the Finite Length Periodic Bit Stream Parameters

TRIGx_CFG_1[6:4] = “101” for generating a positive periodic signal.

High part of cycle defined by bits[15:0] in the TRIGx_CFG_2 register. Each Unit is 8ns.

Cycle width defined by bits[15:0] in TRIGx_CFG_3 and TRIGx_CFG_4 registers. Each Unit is 1ns.

Finite length count established by setting TRIGx_CFG_5, bits[15:0] = “number of cycles”. Each Unit is one cycle.

Associate this Trigger Output Unit to a Specific GPIO Pin

TRIGx_CFG_1[3:0] = Selects GPIO pin to use.

Set Up Interrupts if Needed

If it is desired to get notification that the trigger output event occurred set up the following registers.

TRIGx_CFG_1, bit[8] (Trigger Notify) = “1” is one requirement for enabling interrupt on done or error.

Set the corresponding trigger Unit interrupt enable bit in the PTP_TRIG_IE register.

Enabling the Trigger Output Unit

Set the corresponding Trigger Unit Enable bit in the TRIG_EN register.

Creating Finite Length Non-Uniform Bit Streams at a Specific Time

Generation of a finite length non-uniform waveform which is a multiple of the bit pattern stored in the data storage register.

Specifying the Time

The desired trigger time will be set in TRIGx_TGT_NSH, TRIGx_TGT_NSL, TRIGx_TGT_SH, and TRIGx_TGT_SL

registers.

Specifying the Finite Length Non-Uniform Bit Stream Parameters

TRIGx_CFG_1[6:4] = “110” for generating signal based on contents of data register.

16-bit pattern stored in TRIGx_CFG_6 register.

Bit width defined by bits[15:0] in TRIGx_CFG_3 and TRIGx_CFG_4 registers. Each Unit is 1ns.

Bit length of finite pattern is established by shifting the data register “N” times. Set TRIGx_CFG_5, bits[15:0] = “N”.

Associate this Trigger Output Unit to a Specific GPIO Pin

TRIGx_CFG_1[3:0] = Selects GPIO pin to use.

Set up Interrupts if Needed

If it is desired to get notification that the trigger output event occurred set up the following registers.

TRIGx_CFG_1, bit[8] (Trigger Notify) = “1” is one requirement for enabling interrupt on done or error.

Set the corresponding trigger unit interrupt enable bit in the PTP_TRIG_IE register.

Enabling the Trigger Output Unit

Set the corresponding trigger unit enable bit in the TRI G _EN register.

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Creating Complex Waveforms at a Specific Time

Complex waveforms can be created by combining the various functions available in the trigger output units using a

method called “cascading”.

Figure 14 illustrat es the generation of a complex waveform onto one GPIO pin. Trigger output Unit 1 (TOU1) and trigger

output Unit 2 (TOU2) are cascaded to produce the complex waveform. Cascading allows multiple outputs to be

sequentia lly output onto one GPIO pin . In Figure 1 4, the waveform created b y T OU1 is output f irst on the selec ted GPIO

pin when t he indicated T OU1 trigger time is reached. The value in TRIG1_CFG 7 and TRIG1_CFG8 will be added to the

TOU1 trigger time and the next TOU1 output will occur at that time. Meanwhile, TOU2, will operate in the s ame manner;

outputting its waveform at TOU2 trigger time and then outputting again at a time TRIG2_CFG7 and TRIG2_CFG8 later.

The T R IGx _CF G7 and 8 register va lues must be the s ame f or all T O Us that ar e c as c aded tog eth er . The number of tim es

TOU1 and TOU2 will be output will depend on the cycle times programmed into the TRIG1_CFG6 and TRIG2_CFG6

registers. Care must be taken to select the correct values so as to avoid erroneous overlap.

Additional steps are required in setting up cascaded TOUs:

• Specif ying whic h trigger out put Unit in the cascade is the last Unit called the t ail unit.

• The last trigger output Unit in a cascade setup should have its tail bit set to “1”.

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Figure 14. Complex Waveform Generation Using Cascade Mode

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Using the GPIO Pins with the Timestamp Input Units

The twelve timestamp input units (TSU) can be set up to capture a variety of inputs at user selectable GPIO pins. The

current tim e of the precision time clock time will be captured and stored at the time in which the input event occurs. This

section provides some information on configuring the timestamp input units. In the information below, the value “x”

represents o ne of th e t we l ve timestamp input units. Since this area of the d ev ice i s ver y flex ibl e a nd po werf ul , it is advised

that you contac t your Micrel r epres entat iv e f or additi on al inf ormation on capturing spec if ic types of wavefor m s and utili zing

this feature.

Timestamp Value

Each tim estamp input nit c an ca pture two s am pled va lues of tim estam ps. T hes e firs t two val ues rem ain until r ead, e ven if

more events occur. The timestamp value captured consists of three parts which are latched in three registers.

Sample #1, the seconds value; TSx_SMPL1_SH, TSx_SMPL1_SL

Sample #1, the nanoseconds value; TSx_SMPL1_NSH, TSx_SMPL1_NSL

Sample #1, the sub-nanoseconds value; TSx_SMPL1_SUB_NS

Sample #2, the seconds value; TSx_SMPL2_SH, TSx_SMPL2_SL

Sample #2, the nanoseconds value; TSx_SMPL2_NSH, TSx_SMPL2_NSL

Sample #2, the sub-nanoseconds value; TSx_SMPL2_SUB_NS

The actual value in TSx_SMPL1/2_SUB_NS is a binary value of 0 through 4 which indicates 0ns, 8ns, 16ns, 24ns, or

32ns. Note t h at the proc es s or needs to add t his value t o t he sec on ds and nan os econds v al ue to g et th e c lose st tr u e va lue

of the timestamp event.

Number of Timestamps Available

Each timestamp input unit can capture two events or two timestamps values. Note that the exception to this is TSU12.

TSU12 can c apture eight events and thus has eight sam ple time regis ters (SMPL1 thru SMP L8) allowing fo r more robust

timing acquisition in one TSU. Note that the amount of samples for any given GPIO pin can be increased by cascading

time stamp unit. W hen TSUs are cascaded, the incoming events are routed to a sequentially established order of TSUs

for c apture. F or ex ample, you c an c asc ade TSU12, an d TSU 1-4 to be ab le to c a ptur e t we lv e t imestam ps off of one G PIO

pin. Cascading is set up in the TSx_CFG registers.

Events that can be Captured

The timestamp input units can capture rising edges and falling edges. In this case, the timestamp of the event will be

captured in the Sam ple #1 timestamp registers. A pulse can be capt ured if rising edge detection is combined with f alling

edge detection. In this case, one edge will be captured in the Sample #1 timestamp registers and the other edge will be

captured in the Sample #2 timestamp registers. This functionality is programmed in the TSx_CFG register for each

timestamp unit.

Timestamping an inc oming low-going edge

Specifying the Edge Parameters

TSx_CFG bit[6] = “1”

Associate this Timestamp Unit to a Specific GPIO Pin

TSx_CFG bits[11:8] = Selected GPIO Pin #

Set Up Interrupts if Needed

Set the corresponding timestamp unit interrupt enable bit in the PTP_TS_IE register.

Enabling the Timestamp Unit

Set the corresponding timestamp unit enable bit in the TS_EN register.

Timestamping an inc oming high-go ing edge

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Specifying the Edge Parameters

TSx_CFG bit[7] = “1”

Associate this Timestamp Unit to a Specific GPIO Pin

TSx_CFG bits[11:8] = Selected GPIO Pin #

Set Up Interrupts if Needed

Set the corresponding timestamp unit interrupt enable bit in the PTP_TS_IE register.

Enabling the Timestamp Unit

Set the corresponding timestamp unit enable bit in the TS_EN register.

Timestamping an incoming low-going pulse or high-going pulse

Specifying the Edge Parameters

TSx_CFG bit[7] = “1”

TSx_CFG bit[6] = “1”

Associate this Timestamp Unit to a Specific GPIO Pin

TSx_CFG bits[11:8] = Selected GPIO Pin #

Set Up Interrupts if Needed

Set the corresponding timestamp unit interrupt enable bit in the PTP_TS_IE register.

Enabling the Timestamp Unit

Set the corresponding timestamp unit enable bit in the TS_EN register.

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Device Clocks

A 25MHz clock source on X1/X2 is required for MII operation. The RMII 50MHz clock can either be derived from the

25MHz X1/ X2 refer ence, or is received from an external source. If an ext ernal 50 MHz clock is used f or RMII, the n a loca l

25MHz crystal or clock oscillator is not required. There are a number of pins with clock related functions on this device.

Table 9 sum marizes those pins and the ar ea of usage and if they are related to 25MHz, 50MHz, RMII, or MII clocking.

Table 9. Device Clocks and Related Pins

Clock Signal Name Pin # Usage Strapping Option Information

X1, X2 18, 19

The X1 and X2 pins are used to input a clock

which is used to clock all of the circuits within

the device.

MII – Clocking Choices

- 25MHz crystal connected between X1, X2

- 25MHz oscillator connected to pin X1 only.

X2 shall be unconnected.

RMII – Clocking Choices

- Either connection specified above for X1 and

X2 with other control bits and pins configured

as specified in Table 17 to produce the

required 50MHz output on REFCLK_O .

REFCLK_O externally connected to

REFCLK_I.

- 50MHz supplied on REFCLK_I pin from

external source. X1 and X2 unconnected.

Other control bits and pins configured as

spe c ified in Table 17.

Refer also to X1, X2 pin descriptions.

The SPI_DO pin (pin 41) is used to

select if a 25MHz cloc k on the X1

and X2 pins or a 50MH z clock on

the REFCLK_I pin will be used as

the source of all RMII clocking.

Other control bits and control pins

are used to determine other

attributes of the RMII/MII clocking

scheme.

Refer to Table 17 for more

information on the control bits and

pins.

Refer to the Strapping Options

section.

TX_CLK/REFCLK_I 27 These four pins are used for the clocking and

configuration of the MII and RMII interfaces.

MII

- 25MHz clocks are output on TX_CLK and

RX_CLK.

RMII

- A 50MHz clock must be received on

REFCLK_I. This comes either from an

external source or via external connection

from REFCLK_O.

Refer to Table 17 for details on the usage of

these signal pins.

TXD3/EN_REFCLK_O 23

RXD3/REFCLK_O 32

RX_CLK/GPIO7_RLI 38

SPI_SCLK/MDC 44 This pin is the clock for the SPI interface.

RXD2 33 This pin determines the clocking range of the

SPI clock. Refer to the Strapping Options

section.

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Note that the c lock tree power -do wn control regist er ( 0x038 – 0x03 9): CTPDC is used to po wer do wn the c locks in various

areas of the device. There are no other internal register bits which control the clock generation or usage in the device.

GPIO and IEEE 1588-Related Clocking

The GPIO and IEEE 1588-related c ircuits bot h utili ze the 25MH z clock and t he derived 1 25MH z clock . The tolera nce and

accurac y of the 25 MHz clo ck s ource will af fect the IEEE 1588 j itter and off set in a s ystem utili zing m ultiple slave de vices .

Therefore, the 25MHz source should be chosen with care towards the performance of the application in mind. Using an

oscillator will gener a ll y provide bett er results.

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Power

The KSZ8463 device requires a single 3.3V supply to operate. An internal low-voltage LDO provides the necessary low

voltage (n om inal ~1.3V) to power the an alog and d igit al logic cores . T he var ious I/O’s c an be oper ated at 1. 8V, 2.5 V, an d

3.3V. T able 10 illustrates the various voltage options and requirements of the device.

Table 10. Voltage Options and Requirements

Power Signal Name Device Pin Requirement

VDD_A3.3 9 3.3V input power to the analog blocks in the device.

VDD_IO 21, 30, 56 Choice of 1.8V or 2.5V or 3.3V for the I/O circuits. These input power pins power

the I/O circuitry of the devic e. T his voltag e is also used as the input to the internal

low-voltage regulator.

VDD_AL 6 Filtered low-voltage analog input voltage. This is where the filtered low voltage is

fed back into the device to power the analog block.

VDD_COL 16 Filtered low-voltage AD input voltage. This pin feeds the low voltage to the digital

circuits within the analog block.

VDD_L 40, 51

Output of internal low-voltage LDO regulator. This voltage is available on these pins

to allow connection to external capacitors and ferrite beads for filtering and power

integrity. These pins must be externally connected to pins 6 and 16.

If the internal LDO regulator is turned off, these pins become power inputs.

AGND 3, 8, 12 Analog Ground.

DGND 20, 29, 39, 50, 57 Digital Ground.

The preferred method of configuring the related low-voltage power pins when using an external low-voltage regulator is

illustrated in Figure 15. The num ber of capacitors, values of capacitors, and exact placem ent of components will depend

upon the specific design.

Figure 15. Recommended L o w-Voltage Power Connection using an External Low-Voltage Regulator

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Interna l Low Voltage LDO Regulator

The KSZ8463 reduces board cost and simplifies board layout by integrating a low noise internal low-voltage LDO

regulator to supply the nominal ~1.3V core power voltage for a single 3.3V power supply solution. If it is desired to take

advantage of an external low-voltage supply that is available, the internal low-voltage regulator can be disabled to save

power. The LDO_Off bit, bit[7] in Register 0x748 is used to enable or disable the internal low-voltage regulator. The

default sta te of the LDO _Off bit is “0” whic h enab les the int erna l low-v oltage r egul ator. T urning of f the interna l low-voltage

regulator will require software to write a “1” to that control bit. During the time from power up to setting this bit, both the

external voltage supply and the internal regulator will be supplying power. Note that it is not necessary to turn off the

internal l ow-voltage regulat or. No dam age will occur if it is lef t on. How ever, lea ving it on will resu lt in les s than o ptimized

power consumption.

The interna l regulator tak es its po wer from VDD_IO, and f unctions best when VDD_IO is 3.3V or 2.5V. If VDD_IO is 1.8V,

the output voltage will be somewhat decreased. For optimal performance, an external power supply, in place of the

internal regulator, is recommended when VDD_IO is 1.8V.

The preferred method of configuring the low-voltage related power pins for using the internal low-voltage regulator is

illustrated in Figure 16. The output of the internal regulator is available on pins 40 and 51 and is filtered using external

capacitors and a fer rite bead to sup pl y power to pins 6 and 1 6. The num ber of capac itors, values of capac ito rs, and ex act

placement of components will depend upon the specific design.

Figure 16. Recommended L o w-Voltage Power Connection using the Internal Low-Voltage Regulator

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Power Management

The KSZ8463 supports enhanced power management features in low-power state with energy detection to ensure low-

power dissipation during device idle periods. There are three operation modes under the power management function

which is controlled by two bits in the power management control and wake-up event status register (PMCTRL, 0x032 –

0x033) as shown below:

PMCTRL[1:0] = “00” Normal Operation Mode

PMCTRL[1: 0] = “01” Energy Detect Mode

PMCTRL[1:0] = “10” Global Soft Power-Down Mode

The Table 11 indicates all internal function blocks status under three different power-management operation modes.

Table 11. Power Management and Internal Blocks

KSZ8463 Function Blocks Power Management Operation Modes

Normal M ode Energy Detect Mode Soft Power-Down Mode

Internal PLL Clock Enabled Disabled Disabled

Tx/Rx PHYs Enabled Energy Detect at Rx Disabled

MACs Enabled Disabled Disabled

Host Interface Enabled Disabled Disabled

Normal Operation Mode

Normal operation mode is the power management mode entered into after device power-up or after hardware reset pin

63. It is est ablished via bits [1:0] = “00” in the PMCTRL regis ter. When the KSZ 8463 is in norm al operation m ode, all PLL

clocks are running, PHYs and MACs are on, and the CPU is ready to read or write the KSZ8463 through these serial

interfaces (SPI and MIIM).

During the normal operation mode, the host CPU can change the power management mode bits[1:0] in the PMCTRL

Energy-Detect Mode

Energy-detect m ode provid es a mec hanism to save m ore po wer than in norm al operati on m ode when t he KSZ 8463 is no t

connecte d to an active l ink partner. For ex ample, if the cable is no t present or it is connect ed to a powered d own partner ,

the KSZ8463 c an autom aticall y enter the low po wer state in energ y detect m ode. Onc e activit y resum es after attaching a

cable or by a link partner attempting to establish a link, the KSZ8463 will automatically power-up into the normal power

state in energy detect normal power state. The energy-detect mode function is not valid in fiber mode using the

KSZ8463F ML and KSZ8463FRL devices.

Energy-detect mode consists of two states, normal-power state and low-power state. While in low-power state, the

KSZ8463 reduces power consum ption by disabling all circuitry except the energy detect circuitry of the receiver. Energy

detect mode is enabled by setting bits[1:0] = “01” in the PMCTRL register. When the KSZ8463 is in this mode, it will

monitor the cable e nergy. If there is no energy on the cable for a tim e longer than a pre-configured value determ ined by

bits[7:0] (Go-Sleep Time) in the GST register, the device will go into the low-power state. When the KSZ8463 is in low-

power state, it will keep monitoring the cable energy. Once energy is detected from the cable and is present for a time

longer than 100ns, the KSZ8463 will enter the normal-power state.

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Global So ft Power-Down Mode

Soft power-d own m ode is e ntered by settin g bits [1:0] = “10” in PMC TRL r egister . W hen the device is in this m ode, all PLL

clock s are dis abled, t he PH Ys and t he M ACs are off , all int ernal r egister s val ue wi ll chang e to def ault value , and t he CPU

serial interf ace is only used to wake-up this device from the current soft power-down mode to normal operation mode by

setting bits[1:0] = “00” in the PMCTRL register.

All strap-in pins are sampled to latch any new values when soft power-down is disabled.

Energy-Efficient Ethernet (EEE)

Energy-efficient Ether net (EE E) is im plem ented in the KSZ8463M L device as desc ribed in the IEE E 802.3 AZ s pecific ation

for MII operations on Port 1 and Port 2. The EEE function is not available for fiber mode Ports using the KSZ8463FML

and KSZ84 63FRL dev ices. EEE is not perfor med at Port 3 sinc e that is a MAC to M AC interf ace and not a MAC to PHY

interface. The internal connection between the MAC and PHY blocks are performed in MII mode. The details of the

implementation are provided in the information that follows. The standards are defined around a MAC that supports

special signaling associated with EEE. EEE saves power by keeping the voltage on the Ethernet cable at approximately

0V for as of ten as possible during periods of no traf fic activit y. This is called low-power i dle (LPI) state. However, t he link

will respond automatically when traffic resumes and do so in such a way as to not cause blocking or dropping of any

packets (the wake-up time for 100BT is specified to be less than 30µs.). The transmit and receive directions are

independe ntly control le d. N ote the EE E is no t s pec ifie d or implem ented f or 1 0BT . In 10 BT, the tra nsmitter is alre ady OFF

during idle periods.

The EEE feat ure is enable d by default. EEE is auto-negotiated i ndependentl y for each direction on a link, and is enab led

only if both nodes on a link support it. To disable EEE, clear the Next Page Enable bit(s) for the desired port(s) in the

PCSEEEC register (0x0F3) and restart auto-negotiation.

Based on the EEE specification, the energy savings from EEE occurs at the PHY level. However, the KSZ8463 device

reduces the power consumption not only in the PHY block but also in the MAC and switch blocks by shutting down any

unused clocks as much as possible when the device is at LPI state. A comprehensive LPI request on/off policy is also

built-in at the switch level to determine when to issue LPI requests and when to stop the LPI request. Some software

control options are provided in the device to terminate the LPI request in the early phase when certain events occur to

reduce the latency impact during LPI recovery. A configurable LPI recovery time register is provided at each port to

specif y the recover y time ( 25µs at def ault) requ ired for the KSZ8463 an d its l ink partner before th ey are re ady to tra nsm it

and rece ive a pack et after goi ng back to the norm al state. For d etails, ple ase refer to the KSZ8463 EEE reg ister s (0x0E0

– 0x0F7) description.

The time during which LPI mode is active is during what is called quiet time. This is shown in Figure 17.

Figure 17. Traffic Activity and EEE

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Transmit Direction Control for MII Mode

For ports 1 and 2, low-power idle (LPI) s tate for the transm it directio n will be ent ered when t he internal E EE MAC signals

to its PHY to do so. The PHY will stay in the transmit LPI state as long as indicated by the MAC. The TX_CLK is not

stopped.

Even though the PHY is in LPI state, it will periodically leave the LPI state to transmit a refresh signal using specific

transm it code bits . This allows the li nk partner to k eep trac k of the long-term variat ion of c hannel char act eristic s and clock

drift bet ween the t wo partners. Approx imatel y every 20ms − 22ms, the PH Y will trans mit a bit pattern to its li nk partner of

duration 200µs − 220µs. The refresh times are listed in Figure 17.

Recei ve Direction Control for MII Mode

If enabled for LPI mode, upon receiving a P Code bit pattern (refresh), the PH Y will enter the LPI state and signal to the

internal MAC . If the PH Y r e ceiv es som e non-P C od e bit pattern, it will s igna l to the MAC to return to “normal frame” mode.

The PHY can turn off the RX_CLK after nine or more clocks have occurred in the LPI state.

In the EEE-compliant environment, the internal PHYs will be monitoring and expecting the P Code (refresh) bit pattern

from its link partner that is generated approximately every 20ms − 22ms, with a duration of about 200µs − 220µs. This

allows the link partner to keep track of the long term variation of channel characteristics and clock drift between the two

partners.

Registers Associated with EEE

The following registers are used to configure or manage the EEE feature:

• Reg. DCh, DDh − P1ANPT – Port 1 Auto-Negotiation Next Page Transmit Register

• Reg. DEh, DFh − P1ALPRNP – Port 1 Auto-Negotiation Link Partner Received Next Page Register

• Reg. E0h, E1h − P1EEEA – Port 1 EEE and Link Partner Advertisement Register

• Reg. E2h, E3h − P1EEEWEC – Port 1 EEE Wake Error Count Register

• Reg. E4h, E5h − P1EEECS – Port 1 EEE Control/Status and Auto-Negotiation Expansion Register

• Reg. E6h − P1LPIRTC – Port 1 LPI Recovery Time Counter Register

• Reg. E7h − BL2LPIC1 – Buffer Load to LPI Control 1 Register

• Reg. E8h, E9h − P2ANPT – Port 2 Auto-Negotiation Next Page Transmit Register

• Reg. EAh, EBh − P2ALPRNP – Port 2 Auto-Negotiation Link Partner Received Next Page Register

• Reg. ECh, EDh − P2EEEA – Port 2 EEE and Link Partner Advertisement Register

• Reg. EEh, EFh − P2EEEWEC – Port 2 EEE Wake Error Count Register

• Reg. F0h, F1h − P2EEECS – Port 2 EEE Control/Status and Auto-Negotiation Expansion Register

• Reg. F2h − P2LPIRTC – Port 2 LPI Recovery Time Counter Register

• Reg. F3h − PCSEEEC – PCS EEE Control Register

• Reg. F4h, F5h − ETLWTC – Empty TXQ to LPI Wait Time Control Register

• Reg. F6h, F7h − BL2LPIC2 – Buffer Load to LPI Control 2 Register

Interrupt Generation on Power Management-Related E vents

The various status bits associated with link change and energy detect situations are found in the PMCTRL Register

(0x032 – 0x033) bits [3:2]. T he e nabling of thes e sign als to gen erate an int errupt a re in IER (0x1 90 – 0x 191) bits [3:2]. T h e

actual interrupt status for these bits are located in ISR (0x192 – 0x193) bits[3:2].

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Interfaces

The KSZ8463 device incorporates a number of inter f ac es to ena bl e it t o be des i g ned into a s tan dard network environment

as well as a vend or unique environm ent. The avai lable interf aces are sum marized in T able 12. The details o f each us age

in Table 12 are provided in the sections which follow.

Table 12. Available Interfaces

Interface Type Usage Registers

Accessed

SPI Configuration and

−

External CPU or controller can R/W all internal registers

thru this interfac e. All

MIIM Configuration and

MII Data Flow Interface to the port 3 MAC using the standard MII timing. N/A

RMII Data Flow Interface to the port 3 MAC using the faster reduced RMII timing. N/A

PHY Data Flow Interface to the two internal PHY devices. N/A

Configura tion Interface

The KSZ8463 supports a serial configuration interface, which may be either SPI or MIIM. T he strapping option on pin 35

(RXD0) and pin 34 (RXD1) is used to select one of these two interfaces. This setting may be read in the serial bus

selection bits in the configuration status and serial bus mode register (0x0D8 – 0x0D9): CFGR.

SPI Slave Serial Bus Configuration

The KSZ8463 supports a SPI interface in slave mode (see Strapping Options). In this managed mode, an external SPI

master device (micro-controller or CPU) supplies the serial clock (SPI_SCLK), chip select (SPI_CSN), and serial input

data (SPI_DI). Serial output data (SPI_DO) is driven out by the KSZ8463. SPI operations start with the falling edge of

SPI_CSN and e nd with th e rising edge of SPI_CSN . SPI_SCL K is expected t o stay low when S PI operation is idle. A SPI

master device ( external c ontroller/C PU) has c omplete programm ing acces s to all KSZ 8463 reg isters. T able 13 shows the

SPI interface connection for the KSZ8463.

Table 13. SPI Connection

KSZ8463 Pin Number KSZ8463 (SPI Slave) Signal Name External Processor (SPI Master) Signal Description

42 SPI_CSN (input) SPI Chip Select (Master output)

44 SPI_SCLK (input) SPI Clock (Master output)

45 SPI_DI (input) SPI Data Out (Master output)

41 SPI_DO (output) SPI Data In (Master input)

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Input dat a on SPI_DI (MOSI) is sampled b y the K SZ8463 on the r ising edge of SPI_SC LK. Timing of the output data on

SPI_DO (MISO) is user-selectable by a strapping option on pin 33. The options are high-speed SPI and low-speed SPI:

• High-Speed SPI Mode: SPI_DO is clocked out at the rising edge of SPI_SCLK mode. The master will typically sample

MISO data at the falling edge of SPI_SCLK, but depending on the MISO hold time requirements of the master, rising

edge sampling may be possible.

• Low-Speed SPI Mode: SPI_DO is clocked out at the falling edge of SPI_SCLK, ½ cycle later than high-speed SPI

mode. The master will typically sample MISO data at the rising edge of SPI_SCLK.

The KSZ8463 supports two standard SPI commands:

• Internal I/O registers read (Opcode = “0”)

• Internal I/O registers write (Opcode = “1”)

As shown in Table 14 and Figure 18, there are two phases in each SPI operation. The first is the command phase,

followed by the d ata phas e. The c omm and phase is t wo b ytes long f or register acc ess. The dat a phase is in th e range of

one to four bytes long depending on the specified byte enable bits B[3:0] in command phase.

Table 14. Register Access using the SPI Interface

SPI Operation

Command Phase (SI pin)

Data Phase (SO or SI pins)

Byte 0 [7:0] Byte 1 [7:0]

Op Register Address Byte Enable TA Bits

(Read Data on SO pin)

(Write Data on SI pin)

Notes:

1. In Comm and phase, Address A[10:2] access regist er location i n double-word and Byte enable B[3:0] to indic ate which byte to access during read or

write. In Data phase, the byte 0 is first in/out and byte 3 is last in/out during read or write.

2. B[3:0] -> 1: enable byte; 0: disable byte. CPU can enable any one of the four bytes, lower or higher two bytes, or all four bytes during the command

phase.

3. TA bits are turn around bits and “don’t care bits.

SPI Register Access Operation Timing

As shown in Fig ur e 10 and Figure 11, illustrating the SPI internal I/O registers read and write operation timing, the first two

comm and byte 0/1 c ontain opcode (0: rea d com m and, 1: write c omm and), A[10:2 ] addres s bits to ac cess register loc ation

in double words and B[3 :0] Byte en able bits t o indicat e which dat a byte is av ailable in d ata phase (1: byte enab le, 0: b yte

disable). The following is data phase either 1, 2 or 4 bytes depending on B[3:0] setting.

Figure 19 and Fig ure 20 sho w the details of the SPI bus protoc ol for read and write operatio ns. Initiall y the master s ends

a two-b yte comm and. This comm and begins with a 1-bit opcode ( 0: read comm and, 1: write comm and), It is followed b y

address bits A[10] to A[2], then four byte enable bits B[3:0], then finally two zero bits. The byte enable bits are set to

indicate which bytes will be transferred in the data phase of the SPI operation. For a two-byte operation, which is the

most common, B[3:0] = 0011. For a single byte operation, B[3:0] = 0001, and for a four-b yte operat ion, B[3: 0] = 1111.

The sequence for data transfer is least significant byte first. Then within each byte, the most significant bit goes first.

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Figure 18. SPI Register Read Operation

−

Low-Speed Mode

Figure 19. SPI Register Read Operation

−

High-Speed Mode

Figure 20. SPI Register Write Operation Timing

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MII Management (MIIM) Interface

The KSZ8463 supports the IEEE 802.3 MII management interface, also known as the management data input/output

(MDIO) interface. This interface allows upper-layer devices to monitor and con trol the states of the KSZ8463 PHY block.

An external devic e with MD C /MDIO ca pabilit y can read the PHY status or configur e the P HY settings . D et a ils on th e MIIM

interface can be found in Clause 22.2.4.5 of the IEEE 802.3u Specification. Timing information can be found in 802.3

section 22.3 .4.

The MIIM interface consists of the following:

• A physical connection that uses a data signal (MDIO) and a clock signal (MDC) for communication between an external

controller and the KSZ8463 device.

• A specific protocol that operates across the two signal physical connection that allows an external controller to

comm unic ate with the inter nal PH Y dev ices .

• Access to a set of eight 16-bit registers, consisting of six standard MIIM registers (0x0 – 0x5) and two custom MIIM

registers (0x1D and 0x1F). Each set of registers is duplicated for each internal PHY device.

The MIIM Interface can operate up to a maximum clock speed of 5MHz and access is limited to only the registers in the

PHY block. Table 15 summarizes the MII management interface frame format.

Table 15. MII Management Interface Frame Format

Operation

Mode Preamble

(32-bit) Start of Frame

(2-bit)

Operation

Code

(2-bit)

PHY

Address

(5-bit)

Address

(5-bit)

Turn Around

(2-bit) Register Data

(16-bit) Idle

Read All 1s 01 10 A[4:0] Reg[4:0] Z0 D[15:0] Z

Write All 1s 01 01 A[4:0] Reg[4:0] 10 D[15:0] Z

Media Independent Interface (MII)

The media independent interface (MII) is specified in Clause 22 of the IEEE 802.3u Standard. It provides a common

interface between PHY layer and MAC layer devices. The MII provided by the KSZ8463ML and KSZ8463FML is

connected to the device’s third MAC on port 3. This interface is operated in PHY Mode or in MAC Mode. This is

determ ined by the strap pin g option on the RX_DV pin (pin 31) at t he time of de-a ss er tion of RST N . T he in terfac e c ontai ns

two distinc t grou ps of s igna ls, one for trans mission and the oth er f or r ec eption. T able 1 6 des cr ibes th e s ign al s used b y the

MII interface to connect to an external MAC or an external PHY.

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Table 16. MII Interface Signal and Pin Associations

PHY Mode Signals Connection MII Interface

Signals Description

MAC Mode Signals Connection

KSZ8463ML/FML

In PHY-Mode Signals External MAC

Controller Signals External PHY

Device Signals KSZ8463ML/FML

In MAC-Mode Signals

TX_EN (pin 22, input) TX_EN Transmit Enable TX_EN RX_DV (pin 31, output)

MII_BP (pin 28, input) TX_ER Transmit Error TX_ER NA (not used)

TXD3 (pin 23, input) TXD3 Transmit Data Bit 3 TXD3 RXD3 (pin 32, output)

TXD 2 (pin 24, input) TXD2 Transmit Data Bit 2 TXD2 RXD2 (pin 33, output)

TXD 1 (pin 25, input) TXD1 Transmit Data Bit 1 TXD1 RXD1 (pin 34, output)

TXD 0 (pin 26, input) TXD0 Transmit Data Bit 0 TXD0 RXD0 (pin 35, output)

TX_CLK (pin 27, output) TX_CLK Transmit Clock TX_CLK RX_CLK (pin 38, input)

COL (pin 37, output) COL Coll ision Det ection COL COL (pin 37, input)

CRS (pin 36, output) CRS Ca rrier Sense CRS CRS (pin 36, input)

RX_DV (pin 31, output) RX_DV Receive Data Valid RX_DV TX_EN (pin 22, input)

NA (not used) RX_ER Receive Error RX_ER TX_ER (pin 28, input)

RXD3 (pin 32, output) RXD3 Receive Data Bit 3 RXD3 TXD3 (pin 23, input)

RXD2 (pin 33, output) RXD2 Receive Data Bit 2 RXD2 TXD2 (pin 24, input)

RXD1 (pin 34, output) RXD1 Receive Data Bit 1 RXD1 TXD1 (pin 25, input)

RXD0 (pin 35, output) RXD0 Receive Data Bit 0 RXD0 TXD0 (pin 26, input)

RX_CLK (pin 38, output) RX_CLK Receive Clock RX_CLK TX_CLK (pin 27, input)

The MII interface operates in either PHY mode or MAC mode. The data interface is 4-bits wide and runs at one quarter

the network bit rate; either 2.5MHz in 10BT or 25MHz in 100BT (not encoded). Additional signals on the transmit side

indicate when data is valid or when an error occurs during transmission. Similarly, the receive side has signals that

convey when the data is valid and without physical layer errors. For half duplex operation, the COL signal indicates if a

collision has occurred during transmission.

The KSZ8463ML/FML does not provide the RX_ER signal in PHY mode operation or the TX_ER signal in MAC mode

operation. Normally, RX_ER indicates a receive error coming from the physical layer device and TX_ER indicates a

transmit error from the MAC device. Since the switch filters error frames, these MII error signals are not used by the

KSZ8463ML/FML. So, for PHY mode operation, if the device interfacing with the KSZ8463ML/FML has an RX_ER input

pin, it needs to be tied low. And, for MAC mode operation, if the device interfacing with the KSZ8463ML/FML has a

TX_ER input pin, it also needs to be tied low.

The KSZ8 463ML/FML prov ides a bypass f eature in the MI I PH Y m ode. The T X _ER/MII_ BP pi n (pin 2 8) is us ed to ena ble

the MII bypass m ode when this pin is tied to high. The MII (port 3) is shut down if TX_ER/MII_BP is set t o high in the MII

PHY mode. In this case, no new ingress frames from either port 1 or port 2 will be sent out through port 3 and only

switchin g between port 1 and port 2 for all ingr ess pack ets will occur, and th e fram es for port 3 alread y in pack et memor y

will be flushed out.

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Reduced Media Independent Interface (RMII)

The reduced media independent interface (RMII) specifies a low pin count MII. It is available only on port 3 of the

KSZ8463RL and KSZ846 3FRL devices f or com munication with the MAC a ttached to th at port. As with MII, RMII prov ides

a common interface between physical layer and MAC layer devices, and has the following key characteristics:

• Supports network data rates of either 10Mbps or 100Mbps.

• Uses a single 50 MHz clock reference (provided intern all y or externally) for both transmit and receive data.

• Uses independent 2-bit wide transmit and receive data paths.

• Contains two distinct groups of signals: one for transmission and the other for reception.

The user should selec t one the two RMII c lock ing m ethods sho wn in T able 17. W hile EN_REF CLK _O (pin 2 3) is high, t he

KSZ8463RL/FRL will outpu t a 50MHz cl ock on REFC LK_O (pin 32) , which is derived f rom t he 25MHz cr ysta l or oscil lator

attached to the X1 and X2 inputs. In this mode, R EFCLK_O must be externally connect ed to REFCLK_I (pin 27). While

EN_REFCLK_O (pin 23) is low, the KSZ8463RL/FRL will require an external 50 MHz signal to be input to the REFCLK_I

input from an external source. In this mode, the X1 and X2 pins are not used.

Table 17. RMII Clock Settings

EN_REFCLK_O

(Pin 23) 25 / 50 MHz Select (Pin 41)

at Power-Up/Reset Time Output on

REFCLK_0 (Pin 32) Clock Source Note

0 (Disable) 0 (50MHz) No External 50MHz

input to REFCLK_I - X1/X2 are not used. Leave them

unconnected.

1 (Enable) 1 (25MHz) 50MHz

REFCLK_O output

must be externally

connected to

REFCLK_I

- 50MHz output on REFCLK_O

- X1/X2 is connected to a 25MHz

crystal or oscillat or

Do not use the remainder of logical inputs NA NA

The RMII interface in KSZ8463RL/FRL is connected to the device’s third MAC. It complies with the RMII specification.

Table 18 describes the signals used by the RMII interface. Refer to the RMII specification for full details on the signal

descriptions.

Table 18. RMII Signal Descriptions

RMII

Signal Name Direction

(with respect to the PHY) Direction

(with respect to the MAC) RMII

Signal Description KSZ8463RL/FRL

RMII Signal (Direction)

REFCLK Input Input or Output

Synchrono us 50MHz

clock reference for

receive, transmit, and

control interface

REFCLK_I (input)

CRS_DV Output Input Carrier Sense/

Receive Data Valid RX_DV (output)

RXD[1:0] Output Input Receive Data Bit[1:0] RXD[1:0] (output)

TX_EN Input Output Transmit Enable TX_EN (input)

TXD[1:0] Input Output Transmit Data Bit[1:0] TXD[1:0] (input)

RX_ER Output Input or not required Receive Error (not used)

− − − − TX_ER* (input)

* Connects to RX_ER signal

of RMII PHY device

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The KSZ8463RL/FRL filters error frames, and thus does not im plement the RX_ER output signal. T o detect error frames

from RMII PHY devices, the TX_ER input signal of the KSZ8463RL/FRL is connected to the RX_ER output signal of the

RMII PHY device. Collision detection is implemented in accordance with the RMII Specification.

In RMII mode, tie the MII signals (TXD[3:2], RXD[3:2] and TX_ER) to ground via a resister if they are not used.

The KSZ8463RL/FRL can interface to either an RMII PHY or an RMII MAC device. The RMII MAC device allows two

KSZ8463RL/FRL devic es to be c onnected back -to-back. T able 19 sho ws the KSZ8463RL/FRL RMII p in connecti ons wit h

an external RMII PHY and an external RMII MAC, such as another KSZ8463RL/FRL device.

Table 19. RMII PHY-to-MAC and MAC-to-MAC Signal Connections

KSZ8463RL/FRL PHY-MAC Connections Signal

Descriptions

KSZ8463RL/FRL MAC-MAC Connections

External

PHY Signals KSZ8463RL/FRL

MAC Signals KSZ8463RL/FRL

MAC Signals External

MAC Signals

REFCLK REFCLK_I Reference Clock REFCLK_I REF_CLK

TX_EN RX_DV Carrier Sense /

Receive Data Valid RX_DV CRS_DV

TXD1 RXD1 Receive Data Bit[1] RXD1 RXD1

TXD0 RXD0 Receive Data Bit[0] RXD0 RXD0

CRS_DV TX_EN Transmit Enable TX_EN TX_EN

RXD1 TXD1 Transmit Data Bit[1] TXD1 TXD1

RXD0 TXD0 Transmit Data Bit[0] TXD0 TXD0

RX_ER TX_ER Receive Error (not used) (not used)

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Device Registers

The KSZ8463 device has a rich set of registers available to manage the functionality of the device. Access to these

registers is via the M IIM or SPI interfaces . All of the r egisters are not accessibl e via each interface. Figure 21 prov ides a

global picture of accessibility via the various interfaces and addressing ranges from the perspective of each interface.

Figure 21. Interface and Register Mapping

The regis ters with in the l inear 0x0 00 – 0x7FF a ddress space are all acces sible vi a the SP I interfac e by a microproc essor

or CPU attached to that buss. The mapping of the various functions within that linear address space is summarized in

Table 20.

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Table 20. Mapping of Functional Areas within the Address Space

0x000 – 0x0FF Switch Control and Configuration Registers which control the overall functionality of the

Switch, MAC, and PHYs

0x026 – 0x031 Indirect Access Registers

Registers used to indirectly address and access four

distinct areas within the device.

- Management Information Base (MIB) Counters

- Static MAC Address Table

- Dynamic MAC Address Table

- VLAN Table

0x044 – 0x06B PHY1 and PHY2 Registers The same PHY registers as specified in IEEE 802.3

specification

0x100 – 0x1FF Interrupts and Global Reset The registers and bits associated with interrupts and

global reset

0x200 – 0x3FF IEEE 1588 PTP Trigger Control and Output

Registers Registers used to configure and use the IEEE 1588

trigger functions

0x400 – 0x5FF IEEE 1588 PTP Timestamp Input Units Registers used for control lin g and moni tori ng th e

1588 timestamp units

0x600 – 0x7FF IEEE 1588 PTP Clock and Global Control Register s that con trol and mo n itor the PT P clock, port

ingress/egress, and messaging

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In managed s witch mode, the regis ters within the KSZ 8463 can be acces sed using the SPI sla ve serial bus interf ace. An

external microprocessor communicates with the device through these registers. These registers are used for configuring

the device, control li ng proc es ses , and read ing var ious s tatus es .

I/O Registers

The following I/O register space mapping tables apply to 8-bit or 16-bit locations. Depending upon the serial bus mode

selected, each I/O access can be performed using the following operations:

• Using 8-bit accesses for all serial bus modes, there are 2048-byte address locations.

• In byte, word, or double word access for SPI serial bus mode only.

Interna l I/O Register Space Mapping for Switch Control and Configuration (0x000 – 0x0FF)

I/O Register Offset Location Register Name Default Va lue Description

16-Bit 8-Bit

0x000 – 0x001 0x000

0x001 CIDER

0x8443 (ML,

FML)

0x8453 (RL,

FRL)

Chip ID and Enable Register [15:0]

0x002 – 0x003 0x002

0x003 SGCR1 0x3450 Switch Global Control Register 1 [15:0]

0x004 – 0x005 0x004

0x005 SGCR2 0x00F0 Switch Global Control Register 2 [15:0]

0x006 – 0x007 0x006

0x007 SGCR3 0x6320 Switch Global Control Register 3 [15:0]

0x008 – 0x00B 0x008

0x00B Reserved

(4-Bytes) Don’t Care None

0x00C – 0x00D 0x00C

0x00D SGCR6 0xFA50 Switch Global Control Register 6 [15:0]

0x00E – 0x00F 0x00E

0x00F SGCR7 0x0827 Switch Global Control Register 7 [15:0]

0x010 – 0x011 0x010

0x011 MACAR1 0x0010 MAC Address Register 1 [15:0]

0x012 – 0x013 0x012

0x013 MACAR2 0xA1FF MAC Address Register 2 [15:0 ]

0x014 – 0x015 0x014

0x015 MACAR3 0xFFFF MAC Address Register 3 [15:0]

0x016

−

0x017 0x016

0x017 TOSR1 0x0000 TOS Priority Control Register 1 [15:0]

0x018

−

0x019 0x018

0x019 TOSR2 0x0000 TOS Priority Control Register 2 [15:0]

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Interna l I/O Register Space Mapping for Switch Control and Configuration (0x000 – 0x0FF) (Continued)

I/O Register Offset Location Register Name Default Value Description

16-Bit 8-Bit

0x01A

−

0x01B 0x01A

0x01B TOSR3 0x0000 TOS Priority Control Register 3 [15:0]

0x01C

−

0x01D 0x01C

0x01D TOSR4 0x0000 TOS Priority Control Register 4 [15:0]

0x01E

−

0x01F 0x01E

0x01F TOSR5 0x0000 TOS Priority Control Register 5 [15:0]

0x020

−

0x021 0x020

0x021 TOSR6 0x0000 TOS Priority Control Register 6 [15:0]

0x022

−

0x023 0x022

0x023 TOSR7 0x0000 TOS Priority Control Register 7 [15:0]

0x024

−

0x025 0x024

0x025 TOSR8 0x0000 TOS Priority Control Register 8 [15:0]

0x026

−

0x027 0x026

0x027 IADR1 0x0000 Indirect Access Data Register 1 [15:0]

0x028

−

0x029 0x028

0x029 IADR2 0x0000 Indirect Access Data Register 2 [15:0]

0x02A

−

0x02B 0x02A

0x02B IADR3 0x0000 Indirect Access Data Register 3 [15:0]

0x02C

−

0x02D 0x02C

0x02D IADR4 0x0000 Indirect Access Data Register 4 [15:0]

0x02E

−

0x02F 0x02E

0x02F IADR5 0x0000 Indirect Access Data Register 5 [15:0]

0x030

−

0x031 0x030

0x031 IACR 0x0000 Indirect Access Control Register [15:0]

0x032

−

0x033 0x032

0x033 PMCTRL 0x0000 Power Management Control and Wake-up Event Status

0x034

−

0x035 0x034

0x035 Reserved

(2-Bytes) 0x0000 None

0x036

−

0x037 0x036

0x037 GST 0x008E Go Sleep Time Register [15:0]

0x038

−

0x039 0x038

0x039 CTPDC 0x0000 Clock Tree Power Down Control Register [15:0]

0x03A – 0x04B 0x03A

0x04B Reserved

(18-Bytes) Don’t Care None

0x04C – 0x04D 0x04C

0x04D P1MBCR 0x3120 PHY 1 and MII Basic Control Register [15:0]

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Interna l I/O Register Space Mapping for Switch Control and Configuration (0x000 – 0x0FF) (Continued)

I/O Register Offset Location Register Name Default Value Description

16-Bit 8-Bit

0x04E – 0x04F 0x04E

0x04F P1MBSR 0x7808 PHY 1 and MII Basic Status Register [15:0]

0x050

−

0x051 0x050

0x051 PHY1ILR 0x1430 PHY 1 PHYID Low Register [15:0]

0x052

−

0x053 0x052

0x053 PHY1IHR 0x0022 PHY 1 PHYID High Register [15:0]

0x054

−

0x055 0x054

0x055 P1ANAR 0x05E1 PHY 1 Auto-Negotiation Advertisement Register [15:0]

0x056

−

0x057 0x056

0x057 P1ANLPR 0x0001 PHY 1 Auto-Negotiation Link Partner Ability Register [15:0]

0x058

−

0x059 0x058

0x059 P2MBCR 0x3120 PHY 2 and MII Basic Control Register [15:0]

0x05A

−

0x05B 0x05A

0x05B P2MBSR 0x7808 PHY 2 and MII Basic Status Register [15:0]

0x05C

−

0x05D 0x05C

0x05D PHY2ILR 0x1430 PHY 2 PHYID Low Register [15:0]

0x05E

−

0x05F 0x05E

0x05F PHY2IHR 0x0022 PHY 2 PHYID High Register [15:0]

0x060

−

0x061 0x060

0x061 P2ANAR 0x05E1 PHY 2 Auto-Negotiation Advertisement Register [15:0]

0x062

−

0x063 0x062

0x063 P2ANLPR 0x0001 PHY 2 Auto-Negotiation Link Partner Ability Register [15:0]

0x064

−

0x065 0x064

0x065 Reserved

(2-Bytes) Don’t Care None

0x066

−

0x067 0x066

0x067 P1PHYCTRL 0x0004 PHY 1 Special Control and Status Register [15:0]

0x068

−

0x069 0x068

0x069 Reserved

(2-Bytes) Don’t Care None

0x06A

−

0x06B 0x06A

0x06B P2PHYCTRL 0x0004 PHY2 Special Control and Status Register [15:0]

0x06C

−

0x06D 0x06C

0x06D P1CR1 0x0000 Port 1 Control Register 1 [15:0]

0x06E

−

0x06F 0x06E

0x06F P1CR2 0x0607 Port 1 Control Register 2 [15:0]

0x070 - 0x071 0x070

0x071 P1VIDCR 0x0001 Port 1 VID Control Register [15:0]

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Internal I/O Register Space Mapping for Switch Control and Configuration (0x000 – 0x0FF) (Continued)

I/O Register Offset Location Register Name Default Value Description

16-Bit 8-Bit

0x072

−

0x073 0x072

0x073 P1CR3 0x0000 Port 1 Control Register 3 [15:0]

0x074

−

0x075 0x074

0x075 P1IRCR0 0x0000 Port 1 Ingress Rate Control Register 0 [15:0]

0x076

−

0x077 0x076

0x077 P1IRCR1 0x0000 Port 1 Ingress Rate Control Register 1 [15:0]

0x078

−

0x079 0x078

0x079 P1ERCR0 0x0000 Port 1 Egress Rate Control Register 0 [15:0]

0x07A

−

0x07B 0x07A

0x07B P1ERCR1 0x0000 Port 1 Egress Rate Control Register 1 [15:0]

0x07C

−

0x07D 0x07C

0x07D P1SCSLMD 0x0400 Port 1 PHY Special Control/Status, LinkMD Register [15:0]

0x07E

−

0x07F 0x07E

0x07F P1CR4 0x00FF Port 1 Control Register 4 [15:0]

0x080

−

0x081 0x080

0x081 P1SR 0x8000 Port 1 Status Register [15:0]

0x082

−

0x083 0x082

0x083 Reserved

(2-Bytes) Don’t Care None

0x084

−

0x085 0x084

0x085 P2CR1 0x0000 Port 2 Control Register 1 [15:0]

0x086

−

0x087 0x086

0x087 P2CR2 0x0607 Port 2 Control Register 2 [15:0]

0x088

−

0x089 0x088

0x089 P2VIDCR 0x0001 Port 2 VID Control Register [15:0]

0x08A

−

0x08B 0x08A

0x08B P2CR3 0x0000 Port 2 Control Register 3 [15:0]

0x08C

−

0x08D 0x08C

0x08D P2IRCR0 0x0000 Port 2 Ingress Rate Control Register 0 [15:0]

0x08E

−

0x08F 0x08E

0x08F P2IRCR1 0x0000 Port 2 Ingress Rate Control Register 1 [15:0]

0x090

−

0x091 0x090

0x091 P2ERCR0 0x0000 Port 2 Egress Rate Control Register 0 [15:0]

0x092

−

0x093 0x092

0x093 P2ERCR1 0x0000 Port 2 Egress Rate Control Register 1 [15:0]

0x094

−

0x095 0x094

0x095 P2SCSLMD 0x0400 Port 2 PHY Special Control/Status, LinkMD Register [15:0]

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Interna l I/O Register Space Mapping for Switch Control and Configuration (0x000 – 0x0FF) (Continued)

I/O Register Offset Location Register Name Default Value Description

16-Bit 8-Bit

0x096 - 0x097 0x096

0x097 P2CR4 0x00FF Port 2 Control Register 4 [15:0]

0x098 - 0x099 0x098

0x099 P2SR 0x8000 Port 2 Status Register [15:0]

0x09A - 0x09B 0x09A

0x09B Reserved

(2-Bytes) Don’t Care None

0x09C - 0x09D 0x09C

0x09D P3CR1 0x0000 Port 3 Control Register 1 [15:0]

0x09E - 0x09F 0x09E

0x09F P3CR2 0x0607 Port 3 Control Register 2 [15:0]

0x0A0 - 0x0A1 0x0A0

0x0A1 P3VIDCR 0x0001 Port 3 VID Control Register [15:0]

0x0A2 - 0x0A3 0x0A2

0x0A3 P3CR3 0x0000 Port 3 Control Register 3 [15:0]

0x0A4 - 0x0A5 0x0A4

0x0A5 P3IRCR0 0x0000 Port 3 Ingress Rate Control Register 0 [15:0]

0x0A6 - 0x0A7 0x0A6

0x0A7 P3IRCR1 0x0000 Port 3 Ingress Rate Control Register 1 [15:0]

0x0A8 - 0x0A9 0x0A8

0x0A9 P3ERCR0 0x0000 Port 3 Egress Rate Control Register 0 [15:0]

0x0AA - 0x0AB 0x0AA

0x0AB P3ERCR1 0x0000 Port 3 Egress Rate Control Register 1 [15:0]

0x0AC - 0x0AD 0x0AC

0x0AD SGCR8 0x8000 Switch Global Control Register 8 [15:0]

0x0AE - 0x0AF 0x0AE

0x0AF SGCR9 0x0000 Switch Global Control Register 9 [15:0]

0x0B0 - 0x0B1 0x0B0

0x0B1 SAFMACA1L 0x0000 Source Address Filtering MAC Address 1 for Port 1 Register

Low [15:0]

0x0B2 - 0x0B3 0x0B2

0x0B3 SAFMACA1M 0x0000 Source Address Filtering MAC Address 1 for Port 1 Register

Middle [15:0]

0x0B4 - 0x0B5 0x0B4

0x0B5 SAFMACA1H 0x0000 Source Address Filtering MAC Address 1 for Port 1 Register

High [15:0]

0x0B6 - 0x0B7 0x0B6

0x0B7 SAFMACA2L 0x0000 Source Address Filtering MAC Address 2 for Port 2 Register

Low [15:0]

0x0B8 - 0x0B9 0x0B8

0x0B9 SAFMACA2M 0x0000 Source Address Filtering MAC Address 2 for Port 2 Register

Middle [15:0]

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

87 Revision 1.0

Interna l I/O Register Space Mapping for Switch Control and Configuration (0x000 – 0x0FF) (Continued)

I/O Register Offset Location Register Name Defau l t Value Description

16-Bit 8-Bit

0x0BA - 0x0BB 0x0BA

0x0BB SAFMACA2H 0x0000 Source Address Filtering MAC Address 2 for Port 2 Register

High [15:0]

0x0BC - 0x0C7 0x0BC

0x0C7 Reserved

(12-Bytes) Don’t Care None

0x0C8 - 0x0C9 0x0C8

0x0C9 P1TXQRCR1 0x8488 Port 1 TXQ Rate Control Register 1 [15:0]

0x0CA - 0x0CB 0x0CA

0x0CB P1TXQRCR2 0x8182 Port 1 TXQ Rate Control Register 2 [15:0]

0x0CC - 0x0CD 0x0CC

0x0CD P2TXQRCR1 0x8488 Port 2 TXQ Rate Control Register 1 [15:0]

0x0CE - 0x0CF 0x0CE

0x0CF P2TXQRCR2 0x8182 Port 2 TXQ Rate Control Register 2 [15:0]

0x0D0 - 0x0D1 0x0D0

0x0D1 P3TXQRCR1 0x8488 Port 3 TXQ Rate Control Register 1 [15:0]

0x0D2 - 0x0D3 0x0D2

0x0D3 P3TXQRCR2 0x8182 Port 3 TXQ Rate Control Register 2 [15:0]

0x0D4 - 0x0D5 0x0D4

0x0D5 Reserved

(2-Bytes) Don’t Care None

0x0D6 - 0x0D7 0x0D6

0x0D7 IOMXSEL 0x0FFF Input and Output Multiplex Selection Register [15:0]

0x0D8 - 0x0D9 0x0D8

0x0D9 CFGR 0x00FE Configuration Status and Serial Bus Mode Register [15:0]

0x0DA - 0x0DB 0x0DA

0x0DB Reserved

(2-Bytes) Don’t Care None

0x0DC - 0x0DD 0x0DC

0x0DD P1ANPT 0x2001 Port 1 Auto-Negotiation Next Page Transmit Register [15:0]

0x0DE - 0x0DF 0x0DE

0x0DF P1ALPRNP 0x0000 Port 1 Auto-Negotiation Link Partner Received Next Page

0x0E0 - 0x0E1 0x0E0

0x0E1 P1EEEA 0x0002 Port 1 EEE and Link Partner Advertisement Register [15:0]

0x0E2 - 0x0E3 0x0E2

0x0E3 P1EEEWEC 0x0000 Port 1 EEE Wake Error Count Register [15:0]

0x0E4 - 0x0E5 0x0E4

0x0E5 P1EEECS 0x8064 Port 1 EEE Control/Status and Auto-Negotiation Expansion

0x0E6 - 0x0E7 0x0E6

0x0E7 P1LPIRTC

BL2LPIC1 0x27

0x08 Port 1 LPI Recovery Time Counter Register [7:0]

Buffer Load to LPI Control 1 Register [7:0]

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

88 Revision 1.0

Interna l I/O Register Space Mapping for Switch Control and Configuration (0x000 – 0x0FF) (Continued)

I/O Register Offset Location Register Name Default Value Description

16-Bit 8-Bit

0x0E8 - 0x0E9 0x0E8

0x0E9 P2ANPT 0x2001 Port 2 Auto-Negotiation Next Page Transmit Register [15:0]

0x0EA - 0x0EB 0x0EA

0x0EB P2ALPRNP 0x0000 Port 2 Auto-Negotiation Link Partner Received Next Page

0x0EC - 0x0ED 0x0EC

0x0ED P2EEEA 0x0002 Port 2 EEE and Link Partner Advertisement Register [15:0]

0x0EE - 0x0EF 0x0EE

0x0EF P2EEEWEC 0x0000 Port 2 EEE Wake Error Count Register [15:0]

0x0F0 - 0x0F1 0x0F0

0x0F1 P2EEECS 0x8064 Port 2 EEE Control/Status and Auto-Negotiation Expansion

0x0F2 - 0x0F3 0x0F2

0x0F3 P2LPIRTC

PCSEEEC 0x27

0x03 Port 2 LPI Recovery Time Counter Register [7:0]

PCS EEE Control Register [7:0]

0x0F4 - 0x0F5 0x0F4

0x0F5 ETLWTC 0x03E8 Empty TXQ to LPI Wait Time Control Register [15:0]

0x0F6 - 0x0F7 0x0F6

0x0F7 BL2LPIC2 0xC040 Buffer Load to LPI Control 2 Register [15:0]

0x0F8 - 0x0FF 0x0F8

0x0FF Reserved

(8-Bytes) Don’t Care None

Interna l I/O Register Space Mapping for Interrupts and Global Reset (0x100

−

0x1FF)

I/O Register Offset Location

16-Bit

8-Bit

0x100 - 0x123

0x100

0x123

Reserved

(36-Bytes)

Don’t Care None

0x124 - 0x125

0x124

0x125

MBIR 0x0000 Memory BIST Info Register [15:0]

0x126 - 0x127 0x126

0x127

GRR 0x0000 Global Reset Register [15:0]

0x128 - 0x18F

0x128

0x18F

Reserved

(104-Bytes)

Don’t Care None

0x190 - 0x191

0x190

0x191

IER 0x0000 Interrupt Enable Register [15:0]

0x192 - 0x193

0x192

0x193

ISR 0x0000 Interrupt Status Register [15:0]

0x194 - 0x1FF

0x194

0x1FF

Reserved

(108-Bytes)

Don’t Care None

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

89 Revision 1.0

Interna l I/O Register Space Mapping for PTP Trigger Output (1 2 Units, 0x200

−

0x3FF)

I/O Register Offset Location Register Name Default Value Description

16-Bit

8-Bit

0x200 - 0x201 0x200

0x201 TRIG_ERR 0x0000 Trigger Output Unit Error Register [11:0]

0x202 - 0x203 0x202

0x203 TRIG_ACTIVE 0x0000 Trigger Output Unit Active Register [ 11: 0]

0x204 - 0x205 0x204

0x205 TRIG_DONE 0x0000 Trigger Output Unit Done Register [11:0]

0x206 - 0x207 0x206

0x207 TRIG_EN 0x0000 Trigger Output Unit Enable Register [11:0]

0x208 - 0x209 0x208

0x209 TRIG_SW_RST 0x0000 Trigger Output Unit Software Reset Register [11:0]

0x20A - 0x20B 0x20A

0x20B TRIG12_PPS_WIDTH 0x0000 Trigger Output Unit 12 PPS Pulse Width Register

0x20C – 0x21F 0x20C

0x21F Reserved

(20-Bytes) Don’t Care None

0x220 - 0x221 0x220

0x221 TRIG1_TGT_NSL 0x0000 Trigger Output Unit 1 Target Time in Nanoseconds

Low-Word Register [15:0]

0x222 - 0x223 0x222

0x223 TRIG1_TGT_NSH 0x0000 Trigger Output Unit 1 Target Time in Nanoseconds

High-Word Register [29:16]

0x224 - 0x225 0x224

0x225 TRIG1_TGT_SL 0x0000 Trigger Output Unit 1 Target Time in Seconds Low-

Word Register [15:0]

0x226 - 0x227 0x226

0x227 TRIG1_TGT_SH 0x0000 Trigger Output Unit 1 Target Time in Seconds High-

Word Register [31:16]

0x228 - 0x229 0x228

0x229 TRIG1_CFG_1 0x3C00 Trigger Output Unit 1 Configuration/Control Register1

0x22A - 0x22B 0x22A

0x22B TRIG1_CFG_2 0x0000 Trigger Output Unit 1 Configuration/Control Register2

0x22C - 0x22D 0x22C

0x22D TRIG1_CFG_3 0x0000 Trigger Output Unit 1 Configuration/Control Register3

0x22E - 0x22F 0x22E

0x22F TRIG1_CFG_4 0x0000 Trigger Output Unit 1 Configuration/Control Register4

0x230 - 0x231 0x230

0x231 TRIG1_CFG_5 0x0000 Trigger Output Unit 1 Configuration/Control Register5

0x232 - 0x233 0x232

0x233 TRIG1_CFG_6 0x0000 Trigger Output Unit 1 Configuration/Control Register6

0x234 - 0x235 0x234

0x235 TRIG1_CFG_7 0x0000 Trigger Output Unit 1 Configuration/Control Register7

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

90 Revision 1.0

Interna l I/O Register Space Mapping for PTP Trigger Output (1 2 Units, 0x200

−

0x3FF) (Continued)

I/O Register Offset Location Register Name Default Value Description

16-Bit

8-Bit

0x236 - 0x237 0x236

0x237 TRIG1_CFG_8 0x0000 Trigger Output Unit 1 Configuration/Control Register8

0x238 – 0x23F 0x238

0x23F Reserved

(8-Bytes) Don’t Care None

0x240 - 0x241 0x240

0x241 TRIG2_TGT_NSL 0x0000 Trigger Output Unit 2 Target Time in Nanoseconds

Low-Word Register [15:0]

0x242 - 0x243 0x242

0x243 TRIG2_TGT_NSH 0x0000 Trigger Output Unit 2 Target Time in Nanoseconds

High-Word Register [29:16]

0x244 - 0x245 0x244

0x245 TRIG2_TGT_SL 0x0000 Trigger Output Unit 2 Target Time in Seconds Low-

Word Register [15:0]

0x246 - 0x247 0x246

0x247 TRIG2_TGT_SH 0x0000 Trigger Output Unit 2 Target Time in Seconds High-

Word Register [31:16]

0x248 - 0x249 0x248

0x249 TRIG2_CFG_1 0x3C00 Trigger Output Unit 2 Configuration/Control Register1

0x24A - 0x24B 0x24A

0x24B TRIG2_CFG_2 0x0000 Trigger Output Unit 2 Configuration/Control Register2

0x24C - 0x24D 0x24C

0x24D TRIG2_CFG_3 0x0000 Trigger Output Unit 2 Configuration/Control Register3

0x24E - 0x24F 0x24E

0x24F TRIG2_CFG_4 0x0000 Trigger Output Unit 2 Configuration/Control Register4

0x250 - 0x251 0x250

0x251 TRIG2_CFG_5 0x0000 Trigger Output Unit 2 Configuration/Control Register5

0x252 - 0x253 0x252

0x253 TRIG2_CFG_6 0x0000 Trigger Output Unit 2 Configuration/Control Register6

0x254 - 0x255 0x254

0x255 TRIG2_CFG_7 0x0000 Trigger Output Unit 2 Configuration/Control Register7

0x256 - 0x257 0x256

0x257 TRIG2_CFG_8 0x0000 Trigger Output Unit 2 Configuration/Control Register8

0x258 – 0x25F 0x258

0x25F Reserved

(8-Bytes) Don’t Care None

0x260 - 0x261 0x260

0x261 TRIG3_TGT_NSL 0x0000 Trigger Output Unit 3 Target Time in Nanoseconds

Low-Word Register [15:0]

0x262 - 0x263 0x262

0x263 TRIG3_TGT_NSH 0x0000 Trigger Output Unit 3 Target Time in Nanoseconds

High-Word Register [29:16]

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

91 Revision 1.0

Interna l I/O Register Space Mapping for PTP Trigger Output (1 2 Units, 0x200

−

0x3FF) (Continued)

I/O Register Offset Location Register Name Default Value Description

16-Bit

8-Bit

0x264 - 0x265 0x264

0x265 TRIG3_TGT_SL 0x0000 Trigger Output Unit 3 Target Time in Seconds Low-

Word Register [15:0]

0x266 - 0x267 0x266

0x267 TRIG3_TGT_SH 0x0000 Trigger Output Unit 3 Target Time in Seconds High-

Word Register [31:16]

0x268 - 0x269 0x268

0x269 TRIG3_CFG_1 0x3C00 Trigger Output Unit 3 Configuration/Control Register1

0x26A - 0x26B 0x26A

0x26B TRIG3_CFG_2 0x0000 Trigger Output Unit 3 Configuration/Control Register2

0x26C - 0x26D 0x26C

0x26D TRIG3_CFG_3 0x0000 Trigger Output Unit 3 Configuration/Control Register3

0x26E - 0x26F 0x26E

0x26F TRIG3_CFG_4 0x0000 Trigger Output Unit 3 Configuration/Control Register4

0x270 - 0x271 0x270

0x271 TRIG3_CFG_5 0x0000 Trigger Output Unit 3 Configuration/Control Register5

0x272 - 0x273 0x272

0x273 TRIG3_CFG_6 0x0000 Trigger Output Unit 3 Configuration/Control Register6

0x274 - 0x275 0x274

0x275 TRIG3_CFG_7 0x0000 Trigger Output Unit 3 Configuration/Control Register7

0x276 - 0x277 0x276

0x277 TRIG3_CFG_8 0x0000 Trigger Output Unit 3 Configuration/Control Register8

0x278 – 0x27F 0x278

0x27F Reserved

(8-Bytes) Don’t Care None

0x280 - 0x281 0x280

0x281 TRIG4_TGT_NSL 0x0000 Trigger Output Unit 4 Target Time in Nanoseconds

Low-Word Register [15:0]

0x282 - 0x283 0x282

0x283 TRIG4_TGT_NSH 0x0000 Trigger Output Unit 4 Target Time in Nanoseconds

High-Word Register [29:16]

0x284 - 0x285 0x284

0x285 TRIG4_TGT_SL 0x0000 Trigger Output Unit 4 Target Time in Seconds Low-

Word Register [15:0]

0x286 - 0x287 0x286

0x287 TRIG4_TGT_SH 0x0000 Trigger Output Unit 4 Target Time in Seconds High-

Word Register [31:16]

0x288 - 0x289 0x288

0x289 TRIG4_CFG_1 0x3C00 Trigger Output Unit 4 Configuration/Control Register1

0x28A - 0x28B 0x28A

0x28B TRIG4_CFG_2 0x0000 Trigger Output Unit 4 Configuration/Control Register2

0x28C - 0x28D 0x28C

0x28D TRIG4_CFG_3 0x0000 Trigger Output Unit 4 Configuration/Control Register3

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

92 Revision 1.0

Interna l I/O Register Space Mapping for PTP Trigger Output (1 2 Units, 0x200

−

0x3FF) (Continued)

I/O Register Offset Location Register Name Default Value Description

16-Bit

8-Bit

0x28E - 0x28F 0x28E

0x28F TRIG4_CFG_4 0x0000 Trigger Output Unit 4 Configuration/Control Register4

0x290 - 0x291 0x290

0x291 TRIG4_CFG_5 0x0000 Trigger Output Unit 4 Configuration/Control Register5

0x292 - 0x293 0x292

0x293 TRIG4_CFG_6 0x0000 Trigger Output Unit 4 Configuration/Control Register6

0x294 - 0x295 0x294

0x295 TRIG4_CFG_7 0x0000 Trigger Output Unit 4 Configuration/Control Register7

0x296 - 0x297 0x296

0x297 TRIG4_CFG_8 0x0000 Trigger Output Unit 4 Configuration/Control Register8

0x298 – 0x29F 0x298

0x29F Reserved

(8-Bytes) Don’t Care None

0x2A0 - 0x2A1 0x2A0

0x2A1 TRIG5_TGT_NSL 0x0000 Trigger Output Unit 5 Target Time in Nanoseconds

Low-Word Register [15:0]

0x2A2 - 0x2A3 0x2A2

0x2A3 TRIG5_TGT_NSH 0x0000 Trigger Output Unit 5 Target Time in Nanoseconds

High-Word Register [29:16]

0x2A4 - 0x2A5 0x2A4

0x2A5 TRIG5_TGT_SL 0x0000 Trigger Output Unit 5 Target Time in Seconds Low-

Word Register [15:0]

0x2A6 - 0x2A7 0x2A6

0x2A7 TRIG5_TGT_SH 0x0000 Trigger Output Unit 5 Target Time in Seconds High-

Word Register [31:16]

0x2A8 - 0x2A9 0x2A8

0x2A9 TRIG5_CFG_1 0x3C00 Trigger Output Unit 5 Configuration/Control Register1

0x2AA - 0x2AB 0x2AA

0x2AB TRIG5_CFG_2 0x0000 Trigger Output Unit 5 Configuration/Control Register2

0x2AC - 0x2AD 0x2AC

0x2AD TRIG5_CFG_3 0x0000 Trigger Output Unit 5 Configuration/Control Register3

0x2AE - 0x2AF 0x2AE

0x2AF TRIG5_CFG_4 0x0000 Trigger Output Unit 5 Configuration/Control Register4

0x2B0 - 0x2B1 0x2B0

0x2B1 TRIG5_CFG_5 0x0000 Trigger Output Unit 5 Configuration/Control Register5

0x2B2 - 0x2B3 0x2B2

0x2B3 TRIG5_CFG_6 0x0000 Trigger Output Unit 5 Configuration/Control Register6

0x2B4 - 0x2B5 0x2B4

0x2B5 TRIG5_CFG_7 0x0000 Trigger Output Unit 5 Configuration/Control Register7

0x2B6 - 0x2B7 0x2B6

0x2B7 TRIG5_CFG_8 0x0000 Trigger Output Unit 5 Configuration/Control Register8

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

93 Revision 1.0

Interna l I/O Register Space Mapping for PTP Trigger Output (1 2 Units, 0x200

−

0x3FF) (Continued)

I/O Register Offset Location Register Name Default Value Description

16-Bit

8-Bit

0x2B8 – 0x2BF 0x2B8

0x2BF Reserved

(8-Bytes) Don’t Care None

0x2C0 - 0x2C1 0x2C0

0x2C1 TRIG6_TGT_NSL 0x0000 Trigger Output Unit 6 Target Time in Nanoseconds

Low-Word Register [15:0]

0x2C2 - 0x2C3 0x2C2

0x2C3 TRIG6_TGT_NSH 0x0000 Trigger Output Unit 6 Target Time in Nanoseconds

High-Word Register [29:16]

0x2C4 - 0x2C5 0x2C4

0x2C5 TRIG6_TGT_SL 0x0000 Trigger Output Unit 6 Target Time in Seconds Low-

Word Register [15:0]

0x2C6 - 0x2C7 0x2C6

0x2C7 TRIG6_TGT_SH 0x0000 Trigger Output Unit 6 Target Time in Seconds High-

Word Register [31:16]

0x2C8 - 0x2C9 0x2C8

0x2C9 TRIG6_CFG_1 0x3C00 Trigger Output Unit 6 Configuration/Control Register1

0x2CA - 0x2CB 0x2CA

0x2CB TRIG6_CFG_2 0x0000 Trigger Output Unit 6 Configuration/Control Register2

0x2CC - 0x2CD 0x2CC

0x2CD TRIG6_CFG_3 0x0000 Trigger Output Unit 6 Configuration/Control Register3

0x2CE - 0x2CF 0x2CE

0x2CF TRIG6_CFG_4 0x0000 Trigger Output Unit 6 Configuration/Control Register4

0x2D0 - 0x2D1 0x2D0

0x2D1 TRIG6_CFG_5 0x0000 Trigger Output Unit 6 Configuration/Control Register5

0x2D2 - 0x2D3 0x2D2

0x2D3 TRIG6_CFG_6 0x0000 Trigger Output Unit 6 Configuration/Control Register6

0x2D4 - 0x2D5 0x2D4

0x2D5 TRIG6_CFG_7 0x0000 Trigger Output Unit 6 Configuration/Control Register7

0x2D6 - 0x2D7 0x2D6

0x2D7 TRIG6_CFG_8 0x0000 Trigger Output Unit 6 Configuration/Control Register8

0x2D8 – 0x2DF 0x2D8

0x2DF Reserved

(8-Bytes) Don’t Care None

0x2E0 - 0x2E1 0x2E0

0x2E1 TRIG7_TGT_NSL 0x0000 Trigger Output Unit 7 Target Time in Nanoseconds

Low-Word Register [15:0]

0x2E2 - 0x2E3 0x2E2

0x2E3 TRIG7_TGT_NSH 0x0000 Trigger Output Unit 7 Target Time in Nanoseconds

High-Word Register [29:16]

0x2E4 - 0x2E5 0x2E4

0x2E5 TRIG7_TGT_SL 0x0000 Trigger Output Unit 7 Target Time in Seconds Low-

Word Register [15:0]

0x2E6 - 0x2E7 0x2E6

0x2E7 TRIG7_TGT_SH 0x0000 Trigger Output Unit 7 Target Time in Seconds High-

Word Register [31:16]

0x2E8 - 0x2E9 0x2E8

0x2E9 TRIG7_CFG_1 0x3C00 Trigger Output Unit 7 Configuration/Control Register1

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

94 Revision 1.0

Interna l I/O Register Space Mapping for PTP Trigger Output (1 2 Units, 0x200

−

0x3FF) (Continued)

I/O Register Offset Location Register Name Default Value Description

16-Bit

8-Bit

0x2EA - 0x2EB 0x2EA

0x2EB TRIG7_CFG_2 0x0000 Trigger Output Unit 7 Configuration/Control Register2

0x2EC - 0x2ED 0x2EC

0x2ED TRIG7_CFG_3 0x0000 Trigger Output Unit 7 Configuration/Control Register3

0x2EE - 0x2EF 0x2EE

0x2EF TRIG7_CFG_4 0x0000 Trigger Output Unit 7 Configuration/Control Register4

0x2F0 - 0x2F1 0x2F0

0x2F1 TRIG7_CFG_5 0x0000 Trigger Output Unit 7 Configuration/Control Register5

0x2F2 - 0x2F3 0x2F2

0x2F3 TRIG7_CFG_6 0x0000 Trigger Output Unit 7 Configuration/Control Register6

0x2F4 - 0x2F5 0x2F4

0x2F5 TRIG7_CFG_7 0x0000 Trigger Output Unit 7 Configuration/Control Register7

0x2F6 - 0x2F7 0x2F6

0x2F7 TRIG7_CFG_8 0x0000 Trigger Output Unit 7 Configuration/Control Register8

0x2F8 – 0x2FF 0x2F8

0x2FF Reserved

(8-Bytes) Don’t Care None

0x300 - 0x301 0x300

0x301 TRIG8_TGT_NSL 0x0000 Trigger Output Unit 8 Target Time in Nanoseconds

Low-Word Register [15:0]

0x302 - 0x303 0x302

0x303 TRIG8_TGT_NSH 0x0000 Trigger Output Unit 8 Target Time in Nanoseconds

High-Word Register [29:16]

0x304 - 0x305 0x304

0x305 TRIG8_TGT_SL 0x0000 Trigger Output Unit 8 Target Time in Seconds Low-

Word Register [15:0]

0x306 - 0x307 0x306

0x307 TRIG8_TGT_SH 0x0000 Trigger Output Unit 8 Target Time in Seconds High-

Word Register [31:16]

0x308 - 0x309 0x308

0x309 TRIG8_CFG_1 0x3C00 Trigger Output Unit 8 Configuration/Control Register1

0x30A - 0x30B 0x30A

0x30B TRIG8_CFG_2 0x0000 Trigger Output Unit 8 Configuration/Control Register2

0x30C - 0x30D 0x30C

0x30D TRIG8_CFG_3 0x0000 Trigger Output Unit 8 Configuration/Control Register3

0x30E - 0x30F 0x30E

0x30F TRIG8_CFG_4 0x0000 Trigger Output Unit 8 Configuration/Control Register4

0x310 - 0x311 0x310

0x311 TRIG8_CFG_5 0x0000 Trigger Output Unit 8 Configuration/Control Register5

0x312 - 0x313 0x312

0x313 TRIG8_CFG_6 0x0000 Trigger Output Unit 8 Configuration/Control Register6

0x314 - 0x315 0x314

0x315 TRIG8_CFG_7 0x0000 Trigger Output Unit 8 Configuration/Control Register7

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

95 Revision 1.0

Interna l I/O Register Space Mapping for PTP Trigger Output (1 2 Units, 0x200

−

0x3FF) (Continued)

I/O Register Offset Location Register Name Default Value Description

16-Bit

8-Bit

0x316 - 0x317 0x316

0x317 TRIG8_CFG_8 0x0000 Trigger Output Unit 8 Configuration/Control Register8

0x318 – 0x31F 0x318

0x31F Reserved

(8-Bytes) Don’t Care None

0x320 - 0x321 0x320

0x321 TRIG9_TGT_NSL 0x0000 Trigger Output Unit 9 Target Time in Nanoseconds

Low-Word Register [15:0]

0x322 - 0x323 0x322

0x323 TRIG9_TGT_NSH 0x0000 Trigger Output Unit 9 Target Time in Nanoseconds

High-Word Register [29:16]

0x324 - 0x325 0x324

0x325 TRIG9_TGT_SL 0x0000 Trigger Output Unit 9 Target Time in Seconds Low-

Word Register [15:0]

0x326 - 0x327 0x326

0x327 TRIG9_TGT_SH 0x0000 Trigger Output Unit 9 Target Time in Seconds High-

Word Register [31:16]

0x328 - 0x329 0x328

0x329 TRIG9_CFG_1 0x3C00 Trigger Output Unit 9 Configuration/Control Register1

0x32A - 0x32B 0x32A

0x32B TRIG9_CFG_2 0x0000 Trigger Output Unit 9 Configuration/Control Register2

0x32C - 0x32D 0x32C

0x32D TRIG9_CFG_3 0x0000 Trigger Output Unit 9 Configuration/Control Register3

0x32E - 0x32F 0x32E

0x32F TRIG9_CFG_4 0x0000 Trigger Output Unit 9 Configuration/Control Register4

0x330 - 0x331 0x330

0x331 TRIG9_CFG_5 0x0000 Trigger Output Unit 9 Configuration/Control Register5

0x332 - 0x333 0x332

0x333 TRIG9_CFG_6 0x0000 Trigger Output Unit 9 Configuration/Control Register6

0x334 - 0x335 0x334

0x335 TRIG9_CFG_7 0x0000 Trigger Output Unit 9 Configuration/Control Register7

0x336 - 0x337 0x336

0x337 TRIG9_CFG_8 0x0000 Trigger Output Unit 9 Configuration/Control Register8

0x338 – 0x33F 0x338

0x33F Reserved

(8-Bytes) Don’t Care None

0x340 - 0x341 0x340

0x341 TRIG10_TGT_NSL 0x0000 Trigger Output Unit 10 Target Time in Nanoseconds

Low-Word Register [15:0]

0x342 - 0x343 0x342

0x343 TRIG10_TGT_NSH 0x0000 Trigger Output Unit 10 Target Time in Nanoseconds

High-Word Register [29:16]

0x344 - 0x345 0x344

0x345 TRIG10_TGT_SL 0x0000 Trigger Output Unit 10 Target Time in Seconds Low-

Word Register [15:0]

0x346 - 0x347 0x346

0x347 TRIG10_TGT_SH 0x0000 Trigger Output Unit 10 Target Time in Seconds High-

Word Register [31:16]

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

96 Revision 1.0

Interna l I/O Register Space Mapping for PTP Trigger Output (1 2 Units, 0x200

−

0x3FF) (Continued)

I/O Register Offset Location Register Name Default Value Description

16-Bit

8-Bit

0x348 - 0x349 0x348

0x349 TRIG10_CFG_1 0x3C00 Trigger Output Unit 10 Configuration/Control

Register1

0x34A - 0x34B 0x34A

0x34B TRIG10_CFG_2 0x0000 Trigger Output Unit 10 Configuration/Control

Register2

0x34C - 0x34D 0x34C

0x34D TRIG10_CFG_3 0x0000 Trigger Output Unit 10 Configuration/Control

Register3

0x34E - 0x34F 0x34E

0x34F TRIG10_CFG_4 0x0000 Trigger Output Unit 10 Configuration/Control

Register4

0x350 - 0x351 0x350

0x351 TRIG10_CFG_5 0x0000 Trigger Output Unit 10 Configuration/Control

Register5

0x352 - 0x353 0x352

0x353 TRIG10_CFG_6 0x0000 Trigger Output Unit 10 Configuration/Control

Register6

0x354 - 0x355 0x354

0x355 TRIG10_CFG_7 0x0000 Trigger Output Unit 10 Configuration/Control

Register7

0x356 - 0x357 0x356

0x357 TRIG10_CFG_8 0x0000 Trigger Output Unit 10 Configuration/Control

Register8

0x358 – 0x35F 0x358

0x35F Reserved

(8-Bytes) Don’t Care None

0x360 - 0x361 0x360

0x361 TRIG11_TGT_NSL 0x0000 Trigger Output Unit 11 Target Time in Nanoseconds

Low-Word Register [15:0]

0x362 - 0x363 0x362

0x363 TRIG11_TGT_NSH 0x0000 Trigger Output Unit 11 Target Time in Nanoseconds

High-Word Register [29:16]

0x364 - 0x365 0x364

0x365 TRIG11_TGT_SL 0x0000 Trigger Output Unit 11 Target Time in Seconds Low-

Word Register [15:0]

0x366 - 0x367 0x366

0x367 TRIG11_TGT_SH 0x0000 Trigger Output Unit 11 Target Time in Seconds High-

Word Register [31:16]

0x368 - 0x369 0x368

0x369 TRIG11_CFG_1 0x3C00 Trigger Output Unit 11 Configuration/Control

Register1

0x36A - 0x36B 0x36A

0x36B TRIG11_CFG_2 0x0000 Trigger Output Unit 11 Configuration/Control

Register2

0x36C - 0x36D 0x36C

0x36D TRIG11_CFG_3 0x0000 Trigger Output Unit 11 Configuration/Control

Register3

0x36E - 0x36F 0x36E

0x36F TRIG11_CFG_4 0x0000 Trigger Output Unit 11 Configuration/Control

Register4

0x370 - 0x371 0x370

0x371 TRIG11_CFG_5 0x0000 Trigger Output Unit 11 Configuration/Control

Register5

0x372 - 0x373 0x372

0x373 TRIG11_CFG_6 0x0000 Trigger Output Unit 11 Configuration/Control

Register6

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

97 Revision 1.0

Interna l I/O Register Space Mapping for PTP Trigger Output (1 2 Units, 0x200

−

0x3FF) (Continued)

I/O Register Offset Location Register Name Default Value Description

16-Bit

8-Bit

0x374 - 0x375 0x374

0x375 TRIG11_CFG_7 0x0000 Trigger Output Unit 11 Configuration/Control

Register7

0x376 - 0x377 0x376

0x377 TRIG11_CFG_8 0x0000 Trigger Output Unit 11 Configuration/Control

Register8

0x378 – 0x37F 0x378

0x37F Reserved

(8-Bytes) Don’t Care None

0x380 - 0x381 0x380

0x381 TRIG12_TGT_NSL 0x0000 Trigger Output Unit 12 Target Time in Nanoseconds

Low-Word Register [15:0]

0x382 - 0x383 0x382

0x383 TRIG12_TGT_NSH 0x0000 Trigger Output Unit 12 Target Time in Nanoseconds

High-Word Register [29:16]

0x384 - 0x385 0x384

0x385 TRIG12_TGT_SL 0x0000 Trigger Output Unit 12 Target Time in Seconds Low-

Word Register [15:0]

0x386 - 0x387 0x386

0x387 TRIG12_TGT_SH 0x0000 Trigger Output Unit 12 Target Time in Seconds High-

Word Register [31:16]

0x388 - 0x389 0x388

0x389 TRIG12_CFG_1 0x3C00 Trigger Output Unit 12 Configuration/Control

Register1

0x38A - 0x38B 0x38A

0x38B TRIG12_CFG_2 0x0000 Trigger Output Unit 12 Configuration/Control

Register2

0x38C - 0x38D 0x38C

0x38D TRIG12_CFG_3 0x0000 Trigger Output Unit 12 Configuration/Control

Register3

0x38E - 0x38F 0x38E

0x38F TRIG12_CFG_4 0x0000 Trigger Output Unit 12 Configuration/Control

Register4

0x390 - 0x391 0x390

0x391 TRIG12_CFG_5 0x0000 Trigger Output Unit 12 Configuration/Control

Register5

0x392 - 0x393 0x392

0x393 TRIG12_CFG_6 0x0000 Trigger Output Unit 12 Configuration/Control

Register6

0x394 - 0x395 0x394

0x395 TRIG12_CFG_7 0x0000 Trigger Output Unit 12 Configuration/Control

Register7

0x396 - 0x397 0x396

0x397 TRIG12_CFG_8 0x0000 Trigger Output Unit 12 Configuration/Control

Register8

0x398 – 0x3FF 0x398

0x3FF Reserved

(104-Bytes) Don’t Care None

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

98 Revision 1.0

Internal I/O Register Space Mapping for PTP Timestamp Inputs (12 Units, 0x400 – 0x5FF)

I/O Register Offset Location Register Name Default Value Description

16-Bit 8-Bit

0x400 - 0x401 0x400

0x401 TS_RDY 0x0000 Input Unit Ready Register [11:0]

0x402 - 0x403 0x402

0x403 TS_EN 0x0000 Timestamp Input Unit E nab le Regist er [11:0]

0x404 - 0x405 0x404

0x405 TS_SW_RST 0x0000 Timestamp Input Unit Software Reset Register

[11:0]

0x406 – 0x41F 0x406

0x41F Reserved

(26-Bytes) Don’t Care None

0x420 – 0x421 0x420

0x421 TS1_STATUS 0x0000 Timestamp Input Unit 1 Status Register

0x422 – 0x423 0x422

0x423 TS1_CFG 0x0000 Timestamp Input Unit 1 Configuration/Control

0x424 – 0x425 0x424

0x425 TS1_SMPL1_NSL 0x0000 Timestamp Unit 1 Input Sample Time (1st) in

Nanoseconds Low-Word Register [15:0]

0x426 – 0x427 0x426

0x427 TS1_SMPL1_NSH 0x0000 Timestamp Unit 1 Input Sample Time (1st) in

Nanoseconds High-Word Register [29:16]

0x428 – 0x429 0x428

0x429 TS1_SMPL1_SL 0x0000 Timestamp Unit 1 Input Sample Time (1st) in

Seconds Low -Word Register [15:0]

0x42A – 0x42B 0x42A

0x42B TS1_SMPL1_SH 0x0000 Timestamp Unit 1 Input Sample Time (1st) in

Seconds High-Word Register [31:16]

0x42C – 0x42D 0x42C

0x42D TS1_SMPL1_SUB_NS 0x0000 Timestamp Unit 1 Input Sample Time (1st) in Sub-

Nanoseconds R egi ster [2:0]

0x42E – 0x433 0x42E

0x433 Reserved

(6-Bytes) Don’t Care None

0x434 – 0x435 0x434

0x435 TS1_SMPL2_NSL 0x0000 Timestamp Unit 1 Input Sample Time (2nd) in

Nanoseconds Low-Word Register [15:0]

0x436 – 0x437 0x436

0x437 TS1_SMPL2_NSH 0x0000 Timestamp Unit 1 Input Sample Time (2nd) in

Nanoseconds High-Word Register [29:16]

0x438 – 0x439 0x438

0x439 TS1_SMPL2_SL 0x0000 Timestamp Unit 1 Input Sample Time (2nd) in

Seconds Low -Word Register [15:0]

0x43A – 0x43B 0x43A

0x43B TS1_SMPL2_SH 0x0000 Timestamp Unit 1 Input Sample Time (2nd) in

Seconds High-Word Register [31:16]

0x43C – 0x43D 0x43C

0x43D TS1_SMPL2_SUB_NS 0x0000 Timestamp Unit 1 Input Sample Time (2nd) in Sub-

Nanoseconds R egi ster [2:0]

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

99 Revision 1.0

Interna l I/O Register Space Mapping for PTP Timestamp Inputs (12 Units, 0x400 – 0x5FF) (Continued)

I/O Register Offset Location Register Name Default Value Description

16-Bit 8-Bit

0x43E – 0x43F 0x43E

0x43F Reserved

(2-Bytes) Don’t Care None

0x440 – 0x441 0x440

0x441 TS2_STATUS 0x0000 Timestamp Input Unit 2 Status Register

0x442 – 0x443 0x442

0x443 TS2_CFG 0x0000 Timestamp Input Unit 2 Configuration/Control

0x444 – 0x445 0x444

0x445 TS2_SMPL1_NSL 0x0000 Timestamp Unit 2 Input Sample Time (1st) in

Nanoseconds Low-Word Register [15:0]

0x446 – 0x447 0x446

0x447 TS2_SMPL1_NSH 0x0000 Timestamp Unit 2 Input Sample Time (1st) in

Nanoseconds High-Word Register [29:16]

0x448 – 0x449 0x448

0x449 TS2_SMPL1_SL 0x0000 Timestamp Unit 2 Input Sample Time (1st) in

Seconds Low -Word Register [15:0]

0x44A – 0x44B 0x44A

0x44B TS2_SMPL1_SH 0x0000 Timestamp Unit 2 Input Sample Time (1st) in

Seconds High-Word Register [31:16]

0x44C – 0x44D 0x44C

0x44D TS2_SMPL1_SUB_NS 0x0000 Timestamp Unit 2 Input Sample Time (1st) in Sub-

Nanoseconds R egi ster [2:0]

0x44E – 0x453 0x44E

0x453 Reserved

(6-Bytes) Don’t Care None

0x454 – 0x455 0x454

0x455 TS2_SMPL2_NSL 0x0000 Timestamp Unit 2 Input Sample Time (2nd) in

Nanoseconds Low-Word Register [15:0]

0x456 – 0x457 0x456

0x457 TS2_SMPL2_NSH 0x0000 Timestamp Unit 2 Input Sample Time (2nd) in

Nanoseconds High-Word Register [29:16]

0x458 – 0x459 0x458

0x459 TS2_SMP2_SL 0x0000 Timestamp Unit 2 Input Sample Time (2nd) in

Seconds Low -Word Register [15:0]

0x45A – 0x45B 0x45A

0x45B TS2_SMPL2_SH 0x0000 Timestamp Unit 2 Input Sample Time (2nd) in

Seconds High-Word Register [31:16]

0x45C – 0x45D 0x45C

0x45D TS2_SMPL2_SUB_NS 0x0000 Timestamp Unit 2 Input Sample Time (2nd) in Sub-

Nanoseconds R egi ster [2:0]

0x45E – 0x45F 0x45E

0x45F Reserved

(2-Bytes) Don’t Care None

0x460 – 0x461 0x460

0x461 TS3_STATUS 0x0000 Timestamp Input Unit 3 Status Register

0x462 – 0x463 0x462

0x463 TS3_CFG 0x0000 Timestamp Input Unit 3 Configuration/Control

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

100 Revision 1.0

Interna l I/O Register Space Mapping for PTP Timestamp Inputs (12 Units, 0x400 – 0x5FF) (Continued)

I/O Register Offset Location Register Name Default Value Description

16-Bit 8-Bit

0x464 – 0x465 0x464

0x465 TS3_SMPL1_NSL 0x0000 Timestamp Unit 3 Input Sample Time (1st) in

Nanoseconds Low-Word Register [15:0]

0x466 – 0x467 0x466

0x467 TS3_SMPL1_NSH 0x0000 Timestamp Unit 3 Input Sample Time (1st) in

Nanoseconds High-Word Register [29:16]

0x468 – 0x469 0x468

0x469 TS3_SMPL1_SL 0x0000 Timestamp Unit 3 Input Sample Time (1st) in

Seconds Low-Word Register [15:0]

0x46A – 0x46B 0x46A

0x46B TS3_SMPL1_SH 0x0000 Timestamp Unit 3 Input Sample Time (1st) in

Seconds High-Word Register [31:16]

0x46C – 0x46D 0x46C

0x46D TS3_SMPL1_SUB_NS 0x0000 Timestamp Unit 3 Input Sample Time (1st) in Sub-

Nanoseconds R egi ster [2:0]

0x46E – 0x473 0x46E

0x473 Reserved

(6-Bytes) Don’t Care None

0x474 – 0x475 0x474

0x475 TS3_SMPL2_NSL 0x0000 Timestamp Unit 3 Input Sample Time (2nd) in

Nanoseconds Low-Word Register [15:0]

0x476 – 0x477 0x476

0x477 TS3_SMPL2_NSH 0x0000 Timestamp Unit 3 Input Sample Time (2nd) in

Nanoseconds High-Word Register [29:16]

0x478 – 0x479 0x478

0x479 TS3_SMP2_SL 0x0000 Timestamp Unit 3 Input Sample Time (2nd) in

Seconds Low-Word Register [15:0]

0x47A – 0x47B 0x47A

0x47B TS3_SMPL2_SH 0x0000 Timestamp Unit 3 Input Sample Time (2nd) in

Seconds High-Word Register [31:16]

0x47C – 0x47D 0x47C

0x47D TS3_SMPL2_SUB_NS 0x0000 Timestamp Unit 3 Input Sample Time (2nd) in Sub-

Nanoseconds R egi ster [2:0]

0x47E – 0x47F 0x47E

0x47F Reserved

(2-Bytes) Don’t Care None

0x480 – 0x481 0x480

0x481 TS4_STATUS 0x0000 Timestamp Input Unit 4 Status Register

0x482 – 0x483 0x482

0x483 TS4_CFG 0x0000 Timestamp Input Unit 4 Configuration/Control

0x484 – 0x485 0x484

0x485 TS4_SMPL1_NSL 0x0000 Timestamp Unit 4 Input Sample Time (1st) in

Nanoseconds Low-Word Register [15:0]

0x486 – 0x487 0x486

0x487 TS4_SMPL1_NSH 0x0000 Timestamp Unit 4 Input Sample Time (1st) in

Nanoseconds High-Word Register [29:16]

0x488 – 0x489 0x488

0x489 TS4_SMPL1_SL 0x0000 Timestamp Unit 4 Input Sample Time (1st) in

Seconds Low-Word Register [15:0]

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

101 Revision 1.0

Interna l I/O Register Space Mapping for PTP Timestamp Inputs (12 Units, 0x400 – 0x5FF) (Continued)

I/O Register Offset Location Register Name Default Value Description

16-Bit 8-Bit

0x48A – 0x48B 0x48A

0x48B TS4_SMPL1_SH 0x0000 Timestamp Unit 4 Input Sample Time (1st) in

Seconds High-Word Register [31:16]

0x48C – 0x48D 0x48C

0x48D TS4_SMPL1_SUB_NS 0x0000 Timestamp Unit 4 Input Sample Time (1st) in Sub-

Nanoseconds R egi ster [2:0]

0x48E – 0x493 0x48E

0x493 Reserved

(6-Bytes) Don’t Care None

0x494 – 0x495 0x494

0x495 TS4_SMPL2_NSL 0x0000 Timestamp Unit 4 Input Sample Time (2nd) in

Nanoseconds Low-Word Register [15:0]

0x496 – 0x497 0x496

0x497 TS4_SMPL2_NSH 0x0000 Timestamp Unit 4 Input Sample Time (2nd) in

Nanoseconds High-Word Register [29:16]

0x498 – 0x499 0x498

0x499 TS4_SMP2_SL 0x0000 Timestamp Unit 4 Input Sample Time (2nd) in

Seconds Low-Word Register [15:0]

0x49A – 0x49B 0x49A

0x49B TS4_SMPL2_SH 0x0000 Timestamp Unit 4 Input Sample Time (2nd) in

Seconds High-Word Register [31:16]

0x49C – 0x49D 0x49C

0x49D TS4_SMPL2_SUB_NS 0x0000 Timestamp Unit 4 Input Sample Time (2nd) in Sub-

Nanoseconds R egi ster [2:0]

0x49E – 0x49F 0x49E

0x49F Reserved

(2-Bytes) Don’t Care None

0x4A0 – 0x4A1 0x4A0

0x4A1 TS5_STATUS 0x0000 Timestamp Input Unit 5 Status Register

0x4A2 – 0x4A3 0x4A2

0x4A3 TS5_CFG 0x0000 Timestamp Input Unit 5 Configuration/Control

0x4A4 – 0x4A5 0x4A4

0x4A5 TS5_SMPL1_NSL 0x0000 Timestamp Unit 5 Input Sample Time (1st) in

Nanoseconds Low-Word Register [15:0]

0x4A6 – 0x4A7 0x4A6

0x4A7 TS5_SMPL1_NSH 0x0000 Timestamp Unit 5 Input Sample Time (1st) in

Nanoseconds High-Word Register [29:16]

0x4A8 – 0x4A9 0x4A8

0x4A9 TS5_SMPL1_SL 0x0000 Timestamp Unit 5 Input Sample Time (1st) in

Seconds Low-Word Register [15:0]

0x4AA – 0x4AB 0x4AA

0x4AB TS5_SMPL1_SH 0x0000 Timestamp Unit 5 Input Sample Time (1st) in

Seconds High-Word Register [31:16]

0x4AC – 0x4AD 0x4AC

0x4AD TS5_SMPL1_SUB_NS 0x0000 Timestamp Unit 5 Input Sample Time (1st) in Sub-

Nanoseconds R egi ster [2:0]

0x4AE – 0x4B3 0x4AE

0x4B3 Reserved

(6-Bytes) Don’t Care None

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

102 Revision 1.0

Interna l I/O Register Space Mapping for PTP Timestamp Inputs (12 Units, 0x400 – 0x5FF) (Continued)

I/O Register Offset Location Register Name Default Value Description

16-Bit 8-Bit

0x4B4 – 0x4B5 0x4B4

0x4B5 TS5_SMPL2_NSL 0x0000 Timestamp Unit 5 Input Sample Time (2nd) in

Nanoseconds Low-Word Register [15:0]

0x4B6 – 0x4B7 0x4B6

0x4B7 TS5_SMPL2_NSH 0x0000 Timestamp Unit 5 Input Sample Time (2nd) in

Nanoseconds High-Word Register [29:16]

0x4B8 – 0x4B9 0x4B8

0x4B9 TS5_SMP2_SL 0x0000 Timestamp Unit 5 Input Sample Time (2nd) in

Seconds Low-Word Register [15:0]

0x4BA – 0x4BB 0x4BA

0x4BB TS5_SMPL2_SH 0x0000 Timestamp Unit 5 Input Sample Time (2nd) in

Seconds High-Word Register [31:16]

0x4BC – 0x4BD 0x4BC

0x4BD TS5_SMPL2_SUB_NS 0x0000 Timestamp Unit 5 Input Sample Time (2nd) in Sub-

Nanoseconds R egi ster [2:0]

0x4BE – 0x4BF 0x4BE

0x4BF Reserved

(2-Bytes) Don’t Care None

0x4C0 – 0x4C1 0x4C0

0x4C1 TS6_STATUS 0x0000 Timestamp Input Unit 6 Status Register

0x4C2 – 0x4C3 0x4C2

0x4C3 TS6_CFG 0x0000 Timestamp Input Unit 6 Configuration/Control

0x4C4 – 0x4C5 0x4C4

0x4C5 TS6_SMPL1_NSL 0x0000 Timestamp Unit 6 Input Sample Time (1st) in

Nanoseconds Low-Word Register [15:0]

0x4C6 – 0x4C7 0x4C6

0x4C7 TS6_SMPL1_NSH 0x0000 Timestamp Unit 6 Input Sample Time (1st) in

Nanoseconds High-Word Register [29:16]

0x4C8 – 0x4C9 0x4C8

0x4C9 TS6_SMPL1_SL 0x0000 Timestamp Unit 6 Input Sample Time (1st) in

Seconds Low-Word Register [15:0]

0x4CA – 0x4CB 0x4CA

0x4CB TS6_SMPL1_SH 0x0000 Timestamp Unit 6 Input Sample Time (1st) in

Seconds High-Word Register [31:16]

0x4CC – 0x4CD 0x4CC

0x4CD TS6_SMPL1_SUB_NS 0x0000 Timestamp Unit 6 Input Sample Time (1st) in Sub-

Nanoseconds R egi ster [2:0]

0x4CE – 0x4D3 0x4CE

0x4D3 Reserved

(6-Bytes) Don’t Care None

0x4D4 – 0x4D5 0x4D4

0x4D5 TS6_SMPL2_NSL 0x0000 Timestamp Unit 6 Input Sample Time (2nd) in

Nanoseconds Low-Word Register [15:0]

0x4D6 – 0x4D7 0x4D6

0x4D7 TS6_SMPL2_NSH 0x0000 Timestamp Unit 6 Input Sample Time (2nd) in

Nanoseconds High-Word Register [29:16]

0x4D8 – 0x4D9 0x4D8

0x4D9 TS6_SMP2_SL 0x0000 Timestamp Unit 6 Input Sample Time (2nd) in

Seconds Low-Word Register [15:0]

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

103 Revision 1.0

Interna l I/O Register Space Mapping for PTP Timestamp Inputs (12 Units, 0x400 – 0x5FF) (Continued)

I/O Register Offset Location Register Name Default Value Description

16-Bit 8-Bit

0x4DA – 0x4DB 0x4DA

0x4DB TS6_SMPL2_SH 0x0000 Timestamp Unit 6 Input Sample Time (2nd) in

Seconds High-Word Register [31:16]

0x4DC – 0x4DD 0x4DC

0x4DD TS6_SMPL2_SUB_NS 0x0000 Timestamp Unit 6 Input Sample Time (2nd) in Sub-

Nanoseconds R egi ster [2:0]

0x4DE – 0x4DF 0x4DE

0x4DF Reserved

(2-Bytes) Don’t Care None

0x4E0 – 0x4E1 0x4E0

0x4E1 TS7_STATUS 0x0000 Timestamp Input Unit 7 Status Register

0x4E2 – 0x4E3 0x4E2

0x4E3 TS7_CFG 0x0000 Timestamp Input Unit 7 Configuration/Control

0x4E4 – 0x4E5 0x4E4

0x4E5 TS7_SMPL1_NSL 0x0000 Timestamp Unit 7 Input Sample Time (1st) in

Nanoseconds Low-Word Register [15:0]

0x4E6 – 0x4E7 0x4E6

0x4E7 TS7_SMPL1_NSH 0x0000 Timestamp Unit 7 Input Sample Time (1st) in

Nanoseconds High-Word Register [29:16]

0x4E8 – 0x4E9 0x4E8

0x4E9 TS7_SMPL1_SL 0x0000 Timestamp Unit 7 Input Sample Time (1st) in

Seconds Low-Word Register [15:0]

0x4EA – 0x4EB 0x4EA

0x4EB TS7_SMPL1_SH 0x0000 Timestamp Unit 7 Input Sample Time (1st) in

Seconds High-Word Register [31:16]

0x4EC – 0x4ED 0x4EC

0x4ED TS7_SMPL1_SUB_NS 0x0000 Timestamp Unit 7 Input Sample Time (1st) in Sub-

Nanoseconds R egi ster [2:0]

0x4EE – 0x4F3 0x4EE

0x4F3 Reserved

(6-Bytes) Don’t Care None

0x4F4 – 0x4F5 0x4F4

0x4F5 TS7_SMPL2_NSL 0x0000 Timestamp Unit 7 Input Sample Time (2nd) in

Nanoseconds Low-Word Register [15:0]

0x4F6 – 0x4F7 0x4F6

0x4F7 TS7_SMPL2_NSH 0x0000 Timestamp Unit 7 Input Sample Time (2nd) in

Nanoseconds High-Word Register [29:16]

0x4F8 – 0x4F9 0x4F8

0x4F9 TS7_SMP2_SL 0x0000 Timestamp Unit 7 Input Sample Time (2nd) in

Seconds Low-Word Register [15:0]

0x4FA – 0x4FB 0x4FA

0x4FB TS7_SMPL2_SH 0x0000 Timestamp Unit 7 Input Sample Time (2nd) in

Seconds High-Word Register [31:16]

0x4FC – 0x4FD 0x4FC

0x4FD TS7_SMPL2_SUB_NS 0x0000 Timestamp Unit 7 Input Sample Time (2nd) in Sub-

Nanoseconds R egi ster [2:0]

0x4FE – 0x4FF 0x4FE

0x4FF Reserved

(2-Bytes) Don’t Care None

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

104 Revision 1.0

Interna l I/O Register Space Mapping for PTP Timestamp Inputs (12 Units, 0x400 – 0x5FF) (Continued)

I/O Register Offset Location Register Name Default Value Description

16-Bit 8-Bit

0x500 – 0x501 0x500

0x501 TS8_STATUS 0x0000 Timestamp Input Unit 8 Status Register

0x502 – 0x503 0x502

0x503 TS8_CFG 0x0000 Timestamp Input Unit 8 Configuration/Control

0x504 – 0x505 0x504

0x505 TS8_SMPL1_NSL 0x0000 Timestamp Unit 8 Input Sample Time (1st) in

Nanoseconds Low-Word Register [15:0]

0x506 – 0x507 0x506

0x507 TS8_SMPL1_NSH 0x0000 Timestamp Unit 8 Input Sample Time (1st) in

Nanoseconds High-Word Register [29:16]

0x508 – 0x509 0x508

0x509 TS8_SMPL1_SL 0x0000 Timestamp Unit 8 Input Sample Time (1st) in

Seconds Low-Word Register [15:0]

0x50A – 0x50B 0x50A

0x50B TS8_SMPL1_SH 0x0000 Timestamp Unit 8 Input Sample Time (1st) in

Seconds High-Word Register [31:16]

0x50C – 0x50D 0x50C

0x50D TS8_SMPL1_SUB_NS 0x0000 Timestamp Unit 8 Input Sample Time (1st) in Sub-

Nanoseconds R egi ster [2:0]

0x50E – 0x513 0x50E

0x513 Reserved

(6-Bytes) Don’t Care None

0x514 – 0x515 0x514

0x515 TS8_SMPL2_NSL 0x0000 Timestamp Unit 8 Input Sample Time (2nd) in

Nanoseconds Low-Word Register [15:0]

0x516 – 0x517 0x516

0x517 TS8_SMPL2_NSH 0x0000 Timestamp Unit 8 Input Sample Time (2nd) in

Nanoseconds High-Word Register [29:16]

0x518 – 0x519 0x518

0x519 TS8_SMP2_SL 0x0000 Timestamp Unit 8 Input Sample Time (2nd) in

Seconds Low-Word Register [15:0]

0x51A – 0x51B 0x51A

0x51B TS8_SMPL2_SH 0x0000 Timestamp Unit 8 Input Sample Time (2nd) in

Seconds High-Word Register [31:16]

0x51C – 0x51D 0x51C

0x51D TS8_SMPL2_SUB_NS 0x0000 Timestamp Unit 8 Input Sample Time (2nd) in Sub-

Nanoseconds R egi ster [2:0]

0x51E – 0x51F 0x51E

0x51F Reserved

(2-Bytes) Don’t Care None

0x520 – 0x521 0x520

0x521 TS9_STATUS 0x0000 Timestamp Input Unit 9 Status Register

0x522 – 0x523 0x522

0x523 TS9_CFG 0x0000 Timestamp Input Unit 9 Configuration/Control

0x524 – 0x525 0x524

0x525 TS9_SMPL1_NSL 0x0000 Timestamp Unit 9 Input Sample Time (1st) in

Nanoseconds High-Word Register [15:0]

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

105 Revision 1.0

Interna l I/O Register Space Mapping for PTP Timestamp Inputs (12 Units, 0x400 – 0x5FF) (Continued)

I/O Register Offset Location Register Name Defa u l t Value Description

16-Bit 8-Bit

0x526 – 0x527 0x526

0x527 TS9_SMPL1_NSH 0x0000 Timestamp Unit 9 Input Sample Time (1st) in

Nanoseconds High-Word Register [29:16]

0x528 – 0x529 0x528

0x529 TS9_SMPL1_SL 0x0000 Timestamp Unit 9 Input Sample Time (1st) in

Seconds High-Word Register [15:0]

0x52A – 0x52B 0x52A

0x52B TS9_SMPL1_SH 0x0000 Timestamp Unit 9 Input Sample Time (1st) in

Seconds High-Word Register [31:16]

0x52C – 0x52D 0x52C

0x52D TS9_SMPL1_SUB_NS 0x0000 Timestamp Unit 9 Input Sample Time (1st) in Sub-

Nanoseconds R egi ster [2:0]

0x52E – 0x533 0x52E

0x533 Reserved

(6-Bytes) Don’t Care None

0x534 – 0x535 0x534

0x535 TS9_SMPL2_NSL 0x0000 Timestamp Unit 9 Input Sample Time (2nd) in

Nanoseconds Low-Word Register [15:0]

0x536 – 0x537 0x536

0x537 TS9_SMPL2_NSH 0x0000 Timestamp Unit 9 Input Sample Time (2nd) in

Nanoseconds High-Word Register [29:16]

0x538 – 0x539 0x538

0x539 TS9_SMP2_SL 0x0000 Timestamp Unit 9 Input Sample Time (2nd) in

Seconds Low-Word Register [15:0]

0x53A – 0x53B 0x53A

0x53B TS9_SMPL2_SH 0x0000 Timestamp Unit 9 Input Sample Time (2nd) in

Seconds High-Word Register [31:16]

0x53C – 0x53D 0x53C

0x53D TS9_SMPL2_SUB_NS 0x0000 Timestamp Unit 9 Input Sample Time (2nd) in Sub-

Nanoseconds R egi ster [2:0]

0x53E – 0x53F 0x53E

0x53F Reserved

(2-Bytes) Don’t Care None

0x540 – 0x541 0x540

0x541 TS10_STATUS 0x0000 Timestamp Input Unit 10 Status Register

0x542 – 0x543 0x542

0x543 TS10_CFG 0x0000 Timestamp Input Unit 10 Configuration/Control

0x544 – 0x545 0x544

0x545 TS10_SMPL1_NSL 0x0000 Timestamp Unit 10 Input Sample Time (1st) in

Nanoseconds Low-Word Register [15:0]

0x546 – 0x547 0x546

0x547 TS10_SMPL1_NSH 0x0000 Timestamp Unit 10 Input Sample Time (1st) in

Nanoseconds High-Word Register [29:16]

0x548 – 0x549 0x548

0x549 TS10_SMPL1_SL 0x0000 Timestamp Unit 10 Input Sample Time (1st) in

Seconds Low-Word Register [15:0]

0x54A – 0x54B 0x54A

0x54B TS10_SMPL1_SH 0x0000 Timestamp Unit 10 Input Sample Time (1st) in

Seconds High-Word Register [31:16]

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

106 Revision 1.0

Interna l I/O Register Space Mapping for PTP Timestamp Inputs (12 Units, 0x400 – 0x5FF) (Continued)

I/O Register Offset Location Register Name Default Value Description

16-Bit 8-Bit

0x54C – 0x54D 0x54C

0x54D TS10_SMPL1_SUB_NS 0x0000 Timestamp Unit 10 Input Sample Time (1st) in Sub-

Nanoseconds R egi ster [2:0]

0x54E – 0x553 0x54E

0x553 Reserved

(6-Bytes) Don’t Care None

0x554 – 0x555 0x554

0x555 TS10_SMPL2_NSL 0x0000 Timestamp Unit 10 Input Sample Time (2nd) in

Nanoseconds Low-Word Register [15:0]

0x556 – 0x557 0x556

0x557 TS10_SMPL2_NSH 0x0000 Timestamp Unit 10 Input Sample Time (2nd) in

Nanoseconds High-Word Register [29:16]

0x558 – 0x559 0x558

0x559 TS10_SMP2_SL 0x0000 Timestamp Unit 10 Input Sample Time (2nd) in

Seconds Low-Word Register [15:0]

0x55A – 0x55B 0x55A

0x55B TS10_SMPL2_SH 0x0000 Timestamp Unit 10 Input Sample Time (2nd) in

Seconds High-Word Register [31:16]

0x55C – 0x55D 0x55C

0x55D TS10_SMPL2_SUB_NS 0x0000 Timestamp Unit 10 Input Sample Time (2nd) in Sub-

Nanoseconds R egi ster [2:0]

0x55E – 0x55F 0x55E

0x55F Reserved

(2-Bytes) Don’t Care None

0x560 – 0x561 0x560

0x561 TS11_STATUS 0x0000 Timestamp Input Unit 11 Status Register

0x562 – 0x563 0x562

0x563 TS11_CFG 0x0000 Timestamp Input Unit 11 Configuration/Control

0x564 – 0x565 0x564

0x565 TS11_SMPL1_NSL 0x0000 Timestamp Unit 11 Input Sample Time (1st) in

Nanoseconds Low-Word Register [15:0]

0x566 – 0x567 0x566

0x567 TS11_SMPL1_NSH 0x0000 Timestamp Unit 11 Input Sample Time (1st) in

Nanoseconds High-Word Register [29:16]

0x568 – 0x569 0x568

0x569 TS11_SMPL1_SL 0x0000 Timestamp Unit 11 Input Sample Time (1st) in

Seconds Low-Word Register [15:0]

0x56A – 0x56B 0x56A

0x56B TS11_SMPL1_SH 0x0000 Timestamp Unit 11 Input Sample Time (1st) in

Seconds High-Word Register [31:16]

0x56C – 0x56D 0x56C

0x56D TS11_SMPL1_SUB_NS 0x0000 Timestamp Unit 11 Input Sample Time (1st) in Sub-

Nanoseconds R egi ster [2:0]

0x56E – 0x573 0x56E

0x573 Reserved

(6-Bytes) Don’t Care None

0x574 – 0x575 0x574

0x575 TS11_SMPL2_NSL 0x0000 Timestamp Unit 11 Input Sample Time (2nd) in

Nanoseconds Low-Word Register [15:0]

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

107 Revision 1.0

Interna l I/O Register Space Mapping for PTP Timestamp Inputs (12 Units, 0x400 – 0x5FF) (Continued)

I/O Register Offset Location Register Name Default Value Description

16-Bit 8-Bit

0x576 – 0x577 0x576

0x577 TS11_SMPL2_NSH 0x0000 Timestamp Unit 11 Input Sample Time (2nd) in

Nanoseconds High-Word Register [29:16]

0x578 – 0x579 0x578

0x579 TS11_SMP2_SL 0x0000 Timestamp Unit 11 Input Sample Time (2nd) in

Seconds Low-Word Register [15:0]

0x57A – 0x57B 0x57A

0x57B TS11_SMPL2_SH 0x0000 Timestamp Unit 11 Input Sample Time (2nd) in

Seconds High-Word Register [31:16]

0x57C – 0x57D 0x57C

0x57D TS11_SMPL2_SUB_NS 0x0000 Timestamp Unit 11 Input Sample Time (2nd) in Sub-

Nanoseconds R egi ster [2:0]

0x57E – 0x57F 0x57E

0x57F Reserved

(2-Bytes) Don’t Care None

0x580 – 0x581 0x580

0x581 TS12_STATUS 0x0000 Timestamp Input Unit 12 Status Register

0x582 – 0x583 0x582

0x583 TS12_CFG 0x0000 Timestamp Input Unit 12 Configuration/Control

0x584 – 0x585 0x584

0x585 TS12_SMPL1_NSL 0x0000 Timestamp Unit 12 Input Sample Time (1st) in

Nanoseconds Low-Word Register [15:0]

0x586 – 0x587 0x586

0x587 TS12_SMPL1_NSH 0x0000 Timestamp Unit 12 Input Sample Time (1st) in

Nanoseconds High-Word Register [29:16]

0x588 – 0x589 0x588

0x589 TS12_SMPL1_SL 0x0000 Timestamp Unit 12 Input Sample Time (1st) in

Seconds Low-Word Register [15:0]

0x58A – 0x58B 0x58A

0x58B TS12_SMPL1_SH 0x0000 Timestamp Unit 12 Input Sample Time (1st) in

Seconds High-Word Register [31:16]

0x58C – 0x58D 0x58C

0x58D TS12_SMPL1_SUB_NS 0x0000 Timestamp Unit 12 Input Sample Time (1st) in Sub-

Nanoseconds R egi ster [2:0]

0x58E – 0x593 0x58E

0x593 Reserved

(6-Bytes) Don’t Care None

0x594 – 0x595 0x594

0x595 TS12_SMPL2_NSL 0x0000 Timestamp Unit 12 Input Sample Time (2nd) in

Nanoseconds Low-Word Register [15:0]

0x596 – 0x597 0x596

0x597 TS12_SMPL2_NSH 0x0000 Timestamp Unit 12 Input Sample Time (2nd) in

Nanoseconds High-Word Register [29:16]

0x598 – 0x599 0x598

0x599 TS12_SMP2_SL 0x0000 Timestamp Unit 12 Input Sample Time (2nd) in

Seconds Low-Word Register [15:0]

0x59A – 0x59B 0x59A

0x59B TS12_SMPL2_SH 0x0000 Timestamp Unit 12 Input Sample Time (2nd) in

Seconds High-Word Register [31:16]

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

108 Revision 1.0

Interna l I/O Register Space Mapping for PTP Timestamp Inputs (12 Units, 0x400 – 0x5FF) (Continued)

I/O Register Offset Location Register Name Default Value Description

16-Bit 8-Bit

0x59C – 0x59D 0x59C

0x59D TS12_SMPL2_SUB_NS 0x0000 Timestamp Unit 12 Input Sample Time (2nd) in Sub-

Nanoseconds R egi ster [2:0]

0x59E – 0x5A3 0x59E

0x5A3 Reserved

(6-Bytes) Don’t Care None

0x5A4 – 0x5A5 0x5A4

0x5A5 TS12_SMPL3_NSL 0x0000 Timestamp Unit 12 Input Sample Time (3rd) in

Nanoseconds Low-Word Register [15:0]

0x5A6 – 0x5A7 0x5A6

0x5A7 TS12_SMPL3_NSH 0x0000 Timestamp Unit 12 Input Sample Time (3rd) in

Nanoseconds High-Word Register [29:16]

0x5A8 – 0x5A9 0x5A8

0x5A9 TS12_SMPL3_SL 0x0000 Timestamp Unit 12 Input Sample Time (3rd) in

Seconds Low-Word Register [15:0]

0x5AA – 0x5AB 0x5AA

0x5AB TS12_SMPL3_SH 0x0000 Timestamp Unit 12 Input Sample Time (3rd) in

Seconds High-Word Register [31:16]

0x5AC – 0x5AD 0x5AC

0x5AD TS12_SMPL3_SUB_NS 0x0000 Timestamp Unit 12 Input Sample Time (3rd) in Sub-

Nanoseconds R egi ster [2:0]

0x5AE – 0x5B3 0x5AE

0x5B3 Reserved

(6-Bytes) Don’t Care None

0x5B4 – 0x5B5 0x5B4

0x5B5 TS12_SMPL4_NSL 0x0000 Timestamp Unit 12 Input Sample Time (4th) in

Nanoseconds Low-Word Register [15:0]

0x5B6 – 0x5B7 0x5B6

0x5B7 TS12_SMPL4_NSH 0x0000 Timestamp Unit 12 Input Sample Time (4th) in

Nanoseconds High-Word Register [29:16]

0x5B8 – 0x5B9 0x5B8

0x5B9 TS12_SMPL4_SL 0x0000 Timestamp Unit 12 Input Sample Time (4th) in

Seconds Low-Word Register [15:0]

0x5BA – 0x5BB 0x5BA

0x5BB TS12_SMPL4_SH 0x0000 Timestamp Unit 12 Input Sample Time (4th) in

Seconds High-Word Register [31:16]

0x5BC – 0x5BD 0x5BC

0x5BD TS12_SMPL4_SUB_NS 0x0000 Timestamp Unit 12 Input Sample Time (4th) in Sub-

Nanoseconds R egi ster [2:0]

0x5BE – 0x5C3 0x5BE

0x5C3 Reserved

(6-Bytes) Don’t Care None

0x5C4 – 0x5C5 0x5C4

0x5C5 TS12_SMPL5_NSL 0x0000 Timestamp Unit 12 Input Sample Time (5th) in

Nanoseconds Low-Word Register [15:0]

0x5C6 – 0x5C7 0x5C6

0x5C7 TS12_SMPL5_NSH 0x0000 Timestamp Unit 12 Input Sample Time (5th) in

Nanoseconds High-Word Register [29:16]

0x5C8 – 0x5C9 0x5C8

0x5C9 TS12_SMPL5_SL 0x0000 Timestamp Unit 12 Input Sample Time (5th) in

Seconds Low-Word Register [15:0]

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

109 Revision 1.0

Interna l I/O Register Space Mapping for PTP Timestamp Inputs (12 Units, 0x400 – 0x5FF) (Continued)

I/O Register Offset Location Register Name Default Value Description

16-Bit 8-Bit

0x5CA – 0x5CB 0x5CA

0x5CB TS12_SMPL5_SH 0x0000 Timestamp Unit 12 Input Sample Time (5th) in

Seconds High-Word Register [31:16]

0x5CC – 0x5CD 0x5CC

0x5CD TS12_SMPL5_SUB_NS 0x0000 Timestamp Unit 12 Input Sample Time (5th) in Sub-

Nanoseconds R egi ster [2:0]

0x5CE – 0x5D3 0x5CE

0x5D3 Reserved

(6-Bytes) Don’t Care None

0x5D4 – 0x5D5 0x5D4

0x5D5 TS12_SMPL6_NSL 0x0000 Timestamp Unit 12 Input Sample Time (6th) in

Nanoseconds Low-Word Register [15:0]

0x5D6 – 0x5D7 0x5D6

0x5D7 TS12_SMPL6_NSH 0x0000 Timestamp Unit 12 Input Sample Time (6th) in

Nanoseconds High-Word Register [29:16]

0x5D8 – 0x5D9 0x5D8

0x5D9 TS12_SMPL6_SL 0x0000 Timestamp Unit 12 Input Sample Time (6th) in

Seconds Low-Word Register [15:0]

0x5DA – 0x5DB 0x5DA

0x5DB TS12_SMPL6_SH 0x0000 Timestamp Unit 12 Input Sample Time (6th) in

Seconds High-Word Register [31:16]

0x5DC – 0x5DD 0x5DC

0x5DD TS12_SMPL6_SUB_NS 0x0000 Timestamp Unit 12 Input Sample Time (6th) in Sub-

Nanoseconds R egi ster [2:0]

0x5DE – 0x5E3 0x5DE

0x5E3 Reserved

(6-Bytes) Don’t care None

0x5E4 – 0x5E5 0x5E4

0x5E5 TS12_SMPL7_NSL 0x0000 Timestamp Unit 12 Input Sample Time (7th) in

Nanoseconds Low-Word Register [15:0]

0x5E6 – 0x5E7 0x5E6

0x5E7 TS12_SMPL7_NSH 0x0000 Timestamp Unit 12 Input Sample Time (7th) in

Nanoseconds High-Word Register [29:16]

0x5E8 – 0x5E9 0x5E8

0x5E9 TS12_SMPL7_SL 0x0000 Timestamp Unit 12 Input Sample Time (7th) in

Seconds Low-Word Register [15:0]

0x5EA – 0x5EB 0x5EA

0x5EB TS12_SMPL7_SH 0x0000 Timestamp Unit 12 Input Sample Time (7th) in

Seconds High-Word Register [31:16]

0x5EC – 0x5ED 0x5EC

0x5ED TS12_SMPL7_SUB_NS 0x0000 Timestamp Unit 12 Input Sample Time (7th) in Sub-

Nanoseconds R egi ster [2:0]

0x5EE – 0x5F3 0x5EE

0x5F3 Reserved

(6-Bytes) Don’t Care None

0x5F4 – 0x5F5 0x5F4

0x5F5 TS12_SMPL8_NSL 0x0000 Timestamp Unit 12 Input Sample Time (8th) in

Nanoseconds Low-Word Register [15:0]

0x5F6 – 0x5F7 0x5F6

0x5F7 TS12_SMPL8_NSH 0x0000 Timestamp Unit 12 Input Sample Time (8th) in

Nanoseconds High-Word Register [29:16]

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

110 Revision 1.0

Interna l I/O Register Space Mapping for PTP Timestamp Inputs (12 Units, 0x400 – 0x5FF) (Continued)

I/O Register Offset Location Register Name Default Value Description

16-Bit 8-Bit

0x5F8 – 0x5F9 0x5F8

0x5F9 TS12_SMPL8_SL 0x0000 Timestamp Unit 12 Input Sample Time (8th) in

Seconds Low-Word Register [15:0]

0x5FA – 0x5FB 0x5FA

0x5FB TS12_SMPL8_SH 0x0000 Timestamp Unit 12 Input Sample Time (8th) in

Seconds High-Word Register [31:16]

0x5FC – 0x5FD 0x5FC

0x5FD TS12_SMPL8_SUB_NS 0x0000 Timestamp Unit 12 Input Sample Time (8th) in Sub-

Nanoseconds R egi ster [2:0]

0x5FE – 0x5FF 0x5FE

0x5FF Reserved

(2-Bytes) Don’t Care None

Interna l I/O Register Space Mapping for PTP 1588 Clock and Global Control (0x600 – 0x7FF)

I/O Register Offset Location Register Name Default Value Description

16-Bit 8-Bit

0x600 – 0x601 0x600

0x601 PTP_CLK_CTL 0x0002 PTP Clock Control Register [6:0]

0x602 – 0x603 0x602

0x603 Reserved

(2-Bytes) Don’t care None

0x604 – 0x605 0x604

0x605 PTP_RTC_NSL 0x0000 PTP Real Time Clock in Nanoseconds Low-

Word Register [15:0]

0x606 – 0x607 0x606

0x607 PTP_RTC_NSH 0x0000 PTP Real Time Clock in Nanoseconds High-

Word Register [31:16]

0x608 – 0x609 0x608

0x609 PTP_RTC_SL 0x0000 PTP Real Time Clock in Seconds Low-Word

0x60A – 0x60B 0x60A

0x60B PTP_RTC_SH 0x0000 PTP Real Time Clock in Seconds High-Word

0x60C – 0x60D 0x60C

0x60D PTP_RTC_PHASE 0x0000 PTP Real Time Clock in Phase Register [2:0]

0x60E – 0x60F 0x60E

0x60F Reserved

(2-Bytes) Don’t Care None

0x610 – 0x611 0x610

0x611 PTP_SNS_RATE_L 0x0000 PTP Sub-nanosecond Rate Low-Word Register

[15:0]

0x612 – 0x613 0x612

0x613 PTP_SNS_RATE_H 0x0000 PTP Sub-nanosecond Rate High-Word [29:16]

and Configuration Register

0x614 – 0x615 0x614

0x615 PTP_TEMP_ADJ_DURA_L 0x0000 PTP Temporary Adjustment Mode Duration

Low-Word Register [15:0]

0x616 – 0x617 0x616

0x617 PTP_TEMP_ADJ_DURA_H 0x0000 PTP Temporary Adjustment Mode Duration

High-Word Register [31:16]

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

111 Revision 1.0

Interna l I/O Register Space Mapping for PTP 1588 Clock and Global Control (0x600 – 0x7FF) (Conti n u ed)

I/O Register Offset Location Register Name Default Value Description

16-Bit 16-Bit

0x618 – 0x61F 0x618

0x61F Reserved

(8-Bytes) Don’t Care None

0x620 – 0x621 0x620

0x621 PTP_MSG_CFG_1 0x0059 PTP Message Configuration 1 Register [7:0]

0x622 – 0x623 0x622

0x623 PTP_MSG_CFG_2 0x0404 PTP Message Configuration 2 Register [10:0]

0x624 – 0x625 0x624

0x625 PTP_DOMAIN_VER 0x0200 PTP Domain and Version Register [11:0]

0x626 – 0x63F 0x626

0x63F Reserved

(26-Bytes) Don’t Care None

0x640 – 0x641 0x640

0x641 PTP_P1_RX_ LATENCY 0x019F PTP Port 1 Receive Latency Register [15:0]

0x642 – 0x643 0x642

0x643 PTP_P1_TX_ LATENCY 0x002D PTP Port 1 Transmit Latency Register [15:0]

0x644 – 0x645 0x644

0x645 PTP_P1_ASYM_COR 0x0000 PTP Port 1 Asymmetry Correction Register

[15:0]

0x646 – 0x647 0x646

0x647 PTP_P1_LINK_DLY 0x0000 PTP Port 1 Link Delay Register [15:0]

0x648 – 0x649 0x648

0x649 P1_XDLY_REQ_TSL 0x0000 PTP Port 1 Egress Timestamp Low-Word for

Pdelay_REQ and Delay_REQ Frames Register

[15:0]

0x64A – 0x64B 0x64A

0x64B P1_XDLY_REQ_TSH 0x0000 PTP Port 1 Egress Timestamp High-Word for

Pdelay_REQ and Delay_REQ Frames Register

[31:16]

0x64C – 0x64D 0x64C

0x64D P1_SYNC_TSL 0x0000 PTP Port 1 Egress Timestamp Low-Word for

SYNC Frame Register [15:0]

0x64E – 0x64F 0x64E

0x64F P1_SYNC_TSH 0x0000 PTP Port 1 Egress Timestamp High-Word for

SYNC Frame Register [31:16]

0x650 – 0x651 0x650

0x651 P1_PDLY_RESP_TSL 0x0000 PTP Port 1 Egress Timestamp Low-Word for

Pdelay_resp Frame Register [15:0]

0x652 – 0x653 0x652

0x653 P1_PDLY_RESP_TSH 0x0000 PTP Port 1 Egress Timestamp High-Word for

Pdelay_resp Frame Register [31:16]

0x654 – 0x65F 0x654

0x65F Reserved

(12-Bytes) Don’t Care None

0x660 – 0x661 0x660

0x661 PTP_P2_RX_LATENCY 0x019F PTP Port 2 Receive Latency Register [15:0]

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

112 Revision 1.0

Interna l I/O Register Space Mapping for PTP 1588 Clock and Global Control (0x600 – 0x7FF) (Conti n u ed)

I/O Register Offset Location Register Name Default Value Description

16-Bit 16-Bit

0x662 – 0x663 0x662

0x663 PTP_P2_TX_ LATENCY 0x002D PTP Port 2 Transmit Latency Register [15:0]

0x664 – 0x665 0x664

0x665 PTP_P2_ASYM_COR 0x0000 PTP Port 2 Asymmetry Correction Register

[15:0]

0x666 – 0x667 0x666

0x667 PTP_P2_LINK_DLY 0x0000 PTP Port 2 Link Delay Register [15:0]

0x668 – 0x669 0x668

0x669 P2_XDLY_REQ_TSL 0x0000 PTP Port 2 Egress Timestamp Low-Word for

Pdelay_REQ and Delay_REQ Frames Register

[15:0]

0x66A – 0x66B 0x66A

0x66B P2_XDLY_REQ_TSH 0x0000 PTP Port 2 Egress Timestamp High-Word for

Pdelay_REQ and Delay_REQ Frames Register

[31:16]

0x66C – 0x66D 0x66C

0x66D P2_SYNC_TSL 0x0000 PTP Port 2 Egress Timestamp Low-Word for

SYNC Frame Register [15:0]

0x66E – 0x66F 0x66E

0x66F P2_SYNC_TSH 0x0000 PTP Port 2 Egress Timestamp High-Word for

SYNC Frame Register [31:16]

0x670 – 0x671 0x670

0x671 P2_PDLY_RESP_TSL 0x0000 PTP Port 2 Egress Timestamp Low-Word for

Pdelay_resp Frame Register [15:0]

0x672 – 0x673 0x672

0x673 P2_PDLY_RESP_TSH 0x0000 PTP Port 2 Egress Timestamp High-Word for

Pdelay_resp Frame Register [31:16]

0x674 – 0x67F 0x674

0x67F Reserved

(12-Bytes) Don’t Care None

0x680 – 0x681 0x680

0x681 GPIO_MONITOR 0x0000 PTP GPIO Monitor Register [11:0]

0x682 – 0x683 0x682

0x683 GPIO_OEN 0x0000 PTP GPIO Output Enable Register [11:0]

0x684 – 0x687 0x686

0x687 Reserved

(4-Bytes) Don’t Care None

0x688 – 0x689 0x688

0x689 PTP_TRIG_IS 0x0000 PTP Trigger Unit Interrupt Status Register

0x68A – 0x68B 0x68A

0x68B PTP_TRIG_IE 0x0000 PTP Trigger Unit Interrupt Enable Register

0x68C – 0x68D 0x68C

0x68D PTP_TS_IS 0x0000 PTP Tim e s ta m p Unit Inter r upt S tatus Regi ster

0x68E – 0x68F 0x68E

0x68F PTP_TS_IE 0x0000 PTP Tim e s ta m p Unit Interrupt Enable Regi ster

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Interna l I/O Register Space Mapping for PTP 1588 Clock and Global Control (0x600 – 0x7FF) (Conti n u ed)

I/O Register Offset Location Register Name Default Value Description

16-Bit 16-Bit

0x690 – 0x733 0x690

0x733 Reserved

(164-Bytes) Don’t Care None

0x734 – 0x735 0x734

0x735 DSP_CNTRL_6 0x3020 DSP Control 1 Register

0x736 – 0x747 0x736

0x747 Reserved

(18-Bytes) Don’t Care None

0x748 – 0x749 0x748

0x749 ANA_CNTRL_1 0x0000 Analog Control 1 Register

0x74A – 0x74B 0x74A

0x74B Reserved

(2-Bytes) Don’t Care None

0x74C – 0x74D 0x74C

0x74D ANA_CNTRL_3 0x0000 Analog Control 3 Register

0x74E – 0x7FF 0x74E

0x7FF Reserved

(178-Bytes) Don’t Care None

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The section provides details of the bit definitions for the registers summarized in the previous section. Writing to a bit or

register defined as reserved could potentially cause unpredictable results. If it is necessary to write to registers which

contain bot h writab le and res erved bits in th e sam e register , the user s hould f irst read bac k the reserved bits (RO or RW ),

then “OR” the desired settable bits with the value read and write back the “ORed” value back to the register.

Bit Type Definition:

• RO = Read only.

• WO = Write only.

• RW = Read/Write.

• SC = Self-Clear.

• W1C = Write “1” to Clear (Write a “1” to clear this bit).

Internal I/O Register Space Mapping for Switch Control and Configuration (0x000 – 0x0FF)

Chip ID and Enable Register (0x 000 – 0x001): CIDER

This register contains the chip ID and switch-enable control.

Bit Default Value R/W Description

15 − 8 0x84 RO Family ID

Chip family ID.

7 − 4 0x4 or 0x5 RO Chip ID

0x4 is assigned to KSZ8463ML/FML.

0x5 is assigned to KSZ8463RL/FRL.

3 − 1 001 RO Revision ID

Chip revision ID.

0 1 RW Start Switch

1 = Start the chip.

0 = Switch is disabled.

Switch Global Control Register 1 (0x002

−

0x003): SG CR1

This register contains global control bits for the switch function.

Bit Default R/W Description

15 0 RW

Pass All Frames

1 = Switch all packets including bad ones. Used solely for debugging purposes. Works

in conjunction with sniffer mode only.

0 = Do not pass bad frames.

14 0 RW Receive 2000 Byte Packet Length Enable

1 = Enables the receipt of packets up to and including 2000 bytes in length.

0 = Discards the received packets if their length is greater than 2000 bytes.

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Switch Global Control Register 1 (0x002

−

0x003): SGCR1 (Continued)

Bit Default R/W Description

13 1 RW

IEEE 802.3x Transmit Direction Flow Control Enable

1 = Enables transmit direction flow control feature.

0 = Disable transmit direction flow control feature. The switch will not generate any

flow control packets.

12 1 RW

IEEE 802.3x Receive Direction Flow Control Enable

1 = Enables receive direction flow control feature.

0 = Disable receive direction flow control feature. The switch will not react to any

received flow control packets.

11 0 RW

Frame Length Field Check

1 = Enable checking frame length field in the IEEE packets. If the actual length does not

match, the packet will be dropped (for Length/Type field < 1500).

0 = Disable checking frame length field in the IEEE packets.

10 1 RW Aging Enable

1 = Enable aging function in the chip.

0 = Disable aging function in the chip.

9 0 RW Fast Age Enable

1 = Turn on fast age (800 μs).

8 0 RW Aggressive Back-Off Enable

1 = Enable mor e aggres siv e back-off algorithm in half-duplex mode to enhance

performance. This is not an IEEE standard.

7 − 6 01 RW Reserved

5 0 RW Enable Flow Control when Exceeding Ingress Limit

1 = Flow control frame wi ll be sent to link partner when exceeding the ingress rate limit.

0 = Frame will be dropped when exceeding the ingress rate limit.

4 1 RW

Receive 2K Byte Packets Enable

1 = Enable packet length up to 2K bytes. While set, SGCR2

bits[2,1] will have no effect.

0 = Discard packet if packet length is greater than 2000

bytes.

3 0 RW Pass Flow Control Packet

1 = Switch will not filter 802.1x “flow control” packets.

2 − 1 00 RW Reserved

0 0 RW

Link Change Age

1 = Link change from “link” to “no link” will cause fast aging (<800 us) to age address

table faster. After an age cycle is complete, the age logic will return to normal (300

+ 75 second s). This affects Ports not linked and not activ e linked ports.

Note: If any port is unpl ugg ed, all addre sses w ill be auto mati cally aged out.

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Switch Global Control Register 2 (0x004 – 0x005): SGCR2

This register contains global control bits for the switch function.

Bit Default R/W Description

15 0 RW 802.1Q VLAN Enable

1 = 802.1Q VLAN mode is turned on. VLAN table must be set-up before the operation.

0 = 802.1Q VLAN is disabled.

14 0 RW IGMP Snoop Enable

1 = IGMP snoop is enabled.

0 = IGMP snoop is disabled.

13 0 RW IPv6 MLD Snooping Enable

1 = Enable IPv6 MLD snooping.

12 0 RW IPv6 MLD Snooping Option Select

1 = Enable IPv6 MLD snooping option.

11 − 9 000 RW Reserved

8 0 RW

Sniff Mode Select

1 = Performs RX and TX sniff (both the source port and destination port need to

match).

0 = Performs RX or TX sniff (either the source port or dest ina t ion port needs to

match). This is the mode used to implement RX only sniff.

7 1 RW

Unicast Port-VLAN Mismatch Discard

1 = No packets can cross the VLAN boundary.

0 = Unicast packets (excluding unknown/multicast/broadcast) can cross the VLAN

boundary.

6 1 RW

Multicast Storm Protection Disable

1 = “Broadcast Storm Protection” does not include multicast packets. Only DA =

FF-FF-FF-FF-FF-FF packets are regulated.

0 = “Broadcast Storm Protection” includes DA = FF-FF-FF-FF-FF-FF and DA[40] = “1”

packets.

5 1 RW Back Pressure Mode

1 = Carrier sense-based back pressure is selected.

0 = Collision-based back pressure is selected.

4 1 RW

Flow Control and Back Pressure Fair Mode

1 = Fair mode is selected. In this mode, if a flow control port and a non-flow control

port talk to the same destina tion port, packets from the non-flow control port may

be dropped. This prevents the flow control port from being flow controlled for an

extended period of time.

0 = In this mode, if a flow control port and a non-flow control port talk to the sa me

destination port, the flow control port is flow controlled. This may not be “fair” to the

flow control port.

3 0 RW No Excessive Collision Drop

1 = The switch does not drop packets when 16 or more collisions occur.

0 = The switch drops packets when 16 or more collisions occur.

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Switch Global Control Register 2 (0x004 – 0x005): SGCR2 (Continued)

Bit Default R/W Description

2 0 RW

Huge Packet Support

1 = Accepts packet sizes up to 1916 bytes (inclusive). This bit sett ing ov errid es sett ing

from bit [1] of the same register.

0 = The max packet size is determined by bit [1] of this register.

1 0 RW

Legal Maximum Packet Size Check Enable

1 = 1522 bytes for tagged packets, 1518 bytes for untagged packets. Any packets

larger than the specified value are dropped.

0 = Accepts packet sizes up to 1536 bytes (inclusive).

0 0 RW

Priority Buffe r Reserve

1 = Each port is pre-allocated 48 buffers, used exclusively for high priority (q3, q2,

and q1) packets. Effective only when the multiple queue feature is turned on.

0 = Each port is pre-allocated 48 buffers used for all priority packets (q3, q2, q1, and

q0).

Switch Global Control Register 3 (0x006 – 0x007): SGCR3

This register contains global control bits for the switch function.

Bit Default R/W Description

15 − 8 0x63 RW Broadcast Storm Protection Rate Bits[7:0]

These bits, along with SGCR3[2:0], determine how many 64-byte blocks of packet data are allowed on

an input port in a preset period. The period is 67ms for 100BT or 670ms for 10BT. The default is 1%.

7 0 RO Reserved

6 0 RW Switch Host Port in Half-Duplex Mode

1 = Enable host port in ter fa ce half-duplex mode.

0 = Enable host port in terfa ce full-duplex mode.

5 1 RW Switch Host Port Flow Control Enable

1 = Enable full-duplex flow control on sw itch h o st port.

0 = Disable full-duplex flow control on switch host port

4 0 RW Switch MII 10BT

1 = The switch is in 10Mbps mode.

0 = The switch is in 100M bps mode .

3 0 RW Null VID Replacement

1 = Replaces NULL VID with port VID (12 bits).

0 = No replacement for NULL VID.

2 − 0 000 RW

Broadcast Storm Protection Rate Bits[10:8]

These bits, along with SGCR3[15:8] determine how many 64-byte blocks of packet data are allowed

on an input port in a preset period. The period is 67ms for 100BT or 670ms for 10BT. The default is

1%.

Broadcast stor m protection rate: 148,800 frames/sec * 67ms/interval * 1% = 99 frames/interval

(approx. 0x63)

0x008 – 0x00B: Reserved

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Switch Global Control Register 6 (0x00C – 0x 00D) : SG CR6

This register contains global control bits for the switch function.

Bit Default R/W Description

15 − 14 11 R/W Tag_0x7

IEEE 802.1p mapping. The value in this field is used as the frame’s priority when its VLAN Tag has a

value of 0x7.

13 − 12 11 R/W Tag_0x6

IEEE 802.1p mapping. The value in this field is used as the frame’s priority when its VLAN Tag has a

value of 0x6.

11 − 10 10 R/W Tag_0x5

IEEE 802.1p mapping. The value in this field is used as the frame’s priority when its VLAN Tag has a

value of 0x5.

9 − 8 10 R/W Tag_0x4

IEEE 802.1p mapping. The value in this field is used as the frame’s priority when its VLAN Tag has a

value of 0x4.

7 − 6 01 R/W Tag_0x3

IEEE 802.1p mapping. The value in this field is used as the frame’s priority when its VLAN Tag has a

value of 0x3.

5 − 4 01 R/W Tag_0x2

IEEE 802.1p mapping. The value in this field is used as the frame’s priority when its VLAN Tag has a

value of 0x2.

3 − 2 00 R/W Tag_0x1

IEEE 802.1p mapping. The value in this field is used as the frame’s priority when its VLAN Tag has a

value of 0x1.

1 − 0 00 R/W Tag_0x0

IEEE 802.1p mapping. The value in this field is used as the frame’s priority when its VLAN Tag has a

value of 0x0.

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Switch Global Control Register 7 (0x00E – 0x00F ): SGC R7

This register contains global control bits for the switch function.

Bit Default R/W Description

15 − 10 0x02 R/W Reserved

9 − 8 00 R/W

Port LED Mode

When read, these two bits provide the current setting of the LED display mode for P1/2LED1 and

P1/2LED0 as defined as below. Reg. 0x06C – 0x06D, bits [14:12] determine if this automatic

functionality is utilized or if the port 1 LEDs are controlled by the local processor. Reg. 0x084 –

0x085, bits [14:12] determine if this automatic functionality is utilized or if the port 2 LEDs are

controlled by the local processor.

LED Mode P1/2LED1 P1/2LED0

00 Speed Link and Activity

01 Activity Link

10 Full Duplex Link and Activity

11 Full Duplex Link

7 0 R/W Unknown Default Port Enable

Send packets with unknown destination address to specified ports in bit s [2:0].

1 = Enable to send unknown DA packet

6 − 5 01 or 10 R/W

Driver Strength Selection

These two bits determine the drive strength of all I/O pins except for the following category of pins:

LED pins, GPIO pins, INTRN, RSTN, and RXD3/REF CLK_0.

00 = 4mA.

01 = 8mA. (Default when VDD_IO is 3.3V or 2.5V)

10 = 12mA. (Default when VDD_IO is 1.8V)

11 = 16mA.

4 − 3 00 R/W Reserved

2 − 0 111 R/W

Unknown Packet Default Port(s)

Specifies which ports to send packets with unknown destination addresses. Feature is e na bled by

bit[7].

Bit[2] = For Port 3 (MII / RMII Port)

Bit[1] = For Port 2

Bit[0] = For Port 1

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MAC Address Registers

MAC Address Register 1 (0x010 – 0x011): MACAR1

This register contains the two MSBs of the MAC address for the switch function. This MAC address is used for sending

PAUSE frames.

Bit Default R/W Description

15 − 0 0x0010 RW MACA[47:32]

Specifies MAC Address 1 for sending PAUSE frame.

M AC Ad dress Register 2 (0x012 – 0x013): MACA R2

This register contains the MAC address for the switch function. This MAC address is used for sending PAUSE frames.

Bit Default R/W Description

15 − 0 0xA1FF RW MACA[31:16]

Specifies MAC Address 2 for sending PAUSE frame.

MAC Address Register 3 (0x014 – 0x015): MACAR3

This register contains the two LSBs of the MAC address for the switch function. This MAC address is used for sending

PAUSE frames.

Bit Default R/W Description

15 − 0 0xFFFF RW MACA[15:0]

Specifies MAC Address 3 for sending PAUSE frame.

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TOS Priority Control Registers

TOS Prior ity Control Register 1 (0x016 – 0x017): TOSR1

The IPv4/IP v6 type-of-ser vice (TOS) priority control re gisters are us ed to define a 2-bit priorit y to e ach of the 64 pos sible

values in the 6-bit differentiated services code point (DSCP) field in the IP header of ingress frames.

This register contains the TOS priority control bits for the switch function.

Bit Default R/W Description

15 − 14 00 RW DSCP[15:14]

The value in this field is used as the frame’s priority when bits [7:2] of the IP TOS/DiffServ/Traffic

Class value are 0x1c.

13 − 12 00 R/W DSCP[13:12]

The value in this field is used as the frame’s priority when bits [7:2] of the IP TOS/DiffServ/Traffic

Class value are 0x18.

11 − 10 00 R/W DSCP[11:10]

The value in this field is used as the frame’s priority when bits [7:2] of the IP TOS/DiffServ/Traffic

Class value are 0x14.

9 − 8 00 R/W DSCP[9:8]

The value in this field is used as the frame’s priority when bits [7:2] of the IP TOS/DiffServ/Traffic

Class value are 0x10.

7 − 6 00 R/W DSCP[7:6]

The value in this field is used as the frame’s priority when bits [7:2] of the IP TOS/DiffServ/Traffic

Class value are 0x0c.

5 − 4 00 R/W DSCP[5:4]

The value in this field is used as the frame’s priority when bits [7:2] of the IP TOS/DiffServ/Traffic

Class value are 0x08.

3 − 2 00 R/W DSCP[3:2]

The value in this field is used as the frame’s priority when bits [7:2] of the IP TOS/DiffServ/Traffic

Class value are 0x04.

1 − 0 00 R/W DSCP[1:0]

The value in this field is used as the frame’s priority when bits [7:2] of the IP TOS/DiffServ/Traffic

Class value are 0x00.

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TOS Prior ity Control Register 2 (0x018 – 0x019): TOSR2

This register contains the TOS priority control bits for the switch function.

Bit Default R/W Description

15 − 14 00 RW DSCP[31:30]

The value in this field is used as the frame’s pri ority when bits [7:2] of the IP TOS/DiffServ/Traffic

Class value are 0x3c.

13 − 12 00 R/W DSCP[29:28]

The value in this field is used as the frame’s priority when bits [7:2] of the IP TOS/DiffServ/Traffic

Class value are 0x38.

11 − 10 00 R/W DSCP[27:26]

The value in this field is used as the frame’s priority when bits [7:2] of the IP TOS/DiffServ/Traffic

Class value are 0x34.

9 − 8 00 R/W DSCP[25:24]

The value in this field is used as the frame’s priority when bits [7:2] of the IP TOS/DiffServ/Traffic

Class value are 0x30.

7 − 6 00 R/W DSCP[23:22]

The value in this field is used as the frame’s priority when bits [7:2] of the IP TOS/DiffServ/Traffic

Class value are 0x2c.

5 − 4 00 R/W DSCP[21:20]

The value in this field is used as the frame’s priority when bits [7:2] of the IP TOS/DiffServ/Traffic

Class value are 0x28.

3 −2 00 R/W DSCP[19:18]

The value in this field is used as the frame’s priority when bits [7:2] of the IP TOS/DiffServ/Traffic

Class value are 0x24.

1 − 0 00 R/W DSCP[17:16]

The value in this field is used as the frame’s priority when bits [7:2] of the IP TOS/DiffServ/Traffic

Class value are 0x20.

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TOS Prior ity Control Register 3 (0x01A – 0x01B): TOSR3

This register contains the TOS priority control bits for the switch function.

Bit Default R/W Description

15 − 14 00 RW DSCP[47:46]

The value in this field is used as the frame’s priority when bits [7:2] of the IP TOS/DiffServ/Traffic

Class value are 0x5c.

13 − 12 00 R/W DSCP[45:44]

The value in this field is used as the frame’s priority when bits [7:2] of the IP TOS/DiffServ/Traffic

Class value are 0x58.

11 − 10 00 R/W DSCP[43:42]

The value in this field is used as the frame’s priority when bits [7:2] of the IP TOS/DiffServ/Traffic

Class value are 0x54.

9 − 8 00 R/W DSCP[41:40]

The value in this field is used as the frame’s priority when bits [7:2] of the IP TOS/DiffServ/Traffic

Class value are 0x50.

7 − 6 00 R/W DSCP[39:38]

The value in this field is used as the frame’s priority when bits [7:2] of the IP TOS/DiffServ/Traffic

Class value are 0x4c.

5 − 4 00 R/W DSCP[37:36]

The value in this field is used as the frame’s priority when bits [7:2] of the IP TOS/DiffServ/Traffic

Class value are 0x48.

3 − 2 00 R/W DSCP[35:34]

The value in this field is used as the frame’s priority when bits [7:2] of the IP TOS/DiffServ/Traffic

Class value are 0x44.

1 − 0 00 R/W DSCP[33:32]

The value in this field is used as the frame’s priority when bits [7:2] of the IP TOS/DiffServ/Traffic

Class value are 0x40.

TOS Prior ity Control Register 4 (0x01C – 0x1D): TOSR4

This register contains the TOS priority control bits for the switch function.

Bit Default R/W Description

15 − 14 00 RW DSCP[63:62]

The value in this field is used as the frame’s priority when bits [7:2] of the IP TOS/DiffServ/Traffic

Class value are 0x7c.

13 − 12 00 R/W DSCP[61:60]

The value in this field is used as the frame’s priority when bits [7:2] of the IP TOS/DiffServ/Traffic

Class value are 0x78.

11 − 10 00 R/W DSCP[59:58]

The value in this field is used as the frame’s priority when bits [7:2] of the IP TOS/DiffServ/Traffic

Class value are 0x74.

9 − 8 00 R/W DSCP[57:56]

The value in this field is used as the frame’s priority when bits [7:2] of the IP TOS/DiffServ/Traffic

Class value are 0x70.

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TOS Prior ity Control Register 4 (0x01C – 0x1D): TOSR4 (Continued)

Bit Default R/W Description

7 − 6 00 R/W DSCP[55:54]

The value in this field is used as the frame’s priority when bits [7:2] of the IP TOS/DiffServ/Traffic

Class value are 0x6c.

5 − 4 00 R/W DSCP[53:52]

The value in this field is used as the frame’s priority when bits [7:2] of the IP TOS/DiffServ/Traffic

Class value are 0x68.

3 − 2 00 R/W DSCP[51:50]

The value in this field is used as the frame’s priority when bits [7:2] of the IP TOS/DiffServ/Traffic

Class value are 0x64.

1 − 0 00 R/W DSCP[49:48]

The value in this field is used as the frame’s priority when bits [7:2] of the IP TOS/DiffServ/Traffic

Class value are 0x60.

TOS Prior ity Control Register 5 (0x01E – 0x1F): TOSR5

This register contains the TOS priority control bits for the switch function.

Bit Default R/W Description

15 − 14 00 RW DSCP[79:78]

The value in this field is used as the frame’s priority when bits [7:2] of the IP TOS/DiffServ/Traffic

Class value are 0x9c.

13 − 12 00 R/W DSCP[77:76]

The value in this field is used as the frame’s priority when bits [7:2] of the IP TOS/DiffServ/Traffic

Class value are 0x98.

11 − 10 00 R/W DSCP[75:74]

The value in this field is used as the frame’s priority when bits [7:2] of the IP TOS/DiffServ/Traffic

Class value are 0x94.

9 − 8 00 R/W DSCP[73:72]

The value in this field is used as the frame’s priority when bits [7:2] of the IP TOS/DiffServ/Traffic

Class value are 0x90.

7 − 6 00 R/W DSCP[71:70]

The value in this field is used as the frame’s priority when bits [7:2] of the IP TOS/DiffServ/Traffic

Class value are 0x8c.

5 − 4 00 R/W DSCP[69:68]

The value in this field is used as the frame’s priority when bits [7:2] of the IP TOS/DiffServ/Traffic

Class value are 0x88.

3 −2 00 R/W DSCP[67:66]

The value in this field is used as the frame’s priority when bits [7:2] of the IP TOS/DiffServ/Traffic

Class value are 0x84.

1 − 0 00 R/W DSCP[65:64]

The value in this field is used as the frame’s priority when bits [7:2] of the IP TOS/DiffServ/Traffic

Class value are 0x80.

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TOS Prior ity Control Register 6 (0x020 – 0x021): TOSR6

This register contains the TOS priority control bits for the switch function.

Bit Default R/W Description

15 − 14 00 RW DSCP[95:94]

The value in this field is used as the frame’s priority when bits [7:2] of the IP TOS/DiffServ/Traffic

Class value are 0xbc.

13 −12 00 R/W DSCP[93:92]

The value in this field is used as the frame’s priority when bits [7:2] of the IP TOS/DiffServ/Traffic

Class value are 0xb8.

11 − 10 00 R/W DSCP[91:90]

The value in this field is used as the frame’s priority when bits [7:2] of the IP TOS/DiffServ/Traffic

Class value are 0xb4.

9 − 8 00 R/W DSCP[89:88]

The value in this field is used as the frame’s priority when bits [7:2] of the IP TOS/DiffServ/Traffic

Class value are 0xb0.

7 − 6 00 R/W DSCP[87:86]

The value in this field is used as the frame’s priority when bits [7:2] of the IP TOS/DiffServ/Traffic

Class value are 0xac.

5 − 4 00 R/W DSCP[85:84]

The value in this field is used as the frame’s priority when bits [7:2] of the IP TOS/DiffServ/Traffic

Class value are 0xa8.

3 − 2 00 R/W DSCP[83:82]

The value in this field is used as the frame’s priority when bits [7:2] of the IP TOS/DiffServ/Traffic

Class value are 0xa4.

1 − 0 00 R/W DSCP[81:80]

The value in this field is used as the frame’s priority when bits [7:2] of the IP TOS/DiffServ/Traffic

Class value are 0xa0.

TOS Prior ity Control Register 7 (0x022 – 0x023): TOSR7

This register contains the TOS priority control bits for the switch function.

Bit Default R/W Description

15 − 14 00 RW DSCP[111:110]

The value in this field is used as the frame’s priority when bits [7:2] of the IP TOS/DiffServ/Traffic

Class value are 0xdc.

13 − 12 00 R/W DSCP[109:108]

The value in this field is used as the frame’s priority when bits [7:2] of the IP TOS/DiffServ/Traffic

Class value are 0xd8.

11 − 10 00 R/W DSCP[107:106]

The value in this field is used as the frame’s priority when bits [7:2] of the IP TOS/DiffServ/Traffic

Class value are 0xd4.

9 − 8 00 R/W DSCP[105:104]

The value in this field is used as the frame’s priority when bits [7:2] of the IP TOS/DiffServ/Traffic

Class value are 0xd0.

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TOS Prior ity Control Register 7 (0x022 – 0x023): TOSR7 (Continued)

Bit Default R/W Description

7 − 6 00 R/W DSCP[103:102]

The value in this field is used as the frame’s priority when bits [7:2] of the IP TOS/DiffServ/Traffic

Class value are 0xcc.

5 − 4 00 R/W DSCP[101:100]

The value in this field is used as the frame’s priority when bits [7:2] of the IP TOS/DiffServ/Traffic

Class value are 0xc8.

3 − 2 00 R/W DSCP[99:98]

The value in this field is used as the frame’s priority when bits [7:2] of the IP TOS/DiffServ/Traffic

Class value are 0xc4.

1 − 0 00 R/W DSCP[97:96]

The value in this field is used as the frame’s priority when bits [7:2] of the IP TOS/DiffServ/Traffic

Class value are 0xc0.

TOS Priority Control Register 8 (0x024 – 0x025): TOSR8

This register contains the TOS priority control bits for the switch function.

Bit Default R/W Description

15 − 14 00 RW DSCP[127:126]

The value in this field is used as the frame’s priority when bits [7:2] of the IP TOS/DiffServ/Traffic

Class value are 0xfc

13 − 12 00 R/W DSCP[125:124]

The value in this field is used as the frame’s priority when bits [7:2] of the IP TOS/DiffServ/Traffic

Class value are 0xf8.

11 − 10 00 R/W DSCP[123:122]

The value in this field is used as the frame’s priority when bits [7:2] of the IP TOS/DiffServ/Traffic

Class value are 0xf4.

9 − 8 00 R/W DSCP[121:120]

The value in this field is used as the frame’s priority when bits [7:2] of the IP TOS/DiffServ/Traffic

Class value are 0xf0.

7 − 6 00 R/W DSCP[119:118]

The value in this field is used as the frame’s priority when bits [7:2] of the IP TOS/DiffServ/Traffic

Class value are 0xec.

5 − 4 00 R/W DSCP[117:116]

The value in this field is used as the frame’s priority when bits [7:2] of the IP TOS/DiffServ /T raffic

Class value are 0xe8.

3 − 2 00 R/W DSCP[115:114]

The value in this field is used as the frame’s priority when bits [7:2] of the IP TOS/DiffServ/Traffic

Class value are 0xe4.

1 − 0 00 R/W DSCP[113:112]

The value in this field is used as the frame’s priority when bits [7:2] of the IP TOS/DiffServ/Traffic

Class value are 0xe0.

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KSZ8463ML/RL/FML/FRL

June 11, 2014

127 Revision 1.0

Indirect Access Data Registers

Indirect Access Data Register 1 (0x026 – 0x027): IADR1

This r egister is us ed to ind irectl y read or writ e the dat a in the M anagem ent Inform ation Base ( MIB) Cou nters , Stat ic MAC

Address Table, Dynamic MAC Address Table, or the VLAN Table. Review those sections for detail bit information.

Bit Default R/W Description

15 − 8 0x00 RO Reserved

7 0 RO

CPU Read Status

Only for dynamic and statistics counter reads.

1 = Read is still in progress.

0 = Read has completed.

6 − 3 0x0 RO Reserved

2 − 0 000 RO Indirect Data [66:64]

Bit[66:64] of indire ct data.

Indirect Access Data Register 2 (0x028 – 0x029): IADR2

This r egister is us ed to ind irectl y read or writ e the dat a in the M anagem ent Inform ation Base ( MIB) Cou nters , Stat ic MAC

Address Table, Dynamic MAC Address Table, or the VLAN Table. Review those sections for detail bit information.

Bit Default R/W Description

15 − 0 0x0000 RW Indirect Data [47:32]

Bit[47:32] of indire ct data.

Indirect Access Data Register 3 (0x02A – 0x02B): IADR3

This r egister is us ed to ind irectl y read or writ e the dat a in the M anagem ent Inform ation Base ( MIB) Cou nters , Stat ic MAC

Address Table, Dynamic MAC Address Table, or the VLAN Table. Review those sections for detail bit information.

Bit Default R/W Description

15 − 0 0x0000 RW Indirect Data [63:48]

Bit[63:48] of indire ct data.

Indirect Access Data Register 4 (0x02C – 0x02D): IADR4

This r egister is us ed to ind irectl y read or writ e the dat a in the M anagem ent Inform ation Base ( MIB) Cou nters , Stat ic MAC

Address Table, Dynamic MAC Address Table, or the VLAN Table. Review those sections for detail bit information.

Bit Default R/W Description

15 − 0 0x0000 RW Indirect Data [15:0]

Bit[15:0] of indirect data.

Micrel, Inc.

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128 Revision 1.0

Indirect Access Data Register 5 (0x02E – 0x02F): IADR5

This r egister is us ed to ind irectl y read or writ e the dat a in the M anagem ent Inform ation Base ( MIB) Cou nters , Stat ic MAC

Address Table, Dynamic MAC Address Table, or the VLAN Table. Review those sections for detail bit information.

Bit Default R/W Description

15 − 0 0x0000 RW Indirect Data [31:16]

Bit[31:16] of indire ct data.

Indirect Access Control Register (0x030 – 0x031): IACR

This r egister is us ed to ind irectl y read or writ e the dat a in the M anagem ent Inform ation Base ( MIB) Cou nters , Stat ic MAC

Address Table, Dynamic MAC Addr es s T able, or th e V LAN Table. Re vi e w thos e s ect ions f or d eta il b it infor m atio n. Writing

to IACR triggers a command. Read or write access is determined by Register bit 12.

Bit Default R/W Description

15-13 000 RW Reserved

12 0 RW Read or Write Access Selection

1 = Read cycle.

0 = Write cycle.

11-10 00 RW

Table Select

00 = Static MAC address table selected.

01 = VLAN table selected.

10 = Dynamic MAC address table selected.

11 = MIB counter selected.

9-0 0x000 RW Indirect Address [9:0]

Bit[9:0] of indirect address.

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129 Revision 1.0

Power Management Control and Wake-Up Event Status

Power Management Control and Wake-Up Event Status (0x032 – 0x033): PMCTRL

This register controls the power management mode and provides wake-up event status .

Bit Default R/W Description

15 − 4 0x000 RO Reserved.

3 0 RW

(W1C)

Link-Up Detect Status

1 = A Link Up condition has been detected at either port 1 or port 2 (Write a “1 “to clear).

0 = No Link Up has been detected.

2 0 RW

(W1C)

Energy Detect Status

1 = Energy is detected at either port 1 or port 2 (Write a “1” to clear).

0 = No energy is detected.

1 − 0 00 RW

Power Management Mode

These two bits are used to control device power management mode.

00 = Normal Mode.

01 = Energy Detect Mode.

10 = Global Soft Power-Down Mode.

11 = Reserved.

(0x034 – 0x035): Reserved

Micrel, Inc.

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130 Revision 1.0

Go Sleep Time and Clock Tree Power-Down Control Registers

Go Sleep Time Register (0x036 – 0x037): GST

This register contains the value which is used to control the minimum Go-Sleep time period when the device transitions

from normal power state to low power state in energy detect mode.

Bit Default R/W Description

15 − 8 0x00 RO Reserved

7 − 0 0x8E RW

Go Sleep Time

This value is used to control the minimum period the no energy event has to be detected consecutively

before the devic e enters the low power state during energy-detect mode.

The unit is 20ms. The default go sleep time is around 3.0 seconds.

Clock Tree Power-Down Control Register (0x038 – 0x039): CTPDC

This register contains the power-down control bits for all clocks.

Bit Default R/W Description

15 − 5 0x000 RO Reserved

4 0 RW

PLL Auto Power-Down E nable

1 = When all the following condition are met, the device will automatically shut down the

PLL. Any line or host activity will wake up the PLL.

1) No energy is detected at both port 1 and port 2 in energy-detect mode.

2) Port 3 is at PHY -MII mode and TX_ER is set at high.

0 = PLL clock is always on.

3 0 RW

Switch Clock Auto Shut Down Enable

1 = When no packet transfer is detected on the MII interface of all ports (port 1, port 2,

and port 3) longer than the time specified in bit[1:0] of current register, the device

will shut down the switch clock automatically. The switch clock will be woken up

automat ically when the MII inter fac e of any port becomes bus y .

0 = Swit ch clock is always on.

2 0 RW

CPU Clock Auto Shutdown Enable

1 = When no packet transfer is detected both on host interface and on MII interface of

all ports (port 1, port 2, and port 3) longer tha n the time s pecif ied in bit[1:0] of

current register, the device will shut down CPU clock automatically. The CPU clock

will be waked up automatically when host activity is detected or MII interface of any

port becomes busy.

0 = CPU clock is always on.

1 − 0 00 RW

Shutdown Wait Period

These two bits specify the time for device to monitor host/MII activity continuously before it could shut

down switch or CPU clock.

00 = 5.3s.

01 = 1.6s.

10 = 1ms.

11 = 3.2µs.

0x03A – 0x04B: Reserved

Micrel, Inc.

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131 Revision 1.0

PHY and MII Basic Control Registers

PHY 1 and MII Basic Control Register (0x04C – 0x04D): P1MBCR

This register contains m edia independent interface (MII) control bits for the s witch port 1 function as defined in the IEEE

802.3 specification.

Bit Default R/W Description Bit is Same As:

15 0 RO Reserved

14 0 RW

Far-End Loopback

1 = Perform loopback as follows:

Start: RXP2/RXM2 (port 2)

Loop back: PMD/PMA of port 1’s PH Y

End: TXP2/TXM2 (port 2)

0 = Normal operation.

Bit[8] in P1CR4

13 1 RW

Force 100BT

1 = Force 100Mbps if auto-negotiation is disabled

(bit [12])

0 = Force 10Mbps if auto-negotiation is disabled

(bit [12])

Bit[6] in P1CR4

12 1 RW Auto-Negotiation Enable

1 = Auto-negotiation enabled.

0 = Auto-negotiation disabled. Bit[7] in P1CR4

11 0 RW Power-Down

1 = Power-down.

0 = Normal operation. Bit[11] in P1CR4

10 0 RO Isolate

Not supported.

9 0 RW/SC Restart Auto-Negotiation

1 = Restart auto-negotiation.

0 = Normal operation.

Bit[13] in P1CR4

8 1 RW

Force Full Duplex

1 = Force full duplex.

0 = Force half duplex.

Applies only when auto-negotiation is disabled (bit

[12]).

It is always in half duplex if auto-negotiation is

enabled but failed.

Bit[5] in P1CR4

7 0 RO Collision test

Not supported.

6 0 RO Reserved.

5 1 R/W HP_MDIX

1 = HP Auto-MDI-X mode.

0 = Micrel Auto-MDI-X mode. Bit[15] in P1SR

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132 Revision 1.0

PHY 1 and MII Basic Control Register (0x04C – 0x04D): P1MBCR (Continued )

Bit Default R/W Description Bit is Same As:

4 0 RW Force MDI-X

1 = Force MDI-X.

0 = Normal operation. Bit[9] in P1CR4

3 0 RW Disable Auto-MDI-X

1 = Disable Auto-MDI-X.

0 = Normal operation. Bit[10] in P1CR4

2 0 RW

Disable Far-End-Fault

1 = Disable far-end-fault detection.

0 = Normal opera tion .

For 100BASE-FX fiber mode operation.

Bit[12] in P1CR4

1 0 RW Disable Transm it

1 = Disable transmit.

0 = Normal operation. Bit[14] in P1CR4

0 0 RW Reserved

PHY 1 and MII Basic Status Register (0x04E – 0x04F): P1MBSR

This register contains the media independent interface (MII) status bits for the switch port 1 function.

Bit Default R/W Description Bit is Same As:

15 0 RO T4 Capable

1 = 100BASE-T4 capable.

0 = Not 100BASE-T4 capable.

14 1 RO 100BT Full Capable

1 = 100BASE-TX full-duplex capable.

0 = Not 100BASE-TX full duplex capable.

13 1 RO 100BT Half Capable

1 = 100BASE-TX half-duplex capable.

0 = Not 100BASE-TX half-duplex capable.

12 1 RO 10BT Full Capable

1 = 10BASE-T f ull-duplex capable.

0 = Not 10BASE-T fu ll-duplex capable.

11 1 RO 10BT Half Capable

1 = 10BASE-T half-duplex capable.

0 = Not 10BASE-T half-duplex capable.

10 − 7 0x0 RO Reserved

6 0 RO Preamble Suppressed

Not supported.

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133 Revision 1.0

PHY 1 and MII Basic Status Register (0x04E – 0x04F): P1MBSR (Continued)

Bit Default R/W Description Bit is Same As:

5 0 RO Auto-Negotiation Complete

1 = Auto-negotiation complete.

0 = Auto-negotiation not completed.

Bit[6] in P1SR

4 0 RO

Far-End-Fault

1 = Far-end-fault detected.

0 = No far-end-fault detected.

For 100BASE-FX fiber mode operation.

Bit[8] in P1SR

3 1 RO Auto-Negotiation Capable

1 = Auto-negotiation capable.

0 = Not auto-negotiation capable.

2 0 RO Link Status

1 = Link is up.

0 = Link is down. Bit[5] in P1SR

1 0 RO Jabber test

Not supported.

0 0 RO Extended Capable

1 = Extended register capable.

0 = Not extended register capable.

PHY 1 PHYID Low Register (0x050 – 0x051): PHY1ILR

This register contains the PHY ID (low) for the switch port 1 function.

Bit Default R/W Description

15 − 0 0x1430 RO PHY 1 ID Low Word

Low order PHY 1 ID bits.

PHY 1 PHYID High Register (0x052 – 0x053): PHY1IHR

This register contains the PHY ID (high) for the switch port 1 function.

Bit Default R/W Description

15 − 0 0x0022 RO PHY 1 ID High Word

High-order PHY 1 ID bits.

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134 Revision 1.0

PHY 1 Auto-Negotiation Advertisement Register (0x054 – 0x 055) : P1ANAR

This register contains the auto-negotiation advertisement bits for the switch port 1 function.

Bit Default R/W Description Bit is Same As:

15 0 RO Next page

Not supported.

14 0 RO Reserved

13 0 RO Remote fault

Not supported.

12 − 11 00 RO Reserved

10 1 RW Pause (flow control capabilit y)

1 = Advertise pause ability.

0 = Do not advertise pause capability.

Bit[4] in P1CR4

9 0 RW

Reserved

8 1 RW

Advert ise 100BT Full-Duplex

1 = Advertise 100BT full-duplex capabl e.

0 = Do not advertise 100BT full-duplex

capability.

Bit[3] in P1CR4

7 1 RW

Advertise 100BT Half-Duplex

1= Advertise 100BT half-duplex capabl e.

0 = Do not advertise 100BT half-duplex

capability.

Bit[2] in P1CR4

6 1 RW

Advertise 10BT Full-Duplex

1 = Advertise 10BT full-duplex capable.

0 = Do not advertise 10BT full-duplex

capability.

Bit[1] in P1CR4

5 1 RW

Advertise 10BT Half-Duplex

1 = Advertise 10BT half-duplex capable.

0 = Do not advertise 10BT half-duplex

capability.

Bit[0] in P1CR4

4 − 0 0x01 RO Selector Field

802.3

Micrel, Inc.

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135 Revision 1.0

PHY 1 Auto-Ne g o tiation Link Partner Ability Register (0x056 – 0x057): P1ANLPR

This register contains the auto-negotiation link partner ability bits for the switch port 1 function.

Bit Default R/W Description Bit is Same As:

15 0 RO Next page

Not supported.

14 0 RO L P ACK

Not supported.

13 0 RO Remote fault

Not supported.

12 − 11 00 RO Reserved

10 0 RO Pause

Link partner pause capability. Bit[4] in P1SR

9 0 RO

Reserved

8 0 RO Advertise 100BT Full-Duplex

Link partner 100BT full-duplex capability. Bit[3] in P1SR

7 0 RO Advertise 100BT Half-Duplex

Link partner 100 half-duplex capability. Bit[2] in P1SR

6 0 RO Advertise 10BT Full-Duplex

Link partner 10BT full-duplex capability. Bit[1] in P1SR

5 0 RO Advertise 10BT Half-Duplex

Link partner 10BT half-duplex capability. Bit[0] in P1SR

4 − 0 0x01 RO Reserved

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

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136 Revision 1.0

PHY 2 and MII Basic Control Register (0x058 – 0x059): P2MBCR

This register contains m edia independent interface (MII) control bits for the switch port 2 function as defined in t he IEEE

802.3 specification.

Bit Default R/W Description Bit is Same As:

15 0 RO Reserved

14 0 RW

Far-End Loopback

1 = Perform loop back, as follo ws:

Start: RXP1/RXM1 (port 1)

Loop back: PMD/PMA of port 2’s PH Y

End: TXP1/TXM1 (port 1)

0 = Normal operation.

Bit[8] in P2CR4

13 1 RW Force 100BT

1 = Force 100 Mbps if auto-negotiation is disabled (bit [12])

0 = Force 10 Mbps if auto-negotiation is dis abl ed (bit [12]) Bit[6] in P2CR4

12 1 RW Auto-Negotiation Enable

1 = Auto-negotiation enabled.

0 = Auto-negotiation disabled.

Bit[7] in P2CR4

11 0 RW Powe r Dow n

1 = Power down.

0 = Normal opera tion . Bit[11] in P2CR4

10 0 RO Isolate

Not supported.

9 0 RW/SC Restart Auto-Negotiation

1 = Restart auto-negotiation.

0 = Normal operation, Bit[13] in P2CR4

8 1 RW

Force Full Duplex

1 = Force full duplex.

0 = Force half duplex .

Applies only when auto-negotiation is disabled (bit [12]).

It is always in half duplex if auto-negotiation is enabled but failed.

Bit[5] in P2CR4

7 0 RO Collision test

Not supported.

6 0 RO Reserved

5 1 R/W HP_MDIX

1 = HP Auto-MDI-X mode.

0 = Micrel Auto-MDI-X mode. Bit[15] in P2SR

4 0 RW Force MDI-X

1 = Force MDI-X.

0 = Normal operation. Bit[9] in P2CR4

Micrel, Inc.

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137 Revision 1.0

PHY 2 and MII Basic Control Register (0x058 – 0x059): P2MBCR (Continued)

Bit Default R/W Description Bit is Same As:

3 0 RW Disable Auto- MDI-X

1 = Disable Auto-MDI-X.

0 = Normal operation. Bit[10] in P2CR4

2 0 RW

Disable Far-End-Fault

1 = Disable far-end-fault detection.

0 = Normal opera tion .

For 100BASE-FX fiber mode operation.

Bit[12] in P2CR4

1 0 RW Disable Transm it

1 = Disable transmit.

0 = Normal opera tion . Bit[14] in P2CR4

0 0 RW Reserved

PHY 2 and MII Basic Status Register (0x05A – 0x05B): P2MBSR

This register contains the media independent interface (MII) status bits for the switch port 2 function.

Bit Default R/W Description Bit is Same As:

15 0 RO T4 Capable

1 = 100BASE-T4 capable.

0 = Not 100BASE-T4 capable.

14 1 RO 100BT Full Capable

1 = 100BASE-TX full-duplex capable.

0 = Not 100BASE-TX full-duplex capable.

13 1 RO 100BT Half Capable

1 = 100BASE-TX half-duplex capable.

0 = Not 100BASE-TX half-duplex capable.

12 1 RO 10BT Full Capable

1 = 10BASE-T f ull-duplex capable.

0 = Not 10BASE-T fu ll-duplex capable.

11 1 RO 10BT Half Capable

1 = 10BASE-T half-duplex capable.

0 = Not 10BASE-T half-duplex capable.

10 − 7 0x0 RO Reserved

6 0 RO Preamble Suppressed

Not supported.

5 0 RO Auto-Negotiation Complete

1 = Auto-negotiation complete.

0 = Auto-negotiation not completed. Bit[6] in P2SR

Micrel, Inc.

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138 Revision 1.0

PHY 2 and MII Basic Status Register (0x05A – 0x05B): P2 MBSR (Con tinued)

Bit Default R/W Description Bit is Same As:

4 0 RO

Far-End-Fault

1 = Far-end-fault detected.

0 = No far-end-fault detected.

For 100BASE-FX fiber mode operation.

Bit[8] in P2SR

3 1 RO Auto-Negotiation Capable

1 = Auto-negotiation capable.

0 = Not auto-negotiation capable.

2 0 RO Link Status

1 = Link is up.

0 = Link is down. Bit[5] in P2SR

1 0 RO Jabber Test

Not supported.

0 0 RO Extended Capable

1 = Extended register capable.

0 = Not extended register capable.

PHY 2 PHYID Low Register (0x05C – 0x05D): PHY2ILR

This register contains the PHY ID (low) for the switch port 2 function.

Bit Default R/W Description

15 − 0 0x1430 RO PHY 2 ID Low Word

Low order PHY 2 ID bits.

PHY 2 PHYID High Register (0x05E – 0x05F): PHY2IHR

This register contains the PHY ID (high) for the switch port 2 function.

Bit

Default

R/W

Description

15 − 0 0x0022 RO PHY 2 ID High Word

High order PHY 2 ID bits.

Micrel, Inc.

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139 Revision 1.0

PHY 2 Auto-Negotiation Advertisement Register (0x060 – 0x 061) : P2ANAR

This register contains the auto-negotiation advertisement bits for the switch port 2 function.

Bit Default R/W Description Bit is Same As:

15 0 RO Next Page

Not supported.

14 0 RO Reserved

13 0 RO Remote Fault

Not supported.

12 − 11 00 RO Reserved

10 1 RW Pause (Flow Contr ol Capability)

1 = Advertise pause ability.

0 = Do not advertise pause capability. Bit[4] in P2CR4

9 0 RW

Reserved

8 1 RW

Advert ise 100BT Full-Duplex

1 = Advertise 100BT full-duplex capabl e.

0 = Do not advertise 100BT full-duplex

capability.

Bit[3] in P2CR4

7 1 RW

Advertise 100BT Half-Duplex

1 = Advertise 100BT half-duplex capable.

0 = Do not advertise 100BT half-duplex

capability.

Bit[2] in P2CR4

6 1 RW

Advertise 10BT Full-Duplex

1 = Advertise 10BT full-duplex capable.

0 = Do not advertise 10BT full-duplex

capability.

Bit[1] in P2CR4

5 1 RW

Advertise 10BT Half-Duplex

1 = Advertise 10BT half-duplex capable.

0 = Do not advertise 10BT half-duplex

capability.

Bit[0] in P2CR4

4 − 0 0x01 RO Selector Field

802.3

Micrel, Inc.

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140 Revision 1.0

PHY 2 Auto-Ne g o tiation Link Partner Ability Register (0x062 – 0x063): P2ANLPR

This register contains the auto-negotiation link partner ability bits for the switch port 2 function.

Bit Default R/W Description Bit is Same As:

15 0 RO Next page

Not supported.

14 0 RO L P ACK

Not supported.

13 0 RO Remote fault

Not supported.

12 − 11 00 RO Reserved

10 0 RO Pause

Link partner pause capability. Bit[4] in P2SR

9 0 RO

Reserved

8 0 RO Advertise 100BT Full-Duplex

Link partner 100BT full-duplex capability. Bit[3] in P2SR

7 0 RO Advertise 100BT Half-Duplex

Link partner 100 half-duplex capability. Bit[2] in P2SR

6 0 RO Advertise 10BT Full-Duplex

Link partner 10BT full-duplex capability. Bit[1] in P2SR

5 0 RO Advertise 10BT Half-Duplex

Link partner 10BT half-duplex capability. Bit[0] in P2SR

4 − 0 0x01 RO Reserved

0x064 – 0x065: Reserved

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PHY1 Special Control and Status Register (0x066 – 0x067): P1PHYCTRL

This register contains control and status information of PHY 1.

Bit Default R/W Description Bit is Same As:

15 − 6 0x000 RO Reserved

5 0 RO Polarity Reverse

1 = Polarity is reversed.

0 = Polarity is not reversed. Bit[13] in P1SR

4 0 RO MDI-X Status

0 = MD I

1 = MD I-X Bit[7] in P1SR

3 0 RW Force Link

1 = Force link pass.

0 = Normal operation. Bit[11] in P1SCSLMD

2 1 RW Enable Energy Efficient Ethernet (EEE) on 10BTe

1 = Disable 10BTe.

0 = Enable 10BTe.

1 0 RW

Remote (Near-End) Loopback

1 = Perform remote loopback at port 1' s PHY

(RXP1/RXM1 -> TXP1/T XM1)

0 = Normal operation

Bit[9] in P1SCSLMD

0 0 RW Reserved

0x068 – 0x069: Reserved

Micrel, Inc.

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PHY 2 Special Control and Status Register (0x06A – 0x06B): P2PHYCTRL

This register contains control and status information of PHY 2.

Bit Default R/W Description Bit is Same As:

15 − 6 0x000 RO Reserved

5 0 RO Polarity Reverse

1 = Polarity is reversed.

0 = Polarity is not reversed. Bit[13] in P2SR

4 0 RO MDI-X Status

0 = MD I

1 = MD I-X Bit[7] in P2SR

3 0 RW Force Link

1 = Force link pass.

0 = Normal operation. Bit[11] in P2SCSLMD

2 1 RW Enable Energy Efficient Ethernet (EEE) on 10BTe

1 = Disable 10BTe.

0 = Enable 10BTe.

1 0 RW

Remote (Near-End) Loopback

1 = Perform remote loopback at port 2' s PHY

(RXP2/RXM2 -> TXP2/T XM2)

0 = Normal operation

Bit[9] in P2SCSLMD

0 0 RW Reserved

Micrel, Inc.

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Port 1 Control Registers

Port 1 Con tro l Regi ster 1 ( 0x06C – 0x06D): P1CR1

This register contains control bits for the switch Port 1 function.

Bit Default R/W Description

15 0 RO Reserved

14 - 12 000 R/W

Port 1 LED Direct Control

These bits directly control the port 1 LED pins.

0xx = Normal LED function as set up via Reg. 0x00E – 0x00F, Bits[9:8].

100 = Both port 1 LEDs off.

101 = Port 1 LED1 off, LED0 on.

110 = Port 1 LED1 on, LED0 off.

111 = Both port 1 LEDs on.

11 0 RW

Source Address Filtering Enable for MAC Address 2

1 = Enable the source addres s filtering function when the SA matches MAC

Address 2 in SAFMACA2 (0x0B6 – 0x0BB).

0 = Disable source address filtering function.

10 0 RW

Source Address Filtering Enable for MAC Address 1

1 = Enable the source addres s filtering function when the SA matches MAC

Address 1 in SAFMACA1 (0x0B0 – 0x0B5).

0 = Disable source address filtering function.

9 0 RW Drop Tagged Packet Enable

1 = Enable to drop tagged ingress packets.

0 = Disable to drop tagged ingr ess packet s.

8 0 RW

TX Two Queues Select Enable

1 = The port 1 output queue is split into two priority queues (q0 and q1).

0 = Single output queue on port 1. There is no priority differentiat ion even th ough

packets are classified into high or low priority.

7 0 RW Broadcast Storm Protection Enable

1 = Enable broadcast storm protection for ingress packets on port 1.

0 = Disable broadcast storm protection.

6 0 RW Diffserv Priority Classification Enable

1 = Enable DiffServ priority classification for ingress packets on port 1.

0 = Disable DiffServ function.

5 0 RW 802.1p Priority Classification Enable

1 = Enable 802.1p priority classification for ingress packets on port 1.

0 = Disable 802.1p.

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Port 1 Con tro l Regi ster 1 ( 0x06C – 0x06D): P1CR1 (Continued)

Bit Default R/W Description

4 − 3 00 RW

Port-Based Priority Classification

00 = Ingress packets on port 1 are classified as priority 0 queue if “Di ffServ” or

“802.1p” classification is not enabled or fails to classify.

01 = Ingress packets on port 1 are classified as priority 1 queue if “Di ffServ” or

“802.1p” classification is not enabled or fails to classify.

10 = Ingress packets on port 1 are classified as priority 2 queue if “Di ffServ” or

“802.1p” classification is not enabled or fails to classify.

11 = Ingress packets on port 1 are classified as priority 3 queue if “Di ffserv” or

“802. 1p” cla ss ifi cati on is not enabl ed or fails to classify.

Note: “DiffServ”, “802.1p” and port priority can be enabled at the same time. The OR’ed result of

802.1p and DSCP overwrites the port priority.

2 0 RW

Tag Insertion

1 = When packets are output on port 1, the switch adds 802.1p/q tags to packets

without 802.1p/q tags when received. The swi tch will not add tags to packets

already tagged. The tag inserted is the ingress port’s “port VID”.

0 = Disable tag insertion.

1 0 RW

Tag Removal

1 = When packets are output on port 1, the switch removes 802.1p/q tags from

packets with 802.1p/q tags when received. The switch will not modify packets

received without tags.

0 = Disable tag removal.

0 0 RW

TX Multiple Queues Select Enable

1 = The port 1 output queue is split into four priority queues (q0, q1, q2 and q3).

0 = Single output queue on the port 1. There is no priority differentiation even though

packets are classified into high or low priority.

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Port 1 Con tro l Regi ster 2 ( 0x06 E – 0x06F): P1CR2

This register contains control bits for the switch port 1 function.

Bit Default R/W Description

15 0 RW Reserved

14 0 RW

Ingress VLAN Filtering

1 = The switch discards packets whose VID port membership in VLAN table bits

[18:16] does not include the ingress port VID.

0 = No ingress VLAN filtering.

13 0 RW

Discard Non PVID Packets

1 = The switch discards packets whose VID does not match the ingress port default

VID.

0 = No packets are discarded.

12 0 RW Force Flow Control

1 = Always enable flow control on the port, regardless of auto-negotiation result.

0 = The flow control is enabled based on auto-negotiation result.

11 0 RW Back Pressure Enable

1 = Enable port’s half-duplex back pressur e.

0 = Disable port’s half-duplex back pressure.

10 1 RW Transmit Enable

1 = Enable packet transmission on the port.

0 = Disable packet transmission on the port.

9 1 RW Receive Enable

1 = Enable packet reception on the port.

0 = Disable packet reception on the port.

8 0 RW Learning Disable

1 = Disable switch address learning capability.

0 = Enable switch address learning.

7 0 RW Sniffer Port

1 = Port is designated as a sniffer port and transmits packets that are monitored.

0 = Port is a normal port.

6 0 RW

Receive Sniff

1 = All packets received on the port are marked as “monitored packets” and forw ar ded

to the designated “sniffer port.”

0 = No receive monitoring.

5 0 RW

Transmit Sniff

1 = All packets transmitted on the port are marked as “monitored packets” and

forwarded to the designated “sniffer port.”

0 = No transmit monitoring.

4 0 RW Reserved

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Port 1 Con tro l Regi ster 2 ( 0x06 E – 0x06F): P1CR2 (Continued)

Bit Default R/W Description

3 0 RW

User Priority Ceiling

1 = If the packet’s “priority field” is greater than the “user priority field” in the port VID

control register bit[15:13], replace the packet’s “priority field” with the “user priority

field” in the port VID control register bit[15:13].

0 = Do not compare and replace the packet’s “pri ority field.”

2 − 0 111 RW

Port VLAN Membership

Define the port’s port VLAN member sh ip. Bi t[2] stands for the host port, bit [1] for port 2, and bit [0] for

port 1. The port can only communicate within the membership. A ‘1’ includes a port in the membership;

a ‘0’ excludes a port from the mem bers hip.

Port 1 VID Control Register (0x070 – 0x071): P1VIDCR

This r egister contains control bits f or the sw itch port 1 function. T his register has two m ain uses. It is associated with the

ingress of untagged packets and used for egress tagging as well as being used for address lookup and providing a default

VID for the ingress of untagged or null-VID-tagged packets.

Bit Default R/W Description

15 − 13 0x0 RW Default Tag[15:13]

Port’s default tag, containing “User Priority Field” bits.

12 0 RW Default Tag[12]

Port’s default tag, contai ning the CFI bit.

11 − 0 0x001 RW Default Tag[11:0]

Port’s default tag, contai ning the VID[11:0].

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Port 1 Con tro l Regi ster 3 ( 0x07 2 – 0x073): P1CR3

This register contains control bits for the switch port 1 function.

Bit Default R/W Description

15 − 5 0x000 RO Reserved

4 0 RW Reserved

3 − 2 00 RW

Ingress Limit Mode

These bits determine what kinds of frames are limited and counted against ingress rate limiting as

follows:

00 = Limit and count all frames.

01 = Limit and count Broadcast, Multicast, and flooded Unicast frames.

10 = Limit and count Broadcast and Multicast frames only.

11 = Limit and count Broadcast frames only.

1 0 RW

Count Inter Frame Gap

Count IFG Bytes.

1 = Each frame’s minimum inter frame gap.

IFG bytes (12 per frame) are included in Ingress and Egress rate limiting

calculations.

0 = IFG bytes are not counted.

0 0 RW

Count Preamble

Count preamble Bytes.

1 = Each frame’s preamble bytes (8 per frame) are included in Ingress and Egress

rate limiting calculations.

0 = Preamble bytes are not counted.

Port 1 Ingress Rate Control Register 0 (0x074 – 0x075): P1IRCR0

This register contains the port 1 ingress rate limiting control for priority 1 and priority 0.

Bit Default R/W Description

15 0 RW Reserved

14 − 8 0x00 RW

Ingress Data Rate Limit for Priority 1 Frames

Ingress priority 1 frames will be limited or discarded as shown in the Ingress or Egress Data Rate

Limits table.

Note: The default value 0x00 is full rate at 10Mbps or 100Mbps with no limit.

7 0 RW Reserved

6 − 0 0x00 RW

Ingress Data Rate Limit for Priority 0 Frames

Ingress priority 0 frames will be limited or discarded as shown in the Ingress or Egress Data Rate

Limits table.

Note: The default value 0x00 is full rate at 10Mbps or 100Mbps with no limit.

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Table 21. Ingress or Egress Data Rate Limits

Data Rate Limit for Ingress or

Egress

100BT fo r P riority [3:0]

Registe r Bit[14:8] or Bit[6:0]

0x01 to 0x64 for the rate matches 1 Mbps

to 100Mbps respectively 0x01 to 0x0A for the rate matches

1Mbps to 10Mbps respectively

0x00 (default) for the rate is no limit

(full 100Mbps) 0x00 (default) for the rate

is no limit (full 10Mbps)

64 Kbps 0x65

128 Kbps 0x66

192 Kbps 0x67

256 Kbps 0x68

320 Kbps 0x69

384 Kbps 0x6A

448 Kbps 0x6B

512 Kbps 0x6C

576 Kbps 0x6D

640 Kbps 0x6E

704 Kbps 0x6F

768 Kbps 0x70

832 Kbps 0x71

896 Kbps 0x72

960 Kbps 0x73

Port 1 Ingress Rate Control Register 1 (0x076 – 0x077): P1IRCR1

This register contains the port 1 ingress rate limiting control bits for priority 3 and priority 2.

Bit Default R/W Description

15 0 RW Reserved

14 − 8 0x00 RW

Ingress Data Rate Limit for Priority 3 Frames

Ingress priority 3 frames will be limited or discarded as shown in the Ingress or Egress Data Rate

Limits table.

Note: The default value 0x00 is full rate at 10Mbps or 100Mbps with no limit.

7 0 RW Reserved

6 − 0 0x00 RW

Ingress Data Rate Limit for Priority 2 Frames

Ingress priority 2 frames will be limited or discarded as shown in the Ingress or Egress Data Rate

Limits table.

Note: The default value 0x00 is full rate at 10Mbps or 100Mbps with no limit.

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Port 1 Egress Rate Control Register 0 (0x078 – 0x079): P1ERCR0

This register contains the port 1 egress rate limiting control bits for priority 1 and priority 0.

Bit Default R/W Description

15 0 RW Reserved

14 − 8 0x00 RW

Egress Data Rate Limit for Priority 1 Frames

Egress priority 1 frames will be limited or discarded as shown in the Ingress or Egress Data Rate

Limits table.

Note: The default value 0x00 is full rate at 10Mbps or 100Mbps with no limit.

7 0 RW Egress Rate Limit Control Enable

1 = Enable egress rate limit control.

0 = Disable egress rate limit control.

6 − 0 0x00 RW

Egress Data Rate Limit for Priority 0 Frames

Egress priority 0 frames will be limited or discarded as shown in the Ingress or Egress Data Rate

Limits table.

Note: The default value 0x00 is full rate at 10Mbps or 100Mbps with no limit.

Port 1 Egress Rate Control Register 1 (0x07A – 0x07B): P1ERCR1

This register contains the port 1 egress rate limiting control bits for priority 3 and priority 2.

Bit Default R/W Description

15 0 RW Reserved

14 − 8 0x00 RW

Egress Data Rate Limit for Priority 3 Frames

Egress priority 3 frames will be limited or discarded as shown in the Ingress or Egress Data Rate

Limits table.

Note

: The default value 0x00 is full rate at 10Mbps or 100Mbps with no limit.

7 0 RW Reserved

6 − 0 0x00 RW

Egress Data Rate Limit for Priority 2 Frames

Egress priority 2 frames will be limited or discarded as shown in the Ingress or Egress Data Rate

Limits table.

Note: The default value 0x00 is full rate at 10Mbps or 100Mbps with no limit.

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Port 1 PHY Special Control/Status, LinkMD (0x07C – 0x07D): P1SCSLMD

This register contains the LinkMD control and status information of PHY 1.

Bit Default R/W Description Bit is Same As:

15 0 RO CDT_10m_Short

1 = Less than 10 meter short. Bit [12] in MIIM

PHYAD1 = 0x1, 0x1D

14 − 13 00 RO

Cable Diagnostic Test Results

[00] = Normal condition.

[01] = Open condition has been detected in cable.

[10] = Short condition has been detected in cable.

[11] = Cable diagnostic test has failed.

Bits[14:13] in MIIM

PHYAD1 = 0x1, 0x1D

12 0 RW/

Cable Diagnostic Test Enable

1 = Cable diagnostic test is enabled. It is self-

cleared after the test is done.

0 = Indicates that the cable diagnostic test has

completed and the status information is valid for

reading.

Bit[15] in MIIM

PHYAD1 = 0x1, 0x1D

11 0 RW Force_Link

1 = Force link pass.

0 = Normal operation. Bit[3] in P1PHYCTRL

10 1 RW Reserved

9 0 RW

Remote (Near-End) Loopback

1 = Perform remote loopback at port 1' s PHY

(RXP1/RXM1 -> TXP1/TXM1)

0 = Normal operation

Bit[1] in P1PHYCTRL

8 − 0 0x000 RO CDT_Fault_Count

Distance to the fault. It’s approximately

0.4m*CDT_Fault_Count.

Bits[8:0] in MIIM

PHYAD1 = 0x1, 0x1D

Port 1 Con tro l Regi ster 4 ( 0x07 E – 0x07F): P1CR4

This register contains control bits for the switch port 1 function.

Bit Default R/W Description Bit is Same As:

15 0 RW Reserved

14 0 RW Disable Transmit

1 = Disable the port’s transmitter.

0 = Normal operation. Bit[1] in P1MBCR

13 0 RW/SC Restart Auto-Negotiation

1 = Restart auto-negotiation.

0 = Normal operation. Bit[9] in P1MBCR

12 0 RW

Disable Far-End-Fault

1 = Disable far-end-fault detection.

0 = Normal opera tion .

For 100BASE-FX fiber mode operation.

Bit[2] in P1MBCR

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Port 1 Con tro l Regi ster 4 ( 0x07 E – 0x07F): P1CR4 (Continued)

Bit Default R/W Description Bit is Same As:

11 0 RW

Power Down

1 = Power down.

0 = Normal opera tion .

No change to registers setting.

Bit[11] in P1MBCR

10 0 RW Disable Auto-MDI/MDI-X

1 = Disable Auto-MDI/MDI-X function.

0 = Enable Auto-MDI/MDI-X function. Bit[3] in P1MBCR

9 0 RW

Force M DI-X

1 = If Auto-MDI/MDI-X is disabled, force PHY into

MDI-X mode.

0 = Do not force PHY into MDI-X mode.

Bit[4] in P1MBCR

8 0 RW

Far-End Loopback

1 = Perform loopback, as indi c ated:

Start: RXP2/RXM2 (port 2).

Loopback: PMD/PMA of port 1’s PHY.

End: TXP2/TXM2 (port 2).

0 = Normal operation.

Bit[14] in P1MBCR

7 1 RW

Auto-Negotiation Enable

1 = Auto-negotiation is enabled.

0 = Disable auto-negotiation, speed, and duplex are

decided by bits[6:5] of the same register.

Bit[12] in P1MBCR

6 1 RW Force Speed

1 = Force 100BT if auto-negotiation is disabled (bit[7]).

0 = Force 10BT if auto-negotiation is dis abl ed (b it[7]). Bit[13] in P1MBCR

5 1

Force Duplex

1 = Force full-duplex if auto-negotiation is disabled.

0 = Force half-duplex if auto-negotiation is disabled.

It is always in half-duplex if auto-negotiation is enabled but failed.

Bit[8] in P1MBCR

4 1 RW

Advertised Flow Control Capability.

1 = Advertise flow control (pause) capability.

0 = Suppress flow control (pause) capability from

transmission to link partner.

Bit[10] in P1ANAR

3 1 RW

Advertised 100BT Full-Duplex Capability.

1 = Advertise 100BT full-duplex capabi li ty.

0 = Suppress 100BT full-duplex c apabi li ty from

transmission to link partner.

Bit [8] in P1ANAR

2 1 RW

Advertised 100BT Half-Duplex Capability.

1 = Advertise 100BT half-duplex capability.

0 = Suppress 100BT half-duplex capabi lity from

transmission to link partner.

Bit[7] in P1ANAR

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Port 1 Con tro l Regi ster 4 ( 0x07 E – 0x07F): P1CR4 (Continued)

Bit Default R/W Description Bit is Same As:

1 1 RW

Advertised 10BT Full-Duplex Capability

1 = Advertise 10BT full-duplex capability.

0 = Suppress 10BT full-duplex capability from

transmission to link partner.

Bit[6] in P1ANAR

0 1 RW

Advertised 10BT Half-Duplex Capability

1 = Advertise 10BT half-duplex capabil ity.

0 = Suppress 10BT half-duplex capabi li ty from

transmission to link partner.

Bit[5] in P1ANAR

Port 1 Status Register (0x080 – 0x 081): P1 SR

This register contains status bits for the switch port 1 function.

Bit Default R/W Description Bit is Same As:

15 1 RW HP_Mdix

1 = HP Auto-MDI-X mode.

0 = Micrel Auto-MDI-X mode. Bit[5] in P1M BC R

14 0 RO Reserved

13 0 RO Polarity Reverse

1 = Polarity is reversed.

0 = Polarity is not reversed. Bit[5] in P1PHYCTRL

12 0 RO Transmit Flow Control Enable

1 = Transmit flow control feature is active.

0 = Transmit flow control feature is inactive.

11 0 RO Receive Flow Control Enable

1 = Receive flow control feature is active.

0 = Receive flow control feature is inactive.

10 0 RO Operation Speed

1 = Link speed is 100Mbps.

0 = Link speed is 10Mbps.

9 0 RO Operation Duplex

1 = Link duplex is full.

0 = Link duplex is half.

8 0 RO

Far-End-Fault

1 = Far-end-fault detected.

0 = No far-end-fault detected.

For 100BASE-FX fiber mode operation.

Bit[4] in P1MBSR

7 0 RO MDI-X Status

0 = MDI.

1 = MDI-X. Bit[4] in P1PHYCTRL

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Port 1 Status Register (0x080 – 0x081): P1SR (Continued)

Bit Default R/W Description Bit is Same As:

6 0 RO Auto-Negotiation Done

1 = Auto-negotiation done.

0 = Auto-negotiation not done. Bit[5] in P1MBSR

5 0 RO Link Status

1 = Link good.

0 = Link not good. Bit[2] in P1MBSR

4 0 RO Partner Flow Control Capability

1 = Link partner flow control (pause) capable.

0 = Link partner not flow control (pause) capable. Bit[10] in P1ANLPR

3 0 RO Partner 100BT Full-Duplex Capability

1 = Link partner 100BT full-duplex capable.

0 = Link partner not 100BT full-duplex capable. Bit[8] in P1ANLPR

2 0 RO Partner 100BT Half-Duplex Capability

1 = Link partner 100BT half-duplex capable.

0= Link partner not 100BT half-duplex capable. Bit[7] in P1ANLPR

1 0 RO Partner 10BT Full-Duplex Capability

1= Link partner 10BT full-duplex capable.

0 = Link partner not 10BT full-duplex capable. Bit[6] in P1ANLPR

0 0 RO Partner 10BT Half-Duplex Capability

1 = Link partner 10BT half-duplex capable.

0 = Link partner not 10BT half-duplex capable. Bit[5] in P1ANLPR

0x082 – 0x083: Reserved

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Port 2 Control Registers

Port 2 Con tro l Regi ster 1 ( 0x08 4 – 0x085): P2CR1

This register contains control bits for the switch port 2 function.

Bit Default R/W Description

15 0 RO Reserved

14 - 12 000 R/W

Port 2 LED Direct Control

These bits directly control the port 2 LED pins.

0xx = Normal LED function as set up via Reg. 0x00E – 0x00F, Bit[9:8].

100 = Both port 2 LEDs off.

101 = Port 2 LED1 off, LED0 on.

110 = Port 2 LED1 on, LED0 off.

111 = Both port 2 LEDs on.

11 0 RW

Source Address Filtering Enable for MAC Address 2

1 = Enable the source addres s filtering function when the SA matches MAC Address

2 in SAFMACA2 (0x0B6 – 0x0BB).

0 = Disable source address filtering function.

10 0 RW

Source Address Filtering Enable for MAC Address 1

1 = Enable the source address filtering function when the SA matches MAC Address

1 in SAFMACA1 (0x0B0 – 0x0B5).

0 = Disable source address filtering function.

9 0 RW Drop Tagged Packet Enable

1 = Enable to drop tagged ingress packets.

0 = Disable to drop tagged ingr ess packet s.

8 0 RW

TX Two Queues Select Enable

1 = The port 2 output queue is split into two priority queues (q0 and q1)

0 = Single output queue on port 2. There is no priority differentiation even though

packets are classified into high or low priority.

7 0 RW Broadcast Storm Protection Enable

1 = Enable broadcast storm protection for ingress packets on port 2.

0 = Disable broadcast storm protection.

6 0 RW Diffserv Priority Classification Enable

1 = Enable DiffServ priority classification for ingress packets on port 2.

0 = Disable DiffServ function.

5 0 RW 802.1p Priority Classification Enable

1 = Enable 802.1p priority classification for ingress packets on port 2.

0 = Disable 802.1p.

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Port 2 Con tro l Regi ster 1 ( 0x08 4 – 0x085): P2CR1 (Continued)

Bit Default R/W Description

4 − 3 00 RW

Port-Based Priority Classification

00 = Ingress packets on port 2 are classified as priority 0 queue if “Di ffServ” or “802.1p”

class ifi cat ion is not enabled or fails to classify.

01 = Ingress packets on port 2 are classified as priority 1 queue if “Di ffServ” or “802.1p”

classification is not enabled or fails to classify.

10 = Ingress packets on port 2 are classified as priority 2 queue if “Di ffServ” or “802.1p”

classification is not enabled or fails to classify.

11 = Ingress packets on port 2 are classified as priority 3 queue if “Di ffserv” or “802.1p”

classification is not enabled or fails to classify.

Note: “DiffServ”, “802.1p” and port pri ority can be enabled at the same time. The OR’ed result of

802.1p and DSCP overwrites the port priority.

2 0 RW

Tag Insertion

1 = When packets are output on port 2, the switch adds 802.1p/q tags to packets

without 802.1p/q tags when received. The switch will not add tags to packets

already tagged. The tag inserted is the ingress port’s “port VID”.

0 = Disable tag insertion.

1 0 RW

Tag Removal

1 = When packets are output on port 2, the switch removes 802.1p/q tags from

packets with 802.1p/q tags when received. The switch will not modify packets

received without tags.

0 = Disable tag removal.

0 0 RW

TX Multiple Queues Select Enable

1 = The port 2 output queue is split into four priority queues (q0, q1, q2 and q3).

0 = Single output queue on port 2. There is no priority differentiation even though

packets are classified into high or low priority.

Port 2 Con tro l Regi ster 2 ( 0x08 6 – 0x087): P2CR2

This register contains control bits for the switch port 2 function.

Bit

Default

R/W

Description

15 0 RW Reserved

14 0 RW

Ingress VLAN Filtering

1 = The switch discards packets whose VID port membership in VLAN table bits

[18:16] does not include the ingress port VID.

0 = No ingress VLAN filtering.

13 0 RW

Discard Non PVID Packets

1 = The switch discards packets whose VID does not match the ingress port default

VID.

0 = No packets are discarded.

12 0 RW Force Flow Control

1 = Always enable flow control on the port, regardless of auto-negotiation result.

0 = The flow control is enabled based on auto-negotiation result.

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Port 2 Con tro l Regi ster 2 ( 0x08 6 – 0x087): P2CR2 (Continued)

Bit Default R/W Description

11 0 RW Back Pressure Enable

1 = Enable port’s half-duplex back pressure.

0 = Disable port’s half-duplex back pressure.

10 1 RW Transmit Enable

1 = Enable packet transmission on the port.

0 = Disable packet transmission on the port.

9 1 RW Receive Enable

1 = Enable packet reception on the port.

0 = Disable packet reception on the port.

8 0 RW Learning Disable

1 = Disable switch address learning capability.

0 = Enable switch address learning.

7 0 RW Sniffer Port

1 = Port is designated as a sniffer port and transmits packets that are monitored.

0 = Port is a normal port.

6 0 RW

Receive Sniff

1 = All packets received on the port are marked as “monitored packets” and forw ar ded

to the designated “sniffer port.”

0 = No receive monitoring.

5 0 RW

Transmit Sniff

1 = All packets transmitted on the port are marked as “monitored packets” and

forwarded to the designated “sniffer port.”

0 = No transmit monitoring.

4 0 RW Reserved

3 0 RW

User Priority Ceiling

1 = If the packet’s “priority field” is greater than the “user priority field” in the port VID

control register bit[15:13], replace the packet’s “priority field” with the “user priority

field” in the port VID control register bit[15:13].

0 = Do not compare and replace the packet’s “pri ority field.”

2 − 0 111 RW

Port VLAN Membership

Define the port’s port VLAN member sh ip. Bi t[2] stands for the host port, bit[1] for port 2, and bit[0] for

port 1. The port can only communicate within the membership. A ‘1’ includes a port in the membership;

a ‘0’ excludes a port from the mem bers hip.

Micrel, Inc.

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Port 2 VID Control Register (0x088 – 0x089): P2VIDCR

This r egister contains control bits f or the s witch port 2 function. This register has two m ain uses. It is associa ted with the

ingress of untagged packets and used for egress tagging as well as being used for address lookup and providing a default

VID for the ingress of untagged or null-VID-tagged packets.

Bit Default R/W Description

15 − 13 000 RW Default Tag[15:13]

Port’s default tag, containing “User Priority Field” bits.

12 0 RW Default Tag[12]

Port’s default tag, contai ning CFI bit.

11 − 0 0x001 RW Default Tag[11:0]

Port’s default tag, contai ning V ID[ 11:0].

Port 2 Con tro l Regi ster 3 ( 0x08A – 0x08B): P2CR3

This register contains the control bits for the switch port 2 function.

Bit Default R/W Description

15 − 5 0x000 RO Reserved

4 0 RW Reserved

3 − 2 00 RW

Ingress Limit Mode

These bits determine what kinds of frames are limited and counted against ingress rate limiting as

follows:

00 = Limit and count all frames.

01 = Limit and count Broadcast, Multicast, and flooded Unicast frames.

10 = Limit and count Broadcast and Multicast frames only.

11 = Limit and count Broadcast frames only.

1 0 RW

Count Inter Frame Gap

Count IFG Bytes.

1 = Each fram e’s minimum inter frame gap.

IFG bytes (12 per frame) are included in Ingress and Egress rate limiting

calculations.

0 = IFG bytes are not counted.

0 0 RW

Count Preamble

Count preamble Bytes.

1 = Each frame’s preamble bytes (8 per frame) are included in Ingress and Egress

rate limiting calculations.

0 = Preamble bytes are not counted.

Micrel, Inc.

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Port 2 Ingress Rate Control Register 0 (0x08C – 0x08D): P2IRCR0

This register contains the port 2 ingress rate limiting control bits for priority 1 and priority 0.

Bit Default R/W Description

15 0 RW Reserved

14 − 8 0x00 RW

Ingress Data Rate Limit for Priority 1 Frames

Ingress priority 1 frames will be limited or discarded as shown in the Ingress or Egress Data Rate

Limits table.

Note: The default value 0x00 is full rate at 10Mbps or 100Mbps with no limit.

7 0 RW Reserved

6 − 0 0x00 RW

Ingress Data Rate Limit for Priority 0 Frames

Ingress priority 0 frames will be limited or discarded as shown in the Ingress or Egress Data Rate

Limits table.

Note: The default value 0x00 is full rate at 10Mbps or 100Mbps with no limit.

Port 2 Ingress Rate Control Register 1 (0x08E – 0x08F): P2IRCR1

This register contains the port 2 ingress rate limiting control bits for priority 3 and priority 2.

Bit Default R/W Description

15 0 RW Reserved

14 − 8 0x00 RW

Ingress Data Rate Limit for Priority 3 Frames

Ingress priority 3 frames will be limited or discarded as show n in the Ingress or Egress Data Rate

Limits table.

Note: The default value 0x00 is full rate at 10Mbps or 100Mbps with no limit.

7 0 RW Reserved

6 − 0 0x00 RW

Ingress Data Rate Limit for Priority 2 Frames

Ingress priority 2 frames will be limited or discarded as shown in the Ingress or Egress Data Rate

Limits table.

Note

: The default value 0x00 is full rate at 10Mbps or 100Mbps with no limit.

Micrel, Inc.

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Port 2 Egress Rate Control Register 0 (0x090 – 0x091): P2ERCR0

This register contains the port 2 egress rate limiting control bits for priority 1 and priority 0.

Bit Default R/W Description

15 0 RW Reserved

14 − 8 0x00 RW

Egress Data Rate Limit for Priority 1 Frames

Egress priority 1 frames will be limited or discarded as shown in the Ingress or Egress Data Rate

Limits table.

Note: The default value 0x00 is full rate at 10Mbps or 100Mbps with no limit.

7 0 RW

Egress Rate Limit Control Enable

1 = Enable egre ss rate li mit co ntr ol.

0 = Disable egress rate limit control.

6 − 0 0x00 RW

Egress Data Rate Limit for Priority 0 Frames

Egress priority 0 frames will be limited or discarded as shown in the Ingress or Egress Data Rate

Limits table.

Note: The default value 0x00 is full rate at 10Mbps or 100Mbps with no limit.

Port 2 Egress Rate Control Register 1 (0x092 – 0x093): P2ERCR1

This register contains the port 2 egress rate limiting control bits for priority 3 and priority 2.

Bit Default R/W Description

15 0 RW Reserved

14 − 8 0x00 RW

Egress Data Rate Limit for Priority 3 Frames

Egress priority 3 frames will be limited or discarded as shown in the Ingress or Egress Data Rate

Limits table.

Note: The default value 0x00 is full rate at 10Mbps or 100Mbps with no limit.

7 0 RW Reserved

6 − 0 0x00 RW

Egress Data Rate Limit for Priority 2 Frames

Egress priority 2 frames will be limited or discarded as shown in the Ingress or Egress Data Rate

Limits table.

Note

: The default value 0x00 is full rate at 10Mbps or 100Mbps with no limit.

Micrel, Inc.

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160 Revision 1.0

Port 2 PHY Special Co n trol /Status, LinkMD® (0x094 – 0x 095): P2 SCSLMD

This register contains the LinkMD control and status information of PHY 2.

Bit Default R/W Description Bit is Same As:

15 0 RO CDT_10m_Short

1 = Less than 10 meter short. Bit[12] in MIIM

PHYA D = 0x2, 0x1D

14 − 13 00 RO

Cable Diagnostic Results

[00] = Normal condition.

[01] = Open condition has been detected in cable.

[10] = Short condition has been detected in cable.

[11] = Cable diagnostic test has failed.

Bits[14:13] in MIIM

PHYA D = 0x2, 0x1D

12 0 RW/

Cable Diagnostic Test Enable

1 = Cable diagnostic test is enabled. It is self-cleared after the

test is done.

0 = Indicates that the cable diagnostic test has completed and

the status information is valid for reading.

Bit[15] inMIIM

PHYA D = 0x2, 0x1D

11 0 RW

Force_Link

Force link.

1 = Force link pass.

0 = Normal opera t ion .

Bit[3] in P2PHYCTRL

10 1 RW Reserved

9 0 RW

Remote (Near-End) Loopback

1 = Perform remote loopback at port 2' s PHY

(RXP2/RXM2 -> TXP2/T XM2)

0 = Normal operation

Bit[1] in P2PHYCTRL

8 − 0 0x000 RO CDT_Fault_Count

Distance to the fault. It’s approximately

0.4m*CDT_Fault_Count.

Bits[8:0] in MIIM

PHYA D = 0x2, 0x1D

Port 2 Con tro l Regi ster 4 ( 0x09 6 – 0x097): P2CR4

This register contains the control bits for the switch port 2 function.

Bit Default R/W Description Bit is Same As:

15 0 RW Reserved

14 0 RW DisableTransmit

1 = Disable the port’s transmitter.

0 = Normal operation. Bit[1] in P2MBCR

13 0 RW/SC Restart Auto-Negotiation

1 = Restart auto-negotiation.

0 = Normal operation. Bit[9] in P2MBCR

12 0 RW

Disable Far-End-Fault

1 = Disable far-end-fault detection.

0 = Normal opera tion .

For 100BASE-FX fiber-mode oper ati on.

Bit[2] in P2MBCR

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Port 2 Con tro l Regi ster 4 ( 0x09 6 – 0x097): P2CR4 (Continued)

Bit Default R/W Description Bit is Same As:

11 0 RW

Power Down

1 = Power down.

0 = Normal operation .

No change to registers setting

Bit[11] in P2MBCR

10 0 RW Disable Auto-MDI/MDI-X

1 = Disable Auto-MDI/MDI-X function.

0 = Enable Auto- MDI/MDI-X function. Bit[3] in P2MBCR

9 0 RW

Force M DI-X

1 = If Auto-MDI/MDI-X is disabled, force PHY into

MDI-X mode.

0 = Do not force PHY into MDI-X mode.

Bit[4] in P2MBCR

8 0 RW

Far-End Loopback

1 = Perform loopback, as indi c ated:

Start: RXP1/RXM1 (port 1).

Loopback: PMD/PMA of port 2’s PHY.

End: TXP1/TXM1 (port 1).

0 = Normal operation.

Bit[14] in P2MBCR

7 1 RW

Auto-Negotiation Enable

1 = Auto-negotiation is enabled.

0 = Disable auto-negotiation, speed, and duplex are

decided by bits [6:5] of the same register.

Bit[12] in P2MBCR

6 1 RW Force Speed

1 = Force 100BT if auto-negotiation is disabled (bit[7]).

0 = Force 10BT if auto-negotiation is dis abl ed (b it[7]). Bit[13] in P2MBCR

5 1

Force Duplex

1 = Force full duplex if auto-negotiation is disabled.

0 = Force half duplex if auto-negotiation is dis abled.

It is always in half duplex if auto-negotiation is enabled but failed.

Bit[8] in P2MBCR

4 1 RW

Advertised Flow Control Capability.

1 = Advertise flow control (pause) capability.

0 = Suppress flow control (pause) capability from

transmission to link partner.

Bit[10] in P2ANAR

3 1 RW

Advertised 100BT Full-Duplex Capability.

1 = Advertise 100BT full-duplex capabi li ty.

0 = Suppress 100BT full-duplex c apabi li ty from

transmission to link partner.

Bit[8] in P2ANAR

2 1 RW

Advertised 100BT Half-Duplex Capability.

1 = Advertise 100BT half-duplex capability.

0 = Suppress 100BT half-duplex capabi lity from

transmission to link partner.

Bit[7] in P2ANAR

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Port 2 Con tro l Regi ster 4 ( 0x09 6 – 0x097): P2CR4 (Continued)

Bit Default R/W Description Bit is Same As:

1 1 RW

Advertised 10BT Full-Duplex Capability.

1 = Advertise 10BT full-duplex capability.

0 = Suppress 10BT full-duplex capability from

transmission to link partner.

Bit[6] in P2ANAR

0 1 RW

Advertised 10BT Half-Duplex Capability.

1 = Advertise 10BT half-duplex capabil ity.

0 = Suppress 10BT half-duplex capabi li ty from transmission to link

partner.

Bit[5] in P2ANAR

Port 2 Status Register (0x098 – 0x 099): P2 SR

This register contains status bits for the switch port 2 function.

Bit Default R/W Description Bit is Same As:

15 1 RW HP_MDIX

1 = HP Auto-MDI-X mode.

0 = Micrel Auto-MDI-X mode. Bit[5] in P2M BC R

14 0 RO Reserved

13 0 RO Polarity Reverse

1 = Polarity is reversed.

0 = Polarity is not reversed. Bit[5] in P2PHYCTRL

12 0 RO Transmit Flow Control Enable

1 = Transmit flow control feature is active.

0 = Transmit flow control feature is inactive.

11 0 RO Receive Flow Control Enable

1 = Receive flow control featur e is active.

0 = Receive flow control feature is inactive.

10 0 RO Operation Speed

1 = Link speed is 100Mbps.

0 = Link speed is 10Mbps.

9 0 RO Operation Duplex

1 = Link duplex is full.

0 = Link duplex is half.

8 0 RO

Far-End-Fault

1 = Far-end-fault detected.

0 = No far-end-fault detected.

For 100BASE-FX fiber mode operation.

Bit[4] in P2MBSR

7 0 RO MDI-X status

0 = MDI.

1 = MDI-X. Bit[4] in P2PHYCTRL

Micrel, Inc.

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163 Revision 1.0

Port 2 Status Register (0x098 – 0x099): P2SR (Continued)

Bit Default R/W Description Bit is Same As:

6 0 RO Auto-Negotiation Done

1 = Auto-negotiation done.

0 = Auto-negotiation not done. Bit[5] in P2MBSR

5 0 RO Link Status

1 = Link good.

0 = Link not good. Bit[2] in P2MBSR

4 0 RO Partner Flow Control Capability.

1 = Link partner flow control (pause) capable.

0 = Link partner not flow control (pause) capable. Bit[10] in P2ANLPR

3 0 RO Partner 100BT Full-Duplex Capability.

1 = Link partner 100BT full-duplex capable.

0 = Link partner not 100BT full-duplex capable. Bit[8] in P2ANLPR

2 0 RO Partner 100BT Half-Duplex Capability.

1 = Link partner 100BT half-duplex capable.

0= Link partner not 100BT half-duplex capable. Bit[7] in P2ANLPR

1 0 RO Partner 10BT Full-Duplex Capability.

1= Link partner 10BT full-duplex capable.

0 = Link partner not 10BT full-duplex capable. Bit[6] in P2ANLPR

0 0 RO Partner 10BT Half-Duplex Capability.

1 = Link partner 10BT half-duplex capable.

0 = Link partner not 10BT half-duplex capable. Bit[5] in P2ANLPR

0x09A – 0x09B: Reserved

Micrel, Inc.

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Port 3 Control Registers

Port 3 Con tro l Regi ster 1 ( 0x09C – 0x09D): P3CR1

This register contains control bits for the switch port 3 function.

Bit Default R/W Description

15 − 10 0x00 RO Reserved

9 0 RW Drop Tagged Packet Enable

1 = Enable to drop tagged ingr ess p a ckets.

0 = Disable to drop tagged ingr ess packet s.

8 0 RW

TX Two Queues Select Enable

1 = The port 3 output queue is split into two priority queues (q0 and q1).

0 = Single output queue on port 3. There is no priority differentiation even though

packets are classified into high or low priority.

7 0 RW Broadcast Storm Protection Enable

1 = Enable broadcast storm protection for ingress packets on port 3.

0 = Disable broadcast storm protection.

6 0 RW Diffserv Priority Classification Enable

1 = Enable DiffServ priority classification for ingress packets on port 3.

0 = Disable DiffServ function.

5 0 RW 802.1p Priority Classification Enable

1 = Enable 802.1p priority classification for ingress packets on port 3.

0 = Disable 802.1p.

4 − 3 00 RW

Port-Based Priority Classification

00 = Ingre ss packet s on port 3 are cl assified as priority 0 queue if “DiffServ” or “802.1p”

classification is not enabled or fails to classify.

01 = Ingress packets on port 3 are classified as priority 1 queue if “DiffServ” or “802.1p”

classification is not enabled or fails to classify.

10 = Ingre ss packet s on port 3 are cl assified as priority 2 queue if “DiffServ” or “802.1p”

classification is not enabled or fails t o classify .

11 = Ingre ss packet s on port 3 are cl assified as priority 3 queue if “Diffserv” or “802.1p”

classification is not enabled or fails to classify.

Note: “DiffServ”, “802.1p” and port pri ority can be enabled at the same time. The OR’ed result of

802.1p and DSCP overwrites the port priority.

2 0 RW

Tag Insertion

1 = When packets are output on port 3, the switch adds 802.1p/q tags to packets

without 802.1p/q tags when received. The switch will not add tags to packets

already tagged. The tag inserted is the ingress port’s “port VID”.

0 = Disable tag insertion.

1 0 RW

Tag Removal

1 = When packets are output on port 3, the switch removes 802.1p/q tags from

packets with 802.1p/q tags when received. The switch will not modify packets

received without tags.

0 = Disable tag removal.

Micrel, Inc.

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165 Revision 1.0

Port 3 Con tro l Regi ster 1 ( 0x09C – 0x09D): P3CR1 (Continued)

Bit Default R/W Description

0 0 RW

TX Multiple Queues Select Enable

1 = The port 3 output queue is split into four priority queues (q0, q1, q2 and q3).

0 = Single output queue on port 3. There is no priority differentiation even though

packets are classified into high or low priority.

Port 3 Con tro l Regi ster 2 ( 0x09 E – 0x09F): P3CR2

This register contains control bits for the switch port 3 function.

Bit Default R/W Description

15 0 RW Reserved

14 0 RW

Ingress VLAN Filtering

1 = The switch discards packets whose VID port membership in VLAN table bits

[18:16] does not include the ingress port VID.

0 = No ingress VLAN filtering.

13 0 RW

Discard Non PVID Packets

1 = The switch discards packets whose VID does not match the ingress port default

VID.

0 = No packets are discarded.

12 0 RW Reserved

11 0 RW Back Pressure Enable

1 = Enable port’s half-duplex back pressur e.

0 = Disable port’s half-duplex back pressure.

10 1 RW Transmit Enable

1 = Enable packet transmission on the port.

0 = Disable packet transmission on the port.

9 1 RW Receive Enable

1 = Enable packet reception on the port.

0 = Disable packet reception on the port.

8 0 RW Learning Disable

1 = Disable switch address learning capability.

0 = Enable switch address learning.

7 0 RW Sniffer Port

1 = Port is designated as a sniffer port and transmits packets that are monitored.

0 = Port is a normal port.

6 0 RW

Receive Sniff

1 = All packets received on the port are marked as “monitored packets” and forw ar ded

to the designated “sniffer port.”

0 = No receive monitoring.

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Port 3 Con tro l Regi ster 2 ( 0x09 E – 0x09F): P3CR2 (Continued)

Bit Default R/W Description

5 0 RW

Transmit Sniff

1 = All packets transmitted on the port are marked as “monitored packets” and

forwarded to the designated “sniffer port.”

0 = No transmit monitoring.

4 0 RW Reserved

3 0 RW

User Priority Ceiling

1 = If the packet’s “priority field” is greater than the “user priority field” in the port VID

control register bit[15:13], replace the packet’s “priority field” with the “user priority

field” in the port VID control register bit[15:13].

0 = Do not compare and replace the packet’s “pri ority field.”

2 − 0 111 RW

Port VLAN Membership

Define the port’s port VLAN member sh ip. Bi t[2] stands for the host port, bit [1] for port 2, and bit [0] for

port 1. The port can only communicate within the membership. A ‘1’ includes a port in the membership;

a ‘0’ excludes a port from the mem bers hip.

Port 3 VID Control Register (0x0A0 – 0x0A1): P3 VI D CR

This r egister contains the control bits for th e switch port 3 functi on. This reg ister has t wo main uses. It is ass ociated with

the ingress of untagged packets and used for egress tagging as well as being used for address lookup and providing a

default VID for the ingress of untagged or null-VID-tag ged pac k et s.

Bit Default R/W Description

15 − 13 0x0 RW Default Tag[15:13]

Port’s default tag, containing “User Priority Field” bits.

12 0 RW Default Tag[12]

Port’s default tag, contai ning CFI bit.

11 − 0 0x001 RW Default Tag[11:0]

Port’s default tag, contai ning V ID[ 11:0].

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Port 3 Con tro l Regi ster 3 ( 0x0A2 – 0x0A3): P3C R3

This register contains the control bits for the switch port 3 function.

Bit Default R/W Description

15 − 8 0x00 RO Reserved

7 − RW

Port 3 MAC Mode

The RX_DV (pin 31) value is latched into this bit during power-up/reset.

1 = MAC MII mode.

0 = PHY MII mode.

6 − 4 000 RW Reserved

3 − 2 00 RW

Ingress Limit Mode

These bits determine what kinds of frames are limited and counted against ingress rate limiting as

follows:

00 = Limit and count all frames.

01 = Limit and count Broadcast, Multicast, and flooded Unicast frames.

10 = Limit and count Broadcast and Multicast frames only.

11 = Limit and count Broadcast frames only.

1 0 RW

Count Inter Frame Gap

Count IFG Bytes.

1 = Each frame’s minimum inter frame gap.

IFG bytes (12 per frame) are included in Ingress and Egress rate limiting

calculations.

0 = IFG bytes are not counted.

0 0 RW

Count Preamble

Count preamble Bytes.

1 = Each frame’s preamble bytes (8 per frame) are included in Ingress and Egress

rate limiting calculations.

0 = Preamble bytes are not counted.

Micrel, Inc.

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Port 3 Ingress Rate Control Register 0 (0x0A4 – 0x0A5): P3IRCR0

This register contains the port 3 ingress rate limiting control bits for priority 1 and priority 0.

Bit Default R/W Description

15 0 RW Reserved

14 − 8 0x00 RW

Ingress Data Rate Limit for Priority 1 Frames

Ingress priority 1 frames will be limited or discarded as shown in the Ingress or Egress Data Rate

Limits table.

Note: The default value 0x00 is full rate at 10Mbps or 100Mbps with no limit.

7 0 RW

Sample Edge of REFCLK_I clock in Port 3 RMII Mode

The REFCLK input clock sample edge control.

0 = Use the rising edge of REFCLK clock to sample the input data in RMII mode.

1 = Use the falling edge of REFCLK clock to sample the input data in RMII mode.

6 − 0 0x00 RW

Ingress Data Rate Limit for Priority 0 Frames

Ingress priority 0 frames will be limited or discarded as shown in the Ingress or Egress Data Rate

Limits table.

Note: The default value 0x00 is full rate at 10Mbps or 100Mbps with no limit.

Port 3 Ingress Rate Control Register 1 (0x0A6 – 0x0A7): P3IRCR1

This register contains the port 3 ingress rate limiting control bits for priority 3 and priority 2.

Bit Default R/W Description

15 0 RW Reserved

14 − 8 0x00 RW

Ingress Data Rate Limit for Priority 3 Frames

Ingress priority 3 frames will be limited or discarded as shown in the Ingress or Egress Data Rate

Limits table.

Note: The default value 0x00 is full rate at 10Mbps or 100Mbps with no limit.

7 0 RW Reserved

6 − 0 0x00 RW

Ingress Data Rate Limit for Priority 2 Frames

Ingress priority 2 frames will be limited or discarded as show n in the Ingress or Egress Data Rate

Limits table.

Note

: The default value 0x00 is full rate at 10Mbps or 100Mbps with no limit.

Micrel, Inc.

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Port 3 Egress Rate Control Register 0 (0x0A8 – 0x0A9): P3ERCR0

This register contains the port 3 egress rate limiting control bits for priority 1 and priority 0.

Bit Default R/W Description

15 0 RW Reserved

14 − 8 0x00 RW

Egress Data Rate Limit for Priority 1 Frames

Egress priority 1 frames will be limited or discarded as shown in the Ingress or Egress Data Rate

Limits table.

Note: The default value 0x00 is full rate at 10Mbps or 100Mbps with no limit.

7 0 RW Egress Rate Limit Control Enable

1 = Enable egre ss rate li mit co ntrol.

0 = Disable egress rate limit control.

6 − 0 0x00 RW

Egress Data Rate Limit for Priority 0 Frames

Egress priority 0 frames will be limited or discarded as shown in the Ingress or Egress Data Rate

Limits table.

Note: The default value 0x00 is full rate at 10Mbps or 100Mbps with no limit.

Port 3 Egress Rate Control Register 1 (0x0AA – 0x0AB): P3ERCR1

This register contains the port 3 egress rate limiting control bits for priority 3 and priority 2.

Bit Default R/W Description

15 0 RW

Reserved

14 − 8 0x00 RW

Egress Data Rate Limit for Priority 3 Frames

Egress priority 3 frames will be limited or discarded as shown in the Ingress or Egress Data Rate

Limits table.

Note

: The default value 0x00 is full rate at 10Mbps or 10Mbps with no limit.

7 0 RW Reserved

6 − 0 0x00 RW

Egress Data Rate Limit for Priority 2 Frames

Egress priority 2 frames will be limited or discarded as shown in the Ingress or Egress Data Rate

Limits table.

Note: The default value 0x00 is full rate at 10Mbps or 100Mbps with no limit.

Micrel, Inc.

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Switch Global Control Registers

Switch Global Control Register 8 (0x0AC – 0x0AD): SGCR8

This register contains the global control bits for the switch function.

Bit Default R/W Description

15 − 14 10 RW

Two Queue Priority Mapping

These bits determine the mapping between the priority of the incoming frames and the destination

on-chip queue in a two queue configuration which uses egress queues 0 and 1.

‘00’ = Egress Queue 1 receives priority 3 frames

Egress Queue 0 receives priority 0, 1, 2 frames

‘01’ = Egress Queue 1 receives priority 1, 2, 3 frames

Egress Queue 0 receives priority 0 frames

‘10’ = (default) Egress Queue 1 receives prior ity 2, 3 frames

Egress Queue 0 receives priority 0, 1 frames

‘11’ = Egress Queue 1 receives priority 1, 2, 3 frames

Egress Queue 0 receives priority 0 frames

13 − 11 000 RO Reserved

10 0 RW/

Flush Dynamic MAC Table

Before flushing the dynamic MAC table, switch address learning must be disabled by setting bit[8] in

the P1CR2, P2CR2 and P3CR2 registers .

9 0 RW Flush Static MAC Table

1 = Enable flush static MAC table for spann ing tree app lic atio n.

0 = Disable flush static MAC tab le for spanning tree app lic atio n.

8 0 RW Port 3 Tail-Tag Mode Enable

1 = Enable tail tag mode.

0 = Disable tail tag mode.

7 − 0 0x00 RW Force PAUSE Off Iteration Limit Time Enable

0x01 – 0xFF = Enable to force PAUSE off iteration limit time (a unit number is 160ms).

0x00 = Disable Force PAUSE O ff Iterat ion Lim it.

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Switch Global Control Register 9 (0x0AE – 0x0AF): SGCR9

This register contains the global control bits for the switch function.

Bit Default R/W Description

15 − 11 0x00 RO Reserved

10 − 8 000 RW Forwarding Invalid Frame

Define the forw arding port for frame with invalid VID. Bit[10] stands for the host port, bit[9] for port 2,

and bit[8] for port 1.

7 − 6 00 RW Reserved

5 0 RW Enable Insert Source Port PVID Tag when Untagged Frame from Port 3 to Port 2

1 = Enable.

0 = Disable.

4 0 RW Enable Insert Source Port PVID Tag when Untagged Frame from Port 3 to Port 1

1 = Enable.

0 = Disable.

3 0 RW Enable Insert Source Port PVID Tag when Untagged Frame from Port 2 to Port 3

1 = Enable.

0 = Disable.

2 0 RW Enable Insert Source Port PVID Tag when Untagged Frame from Port 2 to Port 1

1 = Enable.

0 = Disable.

1 0 RW Enable Insert Source Port PVID Tag when Untagged Frame from Port 1 to Port 3

1 = Enable.

0 = Disable.

0 0 RW Enable Insert Source Port PVID Tag when Untagged Frame from Port 1 to Port 2

1 = Enable.

0 = Disable.

Micrel, Inc.

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Source Address Filtering MAC Address Registers

Source Address Filtering MAC Address 1 Register Low (0x0B0 – 0x0B1): SAFM ACA1L

The following table shows the register bit fields for the low word of MAC Address 1.

Bit Default Value R/W Description

15 − 0 0x0000 RW Source Filtering MAC Address 1 Low

The least significant word of MAC Address 1.

Source Address Filtering MAC Address 1 Register Midd le (0x0B2 – 0x0B3): SAFMACA1M

The following table shows the register bit fields for the middle word of MAC Address 1.

Bit Default Value R/W Description

15 − 0 0x0000 RW Source Filtering MA C Address Middle 1

The middle word of MAC Address 1.

Source Address Filtering MAC Address 1 Register High (0x0B4 – 0x0B5): SAFMACA1H

The following table shows the register bit fields for the high word of MAC Address 1.

Bit Default Value R/W Description

15 − 0 0x0000 RW Source Filtering MAC Address 1 High

The most significant word of MAC Address 1.

Source Address Filtering MAC Address 2 Register Low (0x0B6 – 0x0B7): SAFM ACA2L

The following table shows the register bit fields for the low word of MAC Address 2.

Bit Default Value R/W Description

15− 0 0x0000 RW Source Filtering MAC Address Low 2

The least significant word of MAC Address 2.

Source Address Filtering MAC Address 2 Register Middle (0x0B8 – 0x0B9): SAFMACA2M

The following table shows the register bit fields for the middle word of MAC Address 2.

Bit

Default Value

R/W

Description

15 − 0 0x0000 RW Source Filtering MA C Address Middle 2

The middle word of MAC Address 2.

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Source Address Filtering MAC Address 2 Register High (0x0BA – 0x0BB): SAFMACA2H

The following table shows the register bit fields for the high word of MAC Address 2.

Bit Default Value R/W Description

15 − 0 0x0000 RW Source Filtering MA C Address High 2

The most significant word of MAC Address 2.

0x0BC – 0x0C7: Reserved

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TXQ Rate Control Registers

Port 1 TXQ Rate Control Register 1 (0x0C8 – 0x0C9): P1TXQRCR1

This register contains the q2 and q3 rate control bits for port 1.

Bit Default Value R/W Description

15 1 RW

Port 1 Transmit Queue 2 (high) Ratio Control

0 = Strict priority. Port 1 will transmit all the packets from this priority q2 before

transmit lower priority queue.

1 = Bit[14:8] reflect the number of packets allow to transmit from this priority q2

within a certain time.

14 − 8 0x04 RW Port 1 Transmit Queue 2 (high) Ratio

This ratio indicates the number of packet for high priority packet can transmit within a given

period.

7 1 RW

Port 1 Transmit Queue 3 (highest) Ratio Control

0 = Strict priority. Port 1 will transmit all the packets from this priority q3 before

transmit lower priority queue.

1 = Bit[6:0] reflect the num ber of packets allow to transmit from this priority q3

within a certain time.

6 − 0 0x08 RW Port 1 Transmit Queue 3 (highest) Ratio

This ratio indicates the number of packet for highest priority packet can transmit within a

given period.

Port 1 TXQ Rate Control Register 2 (0x0CA – 0x0CB): P1TXQRCR2

This register contains the q0 and q1 rate control bits for port 1.

Bit Default Value R/W Description

15 1 RW

Port 1 Transmit Queue 0 (lowest) Ratio Control

0 = Strict priority. Port 1 will transmit all the packets from this priority q0 after

transmit higher priority queue.

1 = Bit[14:8] reflect the number of packets allow to transmit from this priority q0

within a certain time.

14 − 8 0x01 RW Port 1 Transmit Queue 0 (lowest) Ratio

This ratio indicates the number of packet for lowes t priority packet can transmit within a given

period.

7 1 RW

Port 1 Transmit Queue 1 (low) Ratio Control

0 = Strict priority. Port 1 will transmit all the packets from this priority q1 before

transmit lower priority queue.

1 = Bit[6:0] reflect the num ber of packets allow to transmit from this priority q1

within a certain time.

6 − 0 0x02 RW Port 1 Transmit Queue 1 (low) Ratio

This ratio indicates the number of packet for low priority packet can transmit within a given

period.

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Port 2 TXQ Rate Control Register 1 (0x0CC – 0x0CD): P2TXQRCR1

This register contains the q2 and q3 rate control bits for port 2.

Bit Default Value R/W Description

15 1 RW

Port 2 Transmit Queue 2 (high) Ratio Control

0 = Strict priority. Port 2 will transmit all the packets from this priority q2 before

transmit lower priority queue.

1 = Bit[14:8] reflect the number of packets allow to transmit from this priority q2

within a certain time.

14 − 8 0x04 RW Port 2 Transmit Queue 2 (high) Ratio

This ratio indicates the number of packet for high priority packet can transmit within a given

period.

7 1 RW

Port 2 Transmit Queue 3 (highest) Ratio Control

0 = Strict priority. Port 2 will transmit all the packets from this priority q3 before

transmit lower priority queue.

1 = Bit[6:0] reflect the num ber of packets allow to transmit from this priority q3

within a certain time.

6 − 0 0x08 RW Port 2 Transmit Queue 3 (highest) Ratio

This ratio indicates the number of packet for hig hest priority packet can tr an smit within a giv en

period.

Port 2 TXQ Rate Control Register 2 (0x0CE – 0x0CF): P2TXQRCR2

This register contains the q0 and q1 rate control bits for port 2.

Bit Default Value R/W Description

15 1 RW

Port 2 Transmit Queue 0 (lowest) Ratio Control

0 = Strict priority. Port 2 will transmit all the packets from th is prior ity q0 after

transmit higher priority queue.

1 = Bit[14:8] reflect the number of packets allow to transmit from this priority q0

within a certain time.

14 − 8 0x01 RW Port 2 Transmit Queue 0 (lowest) Ratio

This ratio indicates the number of packet for lowes t priority packet can transmit within a given

period.

7 1 RW

Port 2 Transmit Queue 1 (low) Ratio Control

0 = Strict priority. Port 2 will transmit all the packets from th is prior ity q1 before

transmit lower priority queue.

1 = Bit[6:0] reflect the num ber of packets allow to transmit from this priority q1

within a certain time.

6 − 0 0x02 RW Port 2 Transmit Queue 1 (low) Ratio

This ratio indicates the number of packet for low priority packet can transmit within a given

period.

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Port 3 TXQ Rate Control Register 1 (0x0D0 – 0x0D1): P3TXQRCR1

This register contains the q2 and q3 rate control bits for port 3.

Bit Default Value R/W Description

15 1 RW

Port 3 Transmit Queue 2 (high) Ratio Control

0 = Strict priority. Port 3 will transmit all the packets from th is prior ity q2 before

transmit lower priority queue.

1 = Bit[14:8] reflect the number of packets allow to transmit from th is priority q2

within a certain time.

14 − 8 0x04 RW Port 3 Transmit Queue 2 (high) Ratio

This ratio indicates the number of packet for high priority packet can transmit within a given

period.

7 1 RW

Port 3 Transmit Queue 3 (highest) Ratio Control

0 = Strict priority. Port 3 will transmit all the packets from this priority q3 before

transmit lower priority queue.

1 = Bit[6:0] reflect the num ber of packets allow to transmit from this priority q3

within a certain time.

6 − 0 0x08 RW Port 3 Transmit Queue 3 (highest) Ratio

This ratio indicates the number of packet for highest priority packet can transmit within a given

period.

Port 3 TXQ Rate Control Register 2 (0x0D2 – 0x0D3): P3TXQRCR2

This register contains the q0 and q1 rate control bits for port 3.

Bit Default Value R/W Description

15 1 RW

Port 3 Transmit Queue 0 (lowest) Ratio Control

0 = Strict priority. Port 3 will transmit all the packets from th is prior ity q0 after

transmit higher priority queue.

1 = Bit[14:8] reflect the number of packets allow to transmit from this priority q0

within a certain time.

14 − 8 0x01 RW Port 3 Transmit Queue 0 (lowest) Ratio

This ratio indicates the number of packet for lowes t priority packet can transmit within a given

period.

7 1 RW

Port 3 Transmit Queue 1 (low) Ratio Control

0 = Strict priority. Port 3 will transmit all the packets from th is prior ity q1 before

transmit lower priority queue.

1 = Bit[6:0] reflect the number of packets allow to transmit from this priority q1

within a certain time.

6 − 0 0x02 RW Port 3 Transmit Queue 1 (low) Ratio

This ratio indicates the number of packet for low priority packet can transmit within a given

period.

0x0D4 – 0x0D5: Reserved

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Input and Output Multiplex Selection Register

Input and Output Multiplex Selection Register (0x0D6 – 0x0D7): IOMXSEL

This register is used to select the functionality of pins 59, 61, and 62. Note that further programmability of the LED

function is controlled via bits [9:8] in the SG CR7 Cont r ol regis ter .

Bit Default R/W Description

15 − 12 0x0 RO Reserved

11 1 RW Reserved

10 1 RW Selection of P2LED1 or GPIO9 on Pin 61

1 = This pin is used for P2LED1 (default).

0 = This pin is used for GPIO9.

9 1 RW Selecti on of P2LED0 or GPIO10 on Pin 62

1 = This pin is used for P2LED0 (default).

0 = This pin is used for GPIO10.

8 1 RW Selecti on of P1LED1 or GPIO7 on Pin 59

1 = This pin is used for P1LED1 (default).

0 = This pin is used for GPIO7.

7 1 RW Reserved

6 1 RW

Reserved

5 1 RW Reserved

4 1 RW Reserved

3 1 RW Reserved

2 1 RW Reserved

1 1 RW Reserved

0 1 RW Reserved

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Configuration Status and Serial Bus Mode Register

Configuration Status and Serial Bus Mode Register (0x0D8 – 0x0D9): CFGR

This r egister is us ed to s e le c t the S eria l Bus an d Fib er m ode. T he s tate of bits [1:0] are de ter mined at reset t ime using the

RXD[1:0] pins.

Bit Default R/W Description

15 − 8 0x00 RO Reserved

7 1 RW

Selection of Port 2 Mode of Operation

1 = Select copper mode

0 = Select fiber mode (bypass MLT3 encoder/decoder, scrambler and

descrambler). Valid for FML and FRL devices only.

When fiber mode is selecte d, bit[13] in DSP_CNTRL_6 (0x734 – 0x735) should be

cleared.

6 1 RW

Selection of Port 1 Mode of Operation

1 = Select copper mode

0 = Select fiber mode (bypass MLT3 encoder/decoder, scrambler and

descrambler). Valid for FML and FRL devices only.

When fiber mode is selecte d, bit [13] in DSP_CNTRL_6 (0x734 – 0x735) should be

cleared.

5 − 4 11 RO Reserved

3 – 2 11 RW Reserved

1 − 0 Strap-in value from

RXD[1:0] RW

Selection of Serial Bus Mode

00 = Reserved

01 = Reserved

10 = SPI slave Mode

11 = MIIM Mode

0x0DA – 0 x0DB : R es erv e d

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Port 1 Auto-Negotiation Registers

Port 1 Auto-Negotiation Next Page Transmit Register (0x0DC – 0x0DD): P1ANPT

This register contains the port 1 auto-negotiation next page transmit related bits.

Bit Default R/W Description

15 0 RO

Next Page (NP) is used by the Next Page function to indicate whether or not this is the last Next Page

to be transmitted. NP shall be set as follows:

1 = Additional Next Page(s) will follow.

0 = Last page.

14 0 RO Reserved

13 1 RO

Message Page

Message Page (MP) is used by the Next Page function to differentiate a Message Page from an

Unformatted Page. MP shall be set as follows:

1 = Message Page.

0 = Unformatted Page.

12 0 RO

Acknowledge 2

Acknowledge 2 (Ack2) is used by the Next Page function to indicate that a device has the ability to

comply with the message. Ack2 shall be set as follows:

1 = Able to comply with message.

0 = Unable to comply with message.

11 0 RO

Toggle

Toggle (T) is used by the arbitration function to ensure synchronization with the link partner during

Next Page exchange. This bit shall always take the opposite value of the Toggle bit in the previously

exchanged Link Codeword. The initial value of the Toggle bit in the first Next Page transmitted is the

inverse of bit [11] in the base Link Codeword and, therefore, may assume a value of logic one or zero.

The Toggle bit shall be set as follows:

1 = Previous value of the transmitted Link Codeword equal to logic zero.

0 = Previous value of the transmitted Link Codeword equal to logic one.

10 − 0 0x001 RO Mess age and Unformatted Code Field

Message/Unformatted code field bit[10:0]

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Port 1 Auto-Negotiation Link Partner Received Next Page Register (0x0DE – 0x0DF): P1ALPRNP

This register contains the port 1 auto-negotiation link partner received next page r elat ed bits .

Bit Default R/W Description

15 0 RO

Next Page (NP) is used by the Next Page function to indicate whether or not this is the last Next Page

to be transmitted. NP shall be set as follows:

1 = Additional Next Page(s) will follow.

0 = Last page.

14 0 RO

Acknowledge

Acknowledge (Ack) is used by the auto-negotiation function to indicate that a device has successfully

received its Link Partner’s Link Codeword. The Acknowledge bit is encoded in bit 14 regardless of the

value of the Selector Field or Link Codeword encoding. If no Next Page information is to be sent, this

bit shall be set to logic one in the Link Codeword after the reception of at least three consecutive and

consistent FLP Bursts (ignoring the Acknowledge bit value).

13 0 RO

Message Page

Message Page (MP) is used by the Next Page function to differentiate a Message Page from an

Unformatted Page. MP shall be set as follows:

1 = Message Page.

0 = Unformatted Page.

12 0 RO

Acknowledge 2

Acknowledge 2 (Ack2) is used by the Next Page function to indicate that a device has the ability to

comply with the message. Ack2 shall be set as follows:

1 = Able to comply with message.

0 = Unable to comply with message.

11 0 RO

Toggle

Toggle (T) is used by t he arbitration function to ensure synchronization with the link partner during

Next Page exchange. This bit shall always take the opposite value of the Toggle bit in the previously

exchanged Link Codeword. The initial value of the Toggle bit in the first Next Page transmitted is the

inverse of bit [11] in the base Link Codeword and, therefore, may assume a value of logic one or zero.

The Toggle bit shall be set as follows:

1 = Previous value of the transmitted Link Codeword equal to logic zero.

0 = Previous value of the transmitted Link Codeword equal to logic one.

10 − 0 0x000 RO Message and Unformatted Code Field

Message/Unformatted code field bit[10:0]

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Port 1 EEE Registers

Port 1 EEE and Link Partner Advertisement Register (0x0E0 – 0x0 E1) : P1EEEA

This register contains the port 1 EEE advertisement and link partner advertisement information. Note that EEE is not

supported in fiber mode.

Bit Default R/W Description

15 0 RO Reserved

14 0 RO 10GBASE-KR EEE

1 = Link Partner EEE is supported for 10GBASE-KR.

0 = Link Partner EEE is not supported for 10GBASE-KR.

13 0 RO 10GBASE-KX4 EEE

1 = Link Partner EEE is supported for 10GBASE-KX4.

0 = Link Partner EEE is not supported for 10GBASE-KX4.

12 0 RO 1000BASE-KX EEE

1 = Link Partner EEE is supported for 1000BASE-KX.

0 = Link Partner EEE is not supported for 1000BASE-KX.

11 0 RO 10GBASE-T EEE

1 = Link Partner EEE is supported for 10GBASE-T.

0 = Link Partner EEE is not supported for 10GBASE-T.

10 0 RO 1000BASE-T EEE

1 = Link Partner EEE is supported for 1000BASE-T.

0 = Link Partner EEE is not supported for 1000BASE-T.

9 0 RO 100BASE-TX EEE

1 = Link Partner EEE is supported for 100BASE-TX.

0 = Link Partner EEE is not supported for 100BASE-TX.

8 – 7 00 RO Reserved

6 0 RO 10GBASE-KR EEE

1 = Port 1 EEE is supported for 10GBASE-KR.

0 = Port 1 EEE is not supported for 10GBASE-KR.

5 0 RO 10GBASE-KX4 EEE

1 = Port 1 EEE is supported for 10GBASE-KX4.

0 = Port 1 EEE is not supported for 10GBASE-KX4.

4 0 RO 1000BASE-KX EEE

1 = Port 1 EEE is supported for 1000BASE-KX.

0 = Port 1 EEE is not supported for 1000BASE-KX.

3 0 RO 10GBASE-T EEE

1 = Port 1 EEE is supported for 10GBASE-T.

0 = Port 1 EEE is not supported for 10GBASE-T.

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Port 1 EEE and Link Partner Advertisement Register (0x0E0 – 0x0E1): P1EEEA (Continued)

Bit Default R/W Description

2 0 RO 1000BASE-T EEE

1 = Port 1 EEE is supported for 1000BASE-T.

0 = Port 1 EEE is not supported for 1000BASE-T.

1 1 RW

100BASE-TX EEE

1 = Port 1 EEE is supported for 100BASE-TX.

0 = Port 1 EEE is not supported for 100BASE-TX.

To disable EEE capability, clear the port 1 Next Page Enable bit in the PCSEEEC register (0x0F3).

0 0 RO Reserved

Port 1 EEE Wake Error Count Register (0x0E2 – 0x0 E3) : P1EEEW EC

This register contains the port 1 EEE wake error count information. Note that EEE is not supported in Fiber mode.

Bit Default Value R/W Description

15 − 0 0x0000 RW

Port 1 EEE Wake Error Count

This counter is increm ente d by each transition of lpi_wake_timer_done from FALSE to TRUE. It

means the wakeup time is longer than 20.5µs.

The value wil l be held at all ones in the case of overflow and wi ll be cleared to zero after this

Port 1 EEE Control/Status and Auto-Negotiation Expansion Register (0x0E4 – 0x0E5): P1 EE ECS

This register contains the port 1 EEE control/status and auto-negotiation expansion information. Note that EEE is not

supported in Fiber mode.

Bit Default R/W Description

15 1 RW Reserved

14 0 RO Hardware 100BT EEE Enable Status

1 = 100BT EEE is enabled by hardware-based NP exchange.

0 = 100BT EEE is disabled.

13 0 RO/LH

(Latching High)

TX LPI Received

1 = Indicates that the transmit PCS has received low power idle (LPI) signaling one or

more times since the register was last read.

0 = Indicates that the PCS has not received low power idle (LPI) signaling.

The status will be latched high and stay that way until cleared. To clear this status bit, a “1”

needs to be written to this register bit.

12 0 RO

TX LPI Indication

1 = Indicates that the transmit PCS is currently receiving low power idle (LPI) signals.

0 = Indicates that the PCS is not currently receiving low power idle (LPI) signals.

This bit will dynamically indicate the presence of the TX LPI signal.

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Port 1 EEE Control/Status and Auto-Negotiation Expansion Register (0x0E4 – 0x0E5): P1EEE CS (Continued)

Bit Default R/W Description

11 0 RO/LH

(Latching

High)

RX LPI Received

1 = Indicates that the receive PCS has received low power idle (LPI) signaling one or

more times since the register was last read.

0 = Indicates that the PCS has not received low power idle (LPI) signaling.

The status will be latched high and stay that way until cleared. To clear this status bit, a “1”

needs to be written to this register bit.

10 0 RO

RX LPI Indication

1 = Indicates that the receive PCS is currently receiving low power idle (LPI) signals.

0 = Indicates that the PCS is not currently receiving low power idle (LPI) signals.

This bit will dynamically indicate the presence of the RX LPI signal.

9 – 8 00 RW Reserved

7 0 RO Reserved

6 1 RO Received Next Page Location Able

1 = Received Next Page storage location is specif ied by bit[6:5].

0 = Received Next Page storage locat ion is not spe cif ied by bit[6:5].

5 1 RO Received Next Page Storage Location

1 = Link partner Next Pages are stored in P1ALPRNP (Reg. 0x0DE – 0x0DF).

0 = Link partner Next Pages are stored in P1ANLPR (Reg. 0x056 – 0x057).

4 0 RO/LH

(Latching

High)

Parallel Detection Fault

1 = A fault has been detected via the parallel detection function.

0 = A fault has not been detected via the parallel detection function.

This bit is cleared after read.

3 0 RO Link Partner Next Page Able

1 = Link partner is Next Page abled.

0 = Link partner is not Next Page abled.

2 0 RO Next Page Able

1 = Local device is Next Page abled.

0 = Local device is not Next Page abled.

1 0 RO/LH

(Latching

High)

Page Received

1 = A New Page has been received.

0 = A New Page has not been received.

0 0 RO Link Partner Auto-Negotiation Able

1 = Link partner is auto-negotiation abled.

0 = Link partner is not auto-negotiation abled.

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Port 1 LPI Recovery Time Counter Register

Port 1 LPI Recovery Time Counter Register (0x0E6): P1LPIRTC

This register contains the port 1 LPI recovery time counter information.

Bit Default Value R/W Description

7 − 0 0x27 (25µs) RW

Port 1 LPI Recovery Time Counter

This register specifies the time that the MAC device has to wait before it can start to send out

packets. This value should be the maximum of the LPI recovery time between local device and

remote device.

Each count is 640ns.

Buffer Load-to-LPI Control 1 Register

Buffer Loa d to L PI Control 1 Register (0x0E7): BL2LPIC1

This register contains the buffer load to LPI Control 1 information.

Bit Default Value R/W Description

7 0 RW LPI Terminated by Input Traffic Enable

1 = LPI request will be stopped if input traffic is detected.

0 = LPI request won’t be stopped by input traffic.

6 0 RO Reserved

5 − 0 0x08 RW Buffer Load Threshold for Source Port LPI Termination

This value defines the maximum buffer usage allowed for a single port before it starts to trigger

the LPI termination for the specific source port. (512 b y tes per unit)

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Port 2 Aut o -Negotiation Registers

Port 2 Auto-Negotiation Next Page Transmit Register (0x0E8 – 0x 0 E9) : P2ANPT

This register contains the port 2 auto-negotiation next page transmit related bits.

Bit Default R/W Description

15 0 RO

Next Page (NP) is used by the Next Page function to indicate whether or not this is the last Next Page

to be transmitted. NP shall be set as follows:

1 = Additional Next Page(s) will follow.

0 = Last page.

14 0 RO Reserved

13 1 RO

Message Page

Message Page (MP) is used by the Next Page function to differentiate a Message Page from an

Unformatted Page. MP shall be set as follows:

1 = Message Page.

0 = Unformatted Page.

12 0 RO

Acknowledge 2

Acknowledge 2 (Ack2) is used by the Next Page function to indicate that a device has the ability to

comply with the message. Ack2 shall be set as follows:

1 = Able to comply with message.

0 = Unable to comply with message.

11 0 RO

Toggle

Toggle (T) is used by the arbitration function to ensure synchronization with the link partner during

Next Page exchange. This bit shall always take the opposite value of the Toggle bit in the previously

exchanged Link Codeword. The initial value of the Toggle bit in the first Next Page transmitted is the

inverse of bit[11] in the base Link Codeword and, therefore, may assume a value of logic one or zero.

The Toggle bit shall be set as follows:

1 = Previous value of the transmitted Link Codeword equal to logic zero.

0 = Previous value of the transmitted Link Codeword equal to logic one.

10 − 0 0x001 RO Message and Unformatted Code Field

Message/Unformatted code field bit[10:0]

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Port 2 Auto-Negotiation Link Partner Received Next Page Register (0x0EA – 0x0EB): P2ALPRNP

This register contains the port 2 auto-negotiation link partner received next page related bits .

Bit Default R/W Description

15 0 RO

Next Page (NP) is used by the Next Page function to indicate whether or not this is the last Next Page

to be transmitted. NP shall be set as follows:

1 = Additional Next Page(s) will follow.

0 = Last page.

14 0 RO

Acknowledge

Acknowledge (Ack) is used by the auto-negotiation function to indicate that a device has successfully

received its Link Partner’s Link Codeword. The Acknowledge bit is encoded in bit [14] regardless of the

value of the Selector Field or Link Codeword encoding. If no Next Page information is to be sent, this

bit shall be set to logic one in the Link Codeword after the reception of at least three consecutive and

consistent FLP Bursts (ignoring the Acknowledge bit value).

13 0 RO

Message Page

Message Page (MP) is used by the Next Page function to differentiate a Message Page from an

Unformatted Page. MP shall be set as follows:

1 = Message Page.

0 = Unformatted Page.

12 0 RO

Acknowledge 2

Acknowledge 2 (Ack2) is used by the Next Page funct ion to indicate that a device has the ability to

comply with the message. Ack2 shall be set as follows:

1 = Able to comply with message.

0 = Unable to comply with message.

11 0 RO

Toggle

Toggle (T) is used by the arbitration function to ensure sy nchr oniz atio n with the link partner during

Next Page exchange. This bit shall always take the opposite value of the Toggle bit in the previously

exchanged Link Codeword. The initial value of the Toggle bit in the first Next Page transmitted is the

inverse of bit[11] in the base Link Codeword and, therefore, may assume a value of logic one or zero.

The Toggle bit shall be set as follows:

1 = Previous value of the transmitted Link Codeword equal to logic zero.

0 = Previous value of the transmitted Link Codeword equal to logic one.

10 − 0 0x000 RO Message and Unformatted Code Field

Message/Unformatted code field bit[10:0]

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Port 2 EEE Registers

Port 2 EEE and Link Partner Advertisement Register (0x0EC – 0x0ED): P2EEEA

This register contains the port 2 EEE advertisement and link partner advertisement information. Note that EEE is not

supported in Fiber mode. Note that EEE is not supported in Fiber mode.

Bit Default R/W Description

15 0 RO Reserved

14 0 RO 10GBASE-KR EEE

1 = Link Partner EEE is supported for 10GBASE-KR.

0 = Link Partner EEE is not supported for 10GBASE-KR.

13 0 RO 10GBASE-KX4 EEE

1 = Link Partner EEE is supported for 10GBASE-KX4.

0 = Link Partner EEE is not supported for 10GBASE-KX4.

12 0 RO 1000BASE-KX EEE

1 = Link Partner EEE is supported for 1000BASE-KX.

0 = Link Partner EEE is not supported for 1000BASE-KX.

11 0 RO 10GBASE-T EEE

1 = Link Partner EEE is supported for 10GBASE-T.

0 = Link Partner EEE is not supported for 10GBASE-T.

10 0 RO 1000BASE-T EEE

1 = Link Partner EEE is supported for 1000BASE-T.

0 = Link Partner EEE is not supported for 1000BASE-T.

9 0 RO 100BASE-TX EEE

1 = Link Partner EEE is supported for 100BASE-TX.

0 = Link Partner EEE is not supported for 100BASE-TX.

8 – 7 00 RO Reserved

6 0 RO 10GBASE-KR EEE

1 = Port 2 EEE is supported for 10GBASE-KR.

0 = Port 2 EEE is not supported for 10GBASE-KR.

5 0 RO 10GBASE-KX4 EEE

1 = Port 2 EEE is supported for 10GBASE-KX4.

0 = Port 2 EEE is not supported for 10GBASE-KX4.

4 0 RO 1000BASE-KX EEE

1 = Port 2 EEE is supported for 1000BASE-KX.

0 = Port 2 EEE is not supported for 1000BASE-KX.

3 0 RO 10GBASE-T EEE

1 = Port 2 EEE is supported for 10GBASE-T.

0 = Port 2 EEE is not supported for 10GBASE-T.

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Port 2 EEE and Link Partner Advertisement Register (0x0EC – 0x0ED): P2EEEA (Continued)

Bit Default R/W Description

2 0 RO 1000BASE-T EEE

1 = Port 2 EEE is supported for 1000BASE-T.

0 = Port 2 EEE is not supported for 1000BASE-T.

1 1 RW

100BASE-TX EEE

1 = Port 2 EEE is supported for 100BASE-TX.

0 = Port 2 EEE is not supported for 100BASE-TX.

To disable EEE capability, clear the port 2 Next Page Enable bit in the PCSEEEC register (0x0F3).

0 0 RO Reserved

Port 2 EEE Wake Error Count Register (0x0EE – 0x0EF): P2EEEWEC

This register contains the port 2 EEE wake error count information. Note that EEE is not supported in Fiber mode.

Bit Default Value R/W Description

15 − 0 0x0000 RW

Port 2 EEE Wake Error Count

This counter is increm ente d by each transition of l pi_w ake _t i mer_d one fr om FALSE to TRUE. It

means the wake-up time is longer than 20.5µs.

The value wil l be held at all ones in the case of overflow and wi ll be cleared to zero after this

Port 2 EEE Control/Status and Auto-Negotiation Expansion Register (0x0F 0 – 0x0F1): P2EEECS

This register contains the port 2 EEE control/status and auto-negotiation expansion information. Note that EEE is not

supported in Fiber mode.

Bit Default R/W Description

15 1 RW Reserved

14 0 RO Hardware 100BT EEE Enable Status

1 = 100BT EEE is enabled by hardware based NP exchange.

0 = 100BT EEE is disabled.

13 0 RO/LH

(Latching High)

TX LPI Received

1 = Indicates that the transmit PCS has received low power idle (LPI) signaling one or

more times since the register was last read.

0 = Indicates that the PCS has not received low power idle (LPI) signaling.

The status will be latched high and stay that way until cleared. To clear this status bit, a “1”

needs to be written to this register bit.

12 0 RO

TX LPI Indication

1 = Indicates that the transmit PCS is currently receiving low power idle (LPI) signals.

0 = Indicates that the PCS is not currently receiving low power idle (LPI) signals.

This bit will dynamically indicate the presence of the TX LPI signal.

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Port 2 EEE Control/Status and Auto-Negotiation Expansion Register (0x0F 0 – 0x0F1): P2EEECS (Continued)

Bit Default R/W Description

11 0 RO/LH

(Latching High)

RX LPI Received

1 = Indicates that the receive PCS has received low power idle (LPI) signaling one or

more times since the register was last read.

0 = Indicates that the PCS has not received low power idle (LPI) signaling.

The status will be latched high and stay that way until cleared. To clear this status bit, a “1”

needs to be written to this register bit.

10 0 RO

RX LPI Indication

1 = Indicates that the receive PCS is currently receiving low power idle (LPI) signals.

0 = Indicates that the PCS is not currently receiving low power idle (LPI) signals.

This bit will dynamically indicate the presence of the RX LPI signal.

9 – 8 00 RW Reserved

7 0 RO Reserved

6 1 RO Received Next Page Location Able

1 = Received Next Page storage location is specif ied by bit[6:5].

0 = Received Next Page storage locat ion is not spe cif ied by bit[6:5].

5 1 RO Received Next Page Storage Location

1 = Link partner Next Pages are stored in P2ALPRNP (Reg. 0x0EA – 0x0EB).

0 = Link partner Next Pages are stored in P2ANLPR (Reg. 0x062 – 0x063).

4 0 RO/LH

(Latching High)

Parallel Detection Fault

1 = A fault has been detected via the parallel detection function.

0 = A faul t has not been detected via the parallel detection function.

This bit is cleared after read.

3 0 RO Link Partner Next Page Able

1 = Link partner is Next Page abled.

0 = Link partner is not Next Page abled.

2 1 RO Next Page Able

1 = Local device is Next Page abled.

0 = Local device is not Next Page abled.

1 0 RO/LH

(Latching High)

Page Received

1 = A New Page has been received.

0 = A New Page has not been received.

0 0 RO Link Partner Auto-Negotiation Able

1 = Link partner is auto-negotiation abled.

0 = Link partner is not auto-negotiation abled.

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Port 2 LPI Recovery Time Counter Register

Port 2 LPI Recovery Time Counter Register (0x0F2): P2LPIRTC

This register contains the port 2 LPI recovery time counter information.

Bit Default Value R/W Description

7 − 0 0x27 (25us) RW

Port 2 LPI Recovery Time Counter

This register specifies the time that the MAC device has to wait before it can start to send out

packets. This value should be the maximum of the LPI recovery time between local device and

remote device.

Each count is 640ns.

PCS EEE Control Register

PCS EEE Control Register (0x0F3): PCSEEEC

This register contains the PCS EEE control information.

Bit Default R/W Description

7 0 RW Reserved

6 0 RW

Reserved

5 − 2 0x0 RO Reserved

1 1 RW

Port 2 Next Page Enable

1 = Enable next page exchange during auto-negotiation.

0 = Skip next page exchange during auto-negotiation.

Auto-negotiation uses next page to negotiate EEE. To disable EEE auto-negotiation on port 2, clear this

bit to zero. Restarting auto-negotiation may then be required.

0 1 RW

Port 1 Next Page Enable

1 = Enable next page exchange during auto-negotiation.

0 = Skip next page exchange during auto-negotiation.

Auto-negotiation uses next page to negotiate EEE. To disable EEE auto-negotiation on port 1, clear this

bit to zero. Restarting auto-negotiation may then be required.

Empty TXQ-to-LPI Wait Time Control Register

Empty TXQ to LPI Wait Time Control Register (0x0F4 – 0x0F5): ETLWTC

This register contains the empty TXQ to LPI wait time control information.

Bit Default Value R/W Description

15 − 0 0x03E8 RW

Empty TXQ to LPI Wait Time Control

This register specifies the time that the LPI request will be generated after a TXQ has been

empty exceeds this configured time. This is only valid when EEE 100BT i s enabled. This setting

will apply to all the three ports. The Unit is 1.3ms. The default value is 1.3 seconds (range from

1.3ms to 86 seconds)

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Buffer Load-to-LPI Control 2 Register

Buffer Loa d to L PI Control 2 Register (0x0F6 – 0x0F7): BL2LPIC2

This register contains the buffer load to LPI control 2 information.

Bit Default Value R/W Description

15 − 8 0x01 RO Reserved

7 − 0 0x40 RW Buffer Load Threshold for All Ports LPI Termination

This value defines the maximum buffer usage allowed for a single port before it starts to trigger

the LPI term ina tion for every port. (128 bytes per unit)

0x0F8 – 0x0FF: Reserved

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Internal I/O Register Space Mapping for Interrupts and Global Reset (0x100 – 0x1FF)

0x100 – 0x123: Reserved

Memory BIST Info Register (0x124 – 0x125): MBIR

This register indicates the built-in self-test results for both TX and RX memories after power-up/reset. The device should

be reset after the BIST procedure to ensure proper subsequent operation.

Bit Default Value R/W Description

15 0 RO Memory BIST Done

0 = BIST In progress

1 = BIST Done

14 − 13 00 RO Reserved.

12 − RO TXMBF TX Memory BIST Completed

0 = TX Memory built-in self-test has not completed.

1 = TX Memory built-in self-test has completed.

11 − RO TXMBFA TX Memory BIST Failed

0 = TX Memory built-in self-test has completed without failure.

1 = TX Memory built-in self-test has completed with failure.

10 − 8 − RO TXMBFC TX Memory BIST Fail Count

0 = TX Memory built-in self-test completed with no count failure.

1 = TX Memory built-in self-test encount ered a faile d count c ondition.

7 − 5 − RO Reserved.

4 − RO RXMBF RX Memory BIST Complet ed

0 = Completion has not occurred for the RX Memory built-in self-test.

1 = Indicates completion of the RX Memory built-in self-test.

3 − RO RXMBFA RX Memory BIST Failed

0 = No failure with the RX Memory built-in self-test.

1 = Indicates the RX Memory built-in self-test has failed.

2 − 0 − RO RXMBFC RX Memory BIST Test Fail Count

0 = No count failure for the RX Memory BIST.

1 = Indicates the RX Memory built−in self-test fai led cou nt.

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Global Reset Register (0x126 – 0x127): GRR

This register controls the global and PTP reset functions with information programmed by the CPU.

Bit Default Value R/W Description

15 − 4 0x000 RO Reserved.

3 0 RW Memory BIST Start

1 = Setting thi s bit will start the Me mory BIST.

0 = Setting this bit will stop the Memory BIST.

2 0 RW

PTP Module Soft Reset

1 = Setting this bit resets the 1588/PTP blocks including the timestamp input units,

the trigger output units and th e PTP clock.

0 = Software reset is inactive.

1 0 RO Reserved.

0 0 RW

Global Soft Reset

1 = Software reset is active.

0 = Software reset is inactive.

Global software reset will reset all registers to their default value. The strap−in values are not

affected. This bit is not self-clearing. After writing a “1” to this bit, wait for 10ms to elapse then

write a “0” for normal operation.

0x128 – 0x18F: Reserved

Interrupt Enable Register (0x190 – 0x191): IER

This register either enables various interrupts or indicates that the interrupts have been enabled.

Bit Default Value R/W Description

15 0 RW LCIE Link Change Interr upt Enable

1 = When this bit is set, the link change interrupt is enabled.

0 = When this bit is res et, the link change interrupt is disabled.

14 − 13 00 RO Reserved

12 0 RO

PTP Timestamp Interrupt Enable

1 = When set, this bit indicates that the PTP timestamp interrupt is enabled.

0 = When cleared, this bit indicates that the PTP timestamp interrupt is disabled.

Note that this bit is an “OR” of the PTP_TS_IE[11:0] bits. Clearing the appropriate enable bit in

the PTP_TS_IE register (0x68E – 0x68F) or clearing the appropriate status bit in the

PTP_TS_IS register (0x68C – 0x68D) will clear this bit. Always write this bit as a zero.

11 0 RO Reserved

10 0 RO

PTP Trigger Unit Interrupt Enable

1 = When set, this bit indicates that the PTP trigger output unit interrupt is enabled.

0 = When cleared, this bit indicates that the PTP trigger output unit interrupt is disabl ed.

Note that this bit is an “OR” of the PTP_TRIG_IE[11:0] bits. Clearing the appropriate enable bit

in the PTP_TRIG_IE register (0x68A – 0x68B) or clearing the appropriate status bit in the

PTP_TRIG_IS register (0x688 – 0x689) will clear this bit. Always write this bit as a zero.

9 − 4 0x00 RO Reserved

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Interrupt Enable Register (0x190 – 0x191): IER (Continued)

Bit Default Value R/W Description

3 0 RW LDIE Linkup Detect Interrupt Enable

1 = When this bit is set, the wake-up from a link up detect int err upt is enab led.

0 = When this bit is reset, the link up detect interrupt is disabled.

2 0 RW EDIE Energy Detect Interrupt Enable

1 = When this bit is set, the wake-up from energy detect interrupt is enabled.

0 = When this bit is reset, the energy detect interrupt is disabled.

1 0 RO Reserved.

0 0 RO Reserved

Interrupt Status Register (0x192 – 0x193): ISR

This register contains the status bits for all interrupt sources. When the corresponding enable bit is set, it causes the

interrupt pin to be asserted. This register is usually read by the host CPU and device drivers during an interrupt service

routine or polling. The register bits are not cleared when read. To clear the bits, the user has to either write a “1” to a

specific bit to clear it, or write a “1” to another bit in another specified register to clear it.

Bit Default Value R/W Description

15 0 RO (W1C)

LCIS Link Change Interrupt St atus

When this bit is set, it indicates that the link status has changed from link up to link down,

or link down to link up.

This edge-triggered interrupt status is cleared by writing a “1“ to this bit.

14 − 13 00 RO Reserved

12 0 RO

PTP Timestamp Interrupt Status

When this bit is set, it indicates that one of 12 timestamp input units is ready (TS_RDY =

“1”) and an event has b een ca ptured, or the egress timestamp is available from either

port 1 or port 2.

This edge-triggered interrupt status is cleared by writing a “1“ to this bit.

11 0 RO Reserved

10 0 RO PTP Trigger Unit Interrupt Status

When this bit is s et, it indicates that one of 12 trigger output units is done or has an error.

This edge-triggered interrupt status is cleared by writing a “1” to this bit.

9 − 4 0x00 RO Reserved

3 0 RO LDIS Linkup Detect Interrupt Status

When this bit is s et, it indicates that wake-up from linkup detect status has occurred.

Write 0010 to PMCTRL[5:2] to clear this bit.

2 0 RO EDIS Energy Detect Interrupt Status

When this bit is s et, it indicates that wake-up from energy detect status has occurred.

Write 0001 to PMCTRL[5:2] to clear this bit.

1 − 0 00 RO Reserved

0x194 – 0x1FF: Reserved

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Internal I/O Register Space Mapping for Trigger Output Units (12 Units, 0x200 – 0x3FF)

Trigger Error Register (0x200 – 0x201): TRIG_ERR

This register contains the trigger output unit error status.

Bit Default R/W Description

15 − 12 0x0 RO Reserved

11 − 0 0x000 RO

Trigger Output Unit Error

1 = The trigger time is set earlier than the system time clock when TRIG_NOTIFY

bit is set to “1” in TRIG_CFG1 register and it will generate interrupt to host if

interrupt enable bit is set in PTP_TRIG_IE register. This bit can be cleared by

resetting the TRIG_EN bit to “0”.

0 = No trigger output unit error.

There are 12 trigger outp ut units and therefore there is a corresponding Error bit for each of the

trigger output units, bit[11:0] = unit[12:1].

Trigger Active Register (0x202 – 0x203): TRIG_ACTIVE

This register contains the trigger output unit active status.

Bit

Default

R/W

Description

15 − 12 0x0 RO Reserved

11 − 0 0x000 RO

Trigger Output Unit Active

1 = The tri gger outp ut unit is enabled and active without error.

0 = The tri gger outp ut unit is finished and inactive.

There are 12 trigger outp ut units and therefore there is a corresponding active bit for each of the

trigger output units, bit[11:0] = unit[12:1].

Trigger Done Register (0x204 – 0x205): TRIG_DONE

This register contains the trigger output unit event done status.

Bit Default R/W Description

15 − 12 0x0 RO Reserved

11 − 0 0x000 RO

(W1C)

Trigger Output Unit Event Done

1 = The tri gger outp ut unit event has been generated when TRIG_NOTIFY bit is

set to “1” in TRIG_CFG1 register (write “1” to clear this bit) and it will generate

interrupt to host if interrupt enable bit is set in PTP_TRIG_IE register.

0 = The tri gger outp ut unit event is not generated.

There are 12 trigger outp ut units and therefore there is a corres ponding Done bit for each of the

trigger output units, bit[11:0] = unit[12:1].

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Trigger Enable Register (0x206 – 0x207): TRIG_EN

This register contains the trigger output unit enable control bits.

Bit Default R/W Description

15 − 12 0x0 RO Reserved

11 − 0 0x000 RW

Trigger Output Unit Enable

1 = Enables the selected trigger output unit and w ill sel f -clear when the

trigger output is generated. In cascade mode, only enable the head of trigger

unit.

0 = The tri gger outp ut unit is disable d.

There are 12 trigger outp ut units and therefore there is a corresponding enable bit for each of the

trigger output units, bit[11:0] = unit[12:1].

Trigger Software Reset Register (0x208 – 0x209): TRIG_SW_RST

This register contains the software reset bits for the trigger output units.

Bit Default R/W Description

15 − 12 0x0 RO Reserved

11 − 0 0x000 RW/SC

Trigger Output Unit Software Reset

1 = When set, the selected trigger output unit is put into the inactive state and

default setting. This can be used to stop the cascade mode in continuous

operat ion and prep ar e the sele cte d trigger unit for the next operation.

0 = While zero, the selected trigger output unit is in normal operating mode .

There are 12 trigger outp ut units and therefore there is a corresponding software reset bit for each

of the trigger output units, bit[11:0] = unit[12:1].

Trigger Output Unit 12 Output PPS Pulse-Width Register (0x20A – 0x20B): TRIG12_PPS_WIDTH

This register contains the trigger output unit 12 PPS pulse width and trigger output unit 1 path delay compensation.

Bit Default R/W Description

15 − 12 0x0 RO Reserved

11 0 RW Reserved

10 − 8 000 RW Path Delay Compensation for Trigger Output Unit 1

These three bits are used to compensate the path delay of clock skew for event trigger output unit 1

in the range of 0 ~ 7ns (bit[11] = “1”) or 0 ~ 28 ns (bit[11] = “0”).

7 − 0 0x00 RW PPS Pulse Width for Trigger Output Unit 12

This is upper third byte [23:16] in conjunction with the unit 12 trigger output pulse width in

TRIG12_CFG_2[15:0] (0x38A) register to make this register value for PPS pulse width up to 134ms.

0x20C – 0x21F: Reserved

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Trigger Output Unit 1 Target Time in Nanoseconds Low-Word Register (0x220 – 0x221): TRIG1_TGT_NSL

This register contains the trigger output unit 1 target time in nanoseconds low-word.

Bit Default R/W Description

15 − 0 0x0000 RW Trigger Output Unit 1Target Time in Nanoseconds Low-Word [15:0]

This is low-word of target time for trigger output unit 1 in nanoseconds.

Trigger Output Unit 1 Target Time in Nanoseconds High-Word Register (0x222 – 0x223): TRIG1_TGT_NSH

This register contains the trigger output unit 1 target time in nanoseconds high-word.

Bit

Default

R/W

Description

15 − 14 00 RO Reserved

13 − 0 0x0000 RW Trigger Output Unit 1Target Time in Nanoseconds High-Word [29:16]

This is high-word of target time for trigger output unit 1 in nanoseconds.

Trigger Output Unit 1 Target Time in Seconds Low-Word Register (0x224 – 0x225): TRIG1_TGT_SL

This register contains the trigger output unit 1 target time in seconds low-word.

Bit Default R/W Description

15 − 0 0x0000 RW Trigger Output Unit 1Target Time in Seconds Low-Word [15:0]

This is low-word of target time for trigger output unit 1 in seconds.

Trigger Output Unit 1 Target Time in Seconds High-Word Register (0x226 – 0x227): TRIG1_TGT_SH

This register contains the trigger output unit 1 target time in seconds high-word.

Bit Default R/W Description

15 − 0 0x0000 RW Trigger Output Unit 1 Target Time in Seconds High-Word [31:16]

This is high-word of target time for trigger output unit 1 in seconds.

Trigger Output Unit 1 Configuration and Control Register 1 (0x228 – 0x229): TRIG1_CFG_1

This register (1 of 8) contains the trigger output unit 1 configuration and control bits.

Bit Default R/W Description

15 0 RW Enable This Trigger Output Unit in Cascade Mode

1 = Enable this trigger output unit in cascade mode.

0 = disable this trigger output unit in cascade mode.

14 0 RW

Indicate a Tail Unit for This Trigger Output Unit in Cascade Mode

1 = This trigger output unit is the last unit of the chain in cascade mode.

0 = This trigger output unit is not the last unit of a chain in cascade mode.

Note: When this bit is set “0” in all CFG_1 trigger unit s, and all units are in

cascade mode, the iteration count is ignored and it becomes infinite. To stop

the infin ite loo p, set the respective bit[11:0] in TRIG_SW_RST register.

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Trigger Output Unit 1 Configuration and Contro l Register 1 (0x228 – 0x229): TRIG1_CFG_1 (Continued)

Bit Default R/W Description

13 − 10 0xF RW

Select Upstr eam Tri gger Unit in Cascade Mode

These bits are used to select one of the 12 upstream trigger output units in Cascade mode.

Note that 0x0 indicates TOU1, and 0xB indicates TOU12. (0xC to 0xF are not used.) For example, if

units 1, 2 and 3 (tail unit) are set up in cascade mode, then these 4 bits are set as follows at the three

trigger output units: unit 1 is set to 0x2 (indicates TOU3), at unit 2 is set to 0x0 (indicates TOU1) and

at unit 3 is to set 0x1 (indicates TOU2).

9 0 RW

Trigger Now

1 = Immediately create the trigger output if the trigger target time is less than

the system time clock.

0 = Wait for the trigger target time to occur to trigger the event output.

8 0 RW

Trigger Notify

1 = Enable reporting both TRIG_DONE and TRIG_ERR status as well as

interrupt to host if the interrupt enable bit is set in the TRIG_IE register.

0 = Disable reporting both TRIG_DONE and TRIG_ERR status.

7 0 RO Reserved

6 − 4 000 RW

Trigger Output Signal Pattern

This field is used to select the trigger output signal pattern when TRIG_EN = “1” and trigger target

time has reached the system time:

000: TRIG_NEG_EDGE - Generates negative edge (from default “H” -> “L” and

stays “L”).

001: TRIG_POS_EDGE - Generates positive edge (from default “L” -> “H” and

stays “H”).

010: TRIG_NEG_PULSE - Generates negative pulse (from default “H” -> “L” pulse

-> “H” and stays “H”). The pulse width is defined in TRIG1_CFG_2 register.

011: TRIG_POS_PULSE - Generates positive pulse (from default “L” -> “H” pulse -

> “L” and stays “L)”. The pulse width is defined in TRIG1_CFG_2 register.

100: TRIG_NEG_CYCLE - Generates negative periodic signal. The “L” pulse wi dth

is defined in TRIG1_CFG_2 register, the cycle width is defined in

TRIG1_CFG_3/4 registers and the number of cycles is defined in

TRIG1_CFG_5 register (it is an infinite number if this register value is zero).

101: TRIG_POS_CYCLE - Generates positive periodic signal. The “H” pulse width

is defined in TRIG1_CFG_2 register, the cycle width is defined in

TRIG1_CFG_3/4 registers and the number of cycles is defined in

TRIG1_CFG_5 register (it is an infinite number if this register value is zero).

110: TRIG_REG_OUTPUT - Generates an output signal from a 16-bit register.

This 16-bit register bit-pattern in TRIG1_CFG_6 is shifted LSB bit first and

looped, each bit width is defined in TRIG1_CFG_3/4 registers and total

number of bits to shift out is defined in TRIG1_CFG_5 register (it is an

infinite number if this register value is zero).

111: Reserved

Note: the maximum output clock frequency is up to 12.5MHz.

3 − 0 0x0 RW

Select GPIO[11:0] for This Trigger Output Unit

Associate one of the 12 GPIO pins to thi s trigger output unit. The trigger output sig nal s are O R ’ed

together to for m a combined si gnal if mult ipl e trigger outp ut units have selected the same GPIO output

pin.

0x0 indicates GPIO0, and 0xB indicates GPIO11. (0xC to 0xF are not used.)

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Trigger Output Unit 1 Configuration and Control Register 2 (0x22A – 0x22B ): T RI G1_CF G _2

This register (2 of 8) contains the trigger output unit 1 configuration and control bits.

Bit Default R/W Description

15 − 0 0x0000 RW

Trigger Output Pulse Width

This number defines the width of the generated pulse or periodic signal from this trigger output unit. Its

unit value is equal to 8ns. For exam ple, the pulse width is 80ns if this register value is 10 (0xA).

Iteration Count

This number defines the iteration count for register trigger output pattern (TRIG1_CFG_6) in cascade

mode when this trigger outp ut unit is the tail unit. For example, 0x0000 = 1 count and 0x000F = 16

counts. It is an infinite number if there is no tail unit in Cascade mode.

Trigger Output Unit 1 Configuration and Control Register 3 (0x22C – 0x22D ): T RI G1_CF G _3

This register (3 of 8) contains the trigger output Unit 1 configuration and control bits.

Bit Default R/W Description

15 − 0 0x0000 RW

Trigger Output Cycle Width or Bit Width Low-Word [15:0]

To define cycle width for generating periodic signal or to define each bit width in TRIG1_CFG_8. A unit

number of value equals to 1ns. For example, the cycle or bit width is 80 ns if this register value is 80

(0x50) and next register value = 0x0000.

Trigger Output Unit 1 Configuration and Control Register 4 (0x22E – 0x22F) : TRIG1_CF G_4

This register (4 of 8) contains the trigger output unit 1 configur at ion and control bits.

Bit Default R/W Description

15 − 0 0x0000 RW Trigger Output Cycle Width or Bit Width High-Word [31:16]

This number defines the cycle width when generating periodic signals using this trigger output unit.

Also, it is used to define each bit width in TRIG1_CFG_8. Each unit is equal to 1ns.

Trigger Output Unit 1 Configuration and Control Register 5 (0x230 – 0x231): TRIG1_CFG_5

This register (5 of 8) contains the trigger output unit 1 configuration and control bits.

Bit Default R/W Description

15 − 0 0x0000 RW

Trigger Output Cycle Count

This number defines the quantity of cycles of the periodic signal output by the trigger output unit. Use

a value of zero for infinite repetition. Valid for TRIG_NEG_CYCLE and TRIG_POS_CYCLE modes.

Bit Count

This number can define the number of bits that are output when generating output signals from the bit

pattern register. It is an infinite number if this register value is zero. Valid for TRIG_REG_OUTPUT

mode.

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Trigger Output Unit 1 Configuration and Control Register 6 (0x232 – 0x233): TRIG1_CFG_6

This register (6 of 8) contains the trigger output unit 1 configuration and control bits.

Bit Default R/W Description

15 − 0 0x0000 RW

Trigger Output Unit Bit Pattern

This register is used to define the output bit pattern when the TRIG_REG_OUTPUT mode is selected.

Iteration Count

This register is used as the iteration count for the trigger output unit when the tail unit is in cascade

mode but not using register mode. It i s the number of cycles programmed in CFG_5 to be output by

the trigger outp ut unit. For example, 0x0000 =1 count, 0x000F =16 counts. An infinite number of cycles

will occur if there is no tail unit in Cascade mode.

Trigger Output Unit 1 Configuration and Control Register 7 (0x234 – 0x235): TRIG1_CFG_7

This register (7 of 8) contains the trigger output unit 1 configuration and control bits.

Bit Default R/W Description

15 − 0 0x0000 RW

Trigger Output Iteration Cycle Time in Cascade Mode Low-Word [15:0]

The value in this pair of registers defines the iteration cycle time for the trigger output unit in cascad e

mode. This value will be added to the current trigger target time for establishing the next trigger time

for the trigger output unit. A unit number of value equals to 1ns. For example, the cycle is 800ns if this

output cycle count (CFG_5) x waveform cycle time must be less than the iteration cycle time specified

in CFG_7 and CFG_8.

Trigger Output Unit 1 Configuration and Control Register 8 (0x236 – 0x237): TRIG1_CFG_8

This register (8 of 8) contains the trigger output unit 1 configuration and control bits.

Bit Default R/W Description

15 − 0 0x0000 RW

Trigger Output Iteration Cycle Time in Cascade Mode High-Word [31:16]

The value in this pair of registers defines the iteration cycle time for the trigger outpu t unit in cascade

mode. This value will be added to the current trigger target time for establishing the next trigger time

for the trigger output unit. A unit number of value equals 1ns.

0x238 – 0x23F: Reserved

Trigger Output Unit 2 Target Time and Output Conf iguration/Control Registers (0x240 – 0x257)

These 12 registers contain the trigger output unit 2 target time and configuration/control bits, TRIG2_CFG_[1:8]. See

descripti ons in the T rigger O utput Unit 1 Register s (0x 220 – 0x237). Note that th er e is one bit that is diff erent in this set of

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Trigger Output Unit 2 Configuration and Control Register 1 (0x248 – 0x249): TRIG2_CFG_1

This register contains the trigger output unit 2 configuration and control bits.

Bit Default R/W Description

7 0 RW

Trigger Unit 2 Clock Edge Output Select

This bit is used to select either the positive edge or negativ e edge of the 125MHz to clock out the tr ig ger

unit 2 output. This bit onl y pertains to usage with GPIO1 pin. This bit will not function with any other GPIO

pin.

1 = Use negative edge of 125MHz clock to clock out data

0 = Use positive edge of 125MHz clock to clock out data

0x258 – 0x25F: Reserved

Trigger Output Unit 3 Target Time and Output Configuration/Control Registers (0x260 – 0x277)

These 12 registers contain the trigger output unit 3 target time and configuration/control bits, TRIG3_CFG_[1:8]. See

descriptions in the Trigger O utput Unit 1 Registers (0x220 – 0x237).

0x278 – 0x27F: Reserved

Trigger Output Unit 4 Target Time and Output Conf iguration/Control Registers (0x280 – 0x297)

These 12 registers contain the trigger output unit 4 target time and configuration/control bits, TRIG4_CFG_[1:8]. See

descriptions in the Trigger O utput Unit 1 Registers (0x220 – 0x237).

0x298 – 0x29F: Reserved

Trigger Output Unit 5 Target Time and Output Configuration/Co n trol Registers (0x2A 0 – 0x2B7)

These 12 registers contain the trigger output unit 5 target time and configuration/control bits, TRIG5_CFG_[1:8]. See

descriptions in the Trigger O utput Unit 1 Registers (0x220 – 0x237).

0x2B8 – 0x2BF: Reserved

Trigger Output Unit 6 Target Time and Output Configuration/Co n trol Registers (0x2C 0 – 0x2D7)

These 12 registers contain the trigger output unit 6 target time and configuration/control bits, TRIG6_CFG_[1:8]. See

descriptions in the Trigger O utput Unit 1 Registers (0x220 – 0x237).

0x2D8 – 0x2DF: Reserved

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Trigger Output Unit 7 Target Time and Output Configuration/Control Registers (0x2E0 – 0x2F7)

These 12 registers contain the trigger output unit 7 target time and configuration/control bits, TRIG7_CFG_[1:8]. See

descriptions in the Trigger O utput Unit 1 Registers (0x220 – 0x237).

0x2F8 – 0x2FF: Reserved

Trigger Output Unit 8 Target Time and Output Conf iguration/Control Registers (0x300 – 0x317)

These 12 registers contain the trigger output unit 8 target time and configuration/control bits, TRIG8_CFG_[1:8]. See

descriptions in the Trigger O utput Unit 1 Registers (0x220 – 0x237).

0x318 – 0x31F: Reserved

Trigger Output Unit 9 Target Time and Output Configuration/Control Registers (0x320 – 0x337)

These 12 registers contain the trigger output unit 9 target time and configuration/control bits, TRIG9_CFG_[1:8]. See

descriptions in the Trigger O utput Unit 1 Registers (0x220 – 0x237).

0x338 – 0x33F: Reserved

Trigger Output Unit 10 Target Time and Output Configuration/Control Registers (0x340 – 0x357)

These 12 registers contain the trigger output unit 10 target time and configuration/control bits, TRIG10_CFG_[1:8]. See

descriptions in the Trigger O utput Unit 1 Registers (0x220 – 0x237).

0x358 – 0x35F: Reserved

Trigger Output Unit 11 Target Time and Output Config u ration/Control Registers (0x360 – 0x377)

These 12 registers contain the trigger output unit 11 target time and configuration/control bits, TRIG11_CFG_[1:8]. See

descriptions in the Trigger O utput Unit 1 Registers (0x220 – 0x237).

0x378 – 0x37F: Reserved

Trigger Output Unit 12 Target Time and Output Config u ration/Contr o l Registers (0x380 – 0x397)

These 12 registers contain the trigger output unit 12 target time and configuration/control bits, TRIG12_CFG_[1:8]. See

descriptions in the Trigger O utput Unit 1 Registers (0x220 – 0x237).

0x398 – 0x3FF: Reserved

Micrel, Inc.

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203 Revision 1.0

Internal I/O Register Space Mapping for PTP Timestamp Inputs

(12 Units, 0x400

−

0x5FF)

Timestamp Ready Register (0x400 – 0x401): TS_RDY

This register contains the PTP timestamp input unit ready-to-read status bits.

Bit Default R/W Description

15 − 12 0x0 RO Reserved

11 − 0 0x000 RO

Timestamp Input Unit Ready

1 = This timestamp input unit is ready to read and will generate a timestamp

interrupt if PTP_TS_IE = “1”. This bit will clear when TS_EN is disabled.

0 = This timestamp input unit is not ready to read or disabled.

There are 12 timestamp units and therefore there is a corresponding timestamp input ready bit for

each of the timestamp units, bit[11:0] = unit[12:1].

Timestamp Enable Register (0x402 – 0x403): TS_EN

This register contains the PTP timestamp input unit enable control bits.

Bit Default R/W Description

15 − 12 0x0 RO Reserved

11 − 0 0x000 RW

Timestamp Input Unit Enable

1 = Enable the selected time st amp inpu t unit. Writing a ”1” to this bit will clear

the TS[12:1]_EVENT_DET_CNT.

0 = Disable the selected timestamp inp ut unit. Writing a “0” to this bit will clear

the TS_RDY and TS[12:1]_DET_CNT_OVFL.

There are 12 timestamp units and therefore there is a corresponding timesta mp inp ut unit enable bit

for each of the timestamp units, bit[11:0] = unit[12:1].

Timestamp Software Reset Register (0x404 – 0x405): TS_SW_RST

This register contains the PTP timestamp input unit software reset control bits.

Bit Default R/W Description

15 − 12 0x0 RO Reserved

11 − 0 0x000 RW/SC

Timestamp Input Unit Software Reset

1 = Reset the selected timestamp inpu t unit to inactive state and default setting.

0 = The selected timestamp input unit is in normal mode of operation.

There are 12 timestamp units and therefore there is a corresponding timesta mp inp ut unit software

reset bit for each of the timest amp units, bit[11:0] = unit[12:1].

0x406 – 0x41F: Reserved

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Timestamp Unit 1 Status Register (0x420 – 0x421): TS1_STATUS

This register contains PTP timestamp input unit 1 status.

Bit Default R/W Description

15 − 5 0x000 RO Reserved

4 − 1 0x0 RO

Number of Detected Event Count for Timestamp Input Unit 1 (TS1_EVENT_DET_CNT)

This field is used to report the number of detected events (either rising or falling edge) count. in single

mode, it can detect up to 15 events in any single timestamp input unit. in cascade mode, it can detect

up to two events in timestam p input units 1-11 or up to 8 events at timestamp input unit 12 as a non-

tail unit, and it can detect up to 15 events for any timestamp input unit as a tail unit. Pulses or edges

can be detected up to 25MHz. The pulse width can be measured by the difference between

consecutive timestamps in the same timest amp input unit.

0 0 RO

Number of Detected Event Count Overflow for Timestamp Input Unit 1 (TS1_DET_CNT_OVFL)

1 = The number of detected event (either rising or falling edge) count has overflowed.

In cascade mode, only tail unit will set this bit when overflow is occurred. The

TS1_EVENT_DET_CNT will stay at 15 when overflow is occurred.

0 = The number of events (either rising or falling edge) detected count has not overflowed.

Timestamp Unit 1 Configuration and Control Register (0x422 – 0x423): TS1_CFG

This register contains PTP timestamp input unit 1 configuration and control bits.

Bit Default R/W Description

15 − 12 0x0 RO Reserved

11 − 8 0x0 RW Select GPIO[11:0] for Timestamp Unit 1

This field is used to select one of the 12 GPIO pins to serve this timestamp unit. It is GPIO0 if these

bits = “0000” and it is GPIO11 if these bits = “1011” (from “1100” to “1111” are not used).

7 0 RW Enable Rising Edge Detection

1 = Enable rising edge detection.

0 = Disable rising edge detection.

6 0 RW Enable Falling Edge Detection

1 = Enable falling edge detection.

0 = Disable falling edge detection.

5 0 RW Select Tail Unit for this Timestamp Unit in Cascade Mode

1 = This timestamp unit is the last unit of the chain in cascade mode.

0 = This timestamp unit is not the last unit of the chain in cascade mode.

4 − 1 0x0 RW

Select Upstream Timestamp Done Unit in Cascade Mode

This is used to select one of the 12 upstream timestamps units for done input in cascade mode. For

example, if units 1 (head unit), 2 and 3 (tail unit) are set up in cascade mode, then these 4-bits at unit

1 are set to 0x0, at unit 2 are set to 0x1, at unit 3 are set to 0x2.

0 0 RW Enable This Timestamp Unit in Cascade Mode

1 = Enable the selected time st amp inpu t unit in Cascade mode.

0 = Disable the timesta m p input unit in Cascade mode.

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Timestamp Unit 1 Input 1st Sample Time in Nanoseconds Low-Word Register (0x424 – 0x425): TS1_SMPL1_NSL

This register contains the first sample time in nanoseconds low-word (the resolution of 40 ns) for PTP timestamp unit 1.

Bit Default R/W Description

15 − 0 0x0000 RO 1

Sample Time in Ns Low-Word [15:0] Timestamp Unit 1

This is the low-word of first sample time for timestamp unit 1 in nanoseconds.

Timestamp Unit 1 Input 1st Sample Time in Nanoseconds High-Word Register (0x426 – 0x427): TS1_SMPL1_NSH

This register contains the first sample time in nanoseconds high-word and edge detection status for PTP timestamp

unit 1.

Bit Default R/W Description

15 0 RO Reserved

14 0 RO 1st Sample Edge Indication for Timestamp Unit 1

0 = Indicates the event is a fall ing edge sig nal .

1 = Indicates the event is a rising edge signal.

13 − 0 0x0000 RO 1

Sample Time in Ns High-Word [29:16] for Timestamp Unit 1

This is the high-word of first sample time for timestamp unit 1 in nanoseconds.

Timestamp Unit 1 Input 1st Sample Time in Seconds Low-Word Register (0x428 – 0x429): TS1_SMPL1_SL

This register contains the first sample time in seconds lo w-word for PTP timestamp unit 1.

Bit Default R/W Description

15 − 0 0x0000 RO 1

Sample Time in Seconds Lo w-Word [15:0] for Timestamp Unit 1

This is the low-word of first sample time for timestamp unit 1 in seconds.

Timestamp Unit 1 Input 1st Sample Time in Seconds High-Word Register (0x42A – 0x42B): TS1_SMPL1_SH

This register contains the first sample time in seconds high-word for PTP timestamp unit 1.

Bit Default R/W Description

15 − 0 0x0000 RO 1

Sample Time in Seconds High-Word [31:16] for Timestamp Unit 1

This is the high-word of first sample time for timestamp unit 1 in seconds.

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Timestamp Unit 1 Input 1st Sample Time in Sub-Nanoseconds Register (0x42C – 0x42D): TS1_SMPL1_SUB_NS

This register contains the first sample time in sub-8 nanoseconds (the resolution of 8ns) for PTP timestamp unit 1.

Bit Default R/W Description

15 − 3 0x0000 RO Reserved

2 − 0 000 RO

1st Sample Time in Sub-8 Nanoseconds for Timestamp Unit 1

These bits indicate one of the 8 ns cycles for the first sample time for timestamp unit 1.

000: 0 ns (sample time at the first 8 ns cycle in 25MHz/40 ns)

001: 8 ns (sample time at the sec ond 8 ns cycle in 25MHz/40 ns)

010: 16 ns (sample time at the third 8 ns cycle in 25MHz/40 ns)

011: 24 ns (sample time at the fourth 8 ns cycle in 25MHz/40 ns)

100: 32 ns (sample time at the fifth 8 ns cycle in 25MHz/40 ns)

101-111: NA

0x42E – 0x433: Reserved

Timestamp Unit 1 Input 2nd Sample Time in Nanoseconds L o w-Word Register (0x434 – 0x435): TS1_SMPL2_NSL

This register contains the second sample time in nanoseconds low-word (the res olution of 40ns) for PT P timestamp Unit

Bit Default R/W Description

15 − 0 0x0000 RO 2nd Sample Time in Nanoseconds for Low -Word [15:0] for Timestamp Unit 1

This is the low-word of the 2nd sample time for timestamp unit 1 in nanoseconds.

Timestamp Unit 1 Input 2nd Sample Time in Nanoseconds High-Word Register (0x436 – 0x437): TS1_SMPL2_NSH

This register contains the 2nd sample time in nanoseconds high-word and edge detection status for the PTP timestamp

unit 1.

Bit Default R/W Description

15 0 RO Reserved

14 0 RO 2

Sample Edge Indication f or Timestamp Unit 1

0 = Indicates the event is a falling edge signal.

1 = Indicates the event is a rising edge signal.

13 − 0 0x0000 RO 2nd Sample Time in Nanoseconds High-Word [29:16] for Timestamp Unit 1

This is the high-word of the 2nd sample time for timestamp unit 1 in nanoseconds.

Timestamp Unit 1 Input 2nd Sample Time in Seconds Low-Word Register (0x438 – 0x439): TS1_SMPL2_SL

This register contains the 2nd sample time in seconds low-word for PTP timestamp unit 1.

Bit Default R/W Description

15 − 0 0x0000 RO 2nd Sample Time in Seconds Low-Word [15:0] for Timestamp Unit 1

This is the low-word of the second sample time for timestamp unit 1 in seconds.

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Timestamp Unit 1 Input 2nd Sample Time in Seconds High-Word Re g ister (0x43A – 0x43B): TS1_SMPL2_SH

This register contains the 2nd sample time in seconds high-word for PTP timestamp unit 1.

Bit Default R/W Description

15 − 0 0x0000 RO 2

Sample Time in Seconds High-Word [31:16] for Timestamp Unit 1

This is the high-word of the second sample time for timestamp unit 1 in seconds.

Timestamp Unit 1 Input 2nd Sample Time in Sub-Nanoseconds Register (0x43C – 0x43D): TS1_SMPL2_SUB_NS

This register contains the 2nd sample time in sub-8 nanoseconds (the resolution of 8ns) for PTP timestamp unit 1.

Bit

Default

R/W

Description

15 − 3 0x0000 RO Reserved

2 − 0 000 RO

2nd Sample Time in Sub-8 Nanoseconds for Timestamp Unit 1

These bits indicate one of the 8ns cycle for the second sample time for timestamp unit 1.

000: 0ns (sample time at the first 8ns cycle in 25MHz/40ns)

001: 8ns (sample time at the secon d 8ns cycle in 25MHz/40ns)

010: 16ns (sample time at the third 8ns cycle in 25MHz/40ns)

011: 24ns (sample time at the fourth 8ns cycle in 25MHz/40ns)

100: 32ns (sample time at the fifth 8ns cycle in 25MHz/40ns)

101-111: NA

0x43E – 0x43F: Reserved

Timestamp Unit 2 Status/Configuration/Control and Input 1st Sample Time Registers (0x440 – 0x44D)

These seven regis ters contain t he first sam ple time and status /configura tion/con trol inform ation for PT P timestam p unit 2.

See description in timestamp unit 1 (0x420 – 0x42D).

0x44E – 0x453: Reserved

Timestamp Unit 2 Input 2nd Sample Time Registers (0x454 – 0x45D)

These five register s cont ai n the second sample time for PTP timestamp unit 2. See descript ion in timestamp unit 1 (0x434

– 0x43D).

0x45E – 0x45F: Reserved

Timestamp Unit 3 Status/Configuration/Control and Input 1st Sample Time Registers (0x460 – 0x46D)

These s even register s contain the first sample tim e and status /configura tion/contr ol inform ation for PT P timestamp unit 3.

See description in timestamp unit 1 (0x420 – 0x42D).

0x46E – 0x473: Reserved

Timestamp Unit 3 Input 2nd Sample Time Registers (0x474 – 0x47D)

These f ive registers cont ain the 2nd sam ple time for PT P timestamp unit 3. See description in timestamp unit 1 (0x 434 –

0x43D).

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0x47E – 0x47F: Reserved

Timestamp Unit 4 Status/Configuration/Control and Input 1st Sample Time Registers (0x480 – 0x48D)

These seven registers contain the1st sample time and status/configuration/control information for PTP timestamp unit 4.

See description in timestamp unit 1 (0x420 – 0x42D).

0x48E – 0x493: Reserved

Timestamp Unit 4 Input 2nd Sample Time Registers (0x494 – 0x49D)

These five registers contain the 2nd sample time for PTP timestamp unit 4 input. See description in timestamp unit 1

(0x434 – 0x43D).

0x49E – 0x49F: Reserved

Timestamp Unit 5 Status/Configuration/Control and Input 1st Sample Time Registers (0x4A0 – 0x4AD)

These seven registers contain the 1st sample time and status/configuration/control information for PTP timestamp unit 5.

See description in timestamp unit 1 (0x420 – 0x42D).

0x4AE – 0x4B3: Reserved

Timestamp Unit 5 Input 2nd Sample Time Registers (0x4B4 – 0x4BD)

These five registers contain the 2nd sample time for PTP timestamp unit 5. See description in timestamp unit 1 (0x434 –

0x43D).

0x4BE – 0x4BF: Reserved

Timestamp Unit 6 Status/Configuration/Control and Input 1st Sample Time Registers (0x4C0 – 0x4CD)

These seven registers contain the 1st sample time and status/configuration/control information for PTP timestamp unit 6.

See description in timestamp unit 1 (0x420 – 0x42D).

0x4CE – 0x4D3: Reserved

Timestamp Unit 6 Input 2nd Sample Time Registers (0x4D4 – 0x4DD)

These five registers contain the 2nd sample time for PTP timestamp unit 6. See description in timestamp unit 1 (0x434 –

0x43D).

0x4DE – 0x4DF: Reserved

Timestamp Unit 7 Status/Configuration/Control and Input 1st Sample Time Registers (0x4E0 – 0x4ED)

These seven registers contain the 1st sample time and status/configuration/control information for PTP timestamp unit 7.

See description in timestamp unit 1 (0x420 – 0x42D).

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0x4EE – 0x4F3: Reserved

Timestamp Unit 7 Input 2nd Sample Time Registers (0x4F4 – 0x4FD)

These five registers contain the 2nd sample time for PTP timestamp unit 7. See description in timestamp unit 1 (0x434 –

0x43D).

0x4FE – 0x4FF: Reserved

Timestamp Unit 8 Status/Configuration/Control and Input 1st Sample Time Registers (0x500 – 0x50D)

These seven registers contain the1st sample time and status/configuration/control information for PTP timestamp unit 8.

See description in timestamp unit 1 (0x420 – 0x42D).

0x50E – 0x513: Reserved

Timestamp Unit 8 Input 2nd Sample Time Registers (0x514 – 0x51D)

These five registers contain the 2nd sample time for PTP timestamp unit 8. See description in timestamp unit 1 (0x434 –

0x43D).

0x51E – 0x51F: Reserved

Timestamp Unit 9 Status/Configuration/ Control and Input 1st Sample Time Registers (0x520 – 0x52D)

These seven registers contain the 1st sample time and status/configuration/control information for PTP timestamp unit 9.

See description in timestamp unit 1 (0x420 – 0x42D).

0x52E – 0x533: Reserved

Timestamp Unit 9 Input 2nd Sample Time Registers (0x534 – 0x53D)

These five registers contai n the 2nd sam ple time f or PTP timestamp unit 9. See desc ription in timestamp unit 1 (0x43 4 –

0x43D).

0x53E – 0x53F: Reserved

Timestamp Unit 10 Status/Configuration/Control and Input 1st Sample Time Registers (0x540 – 0x54D)

These seven regist ers contain th e 1st sam ple time and status /configurat ion/contro l inform ation for PT P timestamp unit 10.

See description in timestamp unit 1 (0x420 – 0x42D).

0x54E – 0x553: Reserved

Timestamp Unit 10 Input 2nd Sample Time Registers (0x554 – 0x55D)

These five regis ters cont ain the 2 nd s ample tim e for PT P timestamp unit 1 0. See description in timestamp unit 1 (0x 434 –

0x43D).

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0x55E – 0x55F: Reserved

Timestamp Unit 11 Status/Configuration/Control and Input 1st Sample Time Registers (0x560 – 0x56D)

These seven registers contain the1st sam ple tim e and status/configurat ion/control information for PTP timestamp unit 11.

See description in timestamp unit 1 (0x420 – 0x42D).

0x56E – 0x573: Reserved

Timestamp Unit 11 Input 2nd Sample Time Registers (0x574 – 0x57D)

These five regis ters cont ain the 2 nd s ample tim e for PT P timestamp unit 1 1. See description in timestamp unit 1 (0x 434 –

0x43D).

0x57E – 0x57F: Reserved

Timestamp Unit 12 Status/Configuration/Control and Input 1st Sample Time Registers (0x580 – 0x58D)

(Note: Timestamp unit 12 has eight sample time registers available)

These seven regist ers contain th e 1st sam ple time and status /configurat ion/contro l inform ation for PT P timestamp unit 12.

See description in timestamp unit 1 (0x420 – 0x42D).

0x58E – 0x593: Reserved

Timestamp Unit 12 Input 2nd Sample Time Registers (0x594 – 0x59D)

These 5 registers contain the 2nd sample time for PTP timestamp unit 12. See description in timestamp unit 1 (0x434 –

0x43D).

0x59E – 0x5A3: Reserved

Timestamp Unit 12 Input 3rd Sample Time Registers (0x5A4 – 0x5AD)

These 5 registers contain the 3rd sample time for PTP timestamp unit 12. See description in timestamp unit 1 (0x434 –

0x43D).

0x5AE – 0x5B3: Reserved

Timestamp Unit 12 Input 4th Sample Time Registers (0x5B4 – 0x5BD)

These five r egisters conta in the 4th sample tim e for PT P timestamp unit 12. See des cription in timestamp unit 1 (0x43 4 –

0x43D).

0x5BE – 0x5C3: Reserved

Timestamp Unit 12 Input 5th Sample Time Registers (0x5C4 – 0x5CD)

These five regis ters contai n the 5th sam ple time for PT P timestamp unit 12. See description in timestamp unit 1 ( 0x434 –

0x43D).

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0x5CE – 0x5D3: Reserved

Timestamp Unit 12 Input 6th Sample Time Registers (0x5D4 – 0x5DD)

These five regis ters contai n the 6th sam ple time for PT P timestamp unit 12. See description in timestamp unit 1 ( 0x434 –

0x43D).

0x5DE – 0x 5E3: Res erv ed

Timestamp Unit 12 Input 7th Sample Time Registers (0x5E4 – 0x5ED)

These five regist ers contain the 7 th sam ple time f or PTP timestamp unit 12. See description in timestamp unit 1 (0x 434 –

0x43D).0x5EE – 0x5F3: Reserved

0x5EE – 0x5F3: Reserved

Timestamp Unit 12 Input 8th Sample Time Registers (0x5F4 – 0x5FD)

These five registers c ontain the 8th sam ple time f or PTP timestamp unit 12. See description in timestamp unit 1 (0x 434 –

0x43D).

0x5FE – 0x5FF: Reserved

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Internal I/O Registers Space Mapping for PTP 1588 Clock and Global Control

(0x600 – 0x7FF)

PTP Clock Control Register (0x600 – 0x601): PTP_CLK_CTL

This register contains control of PTP 1588 clock.

Bit Default R/W Description

15 − 7 0x000 RO Reserved

6 0 RW/SC

(Self-Clear)

Enable Step Adjustment Mode to PTP 1588 Clock

(PTP_STEP_ADJ_CLK)

Setting this bit will cause the time value in PTP_RTC_NSH/L registers to be added

(PTP_STEP_DIR, bit [5]= “1“ or subtracted (PTP_STEP_DIR, bit [5] = ” 0”) from the system

time clo c k. T his b it is se l f -clearing.

5 0 RW

Direction Control for Step Adjustment Mode

(PTP_STEP_DIR)

1 = To add the time value in PTP_RTC_NSH/L registers to system time clock.

0 = To subtract the time value in PTP_RTC_NSH/L registers from system time

clock.

4 0 RW/SC

(Self-Clear)

Enable Read PTP 1588 Clock

(PTP_READ_CLK)

Setting this bit will cause the device to sample the PTP 1588 clock time value. This time value

will be made available for reading through the PTP_RTC_SH/L, PTP_RTC_NSH/L and

PTP_RTC_PHASE registers. This bit is self-clearing.

3 0 RW/SC

(Self-Clear)

Enable Load PTP 1588 Clock for Direct Time Setting Mode

(PTP_LOAD_CLK)

Setting this bit will cause the device to load the PTP 1588 clock time value from

PTP_RTC_SH/L, PTP_RTC_NSH/L and PTP_RTC_PHASE registers. The writes to

PTP_RTC_SH/L, PTP_RTC_NSH/L and PTP_RTC_PHASE are performed before setting this

bit. This bit is self-clearing.

2 0 RW

Enable Continuous Adjustment Mode for PTP 1588 Clock

(PTP_CONTINU_ADJ_CLK)

1 = Enable continuous incrementing (PTP_RATE_DIR = “0”) or decrementing

(PTP_RATE_DIR = “1”) frequency adjustment by the value in

PTP_SNS_RATE_H [29:16] and PTP_SNS_RATE_L [15:0] on every 25 MHz

clo ck cy cle.

0 = Disable continuous adjustment mode to PTP 1588 clock.

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PTP Clock Control Register (0x600 – 0x601): PTP_CLK_CTL (Continued)

Bit Default R/W Description

1 1 RW

Enable PTP 1588 Clock

(EN_PTP_CLK)

1 = To enable the PTP clock.

0 = To disable the PTP clock and the PTP clock will be frozen. For non-

PTP mode, this bit is set to “0” for stopping clock toggling.

0 0 RW/SC

(Self-Clear)

Reset PTP 1588 Clock

(RESET_PTP _CLK)

Setting this bit will reset the PTP 1588 clock.

0x602 – 0x603: Reserved

PTP Real Time Clock in Nanoseconds Low-Word Register (0x604 – 0x605): P T P_R T C_N SL

This register contains the PTP real time clock in nanoseconds low-word.

Bit Default R/W Description

15 − 0 0x0000 RW PTP Real Time Clock in Nanoseconds Low-Word [15:0]

This is low-word of the PTP real time clock in nanoseconds.

PTP Real Time Clock in Nanoseconds High-Word Register (0x606 – 0x607): P T P_RTC_NSH

This register contains the PTP real time clock in nanoseconds high-word.

Bit Default R/W Description

15 − 14 00 RW Upper two bits in counter not used.

13 − 0 0x0000 RW PTP Real Time Clock in Nanoseconds High-Word [29:16]

This is high-word of the PTP real time clock in nanoseconds.

PTP Real Time Clock in Seconds Low-Word Register (0x608 – 0x609): PTP_RTC_SL

This register contains the PTP real time clock in seconds low-word.

Bit Default R/W Description

15 − 0 0x0000 RW PTP Real Time Clock in Seconds Low-Word [15:0]

This is low-word of the PTP real time clock in seconds.

PTP Real Time Clock in Seconds High-Word Register (0x60A – 0x60B): PTP_RTC_SH

This register contains the PTP real time clock in seconds high-word.

Bit Default R/W Description

15 − 0 0x0000 RW PTP Real Time Clock in Seconds High-Word [31:16]

This is high-word of the PTP real ti me clock in sec onds.

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PTP Real Time Clock in Phase Register (0x60C – 0x60D): PTP_RTC_PHASE

This register indicates which sub phase of the PTP real time clock is current. The resolution is 8ns. The PTP real time

clock is updated every 40ns.

Bit Default R/W Description

15 − 3 0x0000 RO Reserved

2 − 0 000 RW

PTP Real Time Clock in Sub 8ns Phase

These bits indicate one of the 8ns sub-cycle times of the 40ns period PTP real time clock.

000: 0ns (real time clock at the first 8ns cycl e in 25MHz/40ns)

001: 8ns (real time clock at the second 8ns cycle in 25MHz/40ns)

010: 16ns (real time clock at the third 8 ns cycle in 25MHz/40ns)

011: 24ns (real time clock at the fourth 8 ns cycle in 25MHz / 40ns)

100: 32ns (real time clock at the fifth 8ns cycle in 25M Hz /40ns)

101-111: NA

This register is set to zero whenever the PTP_RTC_NSL, PTP_RTC_NSH, PTP_RTC_SL,

PTP_RTC_SH registers are written to by the CPU.

0x60E – 0x60F: Reserved

PTP Rate in Sub-Nanoseconds Low-Word Register (0x610 – 0x611): PTP_SNS_RATE_L

This register contains the PTP rate control in sub-nanoseconds low-word.

Bit Default R/W Description

15 − 0 0x0000 RW

PTP Rate Control in Sub-Nanoseconds Low-Word [15:0]

This is low-word of PTP rate control value in units of 2־³² ns. The PTP rate control value is used for

incrementing (PTP_RATE_DIR = “0”) or decrementing (PTP_RATE_DIR = “1”) the frequency

adjustment by the value in PTP_SNS_RATE_H [29:16] and PTP_SNS_RATE_L [15:0] per reference

clock cy cle (40ns). On each reference clock cycle, the PTP clock will be adjusted REF_CLK_PERIOD

±PTP_SNS_RATE_H/L value. Setting both PTP_SNS_RATE_H/L registers value to “0x0” will disable

both continuous and temporary adjustment modes.

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PTP Rate in Sub-Nanoseconds High-Word and Control Re g ister (0x612 – 0x613): PTP_SNS_RATE_H

This register contains the PTP rate control in sub-nanoseconds high-word and configuration.

Bit Default R/W Description

15 0 RW

Rate Direction Control for Temporary or Continuous Adjustment Mode

(PTP_RATE_DIR)

1 = Lower frequency. The PTP_SNS_RATE_H/L value will be added to system

time cloc k on every 25MHz clock cycle.

0 = Higher frequency. The PTP_SNS_RATE_H/L value will be subtracted from

system time clock on every 25MHz clock cycle.

14 0 RW/SC

(Self-Clear)

Enable Temporary Adjustment Mode for PTP 1588 Clock

(PTP_TEMP_ADJ_CLK)

1 = Enable the temporary incrementing (PTP_RATE_DIR = “0”) or

decrementing (PTP_RATE_DIR = “1”) frequency adjustment by the value in

the PTP_SNS_RATE_H/L registers over the duration of time set in the

PTP_ADJ_DURA_H/L registers on every 25MHz clock cycle. This bit is self-cleared

when the adjustment is completed. Software can read this bit to check

whether the adjustment is still in progress.

0 = Disable the temporary adjustment mode to the PTP clock.

13 − 0 0x0000 RW

PTP Rate Control in Sub-Nanoseconds High-Word [29:16]

(PTP_SNS_RATE_H[29:16])

This is high-word of PTP rate control value in units of 2־³² ns. The PTP rate control value is used

for incrementing (PTP_RATE_DIR = “0”) or decrementing (PTP_RATE_DIR = “1”) the frequency

adjustment by the value in PTP_SNS_RATE_H [29:16] and PTP_SNS_RATE_L [15:0] per

reference clock cycle (40 ns). On each reference clock cycle, the PTP clock will be adjusted by a

REF_CLK_PERIOD ±PTP_SNS_RATE_H/L value. Setting both PTP_SNS_RATE_H/L registers

value to “0x0” will disable both continuous and temporary adjustment modes.

PTP Temporary Adjustment Mode Duration in Low-Word Register (0x614 – 0x615): PTP_TEMP_ADJ_DURA_L

This register contains the PTP temporary rate adjustment duration in low-word.

Bit Default R/W Description

15 − 0 0x0000 RW PTP Temporary Rate Adjustment Duration in Low-Word [15:0]

This register is used to set the duration for the temporary rate adjustment in number of 25MHz clock

cycles.

PTP Temporary Adjustment Mode Duration in High-Word Register (0x616 – 0 x617): PT P_TEMP_ADJ_DUR A_H

This register contains the PTP temporary rate adjustment durat ion in hi gh-word.

Bit Default R/W Description

15 − 0 0x0000 RW PTP Temporary Rate Adjustment Duration in High-Word [31:16]

This register is used to set the duration for the temporary rate adjustment in number of 25MHz clock

cycles.

0x618 – 0x61F: Reserved

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PTP Message Configuration 1 Register (0x620 – 0x621): PTP_MSG_CFG_1

This register contains the PTP message configuration 1.

Bit Default R/W Description

15 − 8 0x00 RO Reserved

7 0 RW Enable IEEE 802. 1AS Mode

Setting this bit will enable the IEEE 802.1AS mode and all PTP packets are forwarded to port 3.

6 1 RW Enable IEEE 1588 PTP Mode

1 = To enable the IEEE 1588 PTP mode.

0 = To disable the IEEE 1588 PTP mode.

5 0 RW Enable Detection of IEEE 802.3 Ethernet PTP Message

1 = Enable to detect the Ethernet PTP message.

0 = Disable to detect the Ethernet PTP message.

4 1 RW Enable Detection of IPv4/UDP PTP Message

1 = Enable to detect the IPv4/UDP PTP message.

0 = Disable to detect the IPv4/UDP PTP message.

3 1 RW Enable Detection of IPv6/UDP PTP Message

1 = Enable to detect the IPv6/UDP PTP message.

0 = Disable to detect the IPv6/UDP PTP message.

2 0 RW Se l ection of P2P or E2E

1 = Select Peer-to-Peer (P2P) transpar en t cloc k mode.

0 = Select End-to-End (E2E) transparent clock mode.

1 0 RW Selection of Master or Slave

1 = Select port 3 as master in ordinary clock mode.

0 = Select port 3 as slave in ordinar y clock mod e.

0 1 RW Se l ection of One-step or Two-Step Operation

1 = Select one-step clock mod e.

0 = Select two-step clo ck mode.

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217 Revision 1.0

PTP Message Configuration 2 Register (0x622 – 0x623): PTP_MSG_CFG_2

This register contains the PTP message configuration 2.

Bit Default R/W Description

15 − 13 000 RO Reserved

12 0 RW

Enable Unicast PTP

1 = The Unicast PTP packet can be recognized. If the packet UDP destination port

is either 319 or 320 and the packet MAC/IP address is not the PTP reserved

address, then the packet will be considered as Unicast PTP packet and the

packet forwarding will be decided by regular table lookup.

0 = Only multicast PTP packet will be recognized.

11 0 RW

Enable Alter nate Mast er

1 = Alternate master clock is supported. The Sync, Follow_Up, Delay_Req, and

Delay_Resp m essages of the same do main rec eiv ed at port 1 /port 2 by active

master clock of same domain will be forwarded to port 2/port 1.

0 = Alternate master clock is not supported. The Sync message will not be

forwarded to the other port when this bit = “0”. The Delay_Req message of

same domain received at port 1/port 2 by active master clock of same domain

will be discarded on port 3 and be forwarded to port 2/port 1 if Delay_Req is

for other domains.

10 1 RW PTP Messages Priority TX Queue

1 = All PTP messages are assigned to highest priority TX queue.

0 = Only the PTP event messages are assigned to highest priority TX queue.

9 0 RW

Enable Checking of Associated Sync and Follow_Up PTP Messages

Setting this bit will associate Follow_Up message with Sync message under certain situations. This

bit only applies to PTP frames on port 3. Refer to the Micrel 1588 PTP Developers Guide document

for detailed information on its usage.

8 0 RW

Enable Checking of Associated Delay_Req and Delay_Resp PTP Messages

While this bit is set, the Delay_Resp message will be forwarded to port 1/port 2 if the associa tions do

not match and is forwarded to port 3 if the associations matc h. Setting this bit will associate

Delay_Resp message with Delay_Req message when it has the same domain, sequenceID, and

sourceportID. The PTP frame will be forwarded to port 3 if the ID matches.

7 0 RW

Enable Checking of Associated Pdelay_Req and Pdelay_Resp PTP Messages

Setting this bit will associate Pdelay_Resp/Pdelay_Resp_Follow_Up messages with Pdelay_Req

message when it has the same domain, sequenceID, and sourceportID. The PTP frame will be

forwarded to port 3 if the ID matches. This bit only applies to PTP frames on port 3.

6 0 RO Reserved

5 0 RW Reserved

4 0 RW

Enable Checking of Domain Field: DOMAIN_EN

Setting this DOMAIN_EN bit will enable the device to automatically check the domain field in PTP

message with the PTP_DOMAIN_VER[7:0]. The PTP message will be forwarded to port 3 if the

domain field is matched to PTP_DOMAIN_VER[7:0] otherwise the PTP message will be dropped.

If set this bit to “0”, regardless of domain field, PTP messages are always forwarded to port 3

according to hardware default rules.

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PTP Message Configuration 2 Register (0x622 – 0x623): PTP_MSG_CFG_2 (Continued)

Bit Default R/W Description

3 0 RO Reserved

2 1 RW

Enable the IPv4/UDP Checksum Calculation for Egress Packets

1 = The device will re-calculate and generate a 2-byte checksum value due to a

frame cont ent s chan ge.

0 = The checksum field is set to zero.

If the IPv4/UDP checksum is zero, the checksum will remain zero regardless

of this bit setting.

For IPv6/UDP, the checksum is always updated.

1 0 RW Announce Message from Port 1

1 = The Announce message is received from port 1 direction.

0 = The Announce message is not received from port 1 direct ion.

0 0 RW Announce Message from Port 2

1 = The Announce message is received from port 2 direction.

0 = The Announce message is not received from port 2 direction.

PTP Domain and Version Register (0x624 – 0x625): PTP_DOMAIN_VER

This register contains the PTP Domain and Version Information.

Bit Default R/W Description

15 − 12 0x0 RO Reserved

11 − 8 0x2 RW

PTP Version

This is the value of PTP message version number field. All PTP packets will be captured when the

receive PTP message version matches the value in this field.

All PTP packets will be dropped if the receive PTP message version does not match the value in this

field. Exc ept for the value of version 1, the device is always forwarding PTP packets between port 1

and port 2, and not to port 3.

7 − 0 0x00 RW

PTP Domain

This is the value of the PTP message domain number field. If the DOMAIN_EN bit is set to “1”, the

PTP messages will be filtered out and only forwarded to port 3 if the domain number matches.

If the DOMAIN_EN bit is set to “0”, the domain number field will be ignored under certain

circumstances.

0x626 – 0x63F: Reserved

PTP Port 1 Receive Latency Register (0x640 – 0x641): PTP_P1_RX_LATENCY

This register contains the PTP port 1 receive latency value in nanoseconds.

Bit Default R/W Description

15 − 0 0x019F RW PTP Port 1 RX Latency in Nanoseconds [15:0]

This register is used to set the fixed receive delay value from port 1 wire to RX timestamp reference

point. The default value is 415ns.

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PTP Port 1 Transmit Latency Register (0x642 – 0x643): PTP_P1_TX_LATENCY

This register contains the PTP port 1 transmit latency value in nanoseconds.

Bit Default R/W Description

15 − 0 0x002D RW PTP Port 1 TX Latency in Nanoseconds [15:0]

This register is used to set the fixed transmit delay value from port 1 TX timestamp reference point to

wire. The default value is 45ns.

PTP Port 1 Asymmetry Correction Register (0x644 – 0x 645) : PTP_P1_ASYM_CO R

This register contains the PTP port 1 asymmetry correction value in nanoseconds.

Bit Default R/W Description

15 0 RW PTP Port 1 Asymmetry Correction Sign Bit

1 = The magnitude in bit[14:0] is negative.

0 = The magnitude in bit[14:0] is positive.

14 − 0 0x0000 RW PTP Port 1 Asymmetry Correction in Nanoseconds [14:0]

This register is used to set the fixed asymmetry value to add in the correction field for ingress Sync

and Pdelay_Resp or to subtract from correction field for egress Delay_Req and Pdelay_Req.

PTP Port 1 Link Delay Register (0x646 – 0x647): PTP_P1_LINK_DLY

This register contains the PTP port 1 link delay in nanoseconds.

Bit Default R/W Description

15 − 0 0x0000 RW PTP Port 1 Link Delay in Nanoseconds [15:0]

This register is used to set the link delay value between port 1 and link partner port.

PTP Port 1 Egress Timestamp Low-Word Register for Pdelay_Req and Delay_Req (0x648 – 0x649):

P1_XDLY_REQ_TSL

This register contains the PTP port 1 egress timestamp low-word value for Pdelay_Req and Delay_Req frames in

nanoseconds.

Bit Default R/W Description

15 − 0 0x0000 RW PTP Port 1 Egress Timestamp for Pdelay_Req and Delay_Req in Nanoseconds [15:0]

This register contains port 1 egress timestamp low-word value for Pdelay_Req and Delay_Req frames

in nanoseconds.

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PTP Port 1 Egress Timestamp High-Word Register for Pdelay_Req and Delay_Req (0x64A – 0x64B):

P1_XDLY_REQ_TSH

This register contains the PTP port 1 egress timestamp high-word value for Pdelay_Req and Delay_Req frames in

nanoseconds.

Bit Default R/W Description

15 − 14 00 RW PTP Port 1 Egress Timestamp for Pdelay_Req and Delay_Req in Seconds [1:0]

These bits are bits [1:0] of the port 1 egress timestamp value for Pdelay_Req and Delay_Req frames

in seconds.

13 − 0 0x0000 RW PTP Port 1 Egress Timestamp for Pdelay_Req and Delay_Req in Nanoseconds [29:16]

These bits are bits [29:16] of the port 1 egress timestamp value for Pdelay_Req and Delay_Req

frames in nanoseconds.

PTP Port 1 Egress Timestamp Low-Word Register for Sync (0x64C – 0x64D): P1_ SYN C_T SL

This register contains the PTP port 1 egress timestamp low-word value for Sync frame in nanoseconds.

Bit Default R/W Description

15 − 0 0x0000 RW PTP Port 1 Egress Timestamp for Sync in Nanoseconds [15:0]

This register contains port 1 egress timestamp low-word value for Sync frame in nanoseconds.

PTP Port 1 Egress Timestamp High-Word Register for Sync (0x64E – 0x64F): P1_SYNC_TSH

This register contains the PTP port 1 egress timestamp high-word value for Sync frame in nanoseconds.

Bit Default R/W Description

15 − 14 00 RW PTP Port 1 Egress Timestamp for Sync in Seconds [1:0]

These bits are bits [1:0] of the port 1 egress timestamp value for Sync frame in seconds.

13 − 0 0x0000 RW PTP Port 1 Egress Timestamp for Sync in Nanoseconds [29:16]

These bits are bits [29:16] of the Port 1 egress timestamp value for Sync frame in nanoseconds.

PTP Port 1 Egress Timestamp Low-Word Register for Pdelay_Resp (0x650 – 0x651): P1_PDLY_RESP_TSL

This register contains the PTP port 1 egress timestamp low-word value for Pdelay_Resp frame in nanoseconds.

Bit Default R/W Description

15 − 0 0x0000 RW PTP Port 1 Egress Timestamp for Pdelay_Resp in Nanoseconds [15:0]

This register contains port 1 egress timestamp low-word value for Pdelay_Resp frame in

nanoseconds.

PTP Port 1 Egress Timestamp High-Word Register for Pdelay_Resp (0x652 – 0x653): P1_PDLY_RESP_TSH

This register contains the PTP port 1 egress timestamp high-word value for Pdelay_Resp frame in nanoseconds.

Bit Default R/W Description

15 − 14 00 RW PTP Port 1 Egress Timestamp for Pdelay_Resp in Seconds [1:0]

These bits are bits [1:0] of the port 1 egress timestamp value for Pdelay_Resp frame in

seconds.

13 − 0 0x0000 RW PTP Port 1 Egress Timestamp for Pdelay_Resp in Nanoseconds [29:16]

These bits are bits [29:16] of the port 1 egress timestamp high-word value for Pdelay_Resp

frame in nanosecond s.

0x654 – 0x65F: Reserved

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PTP Port 2 Receive Latency Register (0x660 – 0x661): PTP_P2_RX_LATENCY

This register contains the PTP port 2 receive latency value in nanoseconds.

Bit Default R/W Description

15 − 0 0x019F RW PTP Port 2 RX Latency in Nanoseconds [15:0]

This register is used to set the fixed receive delay value from port 2 wire to the RX

timestamp reference point. The default value is 415ns.

PTP Port 2 Transmit Latency Register (0x662 – 0x663): PTP_P2_TX_LATENCY

This register contains the PTP port 2 transmit latency value in nanoseconds.

Bit Default R/W Description

15 − 0 0x002D RW PTP Port 2 TX Latency in Nanoseconds [15:0]

This register is used to set the fixed transmit delay value from port 2 TX timestamp

reference point to the wire. The default value is 45ns.

PTP Port 2 Asymmetry Correction Register (0x664 – 0x 665) : PTP_P2_ASYM_CO R

This register contains the PTP port 2 asymmetry correction value in nanoseconds.

Bit Default R/W Description

15 0 RW PTP Port 2 Asymmetry Correction Sign Bit

1 = The magnitude in bit[14:0] is negative.

0 = The magnitude in bit[14:0] is positive.

14 − 0 0x0000 RW

PTP Port 2 Asymmetry Correction in Nanoseconds [14:0]

This register is used to set the fixed asymmetry value to add in the correction field for

ingress Sync and Pdelay_Resp or to subtract from correction field for egress Delay_Req

and Pdelay_Req.

PTP Port 2 Link Delay Register (0x666 – 0x667): PTP_P2_LINK_DLY

This register contains the PTP port 2 link delay in nanoseconds.

Bit

Default

R/W

Description

15 − 0 0x0000 RW PTP Port 2 Link Delay in Nanoseconds [15:0]

This register is used to set the link delay value between port 2 and link partner port.

PTP Port 2 Egress Timestamp Low-Word Register for Pdelay_Req and Delay_Req (0x668 – 0x669):

P2_XDLY_REQ_TSL

This register contains the PTP port 2 egress timestamp low-word value for Pdelay_Req and Delay_Req frames in

nanoseconds.

Bit

Default

R/W

Description

15 − 0 0x0000 RW PTP Port 2 Egress Timestamp for Pdelay_Req and Delay_Req in Nanoseconds [15:0]

This register contains port 2 egress timestamp low-word value for Pdelay_Req and Delay_Req frames

in nanoseconds.

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PTP Port 2 Egress Timestamp High-Word Register for Pdelay_Req and Delay_Req (0x66A – 0x66B):

P2_XDLY_REQ_TSH

This register contains the PTP port 2 egress timestamp high-word value for Pdelay_Req and Delay_Req frames in

nanoseconds.

Bit Default R/W Description

15 − 14 00 RW PTP Port 2 Egress Timestamp for Pdelay_Req and Delay_Req in Seconds [1:0]

These are bits [1:0] of the port 2 egress timestamp value for Pdelay_Req and Delay_Req frames in

seconds.

13 − 0 0x0000 RW PTP Port 2 Egress Timestamp for Pdelay_Req and Delay_Req in Nanoseconds [29:16]

These are bits [29:16] of the port

2 egress timestamp value for Pdelay_Req and Delay_Req frames in

nanoseconds.

PTP Port 2 Egress Timestamp Low-Word Register for Sync (0x66C – 0x66D): P2_ SYN C_T SL

This register contains the PTP port 2 egress timestamp low-word value for Sync frame in nanoseconds.

Bit Default R/W Description

15 − 0 0x0000 RW PTP Port 2 Egress Timestamp for Sync in Nanoseconds [15:0]

This register contains port 2 egress timestamp low-word value for Sync frame in nanoseconds.

PTP Port 2 Egress Timestamp High-Word Register for Sync (0x66E – 0x66F): P2_SYNC_TSH

This register contains the PTP port 2 egress timestamp high-word value for Sync frame in nanoseconds.

Bit Default R/W Description

15 − 14 00 RW PTP Port 2 Egress Timestamp for Sync in Seconds [1:0]

These are bits [1:0] of the port 2 egress timestamp value for Sync frame in seconds.

13 − 0 0x0000 RW PTP Port 2 Egress Timestamp for Sync Nanoseconds [29:16]

These are bits [29:16] of the port 2 egress timestamp value for Sync frame in nanoseconds.

PTP Port 2 Egress Timestamp Low-Word Register for Pdelay_Resp (0x670 – 0x671): P2_PDLY_RESP_TSL

This register contains the PTP port 2 egress timestamp low-word value for Pdelay_Resp frame in nanoseconds.

Bit Default R/W Description

15 − 0 0x0000 RW PTP Port 2 Egress Timestamp for Pdelay_Resp in Nanoseconds [15:0]

This register contains port 2 egress timestamp low-word value for Pdelay_Resp frame in

nanoseconds.

PTP Port 2 Egress Timestamp High-Word Register for Pdelay_Resp (0x672 – 0x673): P2_PDLY_RESP_TSH

This register contains the PTP port 2 egress timestamp high-word value for Pdelay_Resp frame in nanoseconds.

Bit

Default

R/W

Description

15 − 0 0x0000 RW PTP Port 2 Egress Timestamp for Pdelay_Resp in Nanoseconds [31:16]

This register contains port 2 egress timestamp high-word value for Pdelay_Resp frame in

nanoseconds.

0x674 – 0x67F: Reserved

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GPIO Monitor Register (0x680 – 0x681): GPIO_MONITOR

This register contains read-only access for the current values on GPIO inputs.

Bit Default R/W Description

15 − 12 0x0 RO Reserved

11 − 0 0x000 RO GPIO Inputs Monitor

This field reflects the current values seen on the GPIO inputs. GPIOs 11 through

0 are mapped to bits [11:0] in order .

GPIO Output Enable Register (0x682 – 0x683): GPIO_OEN

This register contains the control bits for GPIO output enable.

Bit Default R/W Description

15 − 12 0x0 RO Reserved

11 − 0 0x000 RW

GPIO Output Enable

0 = Enables the GPIO pin as trigger output.

1 = Enables the GPIO pin as timestamp input.

GPIOs 11 through 0 are mapped to bits [11:0] in order.

0x684 – 0x687: Reserved

PTP Trigger Unit Interrupt Status Register (0x688 – 0x689): PTP_TRIG_IS

This register contains the interrupt status of PTP event trigger units.

Bit Default R/W Description

15 − 12 0x0 RO Reserved

11 − 0 0x000 RO

(W1C)

Trigger Output Unit Interrupt Status

When this bit is s et to 1, it indicates that the trigger output unit is done or has an error. The

trigger output units from 12 to 1 are mapped to bit [11:0].

These 12 trigger output unit interrupt status bits are logical OR’ed together and connected

to ISR bit [10].

Any of the interrup status bits are cleared by writing a “1” to the particular bit.

PTP Trigger Unit Interrupt Enable Register (0x68A – 0x68B): PTP_TRIG_IE

This register contains the interrupt enable of PTP trigger output units.

Bit

Default

R/W

Description

15 − 12 0x0 RO Reserved

11 − 0 0x000 RW

Trigger Output Unit Interrupt Enable

When this bit is set to “1”, it indicates that the trigger output unit interrupt is enabled.

The trigger outp ut units from 12 to 1 are mapped to bit [11:0].

These 12 trigger output unit interrupt enables are logical OR’ed together and connected to

IER bit [10].

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PTP Timestamp Unit Interrupt Status Register (0x68C – 0x68D): PTP_TS_IS

This register contains the interrupt status of PTP timestamp units. Each bit in this register is cleared by writing a “1” to it.

Bit Default R/W Description

15 0 RO (W1C)

Port 2 Egress Timestamp for Pdelay_Req/Resp and Delay_Req Frames Interrupt

Status

When this bit is set to “1”, it indicates that the egress timestamp is available from port 2 for

Pdelay_Req/Resp and Delay_Req frames.

This bit will be logical OR’ed together with the rest of bits in this register and the logical

OR’ed output is connected to ISR bit[12].

14 0 RO (W1C)

Port 2 Egress Timestamp for Sync Frame Interrupt Status

When this bit is set to “1”, it indicates that the egress timestamp is available from port 2 for

Sync frame.

This bit will be logical OR’ed together with the rest of bits in this register and the logical

OR’ed output is connected to ISR bit[12].

13 0 RO (W1C)

Port 1 Egress Timestamp for Pdelay_Req/Resp and Delay_Req Frames Interrupt

Status

When this bit is set to “1”, it indicates that the egress timestamp is available from port 1 for

Pdelay_Req/Resp and Delay_Req frames.

This bit will be logical OR’ed together with the rest of bits in this register and the logical

OR’ed output is connected to ISR bit[12].

12 0 RO (W1C)

Port 1 Egress Timestamp for Sync Frame Interrupt Status

When this bit is set to “1”, it indicates that the egress timestamp is available from port 1 for

Sync frame.

This bit will be logical OR’ed together with the rest of bits in this register and the logical

OR’ed output is connected to ISR bit[12].

11 − 0 0x000 RO

(W1C)

Timestamp Unit Interrupt Status

When this bit is set to “1”, it indicates that the timestamp unit is ready (TS_RDY = “1”).

The timestamp units from 12 to 1 are mapped to bit [11:0].

These 12 timestamp interrupts status are logical OR’ed together with the rest of bits in this

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PTP Timestamp Unit Interrupt Enable Register (0x68E – 0x68F): PTP_TS_IE

This register contains the interrupt enable of PTP timestamp units.

Bit Default R/W Description

15 0 RW

Port 2 Egress Timestamp for Pdelay_Req/Resp and Delay_Req Frames Interrupt

Enable

When this bit is set to “1”, it is enabled the interrupt when the egress timestamp is available

from port 2 for Pdelay_Req/Resp and Delay_Req frames.

This bit will be logical OR’ed together with the rest of bits in this register and the logical

OR’ed output is connected to IER bit[12].

14 0 RW

Port 2 Egress Timestamp for Sync Frame Interrupt Enable

When this bit is set to “1”, it is enabled the interrupt when the egress timestamp is available

from port 2 for Sync frame.

This bit will be logical OR’ed together with the rest of bits in this register and the logical

OR’ed output is connected to IER bit[12].

13 0 RW

Port 1 Egress Timestamp for Pdelay_Req/Resp and Delay_Req Frames Interrupt

Enable

When this bit is set to “1”, it is enabled the interrupt when the egress timestamp is available

from port 1 for Pdelay_Req/Resp and Delay_Req frames.

This bit will be logical OR’ed together with the rest of bits in this register and the logical

OR’ed output is connected to IER bit[12].

12 0 RW

Port 1 Egress Timestamp for Sync Frame Interrupt Enable

When this bit is set to “1”, it is enabled the interrupt when the egress timestamp is available

from port 1 for Sync frame.

This bit will be logical OR’ed together with the rest of bits in this register and the logical

OR’ed output is connect ed t o IER bit[12].

11 − 0 0x000 RW

Timestamp Unit Interrupt Enable

When this bit is set to “1”, it indicates that the timestamp unit interr upt is enab led.

The timestamp units from 12 to 1 are mapped to bit[11:0].

These 12 timestamp interrupts enable are logical OR’ed together with the rest of bits in this

0x690 – 0x733: Reserved

DSP Control 1 Register (0x734 – 0x735): DSP_CNTRL_6

This register contains control bits for the DSP block.

Bit Default R/W Description

15 − 14 00 RW Reserved

13 1 RW

Receiver Adjustment

Set this bit to “1” when both ports 1 and 2 are in copper mode. When port 1 and/or port 2 is

in fiber mode, this bit should be cleared to “0”.

Note that the fiber or copper mode is selected in the CFGR register (0x0D8 – 0x0D9).

12 − 0 0x1020 RW Reserved

0x736 – 0x747: Reserved

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Analog Contro l 1 Register (0x748 – 0x749): ANA_CNTRL_1

This register contains control bits for the analog block.

Bit Default R/W Description

15 − 8 0x00 RW Reserved

7 0 RW

LDO Off

This bit is used to control the on/off state of the internal low-v oltage regulator.

0 = LDO On (Default)

1 = Turn LDO Off

6 − 0 0x00 RW Reserved

0x74A – 0x74B: Reserved

Analog Contro l 3 Register (0x74C – 0x74D) : ANA_CNT RL _3

This register contains control bits for the analog block.

Bit Default R/W Description

15 0 RW HIPLS3 Mask

This bit must be set prior to initiating the LinkMD function.

14 - 4 0x000 RW Reserved

3 0 RW BT RX Reduce

This bit must be set prior to initiating the LinkMD function.

2 − 0 000 RW Reserved

0x74E – 0x7FF: Reserved

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MII Management (MIIM) Registers

The MIIM interface is us ed to access the MII PHY re gisters within the two em bedded PHY block s. The SPI i nterface can

also be used to access these registers. The latter three interfaces use a different mapping mechanism than the MIIM

interface. Note that when accessing these reg isters via the SPI interface, the relative order of the registers is not exactly

the same.

The “PHYADs” by defaults are assigned “0x1” for PHY1 (port 1) and “0x2” for PHY2 (port 2).

The “REGAD” supported addresses are 0x0-0x5, 0x1D and 0x1F.

Table 22. PHY Register Mapping using the MII Interface

PHY and Register Address Description

PHYAD = 0x1, REGAD = 0x0 PHY1 Basic Control Register

PHYAD = 0x1, REGAD = 0x1 PHY1 Basic Status Register

PHYAD = 0x1, REGAD = 0x2 PHY1 Physical Identifier I

PHYAD = 0x1, REGAD = 0x3 PHY1 Physical Identifier II

PHYAD = 0x1, REGAD = 0x4 PHY1 Auto-Negotiation Advertisement Register

PHYAD = 0x1, REGAD = 0x5 PHY1 Auto-Negotiation Link Partner Ability Register

PHYA D = 0x1, 0x6 – 0x1C PHY1 Not supported

PHYA D = 0x1, 0x1D PHY1 LinkMD Control/Status

PHYA D = 0x1, 0x1E PHY1 Not supported

PHYA D = 0x1, 0x1F PHY1 Special Control/Status

PHYAD = 0x2, REGAD = 0x0 PHY2 Basic Control Register

PHYAD = 0x2, REGAD = 0x1 PHY2 Basic Status Register

PHYAD = 0x2, REGAD = 0x2 PHY2 Physical Identifier I

PHYAD = 0x2, REGAD = 0x3 PHY2 Physical Identifier II

PHYAD = 0x2, REGAD = 0x4 PHY2 Auto-Negotiation Advertisement Register

PHYAD = 0x2, REGAD = 0x5 PHY2 Auto-Negotiation Link Partner Ability Register

PHYA D = 0x2, 0x6 – 0x1C PHY2 Not supported

PHYA D = 0x2, 0x1D PHY2 LinkMD

Control/Status

PHYA D = 0x2, 0x1E PHY2 Not supported

PHYA D = 0x2, 0x1F PHY2 Special Control/Status

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PHY1 (PHYAD = 0x1) and PHY2 (PHYAD = 0x2): Register 0 (REGAD = 0x0) -> MII Basic Control

Bit Default R/W Description

15 0 RO Reserved

14 0 RW

Far-End Loopback

1 = Perform port 1 loopback example as follows:

Start: RXP2/RXM2 (port 2)

Loop back: PMD/PMA of port 1’s PH Y

End: TXP2/TXM2 (port 2)

0 = Normal operation.

13 0 RW Force 100BT

1 = Force 100 Mbps if auto-negotiation is disabled (bit[12])

0 = Force 10 Mbps if auto-negotiation is disabled (bit[12])

12 1 RW Auto-Negotiation Enable

1 = Auto-negotiation enabled.

0 = Auto-negotiation disabled.

11 0 RW Power-Down

1 = Power-down.

0 = Normal operation.

10 0 RO Isolate

Not supported.

9 0 RW Restart Auto-Negotiation

1 = Restart auto-negotiation.

0 = Normal operation.

8 0 RW

Force Full Duplex

1 = Force full duplex.

0 = Force half duplex .

Applies if auto-negotiation is disabled.

It is always in half duplex if auto-negotiation is enabled but failed.

7 0 RO Collision Test

Not supported.

6 0 RO Reserved

5 1 R/W HP_MDIX

1 = HP Auto-MDI-X mode.

0 = Micrel Auto-MDI-X mode.

4 0 RW Force MDI-X

1 = Force MDI-X.

0 = Normal operation.

3 0 RW Disable Auto-MDI-X

1 = Disable Auto-MDI-X.

0 = Normal operation.

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PHY1 (PHYAD = 0x1) and PHY2 (PHYAD = 0x2): Register 0 (REGAD = 0x0) -> MII Basic Control (Continued)

Bit Default R/W Description

2 0 RW

Disable Far-End Fault

1 = Disable far-end fault detection.

0 = Normal operation.

For 100BASE-FX fiber mode operation.

1 0 RW Disable Transm it

1 = Disable transmit.

0 = Normal operation.

0 0 RW Disable LED

1 = Disable LED.

0 = Normal operation.

PHY1 (PHYAD = 0x1) and PHY2 (PHYAD = 0x2): Register 1 (REGAD = 0x1) -> MII Basic Status

Bit Default R/W Description

15 0 RO T4 Capable

1 = 100 BASE-T4 capable.

0 = Not 100 BASE-T4 capable.

14 1 RO 100BT Full Capable

1 = 100BASE-TX full-duplex capable.

0 = Not 100BASE-TX full duplex capable.

13 1 RO 100BT Half Capable

1 = 100BASE-TX half-duplex capable.

0 = Not 100BASE-TX half-duplex capable.

12 1 RO 10BT Full Capable

1 = 10BASE-T f ull-duplex capable.

0 = not 10BASE-T full-duplex capable.

11 1 RO 10BT Half Capable

1 = 10BASE-T half-duplex capable.

0 = Not 10BASE-T half-duplex capable.

10 − 7 0x0 RO Reserved

6 0 RO Preamble Suppressed

Not supported.

5 0 RO Auto-Negotiation Complete

1 = Auto-negotiation complete.

0 = Auto-negotiation not completed.

4 0 RO

Far-End Fault

1 = Far-end fault detected.

0 = No far-end fault detected.

For 100BASE-FX fiber-mode oper ati on.

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PHY1 (PHYAD = 0x1) and PHY2 (PHYAD = 0x2): Register 1 (REGAD = 0x1) -> MII Basic Status (Continued)

Bit Default R/W Description

3 1 RO Auto-Negotiation Capable

1 = Auto-negotiation capable.

0 = Not auto-negotiation capable.

2 0 RO Link Status

1 = Link is up.

0 = Link is down.

1 0 RO Jabber Test

Not supported.

0 0 RO Extended Capable

1 = Ext ended regis ter capa ble.

0 = Not extended register capable.

PHY1 (PHYAD = 0x1) and PHY2 (PHYAD = 0x2): Register 2 (REGAD = 0x2) -> PHYID High

Bit Default R/W Description

15 − 0 0x0022 RO PHY ID High Word

PHY1 (PHYAD = 0x1) and PHY2 (PHYAD = 0x2): Register 3 (REGAD = 0x3) -> PHYID Low

Bit Default R/W Description

15 − 0 0x1430 RO PHY ID Low Word

PHY1 (PHYAD = 0x1) and PHY2 (PHYAD = 0x2): Reg. 4 (REGAD = 0x4) -> Au to -Negotiation Advertisement Ability

Bit Default R/W Description

15 0 RO Next Page

Not supported.

14 0 RO Reserved

13 0 RO Remote Fault

Not supported.

12 − 11 0x0 RO Reserved

10 1 RW Pause (Flow Contr ol Capability)

1 = Advertise pause ability.

0 = Do not advertise pause capability.

9 0 RW

Reserved

8 1 RW Advertise 100BT Full-Duplex

1 = Advertise 100BT full-duplex capabl e.

0 = Do not advertise 100BT full-duplex capability.

7 1 RW Advertise 100BT Half-Duplex

1= Advertise 100BT half-duplex capabl e.

0 = Do not advertise 100BT half-duplex capability.

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PHY1 (PHY AD = 0x1) and PHY2 (PHY AD = 0x2): Re g. 4 (REG AD = 0x4) -> Auto-Negotiation Advertisement Ability

(Continued)

Bit Default R/W Description

6 1 RW Advertise 10BT Full-Duplex

1 = Advertise 10BT full-duplex capable.

0 = Do not advertise 10BT full-duplex capability.

5 1 RW Advertise 10BT Half-Duplex

1 = Advertise 10BT half-duplex capable.

0 = Do not advertise 10BT half-duplex capability.

4 − 0 0x01 RO Selector Field

802.3

PHY1 (PHYAD = 0x1) and PHY2 (PHYAD = 0x2): Reg. 5 (REGAD = 0x5) -> Auto-Negotiatio n L ink Partner Abil ity

Bit Default R/W Description

15 0 RO Next Page

Not supported.

14 0 RO L P ACK

Not supported.

13 0 RO Remote Fault

Not supported.

12 − 11 0x0 RO Reserved

10 0 RO Pause

Link partner pause capability.

9 0 RO Reserved

8 0 RO Advertise 100BT Full-Duplex

Link partner 100BT full capability.

7 0 RO Advertise 100BT Half-Duplex

Link partner 100 half capability.

6 0 RO Advertise 10BT Full-Duplex

Link partner 10BT full capability.

5 0 RO Advertise 10BT Half-Duplex

Link partner 10BT half capability.

4 − 0 0x01 RO Reserved

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PHY1 (PHYAD = 0x1) and PHY2 (PHYAD = 0x2): Reg. 29 (REGAD = 0x1D) -> LinkMD Control and Status

Bit Default R/W Description

15 0

RW/SC

(Self-Clear)

Cable Diagnostic Test Enable

1 = Cable diagnostic test is enabled. It is self-

cleared after the test is done.

0 = Indicates that the cable diagnostic test has

completed and the status information is valid

for read.

14 − 13 0x0 RO

Cable Diagnostic Test Results

[00] = Normal condition.

[01] = Open condition detected in the cable.

[10] = Short condition detected in the cable.

[11] = Cable diagnostic test has failed.

12 − RO CDT 10M Short

1 = Less than 10m short.

11 −9 0x0 RO Reserved

8 − 0 0x000 RO CDT_Fault_Count

Distance to the fault. The dis tance is approximately 0.4m*CDT_Fault_Count.

PHY1 (PHYAD = 0x1) and PHY2 (PHYAD = 0x2): Reg. 31 (REGAD = 0x1F) -> PHY Specia l Control and Status

Bit Default R/W Description

15 − 6 0x000 RO Reserved

5 0 RO Polarity Reverse

1 = Polarity is reversed.

0 = Polarity is not reversed.

4 0 RO MDI-X Status

0 = MD I

1 = MD I-X

3 0 RW Force Link

1 = Force link pass.

0 = Normal operation.

2 1 RW Enable Energy Efficient Ethernet (EEE) on 10BTe

1 = Disable 10BTe.

0 = Enable 10BTe.

1 0 RW

Remote (Near-End) Loopback

1 = Perform remote loopback at

Port 1's PHY (RXP1/R XM1 -> TXP1/TXM1)

Port 2's PHY (RXP2/R XM2 -> TXP2/TXM2)

0 = Normal operation

0 0 RW Reserved

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Management Information Base (MIB) Counter s

The KSZ8463 provides 34 MIB counters for each port. These counters are used to monitor the port activity for network

management. The MIB counters are formatted “per port” and “all ports dropped packet” as shown in Table 23.

Table 23. Format of Per-Port MIB Counters

Bit Name R/W Description Default

31 Overflow RO 1 = Counter overflow.

0 = No counter overflow. 0

30 Count Valid RO 1 = Counter value is valid.

0 = Counter value is not valid. 0

29 − 0 Counter Values RO Counter value (read clear) 0x00000000

“Per Port” MIB counters are read using indirect memory access. The base address offsets and address ranges for all

three ports are:

Port 1, base address is 0x00 and range is from 0x00 to 0x1F.

Port 2, base address is 0x20 and range is from 0x20 to 0x3F.

Port 3 (Host MII/RMII), base address is 0x40 and range is from 0x40 to 0x5F.

“Per Port” MIB counters are read using indirect access control in the IACR register (0x030 – 0x031) and the indirect

access data registers i n IA DR4[1 5:0], IA DR5[ 31:16] (0 x02C – 0x02F). T he port 1 MIB co unt ers addres s m em ory off set as

in Table 24.

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Table 24. Port 1 MIB Counters

−

Indirect Memory Offset

Offset Counter Name Description

0x0 RxLoPriorityByte Rx lo-priority (default) octet count including bad packets.

0x1 RxHiPriorityByte Rx hi-priority octet count in clu ding bad pac ket s.

0x2 RxUndersizePkt Rx undersize pac ket s with good CRC.

0x3 RxFragments Rx fragment packets with bad CRC, symbol errors or alignment errors.

0x4 RxOversize Rx oversize packets with good CRC (maximum: 2000 by tes).

0x5 RxJabbers Rx packets longer than 1522 bytes with either CRC errors, alignment errors, or symbol errors

(depends on max packet siz e setti ng).

0x6 RxSymbolError Rx packets w/ invalid data symbol and legal packet size.

0x7 RxCRCError Rx packets within (64,1522) bytes w/ an integral number of bytes and a bad CRC (upper limit

depends on maximum packet size setting) .

0x8 RxAlignmentError Rx packets within (64,1522) bytes w/ a non-integral number of bytes and a bad CRC (upper limit

depends on maximum packet size setting) .

0x9 RxControl8808Pkts Number of MAC control frames received by a port with 88-08h in EtherType field.

0xA RxPausePkts Number of PAUSE frames received by a port. PAUSE frame is qualified with EtherType (88-08h),

DA, control opcode (00-01), data length (64B minimum), and a valid CRC.

0xB RxBroadcast Rx good broadcast packets (not including error broadcast packets or valid multicast packets).

0xC RxMulticast Rx good multicast packets (not including MAC control frames, error multicast packets or valid

broadcast packets).

0xD RxUnicast Rx good unicast packets.

0xE Rx64Octets Total Rx packets (bad packets included) that were 64 octets in length.

0xF Rx65to127Octets Total Rx packets (bad packets included) that are between 65 and 127 octets in length.

0x10 Rx128to255Octets Total Rx packets (bad packets included) that are between 128 and 255 octets in length.

0x11 Rx256to511Octets Total Rx packets (bad packets included) that are between 256 and 511 octets in length.

0x12 Rx512to1023Octets Total Rx packets (bad packets included) that are between 512 and 1023 octets in length.

0x13 Rx1024to2000Octets Total Rx packets (bad packets included) that are between 1024 and 2000 octets in length (upper

limit depends on max packet size setting).

0x14 TxLoPriorityByte Tx lo-priority good octet count, including PAUSE packets.

0x15 TxHiPriorityByte Tx hi-priority good octet count, including PAUSE packets.

0x16 TxLateCollision The number of times a collision is detected later than 512 bit-tim es into the Tx of a packet.

0x17 TxPausePkts Number of PAUSE frames transmitted by a port.

0x18 TxBroadcastPkts Tx good broadcast packets (not including error broadcast or valid multicast packets).

0x19 TxMulticastPkts Tx good multicast packet s (not including error mult ica st pack et s or valid broa dca st pac ket s).

0x1A TxUnicastPkts Tx good unicast packets.

0x1B TxDeferred Tx packets by a port for which the 1st Tx attempt is delayed due to the busy medium.

0x1C TxTotalCollision Tx total collision, half duplex only.

0x1D TxExcessiveCollision A count of frames for which Tx fails due to excessive collisions.

0x1E TxSingleCollision Successfully Tx frames on a port for which Tx is inhibited by exactly one collision.

0x1F TxMultipleCollision Successfully Tx frames on a port for which Tx is inhibited by more than one collision.

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Table 25. "All Ports Dropped Packet" MIB Counter Format

Bit Default R/W Description

30 − 16 − N/A Reserved

15 − 0 0x0000 RO Counter Value

Note: “All Ports Dropped Packet” MIB Counters do not indicate overflow or validity; therefore, the application m ust keep

track of overflow and va lid c on dit ions.

“All Ports Dropped Packet” MIB counters are read using indirect memory access. The address offsets for these counters

are in T able 26.

Table 26. "All Ports Dropped Packet" MIB Counters - Indirect Memory Offsets

Offset Counter Name Description

0x100 Port 1 TX Drop Packets TX packets dropped due to lack of resources

0x101 Port 2 TX Drop Packets TX packets dropped due to lack of resources

0x102 Port 3 TX Drop Packets TX packets dropped due to lack of resources

0x103 Port 1 RX Drop Packets RX packets dropped due to lack of resources

0x104 Port 2 RX Drop Packets RX packets dropped due to lack of resources

0x105 Port 3 RX Drop Packets RX packets dropped due to lack of resources

Examples:

1. MIB Counter Read (read port 1 “Rx64Octets” counter at indirect address offset 0x0E)

Write to Reg. IACR with 0x1C0E (set indirect address and trigger a read MIB counters operation)

Then:

Read Reg. IADR5 (MIB counter value [31:16]) // If bit [31] = “1”, there was a counter overflow // If bit [30] = “0”,

restart (re-read) from this register

Read Reg. IADR4 (MIB counter value [15:0])

2. MIB Counter Read (read port 2 “Rx64Octets” counter at indirect address offset 0x2E)

Write to reg. IACR with 0x1C2E (set indirect address and trigger a read MIB counters operation)

Then:

Read Reg. IADR5 (MIB counter value [31:16]) // If bit [31] = “1”, there was a counter overflow // If bit [30] = “0”,

restart (re-read) from this register

Read Reg. IADR4 (MIB counter value [15:0])

3. MIB Counter Read (read “port 1 TX Drop Packets” counter at indirect address offset 0x100)

Write to Reg. IACR with 0x1D00 (set indirect address and trigger a read MIB counters operation)

Then:

Read Reg. IADR4 (MIB counter value [15:0])

Additional MIB Information

“Per Port” MIB counters are designed as “read clear”. That is, these counters will be cleared after they are read.

“All Ports Dr opped Pack et” MIB counters are n ot cleared af ter they are acc essed. T he application ne eds to keep track of

overflow and valid conditions on these counters.

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Static MAC Address Table

The KSZ8463 supports both a static and a dynamic MAC address table. in response to a destination address (DA) look

up, The KSZ8 463 searc hes both tables to m ak e a pack et forwardi ng decis ion. In res ponse to a s ource addr es s (SA) look

up, only the dynamic table is searched for aging, migration and learning purposes.

The st atic DA look up resul t takes precedence ov er the d ynamic DA l ook up res ult. If ther e is a DA m atch i n both tabl es,

the result from the static table is used. These entries in the static table will not be aged out by the KSZ8463.

Table 27. Static MAC Table Format (8 Entries)

Bit Default Value R/W Description

57 − 54 0000 RW FID

Filter VLAN ID - identifi es one of the 16 activ e VLANs.

53 0 R/W Use FID

1 = Specifies the use of FID+MAC for static table look up.

0 = Specifies only the use of MAC for static table look up.

52 0 R/W

Override

1 = Overrides the port setting transmit enable = “0” or receive enable = “0” setting.

0 = Specifies no override.

Note: The override bit also allows usage (turns on the entry) even if the Valid bit = “0”.

51 0 R/W Valid

1 = Specifies that this entry is valid, and the look up result will be used.

0 = Specifies that this entry is not valid.

50 − 48 000 R/W

Forwarding Ports

These 3 bits control the forwarding port(s):

000 = No forward.

001 = Forward to port 1.

010 = Forwar d to port 2.

100 = Forward to port 3.

011 = Forward to port 1 and port 2.

110 = Forward to port 2 and port 3.

101 = Forward to port 1 and port 3.

111 = Broadcasting (excluding the ingress port).

47 − 0 0 R/W MAC Ad d r e s s

48-bit MAC Address

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Static MAC Tabl e Lookup Examples:

4. Static Address Table Read (read the second entry at indirect address offset 0x01)

Write to Reg. IACR with 0x1001 (set indirect address and trigger a read static MAC table operation)

Then:

Read Reg. IADR3 (static MAC table bits [57:48])

Read Reg. IADR2 (static MAC table bits [47:32])

Read Reg. IADR5 (static MAC table bits [31:16])

Read Reg. IADR4 (static MAC table bits [15:0])

5. Static Address Table Write (write the eighth entry at indirect address offset 0x07)

Write to Reg. IADR3 (static MAC table bits [57:48])

Write to Reg. IADR2 (static MAC table bits [47:32])

Write to Reg. IADR5 (static MAC table bits [31:16])

Write to Reg. IADR4 (static MAC table bits [15:0])

Write to Reg. IACR with 0x0007 (set indirect address and trigger a write static MAC table operation)

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Dynamic MAC Address Table

The Dynamic MAC Address is a read-only table.

Table 28. Dynamic MAC Address Table Format (1024 Entries)

Bit Default Value R/W Description

71 RO Data Not Ready

1 = Specifies that the entry is not ready, continue retrying until bit is set to “0”.

0 = Specifies that the entry is ready.

70 − 67 RO Reserved

66 1 RO MAC Empty

1 = Specifies that there is no valid entry in the table

0 = Specifies that there are valid entries in the table

65-56 0x000 RO

Number of Valid Entries

Indicates how many valid entries in the table.

0x3FF means 1 K entries.

0x001 means 2 entries.

0x000 and bit [66] = “0” means 1 entry.

0x000 and bit [66] = “1” means 0 entry.

55 − 54 RO Timestamp

Specifies the 2-bit counter for internal aging.

53 − 52 00 RO

Source Port

Identifies the source port where FID+MAC is learned:

00 = Port 1

01 = Port 2

10 = Port 3

51 − 48 0x0 RO FID

Specifies the filter ID.

47 − 0 0x0000_0000_0000 RO MAC Ad d r e s s

Specifies the 48-bit MAC Address.

Dynamic MAC Address Lookup Example

1. Dynamic MAC Address Table Read (read the first entry at indirect address offset 0 and retrieve the MAC table size)

Write to Reg. IACR with 0x1800 (set indirect address and trigger a read dynamic MAC Address table operation)

Then:

Read Reg. IADR1 (dynamic MAC table bits [71:64]) // If bit [71] = “1”, restart (reread) from this register

Read Reg. IADR3 (dynamic MAC table bits [63:48])

Read Reg. IADR2 (dynamic MAC table bits [47:32])

Read Reg. IADR5 (dynamic MAC table bits [31:16])

Read Reg. IADR4 (dynamic MAC table bits [15:0])

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VLAN Table

The KSZ8 463 uses th e VLAN ta ble to per form look -ups. If 802.1Q VL AN mode is enab led (SGCR 2[15]), th is table will be

used to r etrieve the VLAN i nformation th at is ass ociated with the ingres s pack et. This inf ormation inc ludes F ID (Filter ID) ,

VID (VLAN ID), and VLAN membership as described in Table 29:

Table 29. VLAN Table Format (16 Entries)

Bit Default Value R/W Description

19 1 RW Valid

1 = Specifies that this entry is valid, the look up result will be used.

0 = Specifies that this entry is not valid.

18 − 16 111 R/W

Membership

Specifies which ports are members of the VLAN. If a DA look up fails (no match in both static

and dynamic tables), the packet associated with this VLAN will be forwarded to ports specified

in this field. For example: “101” means port 3 and port 1 are in this VLAN.

15 − 12 0x0 R/W

FID

Specifies the Filter ID. The KSZ8463 supports 16 active VLANs represented by these four bit

fields. The FID is the mapped ID. If 802.1Q VLAN is enabled, the look up will be based on

FID+DA and FID+SA.

11 − 0 0x001 R/W VID

Specifies the IEEE 802.1Q 12 bits VLAN ID.

If 802.1Q VLAN mode is enabled, then KSZ8463 will assign a VID to every ingress packet. If the packet is untagged or

tagged with a null VID, then the packet is assigned with the default port VID of the ingress port. If the packet is tagged

with non-null VID, the n VID in the tag wil l be used . The look up pr oc ess will star t f rom the VLA N tab le lo ok up. If the VID is

not valid, th en pac k et wil l b e dr opp ed an d no ad dres s learni ng will t ake place. If t he VID is va lid, the n FID is r etrie ved . T he

FID+DA a nd FID+SA lookups are per formed. T he FID+DA look up determ ines the forwardi ng ports . If FID+DA fai ls, then

the pack et wil l b e broa dc as t to al l th e members ( excludin g the in gres s port) of the VLA N. If FID+SA f ai ls, the n the FID+SA

will be learned.

VLAN Table Lookup Examples

1. VLAN Table Read (read the third entry, at the indirect address offset 0x02)

Write to Reg. IACR with 0x1402 (set indirect address and trigger a read VLAN table operation)

Then:

Read Reg. IADR5 (VLAN table bits [19:16])

Read Reg. IADR4 (VLAN table bits [15:0])

2. VLAN Table Write (write the seventh entry, at the indirect address offset 0x06)

Write to Reg. IADR5 (VLAN table bits [19:16])

Write to Reg. IADR4 (VLAN table bits [15:0])

Write to Reg. IACR with 0x1406 (set indirect address and trigger a read VLAN table operation)

Micrel, Inc.

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June 11, 2014

240 Revision 1.0

Absolute Maximum Ratings(4)

Suppl y Voltage (VDD_A3.3, VDD_IO) ......... –0.5V to +5.0V

Suppl y Voltage (VDD _A L, VDD _ L) .............. –0.5V to +1.8V

Input Voltage (All Inputs) .............................. –0.5V to +5.0V

Output Voltage (All Outputs) ........................ –0.5V to +5.0V

Lead Temperature (soldering, 20s) ............................ 260°C

Storage Temperature (Ts) ......................... –65°C to +150°C

Maximum Junction Temperature (TJ) ....................... +125°C

HBM ESD Rating ........................................................... 2kV

Operating Ratings(5)

Suppl y Voltage

VDD_A3.3 ...................................... +3.135V to +3.465V

VDD_L, VDD_AL, VDD_COL .............. +1.25V to +1.4V

VDD_IO (3.3V)............................... +3.135V to +3.465V

VDD_IO (2.5V)............................... +2.375V to +2.625V

VDD_IO (1.8V)................................... +1.71V to +1.89V

Ambient Operating Temperature (TA)

Industrial (MLI/RLI/FMLI/FRLI) ............. −40°C to +85°C

Thermal Resistance(6)

Junction-to-Ambient (θJA) ................................... 49°C/W

Junction-to-Case (θJC) ....................................... 19°C/W

Electrical Characteristics(7)

Symbol Condition Parameter/Symbol Min. Typ. Max. Units

Supply Current for 100BASE-TX Operation

(Interna l Low-Voltage Regulator On, MII MAC Mode, VDD_A3.3 = 3.3V, VDD_IO = 3.3V)(7, 8)

100% Traffic on Both Ports

IVDD_A3.3 46 mA

IVDD_IO 98

PDISSDEVICE 476 mW

Ports 1 and 2 Powered Down

(P1CR4, P2CR4 bit[11] = “1”)

IVDD_A3.3 4.5 mA

IVDD_IO 74

PDISSDEVICE 259 mW

Ports 1 and 2 Not C onne cte d, using EDPD Feature

(PMCTRL bits[1:0] = “01”)

IVDD_A3.3 5.3 mA

IVDD_IO 73

PDISSDEVICE 260 mW

Ports 1 and 2 Connected, No T raffic, using EEE

Feature

IVDD_A3.3 5.9 mA

IVDD_IO 74

PDISSDEVICE 264 mW

Soft Power-Down Mode

(PMCTRL bits[1:0] = “10”)

IVDD_A3.3 1.1 mA

IVDD_IO 3.2

PDISSDEVICE 14 mW

Hardware Power-Down Mode

While the PWDRN pin (pin 17) is Held Low.(9)

IVDD_A3.3 0.1 mA

IVDD_IO 1.3

PDISSDEVICE 4.6 mW

Notes:

4. Exceeding the absolute maximum ratings may damage the device.

5. The device is not guarant eed to function outside its operat i ng rating. Unused inputs must al ways be tied to an appropriate logic volt age level

(GROUND to V DD_IO).

6. No (HS) heat spreader in this package. The θJC/θJA is under air velocity 0m/s.

7. IVDD_A3.3 m easured at pin 9. IVDD_IO measured at pins 21, 30, and 56. IVDD_AL measured at pins 6 and 16. IVDD_DL measured at pins 40 and 51.

8. TA = 25°C. Specification for packaged product only.

9. For PW RDN pi n (pin 17), the operating value of VIH is lower than the other CMOS input pi ns. It is not dependent on VDD_IO.

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

241 Revision 1.0

Electrical Characteristics(7) (Continued)

Symbol Condition Parameter/Symbol Min. Typ. Max. Units

Supply Current for 100BASE-TX Operation

(Internal Low-Voltage Regulator Off, MII PHY Mode, VDD_A3.3 and VDD_IO = 3. 3V; VDD_L, VDD_AL

and VDD_COL = 1.4V)( 7, 8)

100% Traffic on Both Ports

IVDD_A3.3 46

mA IVDD_IO 21

IVDD_AL + IVDD_DL 84

PDISSDEVICE 328 mW

Ports 1 and 2 Powered Down

(P1CR4, P2CR4 bit[11] = “1”)

IVDD_A3.3 3.8

mA IVDD_IO 15.2

IVDD_AL + IVDD_DL 71

PDISSDEVICE 155 mW

Ports 1 and 2 Not Connected,

using EDPD Feature

(PMCTRL bits[1:0] = “01”)

IVDD_A3.3 4.6

mA IVDD_IO 15.1

IVDD_AL + IVDD_DL 69

PDISSDEVICE 155 mW

Ports 1 and 2 Connected, No

Traffic, using EEE Feature

IVDD_A3.3 5.2

mA IVDD_IO 15.4

IVDD_AL + IVDD_DL 70

PDISSDEVICE 159 mW

Soft Power-Down Mode

(PMCTRL bits[1:0] = “10”)

IVDD_A3.3 0.1

mA IVDD_IO 2.1

IVDD_AL + IVDD_DL 1.4

PDISSDEVICE 9 mW

Hardware Power-Down Mode

While the PWDRN pin (pin 17) is

Held Low. (9)

IVDD_A3.3 0.1

mA IVDD_IO 2.1

IVDD_AL + IVDD_DL 1.2

PDISSDEVICE 9 mW

Supply Current for 10BASE-T Operation

(Interna l Low-Voltage Regulator On, MII MAC Mode, VDD_A3.3 = 3.3V, VDD_IO = 3.3V)

(7, 8)

100% Traffic on Both Ports

IVDD_A3.3 51 mA

IVDD_IO 78

PDISSDEVICE 425 mW

Link, No Traffic on Both Ports

IVDD_A3.3 19.2 mA

IVDD_IO 72

PDISSDEVICE 302 mW

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

242 Revision 1.0

Electrical Characteristics(7) (Continued)

Symbol Condition Parameter/Symbol Min. Typ. Max. Units

Supply Current for 10BASE-T Operation

(Internal Low-Voltage Regulator Off, MII PHY Mode, VDD_A3.3 and VDD_IO = 3.3V; VDD_L, VDD_AL and

VDD_COL = 1.4V)(7, 8)

100% Traffic on Both Ports

IVDD_A3.3 50

mA IVDD_IO 15.7

IVDD_AL + IVDD_DL 71

PDISSDEVICE 315 mW

Link, No Traffic on Both Ports

IVDD_A3.3 19

mA IVDD_IO 15.3

IVDD_AL + IVDD_DL 69

PDISSDEVICE 212 mW

Internal Voltage Regulator Output Voltage

VLDO Output Voltage at V DD_L VDD_IO = 2.5V or 3.3V; internal

regulator enabled; measured at pins 40

and 51 1.32 V

CMOS Inputs (VDD_IO = 3.3V/2.5V/1.8V)

VIH Input High Voltage 2.1/1.7/1.3 V

VIL Input Low Voltage 0.9/0.9/0.6 V

IIN Input Current VIN = GND ~ VDD_IO −10 10 µA

X1 Crystal/Osc Input Pin

VIH Input High Voltage VDD_A3.3 = 3.3V, VDD_IO = any 2.1 V

VIL Input Low Voltage VDD_A3.3 = 3.3V, VDD_IO = any 0.9 V

IIN Input Current 10 µA

PWRDN Input

(9)

VIH Input High Voltage VDD_A3.3 = 3.3V, VDD_IO = any 1.1 V

VIL Input Low Voltage VDD_A3.3 = 3.3V, VDD_IO = any 0.3 V

FXSD Input

VIH Input High Voltage VDD_A3.3 = 3.3V, VDD_IO = any 2.1 V

VIL Input Low Voltage VDD_A3.3 = 3.3V, VDD_IO = any 1.2 V

CMOS Outputs (VDD_IO = 3.3V/2.5V/1.8V)

VOH Output High Voltage IOH = −8mA 2.4/1.9/1.5 V

VOL Output Low Voltage IOL = 8mA 0.4/0.4/0.2 V

|IOZ| Output Tri-State Leakage 10 µA

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

243 Revision 1.0

Electrical Characteristics(7) (Continued)

Symbol Condition Parameter/Symbol Min. Typ. Max. Units

100BASE-TX Transmit (Measured Differentially After 1:1 Transformer)

VO Peak Differential Output

Voltage 100Ω termination on the

differential output ±0.95 ±1.05 V

Vimb Output Voltage Imbalance 100Ω termination on the

differential output 2 %

tr, / tf Rise/Fall Time 3 5 ns

Rise/Fall Time Imbalance 0 0.5 ns

Duty Cycle Di stortion ±0.25 ns

Overshoot 5 %

VSET Reference Voltage of ISET

(Using 6.49KΩ − 1% Resister 0.65 V

Output Jitter Peak-to-peak 0.7 1.4 ns

10BASE-T Receive

Vsq Squelch Threshold 5MHz square wave 400 mV

10BASE-T Transmit (Measured Differentially After 1:1 Transformer)

Vp Peak Differential Output

Voltage 100Ω termination on the

differential output 2.2 2.5 2.8 V

Jitter Added 100Ω termination on the differential

output (peak-to-peak) 1.8 3.5 ns

tr, tf Rise/Fall Time 25 ns

LED Outputs

ILED Output Drive Current Each LED pin (P1/2LED0, P1/2LED1) 8 mA

I/O Pin Internal Pull-U p and Pull-Down Effective Resistance

R1.8PU I/O Pin Effective

Pull-Up Resistance VDD_IO = 1.8V 57 100 187

kΩ

R1.8PD I/O Pin Effective

Pull-Down Resistance 55 100 190

R2.5PU I/O Pin Effective

Pull-Up Resistance VDD_IO = 2.5V 37 59 102

kΩ

R2.5PD I/O Pin Effective

Pull-Down Resistance 35 60 110

R3.3PU I/O Pin Effective

Pull-Up Resistance VDD_IO = 3.3V 29 43 70

kΩ

R3.3PD I/O Pin Effective

Pull-Down Resistance 27 43 76

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

244 Revision 1.0

Timing Specifications

MII Transmit Timing in MAC Mode

This tim ing illustrat es a wr ite operati on from the KSZ8 463 to a P HY or ot her devi ce while op erating t he KSZ 8463 in M AC

mode.

Figure 22. MII Transmit Timing in MAC Mode

Table 30. MII Transmit Timing Parameters in MAC Mode

Timing Parameter

Description

Min.

Typ.

Max.

Unit

tP (100BT/10BT) RX_CLK Period 40/400 ns

tWL (100BT/10BT) RX_CLK Pulse Wid th Low 20/200 ns

tWH (100BT/10BT) RX_CLK Pulse Width High 20/200 ns

tOD RX_DV, RXD[3:0] Output Delay from Rising Edge of RX_CLK 16 ns

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

245 Revision 1.0

MII Receive Timing in MAC Mode

This tim ing illustrates a read operat ion b y the KSZ8463 f rom a PHY or ot her dev ice while op erating the K SZ8463 in MAC

mode.

Figure 23. MII Receive Timing in MAC Mode

Table 31. MII Receive Timing Parameters In MAC Mode

Timing Parameter Description Min. Typ. Max. Unit

tP (100BT/10BT) TX_CLK period 40/400 ns

tWL (100BT/10BT) TX_CLK pulse width low 20/200 ns

tWH (100BT/10BT) TX_CLK pulse width high 20/200 ns

tSU1 TXD[3:0] setup time to rising edge of TX_CLK 10 ns

tSU2 TX_EN, TX_ER setup time to rising edge of TX_CLK 10 ns

tHD1 TXD[3:0] hold time from rising edge of TX_CLK 10 ns

tHD2 TX_EN, TX_ER hold time from rising edge of TX_CLK 10 ns

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

246 Revision 1.0

MII Receive Timing in PHY Mode

Figure 24. MII Receive Timing in PHY Mode

Table 32. MII Receive Timing Parameters IN PHY Mode

Timing Parameter Description Min. Typ. Max. Unit

tP (100BT/10BT) RX_CLK period 40/400 ns

tWL (100BT/10BT) RX_CLK pulse width low 20/200 ns

tWH (100BT/10BT) RX_CLK pulse width high 20/200 ns

tOD RX_DV, RXD[3:0] output delay from rising edge of RX_CLK 20 ns

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

247 Revision 1.0

MII Transmit Timing in PHY Mode

Figure 25. MII Transmit Timing in PHY Mode

Table 33. MII Transmit Timing Parameters in PHY Mode

Timing Parameter Description Min. Typ. Max. Unit

tP (100BT/10BT) TX_CLK period 40/400 ns

tWL (100BT/10BT) TX_CLK pulse width low 20/200 ns

tWH (100BT/10BT) TX_CLK pulse width high 20/200 ns

tSU1 TXD[3:0] setup time to rising edge of TX_CLK 10 ns

tSU2 TX_EN, TX_ER setup time to rising edge of TX_CLK 10 ns

tHD1 TXD[3:0] hold time from rising edge of TX_CLK 0 ns

tHD2 TX_EN, TX_ER hold time from rising edge of TX_CLK 0 ns

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

248 Revision 1.0

Reduced MII (RMII) Timing

Figure 26. RMII Transmit Timing

Figure 27. RMII Receive Timing

Table 34. RMII Timing Parameters

Timing Parameter Description Min. Typ. Max. Unit

tcyc Clock cycle 20 ns

t1 Setup time 4 ns

t2 Hold time 2 ns

tod Output delay 7 9 13 ns

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

249 Revision 1.0

MIIM (MDC/MDIO) Timing

Figure 28. MIIM (MDC/MDIO) Timing

Table 35. MDC/MDIO Timing Parameters

Timing Parameter Description Min. Typ. Max. Unit

tP MDC period 400 ns

tOD Output delay 200 ns

tSU MDIO setup time to rising edge of MDC 10 ns

tHD MDIO hold time from rising edge of MDC 5 ns

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

250 Revision 1.0

SPI Input and Outp u t Timing

Figure 29. SPI Interface Data Input Timing

Figure 30. SPI Interface Data Output Timing

Table 36. SPI Timing Parameters

Timing Parameter Description Min. Typ. Max. Unit

fSCLK SPI_SCLK Clock Frequency 50 MHz

t1 SPI_CSN active setup time 8 ns

t2 SPI_DI data input setup time 3 ns

t3 SPI_DI data input hold time 3 ns

t4 SPI_CSN active hold time 8 ns

t5 SPI_CSN disable high time 8 ns

t6 SPI_SCLK falling edge to SPI_DO data output valid 2 9 ns

t7 SPI_CSN inactive to SPI_DO data output invalid 1 ns

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

251 Revision 1.0

Auto-Negotiation Timing

Figure 31. Auto-Negotiatio n Timing

Table 37. Auto-Negotiation Timing Parameters

Timing Parameter Description Min. Typ. Max. Unit

tBTB FLP Burst to FLP Burst 8 16 24 ms

tFLPW FLP Burst Width 2 ms

tPW Clock/D ata Pulse Wid th 100 ns

tCTD Clock Pulse to Data Pulse 55.5 64 69.5 µs

tCTC Clock Pulse to Clock Pulse 111 128 139 µs

Number of Clock/Data Pulses per Burst 17 33

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

252 Revision 1.0

Trigger Output Unit and Timestamp Input Unit Timing

The timing information in Figure 32 provides details and constraints on various timing relationships within the twelve

trigger output units and the timestamp input units.

Figure 32. Trigger Output Unit and Timestamp Input Unit Timing

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

253 Revision 1.0

Table 38. Trigger Output Unit and Timestamp Input Unit Timing Parameters

Timing Parameter Description Min. Typ. Max. Unit

Trigger Output Unit Timing [Cascade Mode}

TCASP1

In cascade mode for T R IGX _C FG _1[6:4] = 100,

or 101, or 110 (Neg. Edge, Pos. Edge, and Shift

Reg. Output signals).

Minimum time between start of one TOU and the

start of another TOU cascaded on the same

GPIO pin.

80 − − ns

TCASP2

In cascade mode for TRIGX_CFG_1[6:4] = 010,

011, 100, or 101 (Neg. Pulse, Pos. Pulse, Neg.

Periodic, and Pos. Periodic Output signals).

Minimum time between start of one TOU and the

start of another TOU cascaded on the same

GPIO pin.

120 − − ns

TCYCCASP

In cascade mode for TRIGX_CFG_1[6:4] = 010,

and 011 (Neg. Pulse , Pos. Pulse Output

signals).

In cascade mode, the cycle time of the trigger

output unit operating in the indicat ed mode s.

80 ≥32 + PWIDTH2 ns

TCYCNC1

In cascade mode for TRIGX_CFG_1[6:4] = 100

or 101 (Neg. Periodic , Pos. periodic Output

signals).

Minimum cycle time for any trigger output unit

operating in the indi cat ed mod es.

80 ≥32 + PWIDTH2 ns

TGAP23

In cascade mode for TRIGX_CFG_1[6:4] = 010,

and 011 (Neg. Pulse , Pos. Pulse Output

signals):

Minimum gap time required between end of

period of first trigger output unit to beginning of

output of 2nd trigger output unit.

80 − −

PWIDTH2 In cascade mode, the minimum low or high

pulse width of the trigger output unit. 8 − − ns

Trigger Output Unit Timing [Non-Cascade Mode]

TCYCNC2 In non-cascade mode, the minimum cycle time

for any trigger output unit. 80 ≥32 + PWIDTH1 ns

TPOGAP In non-cascade mode, the minimum time

between the end of the generated pulse to the

start of the next pulse. 32 − − ns

PWIDTH1 In non-cascade mode, the minimum low or high

pulse width of the trigger output unit. 8 − − ns

Timestamp Input Unit Timing

IPHIGH Allowable high time of an incoming digital

waveform on any GPIO pin 24 − − ns

IPLOW In non-cascade mode, the minimum time

between the end of the generated pulse to the

start of the next pulse. 24 − − ns

IPCYC In non-cascade mode, the minimum time

between the end of the generated pulse to the

start of the next pulse. 48 − − ns

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

254 Revision 1.0

Reset and Power Sequence Timing

The KSZ8463 reset timing and power sequence requirements are summarized in Figure 33 and Table 39.

Figure 33. Reset and Power Sequence Timing

Table 39. Reset and Power Sequence Timing Parameters(9, 10, 11)

Timing Parameter Description Min. Max. Unit

tvr Supply voltages rise time (must be monotoni c) 0 μs

tsr Stable supply volta ges to de-assertion of reset 10 ms

tcs Strap-in pin configurati on setup time 5 ns

tch Strap-in pin config uration hold time 5 ns

trc De-assertion of reset to strap-in pin output 6 ns

Notes:

10. The recommended powering sequenc e is to bring up all voltages at the same time. However, if that cannot be attained, then a recommended power-

up sequence is to have the transceiver (VDD_A3.3) and digital I/Os (VDD_IO) voltages power up before the low voltage core (VDD_AL, VDD_L, and

VDD_COL) voltage, if an external low voltage core suppl y is used. There is no power sequence requirement between transceiver (VDD_A3.3) and

digital I/ Os (VDD_IO) power rails. The power-up waveforms should be monotonic for all supply voltages to the KSZ8463.

11. After the de-assertion of reset, it is recommended to wait a minimum of 100μs before starting programming of

the device through any interfac e.

12. The recommended power-down sequence is t o have the low voltage core voltage power down first before powering down the transcei ver and digital

I/O voltages.

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

255 Revision 1.0

Reset Circuit Guidelines

Figure 34 il lustrates the r ecomm ended reset c ircuit for power ing up the KSZ8463 device if r eset is triggere d by the po wer

supply.

Figure 34. Simple Reset Circuit

Figure 35 illus trates the recom mended reset c ircuit for applications where reset is drive n by another de vice (e.g., CPU or

FPGA). At POR, R, C and D1 provide t he necessar y ram p rise time to res et the KSZ8463 device. The RST _OUT_N from

CPU/F PG A pr ov ides the warm reset after power-up.

Figure 35. Recommended Reset Circuit for Interfacing with a CPU/FPGA Output

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

256 Revision 1.0

Reference Clock – Connection and Selection

The three different sources for a reference clock are shown in Figure 36. Note that MII clocks are not discussed in this

section. The KSZ8463 ML and KSZ8463FML require an external 25MHz crystal attached to X1/X2, or a 25MHz oscillator

attached to X1.

The KSZ8 463RL and KSZ8463FRL hav e two options for a referenc e clock, as det ermined b y the str apping option on pin

41. The 25MHz option on X1/X2 is as described above. When the 50MHz optio n is selected, an external 50MHz cloc k is

applied to the REFCLK_I pin, while X1 and X2 are unconnected. Note that in the 25MHz mode, REFCLK_O must be

enabled, and it must be externally connected to REFCLK_I. This is described in detail in Table 17.

The resistor shown on X2 is optional and can be used to limit current to the crystal if needed, depending on the specific

crystal that is used. The maximum recommended value is 30Ω.

Figure 36. Input Reference Clock Connection Options

Selection of Reference Crystal

Table 40. Typical Reference Crystal Characteristics

Characteristics

Value

Units

Frequency 25 MHz

Frequency tolerance (maximum) ±50 ppm

Effective Series resistance (maximum) 50 Ω

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

257 Revision 1.0

Selection of Isolation Transformers

A 1:1 isolation transformer is required at the line interface. An isolation transformer with integrated comm on-mode choke

is recommended for exceeding FCC requirements.

Table 41 gives recommended transformer characteristics.

Table 41. Transformer Selection Criteria

Parameter Value Test Condition

Turns Ratio 1 CT : 1 CT

Open-Circuit Inductance (minimum) 350µH 100mV, 100kHz, 8mA

Leakage Inducta nce (max imu m) 0.4µH 1MHz (minimum)

Inter-Winding Capacitance (maximum) 12pF

D.C. Resistance (maximum) 0.9Ω

Insertion Lo ss (max imum) −1.0dB 100kHz – 100MHz

HIPOT (minimum) 1500VRMS

Table 42. Qualified Single Port Magnetics

Magnetic Manuf act ur er Part Number Auto MDI-X Number of Port

Pulse H1102NL Yes 1

Pulse (low cost) H1260 Yes 1

Transpower HB726 Yes 1

Bel Fuse S558-5999-U7 Yes 1

Delta LF8505 Yes 1

LanKom LF-H41S Yes 1

TDK (Mag Jack) TLA-6T718 Yes 1

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

258 Revision 1.0

Package Information(13) and Recommended Landing Pattern

64-Pin 10mm × 10mm LQFP

Note:

13. Package i nformat i on is correct as of the publication date. For updates and most current inform ation, go to www.micrel.com.

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

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MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA

TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com

Micrel makes no represent ations or warranties with respec t t o the accuracy or completeness of the information furnished in this data sheet. This

informat i on is not intended as a warranty and Micrel does not assume responsibilit y for its use. Micrel reserves the right to change circuitry,

specificat i ons and descript i ons at any time without notice. No license, whether express , im plied, arisi ng by estoppel or otherwise, t o any intellectual

property rights is granted by this document. Except as provided in Micrel’s term s and condit i ons of sale for such products, Micrel assumes no liabil ity

whatsoever, and Micrel disclaims any express or impli ed warranty relati ng to t he sale and/or use of Micrel products i ncludi ng liabi l ity or warranties

relating to fitness for a partic ular purpose, merchant abi lit y, or inf ri ngem ent of any patent, copyright or other intel l ect ual propert y right.

Micrel Products are not designed or authorized for use as components in life support applianc es, devic es or syst ems where malfuncti on of a product

can reasonably be expected to result in personal injury. Life support devices or systems are devices or syst ems that (a) are intended for surgical

implant into the body or (b)

support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the use

r. A

Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or syst ems is a Purchaser’s own risk and Purchaser agrees to ful l y

indemnify Mic rel for any damages resulting from such use or sale.