KSZ8463FMLI - MICROCHIP TECHNOLOGY

KSZ8463ML/RL/FML/FRL

IEEE 1588 Precision Tim e Proto co l-

Enabled, Three -Port, 10/100-Managed

Switch with MII or RMI I

Revision 1.0

ETHERSYNCH is a trademark of Micrel, Inc.

LinkMD is a registered trademark of Micrel, Inc.

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com

June 11, 2014

Revision 1.0

General Description

The KSZ8463 ETHERSYNCH™ product line consists of

IEEE 1588v2 enabled Ethernet switches, providing

integrated communications and synchronization for a

range of Industrial Ethernet applications.

The KSZ8463 ETHERSYNCH product line enables

distributed, daisy-chained topologies preferred for

Industrial Ethernet networks. Conventional centralized

(i.e., star-wired) topologies are also supported for dual-

homed, fault-tolerant arrangements.

A flexible set of standard MAC interfaces is provided to

interface to external host processors with embedded

Ethernet MACs :

• KSZ8463ML: Media Independent Interface (MII)

• KSZ8463RL: Reduced Media Independent Interface

(RMII)

• KSZ8463FML: MII, supports 100BASE-FX fiber in

addition to 10/100BASE-TX copper

• KSZ8463FRL: RMII, supports 100BASE-FX fiber in

addition to 10/100BASE-TX copper

The KSZ8463 devices incorporate the IEEE 1588v2

protocol. Sub-m icros econd s ynchronization is av ailable v ia

the use of hardware-based time-stam ping and transparent

clocks making it the ideal solution for time synchronized

Layer 2 communication in critical industrial applications.

Extensive general purpose I/O (GPIO) capabilities are

available to use with the IEEE 1588v2 PTP to efficiently

and accurately interface to locally connected devices.

Complementing the industry’s most-integrated IEEE

1588v2 device is a precision timing protocol (PTP) v2

software stack that has been pre-qualified with the

KSZ84xx product family. The PTP stack has been

optimized around the KSZ84xx chip architecture, and is

available in source code format along with Micrel’s chip

driver.

ETHERSYNCH™

The KSZ8463 product line is built upon Micrel’s industry-

leading Ethernet technology, with features designed to

offload host processing and streamline your overall design.

• Wire-speed Ethernet switching fabric with extensive

filtering

• Two integrated 10/100BASE-TX PHY transceivers,

featuring the industry’s lowest power consumption

• Full-featured quality-of-service (QoS) support

• Flexible management options that support common

standard inter f ac es

The wire-speed, store-and-forward switching fabric

provides a full com plement of QoS and congestion control

features optimized for real-time Ethernet.

A robust assortment of power-management features

including energy-efficient Ethernet (EEE) have been

designed in to satis fy energy effic ient en viro nments.

Datasheets and support documentation are available on

Micrel’s web site at: www.micrel.com.

Functional Diagram

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

2 Revision 1.0

Functional Diagram

KSZ8463ML/RL/FML/FRL Functional Diagram

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

3 Revision 1.0

Features

Management Capabilities

• The KSZ8463ML/RL/FML/FRL includes all the functions

of a 10/100BASE-T/TX/FX switch system which

combines a switch engine, frame buffer management,

address look-up table, queue management, MIB

counters, media access controllers (MAC) and PHY

transceivers

• Non-blocking store-and-forward switch fabric assures

fast packet delivery by utilizing 1024 entry forwarding

table

• Port mirroring/monitoring/sniffing: ingress and/or egress

traffic to any port

• MIB counters for fully-compliant statistics gathering −

34 counters per port

• Loopback modes for remote failure diagnostics

• Rapid spanning tree protocol support (RSTP) for

topology management and ring/linear recovery

• Bypass mode, which ensure continuity even when a

Host is disabled or fails

Robust PHY Ports

• Two integrated IEEE 80 2.3/ 802. 3u-c ompliant Etherne t

transceivers supporting 10BASE-T and 100BASE-TX

• Copper and 100BASE-FX fiber mode support in the

KSZ8463FML and KSZ8463FRL

• Copper mode support in the KSZ8463ML and

KSZ8463RL

• On-chip termination resistors and internal biasing for

differential pairs to reduce power

• HP Auto MDI/MDI-X crossover support eliminating the

need to differentiate between straight or crossover

cables in applications

MAC Ports

• Three internal media access control (MAC) units

• MII or RMII interface support on MAC port 3

• 2Kbyte jumbo packet support

• Tail tagging mode (one byte added before FCS) support

at port 3 to inform the processor which ingress port

receives the pack et and its prior ity

• Supports r ed uced media independe nt inter f ac e (RMII)

with 50MHz reference clock input or output

• Support Media Independent Interface (MII) in either PHY

mode or MAC mode on port 3

• Programmable MAC addresses for port 1 and port 2 and

self-address filtering support

• MAC filtering function to filter or forward unknown

unicast packets

• Port 1 and port 2 MACs programmable as either E2E or

P2P transparent clock (TC) ports for 1588 support

• Port 3 MAC programmable as slave or master of

ordinary clock (OC) port for 1588 support

• Micrel Link MD ® cable diagnostic capabilities for

determining cable opens, shorts, and length

Advanced Switch Capabilities

• Non-blocking store-and-forward switch fabric assures

fast packet delivery by utilizing 1024 entry forwarding

table

• IEEE 802.1Q VLAN for up to 16 groups with full range of

VLAN IDs

• IEEE 802.1p/Q tag insertion or removal on a per port

basis (egress) and support double-tagging

• VLAN ID tag/untag options on per port basis

• Fully compliant with IEEE 802.3/802.3u standards

• IEEE 802.3x full-duplex with force-mode option and half-

duplex backpressure collision flow control

• IEEE 802.1w rapid spanning tree protocol support

• IGMP v1/v2/v3 snooping for multicast packet filtering

• QoS/CoS packets prioritization support: 802.1p,

DiffServ-based and re-mapping of 802.1p priority field

per-port basis on four priority levels

• IPv4/IPv6 QoS support

• IPv6 multicast listener discovery (MLD) snooping

support

• Programmable rate limiting at the ingress and egress

ports

• Broadcast storm protection

• Bypass mode to sustain the switch function between

port 1 and port 2 when CPU (port 3) goes into sleep

mode

• 1K entry forwarding table with 32K frame buffer

• Four priority queues with dynamic packet mapping for

IEEE 802.1p, IPv4 TOS (DIFFSERV), IPv6 Traffic

Class, etc.

• Source address filtering for implementing ring topologies

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

4 Revision 1.0

Comprehensive Configuration Registers Access

• High-speed SPI (4-wire, up to 50 MHz) Interface to

access all internal registers

• MII Management (MIIM, MDC/MDIO 2-wire) Interface to

access all PHY registers per clause 22.2.4.5 of the IEEE

802.3 specification

• I/O pin strapping facility to set certain register bits from

I/O pins at reset time

• Control registers configurable on-the-fly

IEEE 1588v2 PTP and Clock Synchronization

• Fully compliant with the I E EE 158 8v2 precision time

protocol

• One-step or two-step transparent clock (TC) timing

corrections

• E2E (end-to-end) or P2P (peer-to-peer) transparent

clock (TC)

• Grandmaster, master, slave, ordinary clock (OC)

support

• IEEE1588v2 PTP Multicast and Unicas t frame support

• Transports of PTP over IPv4/IPv6 UDP and IEEE 802.3

Ethernet

• Delay request-response and peer delay mechanism

• Ingress/egress packet timestamp capture/recording and

checksum update

• Correction field update with residence time and link

delay

• IEEE1588v2 PTP packet filtering unit to reduce host

processor overhead

• A 64-bit adjustable system precision clock

• Twelve trigger output units and twelve timestamp input

units available for flexible IEEE1588v2 control of twelve

programmable GPIO[11:0] pins synchronized to the

precision time clock

• GPIO pin usage for 1 PPS generation, frequency

generator, control bit streams, event monitoring,

precision pulse generation, complex waveform

generation

Power and Power Management

• Single 3.3V power supply with optional VDD I/O for

1.8V, 2.5V or 3.3V

• Integrated low voltage (~1.3V) low-noise regulator

(LDO) output for digital and analog core power

• Supports IEEE P802.3az™ energy-efficient Eth er net

(EEE) to reduce power consumption in transceivers in

LPI state

• Full-chip hardware or software power-down (all registers

value are not saved and strap-in valu e will re-strap after

release the pow er-down)

• Energ y detect power -down (EDPD), which disables the

PHY transceiver when cables are removed

• Dynamic clock tree control to reduce clocking in areas

not in use

• Power consumption less than 0.5W

Additional Features

• Single 25MHz ±50ppm reference clock requirement for

MII mode

• Selectable 25MHz or 50MHz inputs for RMII mode

• Comprehensive programmable two LED indicators

support for link, activity, full/half duplex and 10/100

speed.

• LED pins direct l y contro llab le.

• Industrial temperature range: –40°C to +85°C

• 64-pin (10mm x 10mm) lead free (ROHS) LQFP

package

• 0.11μm technology for lower power consumption

Applications

• Industrial Ethernet applications that employ IEEE 802.3-

compliant MACs. (Ethernet/IP, Profinet, MODBUS TCP,

etc)

• Real-time Ethernet networks requiring sub-microsecond

synchronization over standard Ethernet

• IEC 61850 networks supporting power substation

automation

• Networked measurement and control systems

• Industrial automation and motion control systems

• Test and measurement equipment

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

5 Revision 1.0

Ordering Information

Part Number Temperature Range Package Lead Finish Description

KSZ8463MLI –40

C to +85

C 64-Pin LQFP Pb-Free Industrial Temperature Device with MII Interface

KSZ8463FMLI –40oC to +85oC 64-Pin LQFP Pb-Free Industrial Temperature Device with MII Interface

and Fiber (100BASE-FX) suppo rt

KSZ8463RLI –40oC to +85oC 64-Pin LQFP Pb-Free Industrial Temperature Device with RMII Interface

KSZ8463FRLI –40oC to +85oC 64-Pin LQFP Pb-Free Industrial Temperature Device with RMII Interface

and Fiber (100BASE-FX) suppo rt

KSZ8463MLI-EVAL Evaluation Board with KSZ8463MLI. Also supports KSZ8463FMLI, KSZ8463RLI and KSZ8463FRLI.

Revision History

Revision

Date

Summary of Changes

1.0 6/11/14 Initial release of product − S. Thompson

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

6 Revision 1.0

Contents

List of Figures ........................................................................................................................................................................ 15

List of Tables ......................................................................................................................................................................... 16

Acronyms .............................................................................................................................................................................. 17

Pin Configuration ................................................................................................................................................................... 20

Pin Description ...................................................................................................................................................................... 21

Strapping Options ................................................................................................................................................................. 27

Functional Description ........................................................................................................................................................... 28

Physical (PHY) Block ............................................................................................................................................................ 28

100BASE-TX Transmit ...................................................................................................................................................... 28

100BASE-TX Receive ....................................................................................................................................................... 28

Scrambler/De-Scrambler (100BASE-TX Only) .................................................................................................................. 28

PLL Clock Synthesizer (Recovery) .................................................................................................................................... 28

100BASE-FX Operation .................................................................................................................................................... 29

100BASE-FX Signal Detection .......................................................................................................................................... 29

100BASE-FX Far-End Fault .............................................................................................................................................. 29

10BASE-T Transmit ........................................................................................................................................................... 29

10BASE-T Receive ............................................................................................................................................................ 29

MDI/MDI-X Auto Crossover ............................................................................................................................................... 30

Straight Cab le .................................................................................................................................................................... 30

Crossover Cable ................................................................................................................................................................ 31

Auto-Negotiation ................................................................................................................................................................ 31

LinkMD® Cable Diagnos tic s ............................................................................................................................................... 32

Access............................................................................................................................................................................ 32

Usage ............................................................................................................................................................................. 32

On-Chip Termination Resistors ......................................................................................................................................... 33

Loopback Support ............................................................................................................................................................. 33

Far-End Loopbac k ......................................................................................................................................................... 33

Near-End (Remote) Loopback ....................................................................................................................................... 33

MAC (Media Access Controller) Block .................................................................................................................................. 35

MAC Operation .................................................................................................................................................................. 35

Address Lookup ................................................................................................................................................................. 35

Learning ............................................................................................................................................................................. 35

Migration ............................................................................................................................................................................ 35

Aging .................................................................................................................................................................................. 35

Forwarding ......................................................................................................................................................................... 35

Inter-Packet Gap (IPG) ...................................................................................................................................................... 37

Back-Off Algorithm ............................................................................................................................................................ 37

Late Collis ion ..................................................................................................................................................................... 37

Legal Packet Size .............................................................................................................................................................. 37

Flow Control....................................................................................................................................................................... 38

Half-Duplex Backpressure ................................................................................................................................................. 38

Broadcast Storm Protection ............................................................................................................................................... 39

Port Individual MAC Address and Source Port Filtering ................................................................................................... 39

Switch Block .......................................................................................................................................................................... 40

Switching Engine ............................................................................................................................................................... 40

Spanning Tree Support ..................................................................................................................................................... 40

Rapid Spanning Tree Support ........................................................................................................................................... 41

Discarding State ............................................................................................................................................................. 41

Learning State ................................................................................................................................................................ 41

Forwardi ng Stat e ............................................................................................................................................................ 41

Tail Tagging Mode ............................................................................................................................................................. 41

IGMP Support .................................................................................................................................................................... 42

“IGMP” Snooping ........................................................................................................................................................... 42

“Multicast Address Insertion” in the Static MAC Table .................................................................................................. 42

IPv6 MLD Snooping ........................................................................................................................................................... 42

Port Mirroring Support ....................................................................................................................................................... 43

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

7 Revision 1.0

“Receive Only” Mirror-on-a-Port .................................................................................................................................... 43

“Transmit Only” Mirror-on-a-Port ................................................................................................................................... 43

“Receive and Transmit” Mirror-on-Two-Ports ................................................................................................................ 43

IEEE 802.1Q VLAN Support .......................................................................................................................................... 43

Quality-of-Service (QoS) Priority Support ......................................................................................................................... 44

Port-Bas ed Priority ............................................................................................................................................................ 44

802.1p-Bas ed Priority ........................................................................................................................................................ 44

802.1p Priority Field Re-Mapping ...................................................................................................................................... 45

DiffServ-Based Priority ...................................................................................................................................................... 45

Rate Limiting Support ........................................................................................................................................................ 45

MAC Address Filtering Function ........................................................................................................................................ 46

IEEE 1588 Precision Time Protocol (PTP) Block .................................................................................................................. 47

IEEE 1588 PTP Clock Types ............................................................................................................................................. 48

IEEE 1588 PTP One-Step or Two-Step Clock Operation ................................................................................................. 48

IEEE 1588 PTP Best Master Clock Selection ................................................................................................................... 48

IEEE 1588 PTP System Time Clock ................................................................................................................................. 48

Updating the System Time Clock ...................................................................................................................................... 50

Directly Setting or Reading the Time ............................................................................................................................. 50

Step-Time Adjustment ................................................................................................................................................... 50

Continuous Time Adjustment ......................................................................................................................................... 50

Temporary Time Adjustment ......................................................................................................................................... 50

PTP Clock Initialization .................................................................................................................................................. 51

IEEE 1588 PTP Message Processing ............................................................................................................................... 51

IEEE 1588 PTP Ingress Packet Processing .................................................................................................................. 51

IEEE 1588 PTP Egress Packet Processing ................................................................................................................... 51

IEEE 1588 PTP Event Triggering and Timestamping ....................................................................................................... 52

IEEE 1588 PTP Trigger Output ..................................................................................................................................... 52

IEEE 1588 PTP Event Timestamp Input ........................................................................................................................ 52

IEEE 1588 PTP Event Interrupts ................................................................................................................................... 53

IEEE 1588 GPIO ............................................................................................................................................................ 53

General Purpose and IEEE 1588 Input/Output (GPIO) ........................................................................................................ 54

Overview ............................................................................................................................................................................ 54

GPIO Pin Functionality Control.......................................................................................................................................... 54

GPIO Pin Control Register Layout..................................................................................................................................... 55

GPIO Trigger Output Unit and Timestamp Unit Interrupts ................................................................................................ 57

Using the GPIO Pins with the Trigger Output Units .............................................................................................................. 59

Creating a Low-Going Pulse at a Specific Time ................................................................................................................ 59

Creating a High-Going Pulse at a Specific Time ............................................................................................................... 59

Creating a Free Running Clock Source ............................................................................................................................. 60

Creating Finite Length Periodic Bit Streams at a Specific Time ........................................................................................ 61

Creating Finite Length Non-Uniform Bit Streams at a Specific Time ................................................................................ 61

Creating Complex Waveforms at a Specific Time ............................................................................................................. 62

Using the GPIO Pins with the Timestamp Input Units .......................................................................................................... 64

Device Clocks........................................................................................................................................................................ 66

GPIO and IEEE 1588-Related Clocking ............................................................................................................................ 67

Power .................................................................................................................................................................................... 68

Internal Low Voltage LDO Regulator ................................................................................................................................. 69

Power Manag ement .............................................................................................................................................................. 70

Normal Operation Mode .................................................................................................................................................... 70

Energy-Detect Mode .......................................................................................................................................................... 70

Global Soft Power-Down Mode ......................................................................................................................................... 71

Energy-Efficient Ethernet (EEE) ........................................................................................................................................ 71

Transmit Direction Control for MII Mode ........................................................................................................................... 72

Receive Direction Control for MII Mode ............................................................................................................................ 72

Register s Ass ociate d with EE E ......................................................................................................................................... 72

Interrupt Generation on Power Management-Related Events .............................................................................................. 72

Interfaces ............................................................................................................................................................................... 73

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

8 Revision 1.0

Configuration Interface ...................................................................................................................................................... 73

SPI Slave Serial Bus Conf i gur ation ................................................................................................................................... 73

SPI Register Access Operation Timing ............................................................................................................................. 74

MII Management (MIIM) Interface ..................................................................................................................................... 76

Media Independent Interface (MII) .................................................................................................................................... 76

Reduced Media Independent Interface (RMII) .................................................................................................................. 78

Device Registers ................................................................................................................................................................... 80

Register Map of CPU Accessible I/O Registers .................................................................................................................... 82

I/O Registers ...................................................................................................................................................................... 82

Internal I/O Register Space Mapping for Switch Control and Configuration (0x000 – 0x0FF) ...................................... 82

Internal I/O Register Space Mapping for Interrupts and Global Reset (0x100 − 0x1FF) .............................................. 88

Internal I/O Register Space Mapping for PTP Trigger Output (12 Units, 0x200 − 0x3FF) ............................................ 89

Internal I/O Register Space Mapping for PTP Timestamp Inputs (12 Units, 0x400 – 0x5FF) ....................................... 98

Internal I/O Register Space Mapping for PTP 1588 Clock and Global Control (0x600 – 0x7FF) ............................... 110

Register Bit Definitions ........................................................................................................................................................ 114

Internal I/O Register Space Mapping for Switch Control and Configuration (0x000 – 0x0FF) ....................................... 114

Chip ID and Enable Register (0x000 – 0x001): CIDER ............................................................................................... 114

Switch Global Control Register 1 (0x002 − 0x003): SGCR1 ........................................................................................... 114

Switch Global Control Register 2 (0x004 – 0x0 05) : SG C R2 ........................................................................................... 116

Switch Global Control Register 3 (0x006 – 0x0 07) : SG C R3 ........................................................................................... 117

0x008 – 0x00B: Reserv ed ............................................................................................................................................... 117

Switch Global Control Register 6 (0x00C – 0x00D): SGCR6 .......................................................................................... 118

Switch Global Control Register 7 (0x00E – 0x 00F) : SG CR7 .......................................................................................... 119

MAC Address Registers ...................................................................................................................................................... 120

MAC Address Register 1 (0x010 – 0x011): MACAR1 ..................................................................................................... 120

MAC Address Register 2 (0x012 – 0x013): MACAR2 ..................................................................................................... 120

MAC Address Register 3 (0x014 – 0x015): MACAR3 ..................................................................................................... 120

TOS Priority Control Registers ............................................................................................................................................ 121

TOS Priority Control Register 1 (0x016 – 0x017): TOSR1 .............................................................................................. 121

TOS Priority Control Register 2 (0x018 – 0x019): TOSR2 .............................................................................................. 122

TOS Priority Control Register 3 (0x01A – 0x01B): TOSR3 ............................................................................................. 123

TOS Priority Control Register 4 (0x01C – 0x1D): TOSR4 .............................................................................................. 123

TOS Priority Control Register 5 (0x01E – 0x1F): TOSR5 ............................................................................................... 124

TOS Priority Control Register 6 (0x020 – 0x021): TOSR6 .............................................................................................. 125

TOS Priority Control Register 7 (0x022 – 0x023): TOSR7 .............................................................................................. 125

TOS Priority Control Register 8 (0x024 – 0x025): TOSR8 .............................................................................................. 126

Indirect Acc ess Data Reg ister s ........................................................................................................................................... 127

Indirect Access Data Register 1 (0x026 – 0x027): IADR1 .............................................................................................. 127

Indirect Access Data Register 2 (0x028 – 0x029): IADR2 .............................................................................................. 127

Indirect Access Data Register 3 (0x02A – 0x02B): IADR3 ............................................................................................. 127

Indirect Access Data Register 4 (0x02C – 0x02D): IADR4 ............................................................................................. 127

Indirect Access Data Register 5 (0x02E – 0x02F): IADR5 .............................................................................................. 128

Indirect Access Control Register (0x030 – 0x031): IACR ............................................................................................... 128

Power Management Control and Wake-Up Event Status ................................................................................................... 129

Power Management Control and Wake-Up Event Status (0x032 – 0x033) : PM CTRL ................................................... 129

(0x034 – 0x035): Reserved ............................................................................................................................................. 129

Go Sleep Time and Clock Tree Power-Down Control Registers ........................................................................................ 130

Go Sleep Time Register (0x036 – 0x037): GST.............................................................................................................. 130

Clock Tree Power-Down Control Register (0x038 – 0x039): CTPDC ............................................................................. 130

0x03A – 0x04B: Reserved ............................................................................................................................................... 130

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

9 Revision 1.0

PHY and MII Basic Control Registers ................................................................................................................................. 131

PHY 1 and MII Basic Control Register (0x04C – 0x04D ): P1MBCR ............................................................................... 131

PHY 1 and MII Basic Status Register (0x04E – 0x04F): P1MBSR ................................................................................. 132

PHY 1 PHYID Low Register (0x050 – 0x051): PHY1ILR ................................................................................................ 133

PHY 1 PHYID High Register (0x052 – 0x053): PHY1IHR .............................................................................................. 133

PHY 1 Auto-Negotiation Advertisement Register (0x054 – 0x0 55) : P1 ANA R ................................................................ 134

PHY 1 Auto-Negot iation Link Partner Ability Register (0x056 – 0x057): P1ANLPR ....................................................... 135

PHY 2 and MII Basic Control Register (0x058 – 0x059): P2MBCR ................................................................................ 136

PHY 2 and MII Basic Status Register (0x05A – 0x05B): P2MBSR ................................................................................. 137

PHY 2 PHYID Low Register (0x05C – 0x 05D) : PH Y2IL R ............................................................................................... 138

PHY 2 PHYID High Register (0x05E – 0x05F): PHY2IHR .............................................................................................. 138

PHY 2 Auto-Negotiation Advertisement Register (0x060 – 0x0 61) : P2 ANA R ................................................................ 139

PHY 2 Auto-Negotiation Link Partner Ability Register (0x062 – 0x063): P2ANLPR ....................................................... 140

0x064 – 0x065: Reserved ................................................................................................................................................ 140

PHY1 Special Control and Status Register (0x066 – 0x067): P1PHYCTRL .................................................................. 141

0x068 – 0x069: Reserved ................................................................................................................................................ 141

PHY 2 Special Control and Status Register (0x06A – 0x06B) : P2PHYCT R L ................................................................. 142

Port 1 Control Registers ...................................................................................................................................................... 143

Port 1 Control Register 1 (0x06C – 0x 06D) : P1CR 1 ....................................................................................................... 143

Port 1 Control Register 2 (0x06E – 0x06F ): P1CR2........................................................................................................ 145

Port 1 VID Control Register (0x070 – 0x071): P1VIDCR ................................................................................................ 146

Port 1 Control Register 3 (0x072 – 0x073): P1CR3 ........................................................................................................ 147

Port 1 Ingress Rate Control Register 0 (0x074 – 0x075): P1IRCR0 ............................................................................... 147

Port 1 Ingress Rate Control Register 1 (0x076 – 0x077): P1IRCR1 ............................................................................... 148

Port 1 Egress Rate Control Register 0 (0x078 – 0x079): P1ERCR0 .............................................................................. 149

Port 1 Egress Rate Control Register 1 (0x07A – 0x07B): P1ERCR1 ............................................................................. 149

Port 1 PHY Special Control/Status, LinkMD (0x07C – 0x07D): P1SCSLMD .................................................................. 150

Port 1 Control Register 4 (0x07E – 0x07F ): P1CR4........................................................................................................ 150

Port 1 Status Register (0x080 – 0x 081): P1 SR ............................................................................................................... 152

0x082 – 0x083: Reserved ................................................................................................................................................ 153

Port 2 Control Registers ...................................................................................................................................................... 154

Port 2 Control Register 1 (0x084 – 0x085): P2CR1 ........................................................................................................ 154

Port 2 Control Register 2 (0x086 – 0x087): P2CR2 ........................................................................................................ 155

Port 2 VID Control Register (0x088 – 0x089): P2VIDCR ................................................................................................ 157

Port 2 Control Register 3 (0x08A – 0x08 B) : P2CR 3 ....................................................................................................... 157

Port 2 Ingress Rate Control Register 0 (0x08C – 0x08D): P2IRCR0 .............................................................................. 158

Port 2 Ingress Rate Control Register 1 (0x08E – 0x08F): P2IRCR1 .............................................................................. 158

Port 2 Egress Rate Control Register 0 (0x090 – 0x091): P2ERCR0 .............................................................................. 159

Port 2 Egress Rate Control Register 1 (0x092 – 0x093): P2ERCR1 .............................................................................. 159

Port 2 PHY Special Control/Status, LinkMD® (0x094 – 0x095): P2SCS LMD ................................................................. 160

Port 2 Control Register 4 (0x096 – 0x097): P2CR4 ........................................................................................................ 160

Port 2 Status Register (0x098 – 0x099): P2SR ............................................................................................................... 162

0x09A – 0x09B: Reserved ............................................................................................................................................... 163

Port 3 Control Registers ...................................................................................................................................................... 164

Port 3 Control Register 1 (0x09C – 0x09D): P3CR 1 ....................................................................................................... 164

Port 3 Control Register 2 (0x09E – 0x09F ): P3CR2........................................................................................................ 165

Port 3 VID Control Register (0x0A0 – 0x0A1 ): P3 VID C R ............................................................................................... 166

Port 3 Control Register 3 (0x0A2 – 0x0 A3) : P3CR 3 ....................................................................................................... 167

Port 3 Ingress Rate Control Register 0 (0x0A4 – 0x0A5): P3IRCR0 .............................................................................. 168

Port 3 Ingress Rate Control Register 1 (0x0A6 – 0x0A7): P3IRCR1 .............................................................................. 168

Port 3 Egress Rate Control Register 0 (0x0A8 – 0x0A9): P3ERCR0 ............................................................................. 169

Port 3 Egress Rate Control Register 1 (0x0AA – 0x0AB): P3ERCR1 ............................................................................. 169

Switch Global Control Registers ......................................................................................................................................... 170

Switch Global Control Register 8 (0x0AC – 0x 0AD): SGCR8 ......................................................................................... 170

Switch Global Control Register 9 (0x0AE – 0x 0AF) : S GC R9 ......................................................................................... 171

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

10 Revision 1.0

Source Address Filtering MAC Address Registers ............................................................................................................. 172

Source Address Filtering MAC Address 1 Register Low (0x0B0 – 0x 0 B1) : S AF M AC A 1L ............................................. 172

Source Address Filtering MAC Address 1 Register Middle (0x0B2 – 0x0 B3) : S AFMACA1M ........................................ 172

Source Address Filtering MAC Address 1 Register High (0x0B4 – 0x0B5): SAFMACA1H ............................................ 172

Source Addr ess Filtering MAC Address 2 Register Low (0x0B6 – 0x 0 B7) : S AF M AC A 2L ............................................. 172

Source Address Filtering MAC Address 2 Register Middle (0x0B8 – 0x 0 B9 ): S AF M AC A2 M ........................................ 172

Source Address Filtering MAC Address 2 Register High (0x0BA – 0x0B B) : SAFMACA2H ........................................... 173

0x0BC – 0x0C7: Reserved .............................................................................................................................................. 173

TXQ Rate Control Registers ............................................................................................................................................... 174

Port 1 TXQ Rate Control Register 1 (0x0C8 – 0x0 C9): P1TX QRCR1 ............................................................................ 174

Port 1 TXQ Rate Control Register 2 (0x0CA – 0x0CB): P1TXQRCR2 ........................................................................... 174

Port 2 TXQ Rate Control Register 1 (0x0CC – 0x0CD): P2TXQRCR1 ........................................................................... 175

Port 2 TXQ Rate Control Register 2 (0x0CE – 0x0CF): P2TXQRCR2 ........................................................................... 175

Port 3 TXQ Rate Control Register 1 (0x0D0 – 0x0 D1): P3TX QRCR1 ............................................................................ 176

Port 3 TXQ Rate Control Register 2 (0x0D2 – 0x0 D3): P3TX QRCR2 ............................................................................ 176

0x0D4 – 0x0D5: Reserved .............................................................................................................................................. 176

Input and Output Multiplex Selection Register .................................................................................................................... 177

Input and Output Multiplex Selection Register (0x0D6 – 0x0D7): IO MXS EL .................................................................. 177

Configuration Status and Serial Bus Mode Register........................................................................................................... 178

Configuration Status and Serial Bus Mode Register (0x0D8 – 0x0D9): CFGR .............................................................. 178

0x0DA – 0x0DB: Reserved .............................................................................................................................................. 178

Port 1 Auto-Ne got iat ion Re gis ters ....................................................................................................................................... 179

Port 1 Auto-Negotiation Next Page Transmit Register (0x0DC – 0x0D D) : P1 AN PT ...................................................... 179

Port 1 Auto-Negotiation Link Partner Received Next Page Register (0x0DE – 0x0DF): P1ALPRNP ............................ 180

Port 1 EEE Registers .......................................................................................................................................................... 181

Port 1 EEE and Link Partner Advertisement Register (0x0E0 – 0x 0 E1) : P1 EEEA ......................................................... 181

Port 1 EEE Wake Error Count Register (0x0E2 – 0x0E3): P1EEEWEC ........................................................................ 182

Port 1 EEE Control/ Stat us and Aut o-Neg oti ati on Ex pa nsion Reg is ter (0x0 E4 – 0x0E5): P1EEEC S ............................. 182

Port 1 LPI Recovery Time Counter Register ....................................................................................................................... 184

Port 1 LPI Recovery Time Counter Register (0x0E6): P1LPIRTC .................................................................................. 184

Buffer Load-to-LPI Control 1 Register ................................................................................................................................. 184

Buffer Load to LPI Control 1 Register (0x0E7): BL2LPIC1 ............................................................................................. 184

Port 2 Auto-Ne got iat ion Re gis ters ....................................................................................................................................... 185

Port 2 Auto-Negotiation Next Page Transmit Register (0x0E8 – 0x0E9 ): P2 AN PT ........................................................ 185

Port 2 Auto-Negotiation Link Partner Received Next Page Register (0x0EA – 0x0EB) : P2ALPRNP ............................ 186

Port 2 EEE Registers .......................................................................................................................................................... 187

Port 2 EEE and Link Partner Advertisement Register (0x0EC – 0x0ED): P2EEEA ....................................................... 187

Port 2 EEE Wake Error Count Register (0x0EE – 0x0EF): P2EEEWEC ........................................................................ 188

Port 2 EEE Control/ Stat us and Aut o-Neg oti ati on Ex pa nsion Reg is ter (0x0F0 – 0x0F1): P2EEECS ............................. 188

Port 2 LPI Recovery Time Counter Register ....................................................................................................................... 190

Port 2 LPI Recovery Time Counter Register (0x0F2): P2LPIRTC .................................................................................. 190

PCS EEE Control Register .................................................................................................................................................. 190

PCS EEE Control Register (0x0F3): PCSEEEC ............................................................................................................. 190

Empty TXQ-to-LPI Wait Time Control Register .................................................................................................................. 190

Empty TXQ to LPI Wait Time Control Register (0x0F4 – 0x 0F5) : ET LWTC ................................................................... 190

Buffer Load-to-LPI Control 2 Register ................................................................................................................................. 191

Buffer Load to LPI Control 2 Register (0x0F6 – 0x0F7): BL2LPIC2 ............................................................................... 191

0x0F8 – 0x0FF: Reserved ............................................................................................................................................... 191

Internal I/O Register Space Mapping for Interrupts and Global Reset (0x100 – 0x1FF) .................................................... 192

0x100 – 0x123: Reserved ................................................................................................................................................ 192

Memory BIST Info Register (0x124 – 0x125): MBIR ....................................................................................................... 192

Global Reset Register (0x126 – 0x127): GRR ................................................................................................................ 193

0x128 – 0x18F: Reserved ............................................................................................................................................... 193

Interrupt Enable Register (0x190 – 0x191): IER ............................................................................................................. 193

Interrupt Status Register (0x192 – 0x193): ISR .............................................................................................................. 194

0x194 – 0x1FF: Reserved ............................................................................................................................................... 194

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

11 Revision 1.0

Internal I/O Register Space Mapping for Trigger Output Units (12 Units, 0x200 – 0x3FF) ................................................ 195

Trigger Error Register (0x200 – 0x201): TRIG_ERR ...................................................................................................... 195

Trigger Active Register (0x202 – 0x203): TRIG_ACTIVE ............................................................................................... 195

Trigger Done Register (0x204 – 0x205): TRIG_DONE ................................................................................................... 195

Trigger Enable Register (0x206 – 0x207): TRIG_EN ...................................................................................................... 196

Trigger Software Reset Register (0x208 – 0x209): TRIG_SW_RST .............................................................................. 196

Trigger Output Unit 12 Output PP S Puls e-Width Register (0x20A – 0x20B): TRIG12_PPS_WIDTH ............................ 196

0x20C – 0x 21F: R eser v ed ............................................................................................................................................... 196

Trigger Output Unit 1 Target Time in Nanoseconds Low-Word Register (0x220 – 0x221): TRIG1_TGT_NSL ............. 197

Trigger Output Unit 1 Target Time in Nanoseconds High-Word Register (0x222 – 0x223): TRIG1_TGT_NSH ............ 197

Trigger Output Unit 1 Target Time in Seconds Low-Word Register (0x224 – 0x225): TRIG1_TGT_SL ........................ 197

Trigger Output Unit 1 Target Time in Seconds High-Word Register (0x226 – 0x227): TRIG1_TGT_SH ....................... 197

Trigger Output Unit 1 Configuration and Control Register 1 (0x228 – 0x229): TRIG1_CFG_1 ...................................... 197

Trigger Output Un it 1 Confi gurati on and Control Register 2 (0x22A – 0x22B): TRIG1_CFG_2 ..................................... 199

Trigger Output Unit 1 Configuration and Control Register 3 (0x22C – 0x22D): TRIG1_CFG_3 .................................... 199

Trigger Output Unit 1 Configuration and Control Register 4 (0x22E – 0x22F): TRIG1_CFG_4 ..................................... 199

Trigger Output Unit 1 Configuration and Control Register 5 (0x230 – 0x231): TRIG1_CFG_5 ...................................... 199

Trigger Output Unit 1 Configuration and Control Register 6 (0x232 – 0x233): TRIG1_CFG_6 ...................................... 200

Trigger Output Unit 1 Configuration and Control Register 7 (0x234 – 0x235): TRIG1_CFG_7 ...................................... 200

Trigger Output Unit 1 Configuration and Control Register 8 (0x236 – 0x237): TRIG1_CFG_8 ...................................... 200

0x238 – 0x23F: Reserved ............................................................................................................................................... 200

Trigger Output Unit 2 Target Time and Output Configuration/Control Registers (0x240 – 0x257) ................................. 200

Trigger Output Unit 2 Configuration and Control Register 1 (0x248 – 0x249): TRIG2_CFG_1 ...................................... 201

0x258 – 0x25F: Reserved ............................................................................................................................................... 201

Trigger Output Unit 3 Target Time and Output Configuration/Control Registers (0x260 – 0x277) ................................. 201

0x278 – 0x27F: Reserved ............................................................................................................................................... 201

Trigger Output Unit 4 Target Time and Output Configuration/Control Registers (0x280 – 0x297) ................................. 201

0x298 – 0x29F: Reserved ............................................................................................................................................... 201

Trigger Output Unit 5 Target Time and Output Configuration/Control Registers (0x2A0 – 0x2B7) ................................ 201

0x2B8 – 0x2BF: Reserved ............................................................................................................................................... 201

Trigger Output Unit 6 Target Time and Output Configuration/Control Registers (0x2C0 – 0x2D7) ................................ 201

0x2D8 – 0x 2DF: Res erv ed .............................................................................................................................................. 201

Trigger Output Unit 7 Target Time and Output Configuration/Control Registers (0x2E0 – 0x2F7) ................................ 202

0x2F8 – 0x2FF: Reserved ............................................................................................................................................... 202

Trigger Output Unit 8 Target Time and Output Configuration/Control Registers (0x300 – 0x317) ................................. 202

0x318 – 0x31F: Reserved ............................................................................................................................................... 202

Trigger Output Unit 9 Target Time and Output Configuration/Control Registers (0x320 – 0x337) ................................. 202

0x338 – 0x33F: Reserved ............................................................................................................................................... 202

Trigger Output Unit 10 Target Time and Output Configuration/Control Registers (0x340 – 0x357) ............................... 202

0x358 – 0x35F: Reserved ............................................................................................................................................... 202

Trigger Output Unit 11 Target Time and Output Configuration/Control Registers (0x360 – 0x377) ............................... 202

0x378 – 0x37F: Reserved ............................................................................................................................................... 202

Trigger Output Unit 12 Target Time and Output Configuration/Control Registers (0x380 – 0x397) ............................... 202

0x398 – 0x3FF: Reserved ............................................................................................................................................... 202

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

12 Revision 1.0

Internal I/O Register Space Mapping for PTP Timestamp Inputs (12 Units, 0x400 − 0x5FF) ........................................... 203

Timestamp Enable Register (0x402 – 0x403): TS_EN ................................................................................................... 203

Timestamp Software Reset Register (0x404 – 0x 4 05): TS_SW _RST ............................................................................ 203

0x406 – 0x41F: Reserved ............................................................................................................................................... 203

Timestamp Unit 1 Status Register (0x420 – 0x421): TS1_STATUS............................................................................... 204

Timestamp Unit 1 Configuration and Control Register (0x422 – 0x423): TS1_CFG ...................................................... 204

Timestamp Unit 1 Input 1st Sample Time in Nanoseconds Low-Word Register (0x424 – 0x425): TS1_SMPL1_NSL . 205

Timestamp Unit 1 Input 1st Sample Time in Nanoseconds High-Word Register (0x426 – 0x427): TS1_SMPL1_NSH 205

Timestamp Unit 1 Input 1st Sample Time in Seconds Low-Word Register (0x428 – 0x429): TS1_SMPL1_SL ............ 205

Timestamp Unit 1 Input 1st Sample Time in Seconds High-Word Register (0x42A – 0x42B): TS1_SMPL1_SH .......... 205

Timestamp Unit 1 Input 1st Sample Time in Sub-Nanoseconds Register (0x42C – 0x42D): TS1_SMPL1_SUB_NS .... 206

0x42E – 0x4 33: R eser v ed ............................................................................................................................................... 206

Timestamp Unit 1 Input 2nd Sample Time in Nanoseconds Low-Word Register (0x434 – 0x435): TS1_SMPL2_NSL .. 206

Timestamp Unit 1 Input 2nd Sample Time in Nanoseconds High-Word Register (0x436 – 0x437): TS1_SMPL2_NSH 206

Timestamp Unit 1 Input 2nd Sample Time in Seconds Low-Word Register (0x438 – 0x439): TS1_SMPL2_SL ............ 206

Timestamp Unit 1 Input 2nd Sample Time in Seconds High-Word Register (0x43A – 0x43B): TS1_SMPL2_SH .......... 207

Timestamp Unit 1 Input 2nd Sample Time in Sub-Nanoseconds Register (0x43C – 0x43D): TS1_SMPL2_SUB_NS ... 207

0x43E – 0x43F: Reserved ............................................................................................................................................... 207

Timestamp Unit 2 Status/Configuration/Control and Input 1st Sample Time Registers (0x440 – 0x44D)....................... 207

0x44E – 0x4 53: R eser v ed ............................................................................................................................................... 207

Timestamp Unit 2 Input 2nd Sample Time Registers (0x454 – 0x45D) ........................................................................... 207

0x45E – 0x45F: Reserved ............................................................................................................................................... 207

Timestamp Unit 3 Status/Configuration/Control and Input 1st Sample Time Registers (0x460 – 0x46D)....................... 207

0x46E – 0x4 73: R eser v ed ............................................................................................................................................... 207

Timestamp Unit 3 Input 2nd Sample Time Registers (0x474 – 0x47D) ........................................................................... 207

0x47E – 0x47F: Reserved ............................................................................................................................................... 208

Timestamp Unit 4 Status/Configuration/Control and Input 1st Sample Time Registers (0x480 – 0x48D)....................... 208

0x48E – 0x4 93: R eser v ed ............................................................................................................................................... 208

Timestamp Unit 4 Input 2nd Sample Time Registers (0x494 – 0x49D) ........................................................................... 208

0x49E – 0x49F: Reserved ............................................................................................................................................... 208

Timestamp Unit 5 Status/Configuration/Control and Input 1st Sample Time Registers (0x4A0 – 0x4AD) ...................... 208

0x4AE – 0x4B3: Reserved .............................................................................................................................................. 208

Timestamp Unit 5 Input 2nd Sample Time Registers (0x4B4 – 0x4BD)........................................................................... 208

0x4BE – 0x 4BF: R eser v ed .............................................................................................................................................. 208

Timestamp Unit 6 Status/Configuration/Control and Input 1st Sample Time Registers (0x4C0 – 0x4CD) ..................... 208

0x4CE – 0x4D3: Reserved .............................................................................................................................................. 208

Timestamp Unit 6 Input 2nd Sample Time Registers (0x4D4 – 0x4DD) .......................................................................... 208

0x4DE – 0x4DF: Reserved .............................................................................................................................................. 208

Timestamp Unit 7 Status/Configuration/Control and Input 1st Sample Time Registers (0x4E0 – 0x4ED) ...................... 208

0x4EE – 0x4F3: Reserved ............................................................................................................................................... 209

Timestamp Unit 7 Input 2nd Sample Time Registers (0x4F4 – 0x4FD) ........................................................................... 209

0x4FE – 0x4FF: Reserved ............................................................................................................................................... 209

Timestamp Unit 8 Status/Configuration/Control and Input 1st Sample Time Registers (0x500 – 0x50D)....................... 209

0x50E – 0x5 13: R eser v ed ............................................................................................................................................... 209

Timestamp Unit 8 Input 2nd Sample Time Registers (0x514 – 0x51D) ........................................................................... 209

0x51E – 0x51F: Reserved ............................................................................................................................................... 209

Timestamp Unit 9 Status/Configuration/Control and Input 1st Sample Time Registers (0x520 – 0x52D)....................... 209

0x52E – 0x5 33: R eser v ed ............................................................................................................................................... 209

Timestamp Unit 9 Input 2nd Sample Time Registers (0x534 – 0x53D) ........................................................................... 209

0x53E – 0x53F: Reserved ............................................................................................................................................... 209

Timestamp Unit 10 Status/Configuration/Control and Input 1st Sample Time Registers (0x540 – 0x54D)..................... 209

0x54E – 0x5 53: R eser v ed ............................................................................................................................................... 209

Timestamp Unit 10 Input 2nd Sample Time Registers (0x554 – 0x55D) ......................................................................... 209

0x55E – 0x55F: Reserved ............................................................................................................................................... 210

Timestamp Unit 11 Status/Configuration/Control and Input 1st Sample Time Registers (0x560 – 0x56D)..................... 210

0x56E – 0x5 73: R eser v ed ............................................................................................................................................... 210

Timestamp Unit 11 Input 2nd Sample Time Registers (0x574 – 0x57D) ......................................................................... 210

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

13 Revision 1.0

0x57E – 0x57F: Reserved ............................................................................................................................................... 210

Timestamp Unit 12 Status/Configuration/Control and Input 1st Sample Time Registers (0x580 – 0x58D)..................... 210

0x58E – 0x5 93: R eser v ed ............................................................................................................................................... 210

Timestamp Unit 12 Input 2nd Sample Time Registers (0x594 – 0x59D) ......................................................................... 210

0x59E – 0x5A3: Reserved ............................................................................................................................................... 210

Timestamp Unit 12 Input 3rd Sample Time Registers (0x5A4 – 0x5AD) ......................................................................... 210

0x5AE – 0x5B3: Reserved .............................................................................................................................................. 210

Timestamp Unit 12 Input 4th Sample Time Registers (0x5B4 – 0x5BD) ......................................................................... 210

0x5BE – 0x 5C3: R eser v ed .............................................................................................................................................. 210

Timestamp Unit 12 Input 5th Sample Time Registers (0x5C4 – 0x5CD) ......................................................................... 210

0x5CE – 0x5D3: Reserved .............................................................................................................................................. 211

Timestamp Unit 12 Input 6th Sample Time Registers (0x5D4 – 0x5DD) ......................................................................... 211

0x5DE – 0x5E3: Reserv ed .............................................................................................................................................. 211

Timestamp Unit 12 Input 7th Sample Time Registers (0x5E4 – 0x5ED) ......................................................................... 211

0x5EE – 0x5F3: Reserved ............................................................................................................................................... 211

Timestamp Unit 12 Input 8th Sample Time Registers (0x5F4 – 0x5FD) .......................................................................... 211

0x5FE – 0x5FF: Reserved ............................................................................................................................................... 211

Internal I/O Registers Space Mapping for PTP 1588 Clock and Global Control (0x600 – 0x7FF) .................................... 212

PTP Clock Control Register (0x600 – 0x601): PTP_CLK_CTL ...................................................................................... 212

0x602 – 0x603: Reserved ................................................................................................................................................ 213

PTP Real Time Clock in Nanoseconds Low-Word Register (0x604 – 0x605): PTP_RTC_NSL .................................... 213

PTP Real Time Clock in Nanoseconds High-Word Register (0x606 – 0x607): PTP_RTC_NSH ................................... 213

PTP Real Time Clock in Seconds Low-Word Register (0x608 – 0x609): PTP_RTC_SL ............................................... 213

PTP Real Time Clock in Seconds High-Word Register (0x60A – 0x 60B): PT P_ RTC_SH ............................................. 213

PTP Real Time Clock in Phase Register (0x60C – 0x60D): PTP_RTC_PHASE ........................................................... 214

0x60E – 0x60F: Reserved ............................................................................................................................................... 214

PTP Rate in Su b -Nanoseconds Low-Word Register (0x610 – 0x611): PTP_SNS_RATE_L ......................................... 214

PTP Rate in Su b -Nanoseconds High-Word and Control Register (0x612 – 0x613): PTP_SNS_RATE_H .................... 215

PTP Temporary Adjustment Mode Duration in Low-Word Register (0x614 – 0x615): PTP_TEMP_ADJ_DURA_L ...... 215

PTP Temporary Adjustment Mode Duration in High-Word Register (0x616 – 0x617): PTP_TEMP_ADJ_DURA_H ..... 215

0x618 – 0x61F: Reserved ............................................................................................................................................... 215

PTP Message Configuration 1 Register (0x620 – 0x621): PTP_MSG_CFG_1 .............................................................. 216

PTP Message Configuration 2 Register (0x622 – 0x623): PTP_MSG_CFG_2 .............................................................. 217

PTP Domain and Version Register (0x624 – 0x6 25): PTP_DOMA IN_ VER ................................................................... 218

0x626 – 0x63F: Reserved ............................................................................................................................................... 218

PTP Port 1 Receive Latency Register (0x640 – 0x641): PTP_P1_RX_LATENCY ........................................................ 218

PTP Port 1 Transmit Latency Register (0x642 – 0x643): PTP_P1_TX_LATENCY ........................................................ 219

PTP Port 1 Asymmetry Correction Register (0x644 – 0x645): PTP_P1_ASYM_COR ................................................... 219

PTP Port 1 Link Delay Register (0x646 – 0x647): PTP_P1_LINK_DLY ......................................................................... 219

PTP Port 1 Egress Timestamp Low-Word Register for Pdelay_Req and Delay_Req (0x648 – 0x649):

P1_XDLY_REQ_TSL ...................................................................................................................................................... 219

PTP Port 1 Egress Timestamp High-Word Register for Pdelay_Req and Delay_Req (0x64A – 0x64B):

P1_XDLY_REQ_TSH ...................................................................................................................................................... 220

PTP Port 1 Egress Timestamp Low-Word Register for Sync (0x64C – 0x64D): P1_SYNC_TSL .................................. 220

PTP Port 1 Egress Timestamp High-Word Register for Sync (0x64E – 0x64F): P1_SYNC_TSH ................................. 220

PTP Port 1 Egress Timestamp Low-Word Register for Pdelay_Resp (0x650 – 0x651): P1_PDLY_RESP_TSL .......... 220

PTP Port 1 Egress Timestamp High-Word Register for Pdelay_Resp (0x652 – 0x653): P1_PDLY_RESP_TSH ......... 220

0x654 – 0x65F: Reserved ............................................................................................................................................... 220

PTP Port 2 Receive Latency Register (0x660 – 0x661): PTP_P2_RX_LATENCY ........................................................ 221

PTP Port 2 Transmit Latency Register (0x662 – 0x663): PTP_P2_TX_LATENCY ........................................................ 221

PTP Port 2 Asymmetry Correction Register (0x664 – 0x665): PTP_P2_ASYM_COR ................................................... 221

PTP Port 2 Link Delay Register (0x666 – 0x667): PTP_P2_LINK_DLY ......................................................................... 221

PTP Port 2 Egress Timestamp Low-Word Register for Pdelay_Req and Delay_Req (0x668 – 0x669):

P2_XDLY_REQ_TSL ...................................................................................................................................................... 221

PTP Port 2 Egress Timestamp High-Word Register for Pdelay_Req and Delay_Req (0x66A – 0x66B):

P2_XDLY_REQ_TSH ...................................................................................................................................................... 222

PTP Port 2 Egress Timestamp Low-Word Register for Sync (0x66C – 0x66D): P2_SYNC_TSL .................................. 222

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

14 Revision 1.0

PTP Port 2 Egress Timestamp High-Word Register for Sync (0x66E – 0x66F): P2_SYNC_TSH ................................. 222

PTP Port 2 Egress Timestamp Low-Word Register for Pdelay_Resp (0x670 – 0x671): P2_PDLY_RESP_TSL .......... 222

PTP Port 2 Egress Timestamp High-Word Register for Pdelay_Resp (0x672 – 0x673): P2_PDLY_RESP_TSH ......... 222

0x674 – 0x67F: Reserved ............................................................................................................................................... 222

GPIO Monitor Register (0x680 – 0x681): GPIO_MONITOR ........................................................................................... 223

GPIO Output Enable Register (0x682 – 0x683): GPIO_OEN ......................................................................................... 223

0x684 – 0x687: Reserved ................................................................................................................................................ 223

PTP Trigger Unit Interrupt Status Register (0x688 – 0x689): PTP_TRIG_IS ................................................................. 223

PTP Trigger Unit Interrupt Enable Register (0x68A – 0 x 68B): PT P_TRIG_IE ............................................................... 223

PTP Timestamp Unit Interrupt Status Register (0x68C – 0x68D): PTP_TS_IS .............................................................. 224

PTP Timestamp Unit Interrupt Enable Register (0x68E – 0x68F): PT P_T S_IE ............................................................. 225

0x690 – 0x733: Reserved ................................................................................................................................................ 225

DSP Control 1 Register (0x734 – 0x735): DSP_CNTRL_6 ............................................................................................ 225

0x736 – 0x747: Reserved ................................................................................................................................................ 225

Analog Control 1 Register (0x748 – 0x749): ANA_CNTRL_1 ......................................................................................... 226

0x74A – 0x74B: Reserved ............................................................................................................................................... 226

Analog Control 3 Register (0x74C – 0x74D): ANA_CNTRL_3 ....................................................................................... 226

0x74E – 0x7F F: Res er ved ............................................................................................................................................... 226

MII Management (MIIM) Registers...................................................................................................................................... 227

PHY1 (PHYAD = 0x1) and PHY2 (PHYAD = 0x2): Register 0 (REGAD = 0x0) -> MII Basic Control ............................ 228

PHY1 (PHYAD = 0x1) and PHY2 (PHYAD = 0x2): Register 1 (REGAD = 0x1) -> MII Basic Status .............................. 229

PHY1 (PHYAD = 0x1) and PHY2 (PHYAD = 0x2): Register 2 (REGAD = 0x2) -> PHYID High .................................... 230

PHY1 (PHYAD = 0x1) and PHY2 (PHYAD = 0x2): Register 3 (REGAD = 0x3) -> P HYI D Lo w ..................................... 230

PHY1 (PHYAD = 0x1) and PHY2 (PHYAD = 0x2): Reg. 4 (REGAD = 0x4) -> Auto-Negotiation Advertisement Ability 230

PHY1 (PHYAD = 0x1) and PHY2 (PHYAD = 0x2): Reg. 5 (REGAD = 0x5) -> Auto-Negotiation Link Partner Ability .... 231

PHY1 (PHYAD = 0x1) and PHY2 (PHYAD = 0x2): Reg. 29 (REGAD = 0x1D) -> LinkMD Control and Status .............. 232

PHY1 (PHYAD = 0x1) and PHY2 (PHYAD = 0x2): Reg. 31 (REGAD = 0x1F) -> P H Y Special Control and Sta tus ...... 232

Management Information Base (MIB) Counters ................................................................................................................. 233

Additional MIB Information .............................................................................................................................................. 235

Static MAC Address Table .................................................................................................................................................. 236

Static MAC Table Lookup Examples: .............................................................................................................................. 237

Dynamic MAC Address Table ............................................................................................................................................. 238

Dynamic MAC Address Lookup Example ....................................................................................................................... 238

VLAN Table ......................................................................................................................................................................... 239

VLAN Table Lookup Examples........................................................................................................................................ 239

Absolute Maximum Ratings ................................................................................................................................................ 240

Operating Ratings ............................................................................................................................................................... 240

Electrical Characteristics ..................................................................................................................................................... 240

Timing Specifications .......................................................................................................................................................... 244

MII Transmit Timing in MAC Mode .................................................................................................................................. 244

MII Receive Timing in MAC Mode ................................................................................................................................... 245

MII Receive Timing in PHY Mode.................................................................................................................................... 246

MII Transmit Timing in PHY Mode .................................................................................................................................. 247

Reduced MII (RMII) Timing ............................................................................................................................................. 248

MIIM (MDC/MDIO) Timing ............................................................................................................................................... 249

SPI Input and Output Timing ........................................................................................................................................... 250

Auto-Negotiation Timing .................................................................................................................................................. 251

Trigger Output Unit and Timestamp Input Unit Timing .................................................................................................... 252

Reset and Power Sequence Timing ................................................................................................................................ 254

Reset Circuit Guidelines ...................................................................................................................................................... 255

Reference Clock – Connection and Selection .................................................................................................................... 256

Selection of Reference Crystal............................................................................................................................................ 256

Selection of Isolation Transformers..................................................................................................................................... 257

Package Information and Recommended Landing Pattern ................................................................................................ 258

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

15 Revision 1.0

List of Figures

Figure 1. Typical Straight Cable Connection ........................................................................................................................ 30

Figure 2. Typical Crossover Cable Connection .................................................................................................................... 31

Figure 3. Auto-Nego tia ti on and Par a llel Op erat ion ............................................................................................................... 32

Figure 4. Near-End and Far-End Loopback .......................................................................................................................... 34

Figure 5. Destination Address Lookup Flow Chart in Stage One ......................................................................................... 36

Figure 6. Destination Address Resolution Flow Chart in Stage Two .................................................................................... 37

Figure 7. Tail Tag Frame Format .......................................................................................................................................... 41

Figure 8. 802.1p Priority Field Format .................................................................................................................................. 44

Figure 9. PTP System Clock Overview ................................................................................................................................. 49

Figure 10. Trigger Output Unit Organization and Associated Registers ............................................................................... 56

Figure 11. Timestamp Input Unit Organization and Associated Registers ........................................................................... 57

Figure 12. Trigger Unit Interrupts .......................................................................................................................................... 58

Figure 13. Timestamp Unit Interrupts ................................................................................................................................... 58

Figure 14. Complex Waveform Generation Using Cascade Mode ....................................................................................... 63

Figure 15. Recom mended Low-V olt age Po wer Conne c tion using an Extern al Lo w -Voltage Regulator .............................. 68

Figure 16. Rec om mended Lo w-Voltage Power Connection using the Internal Low-Voltage Regulator .............................. 69

Figure 17. Traffic Activity and EEE ....................................................................................................................................... 71

Figure 18. SPI Regis ter Read Operatio n − Low-Speed Mode .............................................................................................. 75

Figure 19. SPI Regis ter Read Operatio n − High-Speed Mode ............................................................................................. 75

Figure 20. SPI Register Write Operation Timing ................................................................................................................... 75

Figure 21. Interface and Register Mapping ........................................................................................................................... 80

Figure 22. MII Trans mit Timing in MAC Mode .................................................................................................................... 244

Figure 23. MII Receive Timing in MAC Mode ..................................................................................................................... 245

Figure 24. MII Receive Timing in PHY Mode ...................................................................................................................... 246

Figure 25. MII Trans mit Timing in PHY Mode ..................................................................................................................... 247

Figure 26. RMII Transmit Timing......................................................................................................................................... 248

Figure 27. RMII Receive Tim ing.......................................................................................................................................... 248

Figure 28. MIIM (MDC/MDIO) Timing ................................................................................................................................. 249

Figure 29. SPI Interface Data Input Timing ......................................................................................................................... 250

Figure 30. SPI Interface Data Output Timing ...................................................................................................................... 250

Figure 31. Auto-Negotiation Timing .................................................................................................................................... 251

Figure 32. Trigger Output Unit and Timestamp Input Unit Timing ...................................................................................... 252

Figure 33. Reset and Po we r Sequence T iming .................................................................................................................. 254

Figure 34. Simple Reset Circuit .......................................................................................................................................... 255

Figure 35. Recommended Reset Circuit for Interfacing with a CPU/FPGA Output ............................................................ 255

Figure 36. Input Reference Clock Connection Options ...................................................................................................... 256

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

16 Revision 1.0

List of Tables

Table 1. MDI/MDI-X Pin Definitions ...................................................................................................................................... 30

Table 2. Spanning Tree States ............................................................................................................................................. 40

Table 3. Tail Tag Rules ......................................................................................................................................................... 42

Table 4. FID + DA Lookup in VLAN Mode ............................................................................................................................ 43

Table 5. FID + SA Lookup in VLAN Mode ............................................................................................................................ 44

Table 6. GPIO Pin Reference ............................................................................................................................................... 54

Table 7. Trigger Output Units and Timestamp Input Units Summary ................................................................................... 55

Table 8. GPIO Registers Affecting Either All or Specific Units ............................................................................................. 55

Table 9. Device Clocks and Related Pins ............................................................................................................................. 66

Table 10. Voltage Options and Requirements ...................................................................................................................... 68

Table 11. Power Management and Internal Blocks .............................................................................................................. 70

Table 12. Available Interfaces ............................................................................................................................................... 73

Table 13. SPI Connection ..................................................................................................................................................... 73

Table 14. Register Access using the SPI Interface............................................................................................................... 74

Table 15. MII Management Interface Frame Format ............................................................................................................ 76

Table 16. MII Interface Signal and Pin Associations............................................................................................................. 77

Table 17. RMII Clock Settings ............................................................................................................................................... 78

Table 18. RMII Signal Descriptions ....................................................................................................................................... 78

Table 19. RMII PHY-to-MAC and MAC-to-MAC Signa l Connections ................................................................................... 79

Table 20. Mapping of Functional Areas within the Address Space ...................................................................................... 81

Table 21. Ingress or Egress Data Rate Limits .................................................................................................................... 148

Table 22. PHY Register Mapping using the MII Interface ................................................................................................... 227

Table 23. Format of Per-Port MIB Counters ....................................................................................................................... 233

Table 24. Port 1 MIB Counters − Indirect Memory Offset ................................................................................................... 234

Table 25. "All Ports Dropped Packet" MIB Counter Format ............................................................................................... 235

Table 26. "All Ports Dropped Packet" MIB Counters − Indirect Memory Offsets ................................................................ 235

Table 27. Static MAC Table Format (8 Entries) .................................................................................................................. 236

Table 28. Dynamic MAC Address Table Format (1024 Entries) ......................................................................................... 238

Table 29. VLAN Table Format (16 Entries) ......................................................................................................................... 239

Table 30. MII Transmit Timing Parameters in MAC Mode .................................................................................................. 244

Table 31. MII Receive Timing Parameters In MAC Mode .................................................................................................. 245

Table 32. MII Receive Timing Parameters IN PHY Mode .................................................................................................. 246

Table 33. MII Transmit Timing Parameters in PHY Mode .................................................................................................. 247

Table 34. RMII Timing Parameters ..................................................................................................................................... 248

Table 35. MDC/MDIO Timing Parameters .......................................................................................................................... 249

Table 36. SPI Timing Parameters ....................................................................................................................................... 250

Table 37. Auto-Negotiation Timing Parameters .................................................................................................................. 251

Table 38. Trigger Output Unit and Timestamp Input Unit Timing Parameters ................................................................... 253

Table 39. Reset and Power Sequence Timing Parameters ................................................................................................ 254

Table 40. Typical Reference Crystal Characteristics .......................................................................................................... 256

Table 41. Transformer Selection Criteria ............................................................................................................................ 257

Table 42. Qualified Single Port Magnetics .......................................................................................................................... 257

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

17 Revision 1.0

Acronyms

BIU Bus Interface Unit The host interface function that perform s code conversion , buffering,

and the like required for communications to and from a network.

BPDU Bridge Protocol Data Unit A packet containing ports, address es, etc . to make sure data being

passed through a bridged network arrives at its proper destination.

CMOS Complementary Metal Oxide

Semiconductor A common semiconductor manufacturing technique in which positive

and negative types of transistors are combined to form a current gate

that in turn forms an effective means of controlling electrical current

through a chip.

CRC Cyclic Redundancy Check A common technique for detecting data transmission errors. CRC for

Ethernet is 32 bits long.

CUT-THROUGH SWITCH A switch typically processes received packets by reading in the full

packet (storing), then processing the packet to determine where it

needs to go, then forwarding it. A cut-through switch simply reads in

the first bit of an incoming packet and forwards the packet. Cut-

through switches do not store the packet.

DA Destination Address The address to send packets.

EMI Electro-M agnetic Interference A naturally occurring phenomena when the electromagnetic field of

one device disrupts, impedes or degrades the electromagnetic field

of another device by coming into proximity with it. In computer

technology, computer devices are susceptible to EMI because

electromagnetic fields are a byproduct of passing electri city through

a wire. Data lines that have not been properly shielded are

susceptible to data corruption by EMI.

FCS Frame Check Sequence See CRC.

FID Frame or Filter ID Specifies the frame identifier. Alternately is the filter identi fier.

GPIO General Purpose Input/Output General Purpose Input/Output pins are signal pins that can be

controlled or monitored by hardware and software to perform specific

tasks.

IGMP Internet Group Management

Protocol The protocol defined by RFC 1112 for IP multicast transmissions.

IPG Inter-Packet Gap A time delay between successive data packets mandated by the

network standard for protocol reasons. In Ethernet, the medium has

to be "silent" (i.e., no data tr an sfer) f or a short per iod of time before a

node can consider the network idl e and start to transmit. IPG is used

to correct timing differences between a transmitter and receiver.

During the IPG, no data is transferred, and information in the gap can

be discarded or additions inserted without impact on data integrity.

ISI Inter-Symbol Interference The disruption of transmitted code caused by adjacent pulses

affecting or interfering with each other.

ISA Industry Standard Architecture A bus architecture used in the IBM PC/XT and PC/AT.

Jumbo Packet A packet larger than the standard Ethernet packet (1500 bytes).

Large packet size s allow for more effic ient use of bandw idth, lower

overhead, less processing, etc.

MAC Media Access Controller a functional block responsible for implementing the media access

control layer which is a sub layer of the data link layer.

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

18 Revision 1.0

Acronyms (Continued)

MDI Medium Dependent Interface An Ethernet port connection that allows network hubs or

switches to connect to other hubs or switches without a

null-modem, or crossover, cable. MDI provides the

standard interface to a particular media (copper or fiber)

and is therefore “media dependent”.

MDI-X Medium Dependent Interface Crossover An Ethernet port connection that allows networked end

stations (i.e., PCs or workstations) to connect to each

other using a null-modem, or crossover, cable. For 10/100

full-duplex networks, an end point (such as a computer)

and a switch are wired so that each transmitter connects

to the far end receiver. When connecting two computers

together, a cable that crosses the TX and RX is required

to do this. With auto MDI-X, the PHY senses the correct

TX and RX roles, eliminating any cable confusion.

MIB M anagement Inf or mat ion B ase The MIB comprises the management portion of network

devices. This can include things like monitoring traffic

levels and faults (statistical), and can also change

operating para met er s in netw or k nodes (stat ic forw arding

addresses).

MII Media Independent Interface The MII accesses PHY registers as defined in the IEEE

802.3 specific atio n.

NIC Network Interface Card An expansion board inserted into a computer to allow it to

be connected to a network. Most NICs are designed for a

particular type of network, protocol, and media, although

some can serve multiple networks.

NPVID Non-Port VLAN ID The port VLAN ID value is used as a VLAN reference.

NRZ Non-Return to Zero A type of signal data encoding whereby the signal does

not return to a zero state in between bits.

PHY A device or functional block which performs the physical

layer interface function in a network.

PLL Phase-Locked Loop An electronic circuit that controls an oscillator so that it

maintains a constant phase angle (i.e., lock) on the

frequency of an input, or reference, signal. A PLL ensures

that a communicat ion sig nal is locked on a specifi c

frequency and can also be used to generate, modulate,

and demodulate a signal and divide a frequency.

PTP Precision Time Protocol A protocol, IEEE 1588 as applied to this device, for

synchroniz ing the cloc ks of dev ices attache d to a specifi c

network.

SA Source Address The address from which information has been sent.

TDR Time Domain Reflectometry TDR is used to pinpoint flaws and problems in

underground and aerial wire, cabling, and fiber optics.

They send a signal down the conductor and measure the

time it takes for the signal -- or part of the signal -- to

return.

TSU Timestamp Input Unit The functional block which captures signals on the GPIO

pins and assigns a time to the specific event.

TOU Trigger Output Unit The functional block which generates user configured

waveforms on a specified GPIO pin at a specific trigger

time.

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

19 Revision 1.0

Acronyms (Continued)

UTP Unshielded Twisted Pair Commonly a cable containing 4 twisted pairs of wires. The

wires are twisted in such a manner as to cancel electrical

interference generated in each wire, therefore shielding is

not required.

VLAN Virtual Local Area Network A configuration of comput ers that acts as if all computers

are connected by the same physical network but which

may be located virtually anywhere.