PRELIMINARY PRODUCT SPECIFICATION 1 Z86E04/E08 1 CMOS Z8 OTP MICROCONTROLLERS PRODUCT DEVICES Part Number Z86E0412PEC Z86E0412PSC1860 Z86E0412PSC1866 Z86E0412PSC1903 Z86E0412PSC1924 Z86E0412SEC Z86E0412SSC1860 Z86E0412SSC1866 Z86E0412SSC1903 Z86E0412SSC1924 Z86E0812PEC Z86E0812PSC1860 Z86E0812PSC1866 Z86E0812PSC1903 Z86E0812PSC1924 Z86E0812SEC Z86E0812SSC1860 Z86E0812SSC1866 Z86E0812SSC1903 Z86E0812SSC1924 Oscillator Operating ROM Type Operating VCC Temperature (KB) Package Crystal Crystal Crystal RC RC Crystal Crystal Crystal RC RC Crystal Crystal Crystal RC RC Crystal Crystal Crystal RC RC 4.5V - 5.5V 3.0V - 5.5V 4.5V - 5.5V 4.5V - 5.5V 3.0V - 5.5V 4.5V - 5.5V 3.0V - 5.5V 4.5V - 5.5V 4.5V - 5.5V 3.0V - 5.5V 4.5V - 5.5V 3.0V - 5.5V 4.5V - 5.5V 4.5V - 5.5V 3.0V - 5.5V 4.5V - 5.5V 3.0V - 5.5V 4.5V - 5.5V 4.5V - 5.5V 3.0V - 5.5V -40C/105C 0C/70C 0C/70C 0C/70C 0C/70C -40C/105C 0C/70C 0C/70C 0C/70C 0C/70C -40C/105 C 0C/70 C 0C/70C 0C/70C 0C/70C -40C/105C 0C/70C 0C/70C 0C/70C 0C/70C 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 18-Pin DIP 18-Pin DIP 18-Pin DIP 18-Pin DIP 18-Pin DIP 18-Pin SOIC 18-Pin SOIC 18-Pin SOIC 18-Pin SOIC 18-Pin SOIC 18-Pin DIP 18-Pin DIP 18-Pin DIP 18-Pin DIP 18-Pin DIP 18-Pin SOIC 18-Pin SOIC 18-Pin SOIC 18-Pin SOIC 18-Pin SOIC Several key product features of the extensive family of Zilog Z86E04/E08 CMOS OTP microcontrollers are presented in the above table. This table enables the user to identify which of the twenty E04/E08 product variants most closely match the user's application requirements. DS97Z8X0401 PRELIMINARY 1 Z86E04/E08 CMOS Z8 OTP Microcontrollers Zilog FEATURES 14 Input / Output Lines Two Programmable 8-Bit Counter/Timers, Each with 6-Bit Programmable Prescaler Six Vectored, Prioritized Interrupts (3 falling edge, 1 rising edge, 2 timers) WDT/ Power-On Reset (POR) Two Analog Comparators On-Chip Oscillator that Accepts XTAL, Ceramic Resonance, LC, RC, or External Clock Program Options: - Low Noise - ROM Protect - Auto Latch - Watch-Dog Timer (WDT) - EPROM/Test Mode Disable Clock-Free WDT Reset Low-Power Consumption (50 mw typical) Fast Instruction Pointer (1s @ 12 MHz) RAM Bytes (125) GENERAL DESCRIPTION Zilog's Z86E04/E08 Microcontrollers (MCU) are One-Time Programmable (OTP) members of Zilog's single-chip Z8 (R) MCU family that allow easy software development, debug, prototyping, and small production runs not economically desirable with masked ROM versions. For applications demanding powerful I/O capabilities, the Z86E04/E08's dedicated input and output lines are grouped into three ports, and are configurable under software control to provide timing, status signals, or parallel I/O. Note: All Signals with a preceding front slash, "/", are active Low, for example: B//W (WORD is active Low); /B/W (BYTE is active Low, only). Power connections follow conventional descriptions below: Connection Circuit Device Power Ground VCC VDD GND VSS Two on-chip counter/timers, with a large number of user selectable modes, offload the system of administering real-time tasks such as counting/timing and I/O data communications. 2 PRELIMINARY DS97Z8X0401 Z86E04/E08 CMOS Z8 OTP Microcontrollers Zilog Input XTAL Vcc Machine Timing & Inst. Control Port 3 Counter/ Timers (2) ALU Interrupt Control FLAG Two Analog Comparators 1 GND Register Pointer OTP Program Counter General-Purpose Register File Port 2 Port 0 I/O (Bit Programmable) I/O Figure 1. Functional Block Diagram DS97Z8X0401 PRELIMINARY 3 Z86E04/E08 CMOS Z8 OTP Microcontrollers Zilog GENERAL DESCRIPTION (Continued) D7 - 0 AD 11- 0 Z8 MCU AD 11- 0 MSN Port 3 Address MUX D7 - 0 AD 11- 0 EPROM Data MUX D7 - 0 Z8 Port 0 Z8 Port 2 ROM PROT Low Noise PGM + Test Mode Logic VPP P33 EPM P32 /OE P31 /PGM P30 /CE XT1 Figure 2. EPROM Programming Mode Block Diagram 4 PRELIMINARY DS97Z8X0401 Z86E04/E08 CMOS Z8 OTP Microcontrollers Zilog PIN DESCRIPTION D4 D5 D6 D7 VCC NC /CE /OE EPM 1 18 9 10 D3 D2 D1 D0 GND /PGM CLOCK CLEAR VPP P24 P25 P26 P27 VCC XTAL2 XTAL1 P31 P32 1 18 9 10 Figure 3. 18-Pin EPROM Mode Configuration Figure 4. 18-Pin DIP/SOIC Mode Configuration Table 1. 18-Pin DIP Pin Identification Table 2. 18-Pin DIP/SOIC Pin Identification EPROM Programming Mode Pin # Symbol Function 1-4 5 D4-D7 VCC Data 4, 5, 6, 7 Power Supply 6 7 8 9 10 N/C /CE /OE EPM VPP No Connection Chip Enable Output Enable EPROM Prog Mode Prog Voltage Clear Clock /PGM GND D0-D3 Clear Clock Address Prog Mode Ground Data 0,1, 2, 3 11 12 13 14 15-18 DS97Z8X0401 Direction In/Output Input Input Input Input Input Input Input 1 P23 P22 P21 P20 GND P02 P01 P00 P33 Standard Mode Pin # Symbol Function Direction 1-4 5 P24-P27 Vcc Port 2, Pins 4,5,6,7 Power Supply In/Output 6 7 8 9 10 11-13 14 15-18 XTAL2 XTAL1 P31 P32 P33 P00-P02 GND P20-P23 Crystal Osc. Clock Crystal Osc. Clock Port 3, Pin 1, AN1 Port 3, Pin 2, AN2 Port 3, Pin 3, REF Port 0, Pins 0,1,2 Ground Port 2, Pins 0,1,2,3 Output Input Input Input Input In/Output In/Output In/Output PRELIMINARY 5 Z86E04/E08 CMOS Z8 OTP Microcontrollers Zilog ABSOLUTE MAXIMUM RATINGS Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for an extended period may affect device reliability. Total power dissipation should not exceed 462 mW for the package. Power dissipation is calculated as follows: Total Power Dissipation = VDD x [I DD - (sum of IOH)] + sum of [(V DD - VOH) x IOH] + sum of (V0L x I0L) Parameter Min Max Units Ambient Temperature under Bias Storage Temperature Voltage on any Pin with Respect to VSS -40 -65 -0.7 +105 +150 +12 C C V Voltage on VDD Pin with Respect to VSS -0.3 +7 V Voltage on Pins 7, 8, 9, 10 with Respect to VSS -0.6 VDD+1 V Total Power Dissipation Maximum Allowable Current out of VSS 1.65 300 W mA Maximum Allowable Current into VDD 220 mA +600 +600 25 25 60 45 A A mA mA mA mA Maximum Allowable Current into an Input Pin Maximum Allowable Current into an Open-Drain Pin Maximum Allowable Output Current Sinked by Any I/O Pin Maximum Allowable Output Current Sourced by Any I/O Pin Total Maximum Output Current Sinked by a Port Total Maximum Output Current Sourced by a Port -600 -600 Note 1 2 3 4 Notes: 1. This applies to all pins except where otherwise noted. Maximum current into pin must be 600 A. 2. There is no input protection diode from pin to V (not applicable to EPROM Mode). 3. This excludes Pin 6 and Pin 7. 4. Device pin is not at an output Low state. DD 6 PRELIMINARY DS97Z8X0401 Z86E04/E08 CMOS Z8 OTP Microcontrollers Zilog STANDARD TEST CONDITIONS The characteristics listed below apply for standard test conditions as noted. All voltages are referenced to Ground. Positive current flows into the referenced pin (Figure 5). 1 From Output Under Test 150 pF Figure 5. Test Load Diagram CAPACITANCE TA = 25C, VCC = GND = 0V, f = 1.0 MHz, unmeasured pins returned to GND. Parameter Input capacitance Output capacitance I/O capacitance DS97Z8X0401 Min Max 0 0 0 10 pF 20 pF 25 pF PRELIMINARY 7 Z86E04/E08 CMOS Z8 OTP Microcontrollers Zilog DC ELECTRICAL CHARACTERISTICS TA = 0C to +70C Sym Parameter VINMAX Max Input Voltage VCH VCL Clock Input High Voltage Clock Input Low Voltage VCC [4] Min Max Typical Note 4 @ 25C Units Conditions Notes 3.0V 12 V IIn<250 A 1 5.5V 12 V IIn<250 A 1 Driven by External Clock Generator Driven by External Clock Generator Driven by External Clock Generator Driven by External Clock Generator 3.0V 0.8 VCC VCC+0.3 1.7 V 5.5V 0.8 VCC VCC+0.3 2.8 V 3.0V VSS-0.3 0.2 VCC 0.8 V 5.5V VSS-0.3 0.2 VCC 1.7 V VIH Input High Voltage 3.0V 5.5V 0.7 VCC 0.7 VCC VCC+0.3 VCC+0.3 1.8 2.8 V V VIL Input Low Voltage 3.0V 5.5V VSS-0.3 VSS-0.3 0.2 VCC 0.2 VCC 0.8 1.5 V V VOH Output High Voltage 3.0V VCC-0.4 3.0 V IOH = -2.0 mA 5 5.5V VCC-0.4 4.8 V IOH = -2.0 mA 5 3.0V VCC-0.4 3.0 V Low Noise @ IOH = -0.5 mA 5.5V VCC-0.4 4.8 V Low Noise @ IOH = -0.5 mA VOL1 VOL2 Output Low Voltage Output Low Voltage VOFFSET Comparator Input Offset Voltage VLV IIL IOL VICR 8 VCC Low Voltage Auto Reset Input Leakage (Input Bias Current of Comparator) Output Leakage Comparator Input Common Mode Voltage Range 3.0V 0.8 0.2 V IOL = +4.0 mA 5 5.5V 0.4 0.1 V IOL = +4.0 mA 5 3.0V 0.4 0.2 V Low Noise @ IOL = 1.0 mA 5.5V 0.4 0.1 V Low Noise @ IOL = 1.0 mA 3.0V 1.0 1.0 V IOL = +12 mA, 5 IOL = +12 mA, 5 5.5V 0.8 0.8 V 3.0V 5.5V 2.2 25.0 25.0 3.0 10.0 10.0 2.8 mV mV V 3.0V -1.0 1.0 A VIN = 0V, VCC 5.5V -1.0 1.0 A VIN = 0V, VCC 3.0V -1.0 1.0 A VIN = 0V, VCC 5.5V -1.0 1.0 A VIN = 0V, VCC 0 VCC -1.0 V PRELIMINARY @ 6 MHz Max. Int. CLK Freq. DS97Z8X0401 Z86E04/E08 CMOS Z8 OTP Microcontrollers Zilog TA = 0C to +70C Sym Parameter ICC Supply Current ICC1 ICC Standby Current Supply Current (Low Noise Mode) DS97Z8X0401 VCC [4] Min Typical Note 4 Max @ 25C 3.0V 3.5 1.5 mA 5.5V 11.0 6.8 mA 3.0V 8.0 3.0 mA 5.5V 15.0 8.2 mA 3.0V 10.0 3.6 mA 5.5V 20.0 12.0 mA 3.0V 2.5 0.7 mA 5.5V 4.0 2.5 mA 3.0V 4.0 1.0 mA 5.5V 5.0 3.0 mA 3.0V 4.5 1.5 mA 5.5V 7.0 4.0 mA 3.0V 3.5 1.5 mA 5.5V 11.0 6.8 mA 3.0V 5.8 2.5 mA 5.5V 13.0 7.5 mA 3.0V 8.0 3.0 mA 5.5V 15.0 8.2 mA PRELIMINARY Units Conditions All Output and I/O Pins Floating @ 2 MHz All Output and I/O Pins Floating @ 2 MHz All Output and I/O Pins Floating @ 8 MHz All Output and I/O Pins Floating @ 8 MHz All Output and I/O Pins Floating @ 12 MHz All Output and I/O Pins Floating @ 12 MHz HALT Mode VIN = 0V,VCC @ 2 MHz HALT Mode VIN = 0V,VCC @ 2 MHz HALT Mode VIN = 0V, VCC @ 8 MHz HALT Mode VIN = 0V, VCC @ 8 MHz HALT Mode VIN = 0V, VCC @ 12 MHz HALT Mode VIN = 0V, VCC @ 12 MHz All Output and I/O Pins Floating @ 1 MHz All Output and I/O Pins Floating @ 1 MHz All Output and I/O Pins Floating @ 2 MHz All Output and I/O Pins Floating @ 2 MHz All Output and I/O Pins Floating @ 4 MHz All Output and I/O Pins Floating @ 4 MHz Notes 5,7 5,7 5,7 5,7 5,7 5,7 5,7 5,7 5,7 5,7 5,7 5,7 7 7 7 7 7 7 9 1 Z86E04/E08 CMOS Z8 OTP Microcontrollers Zilog DC ELECTRICAL CHARACTERISTICS (Continued) TA = 0C to +70C Sym Parameter ICC1 ICC2 IALL IALH VCC [4] Max @ 25C Units 3.0V 2.5 0.7 mA 5.5V 4.0 2.5 mA 3.0V 3.0 0.9 mA 5.5V 4.5 2.8 mA 3.0V 4.0 1.0 mA 5.5V 5.0 3.0 mA 3.0V 10.0 1.0 A 5.5V 10.0 1.0 A Auto Latch Low Current 3.0V 12.0 3.0 A HALT Mode VIN = 0V,VCC @ 1 MHz HALT Mode VIN = 0V,VCC @ 1 MHz HALT Mode VIN = 0V,VCC @ 2 MHz HALT Mode VIN = 0V,VCC @ 2 MHz HALT Mode VIN = 0V,VCC @ 4 MHz HALT Mode VIN = 0V,VCC @ 4 MHz STOP Mode VIN = 0V, VCC WDT is not Running STOP Mode VIN = 0V,VCC WDT is not Running 0V < VIN < VCC 5.5V 32 16 A 0V < VIN < VCC Auto Latch High Current 3.0V -8.0 -1.5 A 0V < VIN < VCC 5.5V -16.0 -8.0 A 0V < VIN < VCC Standby Current (Low Noise Mode) Standby Current Min Typical Note 4 Conditions Notes 7 7 7 7 7 7 7,8 7,8 Notes: 1. Port 2 and Port 0 only 2. VSS = 0V = GND 3. The device operates down to VLV of the specified frequency for VLV . The minimum operational VCC is determined on the value of the voltage VLV at the ambient temperature. The VLV increases as the temperature decreases. 4. The VCC voltage specification of 3.0 V guarantees 3.3 V 0.3 V with typical values measured at VCC = 3.3V. The VCC voltage specification of 5.5 V guarantees 5.0 V 0.5 V with typical values measured at VCC = 5.0 V. 5. Standard Mode (not Low EMI Mode) 6. Z86E08 only 7. All outputs unloaded and all inputs are at VCC or VSS level. 8. If analog comparator is selected, then the comparator inputs must be at VCC level. 10 PRELIMINARY DS97Z8X0401 Z86E04/E08 CMOS Z8 OTP Microcontrollers Zilog Sym Parameter VINMAX Max Input Voltage VCH VCL VIH VIL VOH VOL1 VOL2 Clock Input High Voltage Clock Input Low Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Output Low Voltage VOFFSET Comparator Input Offset Voltage VLV VCC Low Voltage Auto Reset IIL Input Leakage (Input Bias Current of Comparator) Output Leakage IOL VICR Comparator Input Common Mode Voltage Range DS97Z8X0401 VCC [4] TA = -40C to +105C Typical Note 4 Min @ 25C Max Units Conditions Notes 4.5V 12.0 V IIN < 250 A 1 5.5V 12.0 V IIN < 250 A 1 Driven by External Clock Generator Driven by External Clock Generator Driven by External Clock Generator Driven by External Clock Generator 4.5V 0.8 VCC VCC+0.3 2.8 V 5.5V 0.8 VCC VCC+0.3 2.8 V 4.5V VSS-0.3 0.2 VCC 1.7 V 5.5V VSS-0.3 0.2 VCC 1.7 V 4.5V 0.7 VCC VCC+0.3 2.8 V 5.5V 0.7 VCC VCC+0.3 2.8 V 4.5V VSS-0.3 0.2 VCC 1.5 V 5.5V VSS-0.3 0.2 VCC 1.5 V 4.5V VCC-0.4 4.8 V IOH = -2.0 mA 5 5.5V VCC-0.4 4.8 V IOH = -2.0 mA 5 4.5V VCC-0.4 V Low Noise @ IOH = -0.5 mA 5.5V VCC-0.4 V Low Noise @ IOH = -0.5 mA 4.5V 0.4 0.1 V IOL = +4.0 mA 5 5.5V 0.4 0.1 V IOL = +4.0 mA 5 4.5V 0.4 0.1 V Low Noise @ IOL = 1.0 mA 5.5V 0.4 0.1 V Low Noise @ IOL = 1.0 mA 4.5V 1.0 0.3 V IOL = +12 mA, 5 5.5V 1.0 0.3 V IOL = +12 mA, 5 4.5V 5.5V 25.0 25.0 3.8 10.0 10.0 2.8 mV mV V @ 6 MHz Max. Int. CLK Freq. 3 4.5V -1.0 1.0 A VIN = 0V, VCC 5.5V -1.0 1.0 A VIN = 0V, VCC 4.5V -1.0 1.0 A VIN = 0V, VCC 5.5V -1.0 1.0 A VIN = 0V, VCC 1.8 0 VCC -1.5 PRELIMINARY V 11 1 Z86E04/E08 CMOS Z8 OTP Microcontrollers Zilog DC ELECTRICAL CHARACTERISTICS (Continued) TA = -40C to +105C Sym Parameter ICC Supply Current ICC1 ICC 12 Standby Current Supply Current (Low Noise Mode) VCC [4] Min Typical Note 4 Max @ 25C Units 4.5V 11.0 6.8 mA 5.5V 11.0 6.8 mA 4.5V 15.0 8.2 mA 5.5V 15.0 8.2 mA 4.5V 20.0 12.0 mA 5.5V 20.0 12.0 mA 4.5V 5.0 2.5 mA 5.5V 5.0 2.5 mA 4.5V 5.0 3.0 mA 5.5V 5.0 3.0 mA 4.5V 7.0 4.0 mA 5.5V 7.0 4.0 mA 4.5V 11.0 6.8 mA 5.5V 11.0 6.8 mA 4.5V 13.0 7.5 mA 5.5V 13.0 7.5 mA 4.5V 15.0 8.2 mA 5.5V 15.0 8.2 mA PRELIMINARY Conditions Notes All Output and I/O Pins Floating @ 2 MHz All Output and I/O Pins Floating @ 2 MHz All Output and I/O Pins Floating @ 8 MHz All Output and I/O Pins Floating @ 8 MHz All Output and I/O Pins Floating @ 12 MHz All Output and I/O Pins Floating @ 12 MHz HALT Mode VIN = 0V, VCC @ 2 MHz HALT Mode VIN = 0V, VCC @ 2 MHz HALT Mode VIN = 0V, VCC @ 8 MHz HALT Mode VIN = 0V, VCC @ 8 MHz HALT Mode VIN = 0V, VCC @ 12 MHz HALT Mode VIN = 0V, VCC @ 12 MHz All Output and I/O Pins Floating @ 1 MHz All Output and I/O Pins Floating @ 1 MHz All Output and I/O Pins Floating @ 2 MHz All Output and I/O Pins Floating @ 2 MHz All Output and I/O Pins Floating @ 4 MHz All Output and I/O Pins Floating @ 4 MHz 5,7 5,7 5,7 5,7 5,7 5,7 5,7 5,7 5,7 5,7 5,7 5,7 7 7 7 7 7 7 DS97Z8X0401 Z86E04/E08 CMOS Z8 OTP Microcontrollers Zilog TA = -40C to +105C Sym Parameter ICC1 Standby Current (Low Noise Mode) ICC2 IALL IALH Standby Current Auto Latch Low Current Auto Latch High Current VCC [4] Min Typical Note 4 Max @ 25C Units Conditions 4.5V 4.0 2.5 mA 5.5V 4.0 2.5 mA 4.5V 4.5 2.8 mA 5.5V 4.5 2.8 mA 4.5V 5.0 3.0 mA 5.5V 5.0 3.0 mA 4.5V 20 1.0 A 5.5V 20 1.0 A 4.5V 40 16 A HALT Mode VIN = 0V, VCC @ 1 MHz HALT Mode VIN = 0V, VCC @ 1 MHz HALT Mode VIN = 0V, VCC @ 2 MHz HALT Mode VIN = 0V, VCC @ 2 MHz HALT Mode VIN = 0V, VCC @ 4 MHz HALT Mode VIN = 0V, VCC @ 4 MHz STOP Mode VIN = 0V, VCC WDT is not Running STOP Mode VIN = 0V, VCC WDT is not Running 0V < VIN < VCC 5.5V 40 16 A 0V < VIN < VCC 4.5V -20.0 -8.0 A 0V < VIN < VCC 5.5V -20.0 -8.0 A 0V < VIN < VCC Notes 7 7 7 7 7 7 7,8 7,8 Notes: 1. Port 2 and Port 0 only 2. VSS = 0V = GND 3. The device operates down to VLV of the specified frequency for VLV . The minimum operational VCC is determined on the value of the voltage VLV at the ambient temperature. The VLV increases as the temperature decreases. 4. VCC = 4.5V to 5.5V, typical values measured at VCC = 5.0V 5. Standard Mode (not Low EMI Mode) 6. Z86E08 only 7. All outputs unloaded and all inputs are at VCC or VSS level. 8. If analog comparator is selected, then the comparator inputs must be at VCC level. DS97Z8X0401 PRELIMINARY 13 1 Z86E04/E08 CMOS Z8 OTP Microcontrollers Zilog AC ELECTRICAL CHARACTERISTICS 1 3 Clock 2 7 2 3 7 T IN 4 5 6 IRQ N 8 9 Figure 6. AC Electrical Timing Diagram 14 PRELIMINARY DS97Z8X0401 Z86E04/E08 CMOS Z8 OTP Microcontrollers Zilog AC ELECTRICAL CHARACTERISTICS Timing Table (Standard Mode for SCLK/TCLK = XTAL/2) 1 TA= 0 C to +70 C 8 MHz No Symbol Parameter 1 TpC Input Clock Period 2 TrC,TfC Clock Input Rise and Fall Times 3 TwC Input Clock Width 4 TwTinL Timer Input Low Width 5 TwTinH Timer Input High Width 6 TpTin Timer Input Period 7 TrTin, TtTin Timer Input Rise and Fall Time 8 TwIL Int. Request Input Low Time 9 TwIH Int. Request Input High Time 10 Twdt Watch-Dog Timer Delay Time for Timeout 11 Tpor Power-On Reset Time 12 MHz VCC Min Max Min Max Units Notes 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 125 125 DC DC 25 25 83 83 DC DC 15 15 ns ns ns ns ns ns ns ns 100 100 ns ns ns ns 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1,2 1,2 1 1,2 1 1 1 1 62 62 100 70 5TpC 5TpC 8TpC 8TpC 100 100 100 70 5TpC 5TpC 25 12 50 20 180 80 41 41 100 70 5TpC 5TpC 8TpC 8TpC 100 70 5TpC 5TpC 25 12 50 20 180 80 ms ms ms ms Notes: 1. Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0. 2. Interrupt request through Port 3 (P33-P31) 3. The VDD voltage specification of 3.0V guarantees 3.3V 0.3V. The VDD voltage specification of 5.5V guarantees 5.0V 0.5V. DS97Z8X0401 PRELIMINARY 15 Z86E04/E08 CMOS Z8 OTP Microcontrollers Zilog AC ELECTRICAL CHARACTERISTICS Timing Table (Standard Mode for SCLK/TCLK = XTAL/2) TA= -40 C to +105 C 8 MHz 12 MHz No Symbol Parameter VCC Min Max Min Max Units Notes 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 125 125 DC DC 25 25 62 62 83 83 DC DC 15 15 41 41 ns ns ns ns ns ns ns ns 100 100 ns ns ns ns 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1,2 1,2 1 1,2 1 1 1 1 1 TpC Input Clock Period 2 TrC,TfC Clock Input Rise and Fall Times 3 TwC Input Clock Width 4 TwTinL Timer Input Low Width 5 TwTinH Timer Input High Width 6 TpTin Timer Input Period 7 TrTin, TtTin Timer Input Rise and Fall Time 8 TwIL Int. Request Input Low Time 9 TwIH Int. Request Input High Time 10 Twdt Watch-Dog Timer Delay Time for Timeout 11 Tpor Power-On Reset Time 70 70 5TpC 5TpC 8TpC 8TpC 70 70 5TpC 5TpC 8TpC 8TpC 100 100 70 70 5TpC 5TpC 10 10 12 12 100 100 70 70 5TpC 5TpC 10 10 12 12 100 100 ms ms ms ms Notes: 1. Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0. 2. Interrupt request made through Port 3 (P33-P31). 16 PRELIMINARY DS97Z8X0401 Z86E04/E08 CMOS Z8 OTP Microcontrollers Zilog AC ELECTRICAL CHARACTERISTICS Low Noise Mode No Symbol Parameter VCC 1 TPC Input Clock Period 2 TrC TfC Clock Input Rise and Fall Times 3 TwC Input Clock Width 4. TwTinL Timer Input Low Width 5 TwTinH Timer Input High Width 6 TpTin Timer Input Period 7 TrTin, TtTin Timer Input Rise and Fall Time 8 TwIL Low Time Int. Request Input 9 TwIH High Time Int. Request Input 10 Twdt Watch-Dog Timer Delay Time for Timeout 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V TA= 0 C to +70 C 1 MHz 4 MHz Min Max Min Max 1000 1000 DC DC 25 25 500 500 100 70 2.5TpC 2.5TpC 4TpC 4TpC 250 250 100 70 2.5TpC 2.5TpC 25 12 Units Notes DC DC 25 25 ns ns ns ns ns ns ns ns 100 100 ns ns ns ns 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1,2 1,2 1 1,2 1 1 125 125 100 70 2.5TpC 2.5TpC 4TpC 4TpC 100 100 100 70 2.5TpC 2.5TpC 25 12 1 ms ms Notes: 1. Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0. 2. Interrupt request through Port 3 (P33-P31). 3. The VDD voltage specification of 3.0V guarantees 3.3V 0.3V. The VDD voltage specification of 5.5V guarantees 5.0V 0.5V. DS97Z8X0401 PRELIMINARY 17 Z86E04/E08 CMOS Z8 OTP Microcontrollers Zilog AC ELECTRICAL CHARACTERISTICS (Continued) Low Noise Mode No Symbol Parameter VCC 1 TPC Input Clock Period 2 TrC TfC Clock Input Rise and Fall Times 3 TwC Input Clock Width 4. TwTinL Timer Input Low Width 5 TwTinH Timer Input High Width 6 TpTin Timer Input Period 7 TrTin, TtTin Timer Input Rise and Fall Time 8 TwIL Int. Request Input Low Time 9 TwIH Int. Request Input High Time 10 Twdt Watch-Dog Timer Delay Time for Timeout 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V TA= -40 C to +105 C 1 MHz 4 MHz Min Max Min Max 1000 1000 DC DC 25 25 500 500 70 70 2.5TpC 2.5TpC 4TpC 4TpC 100 100 70 70 2.5TpC 2.5TpC 10 10 250 250 Units Notes DC DC 25 25 ns ns ns ns ns ns ns ns 100 100 ns ns ns ns 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1,2 1,2 1 1,2 1 1 125 125 70 70 2.5TpC 2.5TpC 4TpC 4TpC 70 70 2.5TpC 2.5TpC 10 10 ms ms Notes: 1. Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0. 2. Interrupt request through Port 3 (P33-P31). 18 PRELIMINARY DS97Z8X0401 Z86E04/E08 CMOS Z8 OTP Microcontrollers Zilog LOW NOISE VERSION Low EMI Emission Output drivers have resistances of 500 Ohms (typical). The Z86E04/E08 can be programmed to operate in a Low EMI Emission Mode by means of a mask ROM bit option. Use of this feature results in: Oscillator divide-by-two circuitry eliminated. All pre-driver slew rates reduced to 10 ns typical. Internal SCLK/TCLK operation limited to a maximum of 4 MHz - 250 ns cycle time. The Low EMI Mode is mask-programmable to be selected by the customer at the time the ROM code is submitted. PIN FUNCTIONS OTP Programming Mode D7-D0 Data Bus. Data can be read from, or written to, the EPROM through this data bus. VCC Power Supply. It is typically 5V during EPROM Read Mode and 6.4V during the other modes (Program, Program Verify, and so on). /CE Chip Enable (active Low). This pin is active during EPROM Read Mode, Program Mode, and Program Verify Mode. /OE Output Enable (active Low). This pin drives the Data Bus direction. When this pin is Low, the Data Bus is output. When High, the Data Bus is input. EPM EPROM Program Mode. This pin controls the different EPROM Program Modes by applying different voltages. VPP Program Voltage. This pin supplies the program voltage. Clear Clear (active High). This pin resets the internal address counter at the High Level. DS97Z8X0401 Clock Address Clock. This pin is a clock input. The internal address counter increases by one with one clock cycle. /PGM Program Mode (active Low). A Low level at this pin programs the data to the EPROM through the Data Bus. Application Precaution The production test-mode environment may be enabled accidentally during normal operation if excessive noise surges above Vcc occur on the XTAL1 pin. In addition, processor operation of Z8 OTP devices may be affected by excessive noise surges on the Vpp, /CE, /EPM, /OE pins while the microcontroller is in Standard Mode. Recommendations for dampening voltage surges in both test and OTP Mode include the following: Using a clamping diode to VCC. Adding a capacitor to the affected pin. Note: Programming the EPROM/Test Mode Disable option will prevent accidental entry into EPROM Mode or Test Mode. PRELIMINARY 19 1 Z86E04/E08 CMOS Z8 OTP Microcontrollers Zilog PIN FUNCTIONS (Continued) XTAL1, XTAL2 Crystal In, Crystal Out (time-based input and output, respectively). These pins connect a parallelresonant crystal, LC, or an external single-phase clock (8 MHz or 12 MHz max) to the on-chip clock oscillator and buffer. Port 0, P02-P00. Port 0 is a 3-bit bidirectional, Schmitt-triggered CMOS-compatible I/O port. These three I/O lines can be globally configured under software control to be inputs or outputs (Figure 7). Auto Latch. The Auto Latch puts valid CMOS levels on all CMOS inputs (except P33, P32, P31) that are not externally driven. A valid CMOS level, rather than a floating node, reduces excessive supply current flow in the input buffer. On Power-up and Reset, the Auto Latch will set the ports to an undetermined state of 0 or 1. Default condition is Auto Latches enabled. Z86E04 and Z86E08 Port 0 (I/O) Open PAD Out 1.5 2.3 Hysteresis VCC @ 5.0V In Auto Latch Option R 500 k Figure 7. Port 0 Configuration 20 PRELIMINARY DS97Z8X0401 Z86E04/E08 CMOS Z8 OTP Microcontrollers Zilog Port 2, P27-P20. Port 2 is an 8-bit, bit programmable, bidirectional, Schmitt-triggered CMOS-compatible I/O port. These eight I/O lines can be configured under software control to be inputs or outputs, independently. Bits programmed as outputs can be globally programmed as either push-pull or open-drain (Figure 8). Z86E04 and Z86E08 Port 2 (I/O) Port 2 Open-Drain Open PAD Out 1.5 2.3 Hysteresis VCC @ 5.0V In Auto Latch Option R 500 k Figure 8. Port 2 Configuration DS97Z8X0401 PRELIMINARY 21 1 Z86E04/E08 CMOS Z8 OTP Microcontrollers Zilog PIN FUNCTIONS (Continued) Port 3, P33-P31. Port 3 is a 3-bit, CMOS-compatible port with three fixed input (P33-P31) lines. These three input lines can be configured under software control as digital Schmitt-trigger inputs or analog inputs. These three input lines are also used as the interrupt sources IRQ0-IRQ3, and as the timer input signal TIN (Figure 9). Z86E04 and Z86E08 R247 = P3M Port 3 0 = Digital 1 = Analog D1 TIN DIG. P31 Data Latch PAD P31 (AN1) IRQ2 + AN. IRQ3 P32 Data Latch PAD P32 (AN2) IRQ0 + PAD P33 (REF) P33 Data Latch IRQ1 Vcc IRQ 0,1,2 = Falling Edge Detection IRQ3 = Rising Edge Detection Figure 9. Port 3 Configuration 22 PRELIMINARY DS97Z8X0401 Z86E04/E08 CMOS Z8 OTP Microcontrollers Zilog Comparator Inputs. Two analog comparators are added to input of Port 3, P31, and P32, for interface flexibility. The comparators reference voltage P33 (REF) is common to both comparators. Typical applications for the on-board comparators; Zero crossing detection, A/D conversion, voltage scaling, and threshold detection. In Analog Mode, P33 input functions serve as a reference voltage to the comparators. Mode. The common voltage range is 0-4 V when the VCC is 5.0V; the power supply and common mode rejection ratios are 90 dB and 60 dB, respectively. Interrupts are generated on either edge of Comparator 2's output, or on the falling edge of Comparator 1's output. The comparator output is used for interrupt generation, Port 3 data inputs, or TIN through P31. Alternatively, the comparators can be disabled, freeing the reference input (P33) for use as IRQ1 and/or P33 input. The dual comparator (common inverting terminal) features a single power supply which discontinues power in STOP FUNCTIONAL DESCRIPTION The following special functions have been incorporated into the Z86E04/E08 devices to enhance the standard Z8 core architecture to provide the user with increased design flexibility. RESET. This function is accomplished by means of a Power-On Reset or a Watch-Dog Timer Reset. Upon powerup, the Power-On Reset circuit waits for TPOR ms, plus 18 clock cycles, then starts program execution at address 000C (Hex) (Figure 10). The Z86E04/E08 control registers' reset value is shown in Table 3. INT OSC XTAL OSC Delay Line TPOR msec 18 CLK Reset Filiter POR (Cold Start) Chip Reset P27 (Stop Mode) Figure 10. Internal Reset Configuration Power-On Reset (POR). A timer circuit clocked by a dedicated on-board RC oscillator is used for a POR timer function. The POR time allows VCC and the oscillator circuit to stabilize before instruction execution begins. The POR timer circuit is a one-shot timer triggered by one of the four following conditions: Power-bad to power-good status Stop-Mode Recovery WDT time-out WDH time-out DS97Z8X0401 Watch-Dog Timer Reset. The WDT is a retriggerable one-shot timer that resets the Z8 if it reaches its terminal count. The WDT is initially enabled by executing the WDT instruction and is retriggered on subsequent execution of the WDT instruction. The timer circuit is driven by an onboard RC oscillator. PRELIMINARY 23 1 Z86E04/E08 CMOS Z8 OTP Microcontrollers Zilog FUNCTIONAL DESCRIPTION (Continued) Table 3. Z86E04/E08 Control Registers Addr. Reg. D7 D6 Reset Condition D5 D4 D3 D2 FF FD FC FB FA SPL RP FLAGS IMR IRQ 0 0 U 0 U 0 0 U U U 0 0 U U 0 0 0 U U 0 0 0 U U 0 0 0 U U 0 0 0 U U 0 0 0 U U 0 F9 F8* F7* F6* F5 F4 F3 F2 F1 IPR P01M P3M P2M PRE0 T0 PRE1 T1 TMR U U U 1 U U U U 0 U U U 1 U U U U 0 U U U 1 U U U U 0 U 0 U 1 U U U U 0 U U U 1 U U U U 0 U U U 1 U U U U 0 U 0 0 1 U U 0 U 0 U 1 0 1 0 U 0 U 0 D1 D0 Comments IRQ3 is used for positive edge detection Inputs after reset Note: *Registers are not reset after a STOP-Mode Recovery using P27 pin. A subsequent reset will cause these control registers to be reconfigured as shown in Table 4 and the user must avoid bus contention on the port pins or it may affect device reliability. 24 PRELIMINARY DS97Z8X0401 Z86E04/E08 CMOS Z8 OTP Microcontrollers Zilog Program Memory. The Z86E04/E08 addresses up to 1K/2KB of Internal Program Memory (Figure 11). The first 12 bytes of program memory are reserved for the interrupt vectors. These locations contain six 16-bit vectors that correspond to the six available interrupts. Bytes 0-1024/2048 are on-chip one-time programmable ROM. 1023/2047 3FH/7FFH Location of First Byte of Instruction Executed After RESET 12 Interrupt Vector (Lower Byte) Interrupt Vector (Upper Byte) Register File. The Register File consists of three I/O port registers, 124 general-purpose registers, and 14 control and status registers R0-R3, R4-R127 and R241-R255, respectively (Figure 12). General-purpose registers occupy the 04H to 7FH address space. I/O ports are mapped as per the existing CMOS Z8. Location 255 (FFH) On-Chip ROM 0CH Indentifiers Stack Pointer (Bits 7-0) SPL 254 (FE) General-Purpose Register GPR 253 (FD) Register Pointer 252 (FC) Program Control Flags FLAGS 251 (FB) Interrupt Mask Register IMR 250 (FA) Interrupt Request Register IRQ 249 (F9) Interrupt Priority Register IPR 248 (F8) Ports 0-1 Mode P01M 247 (F7) Port 3 Mode P3M 246 (F6) Port 2 Mode P2M 245 (F5) T0 Prescaler PRE0 11 IRQ5 0BH 10 IRQ5 0AH 9 IRQ4 09H 8 IRQ4 08H 7 IRQ3 07H 6 IRQ3 06H 5 IRQ2 05H 4 IRQ2 04H 244 (F4) Timer/Counter 0 3 IRQ1 03H 243 (F3) T1 Prescaler 2 IRQ1 02H 242 (F2) Timer/Counter 1 1 IRQ0 01H 241 (F1H) Timer Mode 0 IRQ0 00H RP T0 PRE1 T1 TMR Not Implemented 128 Figure 11. Program Memory Map 127 (7FH) General-Purpose Registers 4 3 Port 3 P3 2 Port 2 P2 1 Reserved P1 Port 0 P0 0 (00H) Figure 12. Register File DS97Z8X0401 PRELIMINARY 25 1 Z86E04/E08 CMOS Z8 OTP Microcontrollers Zilog FUNCTIONAL DESCRIPTION (Continued) The Z86E04/E08 instructions can access registers directly or indirectly through an 8-bit address field. This allows short 4-bit register addressing using the Register Pointer. Stack Pointer. The Z86E04/E08 has an 8-bit Stack Pointer (R255) used for the internal stack that resides within the 124 general-purpose registers. In the 4-bit mode, the register file is divided into eight working register groups, each occupying 16 continuous locations. The Register Pointer (Figure 13) addresses the starting location of the active working-register group. General-Purpose Registers (GPR). These registers are undefined after the device is powered up. The registers keep their last value after any reset, as long as the reset occurs in the VCC voltage-specified operating range. Note: Register R254 has been designated as a general-purpose register and is set to 00 Hex after any reset or Stop-Mode Recovery. r7 r6 r5 r4 r3 r2 r1 r0 R253 (Register Pointer) The upper nibble of the register file address provided by the register pointer specifies the active working-register group. FF Register Group F R15 to R0 F0 7F 70 6F 60 5F 50 4F 40 3F 30 2F Specified Working Register Group The lower nibble of the register file address provided by the instruction points to the specified register. 20 1F 10 0F Register Group 1 R15 to R0 Register Group 0 R15 to R4* I/O Ports 00 *Expanded Register Group (0) is selected in this figure by handling bits D3 to D0 as "0" in Register R253(RP). R3 to R0 Counter/Timer. There are two 8-bit programmable counter/timers (T0 and T1), each driven by its own 6-bit programmable prescaler. The T1 prescaler is driven by internal or external clock sources; however, the T0 can be driven by the internal clock source only (Figure 15). The 6-bit prescalers divide the input frequency of the clock source by any integer number from 1 to 64. Each prescaler drives its counter, which decrements the value (1 to 256) that has been loaded into the counter. When both counter and prescaler reach the end of count, a timer interrupt request IRQ4 (T0) or IRQ5 (T1) is generated. The counter can be programmed to start, stop, restart to continue, or restart from the initial value. The counters are also programmed to stop upon reaching zero (Single-Pass Mode) or to automatically reload the initial value and continue counting (Modulo-N Continuous Mode). The counters, but not the prescalers, are read at any time without disturbing their value or count mode. The clock source for T1 is user-definable and is either the internal microprocessor clock divided by four, or an external signal input through Port 3. The Timer Mode register configures the external timer input (P31) as an external clock, a trigger input that is retriggerable or non-retriggerable, or used as a gate input for the internal clock. Figure 13. Register Pointer 26 PRELIMINARY DS97Z8X0401 Z86E04/E08 CMOS Z8 OTP Microcontrollers Zilog Internal Data Bus Write OSC Write 1 Read PRE0 Initial Value Register T0 Initial Value Register T0 Current Value Register /2 /4 6-Bit Down Counter 8-bit Down Counter 6-Bit Down Counter 8-Bit Down Counter PRE1 Initial Value Register T1 Initial Value Register IRQ4 Internal Clock External Clock Clock Logic /4 Internal Clock Gated Clock Triggered Clock TIN P31 Write Write IRQ5 T1 Current Value Register Read Internal Data Bus * Note: By passed, if Low EMI Mode is selected. Figure 14. Counter/Timers Block Diagram DS97Z8X0401 PRELIMINARY 27 Z86E04/E08 CMOS Z8 OTP Microcontrollers Zilog FUNCTIONAL DESCRIPTION (Continued) Interrupts. The Z86E04/E08 has six interrupts from six different sources. These interrupts are maskable and prioritized (Figure 15). The sources are divided as follows: the falling edge of P31 (AN1), P32 (AN2), P33 (REF), the rising edge of P32 (AN2), and two counter/timers. The Interrupt Mask Register globally or individually enables or disables the six interrupt requests (Table 4). When more than one interrupt is pending, priorities are resolved by a programmable priority encoder that is controlled by the Interrupt Priority register. All Z86E04/E08 interrupts are vectored through locations in program memory. When an Interrupt machine cycle is activated, an Interrupt Request is granted. This disables all subsequent interrupts, saves the Program Counter and Status Flags, and then branches to the program memory vector location reserved for that interrupt. This memory location and the next byte contain the 16-bit starting address of the interrupt service routine for that particular interrupt request. To accommodate polled interrupt systems, interrupt inputs are masked and the interrupt request register is polled to determine which of the interrupt requests needs service. Note: User must select any Z86E08 mode in Zilog's C12 ICEBOXTM emulator. The rising edge interrupt is not supported on the Z86CCP00ZEM emulator. Table 4. Interrupt Types, Sources, and Vectors Name IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 Source AN2(P32) REF(P33) AN1(P31) AN2(P32) T0 T1 Vector Location 0,1 2,3 4,5 6,7 8,9 10,11 Comments External (F)Edge External (F)Edge External (F)Edge External (R)Edge Internal Internal Notes: F = Falling edge triggered R = Rising edge triggered IRQ0 - IRQ5 IRQ IMR Global Interrupt Enable Interrupt Request 6 IPR PRIORITY LOGIC Vector Select Figure 15. Interrupt Block Diagram 28 PRELIMINARY DS97Z8X0401 Z86E04/E08 CMOS Z8 OTP Microcontrollers Zilog Clock. The Z86E04/E08 on-chip oscillator has a highgain, parallel-resonant amplifier for connection to a crystal, LC, RC, ceramic resonator, or any suitable external clock source (XTAL1 = INPUT, XTAL2 = OUTPUT). The crystal should be AT cut, up to 12 MHz max., with a series resistance (RS) of less than or equal to 100 Ohms. XTAL1 The crystal should be connected across XTAL1 and XTAL2 using the vendors crystal recommended capacitors from each pin directly to device ground pin 14 (Figure 16). Note that the crystal capacitor loads should be connected to VSS, Pin 14 to reduce Ground noise injection. XTAL1 XTAL1 C1 C1 * * * L XTAL2 C2 * * Ceramic Resonator or Crystal C1, C2 = 47 pF TYP * F = 8 MHz LC R XTAL2 XTAL2 C2 XTAL1 C1 External Clock XTAL2 RC @ 5V Vcc (TYP) C1 = 100 pF R = 2K F = 6 MHz * Typical value including pin parasitics Figure 16. Oscillator Configuration DS97Z8X0401 PRELIMINARY 29 1 Z86E04/E08 CMOS Z8 OTP Microcontrollers Zilog FUNCTIONAL DESCRIPTION (Continued) Table 5. Typical Frequency Vs. RC Values VCC = 5.0V @ 25C Load Capacitor 33 pFd Resistor (R) 1.0M 560K 220K 100K 56K 20K 10K 5K 2K 1K A(Hz) 33K 56K 144K 315K 552K 1.4M 2.6M 4.4M 8M 12M 56 pFd B(Hz) 31K 52K 130K 270K 480K 1M 2M 3M 5M 7M A(Hz) 20K 34K 84K 182K 330K 884K 1.6M 2.8M 6M 8.8M 100 pFd B(Hz) 20K 32K 78K 164K 300K 740K 1.3M 2M 4M 6M A(Hz) 12K 20K 48K 100K 185K 500K 980K 1.7K 3.8K 6.3K B(Hz) 11K 19K 45K 95K 170K 450K 820K 1.3M 2.7M 4.2M 0.00 1Fd A(Hz) 1.4K 2.5K 6K 12K 23K 65K 130K 245K 600K 1.0M B(Hz) 1.4K 2.4K 6K 12K 22K 61K 123K 225K 536K 950K Notes: A = STD Mode Frequency. B = Low EMI Mode Frequency. Table 6. Typical Frequency Vs. RC Values VCC = 5.0V @ 25C Load Capacitor Resistor (R) 1.0M 560K 220K 100K 56K 20K 10K 5K 2K 1K 33 pFd A(Hz) 18K 30K 70K 150K 268K 690M 1.2M 2M 4.6M 7M B(Hz) 18K 30K 70K 148K 250K 600K 1M 1.7M 3M 4.6M 56 pFd A(Hz) 12K 20K 47K 97K 176K 463K 860K 1.5M 3.3M 5M B(Hz) 12K 20K 47K 96K 170K 416K 730K 1.2M 2.4M 3.6M 100 pFd A(Hz) 7.4K 12K 30K 60K 100K 286K 540K 950K 2.2M 3.6K B(Hz) 7.7K 12K 30K 60K 100K 266K 480K 820K 1.6M 2.6M 0.00 1Fd A(Hz) 1K 1.6K 4K 8K 15K 40K 80K 151K 360K 660K B(Hz) 1K 1.6K 4K 8K 15K 40K 76K 138K 316K 565K Notes: A = STD Mode Frequency. B = Low EMI Mode Frequency. 30 PRELIMINARY DS97Z8X0401 Z86E04/E08 CMOS Z8 OTP Microcontrollers Zilog HALT Mode. This instruction turns off the internal CPU clock but not the crystal oscillation. The counter/timers and external interrupts IRQ0, IRQ1, IRQ2 and IRQ3 remain active. The device is recovered by interrupts, either externally or internally generated. An interrupt request must be executed (enabled) to exit HALT Mode. After the interrupt service routine, the program continues from the instruction after the HALT. Watch-Dog Timer (WDT). The Watch-Dog Timer is enabled by instruction WDT. When the WDT is enabled, it cannot be stopped by the instruction. With the WDT instruction, the WDT is refreshed when it is enabled within every 1 Twdt period; otherwise, the controller resets itself, The WDT instruction affects the flags accordingly; Z=1, S=0, V=0. WDT = 5F (Hex) Note: On the C12 ICEBOX, the IRQ3 does not wake the device out of HALT Mode. STOP Mode. This instruction turns off the internal clock and external crystal oscillation and reduces the standby current to 10 A. The STOP Mode is released by a RESET through a Stop-Mode Recovery (pin P27). A Low input condition on P27 releases the STOP Mode. Program execution begins at location 000C(Hex). However, when P27 is used to release the STOP Mode, the I/O port Mode registers are not reconfigured to their default power-on conditions. This prevents any I/O, configured as output when the STOP instruction was executed, from glitching to an unknown state. To use the P27 release approach with STOP Mode, use the following instruction: LD NOP STOP Opcode WDT (5FH). The first time Opcode 5FH is executed, the WDT is enabled and subsequent execution clears the WDT counter. This must be done at least every TWDT; otherwise, the WDT times out and generates a reset. The generated reset is the same as a power-on reset of TPOR, plus 18 XTAL clock cycles. The software enabled WDT does not run in STOP Mode. Opcode WDH (4FH). When this instruction is executed it enables the WDT during HALT. If not, the WDT stops when entering HALT. This instruction does not clear the counters, it just makes it possible to have the WDT running during HALT Mode. A WDH instruction executed without executing WDT (5FH) has no effect. Permanent WDT. Selecting the hardware enabled Permanent WDT option, will automatically enable the WDT upon exiting reset. The permanent WDT will always run in HALT Mode and STOP Mode, and it cannot be disabled. P2M, #1XXX XXXXB X = Dependent on user's application. Note: A low level detected on P27 pin will take the device out of STOP Mode even if configured as an output. Auto Reset Voltage (VLV). The Z86E04/E08 has an autoreset built-in. The auto-reset circuit resets the Z86E04/E08 when it detects the VCC below VLV. In order to enter STOP or HALT Mode, it is necessary to first flush the instruction pipeline to avoid suspending execution in mid-instruction. To do this, the user executes a NOP (opcode=FFH) immediately before the appropriate SLEEP instruction, such as: Figure 18 shows the Auto Reset Voltage versus temperature. If the VCC drops below the VCC operating voltage range, the Z86E04/E08 will function down to the VLV unless the internal clock frequency is higher than the specified maximum VLV frequency. FF 6F FF 7F NOP STOP or NOP HALT DS97Z8X0401 ; clear the pipeline ; enter STOP Mode ; clear the pipeline ; enter HALT Mode PRELIMINARY 31 1 Z86E04/E08 CMOS Z8 OTP Microcontrollers Zilog FUNCTIONAL DESCRIPTION (Continued) Vcc (Volts) 2.9 2.8 2.7 2.6 2.5 2.4 Temp 2.3 -40C -20C 0C 20C 40C 60C 80C 100C Figure 17. Typical Auto Reset Voltage (VLV) vs. Temperature 32 PRELIMINARY DS97Z8X0401 Z86E04/E08 CMOS Z8 OTP Microcontrollers Zilog Low EMI Emission The Z86E04/E08 can be programmed to operate in a low EMI Emission (Low Noise) Mode by means of an EPROM programmable bit option. Use of this feature results in: Less than 1 mA consumed during HALT Mode. All drivers slew rates reduced to 10 ns (typical). Internal SCLK/TCLK = XTAL operation limited to a maximum of 4 MHz - 250 ns cycle time. Output drivers have resistances of 500 ohms (typical). Oscillator divide-by-two circuitry eliminated. The Z86E04/E08 offers programmable ROM Protect and programmable Low Noise features. When programmed for Low Noise, the ROM Protect feature is optional. In addition to VDD and GND (VSS), the Z86E04/E08 changes all its pin functions in the EPROM Mode. XTAL2 has no function, XTAL1 functions as /CE, P31 functions as /OE, P32 functions as EPM, P33 functions as VPP, and P02 functions as /PGM. ROM Protect. ROM Protect fully protects the Z86E04/E08 ROM code from being read externally. When ROM Protect is selected, the instructions LDC and LDCI are supported (Z86E04/E08 and Z86C04/C08 do not support the instructions of LDE and LDEI). When the device is programmed for ROM Protect, the Low Noise feature will not automatically be enabled. Please note that when using the device in a noisy environment, it is suggested that the voltages on the EPM and CE pins be clamped to VCC through a diode to VCC to prevent accidentally entering the OTP Mode. The VPP requires both a diode and a 100 pF capacitor. Auto Latch Disable. Auto Latch Disable option bit when programmed will globally disable all Auto Latches. WDT Enable. The WDT Enable option bit, when programmed, will have the hardware enabled Permanent WDT enabled after exiting reset and can not be stopped in Halt or Stop Mode. EPROM/Test Mode Disable. The EPROM/Test Mode Disable option bit, when programmed, will disable the EPROM Mode and the Factory Test Mode. Reading, verifying, and programming the Z8 will be disabled. To fully verify that this mode is disabled, the device must be power cycled. User Modes. Table 7 shows the programming voltage of each mode of Z86E04/E08. Table 7. OTP Programming Table VCC* Programming Modes VPP EPM /CE /OE /PGM ADDR DATA EPROM READ1 NU VH VIL VIL VIH ADDR Out 4.5V EPROM READ2 NU VH VIL VIL VIH ADDR Out 5.5V PROGRAM VH X VIL VIH VIL ADDR In 6.4V PROGRAM VERIFY VH X VIL VIL VIH ADDR Out 6.4V EPROM PROTECT VH VH VH VIH VIL NU NU 6.4V LOW NOISE SELECT VH VIH VH VIH VIL NU NU 6.4V AUTO LATCH DISABLE VH VIH VH VIL VIL NU NU 6.4V WDT ENABLE VH VIL VH VIH VIL NU NU 6.4V EPROM/TEST MODE VH VIL VH VIL VIL NU NU 6.4V Notes: 1. VH =13.0V 0.25 VDC . 2. VIH = As per specific Z8 DC specification. 3. VIL= As per specific Z8 DC specification. 4. X = Not used, but must be set to VH or VIH level. 5. NU = Not used, but must be set to either VIH or VIL level. 6. IPP during programming = 40 mA maximum. 7. ICC during programming, verify, or read = 40 mA maximum. 8. * VCC has a tolerance of - 0.25V. 9. VCC = 5.0V is acceptable. DS97Z8X0401 PRELIMINARY 33 1 Z86E04/E08 CMOS Z8 OTP Microcontrollers Zilog FUNCTIONAL DESCRIPTION (Continued) Internal Address Counter. The address of Z86E04/E08 is generated internally with a counter clocked through pin P01 (Clock). Each clock signal increases the address by one and the "high" level of pin P00 (Clear) will reset the address to zero. Figure 18 shows the setup time of the serial address input. Programming Waveform. Figures 19, 20 and 21 show the programming waveforms of each mode. Table 8 shows the timing of programming waveforms. Programming Algorithm. Figure 22 shows the flow chart of the Z86E04/E08 programming algorithm. Table 8. Timing of Programming Waveforms Parameters Name 1 2 3 Address Setup Time Data Setup Time VPP Setup 2 2 2 s s s 4 VCC Setup Time 2 s 5 6 7 8 9 10 11 12 13 14 15 16 17 Chip Enable Setup Time Program Pulse Width Data Hold Time /OE Setup Time Data Access Time Data Output Float Time Overprogram Pulse Width EPM Setup Time /PGM Setup Time Address to /OE Setup Time Option Program Pulse Width /OE Width Address Valid to /OE Low 2 0.95 2 2 188 s ms s s ns ns ms s s s ms ns ns 34 Min Max 100 2.85 2 2 2 78 250 125 PRELIMINARY Units DS97Z8X0401 Z86E04/E08 CMOS Z8 OTP Microcontrollers Zilog T2 1 P01 = Clock T4 T3 T1 P00 = Clear Vpp/EPM T6 T5 Internal Address 0 Min Vih Data Vil Invalid Valid Invalid Valid 9 Legend: T1 Reset Clock Width T2 Input Clock High T3 Input Clock Period T4 Input Clock Low T5 Clock to Address Counter Out Delay T6 Epm/Vpp Set up Time 30 ns Min 100 ns Min 200 ns Min 100 ns Min 15 ns Max 40 s Min Figure 18. Z86E04/E08 Address Counter Waveform DS97Z8X0401 PRELIMINARY 35 Z86E04/E08 CMOS Z8 OTP Microcontrollers Zilog FUNCTIONAL DESCRIPTION (Continued) VIH Address Address Stable VIL 17 VIH Data VIL Address Stable 17 Invalid Valid Invalid Valid 9 VH VPP VIL VH EPM VIL 5.5V 12 VCC 4.5V VIH /CE VIL 5 VIH /OE 16 VIL 16 16 VIH /PGM VIL 3 Figure 19. Z86E04/E08 Programming Waveform (EPROM Read) 36 PRELIMINARY DS97Z8X0401 Z86E04/E08 CMOS Z8 OTP Microcontrollers Zilog VIH Address 1 VIH Data 1 Address Stable VIL Data Stable VIL Data Out Valid 2 9 10 VH VPP VIH 3 VH EPM VIL 6V VCC 4.5V VIH 4 7 /CE VIL 5 VIH /OE VIL 13 16 VIH /PGM VIL 6 8 11 Program Cycle Verify Cycle Figure 20. Z86E04/E08 Programming Waveform (Program and Verify) DS97Z8X0401 PRELIMINARY 37 Z86E04/E08 CMOS Z8 OTP Microcontrollers Zilog FUNCTIONAL DESCRIPTION (Continued) VIH Address VIL VIH Data VIL VH VPP VIH 3 6V VCC 4.5V 4 VH /CE VIH 5 /OE VIH VH EPM VIH VIL VIH /PGM VIH 12 12 13 13 VIL 15 15 EPROM Protect Low Noise Figure 21. Z86E04/E08 Programming Options Waveform (EPROM Protect and Low Noise Program) 38 PRELIMINARY DS97Z8X0401 Z86E04/E08 CMOS Z8 OTP Microcontrollers Zilog VIH Address 1 VIL VIH Data VIL VH VPP VIH 3 6V VCC 4.5V 4 VH /CE VIH VIH 5 /OE VIL 12 12 13 13 VIH EPM VIL VIH /PGM 12 12 13 13 VIL 15 15 15 Auto Latch WDT EPROM/Test Mode Disable Figure 22. Z86E04/E08 Programming Options Waveform (Auto Latch Disable, Permanent WDT Enable and EPROM/Test Mode Disable) DS97Z8X0401 PRELIMINARY 39 Z86E04/E08 CMOS Z8 OTP Microcontrollers Zilog FUNCTIONAL DESCRIPTION (Continued) Start Addr = First Location Vcc = 6.4V Vpp = 13.0V N=0 Program 1 ms Pulse Increment N Yes N = 25 ? No Fail Verify One Byte Verify Byte Fail Pass Pass Prog. One Pulse 3xN ms Duration Increment Address No Last Addr ? Yes Vcc = Vpp = 4.5V Verify All Bytes Pass Fail Vcc = Vpp = 5.5V Verify All Bytes Pass Device Failed Fail Device Passed Figure 23. Z86E04/E08 Programming Algorithm 40 PRELIMINARY DS97Z8X0401 Z86E04/E08 CMOS Z8 OTP Microcontrollers Zilog Z8 CONTROL REGISTERS 1 R244 T0 R241 TMR D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 T0 Initial Value (When Written) (Range: 1-256 Decimal 01-00 HEX) T0 Current Value (When READ) 0 No Function 1 Load T0 0 Disable T0 Count 1 Enable T0 Count 0 No Function 1 Load T1 0 Disable T1 Count 1 Enable T1 Count TIN Modes 00 External Clock Input 01 Gate Input 10 Trigger Input (Non-retriggerable) 11 Trigger Input (Retriggerable) Figure 27. Counter/Timer 0 Register (F4H: Read/Write) R245 PRE0 D7 D6 D5 D4 D3 D2 D1 D0 Reserved (Must be 0) Count Mode 0 T0 Single Pass 1 T0 Modulo N Figure 24. Timer Mode Register (F1H: Read/Write) Reserved (Must be 0) Prescaler Modulo (Range: 1-64 Decimal 01-00 HEX) R242 T1 D7 D6 D5 D4 D3 D2 D1 D0 T 1 Initial Value (When Written) (Range 1-256 Decimal 01-00 HEX) T 1 Current Value (When READ) Figure 28. Prescaler 0 Register (F5H: Write Only) R246 P2M D7 D6 D5 D4 D3 D2 D1 D0 Figure 25. Counter Timer 1 Register (F2H: Read/Write) P2 7 - P2 0 I/O Definition 0 Defines Bit as OUTPUT 1 Defines Bit as INPUT R243 PRE1 D7 D6 D5 D4 D3 D2 D1 D0 Figure 29. Port 2 Mode Register (F6H: Write Only) Count Mode 0 = T 1 Single Pass 1 = T 1 Modulo N Clock Source 1 = T 1 Internal 0 = T 1 External Timing Input (T IN ) Mode R247 P3M D7 D6 D5 D4 D3 D2 D1 D0 Prescaler Modulo (Range: 1-64 Decimal 01-00 HEX) 0 Port 2 Open-Drain 1 Port 2 Push-pull Port 3 Inputs 0 Digital Mode 1 Analog Mode Figure 26. Prescaler 1 Register (F3H: Write Only) Reserved (Must be 0) Figure 30. Port 3 Mode Register (F7H: Write Only) DS97Z8X0401 PRELIMINARY 41 Z86E04/E08 CMOS Z8 OTP Microcontrollers Zilog Z8 CONTROL REGISTERS (Continued) R251 IMR R248 P01M D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 1 Enables IRQ0-IRQ5 (D0 = IRQ0) P02-P00 Mode 00 = Output 01 = Input Reserved (Must be 0.) 1 Enables Interrupts Reserved (Must be 1.) Reserved (Must be 0.) Figure 34. Interrupt Mask Register (FBH: Read/Write) Figure 31. Port 0 and 1 Mode Register (F8H: Write Only) R252 Flags D7 D6 D5 D4 D3 D2 D1 D0 R249 IPR D7 D6 D5 D4 D3 D2 D1 D0 User Flag F1 User Flag F2 Interrupt Group Priority Reserved = 000 C > A > B = 001 A > B > C = 010 A > C > B = 011 B > C > A = 100 C > B > A = 101 B > A > C = 110 Reserved = 111 Half Carry Flag Decimal Adjust Flag Overflow Flag Sign Flag Zero Flag Carry Flag IRQ1, IRQ4 Priority (Group C) 0 = IRQ1 > IRQ4 1 = IRQ4 > IRQ1 Figure 35. Flag Register (FCH: Read/Write) IRQ0, IRQ2 Priority (Group B) 0 = IRQ2 > IRQ0 1 = IRQ0 > IRQ2 IRQ3, IRQ5 Priority (Group A) 0 = IRQ5 > IRQ3 1 = IRQ3 > IRQ5 Reserved (Must be 0.) R253 RP D7 D6 D5 D4 D3 D2 D1 D0 Figure 32. Interrupt Priority Register (F9H: Write Only) Expanded Register File Working Register Pointer Default After Reset = 00H R250 IRQ D7 D6 D5 D4 D3 D2 Figure 36. Register Pointer (FDH: Read/Write) D1 D0 IRQ0 = P32 Input IRQ1 = P33 Input IRQ2 = P31 Input IRQ3 = P32 Input IRQ4 = T0 IRQ5 = T1 R255 SPL D7 D6 D5 D4 D3 D2 D1 D0 Reserved (Must be 0) Stack Pointer Lower Byte (SP 7 - SP 0 ) Figure 33. Interrupt Request Register (FAH: Read/Write) 42 PRELIMINARY Figure 37. Stack Pointer (FFH: Read/Write) DS97Z8X0401 Z86E04/E08 CMOS Z8 OTP Microcontrollers Zilog PACKAGE INFORMATION 1 18-Pin DIP Package Diagram 18-Pin SOIC Package Diagram DS97Z8X0401 PRELIMINARY 43 Z86E04/E08 CMOS Z8 OTP Microcontrollers Zilog ORDERING INFORMATION Z86E04 Z86E08 Standard and Extended Temperature Standard and Extended Temperature 18-Pin DIP 18-Pin SOIC 18-Pin DIP 18-Pin SOIC Z86E0412PSC Z86E0412PEC Z86E04012SC Z86E0412SEC Z86E0812PSC Z86E0812PEC Z86E0812SSC Z86E0812SEC For fast results, contact your local Zilog sales office for assistance in ordering the part(s) desired. Codes Preferred Temperature S = 0C to +70C E = -40C to +105C Preferred Package P = Plastic DIP Speeds 12 =12 MHz Longer Lead Time S = SOIC Environmental C = Plastic Standard Example: Z 86E04 12 P S C is a Z86E04, 12 MHz, DIP, 0C to +70C, Plastic Standard Flow Environmental Flow Temperature Package Speed Product Number Zilog Prefix (c) 1997 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc. Terms and Conditions of Sale only. Zilog, Inc. makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. Zilog, Inc. makes no warranty of merchantability or fitness for any purpose. Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document. 44 Zilog's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. Zilog, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 FAX (408) 370-8056 Internet: www.zilog.com PRELIMINARY DS97Z8X0401