Features * High-performance, low-power Atmel(R) AVR(R) XMEGA(R) 8/16-bit Microcontroller * Nonvolatile program and data memories * * * * * - 16K - 128KBytes of in-system self-programmable flash - 4K - 8KBytes boot section - 1K - 2KBytes EEPROM - 2K - 8KBytes internal SRAM Peripheral Features - Four-channel event system - Four 16-bit timer/counters Three timer/counters with four output compare or input capture channels One timer/counter with two output compare or input capture channels High-resolution extension on two timer/counters Advanced waveform extension (AWeX) on one timer/counter - Two USARTs with IrDA support for one USART - Two Two-wire interfaces with dual address match (I2C and SMBus compatible) - Two serial peripheral interfaces (SPIs) - CRC-16 (CRC-CCITT) and CRC-32 (IEEE 802.3) generator - 16-bit real time counter (RTC) with separate oscillator - One twelve-channel, 12-bit, 200ksps Analog to Digital Converter - Two Analog Comparators with window compare function, and current sources - External interrupts on all general purpose I/O pins - Programmable watchdog timer with separate on-chip ultra low power oscillator - QTouch(R) library support Capacitive touch buttons, sliders and wheels Special microcontroller features - Power-on reset and programmable brown-out detection - Internal and external clock options with PLL and prescaler - Programmable multilevel interrupt controller - Five sleep modes - Programming and debug interface PDI (program and debug interface) I/O and packages - 34 programmable I/O pins - 44 - lead TQFP - 44 - pad VQFN/QFN - 49 - ball VFBGA Operating voltage - 1.6 - 3.6V Operating frequency - 0 - 12MHz from 1.6V - 0 - 32MHz from 2.7V 8/16-bit Atmel XMEGA D4 Microcontroller ATxmega128D4 ATxmega64D4 ATxmega32D4 ATxmega16D4 Typical Applications * * * * * Industrial control Factory automation Building control Board control White goods * * * * * Climate control RF and ZigBee(R) Motor control Sensor control Optical * * * * * Low power battery applications Power tools HVAC Utility metering Medical applications 8135L-AVR-06/12 XMEGA D4 1. Ordering Information Ordering Code Flash [Bytes] EEPROM [Bytes] SRAM [Bytes] ATxmega128D4-AU 128K + 8K 2K ATxmega128D4-AUR (4) 128K + 8K 2K 8K ATxmega64D4-AU 64K + 4K 2K 4K Power supply Package (1)(2)(3) Temp. 8K ATxmega64D4-AUR (4) 64K + 4K 2K 4K ATxmega32D4-AU 32K + 4K 1K 4K ATxmega32D4-AUR (4) 32K + 4K 1K 4K ATxmega16D4-AU 16K + 4K 1K 2K ATxmega16D4-AUR (4) 16K + 4K 1K 2K ATxmega128D4-MH 128K + 8K 2K 8K ATxmega128D4-MHR (4) 128K + 8K 2K 8K ATxmega64D4-MH 64K + 4K 2K 4K ATxmega64D4-MHR (4) 64K + 4K 2K 4K ATxmega32D4-MH 32K + 4K 1K 4K ATxmega32D4-MHR (4) 32K + 4K 1K 4K ATxmega16D4-MH 16K + 4K 1K 2K ATxmega16D4-MHR (4) 16K + 4K 1K 2K ATxmega128D4-CU 128K + 8K 2K 8K ATxmega128D4-CUR (4) 128K + 8K 2K 8K ATxmega64D4-CU 64K + 4K 2K 4K ATxmega64D4-CUR (4) 64K + 4K 2K 4K ATxmega32D4-CU 32K + 4K 1K 4K ATxmega32D4-CUR (4) 32K + 4K 1K 4K ATxmega16D4-CU 16K + 4K 1K 2K ATxmega16D4-CUR (4) 16K + 4K 1K 2K Notes: Speed [MHz] 44A 32 1.6 - 3.6V 44M1 -40C - 85C 49C2 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information. 2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. For packaging information see "Packaging information" on page 61. 4. Tape and Reel. Package type 44A 44-Lead, 10 x 10mm body size, 1.0mm body thickness, 0.8mm lead pitch, thin profile plastic quad flat package (TQFP) 44M1 44-Pad, 7 x 7 x 1mm body, lead pitch 0.50mm, 5.20mm exposed pad, thermally enhanced plastic very thin quad no lead package (VQFN) 49C2 49-Ball (7 x 7 Array), 0.65mm pitch, 5.0 x 5.0 x 1.0mm, very thin, fine-pitch ball grid array package (VFBGA) 2 8135L-AVR-06/12 XMEGA D4 2. Pinout/Block Diagram AVCC GND PR1 PR0 RESET/PDI PDI 38 37 36 35 34 PA1 41 39 PA2 42 PA0 PA3 43 40 PA4 44 Figure 2-1. Block diagram and QFN/TQFP pinout. Power Programming, debug, test Ground External clock / Crystal pins Digital function General Purpose I /O Analog function / Oscillators Port R PA5 XOSC 1 TOSC 33 PE3 32 PE2 31 VCC 30 GND 29 PE1 28 PE0 27 PD7 26 PD6 25 PD5 24 PD4 23 PD3 DATA BUS PA6 4 PB0 PB1 5 PB2 6 PB3 7 GND 8 VCC 9 OSC/CLK Control Internal oscillators Watchdog Power Supervision Sleep Controller Real Time Counter Watchdog Timer Reset Controller Event System Controller CRC OCD Prog/Debug Interface AREF ADC AC0:1 Port B 3 PA7 Port A 2 Interrupt Controller AREF BUS matrix Internal references CPU SRAM EEPROM FLASH DATA BUS Note: TWI TC0 SPI 13 14 15 16 17 18 19 20 21 22 PC3 PC4 PC5 PC6 PC7 GND VDD PD0 PD1 PD2 Port E 12 Port D PC2 Port C USART0 TC0 SPI 11 TWI PC1 TC0:1 10 USART0 PC0 IRCOM EVENT ROUTING NETWORK 1. For full details on pinout and pin functions refer to "Pinout and Pin Functions" on page 51. 3 8135L-AVR-06/12 XMEGA D4 Figure 2-2. VFBGA pinout. Top view 1 2 3 4 5 Bottom view 6 7 7 6 5 4 3 2 1 A A B B C C D D E E F F G G Table 2-1. BGA pinout. 1 2 3 4 5 6 7 A PA3 AVCC GND PR1 PR0 PDI PE3 B PA4 PA1 PA0 GND RESET/PDI_CLK PE2 VCC C PA5 PA2 PA6 PA7 GND PE1 GND D PB1 PB2 PB3 PB0 GND PD7 PE0 E GND GND PC3 GND PD4 PD5 PD6 F VCC PC0 PC4 PC6 PD0 PD1 PD3 G PC1 PC2 PC5 PC7 GND VCC PD2 4 8135L-AVR-06/12 XMEGA D4 3. Overview The Atmel AVR XMEGA is a family of low power, high performance, and peripheral rich 8/16-bit microcontrollers based on the AVR enhanced RISC architecture. By executing instructions in a single clock cycle, the AVR XMEGA devices achieve CPU throughput approaching one million instructions per second (MIPS) per megahertz, allowing the system designer to optimize power consumption versus processing speed. The AVR CPU combines a rich instruction set with 32 general purpose working registers. All 32 registers are directly connected to the arithmetic logic unit (ALU), allowing two independent registers to be accessed in a single instruction, executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs many times faster than conventional single-accumulator or CISC based microcontrollers. The AVR XMEGA D4 devices provide the following features: in-system programmable flash with read-while-write capabilities; internal EEPROM and SRAM; four-channel event system and programmable multilevel interrupt controller; 34 general purpose I/O lines; 16-bit real-time counter (RTC); four flexible, 16-bit timer/counters with compare and PWM channels; two USARTs; two two-wire serial interfaces (TWIs); two serial peripheral interfaces (SPIs); one twelve-channel, 12bit ADC with programmable gain; two analog comparators (ACs) with window mode; programmable watchdog timer with separate internal oscillator; accurate internal oscillators with PLL and prescaler; and programmable brown-out detection. The program and debug interface (PDI), a fast two-pin interface for programming and debugging, is available. The XMEGA D4 devices have five software selectable power saving modes. The idle mode stops the CPU while allowing the SRAM, event system, interrupt controller, and all peripherals to continue functioning. The power-down mode saves the SRAM and register contents, but stops the oscillators, disabling all other functions until the next TWI, or pin-change interrupt, or reset. In power-save mode, the asynchronous real-time counter continues to run, allowing the application to maintain a timer base while the rest of the device is sleeping. In standby mode, the external crystal oscillator keeps running while the rest of the device is sleeping. This allows very fast startup from the external crystal, combined with low power consumption. In extended standby mode, both the main oscillator and the asynchronous timer continue to run. To further reduce power consumption, the peripheral clock to each individual peripheral can optionally be stopped in active mode and idle sleep mode. Atmel offers a free QTouch library for embedding capacitive touch buttons, sliders and wheels functionality into AVR microcontrollers. The devices are manufactured using Atmel high-density, nonvolatile memory technology. The program flash memory can be reprogrammed in-system through the PDI. A boot loader running in the device can use any interface to download the application program to the flash memory. The boot loader software in the boot flash section will continue to run while the application flash section is updated, providing true read-while-write operation. By combining an 8/16-bit RISC CPU with in-system, self-programmable flash, the AVR XMEGA is a powerful microcontroller family that provides a highly flexible and cost effective solution for many embedded applications. All Atmel AVR XMEGA devices are supported with a full suite of program and system development tools, including: C compilers, macro assemblers, program debugger/simulators, programmers, and evaluation kits. 5 8135L-AVR-06/12 XMEGA D4 3.1 Block Diagram Figure 3-1. XMEGA D4 block diagram. Digital function Programming, debug, test Analog function Oscillator/Crystal/Clock General Purpose I/O PR[0..1] XTAL/ TOSC1 XTAL2/ TOSC2 Oscillator Circuits/ Clock Generation PORT R (2) Real Time Counter Watchdog Oscillator DATA BUS Watchdog Timer ACA Event System Controller PA[0..7] Oscillator Control Sleep Controller Power Supervision POR/BOD & RESET PORT A (8) ADCA SRAM GND BUS Matrix AREFA Interrupt Controller VCC/10 VCC Prog/Debug Controller PDI RESET/ PDI_CLK PDI_DATA Int. Refs. Tempref CPU CRC OCD AREFB NVM Controller PB[0..3] PORT B (4) Flash EEPROM DATA BUS PORT D (8) TCE0 TWIE SPID TCD0 USARTD0 SPIC PORT C (8) TWIC TCC0:1 USARTC0 IRCOM EVENT ROUTING NETWORK To Clock Generator PORT E (4) TOSC1 TOSC2 PC[0..7] PD[0..7] PE[0..3] 6 8135L-AVR-06/12 XMEGA D4 4. Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. 4.1 Recommended reading * Atmel AVR XMEGA D manual * XMEGA application notes This device data sheet only contains part specific information with a short description of each peripheral and module. The XMEGA D manual describes the modules and peripherals in depth. The XMEGA application notes contain example code and show applied use of the modules and peripherals. All documentation are available from www.atmel.com/avr. 5. Capacitive touch sensing The Atmel QTouch library provides a simple to use solution to realize touch sensitive interfaces on most Atmel AVR microcontrollers. The patented charge-transfer signal acquisition offers robust sensing and includes fully debounced reporting of touch keys and includes Adjacent Key Suppression(R) (AKS(R)) technology for unambiguous detection of key events. The QTouch library includes support for the QTouch and QMatrix acquisition methods. Touch sensing can be added to any application by linking the appropriate Atmel QTouch library for the AVR microcontroller. This is done by using a simple set of APIs to define the touch channels and sensors, and then calling the touch sensing API's to retrieve the channel information and determine the touch sensor states. The QTouch library is FREE and downloadable from the Atmel website at the following location: www.atmel.com/qtouchlibrary. For implementation details and other information, refer to the QTouch library user guide - also available for download from the Atmel website. 7 8135L-AVR-06/12 XMEGA D4 6. AVR CPU 6.1 Features * 8/16-bit, high-performance Atmel AVR RISC CPU * * * * * * * 6.2 - 137 instructions - Hardware multiplier 32x8-bit registers directly connected to the ALU Stack in RAM Stack pointer accessible in I/O memory space Direct addressing of up to 16MB of program memory and 16MB of data memory True 16/24-bit access to 16/24-bit I/O registers Efficient support for 8-, 16-, and 32-bit arithmetic Configuration change protection of system-critical features Overview All Atmel AVR XMEGA devices use the 8/16-bit AVR CPU. The main function of the CPU is to execute the code and perform all calculations. The CPU is able to access memories, perform calculations, control peripherals, and execute the program in the flash memory. Interrupt handling is described in a separate section, refer to "Interrupts and Programmable Multilevel Interrupt Controller" on page 28. 6.3 Architectural Overview In order to maximize performance and parallelism, the AVR CPU uses a Harvard architecture with separate memories and buses for program and data. Instructions in the program memory are executed with single-level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This enables instructions to be executed on every clock cycle. For details of all AVR instructions, refer to http://www.atmel.com/avr. Figure 6-1. Block diagram of the AVR CPU architecture. 8 8135L-AVR-06/12 XMEGA D4 The arithmetic logic unit (ALU) supports arithmetic and logic operations between registers or between a constant and a register. Single-register operations can also be executed in the ALU. After an arithmetic operation, the status register is updated to reflect information about the result of the operation. The ALU is directly connected to the fast-access register file. The 32 x 8-bit general purpose working registers all have single clock cycle access time allowing single-cycle arithmetic logic unit (ALU) operation between registers or between a register and an immediate. Six of the 32 registers can be used as three 16-bit address pointers for program and data space addressing, enabling efficient address calculations. The memory spaces are linear. The data memory space and the program memory space are two different memory spaces. The data memory space is divided into I/O registers, SRAM, and external RAM. In addition, the EEPROM can be memory mapped in the data memory. All I/O status and control registers reside in the lowest 4KB addresses of the data memory. This is referred to as the I/O memory space. The lowest 64 addresses can be accessed directly, or as the data space locations from 0x00 to 0x3F. The rest is the extended I/O memory space, ranging from 0x0040 to 0x0FFF. I/O registers here must be accessed as data space locations using load (LD/LDS/LDD) and store (ST/STS/STD) instructions. The SRAM holds data. Code execution from SRAM is not supported. It can easily be accessed through the five different addressing modes supported in the AVR architecture. The first SRAM address is 0x2000. Data addresses 0x1000 to 0x1FFF are reserved for memory mapping of EEPROM. The program memory is divided in two sections, the application program section and the boot program section. Both sections have dedicated lock bits for write and read/write protection. The SPM instruction that is used for self-programming of the application flash memory must reside in the boot program section. The application section contains an application table section with separate lock bits for write and read/write protection. The application table section can be used for safe storing of nonvolatile data in the program memory. 6.4 ALU - Arithmetic Logic Unit The arithmetic logic unit (ALU) supports arithmetic and logic operations between registers or between a constant and a register. Single-register operations can also be executed. The ALU operates in direct connection with all 32 general purpose registers. In a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed and the result is stored in the register file. After an arithmetic or logic operation, the status register is updated to reflect information about the result of the operation. ALU operations are divided into three main categories - arithmetic, logical, and bit functions. Both 8- and 16-bit arithmetic is supported, and the instruction set allows for efficient implementation of 32-bit aritmetic. The hardware multiplier supports signed and unsigned multiplication and fractional format. 6.4.1 Hardware Multiplier The multiplier is capable of multiplying two 8-bit numbers into a 16-bit result. The hardware multiplier supports different variations of signed and unsigned integer and fractional numbers: * Multiplication of unsigned integers 9 8135L-AVR-06/12 XMEGA D4 * Multiplication of signed integers * Multiplication of a signed integer with an unsigned integer * Multiplication of unsigned fractional numbers * Multiplication of signed fractional numbers * Multiplication of a signed fractional number with an unsigned one A multiplication takes two CPU clock cycles. 6.5 Program Flow After reset, the CPU starts to execute instructions from the lowest address in the flash programmemory `0.' The program counter (PC) addresses the next instruction to be fetched. Program flow is provided by conditional and unconditional jump and call instructions capable of addressing the whole address space directly. Most AVR instructions use a 16-bit word format, while a limited number use a 32-bit format. During interrupts and subroutine calls, the return address PC is stored on the stack. The stack is allocated in the general data SRAM, and consequently the stack size is only limited by the total SRAM size and the usage of the SRAM. After reset, the stack pointer (SP) points to the highest address in the internal SRAM. The SP is read/write accessible in the I/O memory space, enabling easy implementation of multiple stacks or stack areas. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR CPU. 6.6 Status Register The status register (SREG) contains information about the result of the most recently executed arithmetic or logic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the status register is updated after all ALU operations, as specified in the instruction set reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The status register is not automatically stored when entering an interrupt routine nor restored when returning from an interrupt. This must be handled by software. The status register is accessible in the I/O memory space. 6.7 Stack and Stack Pointer The stack is used for storing return addresses after interrupts and subroutine calls. It can also be used for storing temporary data. The stack pointer (SP) register always points to the top of the stack. It is implemented as two 8-bit registers that are accessible in the I/O memory space. Data are pushed and popped from the stack using the PUSH and POP instructions. The stack grows from a higher memory location to a lower memory location. This implies that pushing data onto the stack decreases the SP, and popping data off the stack increases the SP. The SP is automatically loaded after reset, and the initial value is the highest address of the internal SRAM. If the SP is changed, it must be set to point above address 0x2000, and it must be defined before any subroutine calls are executed or before interrupts are enabled. During interrupts or subroutine calls, the return address is automatically pushed on the stack. The return address can be two or three bytes, depending on program memory size of the device. For devices with 128KB or less of program memory, the return address is two bytes, and hence the stack pointer is decremented/incremented by two. For devices with more than 128KB of program memory, the return address is three bytes, and hence the SP is decremented/incremented 10 8135L-AVR-06/12 XMEGA D4 by three. The return address is popped off the stack when returning from interrupts using the RETI instruction, and from subroutine calls using the RET instruction. The SP is decremented by one when data are pushed on the stack with the PUSH instruction, and incremented by one when data is popped off the stack using the POP instruction. To prevent corruption when updating the stack pointer from software, a write to SPL will automatically disable interrupts for up to four instructions or until the next I/O memory write. After reset the stack pointer is initialized to the highest address of the SRAM. See Figure 7-2 on page 15. 6.8 Register File The register file consists of 32 x 8-bit general purpose working registers with single clock cycle access time. The register file supports the following input/output schemes: * One 8-bit output operand and one 8-bit result input * Two 8-bit output operands and one 8-bit result input * Two 8-bit output operands and one 16-bit result input * One 16-bit output operand and one 16-bit result input Six of the 32 registers can be used as three 16-bit address register pointers for data space addressing, enabling efficient address calculations. One of these address pointers can also be used as an address pointer for lookup tables in flash program memory. 11 8135L-AVR-06/12 XMEGA D4 7. Memories 7.1 Features * Flash program memory - One linear address space - In-system programmable - Self-programming and boot loader support - Application section for application code - Application table section for application code or data storage - Boot section for application code or boot loader code - Separate read/write protection lock bits for all sections - Built in fast CRC check of a selectable flash program memory section * Data memory - One linear address space - Single-cycle access from CPU - SRAM - EEPROM Byte and page accessible Optional memory mapping for direct load and store - I/O memory Configuration and status registers for all peripherals and modules 16 bit-accessible general purpose registers for global variables or flags * Production signature row memory for factory programmed data - ID for each microcontroller device type - Serial number for each device - Calibration bytes for factory calibrated peripherals * User signature row - One flash page in size - Can be read and written from software - Content is kept after chip erase 7.2 Overview The Atmel AVR architecture has two main memory spaces, the program memory and the data memory. Executable code can reside only in the program memory, while data can be stored in the program memory and the data memory. The data memory includes the internal SRAM, and EEPROM for nonvolatile data storage. All memory spaces are linear and require no memory bank switching. Nonvolatile memory (NVM) spaces can be locked for further write and read/write operations. This prevents unrestricted access to the application software. A separate memory section contains the fuse bytes. These are used for configuring important system functions, and can only be written by an external programmer. The available memory size configurations are shown in "Ordering Information" on page 2 In addition, each device has a Flash memory signature row for calibration data, device identification, serial number etc. 12 8135L-AVR-06/12 XMEGA D4 7.3 Flash Program Memory The Atmel AVR XMEGA devices contain on-chip, in-system reprogrammable flash memory for program storage. The flash memory can be accessed for read and write from an external programmer through the PDI or from application software running in the device. All AVR CPU instructions are 16 or 32 bits wide, and each flash location is 16 bits wide. The flash memory is organized in two main sections, the application section and the boot loader section. The sizes of the different sections are fixed, but device-dependent. These two sections have separate lock bits, and can have different levels of protection. The store program memory (SPM) instruction, which is used to write to the flash from the application software, will only operate when executed from the boot loader section. The application section contains an application table section with separate lock settings. This enables safe storage of nonvolatile data in the program memory. Figure 7-1. Flash program memory (Hexadecimal address). Word address 0 Application Section (128K/64K/32K/16K) ... EFFF / 77FF / 37FF / 17FF EFFF / F000 / 7800 / 3800 / 1800 F000 / FFFF / 7FFF / 3FFF / 1FFF FFFF / 10000 / 8000 / 4000 / 2000 10000 / 10FFF / 87FF / 47FF / 27FF 10FFF / Application Table Section (4K/4K/4K/4K) Boot Section (8K/4K/4K/4K) 7.3.1 Application Section The Application section is the section of the flash that is used for storing the executable application code. The protection level for the application section can be selected by the boot lock bits for this section. The application section can not store any boot loader code since the SPM instruction cannot be executed from the application section. 7.3.2 Application Table Section The application table section is a part of the application section of the flash memory that can be used for storing data. The size is identical to the boot loader section. The protection level for the application table section can be selected by the boot lock bits for this section. The possibilities for different protection levels on the application section and the application table section enable safe parameter storage in the program memory. If this section is not used for data, application code can reside here. 7.3.3 Boot Loader Section While the application section is used for storing the application code, the boot loader software must be located in the boot loader section because the SPM instruction can only initiate programming when executing from this section. The SPM instruction can access the entire flash, including the boot loader section itself. The protection level for the boot loader section can be selected by the boot loader lock bits. If this section is not used for boot loader software, application code can be stored here. 13 8135L-AVR-06/12 XMEGA D4 7.3.4 Production Signature Row The production signature row is a separate memory section for factory programmed data. It contains calibration data for functions such as oscillators and analog modules. Some of the calibration values will be automatically loaded to the corresponding module or peripheral unit during reset. Other values must be loaded from the signature row and written to the corresponding peripheral registers from software. For details on calibration conditions, refer to "Electrical Characteristics" on page 64. The production signature row also contains an ID that identifies each microcontroller device type and a serial number for each manufactured device. The serial number consists of the production lot number, wafer number, and wafer coordinates for the device. The device ID for the available devices is shown in Table 7-1. The production signature row cannot be written or erased, but it can be read from application software and external programmers. Table 7-1. Device ID bytes for Atmel AVR XMEGA D4 devices. Device 7.3.5 7.4 Device ID bytes Byte 2 Byte 1 Byte 0 ATxmega16D4 42 94 1E ATxmega32D4 42 95 1E ATxmega64D4 47 96 1E ATxmega128D4 47 97 1E User Signature Row The user signature row is a separate memory section that is fully accessible (read and write) from application software and external programmers. It is one flash page in size, and is meant for static user parameter storage, such as calibration data, custom serial number, identification numbers, random number seeds, etc. This section is not erased by chip erase commands that erase the flash, and requires a dedicated erase command. This ensures parameter storage during multiple program/erase operations and on-chip debug sessions. Fuses and Lock bits The fuses are used to configure important system functions, and can only be written from an external programmer. The application software can read the fuses. The fuses are used to configure reset sources such as brownout detector and watchdog and startup configuration. The lock bits are used to set protection levels for the different flash sections (that is, if read and/or write access should be blocked). Lock bits can be written by external programmers and application software, but only to stricter protection levels. Chip erase is the only way to erase the lock bits. To ensure that flash contents are protected even during chip erase, the lock bits are erased after the rest of the flash memory has been erased. An unprogrammed fuse or lock bit will have the value one, while a programmed fuse or lock bit will have the value zero. Both fuses and lock bits are reprogrammable like the flash program memory. 14 8135L-AVR-06/12 XMEGA D4 7.5 Data Memory The data memory contains the I/O memory, internal SRAM, optionally memory mapped EEPROM, and external memory if available. The data memory is organized as one continuous memory section, see Figure 7-2. To simplify development, I/O Memory, EEPROM and SRAM will always have the same start addresses for all Atmel AVR XMEGA devices. Figure 7-2. Data memory map (Hexadecimal address). Byte address 0 FFF ATxmega64D4 I/O Registers (4K) 1000 EEPROM (2K) 17FF Byte address 0 FFF 1000 13FF RESERVED 2000 2FFF Internal SRAM (4K) ATxmega32D4 I/O Registers (4K) EEPROM (1K) Byte address 0 FFF 1000 13FF RESERVED 2000 2FFF Internal SRAM (4K) ATxmega16D4 I/O Registers (4K) EEPROM (1K) RESERVED 2000 27FF Byte address 0 FFF 1000 17FF Internal SRAM (2K) ATxmega128D4 I/O Registers (4K) EEPROM (2K) RESERVED 2000 3FFF 7.6 Internal SRAM (8K) EEPROM All devices have EEPROM for nonvolatile data storage. It is either addressable in a separate data space (default) or memory mapped and accessed in normal data space. The EEPROM supports both byte and page access. Memory mapped EEPROM allows highly efficient EEPROM reading and EEPROM buffer loading. When doing this, EEPROM is accessible using load and store instructions. Memory mapped EEPROM will always start at hexadecimal address 0x1000. 7.7 I/O Memory The status and configuration registers for peripherals and modules, including the CPU, are addressable through I/O memory locations. All I/O locations can be accessed by the load (LD/LDS/LDD) and store (ST/STS/STD) instructions, which are used to transfer data between the 32 registers in the register file and the I/O memory. The IN and OUT instructions can address I/O memory locations in the range of 0x00 to 0x3F directly. In the address range 0x00 0x1F, single-cycle instructions for manipulation and checking of individual bits are available. 15 8135L-AVR-06/12 XMEGA D4 The I/O memory address for all peripherals and modules in XMEGA D4 is shown in the "Peripheral Module Address Map" on page 56. 7.7.1 7.8 General Purpose I/O Registers The lowest 16 I/O memory addresses are reserved as general purpose I/O registers. These registers can be used for storing global variables and flags, as they are directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions. Data Memory and Bus Arbitration Since the data memory is organized as four separate sets of memories, the bus masters (CPU, etc.) can access different memory sections at the same time. 7.9 Memory Timing Read and write access to the I/O memory takes one CPU clock cycle. A write to SRAM takes one cycle, and a read from SRAM takes two cycles. EEPROM page load (write) takes one cycle, and three cycles are required for read. For burst read, new data are available every second cycle. Refer to the instruction summary for more details on instructions and instruction timing. 7.10 Device ID and Revision Each device has a three-byte device ID. This ID identifies Atmel as the manufacturer of the device and the device type. A separate register contains the revision number of the device. 7.11 I/O Memory Protection Some features in the device are regarded as critical for safety in some applications. Due to this, it is possible to lock the I/O register related to the clock system, the event system, and the advanced waveform extensions. As long as the lock is enabled, all related I/O registers are locked and they can not be written from the application software. The lock registers themselves are protected by the configuration change protection mechanism. 7.12 Flash and EEPROM Page Size The flash program memory and EEPROM data memory are organized in pages. The pages are word accessible for the flash and byte accessible for the EEPROM. Table 7-2 shows the Flash Program Memory organization and Program Counter (PC) size. Flash write and erase operations are performed on one page at a time, while reading the Flash is done one byte at a time. For Flash access the Z-pointer (Z[m:n]) is used for addressing. The most significant bits in the address (FPAGE) give the page number and the least significant address bits (FWORD) give the word in the page. Table 7-2. Devices PC size Number of words and pages in the flash. Flash size Page size FWORD FPAGE Application Boot [bits] [bytes] [words] Size No of pages Size No of pages ATxmega16D4 14 16K + 4K 128 Z[6:0] Z[13:7] 16K 64 4K 16 ATxmega32D4 15 32K + 4K 128 Z[6:0] Z[14:7] 32K 128 4K 16 ATxmega64D4 16 64K + 4K 128 Z[6:0] Z[15:7] 64K 256 4K 16 ATxmega128D4 17 128K + 8K 128 Z[8:0] Z[16:7] 128K 512 8K 32 16 8135L-AVR-06/12 XMEGA D4 Table 7-3 shows EEPROM memory organization. EEEPROM write and erase operations can be performed one page or one byte at a time, while reading the EEPROM is done one byte at a time. For EEPROM access the NVM address register (ADDR[m:n]) is used for addressing. The most significant bits in the address (E2PAGE) give the page number and the least significant address bits (E2BYTE) give the byte in the page. Table 7-3. Devices Number of bytes and pages in the EEPROM. EEPROM Page size size [bytes] E2BYTE E2PAGE No of pages ATxmega16D4 1K ATxmega32D4 1K 32 ADDR[4:0] ADDR[10:5] 32 32 ADDR[4:0] ADDR[10:5] 32 ATxmega64D4 ATxmega128D4 2K 32 ADDR[4:0] ADDR[10:5] 64 2K 32 ADDR[4:0] ADDR[10:5] 64 17 8135L-AVR-06/12 XMEGA D4 8. Event System 8.1 Features * System for direct peripheral-to-peripheral communication and signaling * Peripherals can directly send, receive, and react to peripheral events * * * * 8.2 - CPU independent operation - 100% predictable signal timing - Short and guaranteed response time Four event channels for up to four different and parallel signal routing configurations Events can be sent and/or used by most peripherals, clock system, and software Additional functions include - Quadrature decoders - Digital filtering of I/O pin state Works in active mode and idle sleep mode Overview The event system enables direct peripheral-to-peripheral communication and signaling. It allows a change in one peripheral's state to automatically trigger actions in other peripherals. It is designed to provide a predictable system for short and predictable response times between peripherals. It allows for autonomous peripheral control and interaction without the use of interrupts or CPU resources, and is thus a powerful tool for reducing the complexity, size and execution time of application code. It also allows for synchronized timing of actions in several peripheral modules. A change in a peripheral's state is referred to as an event, and usually corresponds to the peripheral's interrupt conditions. Events can be directly passed to other peripherals using a dedicated routing network called the event routing network. How events are routed and used by the peripherals is configured in software. Figure 8-1 on page 19 shows a basic diagram of all connected peripherals. The event system can directly connect together analog to digital converter, analog comparators, I/O port pins, the real-time counter, timer/counters, and IR communication module (IRCOM). Events can also be generated from software and the peripheral clock. 18 8135L-AVR-06/12 XMEGA D4 Figure 8-1. Event system overview and connected peripherals. CPU / Software Event Routing Network ADC Event System Controller clkPER Prescaler Real Time Counter AC Timer / Counters Port pins IRCOM The event routing network consists of four software-configurable multiplexers that control how events are routed and used. These are called event channels, and allow for up to four parallel event routing configurations. The maximum routing latency is two peripheral clock cycles. The event system works in both active mode and idle sleep mode. 19 8135L-AVR-06/12 XMEGA D4 9. System Clock and Clock options 9.1 Features * Fast start-up time * Safe run-time clock switching * Internal oscillators: * * * * * * 9.2 - 32MHz run-time calibrated and tuneable oscillator - 2MHz run-time calibrated oscillator - 32.768kHz calibrated oscillator - 32kHz ultra low power (ULP) oscillator with 1kHz output External clock options - 0.4MHz - 16MHz crystal oscillator - 32.768kHz crystal oscillator - External clock PLL with 20MHz - 128MHz output frequency - Internal and external clock options and 1x to 31x multiplication - Lock detector Clock prescalers with 1x to 2048x division Fast peripheral clocks running at two and four times the CPU clock Automatic run-time calibration of internal oscillators External oscillator and PLL lock failure detection with optional non-maskable interrupt Overview Atmel AVR XMEGA D4 devices have a flexible clock system supporting a large number of clock sources. It incorporates both accurate internal oscillators and external crystal oscillator and resonator support. A high-frequency phase locked loop (PLL) and clock prescalers can be used to generate a wide range of clock frequencies. A calibration feature (DFLL) is available, and can be used for automatic run-time calibration of the internal oscillators to remove frequency drift over voltage and temperature. An oscillator failure monitor can be enabled to issue a non-maskable interrupt and switch to the internal oscillator if the external oscillator or PLL fails. When a reset occurs, all clock sources except the 32kHz ultra low power oscillator are disabled. After reset, the device will always start up running from the 2MHz internal oscillator. During normal operation, the system clock source and prescalers can be changed from software at any time. Figure 9-1 on page 21 presents the principal clock system in the XMEGA D4 family of devices. Not all of the clocks need to be active at a given time. The clocks for the CPU and peripherals can be stopped using sleep modes and power reduction registers, as described in "Power Management and Sleep Modes" on page 23. 20 8135L-AVR-06/12 XMEGA D4 Figure 9-1. The clock system, clock sources and clock distribution. Real Time Counter Peripherals RAM AVR CPU Non-Volatile Memory clkPER clkCPU clkPER2 clkPER4 Brown-out Detector System Clock Prescalers Watchdog Timer clkSYS clkRTC System Clock Multiplexer (SCLKSEL) RTCSRC DIV32 DIV32 DIV32 PLL PLLSRC DIV4 XOSCSEL 32 kHz Int. ULP 32.768 kHz Int. OSC 32.768 kHz TOSC 32 MHz Int. Osc 2 MHz Int. Osc XTAL2 XTAL1 TOSC2 TOSC1 9.3 0.4 - 16 MHz XTAL Clock Sources The clock sources are divided in two main groups: internal oscillators and external clock sources. Most of the clock sources can be directly enabled and disabled from software, while others are automatically enabled or disabled, depending on peripheral settings. After reset, the device starts up running from the 2MHz internal oscillator. The other clock sources, DFLLs and PLL, are turned off by default. The internal oscillators do not require any external components to run. For details on characteristics and accuracy of the internal oscillators, refer to the device datasheet. 21 8135L-AVR-06/12 XMEGA D4 9.3.1 32kHz Ultra Low Power Internal Oscillator This oscillator provides an approximate 32kHz clock. The 32kHz ultra low power (ULP) internal oscillator is a very low power clock source, and it is not designed for high accuracy. The oscillator employs a built-in prescaler that provides a 1kHz output. The oscillator is automatically enabled/disabled when it is used as clock source for any part of the device. This oscillator can be selected as the clock source for the RTC. 9.3.2 32.768kHz Calibrated Internal Oscillator This oscillator provides an approximate 32.768kHz clock. It is calibrated during production to provide a default frequency close to its nominal frequency. The calibration register can also be written from software for run-time calibration of the oscillator frequency. The oscillator employs a built-in prescaler, which provides both a 32.768kHz output and a 1.024kHz output. 9.3.3 32.768kHz Crystal Oscillator A 32.768kHz crystal oscillator can be connected between the TOSC1 and TOSC2 pins and enables a dedicated low frequency oscillator input circuit. A low power mode with reduced voltage swing on TOSC2 is available. This oscillator can be used as a clock source for the system clock and RTC, and as the DFLL reference clock. 9.3.4 0.4 - 16MHz Crystal Oscillator This oscillator can operate in four different modes optimized for different frequency ranges, all within 0.4 - 16MHz. 9.3.5 2MHz Run-time Calibrated Internal Oscillator The 2MHz run-time calibrated internal oscillator is the default system clock source after reset. It is calibrated during production to provide a default frequency close to its nominal frequency. A DFLL can be enabled for automatic run-time calibration of the oscillator to compensate for temperature and voltage drift and optimize the oscillator accuracy. 9.3.6 32MHz Run-time Calibrated Internal Oscillator The 32MHz run-time calibrated internal oscillator is a high-frequency oscillator. It is calibrated during production to provide a default frequency close to its nominal frequency. A digital frequency looked loop (DFLL) can be enabled for automatic run-time calibration of the oscillator to compensate for temperature and voltage drift and optimize the oscillator accuracy. This oscillator can also be adjusted and calibrated to any frequency between 30MHz and 55MHz. 9.3.7 External Clock Sources The XTAL1 and XTAL2 pins can be used to drive an external oscillator, either a quartz crystal or a ceramic resonator. XTAL1 can be used as input for an external clock signal. The TOSC1 and TOSC2 pins is dedicated to driving a 32.768kHz crystal oscillator. 9.3.8 PLL with 1x-31x Multiplication Factor The built-in phase locked loop (PLL) can be used to generate a high-frequency system clock. The PLL has a user-selectable multiplication factor of from 1 to 31. In combination with the prescalers, this gives a wide range of output frequencies from all clock sources. 22 8135L-AVR-06/12 XMEGA D4 10. Power Management and Sleep Modes 10.1 Features * Power management for adjusting power consumption and functions * Five sleep modes - Idle - Power down - Power save - Standby - Extended standby * Power reduction register to disable clock and turn off unused peripherals in active and idle modes 10.2 Overview Various sleep modes and clock gating are provided in order to tailor power consumption to application requirements. This enables the Atmel AVR XMEGA microcontroller to stop unused modules to save power. All sleep modes are available and can be entered from active mode. In active mode, the CPU is executing application code. When the device enters sleep mode, program execution is stopped and interrupts or a reset is used to wake the device again. The application code decides which sleep mode to enter and when. Interrupts from enabled peripherals and all enabled reset sources can restore the microcontroller from sleep to active mode. In addition, power reduction registers provide a method to stop the clock to individual peripherals from software. When this is done, the current state of the peripheral is frozen, and there is no power consumption from that peripheral. This reduces the power consumption in active mode and idle sleep modes and enables much more fine-tuned power management than sleep modes alone. 10.3 Sleep Modes Sleep modes are used to shut down modules and clock domains in the microcontroller in order to save power. XMEGA microcontrollers have five different sleep modes tuned to match the typical functional stages during application execution. A dedicated sleep instruction (SLEEP) is available to enter sleep mode. Interrupts are used to wake the device from sleep, and the available interrupt wake-up sources are dependent on the configured sleep mode. When an enabled interrupt occurs, the device will wake up and execute the interrupt service routine before continuing normal program execution from the first instruction after the SLEEP instruction. If other, higher priority interrupts are pending when the wake-up occurs, their interrupt service routines will be executed according to their priority before the interrupt service routine for the wake-up interrupt is executed. After wake-up, the CPU is halted for four cycles before execution starts. The content of the register file, SRAM and registers are kept during sleep. If a reset occurs during sleep, the device will reset, start up, and execute from the reset vector. 10.3.1 Idle Mode In idle mode the CPU and nonvolatile memory are stopped (note that any ongoing programming will be completed), but all peripherals, including the interrupt controller, and event system are kept running. Any enabled interrupt will wake the device. 23 8135L-AVR-06/12 XMEGA D4 10.3.2 Power-down Mode In power-down mode, all clocks, including the real-time counter clock source, are stopped. This allows operation only of asynchronous modules that do not require a running clock. The only interrupts that can wake up the MCU are the two-wire interface address match interrupt, and asynchronous port interrupts. 10.3.3 Power-save Mode Power-save mode is identical to power down, with one exception. If the real-time counter (RTC) is enabled, it will keep running during sleep, and the device can also wake up from either an RTC overflow or compare match interrupt. 10.3.4 Standby Mode Standby mode is identical to power down, with the exception that the enabled system clock sources are kept running while the CPU, peripheral, and RTC clocks are stopped. This reduces the wake-up time. 10.3.5 Extended Standby Mode Extended standby mode is identical to power-save mode, with the exception that the enabled system clock sources are kept running while the CPU and peripheral clocks are stopped. This reduces the wake-up time. 24 8135L-AVR-06/12 XMEGA D4 11. System Control and Reset 11.1 Features * Reset the microcontroller and set it to initial state when a reset source goes active * Multiple reset sources that cover different situations - Power-on reset - External reset - Watchdog reset - Brownout reset - PDI reset - Software reset * Asynchronous operation - No running system clock in the device is required for reset * Reset status register for reading the reset source from the application code 11.2 Overview The reset system issues a microcontroller reset and sets the device to its initial state. This is for situations where operation should not start or continue, such as when the microcontroller operates below its power supply rating. If a reset source goes active, the device enters and is kept in reset until all reset sources have released their reset. The I/O pins are immediately tri-stated. The program counter is set to the reset vector location, and all I/O registers are set to their initial values. The SRAM content is kept. However, if the device accesses the SRAM when a reset occurs, the content of the accessed location can not be guaranteed. After reset is released from all reset sources, the default oscillator is started and calibrated before the device starts running from the reset vector address. By default, this is the lowest program memory address, 0, but it is possible to move the reset vector to the lowest address in the boot section. The reset functionality is asynchronous, and so no running system clock is required to reset the device. The software reset feature makes it possible to issue a controlled system reset from the user software. The reset status register has individual status flags for each reset source. It is cleared at poweron reset, and shows which sources have issued a reset since the last power-on. 11.3 Reset Sequence A reset request from any reset source will immediately reset the device and keep it in reset as long as the request is active. When all reset requests are released, the device will go through three stages before the device starts running again: *Reset counter delay *Oscillator startup *Oscillator calibration If another reset requests occurs during this process, the reset sequence will start over again. 25 8135L-AVR-06/12 XMEGA D4 11.4 11.4.1 Reset Sources Power-on Reset A power-on reset (POR) is generated by an on-chip detection circuit. The POR is activated when the V CC rises and reaches the POR threshold voltage (VPOT ), and this will start the reset sequence. The POR is also activated to power down the device properly when the VCC falls and drops below the VPOT level. The VPOT level is higher for falling VCC than for rising VCC. Consult the datasheet for POR characteristics data. 11.4.2 Brownout Detection The on-chip brownout detection (BOD) circuit monitors the VCC level during operation by comparing it to a fixed, programmable level that is selected by the BODLEVEL fuses. If disabled, BOD is forced on at the lowest level during chip erase and when the PDI is enabled. 11.4.3 External Reset The external reset circuit is connected to the external RESET pin. The external reset will trigger when the RESET pin is driven below the RESET pin threshold voltage, VRST, for longer than the minimum pulse period, tEXT. The reset will be held as long as the pin is kept low. The RESET pin includes an internal pull-up resistor. 11.4.4 Watchdog Reset The watchdog timer (WDT) is a system function for monitoring correct program operation. If the WDT is not reset from the software within a programmable timeout period, a watchdog reset will be given. The watchdog reset is active for one to two clock cycles of the 2MHz internal oscillator. For more details see "WDT - Watchdog Timer" on page 27. 11.4.5 Software Reset The software reset makes it possible to issue a system reset from software by writing to the software reset bit in the reset control register.The reset will be issued within two CPU clock cycles after writing the bit. It is not possible to execute any instruction from when a software reset is requested until it is issued. 11.4.6 Program and Debug Interface Reset The program and debug interface reset contains a separate reset source that is used to reset the device during external programming and debugging. This reset source is accessible only from external debuggers and programmers. 26 8135L-AVR-06/12 XMEGA D4 12. WDT - Watchdog Timer 12.1 Features * * * * * Issues a device reset if the timer is not reset before its timeout period Asynchronous operation from dedicated oscillator 1kHz output of the 32kHz ultra low power oscillator 11 selectable timeout periods, from 8ms to 8s Two operation modes: - Normal mode - Window mode * Configuration lock to prevent unwanted changes 12.2 Overview The watchdog timer (WDT) is a system function for monitoring correct program operation. It makes it possible to recover from error situations such as runaway or deadlocked code. The WDT is a timer, configured to a predefined timeout period, and is constantly running when enabled. If the WDT is not reset within the timeout period, it will issue a microcontroller reset. The WDT is reset by executing the WDR (watchdog timer reset) instruction from the application code. The window mode makes it possible to define a time slot or window inside the total timeout period during which WDT must be reset. If the WDT is reset outside this window, either too early or too late, a system reset will be issued. Compared to the normal mode, this can also catch situations where a code error causes constant WDR execution. The WDT will run in active mode and all sleep modes, if enabled. It is asynchronous, runs from a CPU-independent clock source, and will continue to operate to issue a system reset even if the main clocks fail. The configuration change protection mechanism ensures that the WDT settings cannot be changed by accident. For increased safety, a fuse for locking the WDT settings is also available. 27 8135L-AVR-06/12 XMEGA D4 13. Interrupts and Programmable Multilevel Interrupt Controller 13.1 Features * Short and predictable interrupt response time * Separate interrupt configuration and vector address for each interrupt * Programmable multilevel interrupt controller - Interrupt prioritizing according to level and vector address - Three selectable interrupt levels for all interrupts: low, medium and high - Selectable, round-robin priority scheme within low-level interrupts - Non-maskable interrupts for critical functions * Interrupt vectors optionally placed in the application section or the boot loader section 13.2 Overview Interrupts signal a change of state in peripherals, and this can be used to alter program execution. Peripherals can have one or more interrupts, and all are individually enabled and configured. When an interrupt is enabled and configured, it will generate an interrupt request when the interrupt condition is present. The programmable multilevel interrupt controller (PMIC) controls the handling and prioritizing of interrupt requests. When an interrupt request is acknowledged by the PMIC, the program counter is set to point to the interrupt vector, and the interrupt handler can be executed. All peripherals can select between three different priority levels for their interrupts: low, medium, and high. Interrupts are prioritized according to their level and their interrupt vector address. Medium-level interrupts will interrupt low-level interrupt handlers. High-level interrupts will interrupt both medium- and low-level interrupt handlers. Within each level, the interrupt priority is decided from the interrupt vector address, where the lowest interrupt vector address has the highest interrupt priority. Low-level interrupts have an optional round-robin scheduling scheme to ensure that all interrupts are serviced within a certain amount of time. Non-maskable interrupts (NMI) are also supported, and can be used for system critical functions. 13.3 Interrupt vectors The interrupt vector is the sum of the peripheral's base interrupt address and the offset address for specific interrupts in each peripheral. The base addresses for the Atmel AVR XMEGA D4 devices are shown in Table 13-1. Offset addresses for each interrupt available in the peripheral are described for each peripheral in the XMEGA D manual. For peripherals or modules that have only one interrupt, the interrupt vector is shown in Table 13-1. The program address is the word address. Table 13-1. Reset and interrupt vectors. Program address (base address) Source 0x000 RESET 0x002 OSCF_INT_vect Crystal oscillator failure interrupt vector (NMI) 0x004 PORTC_INT_base Port C interrupt base 0x008 PORTR_INT_base Port R interrupt base 0x014 RTC_INT_base Real time counter interrupt base Interrupt description 28 8135L-AVR-06/12 XMEGA D4 Table 13-1. Reset and interrupt vectors. (Continued) Program address (base address) Source Interrupt description 0x018 TWIC_INT_base Two-Wire Interface on Port C interrupt base 0x01C TCC0_INT_base Timer/Counter 0 on port C interrupt base 0x028 TCC1_INT_base Timer/Counter 1 on port C interrupt base 0x030 SPIC_INT_vect SPI on port C interrupt vector 0x032 USARTC0_INT_base USART 0 on port C interrupt base 0x040 NVM_INT_base Non-Volatile Memory interrupt base 0x044 PORTB_INT_base Port B interrupt base 0x056 PORTE_INT_base Port E interrupt base 0x05A TWIE_INT_base Two-Wire Interface on Port E interrupt base 0x05E TCE0_INT_base Timer/Counter 0 on port E interrupt base 0x080 PORTD_INT_base Port D interrupt base 0x084 PORTA_INT_base Port A interrupt base 0x088 ACA_INT_base Analog Comparator on Port A interrupt base 0x08E ADCA_INT_base Analog to Digital Converter on Port A interrupt base 0x09A TCD0_INT_base Timer/Counter 0 on port D interrupt base 0x0AE SPID_INT_vector SPI on port D interrupt vector 0x0B0 USARTD0_INT_base USART 0 on port D interrupt base 29 8135L-AVR-06/12 XMEGA D4 14. I/O Ports 14.1 Features * 34 general purpose input and output pins with individual configuration * Output driver with configurable driver and pull settings: * * * * * * * * * * 14.2 - Totem-pole - Wired-AND - Wired-OR - Bus-keeper - Inverted I/O Input with synchronous and/or asynchronous sensing with interrupts and events - Sense both edges - Sense rising edges - Sense falling edges - Sense low level Optional pull-up and pull-down resistor on input and Wired-OR/AND configurations Optional slew rate control Asynchronous pin change sensing that can wake the device from all sleep modes Two port interrupts with pin masking per I/O port Efficient and safe access to port pins - Hardware read-modify-write through dedicated toggle/clear/set registers - Configuration of multiple pins in a single operation - Mapping of port registers into bit-accessible I/O memory space Peripheral clocks output on port pin Real-time counter clock output to port pin Event channels can be output on port pin Remapping of digital peripheral pin functions - Selectable USART, SPI, and timer/counter input/output pin locations Overview One port consists of up to eight port pins: pin 0 to 7. Each port pin can be configured as input or output with configurable driver and pull settings. They also implement synchronous and asynchronous input sensing with interrupts and events for selectable pin change conditions. Asynchronous pin-change sensing means that a pin change can wake the device from all sleep modes, included the modes where no clocks are running. All functions are individual and configurable per pin, but several pins can be configured in a single operation. The pins have hardware read-modify-write (RMW) functionality for safe and correct change of drive value and/or pull resistor configuration. The direction of one port pin can be changed without unintentionally changing the direction of any other pin. The port pin configuration also controls input and output selection of other device functions. It is possible to have both the peripheral clock and the real-time clock output to a port pin, and available for external use. The same applies to events from the event system that can be used to synchronize and control external functions. Other digital peripherals, such as USART, SPI, and timer/counters, can be remapped to selectable pin locations in order to optimize pin-out versus application needs. The notation of the ports are PORTA, PORTB, PORTC, PORTD, PORTE, and PORTR. 30 8135L-AVR-06/12 XMEGA D4 14.3 Output Driver All port pins (Pn) have programmable output configuration. The port pins also have configurable slew rate limitation to reduce electromagnetic emission. 14.3.1 Push-pull Figure 14-1. I/O configuration - Totem-pole. DIRn OUTn Pn INn 14.3.2 Pull-down Figure 14-2. I/O configuration - Totem-pole with pull-down (on input). DIRn OUTn Pn INn 14.3.3 Pull-up Figure 14-3. I/O configuration - Totem-pole with pull-up (on input). DIRn OUTn Pn INn 31 8135L-AVR-06/12 XMEGA D4 14.3.4 Bus-keeper The bus-keeper's weak output produces the same logical level as the last output level. It acts as a pull-up if the last level was `1', and pull-down if the last level was `0'. Figure 14-4. I/O configuration - Totem-pole with bus-keeper. DIRn OUTn Pn INn 14.3.5 Others Figure 14-5. Output configuration - Wired-OR with optional pull-down. OUTn Pn INn Figure 14-6. I/O configuration - Wired-AND with optional pull-up. INn Pn OUTn 32 8135L-AVR-06/12 XMEGA D4 14.4 Input sensing Input sensing is synchronous or asynchronous depending on the enabled clock for the ports, and the configuration is shown in Figure 14-7. Figure 14-7. Input sensing system overview. Asynchronous sensing EDGE DETECT Interrupt Control IREQ Synchronous sensing Pn Synchronizer INn D Q D Q INVERTED I/O R EDGE DETECT Event R When a pin is configured with inverted I/O, the pin value is inverted before the input sensing. 14.5 Alternate Port Functions Most port pins have alternate pin functions in addition to being a general purpose I/O pin. When an alternate function is enabled, it might override the normal port pin function or pin value. This happens when other peripherals that require pins are enabled or configured to use pins. If and how a peripheral will override and use pins is described in the section for that peripheral. "Pinout and Pin Functions" on page 51 shows which modules on peripherals that enable alternate functions on a pin, and which alternate functions that are available on a pin. 33 8135L-AVR-06/12 XMEGA D4 15. TC0/1 - 16-bit Timer/Counter Type 0 and 1 15.1 Features * Four 16-bit timer/counters * * * * * * * * * * * * 15.2 - Three timer/counters of type 0 - One timer/counter of type 1 - Split-mode enabling two 8-bit timer/counter from each timer/counter type 0 32-bit timer/counter support by cascading two timer/counters Up to four compare or capture (CC) channels - Four CC channels for timer/counters of type 0 - Two CC channels for timer/counters of type 1 Double buffered timer period setting Double buffered capture or compare channels Waveform generation: - Frequency generation - Single-slope pulse width modulation - Dual-slope pulse width modulation Input capture: - Input capture with noise cancelling - Frequency capture - Pulse width capture - 32-bit input capture Timer overflow and error interrupts/events One compare match or input capture interrupt/event per CC channel Can be used with event system for: - Quadrature decoding - Count and direction control - Capture High-resolution extension - Increases frequency and waveform resolution by 4x (2-bit) or 8x (3-bit) Advanced waveform extension: - Low- and high-side output with programmable dead-time insertion (DTI) Event controlled fault protection for safe disabling of drivers Overview Atmel AVR XMEGA devices have a set of four flexible 16-bit Timer/Counters (TC). Their capabilities include accurate program execution timing, frequency and waveform generation, and input capture with time and frequency measurement of digital signals. Two timer/counters can be cascaded to create a 32-bit timer/counter with optional 32-bit capture. A timer/counter consists of a base counter and a set of compare or capture (CC) channels. The base counter can be used to count clock cycles or events. It has direction control and period setting that can be used for timing. The CC channels can be used together with the base counter to do compare match control, frequency generation, and pulse width waveform modulation, as well as various input capture operations. A timer/counter can be configured for either capture or compare functions, but cannot perform both at the same time. A timer/counter can be clocked and timed from the peripheral clock with optional prescaling or from the event system. The event system can also be used for direction control and capture trigger or to synchronize operations. There are two differences between timer/counter type 0 and type 1. Timer/counter 0 has four CC channels, and timer/counter 1 has two CC channels. All information related to CC channels 3 34 8135L-AVR-06/12 XMEGA D4 and 4 is valid only for timer/counter 0. Only Timer/Counter 0 has the split mode feature that split it into two 8-bit Timer/Counters with four compare channels each. Some timer/counters have extensions to enable more specialized waveform and frequency generation. The advanced waveform extension (AWeX) is intended for motor control and other power control applications. It enables low- and high-side output with dead-time insertion, as well as fault protection for disabling and shutting down external drivers. It can also generate a synchronized bit pattern across the port pins. The advanced waveform extension can be enabled to provide extra and more advanced features for the Timer/Counter. This are only available for Timer/Counter 0. See "AWeX - Advanced Waveform Extension" on page 37 for more details. The high-resolution (hi-res) extension can be used to increase the waveform output resolution by four or eight times by using an internal clock source running up to four times faster than the peripheral clock. See "Hi-Res - High Resolution Extension" on page 38 for more details. Figure 15-1. Overview of a Timer/Counter and closely related peripherals. Timer/Counter Base Counter Timer Period Counter Prescaler Control Logic clkPER Event System clkPER4 Buffer Capture Control Waveform Generation Dead-Time Insertion Pattern Generation Fault Protection PORT Comparator AWeX Hi-Res Compare/Capture Channel D Compare/Capture Channel C Compare/Capture Channel B Compare/Capture Channel A PORTC has one Timer/Counter 0 and one Timer/Counter1. PORTD and PORTE each has one Timer/Conter0. Notation of these are TCC0 (Time/Counter C0), TCC1, TCD0 and TCE0, respectively. 35 8135L-AVR-06/12 XMEGA D4 16. TC2 - Timer/Counter Type 2 16.1 Features * Six eight-bit timer/counters * * * * * 16.2 - Three Low-byte timer/counter - Three High-byte timer/counter Up to eight compare channels in each Timer/Counter 2 - Four compare channels for the low-byte timer/counter - Four compare channels for the high-byte timer/counter Waveform generation - Single slope pulse width modulation Timer underflow interrupts/events One compare match interrupt/event per compare channel for the low-byte timer/counter Can be used with the event system for count control Overview There are three Timer/Counter 2. These are realized when a Timer/Counter 0 is set in split mode. It is then a system of two eight-bit timer/counters, each with four compare channels. This results in eight configurable pulse width modulation (PWM) channels with individually controlled duty cycles, and is intended for applications that require a high number of PWM channels. The two eight-bit timer/counters in this system are referred to as the low-byte timer/counter and high-byte timer/counter, respectively. The difference between them is that only the low-byte timer/counter can be used to generate compare match interrupts and events. The two eight-bit timer/counters have a shared clock source and separate period and compare settings. They can be clocked and timed from the peripheral clock, with optional prescaling, or from the event system. The counters are always counting down. PORTC, PORTD and PORTE each has one Timer/Counter 2. Notation of these are TCC2 (Time/Counter C2), TCD2 and TCE2, respectively. 36 8135L-AVR-06/12 XMEGA D4 17. AWeX - Advanced Waveform Extension 17.1 Features * Waveform output with complementary output from each compare channel * Four dead-time insertion (DTI) units - 8-bit resolution - Separate high and low side dead-time setting - Double buffered dead time - Optionally halts timer during dead-time insertion * Pattern generation unit creating synchronised bit pattern across the port pins - Double buffered pattern generation - Optional distribution of one compare channel output across the port pins * Event controlled fault protection for instant and predictable fault triggering 17.2 Overview The advanced waveform extension (AWeX) provides extra functions to the timer/counter in waveform generation (WG) modes. It is primarily intended for use with different types of motor control and other power control applications. It enables low- and high side output with dead-time insertion and fault protection for disabling and shutting down external drivers. It can also generate a synchronized bit pattern across the port pins. Each of the waveform generator outputs from the timer/counter 0 are split into a complimentary pair of outputs when any AWeX features are enabled. These output pairs go through a deadtime insertion (DTI) unit that generates the non-inverted low side (LS) and inverted high side (HS) of the WG output with dead-time insertion between LS and HS switching. The DTI output will override the normal port value according to the port override setting. The pattern generation unit can be used to generate a synchronized bit pattern on the port it is connected to. In addition, the WG output from compare channel A can be distributed to and override all the port pins. When the pattern generator unit is enabled, the DTI unit is bypassed. The fault protection unit is connected to the event system, enabling any event to trigger a fault condition that will disable the AWeX output. The event system ensures predictable and instant fault reaction, and gives flexibility in the selection of fault triggers. The AWeX is available for TCC0. The notation of this is AWEXC. 37 8135L-AVR-06/12 XMEGA D4 18. Hi-Res - High Resolution Extension 18.1 Features * Increases waveform generator resolution up to 8x (three bits) * Supports frequency, single-slope PWM, and dual-slope PWM generation * Supports the AWeX when this is used for the same timer/counter 18.2 Overview The high-resolution (hi-res) extension can be used to increase the resolution of the waveform generation output from a timer/counter by four or eight. It can be used for a timer/counter doing frequency, single-slope PWM, or dual-slope PWM generation. It can also be used with the AWeX if this is used for the same timer/counter. The hi-res extension uses the peripheral 4x clock (ClkPER4). The system clock prescalers must be configured so the peripheral 4x clock frequency is four times higher than the peripheral and CPU clock frequency when the hi-res extension is enabled. There is one hi-res extension that can be enabled for the timer/counter pair on PORTC. The notation of this is HIRESC. 38 8135L-AVR-06/12 XMEGA D4 19. RTC - 16-bit Real-Time Counter 19.1 Features * 16-bit resolution * Selectable clock source * * * * * 19.2 - 32.768kHz external crystal - External clock - 32.768kHz internal oscillator - 32kHz internal ULP oscillator Programmable 10-bit clock prescaling One compare register One period register Clear counter on period overflow Optional interrupt/event on overflow and compare match Overview The 16-bit real-time counter (RTC) is a counter that typically runs continuously, including in lowpower sleep modes, to keep track of time. It can wake up the device from sleep modes and/or interrupt the device at regular intervals. The reference clock is typically the 1.024kHz output from a high-accuracy crystal of 32.768kHz, and this is the configuration most optimized for low power consumption. The faster 32.768kHz output can be selected if the RTC needs a resolution higher than 1ms. The RTC can also be clocked from an external clock signal, the 32.768kHz internal oscillator or the 32kHz internal ULP oscillator. The RTC includes a 10-bit programmable prescaler that can scale down the reference clock before it reaches the counter. A wide range of resolutions and time-out periods can be configured. With a 32.768kHz clock source, the maximum resolution is 30.5s, and time-out periods can range up to 2000 seconds. With a resolution of 1s, the maximum timeout period is more than18 hours (65536 seconds). The RTC can give a compare interrupt and/or event when the counter equals the compare register value, and an overflow interrupt and/or event when it equals the period register value. Figure 19-1. Real-time counter overview. External Clock TOSC1 TOSC2 32.768kHz Crystal Osc 32.768kHz Int. Osc DIV32 DIV32 32kHz int ULP (DIV32) PER RTCSRC clkRTC 10-bit prescaler = TOP/ Overflow = "match"/ Compare CNT COMP 39 8135L-AVR-06/12 XMEGA D4 20. TWI - Two-Wire Interface 20.1 Features * Two Identical two-wire interface peripherals * Bidirectional, two-wire communication interface * * * * * * * * * 20.2 - Phillips I2C compatible - System Management Bus (SMBus) compatible Bus master and slave operation supported - Slave operation - Single bus master operation - Bus master in multi-master bus environment - Multi-master arbitration Flexible slave address match functions - 7-bit and general call address recognition in hardware - 10-bit addressing supported - Address mask register for dual address match or address range masking - Optional software address recognition for unlimited number of addresses Slave can operate in all sleep modes, including power-down Slave address match can wake device from all sleep modes 100kHz and 400kHz bus frequency support Slew-rate limited output drivers Input filter for bus noise and spike suppression Support arbitration between start/repeated start and data bit (SMBus) Slave arbitration allows support for address resolve protocol (ARP) (SMBus) Overview The two-wire interface (TWI) is a bidirectional, two-wire communication interface. It is I2C and System Management Bus (SMBus) compatible. The only external hardware needed to implement the bus is one pull-up resistor on each bus line. A device connected to the bus must act as a master or a slave. The master initiates a data transaction by addressing a slave on the bus and telling whether it wants to transmit or receive data. One bus can have many slaves and one or several masters that can take control of the bus. An arbitration process handles priority if more than one master tries to transmit data at the same time. Mechanisms for resolving bus contention are inherent in the protocol. The TWI module supports master and slave functionality. The master and slave functionality are separated from each other, and can be enabled and configured separately. The master module supports multi-master bus operation and arbitration. It contains the baud rate generator. Both 100kHz and 400kHz bus frequency is supported. Quick command and smart mode can be enabled to auto-trigger operations and reduce software complexity. The slave module implements 7-bit address match and general address call recognition in hardware. 10-bit addressing is also supported. A dedicated address mask register can act as a second address match register or as a register for address range masking. The slave continues to operate in all sleep modes, including power-down mode. This enables the slave to wake up the device from all sleep modes on TWI address match. It is possible to disable the address matching to let this be handled in software instead. The TWI module will detect START and STOP conditions, bus collisions, and bus errors. Arbitration lost, errors, collision, and clock hold on the bus are also detected and indicated in separate status flags available in both master and slave modes. 40 8135L-AVR-06/12 XMEGA D4 It is possible to disable the TWI drivers in the device, and enable a four-wire digital interface for connecting to an external TWI bus driver. This can be used for applications where the device operates from a different VCC voltage than used by the TWI bus. PORTC and PORTE each has one TWI. Notation of these peripherals are TWIC and TWIE. 41 8135L-AVR-06/12 XMEGA D4 21. SPI - Serial Peripheral Interface 21.1 Features * * * * * * * * * 21.2 Two Identical SPI peripherals Full-duplex, three-wire synchronous data transfer Master or slave operation Lsb first or msb first data transfer Eight programmable bit rates Interrupt flag at the end of transmission Write collision flag to indicate data collision Wake up from idle sleep mode Double speed master mode Overview The Serial Peripheral Interface (SPI) is a high-speed synchronous data transfer interface using three or four pins. It allows fast communication between an Atmel AVR XMEGA device and peripheral devices or between several microcontrollers. The SPI supports full-duplex communication. A device connected to the bus must act as a master or slave. The master initiates and controls all data transactions. PORTC and PORTD each has one SPI. Notation of these peripherals are SPIC and SPID. 42 8135L-AVR-06/12 XMEGA D4 22. USART 22.1 Features * Two identical USART peripherals * Full-duplex operation * Asynchronous or synchronous operation * * * * * * * 22.2 - Synchronous clock rates up to 1/2 of the device clock frequency - Asynchronous clock rates up to 1/8 of the device clock frequency Supports serial frames with 5, 6, 7, 8, or 9 data bits and 1 or 2 stop bits Fractional baud rate generator - Can generate desired baud rate from any system clock frequency - No need for external oscillator with certain frequencies Built-in error detection and correction schemes - Odd or even parity generation and parity check - Data overrun and framing error detection - Noise filtering includes false start bit detection and digital low-pass filter Separate interrupts for - Transmit complete - Transmit data register empty - Receive complete Multiprocessor communication mode - Addressing scheme to address a specific devices on a multidevice bus - Enable unaddressed devices to automatically ignore all frames Master SPI mode - Double buffered operation - Operation up to 1/2 of the peripheral clock frequency IRCOM module for IrDA compliant pulse modulation/demodulation Overview The universal synchronous and asynchronous serial receiver and transmitter (USART) is a fast and flexible serial communication module. The USART supports full-duplex communication and asynchronous and synchronous operation. The USART can be configured to operate in SPI master mode and used for SPI communication. Communication is frame based, and the frame format can be customized to support a wide range of standards. The USART is buffered in both directions, enabling continued data transmission without any delay between frames. Separate interrupts for receive and transmit complete enable fully interrupt driven communication. Frame error and buffer overflow are detected in hardware and indicated with separate status flags. Even or odd parity generation and parity check can also be enabled. The clock generator includes a fractional baud rate generator that is able to generate a wide range of USART baud rates from any system clock frequencies. This removes the need to use an external crystal oscillator with a specific frequency to achieve a required baud rate. It also supports external clock input in synchronous slave operation. When the USART is set in master SPI mode, all USART-specific logic is disabled, leaving the transmit and receive buffers, shift registers, and baud rate generator enabled. Pin control and interrupt generation are identical in both modes. The registers are used in both modes, but their functionality differs for some control settings. An IRCOM module can be enabled for one USART to support IrDA 1.4 physical compliant pulse modulation and demodulation for baud rates up to 115.2Kbps. PORTC and PORTD each has one USART. Notation of these peripherals are USARTC0 and USARTD0 respectively. 43 8135L-AVR-06/12 XMEGA D4 23. IRCOM - IR Communication Module 23.1 Features * Pulse modulation/demodulation for infrared communication * IrDA compatible for baud rates up to 115.2Kbps * Selectable pulse modulation scheme - 3/16 of the baud rate period - Fixed pulse period, 8-bit programmable - Pulse modulation disabled * Built-in filtering * Can be connected to and used by any USART 23.2 Overview Atmel AVR XMEGA devices contain an infrared communication module (IRCOM) that is IrDA compatible for baud rates up to 115.2Kbps. It can be connected to any USART to enable infrared pulse encoding/decoding for that USART. 44 8135L-AVR-06/12 XMEGA D4 24. CRC - Cyclic Redundancy Check Generator 24.1 Features * Cyclic redundancy check (CRC) generation and checking for - Communication data - Program or data in flash memory - Data in SRAM and I/O memory space * Integrated with flash memory and CPU - Automatic CRC of the complete or a selectable range of the flash memory - CPU can load data to the CRC generator through the I/O interface * CRC polynomial software selectable to - CRC-16 (CRC-CCITT) - CRC-32 (IEEE 802.3) * Zero remainder detection 24.2 Overview A cyclic redundancy check (CRC) is an error detection technique test algorithm used to find accidental errors in data, and it is commonly used to determine the correctness of a data transmission, and data present in the data and program memories. A CRC takes a data stream or a block of data as input and generates a 16- or 32-bit output that can be appended to the data and used as a checksum. When the same data are later received or read, the device or application repeats the calculation. If the new CRC result does not match the one calculated earlier, the block contains a data error. The application will then detect this and may take a corrective action, such as requesting the data to be sent again or simply not using the incorrect data. Typically, an n-bit CRC applied to a data block of arbitrary length will detect any single error burst not longer than n bits (any single alteration that spans no more than n bits of the data), and will detect the fraction 1-2-n of all longer error bursts. The CRC module in Atmel AVR XMEGA devices supports two commonly used CRC polynomials; CRC-16 (CRC-CCITT) and CRC-32 (IEEE 802.3). * CRC-16: Polynomial: x16+x12+x5+1 Hex value: 0x1021 * CRC-32: Polynomial: x32+x26+x23+x22+x16+x12+x11+x10+x8+x7+x5+x4+x2+x+1 Hex value: 0x04C11DB7 45 8135L-AVR-06/12 XMEGA D4 25. ADC - 12-bit Analog to Digital Converter 25.1 Features * One Analog to Digital Converter (ADC) * 12-bit resolution * Up to 200 thousand samples per second * * * * * * * * 25.2 - Down to 3.6s conversion time with 8-bit resolution - Down to 5.0s conversion time with 12-bit resolution Differential and single-ended input - Up to 12 single-ended inputs - 12x4 differential inputs without gain - 8x4 differential inputs with gain Built-in differential gain stage - 1/2x, 1x, 2x, 4x, 8x, 16x, 32x, and 64x gain options Single, continuous and scan conversion options Three internal inputs - Internal temperature sensor - VCC voltage divided by 10 - 1.1V bandgap voltage Internal and external reference options Compare function for accurate monitoring of user defined thresholds Optional event triggered conversion for accurate timing Optional interrupt/event on compare result Overview The ADC converts analog signals to digital values. The ADC has 12-bit resolution and is capable of converting up to 200 thosuand samples per second (ksps). The input selection is flexible, and both single-ended and differential measurements can be done. For differential measurements, an optional gain stage is available to increase the dynamic range. In addition, several internal signal inputs are available. The ADC can provide both signed and unsigned results. The ADC measurements can either be started by application software or an incoming event from another peripheral in the device. The ADC measurements can be started with predictable timing, and without software intervention. Both internal and external reference voltages can be used. An integrated temperature sensor is available for use with the ADC. The VCC/10 and the bandgap voltage can also be measured by the ADC. The ADC has a compare function for accurate monitoring of user defined thresholds with minimum software intervention required. 46 8135L-AVR-06/12 XMEGA D4 Figure 25-1. ADC overview. ADC0 * * * ADC11 Compare Register ADC Internal signals ADC0 * * * ADC7 < > VINP Threshold (Int Req) CH0 Result VINN Internal 1.00V Internal VCC/1.6V Internal VCC/2 AREFA AREFB Reference Voltage The ADC may be configured for 8- or 12-bit result, reducing the minimum conversion time (propagation delay) from 5.0s for 12-bit to 3.6s for 8-bit result. ADC conversion results are provided left- or right adjusted with optional `1' or `0' padding. This eases calculation when the result is represented as a signed integer (signed 16-bit number). PORTA has one ADC. Notation of this peripheral is ADCA. 47 8135L-AVR-06/12 XMEGA D4 26. AC - Analog Comparator 26.1 Features * Two Analog Comparators * Selectable hysteresis * * * * * 26.2 - No - Small - Large Analog comparator output available on pin Flexible input selection - All pins on the port - Bandgap reference voltage - A 64-level programmable voltage scaler of the internal VCC voltage Interrupt and event generation on: - Rising edge - Falling edge - Toggle Window function interrupt and event generation on: - Signal above window - Signal inside window - Signal below window Constant current source with configurable output pin selection Overview The analog comparator (AC) compares the voltage levels on two inputs and gives a digital output based on this comparison. The analog comparator may be configured to generate interrupt requests and/or events upon several different combinations of input change. The analog comparator hysteresis can be adjusted in order to achieve the optimal operation for each application. The input selection includes analog port pins, several internal signals, and a 64-level programmable voltage scaler. The analog comparator output state can also be output on a pin for use by external devices. A constant current source can be enabled and output on a selectable pin. This can be used to replace, for example, external resistors used to charge capacitors in capacitive touch sensing applications. The analog comparators are always grouped in pairs on each port. These are called analog comparator 0 (AC0) and analog comparator 1 (AC1). They have identical behavior, but separate control registers. Used as pair, they can be set in window mode to compare a signal to a voltage range instead of a voltage level. PORTA has one AC pair. Notation is ACA. 48 8135L-AVR-06/12 XMEGA D4 Figure 26-1. Analog comparator overview. Pin Input + AC0OUT AC0 Pin Input Hysteresis Enable Voltage Scaler ACnMUXCTRL ACnCTRL Bandgap Interrupt Mode WINCTRL Enable Interrupt Sensititivity Control & Window Function Interrupts Events Hysteresis + Pin Input AC1OUT AC1 Pin Input The window function is realized by connecting the external inputs of the two analog comparators in a pair as shown in Figure 26-2. Figure 26-2. Analog comparator window function. + AC0 Upper limit of window Interrupt sensitivity control Input signal Interrupts Events + AC1 Lower limit of window - 49 8135L-AVR-06/12 XMEGA D4 27. Programming and Debugging 27.1 Features * Programming - External programming through PDI Minimal protocol overhead for fast operation Built-in error detection and handling for reliable operation - Boot loader support for programming through any communication interface * Debugging - Nonintrusive, real-time, on-chip debug system - No software or hardware resources required from device except pin connection - Program flow control Go, Stop, Reset, Step Into, Step Over, Step Out, Run-to-Cursor - Unlimited number of user program breakpoints - Unlimited number of user data breakpoints, break on: Data location read, write, or both read and write Data location content equal or not equal to a value Data location content is greater or smaller than a value Data location content is within or outside a range - No limitation on device clock frequency * Program and Debug Interface (PDI) - Two-pin interface for external programming and debugging - Uses the Reset pin and a dedicated pin - No I/O pins required during programming or debugging 27.2 Overview The Program and Debug Interface (PDI) is an Atmel proprietary interface for external programming and on-chip debugging of a device. The PDI supports fast programming of nonvolatile memory (NVM) spaces; flash, EEPOM, fuses, lock bits, and the user signature row. Debug is supported through an on-chip debug system that offers nonintrusive, real-time debug. It does not require any software or hardware resources except for the device pin connection. Using the Atmel tool chain, it offers complete program flow control and support for an unlimited number of program and complex data breakpoints. Application debug can be done from a C or other high-level language source code level, as well as from an assembler and disassembler level. Programming and debugging can be done through the PDI physical layer. This is a two-pin interface that uses the Reset pin for the clock input (PDI_CLK) and one other dedicated pin for data input and output (PDI_DATA). Any external programmer or on-chip debugger/emulator can be directly connected to this interface. 50 8135L-AVR-06/12 XMEGA D4 28. Pinout and Pin Functions The device pinout is shown in "Pinout/Block Diagram" on page 3. In addition to general purpose I/O functionality, each pin can have several alternate functions. This will depend on which peripheral is enabled and connected to the actual pin. Only one of the pin functions can be used at time. 28.1 Alternate Pin Function Description The tables below show the notation for all pin functions available and describe its function. 28.1.1 28.1.2 28.1.3 28.1.4 Operation/Power Supply VCC Digital supply voltage AVCC Analog supply voltage GND Ground Port Interrupt functions SYNC Port pin with full synchronous and limited asynchronous interrupt function ASYNC Port pin with full synchronous and full asynchronous interrupt function Analog functions ACn Analog Comparator input pin n ACnOUT Analog Comparator n Output ADCn Analog to Digital Converter input pin n AREF Analog Reference input pin Timer/Counter and AWEX functions OCnxLS Output Compare Channel x Low Side for Timer/Counter n OCnxHS Output Compare Channel x High Side for Timer/Counter n 51 8135L-AVR-06/12 XMEGA D4 28.1.5 28.1.6 28.1.7 Communication functions SCL Serial Clock for TWI SDA Serial Data for TWI SCLIN Serial Clock In for TWI when external driver interface is enabled SCLOUT Serial Clock Out for TWI when external driver interface is enabled SDAIN Serial Data In for TWI when external driver interface is enabled SDAOUT Serial Data Out for TWI when external driver interface is enabled XCKn Transfer Clock for USART n RXDn Receiver Data for USART n TXDn Transmitter Data for USART n SS Slave Select for SPI MOSI Master Out Slave In for SPI MISO Master In Slave Out for SPI SCK Serial Clock for SPI Oscillators, Clock and Event TOSCn Timer Oscillator pin n XTALn Input/Output for Oscillator pin n CLKOUT Peripheral Clock Output EVOUT Event Channel Output RTCOUT RTC Clock Source Output Debug/System functions RESET Reset pin PDI_CLK Program and Debug Interface Clock pin PDI_DATA Program and Debug Interface Data pin 52 8135L-AVR-06/12 XMEGA D4 28.2 Alternate Pin Functions The tables below show the primary/default function for each pin on a port in the first column, the pin number in the second column, and then all alternate pin functions in the remaining columns. The head row shows what peripheral that enable and use the alternate pin functions. For better flexibility, some alternate functions also have selectable pin locations for their functions, this is noted under the first table where this apply. Table 28-1. PORT A PIN # Port A - Alternate functions. INTERRUPT ADCA POS/GAINPOS ADCA NEG ADCA GAINNEG ACA POS ACA NEG GND 38 AVCC 39 PA0 40 SYNC ADC0 ADC0 AC0 AC0 PA1 41 SYNC ADC1 ADC1 AC1 AC1 PA2 42 SYNC/ASYNC ADC2 ADC2 AC2 PA3 43 SYNC ADC3 ADC3 AC3 PA4 44 SYNC ADC4 ADC4 AC4 PA5 1 SYNC ADC5 ADC5 AC5 PA6 2 SYNC ADC6 ADC6 AC6 PA7 3 SYNC ADC7 ADC7 Table 28-2. PORT B ACA OUT REFA AREF AC3 AC5 AC1OUT AC7 AC0OUT Port B - Alternate functions. PIN # INTERRUPT ADCA POS REFB PB0 4 SYNC ADC8 AREF PB1 5 SYNC ADC9 PB2 6 SYNC/ASYNC ADC10 PB3 7 SYNC ADC11 53 8135L-AVR-06/12 XMEGA D4 Table 28-3. PORT C Port C - Alternate functions. PIN # INTERRUPT TCC0 (1)(2) AWEXC TCC1 USARTC0 (3) SPIC (4) TWIC CLOCKOUT (5) GND 8 VCC 9 PC0 10 SYNC OC0A OC0ALS PC1 11 SYNC OC0B OC0AHS XCK0 PC2 12 SYNC/ASYNC OC0C OC0BLS RXD0 PC3 13 SYNC OC0D OC0BHS PC4 14 SYNC OC0CLS OC1A SS PC5 15 SYNC OC0CHS OC1B MOSI PC6 16 SYNC OC0DLS MISO clkRTC PC7 17 SYNC OC0DHS SCK clkPER Notes: 1. 2. 3. 4. 5. 6. SDA SCL TXD0 Port D - Alternate functions. PIN # INTERRUPT TCD0 SYNC OC0A USARTD0 SPID GND 18 VCC 19 PD0 20 PD1 21 SYNC OC0B XCK0 PD2 22 SYNC/ASYNC OC0C RXD0 PD3 23 SYNC OC0D TXD0 PD4 24 SYNC SS PD5 25 SYNC MOSI PD6 26 SYNC MISO PD7 27 SYNC SCK Table 28-5. PORT E EVOUT Pin mapping of all TC0 can optionally be moved to high nibble of port. If TC0 is configured as TC2 all eight pins can be used for PWM output. Pin mapping of all USART0 can optionally be moved to high nibble of port. Pins MOSI and SCK for all SPI can optionally be swapped. CLKOUT can optionally be moved between port C, D and E and between pin 4 and 7. EVOUT can optionally be moved between port C, D and E and between pin 4 and 7. Table 28-4. PORT D EVENTOUT (6) CLOCKOUT EVENTOUT clkPER EVOUT Port E - Alternate functions. PIN # INTERRUPT TCE0 TWIE PE0 28 SYNC OC0A SDA PE1 29 SYNC OC0B SCL GND 30 VCC 31 PE2 32 SYNC/ASYNC OC0C PE3 33 SYNC OC0D 54 8135L-AVR-06/12 XMEGA D4 Table 28-6. PORT R PIN # Port R- Alternate functions. INTERRUPT PDI PDI 34 PDI_DATA PDI_CLOCK XTAL TOSC(1) RESET 35 PRO 36 SYNC XTAL2 TOSC2 PR1 37 SYNC XTAL1 TOSC1 Note: 1. TOSC pins can optionally be moved to PE2/PE3. 55 8135L-AVR-06/12 XMEGA D4 29. Peripheral Module Address Map The address maps show the base address for each peripheral and module in Atmel AVR XMEGA D4. For complete register description and summary for each peripheral module, refer to the XMEGA D manual. Base address 0x0000 0x0010 0x0014 0x0018 0x001C 0x0030 0x0040 0x0048 0x0050 0x0060 0x0068 0x0070 0x0078 0x0080 0x0090 0x00A0 0x00B0 0x00D0 0x0180 0x01C0 0x0200 0x0380 0x0400 0x0480 0x04A0 0x0600 0x0620 0x0640 0x0660 0x0680 0x07E0 0x0800 0x0840 0x0880 0x0890 0x08A0 0x08C0 0x08F8 0x0900 0x09A0 0x09C0 0x0A00 Name Description GPIO VPORT0 VPORT1 VPORT2 VPORT3 CPU CLK SLEEP OSC DFLLRC32M DFLLRC2M PR RST WDT MCU PMIC PORTCFG CRC EVSYS NVM ADCA ACA RTC TWIC TWIE PORTA PORTB PORTC PORTD PORTE PORTR TCC0 TCC1 AWEXC HIRESC USARTC0 SPIC IRCOM TCD0 USARTD0 SPID TCE0 General Purpose IO Registers Virtual Port 0 Virtual Port 1 Virtual Port 2 Virtual Port 3 CPU Clock Control Sleep Controller Oscillator Control DFLL for the 32MHz Internal Oscillator DFLL for the 2MHz Internal Oscillator Power Reduction Reset Controller Watch-Dog Timer MCU Control Programmable Multilevel Interrupt Controller Port Configuration CRC Module Event System Non Volatile Memory (NVM) Controller Analog to Digital Converter on port A Analog Comparator pair on port A Real Time Counter Two Wire Interface on port C Two Wire Interface on port E Port A Port B Port C Port D Port E Port R Timer/Counter 0 on port C Timer/Counter 1 on port C Advanced Waveform Extension on port C High Resolution Extension on port C USART 0 on port C Serial Peripheral Interface on port C Infrared Communication Module Timer/Counter 0 on port D USART 0 on port D Serial Peripheral Interface on port D Timer/Counter 0 on port E 56 8135L-AVR-06/12 XMEGA D4 30. Instruction Set Summary Mnemonics Operands Description Operation Flags #Clocks Arithmetic and logic instructions ADD Rd, Rr Add without Carry Rd Rd + Rr Z,C,N,V,S,H 1 ADC Rd, Rr Add with Carry Rd Rd + Rr + C Z,C,N,V,S,H 1 ADIW Rd, K Add Immediate to Word Rd Rd + 1:Rd + K Z,C,N,V,S 2 SUB Rd, Rr Subtract without Carry Rd Rd - Rr Z,C,N,V,S,H 1 SUBI Rd, K Subtract Immediate Rd Rd - K Z,C,N,V,S,H 1 SBC Rd, Rr Subtract with Carry Rd Rd - Rr - C Z,C,N,V,S,H 1 SBCI Rd, K Subtract Immediate with Carry Rd Rd - K - C Z,C,N,V,S,H 1 SBIW Rd, K Subtract Immediate from Word Rd + 1:Rd Rd + 1:Rd - K Z,C,N,V,S 2 AND Rd, Rr Logical AND Rd Rd * Rr Z,N,V,S 1 ANDI Rd, K Logical AND with Immediate Rd Rd * K Z,N,V,S 1 OR Rd, Rr Logical OR Rd Rd v Rr Z,N,V,S 1 ORI Rd, K Logical OR with Immediate Rd Rd v K Z,N,V,S 1 EOR Rd, Rr Exclusive OR Rd Rd Rr Z,N,V,S 1 COM Rd One's Complement Rd $FF - Rd Z,C,N,V,S 1 NEG Rd Two's Complement Rd $00 - Rd Z,C,N,V,S,H 1 SBR Rd,K Set Bit(s) in Register Rd Rd v K Z,N,V,S 1 CBR Rd,K Clear Bit(s) in Register Rd Rd * ($FFh - K) Z,N,V,S 1 INC Rd Increment Rd Rd + 1 Z,N,V,S 1 DEC Rd Decrement Rd Rd - 1 Z,N,V,S 1 TST Rd Test for Zero or Minus Rd Rd * Rd Z,N,V,S 1 CLR Rd Clear Register Rd Rd Rd Z,N,V,S 1 SER Rd Set Register Rd $FF None 1 MUL Rd,Rr Multiply Unsigned R1:R0 Rd x Rr (UU) Z,C 2 MULS Rd,Rr Multiply Signed R1:R0 Rd x Rr (SS) Z,C 2 MULSU Rd,Rr Multiply Signed with Unsigned R1:R0 Rd x Rr (SU) Z,C 2 FMUL Rd,Rr Fractional Multiply Unsigned R1:R0 Rd x Rr<<1 (UU) Z,C 2 FMULS Rd,Rr Fractional Multiply Signed R1:R0 Rd x Rr<<1 (SS) Z,C 2 FMULSU Rd,Rr Fractional Multiply Signed with Unsigned R1:R0 Rd x Rr<<1 (SU) Z,C 2 RJMP k Relative Jump PC PC + k + 1 None 2 Branch instructions IJMP Indirect Jump to (Z) PC(15:0) PC(21:16) Z, 0 None 2 EIJMP Extended Indirect Jump to (Z) PC(15:0) PC(21:16) Z, EIND None 2 JMP k Jump PC k None 3 RCALL k Relative Call Subroutine PC PC + k + 1 None 2 / 3 (1) ICALL Indirect Call to (Z) PC(15:0) PC(21:16) Z, 0 None 2 / 3 (1) EICALL Extended Indirect Call to (Z) PC(15:0) PC(21:16) Z, EIND None 3 (1) PC k None 3 / 4 (1) CALL k call Subroutine 57 8135L-AVR-06/12 XMEGA D4 Mnemonics Operands Description Operation Flags #Clocks RET Subroutine Return PC STACK None 4 / 5 (1) RETI Interrupt Return PC STACK I 4 / 5 (1) if (Rd = Rr) PC PC + 2 or 3 None 1/2/3 CPSE Rd,Rr Compare, Skip if Equal CP Rd,Rr Compare CPC Rd,Rr Compare with Carry CPI Rd,K Compare with Immediate SBRC Rr, b Skip if Bit in Register Cleared SBRS Rr, b Skip if Bit in Register Set SBIC A, b Skip if Bit in I/O Register Cleared SBIS A, b Skip if Bit in I/O Register Set BRBS s, k BRBC BREQ Rd - Rr Z,C,N,V,S,H 1 Rd - Rr - C Z,C,N,V,S,H 1 Rd - K Z,C,N,V,S,H 1 if (Rr(b) = 0) PC PC + 2 or 3 None 1/2/3 if (Rr(b) = 1) PC PC + 2 or 3 None 1/2/3 if (I/O(A,b) = 0) PC PC + 2 or 3 None 2/3/4 If (I/O(A,b) =1) PC PC + 2 or 3 None 2/3/4 Branch if Status Flag Set if (SREG(s) = 1) then PC PC + k + 1 None 1/2 s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC PC + k + 1 None 1/2 k Branch if Equal if (Z = 1) then PC PC + k + 1 None 1/2 BRNE k Branch if Not Equal if (Z = 0) then PC PC + k + 1 None 1/2 BRCS k Branch if Carry Set if (C = 1) then PC PC + k + 1 None 1/2 BRCC k Branch if Carry Cleared if (C = 0) then PC PC + k + 1 None 1/2 BRSH k Branch if Same or Higher if (C = 0) then PC PC + k + 1 None 1/2 BRLO k Branch if Lower if (C = 1) then PC PC + k + 1 None 1/2 BRMI k Branch if Minus if (N = 1) then PC PC + k + 1 None 1/2 BRPL k Branch if Plus if (N = 0) then PC PC + k + 1 None 1/2 BRGE k Branch if Greater or Equal, Signed if (N V= 0) then PC PC + k + 1 None 1/2 BRLT k Branch if Less Than, Signed if (N V= 1) then PC PC + k + 1 None 1/2 BRHS k Branch if Half Carry Flag Set if (H = 1) then PC PC + k + 1 None 1/2 BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC PC + k + 1 None 1/2 BRTS k Branch if T Flag Set if (T = 1) then PC PC + k + 1 None 1/2 BRTC k Branch if T Flag Cleared if (T = 0) then PC PC + k + 1 None 1/2 BRVS k Branch if Overflow Flag is Set if (V = 1) then PC PC + k + 1 None 1/2 BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC PC + k + 1 None 1/2 BRIE k Branch if Interrupt Enabled if (I = 1) then PC PC + k + 1 None 1/2 BRID k Branch if Interrupt Disabled if (I = 0) then PC PC + k + 1 None 1/2 Data transfer instructions MOV Rd, Rr Copy Register MOVW Rd, Rr Copy Register Pair LDI Rd, K Load Immediate Rd Rr None 1 Rd+1:Rd Rr+1:Rr None 1 Rd K None 1 (1)(2) LDS Rd, k Load Direct from data space Rd (k) None 2 LD Rd, X Load Indirect Rd (X) None 1 (1)(2) LD Rd, X+ Load Indirect and Post-Increment Rd X (X) X+1 None 1 (1)(2) LD Rd, -X Load Indirect and Pre-Decrement X X - 1, Rd (X) X-1 (X) None 2 (1)(2) LD Rd, Y Load Indirect Rd (Y) (Y) None 1 (1)(2) LD Rd, Y+ Load Indirect and Post-Increment Rd Y (Y) Y+1 None 1 (1)(2) 58 8135L-AVR-06/12 XMEGA D4 Mnemonics Operands Description Flags #Clocks LD Rd, -Y Load Indirect and Pre-Decrement Y Rd Y-1 (Y) None 2 (1)(2) LDD Rd, Y+q Load Indirect with Displacement Rd (Y + q) None 2 (1)(2) LD Rd, Z Load Indirect Rd (Z) None 1 (1)(2) LD Rd, Z+ Load Indirect and Post-Increment Rd Z (Z), Z+1 None 1 (1)(2) LD Rd, -Z Load Indirect and Pre-Decrement Z Rd Z - 1, (Z) None 2 (1)(2) LDD Rd, Z+q Load Indirect with Displacement Rd (Z + q) None 2 (1)(2) STS k, Rr Store Direct to Data Space (k) Rd None 2 (1) ST X, Rr Store Indirect (X) Rr None 1 (1) ST X+, Rr Store Indirect and Post-Increment (X) X Rr, X+1 None 1 (1) ST -X, Rr Store Indirect and Pre-Decrement X (X) X - 1, Rr None 2 (1) ST Y, Rr Store Indirect (Y) Rr None 1 (1) ST Y+, Rr Store Indirect and Post-Increment (Y) Y Rr, Y+1 None 1 (1) ST -Y, Rr Store Indirect and Pre-Decrement Y (Y) Y - 1, Rr None 2 (1) STD Y+q, Rr Store Indirect with Displacement (Y + q) Rr None 2 (1) ST Z, Rr Store Indirect (Z) Rr None 1 (1) ST Z+, Rr Store Indirect and Post-Increment (Z) Z Rr Z+1 None 1 (1) ST -Z, Rr Store Indirect and Pre-Decrement Z Z-1 None 2 (1) STD Z+q,Rr Store Indirect with Displacement (Z + q) Rr None 2 (1) Load Program Memory R0 (Z) None 3 LPM Operation LPM Rd, Z Load Program Memory Rd (Z) None 3 LPM Rd, Z+ Load Program Memory and Post-Increment Rd Z (Z), Z+1 None 3 Extended Load Program Memory R0 (RAMPZ:Z) None 3 ELPM ELPM Rd, Z Extended Load Program Memory Rd (RAMPZ:Z) None 3 ELPM Rd, Z+ Extended Load Program Memory and PostIncrement Rd Z (RAMPZ:Z), Z+1 None 3 Store Program Memory (RAMPZ:Z) R1:R0 None - (RAMPZ:Z) Z R1:R0, Z+2 None - Rd I/O(A) None 1 I/O(A) Rr None 1 STACK Rr None 1 (1) Rd STACK None 2 (1) Rd(n+1) Rd(0) C Rd(n), 0, Rd(7) Z,C,N,V,H 1 Rd(n) Rd(7) C Rd(n+1), 0, Rd(0) Z,C,N,V 1 SPM SPM Z+ Store Program Memory and Post-Increment by 2 IN Rd, A In From I/O Location OUT A, Rr Out To I/O Location PUSH Rr Push Register on Stack POP Rd Pop Register from Stack Bit and bit-test instructions LSL Rd Logical Shift Left LSR Rd Logical Shift Right 59 8135L-AVR-06/12 XMEGA D4 Mnemonics Operands Description ROL Rd Rotate Left Through Carry ROR Rd ASR Rd Operation Flags #Clocks Rd(0) Rd(n+1) C C, Rd(n), Rd(7) Z,C,N,V,H 1 Rotate Right Through Carry Rd(7) Rd(n) C C, Rd(n+1), Rd(0) Z,C,N,V 1 Arithmetic Shift Right Rd(n) Rd(n+1), n=0..6 Z,C,N,V 1 SWAP Rd Swap Nibbles Rd(3..0) Rd(7..4) None 1 BSET s Flag Set SREG(s) 1 SREG(s) 1 BCLR s Flag Clear SREG(s) 0 SREG(s) 1 SBI A, b Set Bit in I/O Register I/O(A, b) 1 None 1 CBI A, b Clear Bit in I/O Register I/O(A, b) 0 None 1 BST Rr, b Bit Store from Register to T T Rr(b) T 1 BLD Rd, b Bit load from T to Register Rd(b) T None 1 SEC Set Carry C 1 C 1 CLC Clear Carry C 0 C 1 SEN Set Negative Flag N 1 N 1 CLN Clear Negative Flag N 0 N 1 SEZ Set Zero Flag Z 1 Z 1 CLZ Clear Zero Flag Z 0 Z 1 SEI Global Interrupt Enable I 1 I 1 CLI Global Interrupt Disable I 0 I 1 SES Set Signed Test Flag S 1 S 1 CLS Clear Signed Test Flag S 0 S 1 SEV Set Two's Complement Overflow V 1 V 1 CLV Clear Two's Complement Overflow V 0 V 1 SET Set T in SREG T 1 T 1 CLT Clear T in SREG T 0 T 1 SEH Set Half Carry Flag in SREG H 1 H 1 CLH Clear Half Carry Flag in SREG H 0 H 1 MCU control instructions BREAK Break NOP No Operation SLEEP Sleep WDR Watchdog Reset Notes: 1. 2. (See specific descr. for BREAK) None 1 None 1 (see specific descr. for Sleep) None 1 (see specific descr. for WDR) None 1 Cycle times for data memory accesses assume internal memory accesses, and are not valid for accesses via the external RAM interface. One extra cycle must be added when accessing Internal SRAM. 60 8135L-AVR-06/12 XMEGA D4 31. Packaging information 31.1 44A PIN 1 IDENTIFIER PIN 1 e B E1 E D1 D C 0~7 A1 A2 A L COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10mm maximum. SYMBOL MIN NOM MAX A - - 1.20 A1 0.05 - 0.15 A2 0.95 1.00 1.05 D 11.75 12.00 12.25 D1 9.90 10.00 10.10 E 11.75 12.00 12.25 E1 9.90 10.00 10.10 B 0.30 - 0.45 C 0.09 - 0.20 L 0.45 - 0.75 e NOTE Note 2 Note 2 0.80 TYP 2010-10-20 R 2325 Orchard Parkway San Jose, CA 95131 TITLE 44A, 44-lead, 10 x 10mm body size, 1.0mm body thickness, 0.8 mm lead pitch, thin profile plastic quad flat package (TQFP) DRAWING NO. REV. 44A C 61 8135L-AVR-06/12 XMEGA D4 31.2 44M1 D Marked Pin# 1 ID E SEATING PLANE A1 TOP VIEW A3 A K L Pin #1 Corner D2 1 2 3 Option A SIDE VIEW Pin #1 Triangle E2 Option B K Option C b e Pin #1 Chamfer (C 0.30) Pin #1 Notch (0.20 R) BOTTOM VIEW COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX A 0.80 0.90 1.00 A1 - 0.02 0.05 A3 0.20 REF b 0.18 0.23 0.30 D 6.90 7.00 7.10 D2 5.00 5.20 5.40 E 6.90 7.00 7.10 E2 5.00 5.20 5.40 e Note: JEDEC Standard MO-220, Fig. 1 (SAW Singulation) VKKD-3. NOTE 0.50 BSC L 0.59 0.64 0.69 K 0.20 0.26 0.41 9/26/08 Package Drawing Contact: packagedrawings@atmel.com TITLE 44M1, 44-pad, 7 x 7 x 1.0mm body, lead pitch 0.50mm, 5.20mm exposed pad, thermally enhanced plastic very thin quad flat no lead package (VQFN) GPC ZWS DRAWING NO. REV. 44M1 H 62 8135L-AVR-06/12 XMEGA D4 31.3 49C2 E A1 BALL ID 0.10 D A1 TOP VIEW A A2 SIDE VIEW E1 G e F E D D1 COMMON DIMENSIONS (Unit of Measure = mm) C B 1 A1 BALL CORNER MIN NOM MAX A - - 1.00 A1 0.20 - - A2 0.65 - - D 4.90 5.00 5.10 SYMBOL A 2 3 4 5 b 6 7 e BOTTOM VIEW 49 - O0.35 0.05 D1 E 3.90 BSC 4.90 5.00 E1 b NOTE 5.10 3.90 BSC 0.30 0.35 e 0.40 0.65 BSC 3/14/08 Package Drawing Contact: packagedrawings@atmel.com TITLE 49C2, 49-ball (7 x 7 array), 0.65mm pitch, 5.0 x 5.0 x 1.0mm, very thin, fine-pitch ball grid array package (VFBGA) GPC CBD DRAWING NO. REV. 49C2 A 63 8135L-AVR-06/12 XMEGA D4 32. Electrical Characteristics All typical values are measured at T = 25C unless other temperature condition is given. All minimum and maximum values are valid across operating temperature and voltage unless other conditions are given. 32.1 Absolute Maximum Ratings Stresses beyond those listed in Table 32-1 under may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 32-1. Symbol 32.2 Absolute maximum ratings. Parameter Condition Min. Typ. Max. Units 4 V VCC Power Supply Voltage IVCC Current into a VCC pin 200 IGND Current out of a Gnd pin 200 VPIN Pin voltage with respect to Gnd and VCC -0.5 VCC+0.5 V IPIN I/O pin sink/source current -25 25 mA TA Storage temperature -65 150 Tj Junction temperature -0.3 mA C 150 General Operating Ratings The device must operate within the ratings listed in Table 32-2 in order for all other electrical characteristics and typical characteristics of the device to be valid. Table 32-2. Symbol General operating conditions. Parameter Condition Min. Typ. Max. VCC Power Supply Voltage 1.60 3.6 AVCC Analog Supply Voltage 1.60 3.6 TA Temperature range -40 85 Tj Junction temperature -40 105 Units V C 64 8135L-AVR-06/12 XMEGA D4 Table 32-3. Symbol ClkCPU Operating voltage and frequency. Parameter CPU clock frequency Condition Min. Typ. Max. VCC = 1.6V 0 12 VCC = 1.8V 0 12 VCC = 2.7V 0 32 VCC = 3.6V 0 32 Units MHz The maximum CPU clock frequency depends on VCC. As shown in Figure 32-1 the Frequency vs. VCC curve is linear between 1.8V < VCC < 2.7V. Figure 32-1. Maximum frequency vs. VCC. MHz 32 Safe Operating Area 12 1.6 1.8 2.7 3.6 V 65 8135L-AVR-06/12 XMEGA D4 32.3 Current consumption Table 32-4. Symbol Current consumption for active mode and sleep modes. Parameter Condition 32kHz, ext. clk. Active power consumption (1) 1MHz, ext. clk. 2MHz, ext. clk. 32MHz, ext. clk. 32kHz, ext. clk. Idle power consumption (1) 1MHz, ext. clk. 2MHz, ext. clk. ICC 32MHz, ext. clk. Min. Power-down power consumption 68 VCC = 3.0V 145 VCC = 1.8V 260 VCC = 3.0V 540 VCC = 1.8V 460 600 0.96 1.4 9.8 12 VCC = 3.0V Power-save power consumption (2) Reset power consumption Notes: mA 2.4 VCC = 3.0V 3.9 VCC = 1.8V 62 VCC = 3.0V 118 VCC = 1.8V 125 225 240 350 3.8 5.5 0.1 1.0 1.2 4.5 1.3 3.0 2.4 6.0 VCC = 3.0V VCC = 3.0V A mA VCC = 3.0V RTC from ULP clock, WDT and sampled BOD enabled, T = 25C VCC = 1.8V 1.2 VCC = 3.0V 1.3 RTC from 1.024kHz low power 32.768kHz TOSC, T = 25C VCC = 1.8V 0.6 2 VCC = 3.0V 0.7 2 RTC from low power 32.768kHz TOSC, T = 25C VCC = 1.8V 0.8 3 VCC = 3.0V 1.0 3 VCC = 3.0V 320 Current through RESET pin substracted Units A VCC = 1.8V WDT and Sampled BOD enabled, T = 25C WDT and Sampled BOD enabled, T = 85C Max. VCC = 1.8V T = 25C T = 85C Typ. A 1. All Power Reduction Registers set. 2. Maximum limits are based on characterization, and not tested in production. 66 8135L-AVR-06/12 XMEGA D4 Table 32-5. Symbol Current consumption for modules and peripherals. Parameter Condition (1) Min. Typ. ULP oscillator 1.0 32.768kHz int. oscillator 27 Max. Units 85 2MHz int. oscillator DFLL enabled with 32.768kHz int. osc. as reference 115 270 32MHz int. oscillator PLL DFLL enabled with 32.768kHz int. osc. as reference 460 20x multiplication factor, 32MHz int. osc. DIV4 as reference 220 Watchdog Timer A 1 Continuous mode 138 Sampled mode, includes ULP oscillator 1.2 BOD ICC Internal 1.0V reference 100 Temperature sensor 95 3.0 ADC 50ksps VREF = Ext ref 2.6 CURRLIMIT = MEDIUM 2.1 CURRLIMIT = HIGH 1.6 mA AC 330 Timer/Counter 16 USART Rx and Tx enabled, 9600 BAUD Flash memory and EEPROM programming Note: CURRLIMIT = LOW A 2.5 4 8 mA 1. All parameters measured as the difference in current consumption between module enabled and disabled. All data at VCC = 3.0V, ClkSYS = 1MHz external clock without prescaling, T = 25C unless other conditions are given. 67 8135L-AVR-06/12 XMEGA D4 32.4 Wake-up time from sleep modes Table 32-6. Symbol Device wake-up time from sleep modes with various system clock sources. Parameter Condition External 2MHz clock Wake-up time from Idle, Standby, and Extended Standby mode Typ. (1) Max. Units 2 32.768kHz internal oscillator 120 2MHz internal oscillator 2 32MHz internal oscillator 0.2 External 2MHz clock 4.5 32.768kHz internal oscillator 320 s twakeup Wake-up time from Power-save and Power-down mode Note: Min. 2MHz internal oscillator 9 32MHz internal oscillator 5 1. The wake-up time is the time from the wake-up request is given until the peripheral clock is available on pin, see Figure 322. All peripherals and modules start execution from the first clock cycle, expect the CPU that is halted for four clock cycles before program execution starts. Figure 32-2. Wake-up time definition. Wakeup time Wakeup request Clock output 68 8135L-AVR-06/12 XMEGA D4 32.5 I/O Pin Characteristics The I/O pins complies with the JEDEC LVTTL and LVCMOS specification and the high- and low level input and output voltage limits reflect or exceed this specification. Table 32-7. Symbol IOH (1)/ IOL (2) VIH VIL VOH VOL I/O pin characteristics. Parameter Condition Max. Units -15 15 mA VCC = 2.7 - 3.6V 2 VCC+0.3 VCC = 2.0 - 2.7V 0.7xVCC VCC+0.3 VCC = 1.6 - 2.0V 0.7xVCC VCC+0.3 VCC = 2.7- 3.6V -0.3 0.3xVCC VCC = 2.0 - 2.7V -0.3 0.3xVCC VCC = 1.6 - 2.0V -0.3 0.3xVCC I/O pin source/sink current High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage IIN Input Leakage Current RP Pull/Buss keeper Resistor Min. Typ. VCC = 3.3V IOH = -4mA 2.6 2.9 VCC = 3.0V IOH = -3mA 2.1 2.6 VCC = 1.8V IOH = -1mA 1.4 1.6 VCC = 3.3V IOL = 8mA 0.4 0.76 VCC = 3.0V IOL = 5mA 0.3 0.64 VCC = 1.8V IOL = 3mA 0.2 0.46 <0.001 0.1 T = 25C 24 V A k 4 tr Notes: Rise time No load ns slew rate limitation 7 1. The sum of all IOH for PORTA and PORTB must not exceed 100mA. The sum of all IOH for PORTC must not exceed 200mA. The sum of all IOH for PORTD and pins PE[0-1] on PORTE must not exceed 200mA. The sum of all IOH for PE[2-3] on PORTE, PORTR and PDI must not exceed 100mA. 2. The sum of all IOL for PORTA and PORTB must not exceed 100mA. The sum of all IOL for PORTC must not not exceed 200mA. The sum of all IOL for PORTD and pins PE[0-1] on PORTE must not exceed 200mA. The sum of all IOL for PE[2-3] on PORTE, PORTR and PDI must not exceed 100mA. 69 8135L-AVR-06/12 XMEGA D4 32.6 ADC characteristics Table 32-8. Symbol Power supply, reference and input range. Parameter AVCC Analog supply voltage VREF Reference voltage Condition Min. Typ. Max. VCC- 0.3 VCC+ 0.3 1 AVCC- 0.6 Units V Input resistance Switched 4.0 k Csample Input capacitance Switched 4.4 pF RAREF Reference input resistance (leakage only) >10 M CAREF Reference input capacitance Static load 7 pF Rin VIN Input range Conversion range Differential mode, Vinp - Vinn VIN Conversion range Single ended unsigned mode, Vinp V Fixed offset voltage Table 32-9. Symbol ClkADC fADC -0.1 AVCC+0.1 -VREF VREF -V VREF-V 190 V LSB Clock and timing. Parameter ADC Clock frequency Condition Min. Typ. Max. Units Maximum is 1/4 of Peripheral clock frequency 100 1400 Measuring internal signals 100 125 Current limitation (CURRLIMIT) off 14 200 CURRLIMIT = LOW 14 150 CURRLIMIT = MEDIUM 14 100 CURRLIMIT = HIGH 14 50 0.25 5 s 7 10 ClkADC cycles kHz Sample rate ksps Sampling Time 1/2 ClkADC cycle Conversion time (latency) (RES+2)/2+GAIN RES = 8 or 12, GAIN = 0, 1, 2, or 3 Start-up time ADC clock cycles 12 24 After changing reference or input mode 7 7 After ADC flush 1 1 Min. Typ. Max. Units 8 12 12 Bits VCC-1.0V < VREF < VCC-0.6V 1.2 3 All VREF 1.5 4 VCC-1.0V < VREF < VCC-0.6V 1.0 3 All VREF 1.5 4 guaranteed monotonic <0.8 <1 5 ADC settling time ClkADC cycles Table 32-10. Accuracy characteristics. Symbol Parameter Condition (2) RES Resolution Programmable to 8 or 12 bit 50ksps INL (1) Integral non-linearity 200ksps DNL (1) Differential non-linearity lsb 70 8135L-AVR-06/12 XMEGA D4 Table 32-10. Accuracy characteristics. (Continued) Symbol Condition (2) Parameter Offset error Units Temperature drift <0.01 mV/K Operating voltage drift <0.6 mV/V External reference -1 AVCC/1.6 10 AVCC/2.0 8 Bandgap 5 mV Temperature drift <0.02 mV/K Operating voltage drift <0.5 mV/V Differential mode, shorted input 200ksps, VCC = 3.6V, ClkPER = 16MHz 0.4 mV rms 1. Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% input voltage range. 2. Unless otherwise noted all linearity, offset and gain error numbers are valid under the condition that external VREF is used. Table 32-11. Symbol Rin Csample INL (1) Gain stage characteristics. Parameter Condition Min. Typ. Max. Units Input resistance Switched in normal mode 4.0 k Input capacitance Switched in normal mode 4.4 pF Signal range Gain stage output Propagation delay ADC conversion rate Sample rate Same as ADC Integral non-linearity 50ksps Gain error Offset error, input referred 0 Noise VCC - 0.6 14 All gain settings 1.5 1x gain, normal mode -0.8 8x gain, normal mode -2.5 64x gain, normal mode -3.5 1x gain, normal mode -2 8x gain, normal mode -5 64x gain, normal mode -4 8x gain, normal mode 64x gain, normal mode V ClkADC cycles 1 200 kHz 4 lsb % mV 0.5 1x gain, normal mode Note: Max. mV Gain error Notes: Typ. -1 Differential mode Noise Min. VCC = 3.6V Ext. VREF 1.5 mV rms 11 1. Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% input voltage range. 71 8135L-AVR-06/12 XMEGA D4 32.7 Analog Comparator Characteristics Table 32-12. Analog comparator characteristics. Symbol Parameter Voff Input offset voltage Ilk Input leakage current Condition Min. Input voltage range Typ. Max. Units <10 mV <1 nA -0.1 AVCC V AC startup time 100 s Vhys1 Hysteresis, none 0 mV Vhys2 Hysteresis, small 13 Vhys3 Hysteresis, large 30 tdelay Propagation delay 30 90 ns 0.5 lsb 30 64-level voltage scaler 32.8 VCC = 3.0V, T= 85C Integral non-linearity (INL) 0.3 Bandgap and Internal 1.0V Reference Characteristics Table 32-13. Bandgap and Internal 1.0V reference characteristics. Symbol Parameter Condition Min. As reference for ADC Typ. Max. 1 ClkPER + 2.5s Startup time As input voltage to ADC and AC Units s 1.5 Bandgap voltage 1.1 V INT1V Internal 1.00V reference T= 85C, after calibration Variation over voltage and temperature Relative to T= 85C, VCC = 3.0V 0.99 1 1.5 1.01 % 72 8135L-AVR-06/12 XMEGA D4 32.9 Brownout Detection Characteristics Table 32-14. Brownout detection characteristics. Symbol Parameter Condition BOD level 0 falling VCC VBOT Min. Typ. Max. 1.60 1.62 1.72 BOD level 1 falling VCC 1.8 BOD level 2 falling VCC 2.0 BOD level 3 falling VCC 2.2 BOD level 4 falling VCC 2.4 BOD level 5 falling VCC 2.6 BOD level 6 falling VCC 2.8 BOD level 7 falling VCC 3.0 V Continuous mode tBOD 0.4 Detection time s Sampled mode VHYST Units 1000 Hysteresis 1.2 % 32.10 External Reset Characteristics Table 32-15. External reset characteristics. Symbol Parameter Condition Min. Typ. Max. Units 95 1000 ns Minimum reset pulse width tEXT Reset threshold voltage (VIH) VRST Reset threshold voltage (VIL) RRST VCC = 2.7 - 3.6V 0.60xVCC VCC = 1.6 - 2.7V 0.60xVCC VCC = 2.7 - 3.6V 0.50xVCC VCC = 1.6 - 2.7V 0.40xVCC Reset pin pull-up resistor V 25 k 32.11 Power-on Reset Characteristics Table 32-16. Power-on reset characteristics. Symbol Parameter VPOT- (1) POR threshold voltage falling VCC VPOT+ POR threshold voltage rising VCC Note: Condition Min. Typ. VCC falls faster than 1V/ms 0.4 1.0 VCC falls at 1V/ms or slower 0.8 1.0 1.3 Max. Units V 1.59 1. VPOT- values are only valid when BOD is disabled. When BOD is enabled VPOT- = VPOT+. 73 8135L-AVR-06/12 XMEGA D4 32.12 Flash and EEPROM Memory Characteristics Table 32-17. Endurance and data retention. Symbol Parameter Condition Min. 25C 10K 85C 10K 25C 100 55C 25 25C 80K 85C 30K 25C 100 55C 25 Typ. Max. Write/erase cycles Units Cycle Flash Data retention Year Write/erase cycles Cycle EEPROM Data retention Year Table 32-18. Programming time. Symbol Parameter Condition 128KB flash, EEPROM (2) and SRAM erase Typ. (1) 55 32KB flash, EEPROM (2) and SRAM erase 50 16KB flash, EEPROM (2) and SRAM erase Max. Units 75 and SRAM erase 64KB flash, EEPROM Chip Erase (2) Min. 45 Page erase 4 Page write 4 Atomic page erase and write 8 Page erase 4 Page write 4 Atomic page erase and write 8 ms Flash EEPROM Notes: 1. Programming is timed from the 2MHz internal oscillator. 2. EEPROM is not erased if the EESAVE fuse is programmed. 74 8135L-AVR-06/12 XMEGA D4 32.13 Clock and Oscillator Characteristics 32.13.1 Calibrated 32.768kHz Internal Oscillator characteristics Table 32-19. 32.768kHz internal oscillator characteristics. Symbol Parameter Condition Min. Frequency Factory calibration accuracy T = 85C, VCC = 3.0V kHz -0.5 0.5 -0.5 0.5 % 2MHz internal oscillator characteristics. Parameter Frequency range Condition Min. DFLL can tune to this frequency over voltage and temperature 1.8 Factory calibration accuracy Typ. Max. Units 2.2 MHz Factory calibrated frequency 2.0 T = 85C, VCC= 3.0V User calibration accuracy -1.5 1.5 -0.2 0.2 % Max. Units DFLL calibration stepsize 32.13.3 Units Calibrated 2MHz RC Internal Oscillator characteristics Table 32-20. Symbol Max. 32.768 User calibration accuracy 32.13.2 Typ. 0.21 Calibrated and tunable 32MHz internal oscillator characteristics Table 32-21. 32MHz internal oscillator characteristics. Symbol Parameter Frequency range Condition Min. DFLL can tune to this frequency over voltage and temperature 30 32 T = 85C, VCC= 3.0V User calibration accuracy -1.5 1.5 -0.2 0.2 % Max. Units DFLL calibration step size 32.13.4 55 MHz Factory calibrated frequency Factory calibration accuracy Typ. 0.22 32kHz Internal ULP Oscillator characteristics Table 32-22. 32kHz internal ULP oscillator characteristics. Symbol Parameter Condition Min. Output frequency Accuracy Typ. 32 -30 kHz 30 % 75 8135L-AVR-06/12 XMEGA D4 32.13.5 Internal Phase Locked Loop (PLL) characteristics Table 32-23. Internal PLL characteristics. Symbo l Parameter Input frequency fIN Output frequency (1) fOUT Condition Min. Typ. Output frequency must be within fOUT 0.4 64 VCC= 1.6 - 1.8V 20 48 VCC= 2.7 - 3.6V 20 128 Start-up time 25 Re-lock time 25 Max. Units MHz s Note: 1. The maximum output frequency vs. supply voltage is linear between 1.8V and 2.7V, and can never be higher than four times the maximum CPU frequency. 32.13.6 External clock characteristics Figure 32-3. External clock drive waveform. tCH tCH tCR tCF VIH1 VIL1 tCL tCK Table 32-24. External clock used as system clock without prescaling. Symbo l 1/tCK Parameter Clock frequency(1) tCK Clock period tCH Clock high time tCL Clock low time tCR Rise time (for maximum frequency) tCF Fall time (for maximum frequency) tCK Note: Change in period from one clock cycle to the next Condition Min. Typ. Max. VCC = 1.6 - 1.8V 0 12 VCC = 2.7 - 3.6V 0 32 VCC = 1.6 - 1.8V 83.3 VCC = 2.7 - 3.6V 31.5 VCC = 1.6 - 1.8V 30.0 VCC = 2.7 - 3.6V 12.5 VCC = 1.6 - 1.8V 30.0 VCC = 2.7 - 3.6V 12.5 Units MHz ns VCC = 1.6 - 1.8V 10 VCC = 2.7 - 3.6V 3 VCC = 1.6 - 1.8V 10 VCC = 2.7 - 3.6V 3 10 % 1. The maximum frequency vs. supply voltage is linear between 1.8V and 2.7V, and the same applies for all other parameters with supply voltage conditions. 76 8135L-AVR-06/12 XMEGA D4 . Table 32-25. External clock with prescaler (1) for system clock. Symbol 1/tCK Parameter Clock frequency (2) tCK Clock period tCH Clock High Time Condition Min. Typ. Max. VCC = 1.6 - 1.8V 0 90 VCC = 2.7 - 3.6V 0 142 VCC = 1.6 - 1.8V 11 VCC = 2.7 - 3.6V 7 VCC = 1.6 - 1.8V 4.5 VCC = 2.7 - 3.6V 2.4 VCC = 1.6 - 1.8V 4.5 VCC = 2.7 - 3.6V 2.4 MHz ns tCL Clock Low Time tCR Rise time (for maximum frequency) 1.5 tCF Fall time (for maximum frequency) 1.5 Change in period from one clock cycle to the next 10 tCK Notes: Units % 1. System Clock Prescalers must be set so that maximum CPU clock frequency for device is not exceeded. 2. The maximum frequency vs. supply voltage is linear between 1.8V and 2.7V, and the same applies for all other parameters with supply voltage conditions. 77 8135L-AVR-06/12 XMEGA D4 32.13.7 External 16MHz crystal oscillator and XOSC characteristics Table 32-26. External 16MHz crystal oscillator and XOSC characteristics. Symbol Parameter Condition Min. Typ. FRQRANGE=0 <10 FRQRANGE=1, 2, or 3 <1 Max. Units XOSCPWR=0 Cycle to cycle jitter XOSCPWR=1 <1 ns FRQRANGE=0 <6 XOSCPWR=0 Long term jitter FRQRANGE=1, 2, or 3 XOSCPWR=1 XOSCPWR=0 <0.5 <0.5 FRQRANGE=0 <0.1 FRQRANGE=1 <0.05 FRQRANGE=2 or 3 <0.005 Frequency error XOSCPWR=1 <0.005 % XOSCPWR=0 FRQRANGE=0 40 FRQRANGE=1 42 FRQRANGE=2 or 3 45 Duty cycle XOSCPWR=1 48 78 8135L-AVR-06/12 XMEGA D4 Table 32-26. External 16MHz crystal oscillator and XOSC characteristics. (Continued) Symbol Parameter Condition 0.4MHz resonator, CL = 100pF 2.4k 1MHz crystal, CL = 20pF 8.7k 2MHz crystal, CL = 20pF 2.1k 2MHz crystal 4.2k 8MHz crystal 250 9MHz crystal 195 8MHz crystal 360 9MHz crystal 285 12MHz crystal 155 9MHz crystal 365 12MHz crystal 200 16MHz crystal 105 9MHz crystal 435 12MHz crystal 235 16MHz crystal 125 9MHz crystal 495 12MHz crystal 270 16MHz crystal 145 XOSCPWR=1, FRQRANGE=2, CL=20pF 12MHz crystal 305 16MHz crystal 160 XOSCPWR=1, FRQRANGE=3, CL=20pF 12MHz crystal 380 16MHz crystal 205 XOSCPWR=0, FRQRANGE=0 XOSCPWR=0, FRQRANGE=1, CL=20pF XOSCPWR=0, FRQRANGE=2, CL=20pF RQ Negative impedance (1) Min. XOSCPWR=0, FRQRANGE=3, CL=20pF XOSCPWR=1, FRQRANGE=0, CL=20pF XOSCPWR=1, FRQRANGE=1, CL=20pF Typ. Units CXTAL1 Parasitic capacitance XTAL1 pin 5.4 CXTAL2 Parasitic capacitance XTAL2 pin 7.1 CLOAD Parasitic capacitance load 3.07 Note: Max. pF 1. Numbers for negative impedance are not tested in production but guaranteed from design and characterization. 79 8135L-AVR-06/12 XMEGA D4 32.13.8 External 32.768kHz crystal oscillator and TOSC characteristics Table 32-27. External 32.768kHz crystal oscillator and TOSC characteristics. Symbol Parameter Condition ESR/R1 Recommended crystal equivalent series resistance (ESR) Min. Typ. Max. Crystal load capacitance 6.5pF 60 Crystal load capacitance 9.0pF 35 Units k 5.4 CTOSC1 Parasitic capacitance TOSC1 pin CTOSC2 Parasitic capacitance TOSC2 pin pF Alternate TOSC 4.0 7.1 Recommended safety factor Note: pF Alternate TOSC 4.0 capacitance load matched to crystal specification 3 1. See Figure 32-4 for definition. Figure 32-4. TOSC input capacitance. CL1 TOSC1 CL2 Device internal External TOSC2 32.768KHz crystal The parasitic capacitance between the TOSC pins is CL1 + CL2 in series as seen from the crystal when oscillating without external capacitors. 80 8135L-AVR-06/12 XMEGA D4 32.14 SPI Characteristics Figure 32-5. SPI timing requirements in master mode. SS tMOS tSCKR tSCKF SCK (CPOL = 0) tSCKW SCK (CPOL = 1) tSCKW tMIS MISO (Data input) tMIH tSCK MSB LSB tMOH MOSI (Data output) tMOH MSB LSB Figure 32-6. SPI timing requirements in slave mode. SS tSSS tSCKR tSCKF tSSH SCK (CPOL = 0) tSSCKW SCK (CPOL = 1) tSSCKW tSIS MOSI (Data input) tSIH MSB tSOSSS MISO (Data output) tSSCK LSB tSOS MSB tSOSSH LSB 81 8135L-AVR-06/12 XMEGA D4 Table 32-28. SPI timing characteristics and requirements. Symbol Parameter Condition Min. Typ. Max. tSCK SCK period Master (See Table 17-4 in XMEGA D Manual) tSCKW SCK high/low width Master 0.5xSCK tSCKR SCK rise time Master 2.7 tSCKF SCK fall time Master 2.7 tMIS MISO setup to SCK Master 10 tMIH MISO hold after SCK Master 10 tMOS MOSI setup SCK Master 0.5xSCK tMOH MOSI hold after SCK Master 1 tSSCK Slave SCK period Slave 4xt ClkPER tSSCKW SCK high/low width Slave 2xt ClkPER tSSCKR SCK rise time Slave 1600 tSSCKF SCK fall time Slave 1600 tSIS MOSI setup to SCK Slave tSIH MOSI hold after SCK Slave tSSS SS setup to SCK Slave 21 tSSH SS hold after SCK Slave 20 tSOS MISO setup SCK Slave 8 tSOH MISO hold after SCK Slave 13 tSOSS MISO setup after SS low Slave 11 tSOSH MISO hold after SS high Slave 8 Units ns 3 t ClkPER 82 8135L-AVR-06/12 XMEGA D4 32.15 Two-Wire Interface Characteristics Table 32-29 describes the requirements for devices connected to the Two-Wire Interface Bus. The Atmel AVR XMEGA Two-wire interface meets or exceeds these requirements under the noted conditions. Timing symbols refer to Figure 32-7. Figure 32-7. Two-Wire Interface bus timing. tof tHIGH tLOW tr SCL tSU;STA tHD;DAT tSU;STO tSU;DAT tHD;STA SDA tBUF Table 32-29. Two-wire interface characteristics. Symbol Parameter Condition Min. VIH Input high voltage 0.7VCC VIL Input low voltage 0.5 Vhys Hysteresis of schmitt trigger inputs VOL Output low voltage tr Rise time for both SDA and SCL tof Output fall time from VIHmin to VILmax tSP Spikes suppressed by input filter II Input current for each I/O pin CI Capacitance for each I/O pin fSCL SCL clock frequency 0.05VCC 3mA, sink current 10pF < Cb < 400pF (2) fPER >max(10fSCL, 250kHz) Value of pull-up resistor fSCL > 100kHz Units 0.3xVCC V (1) 0.4 20+0.1Cb (1)(2) 300 20+0.1Cb 250 (1)(2) ns 0 50 -10 10 A 10 pF 400 kHz 0 fSCL 100kHz RP Max. VCC+0.5 0 0.1VCC < VI < 0.9VCC (3) Typ. V CC - 0.4V ---------------------------3mA 100ns ---------------Cb 300ns ---------------Cb 83 8135L-AVR-06/12 XMEGA D4 Table 32-29. Two-wire interface characteristics. (Continued) Symbol Parameter tHD;STA Hold time (repeated) START condition tLOW Low period of SCL clock tHIGH High period of SCL Clock tSU;STA Set-up time for a repeated START condition tHD;DAT Data hold time tSU;DAT Data setup time tSU;STO Setup time for STOP condition tBUF Bus free time between a STOP and START condition Notes: Condition Min. Typ. Max. fSCL 100kHz 4.0 fSCL > 100kHz 0.6 fSCL 100kHz 4.7 fSCL > 100kHz 1.3 fSCL 100kHz 4.0 fSCL > 100kHz 0.6 fSCL 100kHz 4.7 fSCL > 100kHz 0.6 fSCL 100kHz 0 3.45 fSCL > 100kHz 0 0.9 fSCL 100kHz 250 fSCL > 100kHz 100 fSCL 100kHz 4.0 fSCL > 100kHz 0.6 fSCL 100kHz 4.7 fSCL > 100kHz 1.3 Units s s 1. Required only for fSCL > 100kHz. 2. Cb = Capacitance of one bus line in pF. 3. fPER = Peripheral clock frequency. 84 8135L-AVR-06/12 XMEGA D4 33. Typical Characteristics 33.1 33.1.1 Current consumption Active mode supply current Figure 33-1. Active supply current vs. frequency. fSYS = 0 - 1MHz external clock, T = 25C. 700 3.3V 600 3.0V ICC [A] 500 2.7V 400 2.2V 300 1.8V 200 100 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency [MHz] Figure 33-2. Active supply current vs. frequency. fSYS = 1 - 32MHz external clock, T = 25C. 12 3.3V 10 3.0V 2.7V ICC [mA] 8 6 2.2V 4 1.8V 2 0 0 4 8 12 16 20 24 28 32 Frequency [MHz] 85 8135L-AVR-06/12 XMEGA D4 Figure 33-3. Active mode supply current vs. VCC. fSYS = 32.768kHz internal oscillator. 270 -40C 240 25C 210 ICC [A] 85C 180 150 120 90 60 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 33-4. Active mode supply current vs. VCC. fSYS = 1MHz external clock. 800 -40C 25C 85C 700 ICC [A] 600 500 400 300 200 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] 86 8135L-AVR-06/12 XMEGA D4 Figure 33-5. Active mode supply current vs. VCC. fSYS = 2MHz internal oscillator. 1600 -40C 1400 25C 85C ICC [A] 1200 1000 800 600 400 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 33-6. Active mode supply current vs. VCC. fSYS = 32MHz internal oscillator prescaled to 8MHz. 6.0 5.5 -40C 5.0 25C 85C ICC [mA] 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] 87 8135L-AVR-06/12 XMEGA D4 Figure 33-7. Active mode supply current vs. VCC. fSYS = 32MHz internal oscillator. 15 -40C 14 25C 13 ICC [mA] 85C 12 11 10 9 8 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 VCC [V] 33.1.2 Idle mode supply current Figure 33-8. Idle mode supply current vs. frequency. fSYS = 0 - 1MHz external clock, T = 25C. ICC [A] 140 3.3V 120 3.0V 100 2.7V 80 2.2V 60 1.8V 40 20 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency [MHz] 88 8135L-AVR-06/12 XMEGA D4 Figure 33-9. Idle mode supply current vs. frequency. fSYS = 1 - 32MHz external clock, T = 25C. 4.5 3.3V 4.0 3.0V 3.5 2.7V ICC [mA] 3.0 2.5 2.0 2.2V 1.5 1.0 1.8V 0.5 0 0 4 8 12 16 20 24 28 32 Frequency [MHz] Figure 33-10. Idle mode supply current vs. VCC. fSYS = 32.768kHz internal oscillator. 33.0 -40C 32.5 85C 32.0 25C 31.5 ICC [A] 31.0 30.5 30.0 29.5 29.0 28.5 28.0 27.5 27.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] 89 8135L-AVR-06/12 XMEGA D4 Figure 33-11. Idle mode supply current vs. VCC. fSYS = 1MHz external clock. 160 85C 25C -40C 150 140 130 ICC [A] 120 110 100 90 80 70 60 50 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 33-12. Idle mode supply current vs. VCC. fSYS = 2MHz internal oscillator. 420 -40C 25C 85C 400 380 360 340 ICC [A] 320 300 280 260 240 220 200 180 160 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] 90 8135L-AVR-06/12 XMEGA D4 Figure 33-13. Idle mode supply current vs. VCC. fSYS = 32MHz internal oscillator prescaled to 8MHz. 2.0 -40C 1.8 25C 85C I CC [mA] 1.6 1.4 1.2 1.0 0.8 0.6 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 33-14. Idle mode current vs. VCC. fSYS = 32MHz internal oscillator. 5.6 -40C 5.4 25C 5.2 5.0 85C I CC [mA] 4.8 4.6 4.4 4.2 4.0 3.8 3.6 3.4 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 VCC [V] 91 8135L-AVR-06/12 XMEGA D4 33.1.3 Power-down mode supply current Figure 33-15. Power-down mode supply current vs. temperature. All functions disabled. 1.20 3.3V 3.0V 2.7V 2.2V 1.8V 1.05 0.90 ICC [A] 0.75 0.60 0.45 0.30 0.15 0 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [C] Figure 33-16. Power-down mode supply current vs. VCC. All functions disabled. 1.4 85C 1.2 I CC [A] 1.0 0.8 0.6 0.4 0.2 25C -40C 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] 92 8135L-AVR-06/12 XMEGA D4 Figure 33-17. Power-down mode supply current vs. VCC. Watchdog and sampled BOD enabled. 2.7 85C 2.5 2.3 I CC [A] 2.1 1.9 1.7 1.5 25C -40C 1.3 1.1 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] 33.1.4 Power-save mode supply current Figure 33-18. Power-save mode supply current vs. VCC. Real Time Counter enabled and running from 1.024kHz output of 32.768kHz TOSC. 0.9 Normal mode 0.8 0.7 ICC [A] 0.6 Low-power mode 0.5 0.4 0.3 0.2 0.1 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] 93 8135L-AVR-06/12 XMEGA D4 33.1.5 Standby mode supply current ICC [A] Figure 33-19. Standby supply current vs. VCC. Standby, fSYS = 1MHz. 9.5 9.0 85C 8.5 8.0 7.5 25C -40C 7.0 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 33-20. Standby supply current vs. VCC. 25C, running from different crystal oscillators. 480 16MHz 12MHz 440 400 I CC [A] 360 320 8MHz 2MHz 280 240 0.454MHz 200 160 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] 94 8135L-AVR-06/12 XMEGA D4 33.2 33.2.1 I/O Pin Characteristics Pull-up Figure 33-21. I/O pin pull-up resistor current vs. input voltage. VCC = 1.8V. 70 60 I [A] 50 40 30 20 10 -40C 25C 85C 0 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 VPIN [V] Figure 33-22. I/O pin pull-up resistor current vs. input voltage. VCC = 3.0V. 120 105 90 I [A] 75 60 45 30 15 -40C 25C 85C 0 0.1 0.4 0.7 1.0 1.3 1.6 1.9 2.2 2.5 2.8 3.1 VPIN [V] 95 8135L-AVR-06/12 XMEGA D4 Figure 33-23. I/O pin pull-up resistor current vs. input voltage. VCC = 3.3V. 135 120 105 I [A] 90 75 60 45 30 -40C 25C 85C 15 0 0.1 0.4 0.7 1.0 1.3 1.6 1.9 2.2 2.5 2.8 3.1 3.4 VPIN [V] 33.2.2 Output Voltage vs. Sink/Source Current Figure 33-24. I/O pin output voltage vs. source current. VCC = 1.8V. 1.9 1.7 VPIN [V] 1.5 1.3 1.1 0.9 0.7 -40C 25C 85C 0.5 -5.0 -4.5 -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0 IPIN [mA] 96 8135L-AVR-06/12 XMEGA D4 Figure 33-25. I/O pin output voltage vs. source current. VCC = 3.0V. 3.0 VPIN [V] 2.5 2.0 1.5 1.0 -40C 0.5 -15.0 25C -12.5 85C -10.0 -7.5 -5.0 -2.5 0 -5.0 -2.5 0 IPIN [mA] Figure 33-26. I/O pin output voltage vs. source current. VCC = 3.3V. 3.5 3.0 VPIN [V] 2.5 2.0 -40C 1.5 25C 1.0 85C 0.5 -15.0 -12.5 -10.0 -7.5 IPIN [mA] 97 8135L-AVR-06/12 XMEGA D4 Figure 33-27. I/O pin output voltage vs. source current. 4.0 3.6V 3.5 3.3V 3.0V 3.0 VPIN [V] 2.7V 2.5 2.3V 2.0 1.8V 1.5 1.0 0.5 -12.0 -10.5 -9.0 -7.5 -6.0 -4.5 -3.0 -1.5 0 IPIN [mA] Figure 33-28. I/O pin output voltage vs. sink current. VCC = 1.8V. 1.0 0.9 0.8 85C 25C 7 8 -40C VPIN [V] 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 1 2 3 4 5 6 9 10 IPIN [mA] 98 8135L-AVR-06/12 XMEGA D4 Figure 33-29. I/O pin output voltage vs. sink current. VCC = 3.0V. 1.0 85C 0.9 25C 0.8 -40C 0.7 VPIN [V] 0.6 0.5 0.4 0.3 0.2 0.1 0 0 1.5 3.0 4.5 6.0 7.5 9.0 10.5 12.0 13.5 15.0 IPIN [mA] Figure 33-30. I/O pin output voltage vs. sink current. VCC = 3.3V. VPIN [V] 1.0 0.9 85C 0.8 25C 0.7 -40C 0.6 0.5 0.4 0.3 0.2 0.1 0 0 1.5 3.0 4.5 6.0 7.5 9.0 10.5 12.0 13.5 15.0 IPIN [mA] 99 8135L-AVR-06/12 XMEGA D4 Figure 33-31. I/O pin output voltage vs. sink current. 1.5 1.8V V PIN [V] 1.2 2.3V 2.7V 3.0V 3.3V 3.6V 0.9 0.6 0.3 0 0 2.5 5.0 7.5 10.0 12.5 15.0 I PIN [mA] 33.2.3 Thresholds and Hysteresis Figure 33-32. I/O pin input threshold voltage vs. VCC. T = 25C. 1.8 VIH 1.6 VIL 1.4 Vthreshold[V] 1.2 1.0 0.8 0.6 0.4 0.2 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] 100 8135L-AVR-06/12 XMEGA D4 Figure 33-33. I/O pin input threshold voltage vs. VCC. VIH I/O pin read as "1". 1.8 -40C 25C 85C 1.7 1.6 Vthreshold[V] 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 33-34. I/O pin input threshold voltage vs. VCC. VIL I/O pin read as "0". 1.62 -40C 25C 85C 1.47 Vthreshold[V] 1.32 1.17 1.02 0.87 0.72 0.57 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] 101 8135L-AVR-06/12 XMEGA D4 Figure 33-35. I/O pin input hysteresis vs. VCC. 0.3 -40C 0.27 Vthreshold [V] 0.24 0.21 25C 0.18 85C 0.15 0.12 0.09 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] 33.3 Analog Comparator Characteristics Figure 33-36. Analog comparator hysteresis vs. VCC. Small hysteresis. 85C -40C 25C 17 16 VHYST [mV] 15 14 13 12 11 10 9 8 7 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] 102 8135L-AVR-06/12 XMEGA D4 Figure 33-37. Analog comparator hysteresis vs. VCC. Large hysteresis. 40 85C 38 25C -40C 36 VHYST[mV] 34 32 30 28 26 24 22 20 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 33-38. Analog comparator current source vs. calibration value. Temperature = 25C. 8 7 I [A] 6 5 3.3V 3.0V 2.7V 4 3 2.2V 1.8V 2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CALIB[3..0] 103 8135L-AVR-06/12 XMEGA D4 Figure 33-39. Analog comparator current source vs. calibration value. VCC = 3.0V. 7 6.5 I [A] 6 5.5 5 4.5 -40C 25C 85C 4 3.5 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CALIB[3..0] Figure 33-40. Voltage scaler INL vs. SCALEFAC. T = 25C, VCC = 3.0V. 0.050 0.025 INL [LSB] 0 -0.025 -0.050 -0.075 -0.100 25C -0.125 -0.150 0 10 20 30 40 50 60 70 SCALEFAC 104 8135L-AVR-06/12 XMEGA D4 33.4 Internal 1.0V reference Characteristics Figure 33-41. ADC internal 1.0V reference vs. temperature. 1.003 1.8V 2.7V 3.0V 3.3V 1.001 Bandgap Voltage [V] 0.999 0.997 0.995 0.993 0.991 0.989 0.987 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 75 85 Temperature [C] 33.5 BOD Characteristics Figure 33-42. BOD thresholds vs. temperature. BOD level = 1.6V. 1.630 Rising Vcc 1.627 1.624 VBOT [V] 1.621 Falling Vcc 1.618 1.615 1.612 1.609 1.606 1.603 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 Temperature [C] 105 8135L-AVR-06/12 XMEGA D4 Figure 33-43. BOD thresholds vs. temperature. BOD level = 3.0V. 3.06 Rising Vcc 3.05 3.04 3.03 VBOT [V] 3.02 Falling Vcc 3.01 3.00 2.99 2.98 2.97 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [C] 33.6 External Reset Characteristics Figure 33-44. Minimum reset pin pulse width vs. VCC. 130 125 120 t RST [ns] 115 110 105 100 95 85C 90 25C -40C 85 80 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] 106 8135L-AVR-06/12 XMEGA D4 Figure 33-45. Reset pin pull-up resistor current vs. reset pin voltage. VCC = 1.8V. 70 60 IRESET [A] 50 40 30 20 -40C 25C 85C 10 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 VRESET [V] Figure 33-46. Reset pin pull-up resistor current vs. reset pin voltage. VCC = 3.0V. 120 105 I RESET [A] 90 75 60 45 30 -40C 25C 85C 15 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 VRESET [V] 107 8135L-AVR-06/12 XMEGA D4 Figure 33-47. Reset pin pull-up resistor current vs. reset pin voltage. VCC = 3.3V. 135 120 105 I RESET [A] 90 75 60 45 30 -40C 25C 85C 15 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 VRESET [V] Figure 33-48. Reset pin input threshold voltage vs. VCC. VIH - Reset pin read as "1". 2.1 -40C 25C 85C 2.0 1.9 Vthreshold [V] 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] 108 8135L-AVR-06/12 XMEGA D4 Figure 33-49. Reset pin input threshold voltage vs. VCC. VIL - Reset pin read as "0". -40C 25C 85C 1.7 1.6 1.5 Vthreshold [V] 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] 33.7 Power-on Reset Characteristics Figure 33-50. Power-on reset current consumption vs. VCC. BOD level = 3.0V, enabled in continuous mode. 700 -40C 600 25C 85C I CC [A] 500 400 300 200 100 0 0.4 0.7 1.0 1.3 1.6 1.9 2.2 2.5 2.8 VCC [V] 109 8135L-AVR-06/12 XMEGA D4 Figure 33-51. Power-on reset current consumption vs. VCC. BOD level = 3.0V, enabled in sampled mode. 650 -40C 585 520 25C 455 85C I CC [A] 390 325 260 195 130 65 0 0.4 0.7 1.0 1.3 1.6 1.9 2.2 2.5 2.8 VCC [V] 33.8 33.8.1 Oscillator Characteristics Ultra Low-Power internal oscillator Figure 33-52. Ultra Low-Power internal oscillator frequency vs. temperature. 32.7 32.5 32.3 Frequency [kHz] 32.1 31.9 31.7 31.5 31.3 31.1 3.3V 3.0V 2.7V 2.2V 1.8V 30.9 30.7 30.5 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [C] 110 8135L-AVR-06/12 XMEGA D4 33.8.2 32.768kHz Internal Oscillator Figure 33-53. 32.768kHz internal oscillator frequency vs. temperature. 3.3V 3.0V 2.7V 2.2V 1.8V 32.79 32.77 32.75 Frequency [kHz] 32.73 32.71 32.69 32.67 32.65 32.63 32.61 32.59 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [C] Figure 33-54. 32.768kHz internal oscillator frequency vs. calibration value. VCC = 3.0V, T = 25C. 52 49 46 Frequency [kHz] 43 40 37 34 31 28 25 22 0 24 48 72 96 120 144 168 192 216 240 264 RC32KCAL[7..0] 111 8135L-AVR-06/12 XMEGA D4 33.8.3 2MHz Internal Oscillator Figure 33-55. 2MHz internal oscillator frequency vs. temperature. DFLL disabled. 2.16 2.14 Frequency [MHz] 2.12 2.10 2.08 2.06 2.04 3.3V 3.0V 2.7V 2.2V 1.8V 2.02 2.00 1.98 -45 -35 -25 -15 -5 5 15 25 35 Temperature [C] 45 55 65 75 85 Figure 33-56. 2MHz internal oscillator frequency vs. temperature. DFLL enabled, from the 32.768kHz internal oscillator. 2.003 2.2V Frequency [MHz] 2.001 3.0V 1.999 1.997 1.995 3.3V 1.993 2.7V 1.8V 1.991 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [C] 112 8135L-AVR-06/12 XMEGA D4 Figure 33-57. 2MHz internal oscillator CALA calibration step size. VCC = 3V. 0.31 0.29 Step size [%] 0.27 0.25 0.23 0.21 -40C 0.19 25C 0.17 85C 0.15 0 10 20 30 40 50 60 70 80 90 100 110 120 130 CALA 33.8.4 32MHz Internal Oscillator Figure 33-58. 32MHz internal oscillator frequency vs. temperature. DFLL disabled. 36.0 35.5 Frequency [MHz] 35.0 34.5 34.0 33.5 33.0 3.3V 3.0V 2.7V 2.2V 1.8V 32.5 32.0 31.5 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [C] 113 8135L-AVR-06/12 XMEGA D4 Figure 33-59. 32MHz internal oscillator frequency vs. temperature. DFLL enabled, from the 32.768kHz internal oscillator. 32.00 3.3V 3.0V 2.7V 2.2V 1.8V 31.98 31.96 Frequency [MHz] 31.94 31.92 31.90 31.88 31.86 31.84 31.82 31.80 31.78 31.76 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [C] Figure 33-60. 32MHz internal oscillator CALA calibration step size. VCC = 3.0V. Step size [%] 0.36 0.34 0.32 0.30 0.28 0.26 0.24 0.22 0.20 85C 0.18 0.16 0.14 25C -40C 0.12 0.10 0 8 16 24 32 40 48 56 64 72 CALA 80 88 96 104 112 120 128 114 8135L-AVR-06/12 XMEGA D4 Figure 33-61. 32MHz internal oscillator frequency vs. CALB calibration value. VCC = 3.0V. 75 -40C 25C 85C 70 Frequency [MHz] 65 60 55 50 45 40 35 30 25 0 7 14 21 28 35 42 49 56 63 CALB 33.8.5 32MHz internal oscillator calibrated to 48MHz Figure 33-62. 48MHz internal oscillator frequency vs. temperature. DFLL disabled. 54 Frequency [MHz] 53 52 51 50 3.3V 3.0V 2.7V 2.2V 1.8V 49 48 47 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [C] 115 8135L-AVR-06/12 XMEGA D4 Figure 33-63. 48MHz internal oscillator frequency vs. temperature. DFLL enabled, from the 32.768kHz internal oscillator. 48.05 3.3V 3.0V 2.7V 2.2V 1.8V Frequency [MHz] 48.00 47.95 47.90 47.85 47.80 47.75 47.70 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [C] Figure 33-64. 48MHz internal oscillator CALA calibration step size. VCC = 3.0V. 0.35 0.32 Step size [%] 0.29 0.26 0.23 -40C 0.20 25C 85C 0.17 0.14 0.11 0 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120 128 CALA 116 8135L-AVR-06/12 XMEGA D4 33.9 Two-Wire Interface characteristics Figure 33-65. SDA hold time vs. temperature. 500 450 3 Hold time [ns] 400 350 2 300 250 200 150 100 1 50 0 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [C] Figure 33-66. SDA hold time vs. supply voltage. 500 450 3 Hold time [ns] 400 350 2 300 250 200 150 100 1 50 0 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 VCC [V] 117 8135L-AVR-06/12 XMEGA D4 33.10 PDI characteristics Figure 33-67. Maximum PDI frequency vs. VCC. 32 25C -40C 85C 30 28 f MAX [MHz] 26 24 22 20 18 16 14 12 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] 118 8135L-AVR-06/12 XMEGA D4 34. Errata 34.1 34.1.1 ATxmega16D4, ATxmega32D4 rev. E * ADC propagation delay is not correct when gain is used * CRC fails for Range CRC when end address is the last word address of a flash section * AWeX fault protection restore is not done correct in Pattern Generation Mode 1. ADC propagation delay is not correct when gain is used The propagation delay will increase by only one ADC clock cycle for all gain setting. Problem fix/Workaround None. 2. CRC fails for Range CRC when end address is the last word address of a flash section If boot read lock is enabled, the range CRC cannot end on the last address of the application section. If application table read lock is enabled, the range CRC cannot end on the last address before the application table. Problem fix/Workaround Ensure that the end address used in Range CRC does not end at the last address before a section with read lock enabled. Instead, use the dedicated CRC commands for complete applications sections. 3. AWeX fault protection restore is not done correctly in Pattern Generation Mode When a fault is detected the OUTOVEN register is cleared, and when fault condition is cleared, OUTOVEN is restored according to the corresponding enabled DTI channels. For Common Waveform Channel Mode (CWCM), this has no effect as the OUTOVEN is correct after restoring from fault. For Pattern Generation Mode (PGM), OUTOVEN should instead have been restored according to the DTILSBUF register. Problem fix/Workaround For CWCM no workaround is required. For PGM in latched mode, disable the DTI channels before returning from the fault condition. Then, set correct OUTOVEN value and enable the DTI channels, before the direction (DIR) register is written to enable the correct outputs again. For PGM in cycle-by-cycle mode there is no workaround. 4. Erroneous interrupt when using Timer/Counter with QDEC When the Timer/Counter is set in Dual Slope mode with QDEC enabled, an additional underflow interrupt (and event) will be given when the counter counts from BOTTOM to one. Problem fix/Workaround When receiving underflow interrupt check direction and value of counter. If direction is UP and counter value is zero, change the counter value to one. This will also remove the additional event. If the counter value is above zero, clear the interrupt flag. 34.1.2 rev. C/D Not sampled. 119 8135L-AVR-06/12 XMEGA D4 34.1.3 rev. A/B * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * Bandgap voltage input for the ACs can not be changed when used for both ACs simultaneously VCC voltage scaler for AC is non-linear ADC gain stage cannot be used for single conversion ADC has increased INL error for some operating conditions ADC gain stage output range is limited to 2.4 V ADC Event on compare match non-functional ADC propagation delay is not correct when 8x -64x gain is used Bandgap measurement with the ADC is non-functional when VCC is below 2.7V Accuracy lost on first three samples after switching input to ADC gain stage Configuration of PGM and CWCM not as described in XMEGA D Manual PWM is not restarted properly after a fault in cycle-by-cycle mode BOD: BOD will be enabled at any reset Sampled BOD in Active mode will cause noise when bandgap is used as reference EEPROM page buffer always written when NVM DATA0 is written Pending full asynchronous pin change interrupts will not wake the device Pin configuration does not affect Analog Comparator Output NMI Flag for Crystal Oscillator Failure automatically cleared Flash Power Reduction Mode can not be enabled when entering sleep Crystal start-up time required after power-save even if crystal is source for RTC RTC Counter value not correctly read after sleep Pending asynchronous RTC-interrupts will not wake up device TWI Transmit collision flag not cleared on repeated start Clearing TWI Stop Interrupt Flag may lock the bus TWI START condition at bus timeout will cause transaction to be dropped TWI Data Interrupt Flag (DIF) erroneously read as set WDR instruction inside closed window will not issue reset Inverted I/O enable does not affect Analog Comparator Output TWIE is not available CRC generator module is not available ADC 1/x gain setting and VCC/2 reference setting is not available TOSC alternate pin locations is not available TWI SDAHOLD time configuration is not available Timer/Counter 2 is not available HIRES+ option is not available Alternate pin locations for digital peripherals are not available XOSCPWR high drive option for external crystal is not available PLL divide by two option is not available Real Time Counter non-prescaled 32 kHZ clock options are not available PLL lock detection failure function is not available Non available functions and options 1. Bandgap voltage input for the ACs cannot be changed when used for both ACs simultaneously 120 8135L-AVR-06/12 XMEGA D4 If the Bandgap voltage is selected as input for one Analog Comparator (AC) and then selected/deselected as input for another AC, the first comparator will be affected for up to 1 s and could potentially give a wrong comparison result. Problem fix/Workaround If the Bandgap is required for both ACs simultaneously, configure the input selection for both ACs before enabling any of them. 2. VCC voltage scaler for AC is non-linear The 6-bit VCC voltage scaler in the Analog Comparators is non-linear. Figure 34-1. Analog Comparator Voltage Scaler vs. Scalefac. T = 25C. 3.5 3.3V 3 2.7V VSCALE [V] 2.5 2 1.8V 1.5 1 0.5 0 0 5 10 15 20 25 30 35 40 45 50 55 60 65 SCALEFAC Problem fix/Workaround Use external voltage input for the analog comparator if accurate voltage levels are needed 3. ADC gain stage cannot be used for single conversion The ADC gain stage will not output correct result for single conversion that is triggered and started from software or event system. Problem fix/Workaround When the gain stage is used, the ADC must be set in free running mode for correct results. 4. ADC has increased INL error for some operating conditions Some ADC configurations or operating condition will result in increased INL error. In signed mode INL is increased to: - 6LSB for sample rates above 130ksps, and up to 8LSB for 200ksps sample rate. - 6LSB for reference voltage below 1.1V when VCC is above 3.0V. - 20LSB for ambient temperature below 0 degree C and reference voltage below 1.3V. In unsigned mode, the INL error cannot be guaranteed, and this mode should not be used. Problem fix/Workaround 121 8135L-AVR-06/12 XMEGA D4 None, avoid using the ADC in the above configurations in order to prevent increased INL error. Use the ADC in signed mode also for single ended measurements. 5. ADC gain stage output range is limited to 2.4V The amplified output of the ADC gain stage will never go above 2.4V, hence the differential input will only give correct output when below 2.4V/gain. For the available gain settings, this gives a differential input range of: - 1x gain: 2.4 V - 2x gain: 1.2 V - 4x gain: 0.6 V - 8x gain: 300 mV - 16x gain: 150 mV - 32x gain: 75 mV - 64x gain: 38 mV Problem fix/Workaround Keep the amplified voltage output from the ADC gain stage below 2.4V in order to get a correct result, or keep ADC voltage reference below 2.4V. 6. ADC Event on compare match non-functional ADC signalling event will be given at every conversion complete even if Interrupt mode (INTMODE) is set to BELOW or ABOVE. Problem fix/Workaround Enable and use interrupt on compare match when using the compare function. 7. ADC propagation delay is not correct when 8x -64x gain is used The propagation delay will increase by only one ADC clock cycle for 8x and 16x gain setting, and 32x and 64x gain settings. Problem fix/Workaround None 8. Bandgap measurement with the ADC is non-functional when VCC is below 2.7V The ADC can not be used to do bandgap measurements when VCC is below 2.7V. Problem fix/Workaround None. 9. Accuracy lost on first three samples after switching input to ADC gain stage Due to memory effect in the ADC gain stage, the first three samples after changing input channel must be disregarded to achieve 12-bit accuracy. Problem fix/Workaround Run three ADC conversions and discard these results after changing input channels to ADC gain stage. 122 8135L-AVR-06/12 XMEGA D4 10. Configuration of PGM and CWCM not as described in XMEGA D Manual Enabling Common Waveform Channel Mode will enable Pattern generation mode (PGM), but not Common Waveform Channel Mode. Enabling Pattern Generation Mode (PGM) and not Common Waveform Channel Mode (CWCM) will enable both Pattern Generation Mode and Common Waveform Channel Mode. Problem fix/Workaround Table 34-1. Configure PWM and CWCM according to this table: PGM CWCM Description 0 0 PGM and CWCM disabled 0 1 PGM enabled 1 0 PGM and CWCM enabled 1 1 PGM enabled 11. PWM is not restarted properly after a fault in cycle-by-cycle mode When the AWeX fault restore mode is set to cycle-by-cycle, the waveform output will not return to normal operation at first update after fault condition is no longer present. Problem fix/Workaround Do a write to any AWeX I/O register to re-enable the output. 12. BOD will be enabled after any reset If any reset source goes active, the BOD will be enabled and keep the device in reset if the VCC voltage is below the programmed BOD level. During Power-On Reset, reset will not be released until VCC is above the programmed BOD level even if the BOD is disabled. Problem fix/Workaround Do not set the BOD level higher than VCC even if the BOD is not used. 13. Sampled BOD in Active mode will cause noise when bandgap is used as reference Using the BOD in sampled mode when the device is running in Active or Idle mode will add noise on the bandgap reference for ADC and Analog Comparator. Problem fix/Workaround If the bandgap is used as reference for either the ADC or the Analog Comparator, the BOD must not be set in sampled mode. 14. EEPROM page buffer always written when NVM DATA0 is written If the EEPROM is memory mapped, writing to NVM DATA0 will corrupt data in the EEPROM page buffer. Problem fix/Workaround Before writing to NVM DATA0, for example when doing software CRC or flash page buffer write, check if EEPROM page buffer active loading flag (EELOAD) is set. Do not write NVM DATA0 when EELOAD is set. 15. Pending full asynchronous pin change interrupts will not wake the device Any full asynchronous pin-change Interrupt from pin 2, on any port, that is pending when the sleep instruction is executed, will be ignored until the device is woken from another source or the source triggers again. This applies when entering all sleep modes where the System Clock is stopped. 123 8135L-AVR-06/12 XMEGA D4 Problem fix/Workaround None. 16. Pin configuration does not affect Analog Comparator output The Output/Pull and inverted pin configuration does not affect the Analog Comparator output. Problem fix/Workaround None for Output/Pull configuration. For inverted I/O, configure the Analog Comparator to give an inverted result (i.e. connect positive input to the negative AC input and vice versa), or use and external inverter to change polarity of Analog Comparator output. 17. NMI Flag for Crystal Oscillator Failure automatically cleared NMI flag for Crystal Oscillator Failure (XOSCFDIF) will be automatically cleared when executing the NMI interrupt handler. Problem fix/Workaround This device revision has only one NMI interrupt source, so checking the interrupt source in software is not required. 18. Flash Power Reduction Mode can not be enabled when entering sleep If Flash Power Reduction Mode is enabled when entering Power-save or Extended Standby sleep mode, the device will only wake up on every fourth wake-up request. If Flash Power Reduction Mode is enabled when entering Idle sleep mode, the wake-up time will vary with up to 16 CPU clock cycles. Problem fix/Workaround Disable Flash Power Reduction mode before entering sleep mode. 19. Crystal start-up time required after power-save even if crystal is source for RTC Even if 32.768kHz crystal is used for RTC during sleep, the clock from the crystal will not be ready for the system before the specified start-up time. See "XOSCSEL[3:0]: Crystal Oscillator Selection" in XMEGA D Manual. If BOD is used in active mode, the BOD will be on during this period (0.5s). Problem fix/Workaround If faster start-up is required, go to sleep with internal oscillator as system clock. 20. RTC Counter value not correctly read after sleep If the RTC is set to wake up the device on RTC Overflow and bit 0 of RTC CNT is identical to bit 0 of RTC PER as the device is entering sleep, the value in the RTC count register can not be read correctly within the first prescaled RTC clock cycle after wakeup. The value read will be the same as the value in the register when entering sleep. The same applies if RTC Compare Match is used as wake-up source. Problem fix/Workaround Wait at least one prescaled RTC clock cycle before reading the RTC CNT value. 21. Pending asynchronous RTC-interrupts will not wake up device Asynchronous Interrupts from the Real-Time-Counter that is pending when the sleep instruction is executed, will be ignored until the device is woken from another source or the source triggers again. 124 8135L-AVR-06/12 XMEGA D4 Problem fix/Workaround None. 22. TWI Transmit collision flag not cleared on repeated start The TWI transmit collision flag should be automatically cleared on start and repeated start, but is only cleared on start. Problem fix/Workaround Clear the flag in software after address interrupt. 23. Clearing TWI Stop Interrupt Flag may lock the bus If software clears the STOP Interrupt Flag (APIF) on the same Peripheral Clock cycle as the hardware sets this flag due to a new address received, CLKHOLD is not cleared and the SCL line is not released. This will lock the bus. Problem fix/Workaround Check if the bus state is IDLE. If this is the case, it is safe to clear APIF. If the bus state is not IDLE, wait for the SCL pin to be low before clearing APIF. Code: /* Only clear the interrupt flag if within a "safe zone". */ while ( /* Bus not IDLE: */ ((COMMS_TWI.MASTER.STATUS & TWI_MASTER_BUSSTATE_gm) != TWI_MASTER_BUSSTATE_IDLE_gc)) && /* SCL not held by slave: */ !(COMMS_TWI.SLAVE.STATUS & TWI_SLAVE_CLKHOLD_bm) ) { /* Ensure that the SCL line is low */ if ( !(COMMS_PORT.IN & PIN1_bm) ) if ( !(COMMS_PORT.IN & PIN1_bm) ) break; } /* Check for an pending address match interrupt */ if ( !(COMMS_TWI.SLAVE.STATUS & TWI_SLAVE_CLKHOLD_bm) ) { /* Safely clear interrupt flag */ COMMS_TWI.SLAVE.STATUS |= (uint8_t)TWI_SLAVE_APIF_bm; } 24. TWI START condition at bus timeout will cause transaction to be dropped If Bus Timeout is enabled and a timeout occurs on the same Peripheral Clock cycle as a START is detected, the transaction will be dropped. Problem fix/Workaround None. 25. TWI Data Interrupt Flag erroneously read as set When issuing the TWI slave response command CMD=0b11, it takes one Peripheral Clock cycle to clear the data interrupt flag (DIF). A read of DIF directly after issuing the command will show the DIF still set. 125 8135L-AVR-06/12 XMEGA D4 Problem fix/Workaround Add one NOP instruction before checking DIF. 26. WDR instruction inside closed window will not issue reset When a WDR instruction is execute within one ULP clock cycle after updating the window control register, the counter can be cleared without giving a system reset. Problem fix/Workaround Wait at least one ULP clock cycle before executing a WDR instruction. 28. Inverted I/O enable does not affect Analog Comparator Output The inverted I/O pin function does not affect the Analog Comparator output function Problem fix/Workaround Configure the analog comparator setup to give an inverted result, or use an external inverter to change polarity of Analog Comparator Output. 29. Non available functions and options The below function and options are not available. Writing to any registers or fuse to try and enable or configure these functions or options will have no effect, and will be as writing to a reserved address location. *TWIE, the TWI module on PORTE *TWI SDAHOLD option in the TWI CTRL register is one bit *CRC generator module *ADC 1/2x gain option, and this configuration option in the GAIN bits in the ADC Channel CTRL register *ADC VCC/2 reference option and this configuration option in the REFSEL bits on the ADC REFCTRL register *ADC option to use internal Gnd as negative input in differential measurements and this configuration option in the MUXNEG bits in the ADC Channel MUXCTRL register *ADC channel scan and the ADC SCAN register *ADC current limitation option, and the CURRLIMIT bits in the ADC CTRLB register *ADC impedance mode selection for the gain stage, and the IMPMODE bit in the ADC CTRLB register *Timer/Counter 2 and the SPLITMODE configuration option in the BYTEM bits in the Timer/Counter 0 CTRLE register *Analog Comparator (AC) current output option, and the AC CURRCTRL and CURRCALIB registers *PORT remap functions with alternate pin locations for Timer/Counter output compare channels, USART0 and SPI, and the PORT REMAP register *PORT RTC clock output option and the RTCOUT bit in the PORT CLKEVOUT register *PORT remap functions with alternate pin locations for the clock and event output, and the CLKEVPIN bit in the PORT CLKEVOUT register *TOSC alternate pin locations, and TOSCSEL bit in FUSEBYTE2 *Real Time Counter clock source options of external clock from TOSC1, and 32.768kHz from TOSC, and 32.768kHz from the 32.768kHz internal oscillator, and these configuration options in the RTCSRC bits in the Clock RTCTRL register 126 8135L-AVR-06/12 XMEGA D4 *PLL divide by two option, and the PLLDIV bit in the Clock PLLCTRL register *PLL lock detection failure function and the PLLDIF and PLLFDEN bits in the Clock XOSCFAIL register *The high drive option for external crystal and the XOSCPWR bit on the Oscillator XOSCCTRL register *The option to enable sequential startup of the analog modules and the ANAINIT register in MCU Control memory Problem fix/Workaround None. 127 8135L-AVR-06/12 XMEGA D4 35. Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 35.1 35.2 35.3 35.4 35.5 8135L - 06/12 1. Editing updates. 2. Updated all tables in the Chapter "Electrical Characteristics" on page 64. 3. Added new "Typical Characteristics" on page 85. 4. Added new Errata "rev. E" on page 119. 5. Added new ERRATA on "rev. A/B" on page 120: Non available functions and options 1. ATxmega64D4-CU is added in "Ordering Information" on page 2 1. Datasheet status changed to complete: Preliminary removed from the front page. 2. Updated all tables in the "Electrical Characteristics" . 3. Replaced Table 31-11 on page 64 4. Replaced Table 31-17 on page 65 and added the figure "TOSC input capacitance" on page 66 5. Updated ERRATA ADC (ADC has increased INL for some operating conditions). 6. Updated ERRATA "rev. A/B" on page 133 with TWIE (TWIE is not available). 7. Updated the last page with Atmel new Brand Style Guide. 1. Updated Table 31-1 on page 58. 1. Updated "Errata" on page 90. 8135K - 06/12 8135J - 12/10 8135I - 10/10 8135H - 09/10 128 8135L-AVR-06/12 XMEGA D4 35.6 35.7 35.8 35.9 8135G - 08/10 1. Updated the Footnote 3 of "Ordering Information" on page 2. 2. All references to CRC removed. Updated Figure 3-1 on page 7. 3. Updated "Features" on page 26. Event Channel 0 output on port pin 7. 4. Updated "DC Characteristics" on page 58 by adding Icc for Flash/EEPROM Programming. 5. Added AVCC in "ADC Characteristics" on page 62. 6. Updated Start up time in "ADC Characteristics" on page 62. 7. Updated and fixed typo in "Errata" section. 1. Added "PDI Speed" on page 89. 1. Updated the device pin-out Figure 2-1 on page 3. PDI_CLK and PDI_DATA renamed only PDI. 2. Updated Table 7-3 on page 18. No of Pages for ATxmega32D4: 32 3. Updated "Alternate Port Functions" on page 29. 4. Updated "ADC - 12-bit Analog to Digital Converter" on page 39. 5. Updated Figure 25-1 on page 50. 6. Updated "Alternate Pin Functions" on page 48. 7. Updated "Timer/Counter and AWEX functions" on page 46. 8. Added Table 31-17 on page 65. 9. Added Table 31-18 on page 66. 10. Changed Internal Oscillator Speed to "Oscillators and Wake-up Time" on page 85. 11. Updated "Errata" on page 90. 1. Added ATxmega128D4 device and updated the datasheet accordingly. 2. Updated "Electrical Characteristics" on page 58 with Max/Min numbers. 3. Added "Flash and EEPROM Memory Characteristics" on page 61. 4. Updated Table 31-10 on page 64, Input hysteresis is in V and not in mV. 5. Added "Errata" on page 90. 8135F - 02/10 8135E - 02/10 8135D - 12/09 129 8135L-AVR-06/12 XMEGA D4 35.10 8135C - 10/09 1. Updated "Features" on page 1 with Two Two-Wire Interfaces. 2. Updated "Block Diagram and QFN/TQFP pinout" on page 3. 3. Updated "Overview" on page 5. 4. Updated "XMEGA D4 Block Diagram" on page 7. 5. Updated Table 13-1 on page 24. 6. Updated "Overview" on page 35. 7. Updated Table 27-5 on page 49. 8. Updated "Peripheral Module Address Map" on page 50. 1. Added "Electrical Characteristics" on page 58. 2. Added "Typical Characteristics" on page 67. 1. Initial revision. 35.11 8135B - 09/09 35.12 8135A - 03/09 130 8135L-AVR-06/12 XMEGA D4 Table of Contents Features ..................................................................................................... 1 1 Ordering Information ............................................................................... 2 2 Pinout/Block Diagram .............................................................................. 3 3 Overview ................................................................................................... 5 3.1 4 Block Diagram ...................................................................................................6 Resources ................................................................................................. 7 4.1 Recommended reading .....................................................................................7 5 Capacitive touch sensing ........................................................................ 7 6 AVR CPU ................................................................................................... 8 7 8 6.1 Features ............................................................................................................8 6.2 Overview ............................................................................................................8 6.3 Architectural Overview .......................................................................................8 6.4 ALU - Arithmetic Logic Unit ...............................................................................9 6.5 Program Flow ..................................................................................................10 6.6 Status Register ................................................................................................10 6.7 Stack and Stack Pointer ..................................................................................10 6.8 Register File ....................................................................................................11 Memories ................................................................................................ 12 7.1 Features ..........................................................................................................12 7.2 Overview ..........................................................................................................12 7.3 Flash Program Memory ...................................................................................13 7.4 Fuses and Lock bits .........................................................................................14 7.5 Data Memory ...................................................................................................15 7.6 EEPROM .........................................................................................................15 7.7 I/O Memory ......................................................................................................15 7.8 Data Memory and Bus Arbitration ...................................................................16 7.9 Memory Timing ................................................................................................16 7.10 Device ID and Revision ...................................................................................16 7.11 I/O Memory Protection .....................................................................................16 7.12 Flash and EEPROM Page Size .......................................................................16 Event System ......................................................................................... 18 8.1 Features ..........................................................................................................18 i 8135L-AVR-06/12 XMEGA D4 8.2 9 Overview ..........................................................................................................18 System Clock and Clock options ......................................................... 20 9.1 Features ..........................................................................................................20 9.2 Overview ..........................................................................................................20 9.3 Clock Sources .................................................................................................21 10 Power Management and Sleep Modes ................................................. 23 10.1 Features ..........................................................................................................23 10.2 Overview ..........................................................................................................23 10.3 Sleep Modes ....................................................................................................23 11 System Control and Reset .................................................................... 25 11.1 Features ..........................................................................................................25 11.2 Overview ..........................................................................................................25 11.3 Reset Sequence ..............................................................................................25 11.4 Reset Sources .................................................................................................26 12 WDT - Watchdog Timer ......................................................................... 27 12.1 Features ..........................................................................................................27 12.2 Overview ..........................................................................................................27 13 Interrupts and Programmable Multilevel Interrupt Controller ........... 28 13.1 Features ..........................................................................................................28 13.2 Overview ..........................................................................................................28 13.3 Interrupt vectors ...............................................................................................28 14 I/O Ports .................................................................................................. 30 14.1 Features ..........................................................................................................30 14.2 Overview ..........................................................................................................30 14.3 Output Driver ...................................................................................................31 14.4 Input sensing ...................................................................................................33 14.5 Alternate Port Functions ..................................................................................33 15 TC0/1 - 16-bit Timer/Counter Type 0 and 1 ......................................... 34 15.1 Features ..........................................................................................................34 15.2 Overview ..........................................................................................................34 16 TC2 - Timer/Counter Type 2 .................................................................. 36 16.1 Features ..........................................................................................................36 16.2 Overview ..........................................................................................................36 ii 8135L-AVR-06/12 XMEGA D4 17 AWeX - Advanced Waveform Extension ............................................. 37 17.1 Features ..........................................................................................................37 17.2 Overview ..........................................................................................................37 18 Hi-Res - High Resolution Extension .................................................... 38 18.1 Features ..........................................................................................................38 18.2 Overview ..........................................................................................................38 19 RTC - 16-bit Real-Time Counter ........................................................... 39 19.1 Features ..........................................................................................................39 19.2 Overview ..........................................................................................................39 20 TWI - Two-Wire Interface ...................................................................... 40 20.1 Features ..........................................................................................................40 20.2 Overview ..........................................................................................................40 21 SPI - Serial Peripheral Interface ........................................................... 42 21.1 Features ..........................................................................................................42 21.2 Overview ..........................................................................................................42 22 USART ..................................................................................................... 43 22.1 Features ..........................................................................................................43 22.2 Overview ..........................................................................................................43 23 IRCOM - IR Communication Module .................................................... 44 23.1 Features ..........................................................................................................44 23.2 Overview ..........................................................................................................44 24 CRC - Cyclic Redundancy Check Generator ...................................... 45 24.1 Features ..........................................................................................................45 24.2 Overview ..........................................................................................................45 25 ADC - 12-bit Analog to Digital Converter ............................................ 46 25.1 Features ..........................................................................................................46 25.2 Overview ..........................................................................................................46 26 AC - Analog Comparator ...................................................................... 48 26.1 Features ..........................................................................................................48 26.2 Overview ..........................................................................................................48 27 Programming and Debugging .............................................................. 50 27.1 Features ..........................................................................................................50 27.2 Overview ..........................................................................................................50 iii 8135L-AVR-06/12 XMEGA D4 28 Pinout and Pin Functions ...................................................................... 51 28.1 Alternate Pin Function Description ..................................................................51 28.2 Alternate Pin Functions ...................................................................................53 29 Peripheral Module Address Map .......................................................... 56 30 Instruction Set Summary ...................................................................... 57 31 Packaging information .......................................................................... 61 31.1 44A ..................................................................................................................61 31.2 44M1 ................................................................................................................62 31.3 49C2 ................................................................................................................63 32 Electrical Characteristics ...................................................................... 64 32.1 Absolute Maximum Ratings .............................................................................64 32.2 General Operating Ratings ..............................................................................64 32.3 Current consumption .......................................................................................66 32.4 Wake-up time from sleep modes .....................................................................68 32.5 I/O Pin Characteristics .....................................................................................69 32.6 ADC characteristics ........................................................................................70 32.7 Analog Comparator Characteristics .................................................................72 32.8 Bandgap and Internal 1.0V Reference Characteristics ...................................72 32.9 Brownout Detection Characteristics ................................................................73 32.10 External Reset Characteristics ........................................................................73 32.11 Power-on Reset Characteristics ......................................................................73 32.12 Flash and EEPROM Memory Characteristics .................................................74 32.13 Clock and Oscillator Characteristics ................................................................75 32.14 SPI Characteristics ..........................................................................................81 32.15 Two-Wire Interface Characteristics .................................................................83 33 Typical Characteristics .......................................................................... 85 33.1 Current consumption .......................................................................................85 33.2 I/O Pin Characteristics .....................................................................................95 33.3 Analog Comparator Characteristics ...............................................................102 33.4 Internal 1.0V reference Characteristics .........................................................105 33.5 BOD Characteristics ......................................................................................105 33.6 External Reset Characteristics ......................................................................106 33.7 Power-on Reset Characteristics ....................................................................109 33.8 Oscillator Characteristics ...............................................................................110 iv 8135L-AVR-06/12 33.9 Two-Wire Interface characteristics ................................................................117 33.10 PDI characteristics .........................................................................................118 34 Errata ..................................................................................................... 119 34.1 ATxmega16D4, ATxmega32D4 .....................................................................119 35 Datasheet Revision History ................................................................ 128 35.1 8135L - 06/12 ................................................................................................128 35.2 8135K - 06/12 ...............................................................................................128 35.3 8135J - 12/10 ................................................................................................128 35.4 8135I - 10/10 .................................................................................................128 35.5 8135H - 09/10 ...............................................................................................128 35.6 8135G - 08/10 ...............................................................................................129 35.7 8135F - 02/10 ...............................................................................................129 35.8 8135E - 02/10 ...............................................................................................129 35.9 8135D - 12/09 ...............................................................................................129 35.10 8135C - 10/09 ...............................................................................................130 35.11 8135B - 09/09 ...............................................................................................130 35.12 8135A - 03/09 ...............................................................................................130 Table of Contents....................................................................................... i Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: (+1)(408) 441-0311 Fax: (+1)(408) 487-2600 www.atmel.com Atmel Asia Limited Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon HONG KONG Tel: (+852) 2245-6100 Fax: (+852) 2722-1369 Atmel Munich GmbH Business Campus Parkring 4 D-85748 Garching b. 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