General Description
The MAX16016/MAX16020/MAX16021 supervisory cir-
cuits monitor power supplies, provide battery-backup
control, and chip-enable (CE) gating to write protect
memory in microprocessor (µP)-based systems. These
low-power devices improve system reliability by providing
several supervisory functions in a small, single integrated
solution.
The MAX16016/MAX16020/MAX16021 perform four
basic system functions:
1) Provide a µP reset output during VCC supply power-
up, power-down, and brownout conditions.
2) Control VCC to battery-backup switching internally
to maintain data or low-power operation for memo-
ries, real-time clocks (RTCs), and other digital logic
when the main power is removed.
3) Provide memory write protection through internal
chip-enable gating during brownout.
4) Provide a combination of additional supervisory
functions listed in the
Features
section.
The MAX16016/MAX16020/MAX16021 operate from a
1.53V to 5.5V supply voltage and offer fixed reset
thresholds for monitoring 5V, 3.3V, 3V, 2.5V, and 1.8V
systems. Each device is available with either a push-
pull or open-drain reset output.
The MAX16016/MAX16020/MAX16021 are available in
small TDFN/TQFN packages and are fully specified for
an operating temperature range of -40°C to +85°C.
Applications
Main/Backup Power for RTCs, CMOS Memories
Industrial Control
GPS Systems
Set-Top Boxes
Point-of-Sale Equipment
Portable/Battery Equipment
Features
oSystem Monitoring for 5V, 3.3V, 3V, 2.5V, or 1.8V
Power-Supply Voltages
o1.53V to 5.5V Operating Voltage Range
oLow 1.2µA Supply Current (0.25µA in Battery-
Backup Mode)
o145ms (min) Reset Timeout Period
oBattery Freshness Seal
oOn-Board Gating of CE Signals, 1.5ns
Propagation Delay (MAX16020/MAX16021)
oDebounced Manual Reset Input
oWatchdog Timer, 1.2s (typ) Timeout
oPower-Fail Comparator and Low-Line Indicator for
Monitoring Voltages Down to 0.6V
oBattery-On, Battery-OK, and Battery Test
Indicators
oSmall 10-Pin TDFN or 16-Pin TQFN Packages
oUL®-Certified to Conform to IEC 60950-1
MAX16016/MAX16020/MAX16021
Low-Power µP Supervisory Circuits with
Battery-Backup Circuit and Chip-Enable Gating
________________________________________________________________
Maxim Integrated Products
1
TOP VIEW
MAX16020
16
VCC
CEIN
CEOUT
OUT
LL
BATT_TEST
BATTOK
BATTON
5
15
6
TQFN
14
7
13
8
EP
121 +
112
103
94
BATT
MR
PFI
WDI
RESET
GND
PFO
WDO
Pin Configurations
19-4145; Rev 6; 11/11
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Ordering Information continued at end of data sheet.
Pin Configurations continued at end of data sheet.
Selector Guide located at end of data sheet.
Ordering Information
PART TEMP RANGE
PIN-PACKAGE
MAX16016_TB_+T -40°C to +85°C 10 TDFN-EP*
The first placeholder “_” designates all output options. Letter
“L” indicates push-pull outputs and letter “P” indicates open-
drain outputs. The last placeholder “_” designates the reset
threshold (see Table 1).
T = Tape and reel.
+
Denotes a lead(Pb)-free/RoHS-compliant package.
*
EP = Exposed pad.
UL is a registered trademark of Underwriters Laboratories, Inc.
MAX16016/MAX16020/MAX16021
Low-Power µP Supervisory Circuits with
Battery-Backup Circuit and Chip-Enable Gating
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VCC = 1.53V to 5.5V, VBATT = 3V, TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 2)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCC, BATT, OUT, BATT_TEST to GND.....................-0.3V to +6V
RESET, RESET, PFO, BATTOK, WDO, BATTON,
BATT_TEST, LL, (all open-drain) to GND .................-0.3V to +6V
RESET, RESET, BATTOK, WDO, BATTON,
LL (all push-pull) to GND......................-0.3V to (VOUT + 0.3V)
WDI, PFI to GND.......................................-0.3V to (VOUT + 0.3V)
CEIN, CEOUT to GND ..............................-0.3V to (VOUT + 0.3V)
MR to GND .................................................-0.3V to (VCC + 0.3V)
Input Current
VCC Peak Current.................................................................1A
VCC Continuous Current ...............................................250mA
BATT Peak Current .......................................................500mA
BATT Continuous Current ...............................................70mA
Output Current
OUT Short Circuit to GND Duration ....................................10s
RESET, RESET, BATTON ....................................................20mA
Continuous Power Dissipation (TA= +70°C)
10-Pin TDFN (derate 24.4mW/°C above +70°C) .......1951mW
16-Pin TQFN (derate 25mW/°C above +70°C) ..........2000mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow)
TDFN............................................................................+260°C
TQFN............................................................................+240°C
PACKAGE THERMAL CHARACTERISTICS (Note 1)
TDFN
Junction-to Ambient Thermal Resistance (θJA) ...........41°C/W
Junction-to Case Thermal Resistance (θJC) ..................9°C/W
TQFN
Junction-to Ambient Thermal Resistance (θJA) ...........40°C/W
Junction-to Case Thermal Resistance (θJC) ..................6°C/W
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Operating Voltage Range (Note 3) VCC
,
VBATT VCC or VBATT > VTH 0 5.5 V
VCC = 1.62V 1.2 2
VCC = 2.8V 1.9 3
VCC = 3.6V 2.3 3.5
Supply Current ICC VCC > VTH
VCC = 5.5V 3.4 5
µA
Supply Current in
Battery-Backup Mode IBATT VCC = 0V 0.25 0.5 µA
VCC Switchover Threshold Voltage VCC rising, VCC - VBATT 0.1
x VCC V
BATT Switchover Threshold
Voltage VCC falling, VCC < VTH, VCC - VBATT 0mV
BATT Standby Current VCC > VBATT + 0.2V -10 +10 nA
BATT Freshness Leakage Current VBATT = 5.5V 20 nA
VCC = 4.75V, IOUT = 150mA 1.4 4.5
VCC = 3.15V, IOUT = 65mA 1.7 4.5
VCC = 2.35V, IOUT = 25mA 2.1 5.0
VCC to OUT On-Resistance RON
VCC = 1.91V, IOUT = 10mA 2.6 5.5
Ω
VBATT = 4.5V, IOUT = 20mA VBATT - 0.1
Output Voltage in
Battery-Backup Mode VOUT VBATT = 2.5V, IOUT = 20mA VBATT - 0.15 V
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
MAX16016/MAX16020/MAX16021
Low-Power µP Supervisory Circuits with
Battery-Backup Circuit and Chip-Enable Gating
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 1.53V to 5.5V, VBATT = 3V, TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
RESET OUTPUT (RESET, RESET)
Reset Threshold VTH (see Table 1) V
VCC Falling to Reset Delay tRD VCC falling at 10V/ms 20 µs
Reset Timeout Period tRP 145 215 285 ms
VCC ≥ 3.3V, ISINK = 3.2mA, RESET asserted 0.3
VCC ≥ 1.6V, ISINK = 1mA, RESET asserted 0.3RESET Output Low Voltage VOL
VCC ≥ 1.2V, ISINK = 100µA, RESET asserted 0.3
V
RESET Output High Voltage
(Push-Pull Output) VOH VCC = 1.1 x VTH, ISOURCE = 100µA,
RESET deasserted
VOUT
- 0.3 V
RESET Output Leakage Current
(Open-Drain Output) VRESET = 5.5V, RESET deasserted 1 µA
VCC ≥ 3.3V, ISINK = 3.2mA, RESET
deasserted 0.3
RESET Output Low Voltage VOL VCC ≥ 1.8V, ISINK = 1.0mA, RESET
deasserted 0.3
V
RESET Output High Voltage
(Push-Pull Output) VOH VCC = 0.9 x VTH, ISOURCE = 100µA,
RESET asserted
VOUT
- 0.3 V
RESET Output Leakage Current
(Open-Drain Output) VRESET = 5.5V, RESET asserted 1 µA
POWER-FAIL COMPARATOR
PFI, Input Threshold VPFT VIN falling, 1.6V ≤ VCC ≤ 5.5V 0.572 0.590 0.611 V
PFI, Hysteresis VPFT-HYS 30 mV
PFI Input Current VCC = 5.5V -1 +1 µA
VCC ≥ 1.6V, ISINK = 1mA, output asserted 0.3
PFO Output Low Voltage VOL VCC ≥ 1.2V, ISINK = 100µA, output asserted 0.3 V
PFO Output Voltage
High (Push-Pull Output) VOH VCC = 1.1 x VTH, ISOURCE = 100µA, output
asserted
VOUT
- 0.3 V
PFO, Leakage Current
(Open-Drain Output) VPFO = 5.5V, output deasserted 1 µA
PFO, Delay Time VPFT + 100mV to VPFT - 100mV 20 µs
MANUAL RESET (MR)
Input Low Voltage VIL 0.3 x VCC V
Input High Voltage VIH 0.7 x VCC V
Pullup Resistance 20 30 kΩ
Glitch Immunity VCC = 3.3V 100 ns
MR to Reset Delay 120 ns
MAX16016/MAX16020/MAX16021
Low-Power µP Supervisory Circuits with
Battery-Backup Circuit and Chip-Enable Gating
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 1.53V to 5.5V, VBATT = 3V, TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
WATCHDOG TIMER (WDI, WDO)
Watchdog Timeout Period tWD 0.83 1.235 1.64 s
Minimum WDI Input Pulse Width tWDI 320 ns
WDI Input Low Voltage VIL (Note 6) 0.3 x
VCC V
WDI Input High Voltage VIH (Note 6) 0.7 x
VCC V
WDI Input Current (Note 7) VWDI = 0V or 5.5V, time average -1 +1 µA
WDO Output Low Voltage VOL VCC = 5.0V, ISINK = 1mA, WDO asserted 0.3 V
WDO Output High Voltage
(Push-Pull Output) VOH VCC = 1.1 x VTH, ISOURCE = 100µA, WDO
deasserted
VOUT
- 0.3 V
WDO Leakage Current
(Open-Drain Output) VWDO = 5.5V, WDO deasserted 1 µA
BATTERY-ON INDICATOR (BATTON)
Output Low Voltage VOL ISINK = 3.2mA, VBATT = 2.1V 0.3 V
BATTON Leakage Current VBATTON = 5.5V 1 µA
BATTON Output High Voltage VOH VCC = 0.9 x VTH, ISOURCE = 100µA,
BATTON asserted
VOUT
- 0.3 V
Output Short-Circuit Current
(Note 4) Sink current, VCC = 5V 60 mA
CE GATING (CEIN, CEOUT)
CEIN Leakage Current Reset asserted, VCC = 0.9 x VTH or 0V -1 +1 µA
CEIN to CEOUT Resistance Reset not asserted (Note 5) 8 50 Ω
CEOUT Short-Circuit Current Reset asserted, CEOUT = 0,
VCC = 0.9 x VTH 0.75 2 mA
CEIN to CEOUT Propagation
Delay 50Ω source, CLOAD = 50pF, VCC = 4.75V 1.5 7 ns
VCC = 5V, VCC ≥ VBATT, ISOURCE = 100µA 0.8 x
VCC
Output High Voltage
VCC = 0V, VBATT ≥ 2.2V, ISOURCE = 1µA VBATT -
0.1
V
Reset to CEOUT Delay 12 µs
MAX16016/MAX16020/MAX16021
Low-Power µP Supervisory Circuits with
Battery-Backup Circuit and Chip-Enable Gating
_______________________________________________________________________________________ 5
Note 2: All devices are 100% production tested at TA= +25°C and TA= +85°C. Limits to -40°C are guaranteed by design.
Note 3: VBATT can be 0V anytime, or VCC can go down to 0V if VBATT is active (except at startup).
Note 4: Use external current-limit resistor to limit current to 20mA (max).
Note 5: CEIN/CEOUT resistance is tested with VCC = 5V and VCEIN = 0V or 5V.
Note 6: WDI is internally serviced within the watchdog period if WDI is left unconnected.
Note 7: The WDI input current is specified as the average input current when the WDI input is driven high or low. The WDI input is
designed for a three-stated output device with a 10µA maximum leakage current and capable of driving a maximum capaci-
tive load of 200pF. The three-state device must be able to source and sink at least 200µA when active.
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 1.53V to 5.5V, VBATT = 3V, TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
LOW LINE (LL)
Low Line to Reset Threshold
Voltage VCC falling (see Table 2) mV
VCC Falling to LL Delay VCC falling at 10V/ms 20 µs
VCC ≥ 1.6V, ISINK = 1mA, LL asserted 0.3
LL Output Low Voltage VOL VCC ≥ 1.2V, ISINK = 100µA, LL asserted 0.3 V
LL Output High Voltage (Push-
Pull Output) VOH VCC = 0.9 x VTH_LL, ISOURCE = 100µA,
LL deasserted
VOUT -
0.3 V
Output Leakage Current VLL = 5.5V, LL deasserted 1 µA
BATTERY-OK INDICATOR (BATTOK, BATT_TEST)
BATTOK Threshold Inferred internally from BATT 2.508 2.6 2.673 V
BATTOK Output Voltage Low VOL VCC = 1.1 x VTH, ISINK = 1mA, reset
asserted 0.3 V
BATTOK Output High Voltage VOH VCC = 1.1 x VTH, ISOURCE = 100µA,
BATTOK asserted
VOUT -
0.3 V
BATTOK Output Leakage
Current VBATTOK = 5.5V, deasserted 1 µA
BATT_TEST Output Low Voltage VCC = 1.1 x VTH, ISINK = 1mA 0.3 V
Table 1a. Reset Threshold Ranges
(MAX16016)
RESET THRESHOLD RANGES (V)
SUFFIX MIN TYP MAX
L 4.508 4.63 4.906
M 4.264 4.38 4.635
T 2.991 3.08 3.239
S 2.845 2.93 3.080
R 2.549 2.63 2.755
Z 2.243 2.32 2.425
Y 2.117 2.19 2.288
W 1.603 1.67 1.733
V 1.514 1.575 1.639
Table 1b. Reset Threshold Ranges
(MAX16020/MAX16021)
RESET THRESHOLD RANGES (V)
SUFFIX MIN TYP MAX
L 4.520 4.684 4.852
M 4.275 4.428 4.585
T 3.010 3.100 3.190
S 2.862 2.946 3.034
R 2.568 2.640 2.716
Z 2.260 2.323 2.390
Y 2.133 2.192 2.255
W 1.616 1.661 1.710
V 1.528 1.571 1.618
MAX16016/MAX16020/MAX16021
Low-Power µP Supervisory Circuits with
Battery-Backup Circuit and Chip-Enable Gating
6 _______________________________________________________________________________________
VCC SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX16016 toc01
SUPPLY VOLTAGE (V)
ICC (µA)
5.04.54.03.53.02.52.0
1
2
3
4
5
0
1.5 5.5
MAX16020PTEZ+
VCC SUPPLY CURRENT
vs. TEMPERATURE (IOUT = 0mA)
MAX16016 toc02
TEMPERATURE (°C)
ICC (µA)
-15 603510
1
2
3
4
5
6
0
-40 85
MAX16020PTEZ+
BATT SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX16016 toc03
SUPPLY VOLTAGE (V)
IBATT (µA)
5.03.00.5 4.51.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0
0 5.52.01.5 4.03.52.5
MAX16020PTEZ+
VBATT = 2.5V
BATTERY SUPPLY CURRENT
vs. TEMPERATURE (VCC = 0V)
MAX16016 toc04
TEMPERATURE (°C)
IBATT (µA)
-15 603510
0.1
0.2
0.3
0.4
0.5
0
-40 85
VBATT = 3.0V
BATT STANDBY CURRENT
vs. TEMPERATURE
MAX16016 toc05
TEMPERATURE (°C)
BATT STANDBY CURRENT (nA)
-15 603510
-4
0
2
3
5
-5
4
-1
-3
1
-2
-40 85
VCC = 3.2V
VBATT = 3.0V
VCC TO OUT ON-RESISTANCE
vs. SUPPLY VOLTAGE
MAX16016 toc06
SUPPLY VOLTAGE (V)
VCC TO OUT ON-RESISTANCE (Ω)
2.52.0 3.0
1.0
0.5
1.5
2.0
2.5
3.0
3.5
4.0
0
1.5 5.55.03.5 4.54.0
MAX16020PTEZ+
IOUT = 25mA
IOUT = 10mA
Typical Operating Characteristics
(VCC = 5V, VBATT = 0V, TA= +25°C, unless otherwise noted.)
Table 2. Low-Line Threshold Ranges
LOW-LINE THRESHOLD RANGES (V)
SUFFIX
MIN TYP MAX
L 4.627 4.806 4.955
M 4.378 4.543 4.683
T 3.075 3.181 3.274
S2.922 3.023 3.111
R2.620 2.409 2.787
Z2.309 2.383 2.450
Y2.180 2.246 2.311
W1.653 1.704 1.752
V1.563 1.612 1.657
MAX16016/MAX16020/MAX16021
Low-Power µP Supervisory Circuits with
Battery-Backup Circuit and Chip-Enable Gating
_______________________________________________________________________________________
7
NORMALIZED RESET THRESHOLD
vs. TEMPERATURE
MAX16016 toc10
TEMPERATURE (°C)
NORMALIZED RESET THRESHOLD
-15 603510
0.996
1.000
1.002
1.003
1.005
0.996
1.004
0.999
0.997
1.001
0.998
-40 85
MAXIMUM TRANSIENT DURATION
vs. RESET THRESHOLD OVERDRIVE
MAX16016 toc11
RESET THRESHOLD OVERDRIVE (mV)
MAXIMUM TRANSIENT DURATION (µs)
10050 150
100
50
150
200
250
300
350
400
450
500
0
0 400350200 300250
MAX16020PTEZ+
RESET OCCURS ABOVE THE CURVE
RESET TIMEOUT PERIOD
vs. TEMPERATURE
MAX16016 toc12
TEMPERATURE (°C)
RESET TIMEOUT PERIOD (ms)
-15 603510
192
198
200
202
208
210
194
196
204
206
190
-40 85
MAX16020PTEZ+
WATCHDOG TIMEOUT PERIOD
vs. TEMPERATURE
MAX16016 toc13
TEMPERATURE (°C)
WATCHDOG TIMEOUT PERIOD (s)
-15 603510
0.6
0.9
1.0
1.1
1.4
1.5
0.7
0.8
1.2
1.3
0.5
-40 85
PFI THRESHOLD
vs. TEMPERATURE
MAX16016 toc14
TEMPERATURE (°C)
PFI THRESHOLD (V)
-15 603510
0.56
0.59
0.60
0.61
0.64
0.65
0.57
0.58
0.62
0.63
0.55
-40 85
VPFI+
VPFI-
NORMALIZED LL THRESHOLD
vs. TEMPERATURE
MAX16016 toc15
TEMPERATURE (°C)
NORMALIZED LL THRESHOLD
-15 603510
0.996
1.000
1.002
1.003
1.005
0.995
1.004
0.999
0.997
1.001
0.998
-40 85
VCC TO OUT ON-RESISTANCE
vs. TEMPERATURE
MAX16016 toc07
TEMPERATURE (°C)
VCC TO OUT ON-RESISTANCE (Ω)
-15 603510
1
2
3
4
5
0
-40 85
VCC = 3.15V, IOUT = 65mA
BATT TO OUT ON-RESISTANCE
vs. TEMPERATURE (VCC = 0V, IOUT = 20mA)
MAX16016 toc08
TEMPERATURE (°C)
BATT TO OUT ON-RESISTANCE (Ω)
-15 603510
1
2
3
4
5
0
-40 85
VBATT = 4.5V
VBATT = 2.5V
VBATT = 3V
RESET OUTPUT VOLTAGE LOW
vs. SINK CURRENT
MAX16016 toc09
SINK CURRENT (mA)
RESET OUTPUT VOLTAGE LOW (V)
18161412108642
0.1
0.2
0.3
0.4
0.5
0
020
VCC = 3.3V
VCC = 5V
Typical Operating Characteristics (continued)
(VCC = 5V, VBATT = 0V, TA= +25°C, unless otherwise noted.)
MAX16016/MAX16020/MAX16021
Low-Power µP Supervisory Circuits with
Battery-Backup Circuit and Chip-Enable Gating
8 _______________________________________________________________________________________
BATTOK OUTPUT VOLTAGE LOW
vs. SINK CURRENT
MAX16016 toc19
SINK CURRENT (mA)
BATTOK OUTPUT VOLTAGE LOW (V)
18161412108642
0.1
0.2
0.3
0.4
0.5
0
020
VCC = 3.3V
VCC = 5V
MR FALLING TO RESET DELAY
MAX16016 toc20
200ns/div
MR
5V/div
RESET
5V/div
RESET PROPAGATION DELAY
vs. THRESHOLD OVERDRIVE
MAX16016 toc21
THRESHOLD OVERDRIVE (mV)
PROPAGATION DELAY (µs)
35030025020015010050
30
40
10
20
50
60
70
0
0400
MAX16020PTEZ+
CHIP-ENABLE GATING LOCKING OUT
SIGNAL DURING RESET CONDITION
MAX16016 toc22
10µs/div
RESET
5V/div
CEIN
5V/div
CEOUT
5V/div
Typical Operating Characteristics (continued)
(VCC = 5V, VBATT = 0V, TA= +25°C, unless otherwise noted.)
WDO OUTPUT VOLTAGE LOW
vs. SINK CURRENT
MAX16016 toc16
SINK CURRENT (mA)
WDO OUTPUT VOLTAGE LOW (V)
18161412108642
0.1
0.2
0.3
0.4
0.5
0
020
VCC = 3.3V
VCC = 5V
VCC SUPPLY CURRENT
vs. WDI FREQUENCY
MAX16016 toc17
WDI FREQUENCY (kHz)
ICC (µA)
10010
20
50
70
10
60
30
40
0
0 1000
BATTON OUTPUT VOLTAGE LOW
vs. SINK CURRENT
MAX16016 toc18
SINK CURRENT (mA)
BATTON OUTPUT VOLTAGE LOW (V)
18161412108642
0.1
0.2
0.3
0.4
0.5
0
020
VCC = 3.3V
VCC = 5V
MAX16016/MAX16020/MAX16021
Low-Power µP Supervisory Circuits with
Battery-Backup Circuit and Chip-Enable Gating
_______________________________________________________________________________________ 9
Pin Description—MAX16016
PIN NAME FUNCTION
1V
CC Supply Voltage Input. Bypass VCC to GND with a 0.1µF capacitor.
2 BATT
Backup Battery Input. If VCC falls below its reset threshold, and if VBATT > VCC, OUT connects to
BATT. If VCC rises above 1.01 x VBATT, OUT connects to VCC. Bypass BATT to GND with a 0.1µF
capacitor.
3MR
Active-Low Manual Reset Input. RESET asserts when MR is pulled low. RESET remains low for the
duration of reset timeout period after MR transitions from low to high. Connect MR to VCC or leave
unconnected if not used. MR is internally connected to VCC through a 30kΩ pullup resistor.
4 PFI
Power-Fail Comparator Input. Connect PFI to a resistive divider to set the desired PFI threshold. The
PFI input is referenced to an internal VPFT threshold. A VPFT-HYS internal hysteresis provides noise
immunity. The power-fail comparator is powered from OUT.
5 WDI
Watchdog Timer Input. If WDI remains high or low for longer than the watchdog timeout period (tWD),
the internal watchdog timer runs out and a reset pulse is triggered for the reset timeout period. The
internal watchdog clears when reset asserts or whenever WDI sees a rising or falling edge. To
disable the watchdog feature, leave WDI unconnected or three-state the driver connected to WDI.
6 BATTON Acti ve- H i g h Batter y- O n Outp ut. BATTON g oes hi g h w hen i n b atter y- b ackup m od e.
7PFO Active-Low Power-Fail Comparator Output. PFO goes low when VPFI falls below the internal VPFT
threshold and goes high when VPFI rises above VPFT + VPFT-HYS hysteresis.
8 GND Ground
9RESET
Acti ve- Low Reset Outp ut. RESET asser ts w hen V
C C fal l s b el ow the r eset thr eshol d or M R i s p ul l ed l ow .
RESET r em ai ns l ow for the d ur ati on of the r eset ti m eout p er i od after V
C C r i ses ab ove the r eset thr eshol d
and M R g oes hi g h. RESET al so asser ts l ow w hen the i nter nal w atchd og ti m er r uns out.
10 OUT
Switched Output. OUT is connected to VCC when the reset output is not asserted or when VCC is
greater than VBATT. OUT connects to BATT when RESET is asserted and VBATT is greater than VCC.
Bypass OUT to GND with a 0.1µF (min) capacitor.
MAX16016/MAX16020/MAX16021
Low-Power µP Supervisory Circuits with
Battery-Backup Circuit and Chip-Enable Gating
10 ______________________________________________________________________________________
Pin Description—MAX16020/MAX16021
PIN
MAX16020 MAX16021 NAME FUNCTION
1 1 BATT
Backup Battery Input. If VCC falls below its reset threshold, and if VBATT > VCC, OUT
connects to BATT. If VCC rises above 1.01 x VBATT, OUT connects to VCC. Bypass BATT to
GND with a 0.1µF capacitor.
22MR
Active-Low Manual Reset Input. RESET asserts when MR is pulled low. RESET remains low
for the duration of reset timeout period after MR transitions from low to high. Connect MR to
VCC or leave unconnected if not used. MR is internally connected to VCC through a 30kΩ
pullup resistor.
3 3 PFI
Power-Fail Comparator Input. Connect PFI to a resistive divider to set the desired PFI
threshold. The PFI input is referenced to an internal threshold VPFT, VPFT-HYS internal
hysteresis provides noise immunity. The power-fail comparator is powered from OUT.
4 4 WDI
Watchdog Timer Input. If WDI remains high or low for longer than the watchdog timeout
period (tWD), the internal watchdog timer runs out and asserts WDO. The internal watchdog
clears when reset asserts or whenever WDI sees a rising or falling edge. To disable the
watchdog feature, leave WDI unconnected or three-state the driver connected to WDI.
55LL
Active-Low Low-Line Output. LL goes low when VCC falls to 2.5% above the reset threshold
(Table 2). LL provides an early warning of VCC failure before reset asserts. Use this output
to generate a nonmaskable interrupt (NMI) to initiate an orderly shutdown routine when
VCC is falling.
6 — BATT_TEST
Open-Drain Battery-Test Output. Pulses low for 1.3s every 24 hours during the battery
voltage test. If VBATT < 2.6V, BATTOK deasserts low. See Figure 6 for providing additional
load during the battery test.
— 6 RESET
Active-High Reset Output. RESET asserts when VCC falls below the reset threshold or when
MR asserts and stays asserted for the reset timeout period after VCC rises above the reset
threshold and MR deasserts.
7 7 BATTOK Battery-OK Output. BATTOK goes low when the battery voltage falls below the BATTOK
threshold (BATTOK is low when in battery-backup mode).
8 8 BATTON Active-High Battery-On Output. BATTON goes high when in battery-backup mode.
MAX16016/MAX16020/MAX16021
Low-Power µP Supervisory Circuits with
Battery-Backup Circuit and Chip-Enable Gating
______________________________________________________________________________________ 11
Pin Description—MAX16020/MAX16021 (continued)
PIN
MAX16020 MAX16021 NAME FUNCTION
99WDO
Active-Low Watchdog Output. WDO asserts when WDI remains high or low longer than the
watchdog timeout period. WDO returns high on the next WDI transition or when a reset is
asserted.
10 10 PFO Active-Low Power-Fail Comparator Output. PFO goes low when VPFI falls below the internal
0.6V VPFT threshold and goes high when VPFI rises above VPFT + VPFT-HYS hysteresis.
11 11 GND Ground
12 12 RESET
Active-Low Reset Output. RESET asserts when VCC falls below the reset threshold or MR is
pulled low. RESET remains low for the duration of the reset timeout period after VCC rises
above the reset threshold and MR goes high.
13 13 OUT
Switched Output. OUT is connected to VCC when the reset output is not asserted or when
VCC is greater than VBATT. OUT connects to BATT when RESET is asserted and VBATT is
greater than VCC. Bypass OUT to GND with a 0.1µF (min) capacitor.
14 14 CEOUT
Active-Low Chip-Enable Output. CEOUT goes low only when CEIN is low and reset is not
asserted. If CEIN is low when reset is asserted, CEOUT stays low for 12µs (typ) or until
CEIN goes high, whichever occurs first.
15 15 CEIN Chip-Enable Input. The input to CE gating circuitry. Connect to GND or OUT if not used.
16 16 VCC Supply Voltage Input. Bypass VCC to GND with a 0.1µF capacitor.
——EP
Exposed Pad. Internally connected to GND. Connect EP to a large ground plane to aid
heat dissipation. Do not use EP as the only ground connection for the device.
MAX16016/MAX16020/MAX16021
Low-Power µP Supervisory Circuits with
Battery-Backup Circuit and Chip-Enable Gating
12 ______________________________________________________________________________________
MAX16016
BATT
RESET
BATTERY
FRESHNESS SEAL
WATCHDOG
TIMER
REF
OUT
DELAY
VCC
OUT
BATTON
MR
PFI
PFO
CLEAR
WATCHDOG
TRANSITION
DETECTOR
WDI
RESET
GND
100nA
25kΩ
Functional Diagrams
MAX16016/MAX16020/MAX16021
MAX16020
MAX16021
BATT
RESET
BATTERY
FRESHNESS SEAL
WATCHDOG
TIMER
BATTERY TEST
CIRCUIT
DISABLE
CE OUTPUT
CONTROL
REF
OUT
DELAY
LATCH
VCC
OUT
BATTON
MR
PF1 OUT
PFO
CLEAR
WATCHDOG
TRANSITION
DETECTOR
RESET
(RESET)
(MAX16021
ONLY)
WDI
LL
WDO
GND
CEIN CEOUT
BATTOK
BATT_TEST
(MAX16020 ONLY)
100nA
25kΩ
Functional Diagrams (continued)
Low-Power µP Supervisory Circuits with
Battery-Backup Circuit and Chip-Enable Gating
______________________________________________________________________________________ 13
MAX16016/MAX16020/MAX16021
Low-Power µP Supervisory Circuits with
Battery-Backup Circuit and Chip-Enable Gating
14 ______________________________________________________________________________________
Detailed Description
The
Typical Application Circuit
shows a typical connec-
tion using the MAX16020. OUT powers the static ran-
dom-access memory (SRAM). If VCC is greater than the
reset threshold (VTH), or if VCC is lower than VTH, but
higher than VBATT, VCC connects to OUT. If VCC is lower
than VTH and VCC is less than VBATT, BATT connects to
OUT (see the
Functional Diagrams
). In battery-backup
mode, an internal MOSFET connects the backup battery
to OUT. The on-resistance of the MOSFET is a function of
backup-battery voltage and temperature.
Backup-Battery Switchover
In a brownout or power failure, it may be necessary to
preserve the contents of the RAM. With a backup battery
installed at BATT, the MAX16016/MAX16020/MAX16021
automatically switch the RAM to the backup power when
VCC falls. The MAX16016/MAX16020/MAX16021 have a
BATTON output that goes high when in battery-backup
mode. These devices require two conditions before
switching to battery-backup mode:
1) VCC must be below the reset threshold.
2) VCC must be below VBATT.
Table 3 lists the status of the inputs and outputs in bat-
tery-backup mode. The device does not power up if the
only voltage source is on BATT. OUT only powers up
from VCC at startup.
CE Signal Gating
The MAX16020/MAX16021 provide internal gating of
CE signals to prevent erroneous data from being written
to CMOS RAM in the event of a power failure or
brownout. During normal operation, the CE gate is
enabled and passes all CE transitions. When the reset
output asserts, this path becomes disabled, preventing
erroneous data from corrupting the CMOS RAM.
CEOUT is pulled up to OUT through an internal current
source. The 1.5ns propagation delay from CEIN to
CEOUT allows the devices to be used with most µPs
and high-speed DSPs.
During normal operation (reset not asserted), CEIN is
connected to CEOUT through a low on-resistance
transmission gate. If CEIN is high when a reset asserts,
CEOUT remains high regardless of any subsequent
transition on CEIN during the reset event.
If CEIN is low when reset asserts, CEOUT is held low
for 12µs to allow completion of the read/write operation.
After the 12µs delay expires, CEOUT goes high and
stays high regardless of any subsequent transitions on
CEIN during the reset event. When CEOUT is disconnect-
ed from CEIN, CEOUT is actively pulled up to OUT.
The propagation delay through the CE circuitry
depends on both the source impedance of the drive to
CEIN and the capacitive loading at CEOUT. Minimize
the capacitive load at CEOUT to minimize the propaga-
tion delay, and use a low output-impedance driver.
Low-Line Output (
LL
)
The low-line comparator monitors VCC with a threshold
voltage typically 2.5% higher than the reset threshold
(see Table 2). LL asserts prior to a reset condition during
a brownout condition. On power-up, LL deasserts after
the reset output. LL can be used to provide a nonmask-
able interrupt (NMI) to the µP when the voltage begins to
fall to initiate an orderly software shutdown routine.
Manual Reset Input
Many µP-based products require manual reset capability,
allowing the operator, a test technician, or external logic
circuitry to initiate a reset. For the MAX16016/MAX16020/
MAX16021, a logic-low on MR asserts RESET/RESET.
RESET/RESET remains asserted while MR is low. When
MR goes high RESET/RESET deasserts after a minimum
of 145ms (tRP). MR has an internal 30kΩpullup resistor to
VCC. MR can be driven with TTL/CMOS logic levels or
with open-drain/collector outputs. Connect a normally
open momentary switch from MR to GND to create a
manual reset function; external debounce circuitry is not
required. If MR is driven from a long cable or the device is
used in a noisy environment, connect a 0.1µF capacitor
from MR to GND to provide additional noise immunity.
Table 3. Input and Output Status in
Battery-Backup Mode
PIN STATUS
VCC Disconnected from OUT
OUT Connected to BATT
BATT
Connected to OUT. Current drawn from the
battery is less than 0.55µA (at VBATT = 3V,
excluding IOUT) when VCC = 0V.
Asserted
High state (push-pull), high impedance
(open-drain)
BATTOK, LL Low state
CEIN Disconnected from CEOUT
CEOUT Pulled up to VOUT
PFO Not affected
MAX16016/MAX16020/MAX16021
Low-Power µP Supervisory Circuits with
Battery-Backup Circuit and Chip-Enable Gating
______________________________________________________________________________________ 15
Watchdog Timer
Watchdog Input
The watchdog monitors µP activity through the input
WDI. If the µP becomes inactive, either the reset output is
asserted in pulses (MAX16016) or the watchdog output
goes low (MAX16020/MAX16021). To use the watchdog
function, connect WDI to a bus line or µP I/O line. If WDI
remains high or low for longer than the watchdog timeout
period, the internal watchdog timer runs out and RESET
asserts for the reset timeout period (MAX16016) or WDO
goes low (MAX16020/MAX16021). The internal watchdog
timer clears whenever the reset output asserts or the
WDI sees a rising or falling edge within the watchdog
timeout period. The WDI input is designed for a three-
stated output device with a 10µA maximum leakage cur-
rent and the capability of driving a maximum capacitive
load of 200pF. The three-state device must be able to
source and sink at least 200µA when active. Disable the
watchdog timer by leaving WDI unconnected or by
three-stating the driver connected to WDI. The watchdog
timer periodically attempts to pulse WDI to the opposite
logic-level through a 25kΩresistor for 40µs to determine
whether WDI is either unconnected or latched to a logic
state. The watchdog function is also disabled when in
battery-backup mode.
Watchdog Output
WDO remains high if there is a transition or pulse at WDI
during the watchdog-timeout period. WDO goes low if no
transition occurs at WDI during the watchdog timeout
period and remains low until the next transition at WDI or
when a reset is asserted. Connect WDO to MR to gener-
ate a system reset on every watchdog fault. When a
watchdog fault occurs in this mode, WDO goes low,
which pulls MR low, causing a reset pulse to be issued.
As soon as the reset output is asserted, the watchdog
timer clears and WDO returns high. With WDO connect-
ed to MR, a continuous high or low on WDI causes
145ms (min) reset pulses to be issued every 1.235s.
Battery Testing Function/BATTOK
Indicator (MAX16020/MAX16021)
The MAX16020/MAX16021 feature a battery testing
function that works in conjunction with the BATTOK out-
put. The battery voltage is tested for 1.235s after VCC is
applied and once every 24 hours thereafter. During this
test, an internal 100kΩresistor is connected from BATT
to ground and the battery is monitored to ensure that
the battery voltage is above 2.6V. If the battery voltage
is below 2.6V, the BATTOK output deasserts low to indi-
cate a weak battery condition. The MAX16020 has a
BATT_TEST output that pulses high during the battery
voltage test. Connect a resistor and FET as shown in
Figure 6 to provide an additional load during the battery
test. In battery-backup mode, the battery testing function
is disabled and BATTOK goes low.
Battery Freshness Seal Mode
The MAX16016/MAX16020/MAX16021 battery fresh-
ness seal disconnects the backup battery from internal
circuitry and OUT until VCC is applied. This ensures the
backup battery connected to BATT is fresh when the
final product is used for the first time.
The internal freshness seal latch prevents BATT from
powering OUT until VCC has come up for the first time,
setting the latch. When VCC subsequently turns off,
BATT begins to power OUT.
WDI
WDO
tWD tWD
tWD
Figure 1. Watchdog Timing (MAX16016/MAX16020)
MAX16016/MAX16020/MAX16021
Low-Power µP Supervisory Circuits with
Battery-Backup Circuit and Chip-Enable Gating
16 ______________________________________________________________________________________
To reenable the freshness seal:
1) Connect a battery to BATT.
2) Bring VCC to 0V.
3) Drive MR higher than VBATT + 1.2V for at least 3µs.
4) Pull OUT to 0V.
Reset Output
A µP’s reset input starts the µP in a known state. The
µP supervisory circuits assert a reset to prevent code-
execution errors during power-up, power-down, and
brownout conditions. Reset output is guaranteed to be
a logic-low or logic-high depending on the device cho-
sen. RESET or RESET asserts when VCC is below the
reset threshold and remains asserted for at least 145ms
(tRP) after VCC rises above the reset threshold. RESET
or RESET also asserts when MR is low. The MAX16016
watchdog function causes RESET to assert in pulses
following a watchdog timeout. The reset output is avail-
able in both push-pull and open-drain configurations.
Power-Fail Comparator
The MAX16016/MAX16020/MAX16021 offer an under-
voltage comparator that the output PFO goes low when
the voltage at PFI falls below its VPFT threshold.
Common uses for the power-fail comparator include
monitoring the power supply (such as a battery) before
any voltage regulation to provide an early power-fail
warning, so software can conduct an orderly system
shutdown. The power-fail comparator has a typical
input hysteresis of VPFT-HYS and is powered from OUT,
making it independent of the reset circuit. Connect the
PFI input to GND if not used.
Applications Information
Monitoring an Additional Supply
The MAX16016/MAX16020/MAX16021 µP supervisors
can monitor either positive or negative supplies using a
resistive voltage-divider to PFI. PFO can be used to
generate an interrupt to the µP or to trigger a reset
(Figures 2 and 3). To monitor a negative supply, con-
nect the top of the resistive divider to VCC. Connect the
bottom of the resistive divider to the negative voltage to
be monitored.
MAX16016L
MAX16020L
MAX16021L
RESET RESET
PFO
MR
µP
GND
ADDITIONAL SUPPLY RESET VOLTAGE
R1+R2
R2
V2(RESET) = VPFT x (—)
VCC
PFI
0.1µF
V1
R2
R1
V2
Figure 2. Monitoring an Additional Supply by Connecting PFO
to MR
MAX16016
MAX16020
MAX16021
PFO
PFO
GND
R2
R1
VTRIP = VPFT -
—
(5 - VPFT)
VTRIP IS NEGATIVE
VCC
PFI
0.1µF
R2
R1
5V
V-
0
+5V
VTRIP V-
0V
Figure 3. Monitoring a Negative Supply
MAX16016/MAX16020/MAX16021
Low-Power µP Supervisory Circuits with
Battery-Backup Circuit and Chip-Enable Gating
______________________________________________________________________________________ 17
MAX16020L
CE
CEIN
GND
CMOS RAM
VCC BATTON
MR
BATT
0.1µF1µF
CEOUT
OUT
RESET
VCC
ADDRESS
DECODE
µP
A0–A15
RESET
Figure 5. BATTON Driving an External Pass Transistor
Adding Hysteresis to PFI
The power-fail comparators have a typical input hys-
teresis of VPFT-HYS. This is sufficient for most applica-
tions where a power-supply line is being monitored
through an external voltage-divider (see the
Monitoring
an Additional Supply
section). Figure 4 shows how to
add hysteresis to the power-fail comparator. Select the
ratio of R1 and R2 so that PFI sees VPFT when VIN falls
to the desired trip point (VTRIP). Resistor R3 adds hys-
teresis. R3 is typically an order of magnitude greater
than R1 or R2. R3 should be larger than 50kΩto pre-
vent it from loading down PFO. Capacitor C1 adds
additional noise rejection.
Battery-On Indicator (Push-Pull Version)
BATTON goes high when in battery-backup mode. Use
BATTON to indicate battery-switchover status or to sup-
ply base drive to an external pass transistor for higher
current applications (Figure 5).
Operation Without a Backup Power Source
The MAX16016/MAX16020/MAX16021 provide a bat-
tery-backup function. If a backup power source is not
used, connect BATT to GND and OUT to VCC.
MAX16016L
MAX16020L
MAX16021L
PFO
GND
VCC
PFI
0.1µF
R2
R1
R3
C1*
PFO
0
+5V
VLVH
VTRIP VIN
0.1µF
+5V
VIN
TO µP
R1+R2
R2
VTRIP = VPFT x (—)
*OPTIONAL
R1
R3
R1
R2
VH = (VPFT + VPFT-HYS) x (– + – + 1)
VCC - VPFT
R3
VPFT
R2
VL = R1 x (
—
+
—
) + VPFT
WHERE VPFT IS THE POWER-FAIL THRESHOLD VOLTAGE
Figure 4. Adding Hysteresis to the Power-Fail Comparator
MAX16016/MAX16020/MAX16021
Low-Power µP Supervisory Circuits with
Battery-Backup Circuit and Chip-Enable Gating
18 ______________________________________________________________________________________
Replacing the Backup Battery
When VCC is above VTH, the backup power source can
be removed without danger of triggering a reset pulse.
The device does not enter battery-backup mode when
VCC stays above the reset threshold voltage.
Negative-Going VCC Transients
The MAX16016/MAX16020/MAX16021 are relatively
immune to short duration, negative going VCC tran-
sients. Resetting the µP when VCC experiences only
small glitches is usually not desirable. A 0.1µF bypass
capacitor mounted close to VCC provides additional
transient immunity.
MAX16020L
BATT
BATT_TEST
RLOAD
VCC
Figure 6. Adjustable BATT_TEST Load
MAX16016/MAX16020/MAX16021
MAX16021
16
VCC
CEIN
CEOUT
OUT
LL
RESET
BATTOK
BATTON
5
15
6
TQFN
14
7
13
8
EP
121
112
103
94
BATT
MR
PFI
WDI
RESET
GND
PFO
WDO
MAX16016
10
OUT
BATTON
VCC
WDI
1
8
3
TDFN
+
+
7
RESETBATT
9
24
6
5
GND
PFO
MR
PFI
EP
TOP VIEW
Pin Configurations (continued)
MAX16020L
CE
CEIN
GND
RAM
VCC
PFO
BATT
0.1µF
R1
R2
0.1µF
0.1µF
CEOUT
OUT
RESET
ADDRESS
DECODE
RTC
µP
MR
A0–A15
RST
LL NMI
WDI I/O
WDO I/O
SECONDARY
DC VOLTAGE
3.3V
PFI
0.1µF
(MIN)
VCC
Typical Application Circuit
Low-Power µP Supervisory Circuits with
Battery-Backup Circuit and Chip-Enable Gating
______________________________________________________________________________________ 19
MAX16016/MAX16020/MAX16021
Low-Power µP Supervisory Circuits with
Battery-Backup Circuit and Chip-Enable Gating
20 ______________________________________________________________________________________
Selector Guide
PART
ALL LOGIC
OUTPUTS (EXCEPT
BATT_TEST)
MR POWER-FAIL
COMPARATOR
WATCHDOG
TIMER BATTON
LOW-
LINE
OUTPUT
BATTOK/
BATT_TEST/
RESET
CHIP-
ENABLE
MAX16016LTB_ Push-pull √√ WDI √———
MAX16016PTB_ Open-drain √√ WDI √———
MAX16020LTE_ Push-pull √√WDI/WDO √√
BATTOK/
BATT_TEST √
MAX16020PTE_ Open-drain √√WDI/WDO √√
BATTOK/
BATT_TEST √
MAX16021LTE_ Push-pull √√WDI/WDO √√
BATTOK/
RESET √
MAX16021PTE_ Open-drain √√WDI/WDO √√
BATTOK/
RESET √
Ordering Information (continued)
PART TEMP RANGE
PIN-PACKAGE
MAX16020_TE_+T -40°C to +85°C 16 TQFN-EP*
MAX16021_TE_+T -40°C to +85°C 16 TQFN-EP*
The first placeholder “_” designates all output options. Letter
“L” indicates push-pull outputs and letter “P” indicates open-
drain outputs. The last placeholder “_” designates the reset
threshold (see Table 1).
T = Tape and reel.
+
Denotes a lead(Pb)-free/RoHS-compliant package.
*
EP = Exposed pad.
Chip Information
PROCESS: BiCMOS
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
10 TDFN-EP T1033+1 21-0137 90-0093
16 TQFN-EP T1644+4 21-0139 90-0070
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
MAX16016/MAX16020/MAX16021
Low-Power µP Supervisory Circuits with
Battery-Backup Circuit and Chip-Enable Gating
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in
the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________
21
© 2011 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 5/08 Initial release —
1 7/08 Released the MAX16016. Updated Ordering Information, Electrical
Characteristics, Tables 1 and 2, Pin Description, and Detailed Description.
1, 3, 4, 5, 9, 10, 12,
13, 15, 16, 19, 20
2 10/08 Released the MAX16021. 20
3 12/08 Updated Electrical Characteristics, Pin Description, Table 3, and the Power-
Fail Comparator section. 3, 9, 10, 11, 14, 16
4 1/10 Updated Electrical Characteristics.4
5 4/11 Updated Pin Description. 9, 10
6 11/11 Updated Pin Description. 9, 10
Mouser Electronics
Authorized Distributor
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Maxim Integrated:
MAX16016LTBL+T MAX16016LTBM+T MAX16016LTBR+T MAX16016LTBS+T MAX16016LTBT+T
MAX16016LTBV+T MAX16016LTBW+T MAX16016LTBY+T MAX16016LTBZ+T MAX16016PTBL+T
MAX16016PTBM+T MAX16016PTBR+T MAX16016PTBS+T MAX16016PTBT+T MAX16016PTBV+T
MAX16016PTBW+T MAX16016PTBY+T MAX16016PTBZ+T MAX16020LTEL+T MAX16020LTEM+T
MAX16020LTES+T MAX16020LTET+T MAX16020LTEV+T MAX16020LTEW+T MAX16020LTEY+T
MAX16020LTEZ+T MAX16020PTEL+T MAX16020PTEM+T MAX16020PTER+T MAX16020PTES+T
MAX16020PTET+T MAX16020PTEV+T MAX16020PTEW+T MAX16020PTEY+T MAX16020PTEZ+T
MAX16021LTEL+ MAX16021LTEL+T MAX16021LTEM+ MAX16021LTEM+T MAX16021LTER+ MAX16021LTER+T
MAX16021LTES+ MAX16021LTET+ MAX16021LTET+T MAX16021LTEV+ MAX16021LTEV+T MAX16021LTEW+
MAX16021LTEW+T MAX16021LTEY+ MAX16021LTEY+T MAX16021LTEZ+ MAX16021LTEZ+T
MAX16021PTEL+ MAX16021PTEL+T MAX16021PTEM+ MAX16021PTEM+T MAX16021PTER+
MAX16021PTER+T MAX16021PTES+ MAX16021PTES+T MAX16021PTET+ MAX16021PTET+T MAX16021PTEV+
MAX16021PTEV+T MAX16021PTEW+T MAX16021PTEY+ MAX16021PTEY+T MAX16021PTEZ+
MAX16021PTEZ+T MAX16021PTEW+ MAX16020LTET+ MAX16020LTES+ MAX16020LTES MAX16020PTET+