* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
Document Number: MMPF0100
Rev. 17.0, 1/2017
NXP Semiconductors
Data sheet: Advance Information
© NXP Semiconductors N.V. 2017
14 channel configurable power
management integrated circuit
The PF0100 SMARTMOS power management integrated circuit (PMIC)
provides a highly programmable/ configurable architecture, with fully integrated
power devices and minimal external components. With up to six buck
converters, six linear regulators, RTC supply, and coin-cell charger, the
PF0100 can provide power for a complete system, including applications
processors, memory, and system peripherals, in a wide range of applications.
With on-chip one time programmable (OTP) memory, the PF0100 is available
in pre-programmed standard versions, or non-programmed to support custom
programming. The PF0100 is defined to power an entire embedded MCU
platform solution such as i.MX 6 based eReader, IPTV, medical monitoring, and
home/factory automation.
Features:
• Four to six buck converters, depending on configuration
• Single/Dual phase/ parallel options
• DDR termination tracking mode option
• Boost regulator to 5.0 V output
• Six general purpose linear regulators
• Programmable output voltage, sequence, and timing
• OTP (one time programmable) memory for device configuration
• Coin cell charger and RTC supply
• DDR termination reference voltage
• Power control logic with processor interface and event detection
•I
2C control
• Individually programmable ON, OFF, and standby modes
Figure 1. Simplified application diagram
POWER MANAGEMENT
PF0100
Applications:
• Tablets
•IPTV
• eReaders
• Set top boxes
• Industrial control
• Medical monitoring
• Home automation/ alarm/ energy management
EP SUFFIX (E-TYPE)
98ASA00405D
56 QFN 8X8
ES SUFFIX (WF-TYPE)
98ASA00589D
56 QFN 8X8
VGEN3
100 mA
VGEN5
100 mA
Camera
Audio
Codec
Cluster/HUD
External AMP
Microphones
Speakers
Front USB
POD
Rear USB
POD
Rear Seat
Infotaiment
Sensors
i.MX 6X
I2C Communication I2C Communication
PF0100
Control Signals Parallel control/GPIOS
LICELL
Charger
COINCELL Main Supply
2.8 – 4.5 V
VGEN1
100 mA
VGEN2
250 mA
VGEN4
350 mA
VGEN6
200 mA
SWBST
600 mA
SW3A/B
2500 mA
SW1C
2000 mA
SW1A/B
2500 mA
SW2
2000 mA
SW4
1000 mA
GPS
MIPI
uPCIe
SATA - FLASH
NAND - NOR
Interfaces
Processor Core
Voltages
Camera
VREFDDR
DDR Memory DDR MEMORY
INTERFACE
SD-MMC/
NAND Mem.
SATA
HDD
WAM
GPS
MIPI
HDMI
LDVS Display
USB
Ethernet
CAN
2NXP Semiconductors
PF0100
Table of Contents
1 Orderable parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 Internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1 Pinout diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2 Pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4 General product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2.1 Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.3.1 General specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.3.2 Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.2 Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.3.1 Power generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.3.2 Control logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6 Functional block requirements and behaviors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.1 Start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.1.1 Device start-up configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.1.2 One time programmability (OTP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.1.3 OTP prototyping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.1.4 Reading OTP fuses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.1.5 Programming OTP fuses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.2 16 MHz and 32 kHz clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.2.1 Clock adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.3 Bias and references block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.3.1 Internal core voltage references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.3.2 VREFDDR voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.4 Power generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.4.1 Modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.4.2 State machine flow summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.4.3 Power tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.4.4 Buck regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.4.5 Boost regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
6.4.6 LDO regulators description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
6.4.7 VSNVS LDO/switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
6.5 Control interface I2C block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
6.5.1 I2C device ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
6.5.2 I2C operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
6.5.3 Interrupt handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
6.5.4 Interrupt bit summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
6.5.5 Specific registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
6.5.6 Register bitmap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
NXP Semiconductors 3
PF0100
7 Typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
7.1.1 Application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
7.1.2 Bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
7.2 PF0100 layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
7.2.1 General board recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
7.2.2 Component placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
7.2.3 General routing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
7.2.4 Parallel routing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
7.2.5 Switching regulator layout recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
7.3 Thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
7.3.1 Rating data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
7.3.2 Estimation of junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
8 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
8.1 Packaging dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
9 Reference section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
9.1 Reference documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
4NXP Semiconductors
PF0100
ORDERABLE PARTS
1 Orderable parts
The PF0100 is available with both pre-programmed and non-programmed OTP memory configurations. The non-programmed device uses
“NP” as the programming code. The pre-programmed devices are identified using the program codes from Table 1, which also list the
associated NXP reference designs where applicable. Details of the OTP programming for each device can be found in Table 10.
Table 1. Orderable Part Variations
Part Number Temperature (TA)Package Programming Reference Designs Notes
MMPF0100NPAEP
-40 °C to 85 °C
(for use in consumer
applications)
56 QFN 8x8 mm - 0.5 mm pitch
E-Type QFN (full lead)
NP N/A
(1), (2)
MMPF0100F0AEP F0
MCIMX6Q-SDP
MCIMX6Q-SDB
MCIMX6DL-SDP
MMPF0100F1AEP F1 MCIMX6SLEVK
(1), (2), (3)
MMPF0100F2AEP F2 N/A
MMPF0100F3AEP F3 N/A
(1), (2)
MMPF0100F4AEP F4 N/A
MMPF0100F6AEP F6 MCIMX6SX-SDB
MMPF0100FCAEP FC N/A
(1), (2)
MMPF0100FDAEP FD MCIMX6SLLEVK
MMPF0100NPANES
-40 °C to 105 °C
(for use in extended
industrial applications)
56 QFN 8x8 mm - 0.5 mm pitch
WF-Type QFN (wettable flank)
NP N/A (1), (2), (4)
MMPF0100F0ANES F0
MCIMX6Q-SDP
MCIMX6Q-SDB
MCIMX6DL-SDP
(1), (2)
MMPF0100F3ANES F3 N/A
MMPF0100F4ANES F4 N/A
MMPF0100F6ANES F6 MCIMX6SX-SDB
MMPF0100F9ANES F9 N/A
(1), (2), (4)
MMPF0100FAANES FA N/A
MMPF0100FBANES FB N/A
MMPF0100FCANES FC N/A (1), (2)
Notes
1. For tape and reel, add an R2 suffix to the part number.
2. For programming details see Table 10. The available OTP options are not restricted to the listed reference designs. They can be used in any
application where the listed voltage and sequence details are acceptable.
3. For designs using the i.MX 6SoloLite, it is recommended to use the F3 OTP option instead of the F1 OTP option and F4 OTP option instead of
the F2 OTP option.
4. SW2 can support an output current rating of 2.5 A in NP, F9, and FA Industrial versions only (ANES suffix) when SW2ILIM=0
NXP Semiconductors 5
PF0100
ORDERABLE PARTS
1.1 PF0100 version differences
PF0100A is an improved version of the PF0100 power management IC. Table 2 summarizes the difference between the two versions and
should be referred to when migrating from the PF0100 to the PF0100A. Note that programming options are the same for both versions of
the device.
In addition to the version differences, Table 3 shows the differences on the test temperature rating for each version of PF0100 covered
on this datasheet.
Table 2. Differences between PF0100 and PF0100A
Description PF0100 PF0100A
Version identification
Reading SILICON REV register at address 0x03
returns 0x11. DEVICEID register at address 0x00
reads 0x10 in PF0100 and PF0100A
Reading SILICON REV register at address 0x03
returns 0x21. DEVICEID register at address 0x00
reads 0x10 in PF0100 and PF0100A
VSNVS current limit VSNVS current limit increased in the PF0100A
OTP_FUSE_PORx register setting during OTP
programming
In the PF0100, FUSE_POR1, FUSE_POR2, and
FUSE_POR3 bits are XOR’ed into the
FUSE_POR_XOR bit. The FUSE_POR_XOR bit
has to be 1 for fuses to be loaded during startup.
This can be achieved by setting any one or all of the
FUSE_PORx bits during OTP programming.
In the PF0100A, the XOR function is removed. It is
required to set FUSE_POR1, FUSE_POR2, and
FUSE_POR3 bits during OTP programming.
Erratum ER19
Erratum ER19 applicable to PF0100. Applications
expecting to operate in the conditions mentioned in
ER19 need to implement an external workaround to
overcome the problem. Refer to the product errata
for details
Errata ER19 fixed in PF0100A. External
workaround not required
Erratum ER20 Erratum ER20 applicable to PF0100 Errata ER20 fixed in PF0100A
Erratum ER22 Erratum ER22 applicable to PF0100 Errata ER22 fixed in PF0100A. Workaround not
required
Table 3. Ambient temperature range
Device Qualification tier Ambient temperature range
(TMIN to TMAX)
MMPF0100 Consumer and Industrial TA = -40 °C to 85 °C
MMPF0100A Consumer TA = -40 °C to 85 °C
MMPF0100AN Extended Industrial TA = -40 °C to 105 °C
6NXP Semiconductors
PF0100
INTERNAL BLOCK DIAGRAM
2 Internal block diagram
Figure 2. Simplified internal block diagram
VIN
INTB
LICELL
SWBSTFB
SWBSTIN
SWBSTLX
O/P
Drive
SWBST
600 mA
Boost
PWRON
STANDBY
ICTEST
SCL
SDA
VDDIO
SW3A/B
Single/Dual
DDR
2500 mA
Buck
VCOREDIG
VCOREREF
SDWNB
GNDREF
SW1CFB
SW1AIN
SW1C
2000 mA
Buck
SW1FB
SW1ALX
SW1BLX
SW1A/B
Single/Dual
2500 mA
Buck
SW1VSSSNS
VSNVS
VSNVS
Li Cell
Charger
RESETBMCU
SW2
2000 mA
Buck
VGEN1
100 mA
VGEN1
VIN1
VGEN2
250 mA
VGEN2
VGEN3
100 mA
VGEN3
VIN2
VGEN4
350 mA
VGEN4
VGEN5
100 mA
VGEN5
VIN3
VGEN6
200 mA
VGEN6
Best
of
Supply
OTP
SW4
1000 mA
Buck
VREFDDR
VDDOTP
VINREFDDR
VHALF
VCORE
PF0100
CONTROL
Clocks
32 kHz and 16 MHz
Initialization State Machine
I2C
Interface
Clocks and
resets
I2C Register
map
Trim-In-Package
O/P
Drive
O/P
Drive SW1BIN
SW1CLX
O/P
Drive SW1CIN
SW2FB
SW2LX
O/P
Drive SW2IN
SW2IN
SW3AIN
SW3AFB
SW3ALX
SW3BLX
O/P
Drive
O/P
Drive SW3BIN
SW3BFB
SW3VSSSNS
SW4IN
SW4FB
SW4LX
O/P
Drive
Supplies
Control
DVS Control
DVS CONTROL
Reference
Generation
Core Control logic
GNDREF1
NXP Semiconductors 7
PF0100
PIN CONNECTIONS
3 Pin connections
3.1 Pinout diagram
Figure 3. Pinout diagram
1
2
3
4
5
6
7
8
9
10
11
12
13
14
4344454647484950515253545556
42
41
40
39
38
37
36
35
34
33
32
31
30
29
2827262524232221201918171615
INTB
SDWNB
RESETBMCU
STANDBY
ICTEST
SW1FB
SW1AIN
SW1ALX
SW1BLX
SW1BIN
SW1CLX
SW1CIN
SW1CFB
SW1VSSSNS
LICELL
VGEN6
VIN3
VGEN5
SW3AFB
SW3AIN
SW3ALX
SW3BLX
SW3BIN
SW3BFB
SW3VSSSNS
VREFDDR
VINREFDDR
VHALF
PWRON
VDDIO
SCL
SDA
VCOREREF
VCOREDIG
VIN
VCORE
GNDREF
VDDOTP
SWBSTLX
SWBSTIN
SWBSTFB
VSNVS
GNDREF1
VGEN1
VIN1
VGEN2
SW4FB
SW4IN
SW4LX
SW2LX
SW2IN
SW2IN
SW2FB
VGEN3
VIN2
VGEN4
EP
8NXP Semiconductors
PF0100
PIN CONNECTIONS
3.2 Pin definitions
Table 4. PF0100 pin definitions
Pin number Pin name Pin
function Max rating Type Definition
1 INTB O 3.6 V Digital Open drain interrupt signal to processor
2 SDWNB O 3.6 V Digital Open drain signal to indicate an imminent system shutdown
3 RESETBMCU O 3.6 V Digital Open drain reset output to processor. Alternatively can be used as a power
good output.
4 STANDBY I 3.6 V Digital Standby input signal from processor
5 ICTEST I 7.5 V Digital/
Analog Reserved pin. Connect to GND in application.
6SW1FB
(6) I 3.6 V Analog Output voltage feedback for SW1A/B. Route this trace separately from the
high current path and terminate at the output capacitance.
7SW1AIN
(6) I 4.8 V Analog Input to SW1A regulator. Bypass with at least a 4.7 μF ceramic capacitor
and a 0.1 μF decoupling capacitor as close to the pin as possible.
8 SW1ALX (6) O 4.8 V Analog Regulator 1A switch node connection
9 SW1BLX (6) O 4.8 V Analog Regulator 1B switch node connection
10 SW1BIN (6) I 4.8 V Analog Input to SW1B regulator. Bypass with at least a 4.7 μF ceramic capacitor
and a 0.1 μF decoupling capacitor as close to the pin as possible.
11 SW1CLX (6) O 4.8 V Analog Regulator 1C switch node connection
12 SW1CIN (6) I 4.8 V Analog Input to SW1C regulator. Bypass with at least a 4.7 μF ceramic capacitor
and a 0.1 μF decoupling capacitor as close to the pin as possible.
13 SW1CFB (6) I 3.6V Analog Output voltage feedback for SW1C. Route this trace separately from the
high current path and terminate at the output capacitance.
14 SW1VSSSNS GND - GND Ground reference for regulators SW1ABC. It is connected externally to
GNDREF through a board ground plane.
15 GNDREF1 GND - GND Ground reference for regulators SW2 and SW4. It is connected externally to
GNDREF, via board ground plane.
16 VGEN1 O 2.5 V Analog VGEN1 regulator output, Bypass with a 2.2 μF ceramic output capacitor.
17 VIN1 I 3.6 V Analog VGEN1, 2 input supply. Bypass with a 1.0 μF decoupling capacitor as close
to the pin as possible.
18 VGEN2 O 2.5 V Analog VGEN2 regulator output, Bypass with a 4.7 μF ceramic output capacitor.
19 SW4FB (6) I 3.6 V Analog Output voltage feedback for SW4. Route this trace separately from the high
current path and terminate at the output capacitance.
20 SW4IN (6) I 4.8 V Analog Input to SW4 regulator. Bypass with at least a 4.7μF ceramic capacitor and
a 0.1 μF decoupling capacitor as close to the pin as possible.
21 SW4LX (6) O 4.8 V Analog Regulator 4 switch node connection
22 SW2LX (6) O 4.8 V Analog Regulator 2 switch node connection
23 SW2IN (6) I 4.8 V Analog Input to SW2 regulator. Connect pin 23 together with pin 24 and bypass with
at least a 4.7 μF ceramic capacitor and a 0.1 μF decoupling capacitor as
close to these pins as possible.
24 SW2IN (6) I 4.8 V Analog
25 SW2FB (6) I 3.6 V Analog Output voltage feedback for SW2. Route this trace separately from the high
current path and terminate at the output capacitance.
26 VGEN3 O 3.6 V Analog VGEN3 regulator output. Bypass with a 2.2 μF ceramic output capacitor.
27 VIN2 I 3.6 V Analog VGEN3,4 input. Bypass with a 1.0 μF decoupling capacitor as close to the
pin as possible.
28 VGEN4 O 3.6 V Analog VGEN4 regulator output, Bypass with a 4.7 μF ceramic output capacitor.
NXP Semiconductors 9
PF0100
PIN CONNECTIONS
29 VHALF I 3.6 V Analog Half supply reference for VREFDDR
30 VINREFDDR I 3.6 V Analog VREFDDR regulator input. Bypass with at least 1.0 μF decoupling capacitor
as close to the pin as possible.
31 VREFDDR O 3.6 V Analog VREFDDR regulator output
32 SW3VSSSNS GND - GND Ground reference for the SW3 regulator. Connect to GNDREF externally via
the board ground plane.
33 SW3BFB (6) I 3.6 V Analog Output voltage feedback for SW3B. Route this trace separately from the high
current path and terminate at the output capacitance.
34 SW3BIN (6) I 4.8 V Analog Input to SW3B regulator. Bypass with at least a 4.7 μF ceramic capacitor
and a 0.1 μF decoupling capacitor as close to the pin as possible.
35 SW3BLX (6) O 4.8 V Analog Regulator 3B switch node connection
36 SW3ALX (6) O 4.8 V Analog Regulator 3A switch node connection
37 SW3AIN (6) I 4.8 V Analog Input to SW3A regulator. Bypass with at least a 4.7 μF ceramic capacitor
and a 0.1 μF decoupling capacitor as close to the pin as possible.
38 SW3AFB (6) I 3.6 V Analog Output voltage feedback for SW3A. Route this trace separately from the high
current path and terminate at the output capacitance.
39 VGEN5 O 3.6 V Analog VGEN5 regulator output. Bypass with a 2.2 μF ceramic output capacitor.
40 VIN3 I 4.8 V Analog VGEN5, 6 input. Bypass with a 1.0 μF decoupling capacitor as close to the
pin as possible.
41 VGEN6 O 3.6 V Analog VGEN6 regulator output. By pass with a 2.2 μF ceramic output capacitor.
42 LICELL I/O 3.6 V Analog Coin cell supply input/output
43 VSNVS O 3.6 V Analog LDO or coin cell output to processor
44 SWBSTFB (6) I 5.5 V Analog Boost regulator feedback. Connect this pin to the output rail close to the
load. Keep this trace away from other noisy traces and planes.
45 SWBSTIN (6) I 4.8 V Analog Input to SWBST regulator. Bypass with at least a 2.2 μF ceramic capacitor
and a 0.1 μF decoupling capacitor as close to the pin as possible.
46 SWBSTLX (6) O 7.5 V Analog SWBST switch node connection
47 VDDOTP I 10 V(5) Digital and
Analog Supply to program OTP fuses
48 GNDREF GND - GND Ground reference for the main band gap regulator.
49 VCORE O 3.6 V Analog Analog Core supply
50 VIN I 4.8 V Analog Main chip supply
51 VCOREDIG O 1.5 V Analog Digital Core supply
52 VCOREREF O 1.5 V Analog Main band gap reference
53 SDA I/O 3.6 V Digital I2C data line (Open drain)
54 SCL I 3.6 V Digital I2C clock
55 VDDIO I 3.6 V Analog Supply for I2C bus. Bypass with 0.1 μF ceramic capacitor
56 PWRON I 3.6 V Digital Power On/off from processor
- EP GND - GND
Expose pad. Functions as ground return for buck regulators. Tie this pad to
the inner and external ground planes through vias to allow effective thermal
dissipation.
Notes
5. 10 V Maximum voltage rating during OTP fuse programming. 7.5 V Maximum DC voltage rated otherwise.
6. Unused switching regulators should be connected as follow: Pins SWxLX and SWxFB should be unconnected and Pin SWxIN should be
connected to VIN with a 0.1 μF bypass capacitor.
Table 4. PF0100 pin definitions (continued)
Pin number Pin name Pin
function Max rating Type Definition
10 NXP Semiconductors
PF0100
GENERAL PRODUCT CHARACTERISTICS
4 General product characteristics
4.1 Absolute maximum ratings
Table 5. Absolute maximum ratings
All voltages are with respect to ground, unless otherwise noted. Exceeding these ratings may cause malfunction or permanent damage
to the device. The detailed maximum voltage rating per pin can be found in the pin list section.
Symbol Description Value Unit Notes
Electrical ratings
VIN Main input supply voltage -0.3 to 4.8 V
VDDOTP OTP programming input supply voltage -0.3 to 10 V
VLICELL Coin cell voltage -0.3 to 3.6 V
VESD
ESD ratings
Human body model
Charge device model
±2000
±500
V(7)
Notes
7. ESD testing is performed in accordance with the human body model (HBM) (CZAP = 100 pF, RZAP = 1500 Ω), and the charge device model (CDM),
robotic (CZAP = 4.0 pF).
NXP Semiconductors 11
PF0100
GENERAL PRODUCT CHARACTERISTICS
4.2 Thermal characteristics
4.2.1 Power dissipation
During operation, the temperature of the die should not exceed the operating junction temperature noted in Table 6. To optimize the
thermal management and to avoid overheating, the PF0100 provides thermal protection. An internal comparator monitors the die
temperature. Interrupts THERM110I, THERM120I, THERM125I, and THERM130I are generated when the respective thresholds specified
in Table 7 are crossed in either direction. The temperature range can be determined by reading the THERMxxxS bits in register
INTSENSE0.
In the event of excessive power dissipation, thermal protection circuitry shuts down the PF0100. This thermal protection acts above the
thermal protection threshold listed in Table 7. To avoid any unwanted power downs resulting from internal noise, the protection is
debounced for 8.0 ms. This protection should be considered as a fail-safe mechanism and therefore the system should be configured so
protection is not tripped under normal conditions.
Table 6. Thermal ratings
Symbol Description (rating) Min. Max. Unit Notes
Thermal ratings
TA
Ambient operating temperature range
• PF0100
• PF0100A
• PF0100AN
-40
-40
-40
85
85
105
°C
TJOperating junction temperature range -40 125 °C(8)
TST Storage temperature range -65 150 °C
TPPRT Peak package reflow temperature – Note 10 °C(9)(10)
QFN56 thermal resistance and package dissipation ratings
RθJA
Junction to ambient
• Natural convection
• Four layer board (2s2p)
• Eight layer board (2s6p)
–
–
28
15
°C/W (11)(12)(13)
RθJMA
Junction to ambient (@200 ft/min)
• Four layer board (2s2p) – 22 °C/W (11)(13)
RθJB Junction to board – 10 °C/W (14)
RΘJCBOTTOM Junction to case bottom – 1.2 °C/W (15)
ΨJT Junction to package top
• Natural convection – 2.0 °C/W (16)
Notes
8. Do not operate beyond 125 °C for extended periods of time. Operation above 150 °C may cause permanent damage to the IC. See Table 7 for
thermal protection features.
9. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause a
malfunction or permanent damage to the device.
10. NXP’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and
Moisture Sensitivity Levels (MSL), go to www.nxp.com, search by part number (remove prefixes/suffixes) and enter the core ID to view all orderable
parts, and review parametrics.
11. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient
temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
12. The Board uses the JEDEC specifications for thermal testing (and simulation) JESD51-7 and JESD51-5.
13. Per JEDEC JESD51-6 with the board horizontal.
14. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the
board near the package.
15. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1).
16. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-
2. When Greek letter (Ψ) are not available, the thermal characterization parameter is written as Psi-JT.
12 NXP Semiconductors
PF0100
GENERAL PRODUCT CHARACTERISTICS
4.3 Electrical characteristics
4.3.1 General specifications
Table 7. Thermal protection thresholds
Parameter Min. Typ. Max. Units
Thermal 110 °C Threshold (THERM110) 100 110 120 °C
Thermal 120 °C Threshold (THERM120) 110 120 130 °C
Thermal 125 °C Threshold (THERM125) 115 125 135 °C
Thermal 130 °C Threshold (THERM130) 120 130 140 °C
Thermal Warning Hysteresis 2.0 – 4.0 °C
Thermal Protection Threshold 130 140 150 °C
Table 8. General PMIC static characteristics.
TMIN to TMAX (See Table 3), VIN = 2.8 to 4.5 V, VDDIO = 1.7 to 3.6 V, typical external component values and full load current range, unless
otherwise noted.
Pin name Parameter Load condition Min. Max. Unit
PWRON
VIL – 0.0 0.2 * VSNVS V
VIH – 0.8 * VSNVS 3.6 V
RESETBMCU
VOL -2.0 mA 0.0 0.4 V
VOH Open Drain 0.7* VIN VIN V
SCL
VIL – 0.0 0.2 * VDDIO V
VIH – 0.8 * VDDIO 3.6 V
SDA
VIL – 0.0 0.2 * VDDIO V
VIH – 0.8 * VDDIO 3.6 V
VOL -2.0 mA 0.0 0.4 V
VOH Open Drain 0.7*VDDIO VDDIO V
INTB
VOL -2.0 mA 0.0 0.4 V
VOH Open Drain 0.7* VIN VIN V
SDWNB
VOL -2.0 mA 0.0 0.4 V
VOH Open Drain 0.7* VIN VIN V
STANDBY
VIL – 0.0 0.2 * VSNVS V
VIH – 0.8 * VSNVS 3.6 V
VDDOTP
VIL –0.00.3V
VIH –1.11.7V
NXP Semiconductors 13
PF0100
GENERAL PRODUCT CHARACTERISTICS
4.3.2 Current consumption
Table 9. Current consumption summary
TMIN to TMAX (See Table 3), VIN = 3.6 V, VDDIO = 1.7 V to 3.6 V, LICELL = 1.8 V to 3.3 V, VSNVS = 3.0 V, typical external component
values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, VDDIO = 3.3 V, LICELL = 3.0 V, VSNVS = 3.0 V and
25 °C, unless otherwise noted.
Mode PF0100 conditions System conditions Typical MAX Unit Notes
Coin Cell
VSNVS from LICELL
All other blocks off
VIN = 0.0 V
VSNVSVOLT[2:0] = 110
No load on VSNVS 4.0 7.0 μA
(17),(19),
(23)
Off
MMPF0100
VSNVS from VIN or LICELL
Wake-up from PWRON active
32 k RC on
All other blocks off
VIN ≥ UVDET
No load on VSNVS, PMIC able to wake-up 16 21 μA(18),(19)
Off
MMPF0100A
VSNVS from VIN or LICELL
Wake-up from PWRON active
32 k RC on
All other blocks off
VIN ≥ UVDET
No load on VSNVS, PMIC able to wake-up 17 25 μA(18),(19)
Sleep
VSNVS from VIN
Wake-up from PWRON active
Trimmed reference active
SW3A/B PFM
Trimmed 16 MHz RC off
32 k RC on
VREFDDR disabled
No load on VSNVS. DDR memories in self
refresh
122
122
220(22)
250(21)
μA(19)
Standby
MMPF0100
VSNVS from either VIN or LICELL
SW1A/B combined in PFM
SW1C in PFM
SW2 in PFM
SW3A/B combined in PFM
SW4 in PFM
SWBST off
Trimmed 16 MHz RC enabled
Trimmed reference active
VGEN1-6 enabled
VREFDDR enabled
No load on VSNVS. Processor enabled in
low power mode. All rails powered on
except boost (load = 0 mA)
297
297
450 (20)
1000 (22)
μA(19)
Standby
MMPF0100A
VSNVS from either VIN or LICELL
SW1A/B combined in PFM
SW1C in PFM
SW2 in PFM
SW3A/B combined in PFM
SW4 in PFM
SWBST off
Trimmed 16 MHz RC enabled
Trimmed reference active
VGEN1-6 enabled
VREFDDR enabled
No load on VSNVS. Processor enabled in
low power mode. All rails powered on
except boost (load = 0 mA)
297
297
450 (22)
550(21)
μA(19)
Notes
17. Refer to Figure 4 for coin cell mode characteristics over temperature.
18. When VIN is below the UVDET threshold, in the range of 1.8 V ≤ VIN < 2.65 V, the quiescent current increases by 50 μA, typically.
19. For PFM operation, headroom should be 300 mV or greater.
20. From 0 °C to 85 °C
21. From -40 °C to 105 °C, applicable only to extended industrial parts.
22. From -40 °C to 85 °C, applicable to consumer, industrial and extended industrial part numbers.
23. Additional current may be drawn in the coin cell mode when RESETBMCU is pulled up to VSNVS due an internal path from RESETBMCU to VIN.
The additional current is < 30 μA with a pull up resistor of 100 kΩ. The i.MX 6x processors have an internal pull up from the POR_B pin to the
VDD_SNVS_IN pin. For i.MX 6x applications, if additional current in the coin cell mode is not desired, use an external switch to disconnect the
RESETBMCU path when VIN is removed. For non-i.MX 6 applications, pull-up RESETBMCU to a rail off in the coin cell mode.
14 NXP Semiconductors
PF0100
GENERAL PRODUCT CHARACTERISTICS
Figure 4. Coin cell mode current vs temperature
Coin Cell mode current (uA)
Coin cell mode
1
10
100
-40-20 0 20406080
Temperature (oC)
MMPF0100
MMPF0100A
Temperature (°C)
NXP Semiconductors 15
PF0100
GENERAL DESCRIPTION
5 General description
The PF0100 is the power management integrated circuit (PMIC) designed primarily for use with NXP’s i.MX 6 series of application
processors.
5.1 Features
This section summarizes the PF0100 features.
• Input voltage range to PMIC: 2.8 V - 4.5 V
• Buck regulators
• Four to six channel configurable
• SW1A/B/C, 4.5 A (single); 0.3 V to 1.875 V
• SW1A/B, 2.5 A (single/dual); SW1C 2.0 A (independent); 0.3 V to 1.875 V
•SW2, 2.0 A; 0.4 V to 3.3 V (2.5 A; 1.2 V to 3.3 V (24))
• SW3A/B, 2.5 A (single/dual); 0.4 V to 3.3 V
• SW3A, 1.25 A (independent); SW3B, 1.25 A (independent); 0.4 V to 3.3 V
•SW4, 1.0 A; 0.4 V to 3.3 V
• SW4, VTT mode provide DDR termination at 50% of SW3A
• Dynamic voltage scaling
• Modes: PWM, PFM, APS
• Programmable output voltage
• Programmable current limit
• Programmable soft start
• Programmable PWM switching frequency
• Programmable OCP with fault interrupt
• Boost regulator
• SWBST, 5.0 V to 5.15 V, 0.6 A, OTG support
• Modes: PFM and auto
• OCP fault interrupt
•LDOs
• Six user programable LDO
• VGEN1, 0.80 V to 1.55 V, 100 mA
• VGEN2, 0.80 V to 1.55 V, 250 mA
• VGEN3, 1.8 V to 3.3 V, 10 0 mA
• VGEN4, 1.8 V to 3.3 V, 35 0 mA
• VGEN5, 1.8 V to 3.3 V, 10 0 mA
• VGEN6, 1.8 V to 3.3 V, 20 0 mA
•Soft start
• LDO/switch supply
• VSNVS (1.0/1.1/1.2/1.3/1.5/1.8/3.0 V), 400 μA
• DDR memory reference voltage
• VREFDDR, 0.6 V to 0.9 V, 10 mA
•16 MHz internal master clock
• OTP(one time programmable) memory for device configuration
• User programmable start-up sequence and timing
• Battery backed memory including coin cell charger
•I
2C interface
• User programmable standby, sleep, and off modes
Notes
24. SW2 capable of 2.5 A in NP, F9, and FA Industrial versions only (ANES suffix)
16 NXP Semiconductors
PF0100
GENERAL DESCRIPTION
5.2 Functional block diagram
Figure 5. Functional block diagram
5.3 Functional description
5.3.1 Power generation
The PF0100 PMIC features four buck regulators (up to six independent outputs), one boost regulator, six general purpose LDOs, one
switch/LDO combination and a DDR voltage reference to supply voltages for the application processor and peripheral devices.
The number of independent buck regulator outputs can be configured from four to six, thereby providing flexibility to operate with higher
current capability, or to operate as independent outputs for applications requiring more voltage rails with lower current demands. Further,
SW1 and SW3 regulators can be configured as single/dual phase and/or independent converters. One of the buck regulators, SW4, can
also operate as a tracking regulator when used for memory termination. The buck regulators provide the supply to processor cores and
to other low voltage circuits such as IO and memory. Dynamic voltage scaling is provided to allow controlled supply rail adjustments for
the processor cores and/or other circuitry.
Depending on the system power path configuration, the six general purpose LDO regulators can be directly supplied from the main input
supply or from the switching regulators to power peripherals, such as audio, camera, Bluetooth, Wireless LAN, etc. A specific VREFDDR
voltage reference is included to provide accurate reference voltage for DDR memories operating with or without VTT termination. The
VSNVS block behaves as an LDO, or as a bypass switch to supply the SNVS/SRTC circuitry on the i.MX processors; VSNVS may be
powered from VIN, or from a coin cell.
5.3.2 Control logic
The PF0100 PMIC is fully programmable via the I2C interface. Additional communication is provided by direct logic interfacing including
interrupt and reset. Start-up sequence of the device is selected upon the initial OTP configuration explained in the Start-up section, or by
configuring the “Try Before Buy” feature to test different power up sequences before choosing the final OTP configuration.
The PF0100 PMIC has the interfaces for the power buttons and dedicated signaling interfacing with the processor. It also ensures supply
of critical internal logic and other circuits from the coin cell in case of brief interruptions from the main battery. A charger for the coin cell
is included as well.
Logic and control
Switching regulators
SW1A/B/C
(0.3 V to 1.875 V)
Configurable 4.5 A or
2.5 A+2.0 A
Linear regulators
SW2
(0.4 V to 3.3 V, 2.0 A)
SW3A/B
(0.4 V to 3.3 V)
Configurable 2.5 A
or 1.25 A+1.25 A
SW4
(0.4 V to 3.3 V, 1.0 A)
Boost Regulator
(5.0 V to 5.15 V, 600 mA)
USB OTG Supply
VGEN1
(0.8 V to 1.55 V, 100 mA)
VGEN2
(0.8 V to 1.55 V, 250 mA)
VGEN3
(1.8 V to 3.3 V, 100 mA)
VGEN4
(1.8 V to 3.3 V, 350 mA)
VGEN5
(1.8 V to 3.3 V, 100 mA)
VGEN6
(1.8 V to 3.3 V, 200 mA)
Bias & references
Parallel MCU interface Regulator control
VSNVS
(1.0 V to 3.0 V, 400 μA)
RTC supply with coin cell
charger
MMPF0100 functional internal block diagram
I2C communication and registers
Power generation
Fault detection and protection
DDR voltage reference
Current limit
Short-circuit
Internal core voltage reference
Thermal
OTP startup configuration
Sequence and
timing
OTP prototyping
(Try before buy) Voltage
Phasing and
frequency selection
NXP Semiconductors 17
PF0100
GENERAL DESCRIPTION
5.3.2.1 Interface signals
5.3.2.1.1 PWRON
PWRON is an input signal to the IC generating a turn-on event. It can be configured to detect a level, or an edge using the PWRON_CFG
bit. Refer to section 6.4.2.1 Turn on events, page 31 for more details.
5.3.2.1.2 STANDBY
STANDBY is an input signal to the IC. When it is asserted the part enters standby mode and when de-asserted, the part exits standby
mode. STANDBY can be configured as active high or active low using the STANDBYINV bit. Refer to the section 6.4.1.3 Standby mode,
page 29 for more details.
Note: When operating the PMIC at VIN ≤ 2.85 V and VSNVS is programmed for a 3.0 V output, a coin cell must be present to provide
VSNVS, or the PMIC does not reliably enter and exit the STANDBY mode.
5.3.2.1.3 RESETBMCU
RESETBMCU is an open drain, active low output configurable for two modes of operation. In its default mode, it is de-asserted 2.0 ms to
4.0 ms after the last regulator in the start-up sequence is enabled; refer to Figure 6 as an example. In this mode, the signal can be used
to bring the processor out of reset, or as an indicator that all supplies have been enabled; it is only asserted for a turn-off event.
When configured for its fault mode, RESETBMCU is de-asserted after the start-up sequence is completed only if no faults occurred during
start-up. At anytime, if a fault occurs and persists for 1.8 ms typically, RESETBMCU is asserted, LOW. The PF0100 is turned off if the
fault persists for more than 100 ms typically. The PWRON signal restarts the part, though if the fault persists, the sequence described
above is repeated. To enter the fault mode, set bit OTP_PG_EN of register OTP PWRGD EN to “1”. This register, 0xE8, is located on
Table 137 of the register map. To test the fault mode, the bit may be set during TBB prototyping, or the mode may be permanently chosen
by programming OTP fuses.
5.3.2.1.4 SDWNB
SDWNB is an open drain, active low output notifying the processor of an imminent PMIC shut down. It is asserted low for one 32 kHz clock
cycle before powering down and is then de-asserted in the OFF state.
5.3.2.1.5 INTB
INTB is an open drain, active low output. It is asserted when any fault occurs, provided the fault interrupt is unmasked. INTB is de-asserted
after the fault interrupt is cleared by software, which requires writing a “1” to the fault interrupt bit.
18 NXP Semiconductors
PF0100
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6 Functional block requirements and behaviors
6.1 Start-up
The PF0100 can be configured to start-up from either the internal OTP configuration, or with a hard-coded configuration built in to the
device. The internal hard-coded configuration is enabled by connecting the VDDOTP pin to VCOREDIG through a 100 kΩ resistor. The
OTP configuration is enabled by connecting VDDOTP to GND.
For NP devices, selecting the OTP configuration causes the PF0100 to not start-up. However, the PF0100 can be controlled through the
I2C port for prototyping and programming. Once programmed, the NP device starts up with the customer programmed configuration.
6.1.1 Device start-up configuration
Table 10 shows the default configuration, which can be accessed on all devices as described previously, as well as the pre-programmed
OTP configurations.
Table 10. Start-up configuration
Registers
Default
configuration Pre-programmed OTP configuration
All devices F0 F1(25) F2(25) F3 F4 F6 F9 FA FB FC FD
Default I2C Address 0x08 0x08 0x08 0x08 0x08 0x08 0x08 0x08 0x08 0x08 0x08 0x08
VSNVS_VOLT 3.0 V 3.0 V 3.0 V 3.0 V 3.0 V 3.0 V 3.0 V 3.0 V 3.0 V 3.0 V 3.0 V 3.0 V
SW1AB_VOLT 1.375 V 1.375 V 1.375 V 1.375 V 1.375 V 1.375 V 1.375 V 1.375 V 1.375 V 1.375 V 1.375 V 1.2 V
SW1AB_SEQ 1 11122255 2 2 2
SW1C_VOLT 1.375 V 1.375 V 1.375 V 1.375 V 1.375 V 1.375 V 1.375 V 1.375 V 1.375 V 1.375 V 1.375 V 1.2 V
SW1C_SEQ 1 21122255 2 2 2
SW2_VOLT 3.0 V 3.3 V 3.15 V 3.15 V 3.15 V 3.15 V 3.3 V 1.375 V 1.375 V 3.3 V 3.3 V 3.15 V
SW2_SEQ 2 52211455 6 5 1
SW3A_VOLT 1.5 V 1.5 V 1.2 V 1.5 V 1.2 V 1.5 V 1.35 V 1.350 V 1.5 V 1.2 V 1.35 V 1.2 V
SW3A_SEQ 3 34444366 4 3 4
SW3B_VOLT 1.5 V 1.5 V 1.2 V 1.5 V 1.2 V 1.5 V 1.35 V 1.350 V 1.5 V 1.2 V 1.35 V 1.2 V
SW3B_SEQ 3 34444366 4 3 4
SW4_VOLT 1.8 V 3.15 V 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V 1.825 V 1.825 V 1.8 V 3.15 V 1.8 V
SW4_SEQ 3 63333477 3 6 3
SWBST_VOLT - 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V
SWBST_SEQ - 13 6 6 6 6 Off 10 10 Off 13 6
VREFDDR_SEQ 3 3 4 4 4 4 3 6 6 4 3 4
VGEN1_VOLT - 1.5 V 1.2 V 1.2 V 1.2 V 1.2 V 1.2 V 1.2 V 1.2 V 1.5 V 1.5 V 1.2 V
VGEN1_SEQ - 9 4 4 4 4 5 - - 3 9 -
VGEN2_VOLT 1.5 V 1.5 V - - - - 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V
VGEN2_SEQ 2 10 - - - - Off 8 8 Off 10 7
VGEN3_VOLT - 2.5 V - - - - 2.8 V 1.8 V 1.8 V 2.5 V 2.5 V 1.8 V
VGEN3_SEQ - 11 - - - - 5 8 8 Off 11 7
VGEN4_VOLT 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V 3.0 V 3.0 V 1.8 V 1.8V 1.8 V
VGEN4_SEQ 3 7 3 3 3 3 4 4 4 7 7 3
VGEN5_VOLT 2.5 V 2.8 V 2.5 V 2.5 V 2.5 V 2.5 V 3.3 V 2.5 V 2.5 V 2.8 V 2.8 V 2.5 V
NXP Semiconductors 19
PF0100
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
VGEN5_SEQ 3 12 5 5 5 5 5 8 8 1 1 5
VGEN6_VOLT 2.8 V 3.3 V - - - - 3.0 V 2.8 V 2.8 V 3.3 V 3.3 V 2.8 V
VGEN6_SEQ 3 8 - - - - 1 7 7 8 8 7
PU CONFIG,
SEQ_CLK_SPEED 1.0 ms 2.0 ms 1.0 ms 1.0 ms 1.0 ms 1.0 ms 0.5 ms 0.5 ms 0.5 ms 2.0 ms 2.0 ms 1.0 ms
PU CONFIG,
SWDVS_CLK 6.25 mV/μs1.5625 mV
/μs
12.5 mV/
μs
12.5 mV/
μs
12.5 mV/
μs
12.5 mV/
μs
6.25 mV/
μs6.25 mV/μs 6.25 mV/μs1.5625 mV/
μs
1.5625 mV/
μs12.5 mV/μs
PU CONFIG,
PWRON Level sensitive
SW1AB CONFIG SW1AB Single Phase, SW1C Independent Mode, 2.0 MHz SW1ABC Single
Phase, 2.0 MHz
SW1AB Single Phase, SW1C
Independent mode, 2.0 MHz
SW1C CONFIG 2.0 MHz
SW2 CONFIG 2.0 MHz
SW3A CONFIG SW3AB Single Phase, 2.0 MHz
SW3B CONFIG 2.0 MHz
SW4 CONFIG No VTT, 2.0 MHz
PG EN RESETBMCU in default mode
Notes
25. For designs using the i.MX 6SoloLite, it is recommended to use the F3 OTP option instead of the F1 OTP option
and F4 OTP option instead of the F2 OTP option.
Table 10. Start-up configuration (continued)
Registers
Default
configuration Pre-programmed OTP configuration
All devices F0 F1(25) F2(25) F3 F4 F6 F9 FA FB FC FD
20 NXP Semiconductors
PF0100
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Figure 6. Default start-up sequence
Table 11. Default start-up sequence timing
Parameter Description Min. Typ. Max. Unit Notes
tD1 Turn-on delay of VSNVS – 5.0 – ms (26)
tR1 Rise time of VSNVS – 3.0 – ms
tD2 User determined delay – 1.0 – ms
tR2 Rise time of PWRON – (27) –ms
tD3
Turn-on delay of first regulator
• SEQ_CLK_SPEED[1:0] = 00 –2.0–
ms
• SEQ_CLK_SPEED[1:0] = 01 –2.5– (28)
• SEQ_CLK_SPEED[1:0] = 10 –4.0–
• SEQ_CLK_SPEED[1:0] = 11 –7.0–
tR3 Rise time of regulators – 0.2 – ms (29)
*VSNVS starts from 1.0 V if LICELL is valid before VIN.