1
1605fc
LTC1605
TYPICAL APPLICATIO
U
DESCRIPTIO
U
APPLICATIO S
U
FEATURES
16-Bit, 100ksps,
Sampling ADC
The LTC
®
1605 is a 100ksps, sampling 16-bit A/D con-
verter that draws only 55mW (typical) from a single 5V
supply. This easy-to-use device includes sample-and-
hold, precision reference, switched capacitor successive
approximation A/D and trimmed internal clock.
The LTC1605’s input range is an industry standard ±10V.
Maximum DC specs include ±2.0LSB INL and 16-bits no
missing codes over temperature. An external reference
can be used if greater accuracy over temperature is
needed.
The ADC has a microprocessor compatible, 16-bit or two
byte parallel output port. A convert start input and a data
ready signal (BUSY) ease connections to FIFOs, DSPs and
microprocessors.
■
Single 5V Supply
■
Bipolar Input Range:
±
10V
■
Power Dissipation: 55mW Typ
■
Guaranteed No Missing Codes
■
Sample Rate: 100ksps
■
Integral Nonlinearity: ±2.0LSB Max
■
Signal-to-Noise Ratio: 86dB Typ
■
Operates with Internal or External Reference
■
Internal Synchronized Clock
■
Improved 2nd Source to ADS7805 and AD976
■
28-Pin 0.3” PDIP, SSOP and SW Packages
■
Industrial Process Control
■
Multiplexed Data Acquisition Systems
■
High Speed Data Acquisition for PCs
■
Digital Signal Processing
Low Power, 100kHz, 16-Bit Sampling ADC on 5V Supply
4k
20k20k200Ω
REFERENCE
4k 10k
16-BIT
SAMPLING ADC D15 TO D0
33.2k
2.2µF
10µF0.1µF
2.2µF
±10V
INPUT
V
IN
CAP
REF
AGND1
1
4
3
2
AGND2
5
DGND
14
CONTROL
LOGIC AND
TIMING
BUSY
BYTE
CS
R/C
28 27
6 TO 13
15 TO 22
26
25
24
23
DIGITAL
CONTROL
SIGNALS
1605 • TA01
16-BIT
OR 2 BYTE
PARALLEL
BUS
5V
V
DIG
V
ANA
BUFFER
Typical INL Curve
CODE
0
INL (LSBs)
65535
1605 • TA02
16384 32768 49152
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
2
LTC1605
1605fc
A
U
G
W
A
W
U
W
ARBSOLUTEXI T
IS
WU
U
PACKAGE/ORDER I FOR ATIO
(Notes 1, 2)
V
ANA
.......................................................................... 7V
V
DIG
to V
ANA
........................................................... 0.3V
V
DIG
........................................................................... 7V
Ground Voltage Difference
DGND, AGND1 and AGND2 .............................. ±0.3V
Analog Inputs (Note 3)
V
IN
..................................................................... ±25V
CAP ............................ V
ANA
+ 0.3V to AGND2 – 0.3V
REF ....................................Indefinite Short to AGND2
Momentary Short to V
ANA
Digital Input Voltage (Note 4) ........ DGND – 0.3V to 10V
Digital Output Voltage ........ V
DGND
– 0.3V to V
DIG
+ 0.3V
Power Dissipation.............................................. 500mW
Operating Ambient Temperature Range
LTC1605C ............................................... 0°C to 70°C
LTC1605I............................................ – 40°C to 85°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
CONVERTER CHARACTERISTICS
U
LTC1605 LTC1605A
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
Resolution ●16 16 Bits
No Missing Codes ●15 16 Bits
Transition Noise 1.0 1.0 LSB
Integral Linearity Error (Note 7) ●±3±2LSB
Bipolar Zero Error Ext. Reference = 2.5V (Note 8) ●±10 ±10 mV
Bipolar Zero Error Drift ±2±2 ppm/°C
Full-Scale Error Drift ±7±5 ppm/°C
Full-Scale Error Ext. Reference = 2.5V (Notes 12, 13) ●±0.50 ±0.25 %
Full-Scale Error Drift Ext. Reference = 2.5V ±2±2 ppm/°C
Power Supply Sensitivity
V
ANA
= V
DIG
= V
DD
V
DD
= 5V ±5% (Note 9) ±8±8LSB
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. With external reference (Notes 5, 6).
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
ORDER PART NUMBER
Consult LTC Marketing for parts specified with wider operating temperature ranges.
LTC1605ACG
LTC1605ACSW
LTC1605AIG
LTC1605AISW
LTC1605CG
T
JMAX
= 125°C, θ
JA
= 95°C/W (G)
T
JMAX
= 125°C, θ
JA
= 130°C/W (N)
T
JMAX
= 125°C, θ
JA
= 130°C/W (SW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VIN
AGND1
REF
CAP
AGND2
D15 (MSB)
D14
D13
D12
D11
D10
D9
D8
DGND
VDIG
VANA
BUSY
CS
R/C
BYTE
D0
D1
D2
D3
D4
D5
D6
D7
G PACKAGE
28-LEAD PLASTIC SSOP
SW PACKAGE
28-LEAD PLASTIC SO WIDE
N PACKAGE
28-LEAD PDIP
TOP VIEW
LTC1605CN
LTC1605CSW
LTC1605IG
LTC1605IN
LTC1605ISW
3
1605fc
LTC1605
LTC1605/LTC1605A
PARAMETER CONDITIONS MIN TYP MAX UNITS
V
REF
Output Voltage I
OUT
= 0 ●2.470 2.500 2.520 V
V
REF
Output Tempco I
OUT
= 0 ±5 ppm/°C
Internal Reference Source Current 1µA
External Reference Voltage for Specified Linearity (Notes 9, 10) 2.30 2.50 2.70 V
External Reference Current Drain Ext. Reference = 2.5V (Note 9) ●100 µA
CAP Output Voltage I
OUT
= 0 2.50 V
LTC1605/LTC1605A
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
S/(N + D) Signal-to-(Noise + Distortion) Ratio 1kHz Input Signal (Note 14) 87.5 dB
10kHz Input Signal 87 dB
20kHz, –60dB Input Signal 30 dB
THD Total Harmonic Distortion 1kHz Input Signal, First 5 Harmonics – 102 dB
10kHz Input Signal, First 5 Harmonics – 94 dB
Peak Harmonic or Spurious Noise 1kHz Input Signal –102 dB
10kHz Input Signal – 94 dB
Full-Power Bandwidth (Note 15) 275 kHz
Aperture Delay 40 ns
Aperture Jitter Sufficient to Meet AC Specs
Transient Response Full-Scale Step (Note 9) 2 µs
Overvoltage Recovery (Note 16) 150 ns
(Notes 5, 14)
The ● denotes specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 5)
LTC1605/LTC1605A
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
IN
Analog Input Range (Note 9) 4.75V ≤ V
ANA
≤ 5.25V, 4.75V ≤ V
DIG
≤ 5.25V ●±10 V
C
IN
Analog Input Capacitance 10 pF
R
IN
Analog Input Impedance 20 kΩ
ANALOG INPUT
UU
DYNAMIC ACCURACY
UW
INTERNAL REFERENCE CHARACTERISTICS
UU U
DIGITAL INPUTS AND DIGITAL OUTPUTS
UU
The ● denotes specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
The ● denotes specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
LTC1605/LTC1605A
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
IH
High Level Input Voltage V
DD
= 5.25V ●2.4 V
V
IL
Low Level Input Voltage V
DD
= 4.75V ●0.8 V
I
IN
Digital Input Current V
IN
= 0V to V
DD
●±10 µA
C
IN
Digital Input Capacitance 5pF
V
OH
High Level Output Voltage V
DD
= 4.75V I
O
= –10µA 4.5 V
I
O
= – 200µA●4.0 V
4
LTC1605
1605fc
LTC1605/LTC1605A
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
DD
Positive Supply Voltage (Notes 9, 10) 4.75 5.25 V
I
DD
Positive Supply Current ●11 16 mA
P
DIS
Power Dissipation 55 80 mW
LTC1605/LTC1605A
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
OL
Low Level Output Voltage V
DD
= 4.75V I
O
= 160µA 0.05 V
I
O
= 1.6mA ●0.10 0.4 V
I
OZ
Hi-Z Output Leakage D15 to D0 V
OUT
= 0V to V
DD
, CS High ●±10 µA
C
OZ
Hi-Z Output Capacitance D15 to D0 CS High (Note 9) ●15 pF
I
SOURCE
Output Source Current V
OUT
= 0V –10 mA
I
SINK
Output Sink Current V
OUT
= V
DD
10 mA
DIGITAL INPUTS AND DIGITAL OUTPUTS
UU
LTC1605/LTC1605A
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
f
SAMPLE(MAX)
Maximum Sampling Frequency ●100 kHz
t
CONV
Conversion Time ●8µs
t
ACQ
Acquisition Time ●2µs
t
1
Convert Pulse Width (Note 11) ●40 ns
t
2
Data Valid Delay After R/C↓(Note 9) ●8µs
t
3
BUSY Delay from R/C↓C
L
= 50pF ●65 ns
t
4
BUSY Low 8µs
t
5
BUSY Delay After End of Conversion 220 ns
t
6
Aperture Delay 40 ns
t
7
Bus Relinquish Time ●10 35 83 ns
t
8
BUSY Delay After Data Valid ●50 200 ns
t
9
Previous Data Valid After R/C↓7.4 µs
t
10
R/C to CS Setup Time (Notes 9, 10) 10 ns
t
11
Time Between Conversions 10 µs
t
12
Bus Access and Byte Delay (Notes 9, 10) 10 83 ns
TIMING CHARACTERISTICS
WU
POWER REQUIREMENTS
WU
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground with DGND, AGND1
and AGND2 wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below ground or above V
ANA
=
V
DIG
= V
DD
, they will be clamped by internal diodes. This product can
handle input currents of greater than 100mA below ground or above V
DD
without latch-up.
Note 4: When these pin voltages are taken below ground, they will be
clamped by internal diodes. This product can handle input currents of
90mA below ground without latchup. These pins are not clamped to V
DD
.
Note 5: V
DD
= 5V, f
SAMPLE
= 100kHz, t
r
= t
f
= 5ns unless otherwise
specified.
Note 6: Linearity, offset and full-scale specifications apply for a V
IN
input
with respect to ground.
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual end points of the transfer curve.
The deviation is measured from the center of the quantization band.
The ● denotes specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
The ● denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
The ● denotes specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. (Note 5)
5
1605fc
LTC1605
ELECTRICAL CHARACTERISTICS
Note 8: Bipolar offset is the offset voltage measured from –0.5 LSB when
the output code flickers between 0000 0000 0000 0000 and 1111 1111
1111 1111.
Note 9: Guaranteed by design, not subject to test.
Note 10: Recommended operating conditions.
Note 11: With CS low the falling R/C edge starts a conversion. If R/C
returns high at a critical point during the conversion it can create small
errors. For best results ensure that R/C returns high within 3µs after the
start of the conversion.
Note 12: As measured with fixed resistors shown in Figure 4. Adjustable to
zero with external potentiometer.
Note 13: Full-scale error is the worst-case of –FS or +FS untrimmed
deviation from ideal first and last code transitions, divided by the transition
voltage (not divided by the full-scale range) and includes the effect of
offset error.
Note 14: All specifications in dB are referred to a full-scale ±10V input.
Note 15: Full-power bandwidth is defined as full-scale input frequency at
which a signal-to-(noise + distortion) degrades to 60dB or 10 bits of
accuracy.
Note 16: Recovers to specified performance after (2 • FS) input
overvoltage.
TYPICAL PERFORMANCE CHARACTERISTICS
UW
Supply Current vs Supply Voltage
Change in CAP Voltage vs
Load Current
SUPPLY VOLTAGE (V)
4.50
9.5
SUPPLY CURRENT (mA)
10.0
10.5
11.0
11.5
12.0
12.5
4.75 5.00 5.25 5.50
1605 • TPC01
f
SAMPLE
= 100kHz
LOAD CURRENT (mA)
–25
CHANGE IN CAP VOLTAGE (mV)
10
30
50
15
1605 TPC03
–10
–30
0
20
40
–20
–40
–50 –15 –5 525
TEMPERATURE (°C)
–50
10.0
POSITIVE SUPPLY CURRENT (mA)
10.5
11.0
11.5
12.0
–25 0 25 50
1605 • TPC02
75 100
f
SAMPLE
= 100kHz
Supply Current vs Temperature
Typical INL Curve
CODE
0
INL (LSBs)
65535
1605 • TPC04
16384 32768 49152
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
CODE
0
DNL (LSBs)
65535
1605 • TPC05
16384 32768 49152
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
Power Supply Feedthrough vs
Ripple FrequencyTypical DNL Curve
RIPPLE FREQUENCY (Hz)
–70
–60
–50
–40
–30
–20
POWER SUPPLY FEEDTHROUGH (dB)
1M
1605 • TPC06
1 10010 1k 100k10k
6
LTC1605
1605fc
TYPICAL PERFORMANCE CHARACTERISTICS
UW
LTC1605 Nonaveraged 4096 Point FFT Plot
FREQUENCY (kHz)
–130
–120
–100
–110
–80
–90
–20
–40
–60
0
–30
–50
–70
–10
MAGNITUDE (dB)
1605 • TPC07
0 5 10 15 20 25 30 35 40 45 50
fSAMPLE = 100kHz
fIN = 1kHz
SINAD = 87.5dB
THD = –101.7dB
SINAD vs Input Frequency
INPUT FREQUENCY (kHz)
1
SINAD (dB)
90
89
88
87
86
85
84
83
82
81
10 100
1605 • TPC08
Total Harmonic Distortion vs
Input Frequency
INPUT FREQUENCY (kHz)
1
TOTAL HARMONIC DISTORTION (dB)
–70
–80
–90
–100
–110
10 100
1605 • TPC09
PIN FUNCTIONS
UUU
V
IN
(Pin 1): Analog Input. Connect through a 200Ω
resistor to the analog input. Full-scale input range is
±10V.
AGND1 (Pin 2): Analog Ground. Tie to analog ground
plane.
REF (Pin 3): 2.5V Reference Output. Bypass with 2.2µF
tantalum capacitor. Can be driven with an external refer-
ence.
CAP (Pin 4): Reference Buffer Output. Bypass with 2.2µF
tantalum capacitor.
AGND2 (Pin 5): Analog Ground. Tie to analog ground
plane.
D15 to D8 (Pins 6 to 13): Three-State Data Outputs.
Hi-Z state when CS is high or when R/C is low.
DGND (Pin 14): Digital Ground.
D7 to D0 (Pins 15 to 22): Three-State Data Outputs.
Hi-Z state when CS is high or when R/C is low.
BYTE (Pin 23): Byte Select. With BYTE low, data will be
output with Pin 6 (D15) being the MSB and Pin 22 (D0)
being the LSB. With BYTE high the upper eight bits and
the lower eight bits will be switched. The MSB is output
7
1605fc
LTC1605
PIN FUNCTIONS
UUU
on Pin 15 and bit 8 is output on Pin 22. Bit 7 is output on
Pin 6 and the LSB is output on Pin 13.
R/C (Pin 24): Read/Convert Input. With CS low, a falling
edge on R/C puts the internal sample-and-hold into the
hold state and starts a conversion. With CS low, a rising
edge on R/C enables the output data bits.
CS (Pin 25): Chip Select. Internally OR’d with R/C. With
R/C low, a falling edge on CS will initiate a conversion.
With R/C high, a falling edge on CS will enable the output
data.
BUSY (Pin 26): Output Shows Converter Status. It is low
when a conversion is in progress. Data valid on the rising
edge of BUSY. CS or R/C must be high when BUSY rises
or another conversion will start without time for signal
acquisition.
V
ANA
(Pin 27): 5V Analog Supply. Bypass to ground with
a 0.1µF ceramic and a 10µF tantalum capacitor.
V
DIG
(Pin 28): 5V Digital Supply. Connect directly to Pin
27.
TEST CIRCUITS
Load Circuit for Access Timing
1k C
L
C
L
DBN DBN
1k
5V
LTC1605 • TC01
A. HI-Z TO V
OH
AND V
OL
TO V
OH
B. HI-Z TO V
OL
AND V
OH
TO V
OL
Load Circuit for Output Float Delay
1k 50pF 50pF
DBN DBN
1k
5V
LTC1605 • TC02
A. V
OH
TO HI-Z B. V
OL
TO HI-Z
FUNCTIONAL BLOCK DIAGRA
UU
W
16-BIT CAPACITIVE DAC COMPREF BUF
2.5V REF
CAP
(2.5V)
C
SAMPLE
C
SAMPLE
•
•
•
D15
D0
BUSY
CONTROL LOGIC
R/C BYTE
INTERNAL
CLOCK
CS
ZEROING SWITCHES
V
DIG
V
ANA
V
IN
REF
AGND1
AGND2
DGND
16
LTC1605 • BD
+
–
SUCCESSIVE APPROXIMATION
REGISTER OUTPUT LATCHES
4k
20k
4k10k
8
LTC1605
1605fc
APPLICATIONS INFORMATION
WUUU
Driving the Analog Inputs
The nominal input range for the LTC1605 is ±10V or
(±4 • V
REF
) and the input is overvoltage protected to ±25V.
The input impedance is typically 20kΩ, therefore, it should
be driven with a low impedance source. Wideband noise
coupling into the input can be minimized by placing a
1000pF capacitor at the input as shown in Figure 2. An
NPO-type capacitor gives the lowest distortion. Place the
capacitor as close to the device input pin as possible. If an
amplifier is to be used to drive the input, care should be
taken to select an amplifier with adequate accuracy, linear-
ity and noise for the application. The following list is a
summary of the op amps that are suitable for driving the
LTC1605. More detailed information is available in the
Linear Technology data books and LinearView
TM
CD-ROM.
Conversion Details
The LTC1605 uses a successive approximation algorithm
and an internal sample-and-hold circuit to convert an
analog signal to a 16-bit or two byte parallel output. The
ADC is complete with a precision reference and an internal
clock. The control logic provides easy interface to micro-
processors and DSPs. (Please refer to the Digital Interface
section for the data format.)
Conversion start is controlled by the CS and R/C inputs. At
the start of conversion the successive approximation
register (SAR) is reset. Once a conversion cycle has begun
it cannot be restarted.
During the conversion, the internal 16-bit capacitive DAC
output is sequenced by the SAR from the most significant
bit (MSB) to the least significant bit (LSB). Referring to
Figure 1, V
IN
is connected through the resistor divider to
the sample-and-hold capacitor during the acquire phase
and the comparator offset is nulled by the autozero switches.
In this acquire phase, a minimum delay of 2µs will provide
enough time for the sample-and-hold capacitor to acquire
the analog signal. During the convert phase, the autozero
switches open, putting the comparator into the compare
mode. The input switch switches C
SAMPLE
to ground,
injecting the analog input charge onto the summing junc-
tion. This input charge is successively compared with the
binary-weighted charges supplied by the capacitive DAC.
Bit decisions are made by the high speed comparator. At
the end of a conversion, the DAC output balances the V
IN
input charge. The SAR contents (a 16-bit data word) that
represents the V
IN
are loaded into the 16-bit output latches.
Figure 1. LTC1605 Simplified Equivalent Circuit
V
DAC
1605 • F01
+
–
C
DAC
DAC
SAMPLE
HOLD
C
SAMPLE
S
A
R
16-BIT
LATCH
COMPARATOR
SAMPLE
SI
R
IN2
R
IN1
V
IN
1605 • F02
1000pF 33.2k
V
IN
CAP
A
IN
200Ω
Figure 2. Analog Input Filtering
LT1007 - Low noise precision amplifier. 2.7mA supply
current ±5V to ±15V supplies. Gain bandwidth product
8MHz. DC applications.
LT1097 - Low cost, low power precision amplifier. 300µA
supply current. ±5V to ±15V supplies. Gain bandwidth
product 0.7MHz. DC applications.
LT1227 - 140MHz video current feedback amplifier. 10mA
supply current. ±5V to ±15V supplies. Low noise and low
distortion.
LT1360 - 37MHz voltage feedback amplifier. 3.8mA sup-
ply current. ±5V to ±15V supplies. Good AC/DC specs.
LT1363 - 50MHz voltage feedback amplifier. 6.3mA sup-
ply current. Good AC/DC specs.
LT1364/LT1365 - Dual and quad 50MHz voltage feedback
amplifiers. 6.3mA supply current per amplifier. Good AC/
DC specs.
LinearView is a trademark of Linear Technology Corporation
9
1605fc
LTC1605
APPLICATIONS INFORMATION
WUUU
Internal Voltage Reference
The LTC1605 has an on-chip, temperature compensated,
curvature corrected, bandgap reference, which is factory
trimmed to 2.50V. The full-scale range of the ADC is equal
to (±4 • V
REF
) or nominally ±10V. The output of the
reference is connected to the input of a unity-gain buffer
through a 4k resistor (see Figure 3). The input to the buffer
or the output of the reference is available at REF (Pin 3).
The internal reference can be overdriven with an external
reference if more accuracy is needed. The buffer output
drives the internal DAC and is available at CAP (Pin 4). The
CAP pin can be used to drive a steady DC load of less than
2mA. Driving an AC load is not recommended because it
can cause the performance of the converter to degrade.
Figure 3. Internal or External Reference Source
S
S
–
+
1605 • F03
INTERNAL
CAPACITOR
DAC
BANDGAP
REFERENCE
V
ANA
4k
2.2µF
CAP
(2.5V)
2.2µF
REF
(2.5V)
4
3
For minimum code transition noise the REF pin and the
CAP pin should each be decoupled with a capacitor to
filter wideband noise from the reference and the buffer
(2.2µF tantalum).
Offset and Gain Adjustments
The LTC1605 offset and full-scale errors have been trimmed
at the factory with the external resistors shown in Figure 4.
This allows for external adjustment of offset and full scale
in applications where absolute accuracy is important. See
Figure 5 for the offset and gain trim circuit. First adjust the
offset to zero by adjusting resistor R3. Apply an input
voltage of –152.6mV (–0.5LSB) and adjust R3 so the code
is changing between 1111 1111 1111 1111 and 0000 0000
0000 0000. The gain error is trimmed by adjusting resistor
R4. An input voltage of 9.999542V (+FS – 1.5LSB) is
applied to V
IN
and R4 is adjusted until the output code is
changing between 0111 1111 1111 1110 and 0111 1111
1111 1111. Figure 6 shows the bipolar transfer character-
istic of the LTC1605.
Figure 4. ±10V Input Without Trim
+
5
4
3
2
1
2.2µF
+
2.2µF
33.2k
1%
±10V INPUT
200Ω
1%
VIN
AGND1
REF
CAP
AGND2
LTC1605
1605 • F04
Figure 5. ±10V Input with Offset and Gain Trim
INPUT VOLTAGE (V)
0V
OUTPUT CODE
–1
LSB
1605 • F06
011...111
011...110
000...001
000...000
100...000
100...001
111...110
1
LSB
BIPOLAR
ZERO
111...111
FS/2 – 1LSB–FS/2
FS = 20V
1LSB = FS/65536
Figure 6. LTC1605 Bipolar Transfer Characteristics
DC Performance
One way of measuring the transition noise associated with
a high resolution ADC is to use a technique where a DC
+
5
4
3
2
1
2.2µF
+
2.2µF
33.2k
1%
±10V INPUT
200Ω
1%
V
IN
AGND1
REF
CAP
AGND2
LTC1605
1605 • F05
576k
R4
50k
R3
50k
5V
10
LTC1605
1605fc
APPLICATIONS INFORMATION
WUUU
signal is applied to the input of the ADC and the resulting
output codes are collected over a large number of conver-
sions. For example in Figure 7 the distribution of output
code is shown for a DC input that has been digitized 10000
times. The distribution is Gaussian and the RMS code
transition is about 1LSB.
Timing and Control
Conversion start and data read are controlled by two
digital inputs: CS and R/C. To start a conversion and put
the sample-and-hold into the hold mode bring CS and
R/C low for no less than 40ns. Once initiated it cannot be
restarted until the conversion is complete. Converter
status is indicated by the BUSY output and this is low while
the conversion is in progress.
There are two modes of operation. The first mode is shown
in Figure 8. The digital input R/C is used to control the start
of conversion. CS is tied low. When R/C goes low the
sample-and-hold goes into the hold mode and a conver-
sion is started. BUSY goes low and stays low during the
conversion and will go back high after the conversion has
been completed and the internal output shift registers
have been updated. R/C should remain low for no less than
40ns. During the time R/C is low the digital outputs are in
a Hi-Z state. R/C should be brought back high within 3µs
after the start of the conversion to ensure that no errors
occur in the digitized result. The second mode, shown in
Figure 9, uses the CS signal to control the start of a
conversion and the reading of the digital output. In this
mode the R/C input signal should be brought low no less
than 10ns before the falling edge of CS. The minimum
pulse width for CS is 40ns. When CS falls, BUSY goes low
and will stay low until the end of the conversion. BUSY will
go high after the conversion has been completed. The new
data is valid when CS is brought back low again to initiate
Figure 8. Conversion Timing with Outputs Enabled After Conversion (CS Tied Low)
CODE
0
500
1500
1000
2500
2000
4000
3500
3000
4500
COUNT
1605 • F07
–5–4–3–2–1012345
Figure 7. Histogram for 10000 Conversions
DIGITAL INTERFACE
Internal Clock
The ADC has an internal clock that is trimmed to achieve
a typical conversion time of 7µs. No external adjustments
are required and, with the typical acquisition time of 1µs,
throughput performance of 100ksps is assured.
t
1
t
11
t
2
t
4
t
3
t
7
t
6
ACQUIRE CONVERT CONVERTACQUIRE
t
5
t
8
t
ACQ
t
CONV
t
9
PREVIOUS
DATA VALID
PREVIOUS
DATA VALID
HI-Z NOT VALID HI-Z
DATA
VALID
DATA
VALID
R/C
BUSY
MODE
DATA MODE
1605 • F08
11
1605fc
LTC1605
Figure 11. LTC1605 Nonaveraged 4096 Point FFT Plot
APPLICATIONS INFORMATION
WUUU
ACQUIRE CONVERT ACQUIRE
DATA
VALID
t
1
t
10
t
10
t
1
t
10
t
10
t
3
t
6
t
4
t
CONV
t
12
t
7
HI-ZHI-Z
R/C
BUSY
CS
MODE
DATA BUS
1605 • F09
Figure 9. Using CS to Control Conversion and Read Timing
FREQUENCY (kHz)
–130
–120
–100
–110
–80
–90
–20
–40
–60
0
–30
–50
–70
–10
MAGNITUDE (dB)
1605 • F11
0 5 10 15 20 25 30 35 40 45 50
f
SAMPLE
= 100kHz
f
IN
= 1kHz
SINAD = 87.5dB
THD = –101.7dB
Figure 10. Using CS and BYTE to Control Data Bus Read Timing
t10
t10
t12 t7
t12
HI-Z
HI-Z
HI-Z
HI-Z
HIGH BYTE
LOW BYTE
LOW BYTE
HIGH BYTE
R/C
BYTE
CS
PINS 6 TO 13
PINS 15 TO 22
1605 • F03
12
LTC1605
1605fc
APPLICATIONS INFORMATION
WUUU
a read. Again it is recommended that both R/C and CS
return high within 3µs after the start of the conversion.
Output Data
The output data can be read as a 16-bit word or it can be
read as two 8-bit bytes. The format of the output data is
two’s complement. The digital input pin BYTE is used to
control the two byte read. With the BYTE pin low the first
eight MSBs are output on the D15 to D8 pins and the eight
LSBs are output on the D7 to D0 pins. When the BYTE pin
is taken high the eight LSBs replace the eight MSBs (Figure
10).
Dynamic Performance
FFT (Fast Fourier Transform) test techniques are used to
test the ADC’s frequency response, distortion and noise at
the rated throughput. By applying a low distortion sine
wave and analyzing the digital output using an FFT algo-
rithm, the ADC’s spectral content can be examined for
frequencies outside the fundamental. Figure 11 shows a
typical LTC1605 FFT plot which yields a SINAD of 87.5dB
and THD of –102dB.
Signal-to-Noise Ratio
The Signal-to-Noise and Distortion Ratio (SINAD) is the
ratio between the RMS amplitude of the fundamental input
frequency to the RMS amplitude of all other frequency
components at the A/D output. The output is band limited
to frequencies from above DC and below half the sampling
frequency. Figure 11 shows a typical SINAD of 87.5dB
with a 100kHz sampling rate and a 1kHz input.
Total Harmonic Distortion
Total Harmonic Distortion (THD) is the ratio of the RMS
sum of all harmonics of the input signal to the fundamental
itself. The out-of-band harmonics alias into the frequency
band between DC and half the sampling frequency. THD is
expressed as:
THD = 20log√V
22
+ V
32
+ V
42
... + V
N2
V
1
where V
1
is the RMS amplitude of the fundamental fre-
quency and V
2
through V
N
are the amplitudes of the
second through Nth harmonics.
Board Layout, Power Supplies and Decoupling
Wire wrap boards are not recommended for high resolu-
tion or high speed A/D converters. To obtain the best
performance from the LTC1605, a printed circuit board is
required. Layout for the printed circuit board should
ensure the digital and analog signal lines are separated as
much as possible. In particular, care should be taken not
to run any digital track alongside an analog signal track or
underneath the ADC. The analog input should be screened
by AGND.
Figures 12 through 15 show a layout for a suggested
evaluation circuit which will help obtain the best perfor-
mance from the 16-bit ADC. Pay particular attention to the
design of the analog and digital ground planes. The DGND
pin of the LTC1605 can be tied to the analog ground plane.
Placing the bypass capacitor as close as possible to the
power supply, the reference and reference buffer output is
very important. Low impedance common returns for
these bypass capacitors are essential to low noise opera-
tion of the ADC, and the foil width for these tracks should
be as wide as possible. Also, since any potential difference
in grounds between the signal source and ADC appears as
an error voltage in series with the input signal, attention
should be paid to reducing the ground circuit impedance
as much as possible. The digital output latches and the
onboard sampling clock have been placed on the digital
ground plane. The two ground planes are tied together at
the power supply ground connection.
13
1605fc
LTC1605
APPLICATIONS INFORMATION
WUUU
Figure 12. Component Side Silkscreen for the Suggested LTC1605 Evaluation Circuit
ANALOG
GROUND PLANE
DIGITAL
GROUND PLANE
ANALOG
GROUND PLANE
Figure 14. Component Side Showing Separate Analog
and Digital Ground Plane
Figure 13. Bottom Side Showing Analog Ground Plane
14
LTC1605
1605fc
Figure 15. LTC1605 Suggested Evaluation Circuit Schematic
D15
+
3
U6A
74HC221
A
B
Q
Q
CEXT
R21, 2k
RCEXT
15
1
2
4
13
CLK
1605_07d.eps
D15
D14
U1
LTC1605
D13
D12
D11
C5
0.1µF
R19
33.2k
1%
C3
0.1µF
C16
1000pF
C4
2.2µF
C2
2.2µF
EXT INTVREF
JP1
C17
10µFD10
D9
D8
D7
D6
D5
D4
D3
D2
D1
6
7
8
9
10
11
12
13
15
16
17
18
19
20
21
D0
D15 D15
D14
D13
D12
D11
D10
D9
D8
2
3
4
5
6
7
8
9
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
4
R20
1K
3
U4B
74HC04
65
U4C
74HC04
C1
15PF
22
1
2
3
4
5
14
23
24
25
26
27
28
VIN Q0
U2
74HC574
19
D0
Q1 18
D1
Q2 17
D2
Q3 16
D3
Q4 15
D4
Q5 14
D5
Q6 13
D6
Q7
12
12
U4A
74HC04
D7
1 OC
11 CLK
2
7
6
5
4
3
U7
74HC160
CLR
LOAD
RCO 15
2
3JP3
1
EXT
CLK
INT
2
3JP5
1
VCC
CS
GND
ENP
10 ENT
QD 11
D
QC 12
C
QB 13
B
QA 14
A
2
U8
1MHz, OSC
OUT 3
GND
1NA
E2
GND
VIN
7V TO 15V
E1
U5
LT1121 D16
MBR0520
C6
22µF
10V
GND
13
2
VIN VIN
4
U9
LT1019-2.5
TRIM 5
GND
1NC1
2INPUT
3
8
7
6
TEMP
NC2
HEATER
OUT
1
9
CLK
D0
D1
D2
D3
D4
D5
D6
D7
2
3
4
5
6
7
8
9
Q0
U3
74HC574
19
D0
Q1 18
D1
Q2 17
D2
Q3 16
D3
Q4 15
D4
Q5 14
D5
Q6 13
D6
Q7 12
D7
1 OC
11 CLK
AGND1
REF
CAP
AGND2
DGND
BYTE
R/C
CS
BUSY
VANA
VDIG
C8
0.1µF
C7
10µF
VKK
VCC
VKK
VKK VDD
VCC
R16
20 C9
0.1µF
C10
0.1µF
DIGITAL I.C. BYPASSING
C11
0.1µF
C12
0.1µF
VCC
C13
0.1µF
C14
0.1µF
C15
10µF
2
3JP4
1
REVERSE
BYTE
NORNAL
VCC
VCC
VCC
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
GND
GND
CLK
D15
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
R8, 1.2k D8
R9, 1.2k D9
R10, 1.2k D10
R11, 1.2k D11
R12, 1.2k D12
R13, 1.2k D13
R14, 1.2k D14
R15, 1.2k
R0, 1.2k D0
R1, 1.2k D1
R2, 1.2k D2
R3, 1.2k D3
R4, 1.2k D4
R5, 1.2k D5
R6, 1.2k D6
R7, 1.2k D7
JP2
LED
ENABLE
1011
U4E
74HC04
81
2
9
EXT_CLK
J1
1
2
AIN
J2
R17
51
U4D
74HC04
R18
200Ω
1%
APPLICATIONS INFORMATION
WUUU
15
1605fc
LTC1605
PACKAGE DESCRIPTION
U
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
N28 1002
.255 ± .015*
(6.477 ± 0.381)
1.370*
(34.789)
MAX
345678910 11 12
21
13 14
151618 171920
22
23
2425
26
2
27
1
28
.020
(0.508)
MIN
.120
(3.048)
MIN
.130 ± .005
(3.302 ± 0.127)
.065
(1.651)
TYP
.045 – .065
(1.143 – 1.651)
.018 ± .003
(0.457 ± 0.076)
.005
(0.127)
MIN
.008 – .015
(0.203 – 0.381)
.300 – .325
(7.620 – 8.255)
.325 +.035
–.015
+0.889
–0.381
8.255
()
NOTE:
1. DIMENSIONS ARE INCHES
MILLIMETERS
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)
.100
(2.54)
BSC
N Package
28-Lead PDIP (Narrow 0.300 Inch)
(Reference LTC DWG # 05-08-1510)
G28 SSOP 0802
0.09 – 0.25
(.0035 – .010)
0° – 8°
0.55 – 0.95
(.022 – .037)
5.00 – 5.60**
(.197 – .221)
7.40 – 8.20
(.291 – .323)
12345678 9 10 11 12 1413
9.90 – 10.50*
(.390 – .413)
2526 22 21 20 19 18 17 16 1523242728
2.0
(.079)
0.05
(.002)
0.65
(.0256)
BSC 0.22 – 0.38
(.009 – .015)
MILLIMETERS
(INCHES)
DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED .152mm (.006") PER SIDE
DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
*
**
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
0.42 ±0.03 0.65 BSC
5.3 – 5.7
7.8 – 8.2
RECOMMENDED SOLDER PAD LAYOUT
1.25 ±0.12
G Package
28-Lead Plastic SSOP (5.3mm)
(Reference LTC DWG # 05-08-1640)
16
LTC1605
1605fc
© LINEAR TECHNOLOGY CORPORATION 2005
LT 0106 REV C • PRINTED IN THE USA
PACKAGE DESCRIPTION
U
SW Package
28-Lead Plastic Small Outline (Wide 0.300 Inch)
(Reference LTC DWG # 05-08-1620)
PART NUMBER DESCRIPTION COMMENTS
LT
®
1019-2.5 Precision Bandgap Reference 0.05% Max, 5ppm/°C Max
LTC1274/LTC1277 Low Power 12-Bit, 100ksps ADCs 10mW Power Dissipation, Parallel/Byte Interface
LTC1415 Single 5V, 12-Bit, 1.25Msps ADC 55mW Power Dissipation, 72dB SINAD
LTC1419 Low Power 14-Bit, 800ksps ADC True 14-Bit Linearity, 81.5dB SINAD, 150mW Dissipation
LT1460-2.5 Micropower Precision Series Reference 0.075% Max, 10ppm/°C Max, Only 130µA Supply Current
LTC1594/LTC1598 Micropower 4-/8-Channel 12-Bit ADCs Serial I/O, 3V and 5V Versions
RELATED PARTS
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear.com
S28 (WIDE) 0502
0° – 8° TYP
NOTE 3
.009 – .013
(0.229 – 0.330)
.016 – .050
(0.406 – 1.270)
.291 – .299
(7.391 – 7.595)
NOTE 4
× 45°
.010 – .029
(0.254 – 0.737)
.037 – .045
(0.940 – 1.143)
.004 – .012
(0.102 – 0.305)
.093 – .104
(2.362 – 2.642)
.050
(1.270)
BSC .014 – .019
(0.356 – 0.482)
TYP
NOTE 3
.697 – .712
(17.70 – 18.08)
NOTE 4
12345678
.394 – .419
(10.007 – 10.643)
910
2526
11 12
22 21 20 19 18 17 16 152324
14
N/2
13
2728
N
.420
MIN
.325 ±.005
RECOMMENDED SOLDER PAD LAYOUT
.045 ±.005
N
1 2 3 N/2
.050 BSC
.030 ±.005
TYP
.005
(0.127)
RAD MIN
INCHES
(MILLIMETERS)
NOTE:
1. DIMENSIONS IN
2. DRAWING NOT TO SCALE
3. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS
4. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
