74LV74
Dual D-type flip-flop with set and reset;
positive-edge trigger
Product specification
Supersedes data of 1996 Nov 07
IC24 Data Handbook
1998 Apr 20
INTEGRATED CIRCUITS
Philips Semiconductors Product specification
74LV74
Dual D-type flip-flop with set and reset;
positive edge-trigger
2
1998 Apr 20 853-1888 19258
FEATURES
•Wide operating voltage: 1.0 to 5.5V
•Optimized for Low V oltage applications: 1.0 to 3.6V
•Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V
•Typical VOLP (output ground bounce) 0.8V @ VCC = 3.3V,
Tamb = 25°C
•Typical VOHV (output VOH undershoot) 2V @ VCC = 3.3V,
Tamb = 25°C
•Output capability: standard
•ICC category: flip-flops
DESCRIPTION
The 74LV74 is a low-voltage Si-gate CMOS device and is pin and
function compatible with 74HC/HCT74.
The 74LV74 is a dual positive edge triggered, D-type flip-flop with
individual data (D) inputs, clock (CP) inputs, set (SD) and (RD)
inputs; also complementary Q and Q outputs.
The set and reset are asynchronous active LOW inputs and operate
independently of the clock input. Information on the data input is
transferred to the Q output on the LOW-to-HIGH transition of the
clock pulse. The D inputs must be stable one set-up time prior to the
LOW-to-HIGH clock transition, for predictable operation.
Schmitt-trigger action in the clock input makes the circuit highly
tolerant to slower clock rise and fall times.
QUICK REFERENCE DATA
GND = 0V ; Tamb = 25°C; tr =tf 2.5 ns
SYMBOL PARAMETER CONDITIONS TYPICAL UNIT
tPHL/tPLH
Propagation delay
nCP to nQ, nQ
nSD to nQ, nQ
nRD to nQ, nQ
CL = 15pF
VCC = 3.3V 11
14
14 ns
fmax Maximum clock frequency CL = 15pF
VCC = 3.3V 76 MHz
CIInput capacitance 3.5 pF
CPD Power dissipation capacitance per flip-flop Notes 1 and 2 24 pF
NOTES:
1. CPD is used to determine the dynamic power dissipation (PD in µW)
PD = CPD VCC2 x fi (CL VCC2 fo) where:
fi = input frequency in MHz; CL = output load capacitance in pF;
fo = output frequency in MHz; VCC = supply voltage in V ;
(CL VCC2 fo) = sum of the outputs.
2. The condition is VI = GND to VCC
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA PKG. DWG. #
14-Pin Plastic DIL –40°C to +125°C74LV74 N 74LV74 N SOT27-1
14-Pin Plastic SO –40°C to +125°C74LV74 D 74LV74 D SOT108-1
14-Pin Plastic SSOP Type II –40°C to +125°C74LV74 DB 74LV74 DB SOT337-1
14-Pin Plastic TSSOP Type I –40°C to +125°C74LV74 PW 74LV74PW DH SOT402-1
PIN DESCRIPTION
PIN
NUMBER SYMBOL FUNCTION
1, 13 1RD, 2RDAsynchronous reset-direct input
(active-LOW)
2, 12 1D, 2D Data inputs
3, 11 1CP, 2CP Clock input (LOW-to-HIGH),
edge-triggered)
4, 10 1SD, 2SDAsynchronous set-direct input
(active-LOW)
5, 9 1Q, 2Q T rue flip-flop outputs
6, 8 1Q, 2Q Complement flip-flop outputs
7 GND Ground (0V)
14 VCC Positive supply voltage
FUNCTION TABLE
INPUTS OUTPUTS
SDRDCP D Q Q
L
H
L
H
L
L
X
X
X
X
X
X
H
L
H
L
H
H
INPUTS OUTPUTS
SDRDCP D Qn+1 Qn+1
H
HH
H
L
HL
HH
L
H = HIGH voltage level
L = LOW voltage level
X = don’t care
= LOW-to-HIGH CP transition
Qn+1 = state after the next LOW-to-HIGH CP transition
Philips Semiconductors Product specification
74LV74
Dual D-type flip-flop with set and reset;
positive edge-trigger
1998 Apr 20 3
PIN CONFIGURATION
1
2
3
4
5
6
78
9
10
11
12
13
14
1RD
1SD
1D
1CP
1Q
1Q
GND
VCC
2D
2CP
2SD
2Q
2Q
2RD
SV00330
LOGIC SYMBOL (IEEE/IEC)
SV00332
4
3
2
1
10
11
12
13
5
6
9
8
S
C1
1D
R
S
C2
2D
R
LOGIC SYMBOL
SV00331
410
1SD2SD
SD
21D 1Q 5
12 2D 2Q 9
DQ
CP FF
11 2CP
Q1Q
RD
1RD2RD
113
2Q 8
3 1CP
6
FUNCTIONAL DIAGRAM
2
3CP FF1
DQ
Q
1D2
1CP
4SD
1RD
6
1Q
1Q 5
CP FF2
DQ
Q
2D12
2CP11
10
13
8
2Q 9
SD
RD
Q
SV00333
1SD
1RD
2SD
2RD
Philips Semiconductors Product specification
74LV74
Dual D-type flip-flop with set and reset;
positive edge-trigger
1998 Apr 20 4
LOGIC DIAGRAM (ONE FLIP-FLOP)
Q
Q
C
C
C
C
C
C
C
C
D
C
C
RD
SD
CP
SV00334
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER CONDITIONS MIN TYP. MAX UNIT
VCC DC supply voltage See Note1 1.0 3.3 5.5 V
VIInput voltage 0 – VCC V
VOOutput voltage 0 – VCC V
Tamb Operating ambient temperature range in free
air See DC and AC
characteristics –40
–40 +85
+125 °C
tr, tfInput rise and fall times except for
Schmitt-trigger inputs
VCC = 1.0V to 2.0V
VCC = 2.0V to 2.7V
VCC = 2.7V to 3.6V
VCC = 3.6V to 5.5V
–
–
–
–
–
–
–
–
500
200
100
50 ns/V
NOTE:
1. The LV is guaranteed to function down to VCC = 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 5.5V.
ABSOLUTE MAXIMUM RATINGS1, 2
In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0V)
SYMBOL PARAMETER CONDITIONS RATING UNIT
VCC DC supply voltage –0.5 to +7.0 V
±IIK DC input diode current VI < –0.5 or VI > VCC + 0.5V 20 mA
±IOK DC output diode current VO < –0.5 or VO > VCC + 0.5V 50 mA
±IODC output source or sink current
– standard outputs –0.5V < VO < VCC + 0.5V 25 mA
±IGND,
±ICC
DC VCC or GND current for types with
–standard outputs 50 mA
Tstg Storage temperature range –65 to +150 °C
Power dissipation per package for temperature range: –40 to +125°C
Ptt
–plastic DIL above +70°C derate linearly with 12mW/K 750
mW
P
tot –plastic mini-pack (SO) above +70°C derate linearly with 8 mW/K 500
mW
–plastic shrink mini-pack (SSOP and TSSOP) above +60°C derate linearly with 5.5 mW/K 400
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
Philips Semiconductors Product specification
74LV74
Dual D-type flip-flop with set and reset;
positive edge-trigger
1998 Apr 20 5
DC CHARACTERISTICS
Over recommended operating conditions voltages are referenced to GND (ground = 0V) LIMITS
SYMBOL PARAMETER TEST CONDITIONS -40°C to +85°C -40°C to +125°CUNIT
MIN TYP1MAX MIN MAX
VCC = 1.2V 0.9 0.9
VIH
HIGH level Input VCC = 2.0V 1.4 1.4
V
V
IH voltage VCC = 2.7 to 3.6V 2.0 2.0
V
VCC = 4.5 to 5.5V 0.7*VCC 0.7*VCC
VCC = 1.2V 0.3 0.3
VIL
LOW level Input VCC = 2.0V 0.6 0.6
V
V
IL voltage VCC = 2.7 to 3.6V 0.8 0.8
V
VCC = 4.5 to 5.5 0.3*VCC 0.3*VCC
VCC = 1.2V ; VI = VIH or VIL; –IO = 100µA 1.2
HIGH level output
VCC = 2.0V ; VI = VIH or VIL; –IO = 100µA 1.8 2.0 1.8
VOH
HIGH
l
eve
l
ou
t
pu
t
voltage
;
all out
p
uts
VCC = 2.7V ; VI = VIH or VIL; –IO = 100µA 2.5 2.7 2.5 V
voltage
all
out uts
VCC = 3.0V ; VI = VIH or VIL; –IO = 100µA 2.8 3.0 2.8
VCC = 4.5V ;VI = VIH or VIL; –IO = 100µA 4.3 4.5 4.3
VOH
HIGH level output
voltage; VCC = 3.0V ;VI = VIH or VIL; –IO = 6mA 2.40 2.82 2.20
V
V
OH
g
STANDARD
outputs VCC = 4.5V ;VI = VIH or VIL; –IO = 12mA 3.60 4.20 3.50
V
VCC = 1.2V ; VI = VIH or VIL; IO = 100µA 0
LOW level output
VCC = 2.0V ; VI = VIH or VIL; IO = 100µA 0 0.2 0.2
VOL
LOW
l
eve
l
ou
t
pu
t
voltage
;
all out
p
uts
VCC = 2.7V ; VI = VIH or VIL; IO = 100µA 0 0.2 0.2 V
voltage
all
out uts
VCC = 3.0V ;VI = VIH or VIL; IO = 100µA 0 0.2 0.2
VCC = 4.5V ;VI = VIH or VIL; IO = 100µA 0 0.2 0.2
VOL
LOW level output
voltage; VCC = 3.0V ;VI = VIH or VIL; IO = 6mA 0.25 0.40 0.50
V
V
OL
g
STANDARD
outputs VCC = 4.5V ;VI = VIH or VIL; IO = 12mA 0.35 0.55 0.65
V
IIInput leakage
current VCC = 5.5V ; VI = VCC or GND 1.0 1.0 µA
ICC Quiescent supply
current; flip-flops VCC = 5.5V; VI = VCC or GND; IO = 0 20.0 80 µA
∆ICC Additional
quiescent supply
current per input VCC = 2.7V to 3.6V; VI = VCC –0.6V 500 850 µA
NOTE:
1. All typical values are measured at Tamb = 25°C.
Philips Semiconductors Product specification
74LV74
Dual D-type flip-flop with set and reset;
positive edge-trigger
1998 Apr 20 6
AC CHARACTERISTICS
GND = 0V ; tr = tf 2.5ns; CL = 50pF; RL = 1KΩ
SYMBOL PARAMETER WAVEFORM CONDITION LIMITS
–40 to +85 °CLIMITS
–40 to +125 °CUNIT
VCC(V) MIN TYP1MAX MIN MAX
1.2 – 70 – – –
Propagation delay
2.0 – 24 44 – 56
tPHL/tPLH
P
ropaga
ti
on
d
e
l
ay
nCP to nQ, nQ
Figures, 1, 3 2.7 – 18 28 – 41 ns
nCP
to
nQ
,
nQ
3.0 to 3.6 – 13226 – 33
4.5 to 5.5 – 9.5317 – 23
1.2 – 90 – – –
Propagation delay
2.0 – 31 46 – 58
tPHL/tPLH
P
ropaga
ti
on
d
e
l
ay
nSDto nQ, nQ
Figures 2, 3 2.7 – 23 34 – 43 ns
nSD
to
nQ
,
nQ
3.0 to 3.6 – 17227 – 34
4.5 to 5.5 – 12319 – 24
1.2 – 90 – – –
Propagation delay
2.0 – 31 46 – 58
tPHL/tPLH
P
ropaga
ti
on
d
e
l
ay
nRDto nQ, nQ
Figures 2, 3 2.7 – 23 34 – 43 ns
nRD
to
nQ
,
nQ
3.0 to 3.6 – 17227 – 34
4.5 to 5.5 – 12319 – 24
2.0 34 10 – 41 –
tW
Clock pulse width
Figure 1
2.7 25 8 – 30 –
ns
t
WHIGH to LOW
Figure
1
3.0 to 3.6 20 72– 24 –
ns
4.5 to 5.5 15 63– 18 –
2.0 34 10 – 41 –
tW
Set or reset pulse
Figure 2
2.7 25 8 – 30 –
ns
t
Wwidth LOW
Figure
2
3.0 to 3.6 20 72– 24 –
ns
4.5 to 5.5 15 63– 18 –
1.2 – 5 – – –
Removal time
2.0 14 2 – 15 –
trem
R
emova
l
ti
me
set or reset
Figure 2 2.7 10 1 – 11 –ns
set
or
reset
3.0 to 3.6 8 12– 9 –
4.5 to 5.5 6 13– 7 –
1.2 – 10 – – –
Set up time
2.0 22 4 – 26 –
tsu
S
e
t
-up
ti
me
nD to nCP
Figure 1 2.7 12 3 – 15 – ns
nD
to
nCP
3.0 to 3.6 8 22– 10 –
4.5 to 5.5 6 12– 8 –
1.2 – –10 – – –
Hold time
2.0 3 –2 – 3 –
th
H
o
ld
ti
me
nD to nCP
Figure 1 2.7 3 –2 – 3 – ns
nD
to
nCP
3.0 to 3.6 3 –22– 3 –
4.5 to 5.5 3 –23– 3 –
2.0 14 40 – 12 –
f
Maximum clock
Figure 1
2.7 50 90 – 40 –
MHz
f
max pulse frequency
Figure
1
3.0 to 3.6 60 1002– 48 –
MHz
4.5 to 5.5 70 1103– 56 –
NOTE:
1. Unless otherwise stated, all typical values are at Tamb = 25°C.
2. Typical value measured at VCC = 3.3V.
3. Typical value measured at VCC = 5.0V.
Philips Semiconductors Product specification
74LV74
Dual D-type flip-flop with set and reset;
positive edge-trigger
1998 Apr 20 7
AC WAVEFORMS
VM = 1.5V at VCC 2.7V 3.6V
VM = 0.5 * VCC at VCC 2.7V and 4.5V
VOL and VOH are the typical output voltage drop that occur with the
output load.
ÏÏÏ
ÏÏÏ
ÏÏÏ
ÏÏÏ
ÏÏÏÏ
ÏÏÏÏ
nQ OUTPUT
VMnD INPUT
nCP INPUT
nQ OUTPUT VM
VM
VM
tsu 1/fmax
th
th
tPHL
tPHL
tPLH
tPLH
tW
GND
GND
VI
VI
VOL
VOL
VOH
VOH
tsu
SV00335
Figure 1.The clock (nCP) to output (nQ, nQ) propagation
delays, the clock pulse width, the nD to nCP setup times, the
nCP to nD hold times, the output transition times and the
maximum clock pulse frequency
NOTE:
The shaded areas indicate when the input is permitted to change for
predictable output performance.
nCP INPUT
nSD INPUT
nRD INPUT
nQ OUTPUT
nQ OUTPUT
GND
GND
GND
VI
VI
VI
VOL
VOL
VOH
VOH
VM
VM
VM
VM
trem
tPHL
tPLH
tWtW
VM
tPLH
tPHL
SV00336
Figure 2.The set (nSD) and reset (nRD) input to output (nQ, nQ)
propagation delays, the set and reset pulse widths and the nRD
to nCP removal time
TEST CIRCUIT
PULSE
GENERATOR
RT
Vl
D.U.T.
VO
CLRL= 1k
Vcc
Test Circuit for Outputs
DEFINITIONS
VCC VI
< 2.7V
2.7–3.6V
VCC
2.7V
TEST
tPLH/tPHL
≥4.5 V VCC
RL = Load resistor
CL = Load capacitance includes jig and probe capacitiance
50pF
RT = Termination resistance should be equal to ZOUT of pulse generators.
SV00902
Figure 3. Load circuitry for switching times
Philips Semiconductors Product specification
74LV74
Dual D-type flip-flop with set and reset;
positive edge-trigger
1998 Apr 20 8
DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1
Philips Semiconductors Product specification
74LV74
Dual D-type flip-flop with set and reset;
positive edge-trigger
1998 Apr 20 9
SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
Philips Semiconductors Product specification
74LV74
Dual D-type flip-flop with set and reset;
positive edge-trigger
1998 Apr 20 10
SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1
Philips Semiconductors Product specification
74LV74
Dual D-type flip-flop with set and reset;
positive edge-trigger
1998 Apr 20 11
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1
Philips Semiconductors Product specification
74LV74
Dual D-type flip-flop with set and reset;
positive edge-trigger
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing
or modification.
LIFE SUPPORT APPLICATIONS
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appl iances, devices,
or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected
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Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
DEFINITIONS
Data Sheet Identification Product Status Definition
Objective Specification
Preliminary Specification
Product Specification
Formative or in Design
Preproduction Product
Full Production
This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
print code Date of release: 05-96
Document order number: 9397-750-04414
