SLVS077D – APRIL 1977 – REVISED FEBRUAR Y 2003
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DComplete Pulse-Width Modulation (PWM)
Power-Control Circuitry
DUncommitted Outputs for Single-Ended or
Push-Pull Applications
DLow Standby Current...8 mA Typ
DInterchangeable With Industry Standard
SG2524 and SG3524
description/ordering information
The SG2524 and SG3524 incorporate all the
functions required in the construction of a
regulating power supply, inverter, or switching
regulator on a single chip. They also can be used
as the control element for high-power-output
applications. The SG2524 and SG3524 were
designed for switching regulators of either polarity, transformer-coupled dc-to-dc converters, transformerless
voltage doublers, and polarity-converter applications employing fixed-frequency, pulse-width modulation
(PWM) techniques. The complementary output allows either single-ended or push-pull application. Each device
includes a n on-chip regulator, error amplifier, programmable oscillator, pulse-steering flip-flop, two uncommitted
pass transistors, a high-gain comparator, and current-limiting and shutdown circuitry.
ORDERING INFORMATION
T
INPUT
REGULATION
PACKAGE†
ORDERABLE TOP-SIDE
TAREGULATION
MAX (mV) PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP (N) Tube of 25 SG3524N SG3524N
0°Cto70°C
30
SOIC (D)
Tube of 40 SG3524D
SG3524
0°C to 70°C 30 SOIC (D) Reel of 2500 SG3524DR SG3524
SOP (NS) Reel of 2000 SG3524NSR SG3524
PDIP (N) Tube of 25 SG2524N SG2524N
–25°C to 85°C 20
SOIC (D)
Tube of 40 SG2524D
SG2524
SOIC (D) Reel of 2500 SG2524DR SG2524
†Package drawings, standard packing quantities, thermal data, symboliztion, and PCB design guidelines are
available at www.ti.com/sc/package.
Copyright 2003, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
IN–
IN+
OSC OUT
CURR LIM+
CURR LIM–
RT
CT
GND
REF OUT
VCC
EMIT 2
COL 2
COL 1
EMIT 1
SHUTDOWN
COMP
SG2524 ...D OR N PACKAGE
SG3524 . . . D, N, OR NS PACKAGE
(TOP VIEW)
SLVS077D – APRIL 1977 – REVISED FEBRUARY 2003
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
TCOL 2
OSC OUT
EMIT 2
EMIT 1
COL 1
Vref
Reference
Regulator
Comparator
Oscillator
SHUTDOWN
Error Amplifier
1
2
9
4
5
CURR LIM–
CURR LIM+
GND 8
10
+
–
+
–
NOTE A: Resistor values shown are nominal.
12
11
13
14
3
IN–
IN+
COMP
1 kΩ
10 kΩ
15
RT
CT
REF OUT
16
6
7
Vref
Vref
Vref
Vref
VCC
Vref
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC (see Notes 1 and 2) 40 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Collector output current, ICC 100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference output current, IO(ref) 50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current through CT terminal –5 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating virtual junction temperature, TJ 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Notes 3 and 4): D package 73°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package 64°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , an d
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to network ground terminal.
2. The reference regulator may be bypassed for operation from a fixed 5-V supply by connecting the VCC and reference output
(REF OUT) pin both to the supply voltage. In this configuration, the maximum supply voltage is 6 V.
3. Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD = (TJ(max) – TA)/θJA. Operation at the absolute maximum TJ of 150°C can impact reliability.
4. The package thermal impedance is calculated in accordance with JESD 51-7.
SLVS077D – APRIL 1977 – REVISED FEBRUARY 2003
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recommended operating conditions
MIN MAX UNIT
VCC Supply voltage 8 40 V
Reference output current 0 50 mA
Current through CT terminal –0.03 –2 mA
RTTiming resistor 1.8 100 kΩ
CTTiming capacitor 0.001 0.1 µF
TA
O
p
erating free air tem
p
erature
SG2524 –25 85
°C
TAOperating free-air temperature SG3524 0 70 °C
electrical characteristics over recommended operating free-air temperature range, VCC = 20 V,
f = 20 kHz (unless otherwise noted)
reference section
PARAMETER
TEST CONDITIONS†
SG2524 SG3524
UNIT
PARAMETER TEST CONDITIONS
†
MIN TYP‡MAX MIN TYP‡MAX UNIT
Output voltage 4.8 5 5.2 4.6 5 5.4 V
Input regulation VCC = 8 V to 40 V 10 20 10 30 mV
Ripple rejection f = 120 Hz 66 66 dB
Output regulation IO = 0 mA to 20 mA 20 50 20 50 mV
Output voltage change with temperature TA = MIN to MAX 0.3% 1% 0.3% 1%
Short-circuit output current§Vref = 0 100 100 mA
†For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
‡All typical values, except for temperature coefficients, are at TA = 25°C
§Standard deviation is a measure of the statistical distribution about the mean, as derived from the formula:
s+
ȍ
N
n+1(xn*X)2
N*1
Ǹ
oscillator section
PARAMETER TEST CONDITIONS†MIN TYP‡MAX UNIT
fosc Oscillator frequency CT = 0.001 µF, RT = 2 kΩ450 kHz
Standard deviation of frequency§All values of voltage, temperature, resistance,
and capacitance constant 5%
∆f
Frequency change with voltage VCC = 8 V to 40 V, TA = 25°C 1%
∆fosc Frequency change with temperature TA = MIN to MAX 2%
Output amplitude at OSC OUT TA = 25°C 3.5 V
twOutput pulse duration (width) at OSC OUT CT = 0.01 µF, TA = 25°C 0.5 µs
†For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
‡All typical values, except for temperature coefficients, are at TA = 25°C
§Standard deviation is a measure of the statistical distribution about the mean, as derived from the formula:
s+
ȍ
N
n+1(xn*X)2
N*1
Ǹ
SLVS077D – APRIL 1977 – REVISED FEBRUARY 2003
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
error amplifier section
PARAMETER
TEST SG2524 SG3524
UNIT
PARAMETER
TEST
CONDITIONS†MIN TYP‡MAX MIN TYP‡MAX UNIT
VIO Input offset voltage VIC = 2.5 V 0.5 5 2 10 mV
IIB Input bias current VIC = 2.5 V 2 10 2 10 µA
Open-loop voltage amplification 72 80 60 80 dB
VICR Common-mode input voltage range TA = 25°C1.8 to
3.4 1.8 to
3.4 V
CMMR Common-mode rejection ratio 70 70 dB
B1Unity-gain bandwidth 3 3 MHz
Output swing TA = 25°C 0.5 3.8 0.5 3.8 V
†For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
‡All typical values, except for temperature coefficients, are at TA = 25°C
output section
PARAMETER TEST CONDITIONS†MIN TYP‡MAX UNIT
V(BR)CE Collector-emitter breakdown voltage 40 V
Collector off-state current VCE = 40 V 0.01 50 µA
Vsat Collector-emitter saturation voltage IC = 50 mA 1 2 V
VOEmitter output voltage VC = 20 V, IE = –250 µA 17 18 V
trTurn-off voltage rise time RC = 2 kΩ0.2 µs
tfTurn-on voltage fall time RC = 2 kΩ0.1 µs
†For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
‡All typical values, except for temperature coefficients, are at TA = 25°C.
comparator section
PARAMETER TEST CONDITIONS†MIN TYP‡MAX UNIT
Maximum duty cycle, each output 45%
V
Inp t threshold oltage at COMP
Zero duty cycle 1
V
VIT Input threshold voltage at COMP Maximum duty cycle 3.5 V
IIB Input bias current –1µA
†For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
‡All typical values, except for temperature coefficients, are at TA = 25°C.
current limiting section
PARAMETER TEST CONDITIONS†MIN TYP‡MAX UNIT
VIInput voltage range (either input) –1 to1 V
V(SENSE) Sense voltage at TA = 25°C
V(IN ) V(IN )≥50 mV V(COMP) 2V
175 200 225 mV
Temperature coefficient of sense voltage V(IN+) – V(IN–) ≥ 50 mV, V(COMP) = 2 V 0.2 mV/°C
‡All typical values, except for temperature coefficients, are at TA = 25°C.
total device
PARAMETER TEST CONDITIONS MIN TYP‡MAX UNIT
Ist Standby current VCC = 40 V, IN–, CURR LIM+, CT, GND, COMP, EMIT 1, EMIT 2 grounded,
IN+ at 2 V, All other inputs and outputs open 8 10 mA
‡All typical values, except for temperature coefficients, are at TA = 25°C.
SLVS077D – APRIL 1977 – REVISED FEBRUARY 2003
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PARAMETER MEASUREMENT INFORMATION
0.1 µF
2 kΩ
10 kΩ
RT
1 W
2 kΩ
8
4
2
1
9
6
7
10
11
14
16
3
12
13
(Open)
Outputs
VCC = 8 V to 40 V
15
SHUTDOWN
CT
RT
COMP
IN–
IN+
CURR LIM+ COL 2
COL 1
OSC OUT
REF OUT
EMIT 2
EMIT 1
GND
SG2524 or SG3524
VCC
CT
2 kΩ
1 W
2 kΩ
2 kΩ10 kΩ
1 kΩ
5CURR LIM–
VREF
VREF
Figure 1. General Test Circuit
≈0 V
≈VCC
VOLTAGE WAVEFORMS
90%
10%
10%
90%
tr
tf
TEST CIRCUIT
Circuit Under Test
Output
2 kΩ
VCC
Output
Figure 2. Switching Times
SLVS077D – APRIL 1977 – REVISED FEBRUARY 2003
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Frequency – Hz
–10
0
10
20
30
40
50
60
70
80
90
Open-Loop Voltage Amplification of Error Amplifier – dB
10 M1 M100 k10 k1 k100
RL is resistance from COMP to ground
ÏÏÏÏÏ
ÏÏÏÏÏ
RL = 300 kΩ
ÏÏÏÏ
RL = 1 MΩ
ÏÏÏÏÏ
ÏÏÏÏÏ
RL = 100 kΩ
ÏÏÏÏ
ÏÏÏÏ
RL = 30 kΩ
OPEN-LOOP VOLTAGE AMPLIFICATION
OF ERROR AMPLIFIER
vs
FREQUENCY
VCC = 20 V
TA = 25°C
RL = ∞
Figure 3
1
– Oscillator Frequency – Hz
RT – Timing Resistance – kΩ
20 40 1007010742
OSCILLATOR FREQUENCY
vs
TIMING RESISTANCE
VCC = 20 V
TA = 25°C
1M
400 k
100 k
40 k
10 k
4 k
1 k
400
100
CT = 0.1 µF
CT = 0.01 µF
CT = 0.03 µF
CT = 0.003 µF
CT = 0
fosc
CT = 0.001 µF
Figure 4
OUTPUT DEAD TIME
vs
TIMING CAPACITANCE
1
10
4
0.001 0.01
Output Dead Time –
0.004 0.10.04
0.1
0.4
µs
CT – Timing Capacitance – µF
Figure 5
SLVS077D – APRIL 1977 – REVISED FEBRUARY 2003
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PRINCIPLES OF OPERATION†
The SG2524 is a fixed-frequency pulse-width-modulation (PWM) voltage-regulator control circuit. The regulator
operates at a fixed frequency that is programmed by one timing resistor, RT, and one timing capacitor, CT. RT
establishes a constant charging current for CT. This results in a linear voltage ramp at CT, which is fed to the
comparator, providing linear control of the output pulse duration (width) by the error amplifier. The SG2524 contains
an onboard 5-V regulator that serves as a reference, as well as supplying the SG2524 internal regulator control
circuitry. The internal reference voltage is divided externally by a resistor ladder network to provide a reference within
the common-mode range of the error amplifier as shown in Figure 6, or an external reference can be used. The output
is sensed by a second resistor divider network and the error signal is amplified. This voltage is then compared to the
linear voltage ramp at CT. The resulting modulated pulse out of the high-gain comparator then is steered to the
appropriate output pass transistor (Q1 or Q2) by the pulse-steering flip-flop, which is synchronously toggled by the
oscillator output. The oscillator output pulse also serves as a blanking pulse to ensure both outputs are never on
simultaneously during the transition times. The duration of the blanking pulse is controlled by the value of CT. The
outputs may be applied in a push-pull configuration in which their frequency is one-half that of the base oscillator, or
paralleled fo r s i n g l e - ended applications in which the frequency is equal to that of the oscillator. The output of the error
amplifier shares a common input to the comparator with the current-limiting and shut-down circuitry and can be
overridden by signals from either of these inputs. This common point is pinned out externally via the COMP pin, which
can be employed to either control the gain of the error amplifier or to compensate it. In addition, the COMP pin can
be used to provide additional control to the regulator.
APPLICATION INFORMATION†
oscillator
The oscillator controls the frequency of the SG2524 and is programmed by RT and CT as shown in Figure 4.
f[1.30
RTCT
where: RT is in kΩ
CT is in µF
f is in kHz
Practical values of CT fall between 0.001 µF and 0.1 µF. Practical values of RT fall between 1.8 kΩ and 100 kΩ.
This results in a frequency range typically from 130 Hz to 722 kHz.
blanking
The output pulse of the oscillator is used as a blanking pulse at the output. This pulse duration is controlled by
the value of CT as shown in Figure 5. If small values of CT are required, the oscillator output pulse duration can
be maintained by applying a shunt capacitance from OSC OUT to ground.
synchronous operation
When an external clock is desired, a clock pulse of approximately 3 V can be applied directly to the oscillator
output terminal. The impedance to ground at this point is approximately 2 kΩ. In this configuration, RTCT must
be selected for a clock period slightly greater than that of the external clock.
†Throughout these discussions, references to the SG2524 apply also to the SG3524.
SLVS077D – APRIL 1977 – REVISED FEBRUARY 2003
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION†
synchronous operation (continued)
If two or more SG2524 regulators are operated synchronously, all oscillator output terminals must be tied
together. The oscillator programmed for the minimum clock period is the master from which all the other
SG2524s operate. In this application, the CTRT values of the slaved regulators must be set for a period
approximately 10% longer than that of the master regulator. In addition, CT (master) = 2 CT (slave) to ensure
that the master output pulse, which occurs first, has a longer pulse duration and, subsequently, resets the slave
regulators.
voltage reference
The 5-V internal reference can be employed by use of an external resistor divider network to establish a
reference common-mode voltage range (1.8 V to 3.4 V) within the error amplifiers (see Figure 6), or an external
reference can be applied directly to the error amplifier. For operation from a fixed 5-V supply, the internal
reference can be bypassed by applying the input voltage to both the VCC and VREF terminals. In this
configuration, however, the input voltage is limited to a maximum of 6 V.
To Negative
Output Voltage
REF OUT
5 kΩR1
To Positive
Output Voltage
R2
5 kΩ
REF OUT
+
–
+
–
5 kΩ
5 kΩ
R2
R1
VO+2.5 V R1 )R2
R1 VO+2.5 V ǒ1*R2
R1Ǔ
2.5 V 2.5 V
Figure 6. Error-Amplifier Bias Circuits
error amplifier
The error amplifier is a differential-input transconductance amplifier. The output is available for dc gain control
or ac phase compensation. The compensation node (COMP) is a high-impedance node (RL = 5 MΩ). The gain
of the amplifier is AV = (0.002 Ω–1)RL and easily can be reduced from a nominal 10,000 by an external shunt
resistance from COMP to ground. Refer to Figure 3 for data.
compensation
COMP, as previously discussed, is made available for compensation. Since most output filters introduce one
or more additional poles at frequencies below 200 Hz, which is the pole of the uncompensated amplifier,
introduction of a zero to cancel one of the output filter poles is desirable. This can be accomplished best with
a series RC circuit from COMP to ground in the range of 50 kΩ and 0.001 µF. Other frequencies can be canceled
by use of the formula f ≈ 1/RC.
†Throughout these discussions, references to the SG2524 apply also to the SG3524.
SLVS077D – APRIL 1977 – REVISED FEBRUARY 2003
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION†
shutdown circuitry
COMP also can be employed to introduce external control of the SG2524. Any circuit that can sink 200 µA can
pull the compensation terminal to ground and, thus, disable the SG2524.
In addition to constant-current limiting, CURR LIM+ and CURR LIM– also can be used in transformer-coupled
circuits to sense primary current and shorten an output pulse should transformer saturation occur. CURR LIM–
also can be grounded to convert CURR LIM+ into an additional shutdown terminal.
current limiting
A current-limiting sense amplifier is provided in the SG2524. The current-limiting sense amplifier exhibits a
threshold o f 200 mV ±25 mV and must be applied in the ground line since the voltage range of the inputs is limited
to 1 V to –1 V. Caution should be taken to ensure the –1-V limit is not exceeded by either input, otherwise,
damage to the device may result.
Foldback current limiting can be provided with the network shown in Figure 7. The current-limit schematic is
shown in Figure 8.
VO
Rs
R2
R1EMIT 2
EMIT 1
SG2524
IO(max) +1
Rsǒ200 mV )
VOR2
R1 )R2Ǔ
IOS +200 mV
Rs
CURR LIM+
CURR LIM–
11
14
5
4
Figure 7. Foldback Current Limiting for Shorted Output Conditions
Constant-Current Source
CURR LIM+
COMP CT
Comparator
Error Amplifier
CURR LIM–
Figure 8. Current-Limit Schematic
†Throughout these discussions, references to the SG2524 apply also to the SG3524.
SLVS077D – APRIL 1977 – REVISED FEBRUARY 2003
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION†
output circuitry
The SG2524 contains two identical npn transistors, the collectors and emitters of which are uncommitted. Each
transistor has antisaturation circuitry that limits the current through that transistor to a maximum of 100 mA for
fast response.
general
There are a wide variety of output configurations possible when considering the application of the SG2524 as
a voltage-regulator control circuit. They can be segregated into three basic categories:
DCapacitor-diode-coupled voltage multipliers
DInductor-capacitor-implemented single-ended circuits
DTransformer-coupled circuits
Examples of these categories are shown in Figures 9, 10, and 11, respectively. Detailed diagrams of specific
applications are shown in Figures 12–15.
D1
VI
VO
VI < VO
VI
D1
VO
VI > VO
D1
VI
–VO
| +VI | > | – VO |
Figure 9. Capacitor-Diode-Coupled Voltage-Multiplier Output Stages
†Throughout these discussions, references to the SG2524 apply also to the SG3524.
SLVS077D – APRIL 1977 – REVISED FEBRUARY 2003
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION†
VIVO
VI > VO
VI
VI < VO
VO
VI–VO
| +VI | < | – VO |
Figure 10. Single-Ended Inductor Circuit
VO
Push-Pull
VO
VI
Flyback
ÏÏ
VI
Figure 11. Transformer-Coupled Outputs
†Throughout these discussions, references to the SG2524 apply also to the SG3524.
SLVS077D – APRIL 1977 – REVISED FEBRUARY 2003
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION†
SG2524
COMP
.
CURR LIM+
EMIT 2
COL 2
COL 1
EMIT 1
GND
OSC OUT
CT
RT
REF OUT
IN+
IN–
0.01 µF
0.1 µF
5 kΩ
5 kΩ
2 kΩ
50 µF
–5 V
20 mA
1N916
1N91620 µF
1N916
15 kΩ
VCC = 15 V
VCC
CURR LIM–
SHUTDOWN
+
1
2
16
6
7
10
3
11
12
13
14
4
5
9
8
15
5 kΩ
+
Figure 12. Capacitor-Diode Output Circuit
VCC = 5 V
0.1 µF
1 MΩ
300 Ω
1N916
1N916
20T
200 Ω
–15 V
20 mA
15 V
50 µF
50 µF
50T
50T
TIP29A
1 Ω
1N916 620 Ω
510 Ω
2N2222
4.7 µF
0.001 µF
0.02 µF
5 kΩ
2 kΩ
100 µF
5 kΩ
5 kΩ
SG2524
VCC
OSC OUT
GND COMP
CURR LIM+
EMIT 2
COL 2
COL 1
EMIT 1
CURR LIM–
CT
RT
REF OUT
IN+
IN–
+
+
SHUTDOWN
25 kΩ
+
+
1
2
16
6
7
10
3
11
12
13
14
4
5
9
15
8
Input
Return
Figure 13. Flyback Converter Circuit
†Throughout these discussions, references to the SG2524 apply also to the SG3524.
SLVS077D – APRIL 1977 – REVISED FEBRUARY 2003
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION†
Input Return 0.1 Ω
3 kΩ1N3880
500 µF
1 A
5 V
0.9 mH
TIP115
SG2524
VCC
OSC OUT
GND
VCC = 28 V
0.001 µF
50 kΩ
5 kΩ
3 kΩ
0.1 µF
0.02 µF
5 kΩ
CURR LIM+
EMIT 2
COL 2
COL 1
EMIT 1
SHUT
DOWN
CT
RT
REF OUT
IN+
IN–
CURR LIM–
COMP
1
2
16
6
7
10
3
11
12
13
14
4
5
9
15
8
5 kΩ
5 kΩ+
Figure 14. Single-Ended LC Circuit
5 kΩ
0.01 µF
0.1 µF
2 kΩ
5 kΩ
20 kΩ
1500 µF
0.1 Ω
100 µF
+
–
5 A
5 V
20T
20T
5T
5T
TIR101A 1 mH
TIP31A
100 Ω
100 Ω
TIP31A
1W
1 kΩ
VCC = 28 V
GND
OSC OUT
VCC
SG2524
CURR LIM+
EMIT 2
COL 2
COL 1
EMIT 1
SHUT
DOWN
CT
RT
REF OUT
IN+
IN–
CURR LIM–
COMP
1
2
16
6
7
10
3
11
12
13
14
4
5
9
15
8
5 kΩ
5 kΩ
0.001 µF
+
+
1W
1 kΩ
Figure 15. Push-Pull Transformer-Coupled Circuit
†Throughout these discussions, references to the SG2524 apply also to the SG3524.
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
SG2524D ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SG2524DE4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SG2524DG4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SG2524DR ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SG2524DRE4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SG2524DRG4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SG2524J OBSOLETE CDIP J 16 TBD Call TI Call TI
SG2524N ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SG2524NE4 ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SG3524D ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SG3524DE4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SG3524DG4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SG3524DR ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SG3524DRE4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SG3524DRG4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SG3524J OBSOLETE CDIP J 16 TBD Call TI Call TI
SG3524N ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SG3524NE4 ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SG3524NS OBSOLETE SO NS 16 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SG3524NSR ACTIVE SO NS 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SG3524NSRE4 ACTIVE SO NS 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SG3524NSRG4 ACTIVE SO NS 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
PACKAGE OPTION ADDENDUM
www.ti.com 4-Jun-2007
Addendum-Page 1
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 4-Jun-2007
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SG2524DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
SG3524DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
SG3524NSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SG2524DR SOIC D 16 2500 333.2 345.9 28.6
SG3524DR SOIC D 16 2500 333.2 345.9 28.6
SG3524NSR SO NS 16 2000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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