intel. PRELIMINARY 27C020 2M (256K x 8) CHMOS EPROM g JEDEC Approved EPROM Pinouts m Fast Programming 32-Pin DIP, 32-Pin PLCC Quick-Pulse Programming Simple Upgrade from Lower Algorithm Densities Programming Time as Fast as 30 = Complete Upgrade Capability to Higher Seconds Densities m High-Performance a Versatile EPROM Features _ ae, val + 10% cc CMOS and TTL Compatibility 30 mA Icc Active Two Line Control mw Surface Mount Packaging Available Smallest 1 Mbit Footprint in SMT Intels 27C020 is a 5V-only, 2,097,152-bit Erasable Programmable Read Only Memory, organized as 262,144 words of 8 bits each. It is pin compatible with lower density DIP EPROMs (JEDEC) and provides for simple upgrades to 8 Mbits in the future in both DIP and PLCC. The 270020 represents state-of-the-art 1 micron CMOS manufacturing technology while providing unequaled performance. Its 150 ns speed (tacc) offers no-wait-state operation with high performance CPUs in applica- tions ranging from numerical control to office automation to telecommunications. Intel offers two DIP profile options to meet your prototyping and production needs. The windowed ceramic DIP (CERDIP) package provides erasability and reprogrammability for prototyping and early production. Once the design is in full production, the plastic DIP (PDIP) one-time programmable part provides a lower cost alterna- tive that is well adapted for auto insertion. - In addition to the JEDEC 32-lead DIP package, Intel also offers a 32-lead PLCC version of the 27C020. This one-time-programmable surface mount device is ideal where board space consumption is a major concern or ' where surface mount manufacturing technology is being implemented across an entire production line. The 270020 is equally at home in both a TTL or CMOS environment. It programs as fast as 30 seconds using Intels industry leading Quick-Pulse Programming algorithm. Veco DATA OUTPUTS cc 05-0, GND o> (ncn eo ttttttt OE OUTPUT ENABLE PGM| CHIP ENABLE CE | prog LOGIC OUTPUT BUFFERS y . Y-GATING DECODER . Ag-Ay7 |_| ADDRESS 4 x : om BIT INPUTS |_| DECODER | CELL MATRIX e a 290226-1 Figure 1. Block Diagram September 1990 5-72 Order Number: 290226-003ntl: 27c020 PRELIMINARY Pin Names Ao-Atg | ADDRESSES [Ce CHIP ENABLE OE OUTPUT ENABLE Oy-07 | OUTPUTS PGM | PROGRAM NG NO INTERNAL CONNECT SMbit | 4Mbit | 1Mbit | 512K { 256K : 270020 256K 512K IMbit | 4Mbit | SMbit Aig Vpp Vpp Vpp 41 32D Vee Veco | Voc |} Vec Aw | Ate | Ate ; AveQ2 31D on | PEM | Ate Ais At Ais Ais Ais Vpp Ais] 30D Ay7 Voc Voc N.C. Ai7 Ai7 Aa Are Ai2 Ai2 Ai2 Ayt4 2 Ay Aw Aya Ava | Ava Ava A7 Ar Ar Az Ar a7Qs 28D Ay3 Aig Aig Ais | Ai Aig Ag As Ag Ag Ae agCi6 2705 Ag Ag Ag As Ag Ag As As As As As asC7 2609 Ay Ag Ag Ag Ag Ag Ag A Ag Ag | Aa Acs 25 PI Ay An Ant An | Aw] An Ag Ag Ag Ag Ag A319 24 5 OE | GE/Vpp} OE | SE | GE/Vpp A2 Ag Ag Ao- Ag 4,10 23 Daj Ato A10 Ato Ato Aio Ay Ay Ay Ay Ay aot 2p cE CE CE CE cE Ao Ao Ao Ao Ao Aoky 12 2175 0, O7 O7: O7 07 O7 Oo Oo Oo Oo Oo S13 20971 0g Og O65 Og Os Os Oo, | oO O; O; O1 Orcs 19F os Os Os Os | Os Os O2 Oo Oe Og Oo 02415 1897) 04 O, Os O% Oa O% GND | GND | GND } GND | GND GND 16 170g O3 Os 03 | 03 Og 290226-2 Figure 2. DIP Pin Configuration N27C020(256K x8) 1M (128Kx8)] Avz | Ais | Ate | Ypp alist fel], 32 LEAD PLCC 0,450" x0.550" TOP VIEW 290226-9 Figure 3. PLCC Lead Configuration 5-73intel. 270020 PRELIMINARY ABSOLUTE MAXIMUM RATINGS* NOTICE: This data sheet contains preliminary intor- ; mation on new products in production. The specifica- Operating Temperature ............. OC to 70C(1) tions are subject to change without notice. Verify with Temperature Under Bias ........... 10C to 80C your local intel Sales office that you have the latest data sheet before finalizi design. Storage Temperature............. 65C to 125C eet before finalizing a design *WARNING: Stressing the device beyond the Absolute Maximum Ratings may cause permanent damage. These are stress ratings only. Operation beyond the Voltage on Any Pin (except Ag, Vcc and Vpp) with Respect to GND .......... 0.6V to 6.5V(2) Operating Conditions is not recommended and ex: Voltage on Ag with tended exposure beyond the Operating Conditions Respectto GND ............. 0.6V to 13.0V(2) May affect device reliability. Vpp Program Voltage with Respect to GND........... 0.6V to 14V(2) Voc Supply Voltage with Respect toGND .......... 0.6V to 7.0V(2) READ OPERATION DC CHARACTERISTICS Vcc = 5.0V + 10% Symbol Parameter Notes Min Typ Max Unit Test Condition I Input Load Current 7 0.01 1.0 BA | Vin = OV to 5.5V lLo Output Leakage Current +10 BA | Vout = OV to 5.5V Isp Voc Standby Current 1.0 mA | CE = Vin | 100 pA | CE = Voc +0.2V loc Voc Operating Current 3 30 mA | CE = Vic f = MHz, lout = OMA Ipp Vpp Operating Current 3 10 pA | Vpp = Voc los Output Short Circuit Current; 4, 6 100 mA ViL Input Low Voltage -0.5 0.8 Vv Vin Input High Voltage 2.0 Voc + .0.5| V Vo Output Low Voltage 0.45 V |lo. = 2.1mA Vou __ | Output High Voltage 2.4 V lion = 400 pA Vpp Vpp Operating Voltage 5 1Vcc 0.7 Voc Vv NOTES: 1. Operating temperature is for commerciai product defined by this specification. 2. Minimum DC input voltage is 0.5V on input/output pins. During transitions, this level may undershoot to 2.0V for periods <20 ns. Maximum DC voltage on input/output pins is Voc + 0.5V which, during transitions, may overshoot to Voc + 2.0V for periods <20 ns. 3. Maximum active power usage is the sum Ipp + Icc. Maximum current is with outputs Op to O7 unloaded. 4, Output shorted for no more than one second. No more than one output shorted. at a time. 5. Vpp may be connected directly to Voc, or may be one diode voitage drop below Voc. Vcc must be applied simultaneously or before Vpp and removed simultaneously or after Vpp. 6. Sampled, not 100% tested. 7. Typical limits are at Voc = 5V, Ta = 28C. 5-74intel. a7c020 PRELIMINARY READ OPERATION AC CHARACTERISTICS(1) Voc = 5:0V'10% : : 27020-200V10 Versions(4) Voc + 10% 27C020-150V10 P27C020-200V10 _N27C020-200v10 | Unit Symbol Parameter Notes Min. | Max Min Max tacc Address to Output Delay 150 200 ns toe CE to Output Delay 2. 150 200 ns toe OE to Output Delay 2 60 70 ns tor OE High to Output High Z 3 60. OUT 60 | ns ton Output Hold from 3 0 0 ns Addresses, CE or OE Change-Whichever is First NOTES: 1. See AC Input/Output Reference Waveform for timing measurements. 2. OE may be delayed up to tce-tog after the falling edge of CE without impact on toe. 3. Sampled, not 100% tested. , 4. Model number prefixes: No Prefix = CERDIP, P = PDIP, N = PLCC. 5-75intel. orco20 PRELIMINARY CAPACITANCE(!) 1, = 25C, f= 1MHz. . Parameter Unit | Conditions =0V Vv = 0V = 0V NOTES: 1. Sampied, not 100% tested. 2. Typical vatues are for Ta = 25C and nominal supply voltages. AC INPUT/OUTPUT REFERENCE WAVEFORM AC TESTING LOAD CIRCUIT 24 = ss 7 1.3V INPUT , TEST POINTS OUTPUT x 0.8 = i <Xe 1N914 0.45 4S 290226-4 RL AC testing inputs are driven at Von (2.4 VrT1) for a logic 4 and eee OUT Vor (0.45 Viz) for a logic 0. Input timing begins at Viq (2.0 TEST Vit and Vi_ (0.8 Vy7_). Output timing ends at V4 and Vi_. Input C. rise and fall times (10% to 90%) <10 ns. C., = 100 pF 290226-5 C, Includes Jig Capacitance RL = 33 KN AC WAVEFORMS Vi) ee te Vin re, tog Vi eee TTY Of ve LA toe , i | >< | face: fou WIGHZ outev HIGH Z VALID OUTPUT a NAA 290226-6 5-76intel. 270020 PRELIMINARY DEVICE OPERATION | The Mode Selection table lists 27C020 operating modes. Read Mode. requires a- single 5V_ pawer r supply. All inputs, except Vee and Vpp, and Ag during intgligent Identifier Mode, are TTL or CMOS... Table 1. Mode Selection Mode Notes | CE | OE | PGM | Ay | Ao | Vpp | Voc | Outputs Read a Mit Mie Xx X | X | Veo | Veo | Dour Output Disable Vin 4 Vie x x X | Veco | Voc | HighZ Standby Vin | xX Xx X X | Voc | Voc | HighZ Program 2 Vit Vin Vit xX X 1 Vpp | Vep. |. Diy Program Verity Vi} Mn {| -Vin | X | xX | Vee | Vop | Dour Program Inhibit Vin | X X X xX | Vpp | Vep | HighZ inteligent | Manufacturer | 2,3 | Vii | Vit x Vin | Vi | Veo | Voc 89H Identifier | Device Vi | Ve} X | Vp | Va | Voc | Veo | 34H NOTES: 1. X can be Vit or Vix 2. See DC Programming Characteristics for Vcp, Vpp, and Vio voltages. 3. AyAg, Aqo-Aq7 = ViL Read Mode The 270020 has two control functions; both must be enabled to obtain data at the outputs. CE is the pow- er control and device select: controls. the output buffers to gate data to the outputs. With addresses stable, the address access time (tacc) equals: the delay from CE to output (tcf). Outputs display valid data tog after OEs falling edge, assuming tacc and tce times are met. Vec must be applied simultaneously or before Vpp and removed simultaneously or after Vpp. Two Line Output Control EPROMs are often used in larger memory arrays. Intel provides two control inputs to accommodate multiple memory connections. Two-line control pro- vides for: 5-77 a) lowest possible memory power dissipation b) complete assurance that data bus contention will not occur To efficiently use these two control inputs, an ad- dress decoder should enable CE, while OE should be connected to.all memory devices and the -sys- tems READ control line. This assures that only se- lected memory devices have active outputs while deselected memory devices are in Standby Mode. Standby Mode Standb Mode substantially reduces Voc current. When CE = Vin the outputs are in a high imped- ance state, independent of OE.nel. 27C020 PRELIMINARY Program Mode Caution: Exceeding 14V on Vpp will permanently damage the device. . Initially, and after each erasure, all EPROM bits are in the 1 state. Data is introduced by selectively programming Os into the desired bit locations. Al- though only Os are programmed, the data word . can contain both 1s and Os. Ultraviolet light era- sure is the only way to change Os to 1s. Program mode is entered when Vpp is raised to 12.75V. Data is introduced b lying an 8-bit word to the output pins. Pulsing tow while CE = Vic and OF = Viq programs that data into the device. Program Verify A verify should be performed following a program operation to determine that bits have been correctly programmed. With Vcc at 6.25V, a substantial pro- gen margin is ensured. The verify is performed with at Vy and PGM at Vj}. Valid data is available tog after OF falls low. Program Inhibit Program Inhibit Mode allows parallel ramming of multiple EPROMs with different data. CE-high in- aS Oa te of non-targeted devices. Except for CE, parallel EPROMs may have common inputs. inteligent Identifier Mode The intgligent Identifier Mode will determine an EPROMs manufacturer and device type, allowing programming equipment to automatically match a device with its proper programming algorithm. This mode is activated when a programmer forces 12V +0.5V on Ag. With CE, OF, A;-Ag, and Aio- Ai7 at Vit, Ao = Vit will present the manufacturer code and Ag = Vip the device code. This mode functions in the 25C +5C ambient temperature range required during programming. UPGRADE PATH Future upgrade to 4-Mbit and 8-Mbit densities are easily accomplished due to the standardized pin configuration of the 27C020. When the 27C020 is in Read Mode, the PGM input becomes non-functional. This allows address line Ayg to be routed directly 5-78 to this input in anticipation of future density up- grades. A jumper between Voc and Aj4g allows fur- ther upgrade using the. Vpp pin. Systems designed for 2-Mbit program memories today can be upgrad- ed to higher densities (4-Mbit and 8-Mbit) in the fu- ture with no circuit board changes. SYSTEM CONSIDERATIONS EPROM power switching characteristics require careful device decoupling. System designers are. in- terested in 3 supply current issues: standby current levels (isg), active current levels (Icc), and transient current peaks produced by falling and rising edges of CE. Transient current magnitudes depend on the device outputs capacitive and inductive. loading. Two-line contro! and proper decoupling capacitor selection will suppress. transient voltage peaks. Each device should have a 0.1 j.F ceramic capacitor connected between its Vcc and GND. This high fre- quency, low inherent-inductance capacitor should be placed as close as possible to the device. Addi- tionally, for every 8 devices, a 4.7 uF electrolytic capacitor should be placed at the arrays power sup- ply connection between Vcc and GND. The bulk ca- pacitor will overcome voltage slumps caused by PC board inductances. ERASURE CHARACTERISTICS Erasure begins when EPROMs are exposed to light with wavelengths shorter than approximately 4000 Angstroms (A). It should be noted that sunlight and certain fluorescent lamps have wavelengths in the 3000A-4000A range. Data shows that constant ex- posure to room jevel fluorescent lighting can erase an EPROM in approximately 3 years, while it takes approximately 1 week when exposed to direct sun- light. If the device is exposed to these lighting condi- tions for extended periods, opaque labels should.be placed over the window to prevent unintentional era- sure. The recommended erasure procedure is exposure to ultraviolet light of wavelength 2537A. The inte- grated dose (UV intensity x exposure time) for era- sure should be a minimum of 15 Wsec/cm?. Erasure time is approximately 15 to 20 minutes using an ul- traviolet lamp with a 12000 .W/cm2 power rating. The EPROM should be placed within 1 inch of the lamp tubes. An EPROM can be permanently dam- aged if the integrated dose exceeds 7258 Wsec/ cm2 (1 week @ 12000 pW/cmz2).270020 PRELIMINARY Voc Vpp INCREMENT ADDRESS ADDRESS = FIRST LOCATION 6.25V 12.75V PROGRAM ONE 100 uss PULSE DEVICE FAILED DEVICE PASSED 290226-7 Figure 4. Quick-Pulse Programming Algorithm Quick-Pulse Programming Algorithm The Quick-Pulse programming algorithm programs Intels 27C020. Developed to substantially reduce programming throughput, this algorithm can program the 270020 as fast as 30 seconds. Actual program- ming time depends on programmer overhead. 5-79 The Quick-Pulse programming algorithm employs a 100 xs pulse followed by a byte verification to deter- mine when the addressed byte has been successful- ly programmed. The aigorithm terminates if 25 at- tempts fail to program a byte. The entire program pulse/byte verify sequence is performed with Vpp = 12.75V and Vcc = 6.25V. When programming is complete, all bytes are com- pared to the original data with Vcc = Vpp = 5.0V.intel. 270020 PRELIMINARY DC PROGRAMMING CHARACTERISTICS Ta = 25C +6C Symbol Parameter Notes | Min Typ | Max | Unit Test Condition tut Input Load Current 1 pA | Vin = Vic Or Vin Icp Voc Program Current 1 40 | mA | CE = PGM = Vit Ipp Vpp Program Current 1 50 mA | CE = PGM = Vit VIL Input Low Voltage 0.1 0.8 Vv ViH Input High Voltage 2.4 6.5 Vv VoL Output Low Voltage (Verify) 0.45 Vv lo, = 2.1mA Vou Output High Voltage (Verify) 3.5. Vv loy = 2.5mA Vip Ag intgligent Identifier Voltage 11.5 12.0 | 12.5 Vv Vpp Vpp Program Voltage 2,3 12.5 |} 12.75 | 13.0 Vop Vcc Supply Voltage (Program) 2 6.0 6.25 6.5 Vv AC PROGRAMMING CHARACTERISTICS(4) T, = 25C +5C Symboi Parameter Notes - Min Typ Max Unit tycs Voc Setup Time 2 2 pS tyes Vpp Setup Time 2 2 ps tcEs CE Setup Time 2 ps tas Address Setup Time 2 pS tos Data Setup Time 2 ps tpw PGM Program Pulse Width 95 100 105 BS tov Data Hold Time 2 ps toes OE Setup Time pS toe Data Valid from OE 5 150 ns tpFp OE High to Output High Z 5,6 130 ns taH Address Hold Time ps NOTES: 1. Maximum current is with outputs OgO7 unloaded. 2. Vop must be applied simultaneously or before Vpp and removed simultaneously or after Vpp. 3. When programming, a 0.1 F capacitor is required across Vpp and GND to suppress spurious voltage transients which can damage the device. 4. See AC Input/Output Reference Waveform for timing measurements. 5. tog and tpgp are device characteristics but must be accommodated by the programmer. 6. Sampied, not 100% tested. 5-80intel. 27C020 PRELIMINARY PROGRAMMING WAVEFORMS VERIFY ~-_-} Vv . w ADDRESSES , ADDRESS STABLE 7 Va - e2 Lee - "AS ___pal tan Nin p HIGH Z Z ~ ; DATA DATA IN STABLE 4 DATA OUT VALID. vie . ee tore tos > Jag OH I 1 12.78V = Vep ] 5.0V tues 6.25V : ~~ Vec ] 5.0 + tvcs, > Vw ce + Vin as tees __] ent nen < PGM Vu tow Lg {OES toe View Pe ae _~ _ Vi 290226-8 REVISION HISTORY Number Description 003 Revised general datasheet structure, text to improve clarity Added PDIP package Combined TTL/NMOS and CMOS Read Operation Characteristics tables Revised classification from Advance Information to Preliminary Deleted 4 Meg and.8 Meg PLCC pinout references. Deleted EXPRESS page 5-81