STH13N120K5-2AG Datasheet Automotive-grade N-channel 1200 V, 630 m typ., 12 A, MDmesh K5 Power MOSFET in an HPAK2 package Features TAB 2 Order code VDS RDS(on) max. ID PTOT STH13N120K5-2AG 1200 V 690 m 12 A 219 W 3 1 H2PAK-2 D(TAB) G(1) * * AEC-Q101 qualified Industry's lowest RDS(on) x area * * * * Industry's best FoM (figure of merit) Ultra-low gate charge 100% avalanche tested Zener-protected Applications * S(2,3) NCHG1DTABS23TZ Switching applications Description This very high voltage N-channel Power MOSFET is designed using MDmesh K5 technology based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance and ultra-low gate charge for applications requiring superior power density and high efficiency. Product status link STH13N120K5-2AG Product summary Order code STH13N120K5-2AG Marking 13N120K5 Package HPAK-2 Packing Tape and reel DS12917 - Rev 2 - September 2019 For further information contact your local STMicroelectronics sales office. www.st.com STH13N120K5-2AG Electrical ratings 1 Electrical ratings Table 1. Absolute maximum ratings Symbol Value Unit Gate-source voltage 30 V Drain current at TC = 25 C 12 A Drain current at TC = 100 C 7.6 A Drain current (pulsed) 28 A PTOT Total power dissipation at TC = 25 C 219 W IAR(2) Maximum current during repetitive or single-pulse avalanche 4 A VGS ID IDM (1) (3) Parameter EAS Single-pulse avalanche energy 600 mJ dv/dt(4) Peak diode recovery voltage slope 4.5 V/ns dv/dt(5) MOSFET dv/dt ruggedness 50 V/ns -55 to 150 C Value Unit Tj Tstg Operating junction temperature range Storage temperature range 1. Pulse width limited by safe operating area. 2. Pulse width limited by TJmax. 3. Starting TJ = 25 C, ID=IAR, VDD= 50 V 4. ISD 12 A, di/dt 100 A/s, VDS (peak) V(BR)DSS 5. VDS 960 V Table 2. Thermal data Symbol Parameter Rthj-case Thermal resistance junction-case 0.57 C/W Rthj-pcb(1) Thermal resistance junction-pcb 30 C/W 1. When mounted on FR-4 board of 1 inch, 2oz Cu. DS12917 - Rev 2 page 2/15 STH13N120K5-2AG Electrical characteristics 2 Electrical characteristics (TCASE = 25 C unless otherwise specified) Table 3. On/off states Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage VGS = 0 V, ID = 1 mA Min. Typ. 1200 Zero gate voltage drain current 1 A 100 A 5 A 4 5 V 630 690 m Min. Typ. Max. Unit - 1360 - pF - 105 - pF - 0.9 - pF - 118 - pF - 42 - pF f = 1 MHz, ID = 0 A - 3.2 - VGS = 0 V, VDS = 1200 V, Tc = 125 C(1) IGSS Unit V VGS = 0 V, VDS = 1200 V IDSS Max. Gate body leakage current VDS = 0 V, VGS = 20 V VGS(th) Gate threshold voltage VDS = VGS, ID = 100 A RDS(on) Static drain-source on- resistance VGS = 10 V, ID= 6 A 3 1. Defined by design, not subject to production test. Table 4. Dynamic Symbol Parameter Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Co(tr)(1) Co(er)(2) Time-related equivalent capacitance Energy-related equivalent capacitance Test conditions VGS = 0 V, VDS = 100 V, f = 1 MHz VGS = 0 V, VDS = 0 to 960 V RG Intrinsic gate resistance Qg Total gate charge VDD = 960 V, ID = 12 A - 41.1 - nC Gate-source charge VGS = 0 to 10 V - 9.9 - nC Gate-drain charge (see Figure 14. Test circuit for gate charge behavior) - 25.2 - nC Qgs Qgd 1. Time-related is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS. 2. Energy-related is defined as a constant equivalent capacitance giving the same stored energy as Coss when VDS increases from 0 to 80% VDSS . Table 5. Switching times Symbol td(on) tr td(off) tf DS12917 - Rev 2 Parameter Test conditions Min. Typ. Max. Unit Turn-on delay time VDD = 600 V, ID = 6 A, - 17.5 - ns Rise time RG = 4.7 , VGS = 10 V - 9 - ns Turn-off delay time (see Figure 13. Test circuit for resistive load switching times and Figure 18. Switching time waveform) - 56 - ns - 22 - ns Fall time page 3/15 STH13N120K5-2AG Electrical characteristics Table 6. Source drain diode Symbol ISD ISDM (1) Parameter Test conditions Min. Typ. Max. Unit Source-drain current - 12 A Source-drain current (pulsed) - 28 A 1.5 V Forward on voltage ISD = 12 A, VGS = 0 V - trr Reverse recovery time ISD = 12 A, VDD = 60 V - 650 ns Qrr Reverse recovery charge di/dt = 100 A/s, - 11 C Reverse recovery current (see Figure 15. Test circuit for inductive load switching and diode recovery times) - 33 A trr Reverse recovery time ISD = 12 A,VDD = 60 V - 950 ns Qrr Reverse recovery charge di/dt = 100 A/s, Tj = 150 C - 13.5 C Reverse recovery current (see Figure 15. Test circuit for inductive load switching and diode recovery times) - 31.5 A Min Typ. VSD IRRM IRRM 1. Pulsed: pulse duration = 300s, duty cycle 1.5% Table 7. Gate-source Zener diode Symbol V(BR)GSO Parameter Gate-source breakdown voltage Test conditions IGS = 1 mA, ID = 0 A 30 Max. - Unit V The built-in back-to-back Zener diodes have been specifically designed to enhance the ESD capability of the device. The Zener voltage is appropriate for efficient and cost-effective intervention to protect the device integrity. These integrated Zener diodes thus eliminate the need for external components. DS12917 - Rev 2 page 4/15 STH13N120K5-2AG Electrical characteristics (curves) 2.1 Electrical characteristics (curves) Figure 1. Safe operating area ID (A) Figure 2. Maximum transient thermal impedance ZthJ-C (C/W) GADG100920191147SOA duty = 0.5 tp =1s DS are (o a n) O is pera lim tio ite n d in by th R is 10 -1 tp =10s tp =100s 10 -2 V(BR)DSS Single pulse, TC =25C TJ 150C, VGS =10V tp =10ms 10 0 10 1 10 2 10 3 VDS (V) Figure 3. Typical output characteristics ID (A) VGS = 10V 10 -2 10 -1 tp (s) Figure 4. Typical transfer characteristics GADG100920191149TCH VDS = 20V 8 4 4 VGS = 6V 4 8 12 16 20 24 VDS (V) Figure 5. Typical gate charge characteristics VDS (V) GADG100920191150QVG VGS 0 4 RDS(on) (m) 10 690 8 670 600 6 650 400 4 630 200 2 610 VDD = 960V, ID = 12A Qg 1000 Qgd Qgs 8 16 24 32 40 0 Qg (nC) 5 6 7 8 9 VGS (V) Figure 6. Typical drain-source on-resistance (V) DS12917 - Rev 2 10 -3 12 VGS = 7V 8 0 0 10 -4 16 12 800 10 -5 20 VGS = 8V 16 0 0 10 -3 10 -6 24 VGS = 9V 20 RthJ-C = 0.57 C/W ID (A) GADG100920191149RCC-50 24 Single pulse tp =1ms -2 10 -1 0.1 0.05 RDS(on) max. 10 -1 10 0.2 IDM 10 1 10 0 GADG100920191147ZTH 0.3 0.4 590 0 GADG100920191158RID VGS =10V 2 4 6 8 10 12 ID (A) page 5/15 STH13N120K5-2AG Electrical characteristics (curves) Figure 7. Typical capacitance characteristics C (pF) Figure 8. Typical output capacitance stored energy GIPD300320151232MT Eoss (J) GADG100920191159CVR 24 10 4 CISS 10 3 20 16 10 2 f = 1 MHz COSS 10 1 CRSS 10 0 12 8 4 10 -1 10 -1 10 0 10 1 10 2 VDS (V) 10 3 Figure 9. Normalized gate threshold vs temperature GIPD300320151241MT VGS(th) 0 0 200 400 800 600 1000 VDS(V) Figure 10. Normalized on-resistance vs temperature GIPD300320151244MT RDS(on) (norm) (norm) ID=100A VGS=10V 2.5 1.2 2.0 1.0 1.5 0.8 1.0 0.6 0.4 -75 0.5 -25 25 75 125 TJ(C) Figure 11. Normalized breakdown voltage vs temperature GIPD300320151249MT V(BR)DSS (norm) 0.0 -75 -25 25 125 75 TJ(C) Figure 12. Typical reverse diode forward characteristics GIPD300320151251MT VSD (V) TJ=-50C ID=1mA 0.9 1.08 TJ=25C 0.8 1.00 0.7 TJ=150C 0.92 0.84 -75 DS12917 - Rev 2 0.6 -25 25 75 125 TJ(C) 0.5 2 4 6 8 10 ISD(A) page 6/15 STH13N120K5-2AG Test circuits 3 Test circuits Figure 13. Test circuit for resistive load switching times Figure 14. Test circuit for gate charge behavior VDD 12 V 2200 + F 3.3 F VDD VD VGS 1 k 100 nF RL IG= CONST VGS RG 47 k + pulse width D.U.T. 2.7 k 2200 F pulse width D.U.T. 100 VG 47 k 1 k AM01469v1 AM01468v1 Figure 15. Test circuit for inductive load switching and diode recovery times D G A D.U.T. S 25 A L A B B 3.3 F D G + VD 100 H fast diode B Figure 16. Unclamped inductive load test circuit RG 1000 + F 2200 + F VDD 3.3 F VDD ID D.U.T. S D.U.T. Vi _ pulse width AM01471v1 AM01470v1 Figure 18. Switching time waveform Figure 17. Unclamped inductive waveform ton V(BR)DSS td(on) VD toff td(off) tr tf 90% 90% IDM VDD 10% 0 ID VDD AM01472v1 VGS 0 VDS 10% 90% 10% AM01473v1 DS12917 - Rev 2 page 7/15 STH13N120K5-2AG Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. DS12917 - Rev 2 page 8/15 STH13N120K5-2AG HPAK-2 package information 4.1 HPAK-2 package information Figure 19. HPAK-2 package outline 8159712_8 DS12917 - Rev 2 page 9/15 STH13N120K5-2AG HPAK-2 package information Table 8. HPAK-2 package mechanical data Dim. mm Min. Typ. Max. A 4.30 4.70 A1 0.03 0.20 C 1.17 1.37 e 4.98 5.18 E 0.50 0.90 F 0.78 0.85 H 10.00 10.40 H1 7.40 L 15.30 L1 1.27 1.40 L2 4.93 5.23 L3 6.85 7.25 L4 1.5 1.7 M 2.6 2.9 R 0.20 0.60 V 0 8 - 7.80 15.80 Figure 20. HPAK-2 recommended footprint 8159712_8 Note: DS12917 - Rev 2 Dimensions are in mm. page 10/15 STH13N120K5-2AG Packing information 4.2 HPAK-2 packing information Figure 21. Tape outline 10 pitches cumulative tolerance on tape +/- 0.2 mm T P0 Top cover tape P2 D E F K0 W B0 A0 P1 D1 User direction of feed R Bending radius User direction of feed AM08852v2 DS12917 - Rev 2 page 11/15 STH13N120K5-2AG Packing information Figure 22. Reel outline T REEL DIMENSIONS 40 mm min. Access hole At slot location B D C N A G measured Tape slot In core for Full radius At hub Tape start Table 9. Tape and reel mechanical data Tape Dim. DS12917 - Rev 2 Reel mm mm Dim. Min. Max. Min. Max. A0 10.5 10.7 A B0 15.7 15.9 B 1.5 D 1.5 1.6 C 12.8 D1 1.59 1.61 D 20.2 E 1.65 1.85 G 24.4 F 11.4 11.6 N 100 K0 4.8 5.0 T P0 3.9 4.1 P1 11.9 12.1 Base quantity 1000 P2 1.9 2.1 Bulk quantity 1000 R 50 T 0.25 0.35 W 23.7 24.3 330 13.2 26.4 30.4 page 12/15 STH13N120K5-2AG Revision history Table 10. Document revision history Date Version 14-Feb-2019 1 Changes First release. Updated title and features in cover page. 10-Sep-2019 2 Updated Section 1 Electrical ratings, Section 2 Electrical characteristics and Section 2.1 Electrical characteristics (curves). Minor text changes. DS12917 - Rev 2 page 13/15 STH13N120K5-2AG Contents Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 4.1 HPAK-2 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.2 HPAK-2 packing information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 DS12917 - Rev 2 page 14/15 STH13N120K5-2AG IMPORTANT NOTICE - PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST's terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers' products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. (c) 2019 STMicroelectronics - All rights reserved DS12917 - Rev 2 page 15/15