LM4924MM/NOPB - NATIONAL SEMICONDUCTOR

LM4924

LM4924 2-Cell Battery, 40mW Per Channel Output Capacitor-Less (OCL)

StereoHeadphone Audio Amplifier

Literature Number: SNAS272A

LM4924 June 1, 2009

2 Cell Battery, 40mW Per Channel Output Capacitor-Less

(OCL) Stereo Headphone Audio Amplifier

General Description

The LM4924 is a Output Capacitor-Less (OCL) stereo head-

phone amplifier, which when connected to a 3.0V supply,

delivers 40mW per channel to a 16Ω load with less than 1%

THD+N.

With the LM4924 packaged in the MM and SD packages, the

customer benefits include low profile and small size. These

packages minimizes PCB area and maximizes output power.

The LM4924 features circuitry that reduces output transients

(“clicks” and “pops”) during device turn-on and turn-off, and

Mute On and Off. An externally controlled, low-power con-

sumption, active-low shutdown mode is also included in the

LM4924. Boomer audio power amplifiers are designed specif-

ically to use few external components and provide high quality

output power in a surface mount packages.

Key Specifications

■OCL output power

■ (RL = 16Ω, VDD = 3.0V, THD+N = 1%) 40mW (typ)

■Micropower shutdown current 0.1µA (typ)

■Supply voltage operating range 1.5V < VDD < 3.6V

■PSRR 100Hz, VDD = 3.0V, AV = 2.5 66dB (typ)

Features

■2-cell 1.5V to 3.6V battery operation

■OCL mode for stereo headphone operation

■Unity-gain stable

■“Click and pop” suppression circuitry for shutdown On and

Off transients

■Active low micropower shutdown

■Thermal shutdown protection circuitry

Applications

■Portable two-cell audio products

■Portable two-cell electronic devices

Typical Application

20121057

FIGURE 1. Block Diagram

Boomer® is a registered trademark of National Semiconductor Corporation.

LM4924 2 Cell Battery, 40mW Per Channel Output Capacitor-Less (OCL) Stereo Headphone

Audio Amplifier

Connection Diagrams

MSOP Package

20121058

Top View

Order Number LM4924MM

See NS Package Number MUB10A for MSOP

MSOP Marking

20121006

Z- Plant Code

X - Date Code

T - Die Traceability

G - Boomer Family

B7 - LM4924MM

SD Package

20121052

Top View

Order Number LM4924SD

See NS Package Number SDA10A

SD Marking

20121007

Z - Plant Code

X - Date Code

T - Die Traceability

Bottom Line - Part Number

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LM4924

Typical Connections

20121059

FIGURE 2. Typical OCL Output Configuration Circuit

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LM4924

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Supply Voltage 3.8V

Storage Temperature −65°C to +150°C

Input Voltage −0.3V to VDD +0.3V

Power Dissipation (Note 2) Internally limited

ESD Susceptibility(Note 3) 2000V

ESD Susceptibility on pin 7, 8, and 9

(Note 3) 2kV

ESD Susceptibility (Note 4) 200V

Junction Temperature 150°C

Solder Information

Small Outline Package Vapor

Phase (60sec) 215°C

Infrared (15 sec) 220°C

See AN-450 “Surface Mounting and their Effects on Product

Reliablilty” for other methods of soldering surface mount

devices.

Thermal Resistance

θJA (typ) MUB10A 175°C/W

θJA (typ) SDA10A 73°C/W

Operating Ratings

Temperature Range

TMIN ≤ TA ≤ TMAX −40°C ≤ TA ≤ +85°C

Supply Voltage 1.5V ≤ VDD ≤ 3.6V

Electrical Characteristics VDD = 3.0V (Notes 1, 5)

The following specifications apply for the circuit shown in Figure 2, unless otherwise specified. AV = 2.5, RL = 16Ω.Limits

apply for TA = 25°C.

Symbol Parameter Conditions LM4924 Units

(Limits)

Typical Limit

(Note 6) (Note 7)

IDD Quiescent Power Supply Current VIN = 0V, IO = 0A, RL = ∞ (Note 8) 1.5 1.9 mA (max)

ISD Shutdown Current VSHUTDOWN = GND 0.1 1 μA (max)

VOS Output Offset Voltage 1 10 mV (max)

POOutput Power (Note 9) f = 1kHz, per channel

OCL (Figure 2), THD+N = 1% 40 30 mW (min)

VNO Output Voltage Noise 20Hz to 20kHz, A-weighted, Figure 2 13 µVRMS

THD PO = 10mW 0.1 0.5 %

Crosstalk Freq = 1kHz 45 35 dB (min)

PSRR Power Supply Rejection Ratio VRIPPLE = 200mVP-P sine wave

Freq = 100Hz, OCL 66 58 dB (min)

TWAKE-UP Wake-Up Time 1.5V ≤ VDD ≤ 3.6V, Fig 2 230 msec

VIH Control Logic High 1.5V ≤ VDD ≤ 3.6V 0.7VDD V (min)

VIL Control Logic Low 1.5V ≤ VDD ≤ 3.6V 0.3VDD V (max)

Mute

Attenuation

1VPP Reference, RIN = 20k, RFB = 50k 90 70 dB

Electrical Characteristics VDD = 1.8V (Notes 1, 5)

The following specifications apply for the circuit shown in Figure 2, unless otherwise specified. AV = 2.5, RL = 16Ω. Limits

apply for TA = 25°C.

Symbol Parameter Conditions LM4924 Units

(Limits)

Typical Limit

(Note 6) (Note 7)

IDD Quiescent Power Supply Current VIN = 0V, IO = 0A, RL = ∞ (Note 8) 1.4 mA (max)

ISD Shutdown Current VSHUTDOWN = GND 0.1 μA (max)

VOS Output Offset Voltage 1 mV (max)

POOutput Power (Note 9)

f = 1kHz

OCL Per channel, Fig. 2, Freq = 1kHz

THD+N = 1%

10 mW

VNO Output Voltage Noise 20Hz to 20kHz, A-weighted, Figure 2 10 µVRMS

THD PO = 5mW 0.1 %

Crosstalk Freq = 1kHz 45 dB (min)

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LM4924

Symbol Parameter Conditions LM4924 Units

(Limits)

Typical Limit

(Note 6) (Note 7)

PSRR Power Supply Rejection Ratio VRIPPLE = 200mVP-P sine wave

Freq = 100Hz, OCL 66 dB

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is

functional, but do not guarantee specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions

which guarantee specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not guaranteed for parameters

where no limit is given, however, the typical value is a good indication of device performance.

Note 2: The maximum power dissipation is dictated by TJMAX, θJA, and the ambient temperature TA and must be derated at elevated temperatures. The maximum

allowable power dissipation is PDMAX = (TJMAX − TA)/θJA. For the LM4924, TJMAX = 150°C. For the θJAs, please see the Application Information section or the

Absolute Maximum Ratings section.

Note 3: Human body model, 100pF discharged through a 1.5kΩ resistor.

Note 4: Machine model, 220pF–240pF discharged through all pins.

Note 5: All voltages are measured with respect to the ground (GND) pins unless otherwise specified.

Note 6: Typicals are measured at 25°C and represent the parametric norm.

Note 7: Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis.

Note 8: The quiescent power supply current depends on the offset voltage when a practical load is connected to the amplifier.

Note 9: Output power is measured at the device terminals.

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LM4924

Typical Performance Characteristics

THD+N vs Frequency

VDD = 1.8V, PO = 5mW, RL = 16Ω

20121013

THD+N vs Frequency

VDD = 1.8V, PO = 5mW, RL = 32Ω

20121014

THD+N vs Frequency

VDD = 3.0V, PO = 10mW, RL = 16Ω

20121015

THD+N vs Frequency

VDD = 3.0V, PO = 10mW, RL = 32Ω

20121016

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LM4924

THD+N vs Output Power

VDD = 1.8V, RL = 16Ω, f = 1kHz

20121017

THD+N vs Output Power

VDD = 1.8V, RL = 32Ω, f = 1kHz

20121018

THD+N vs Output Power

VDD = 3.0V, RL = 16Ω, f = 1kHz

20121019

THD+N vs Output Power

VDD = 3.0V, RL = 32Ω, f = 1kHz

20121020

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LM4924

Power Supply Rejection Ratio

VDD = 1.8V, RL = 16Ω,

Vripple = 200mVp-p, Input Terminated into 10Ω load

20121011

Power Supply Rejection Ratio

VDD = 3.0V, RL = 16Ω,

Vripple = 200mVp-p, Input Terminated into 10Ω load

20121012

Noise Floor

VDD = 1.8V, RL = 16Ω

20121009

Noise Floor

VDD = 3.0V, RL = 16Ω

20121010

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LM4924

Channel Sepration

RL = 16Ω

20121008

Output Power vs Load Resistance

f = 1kHz. from top to bottom:

VDD = 3.0V, 10%THD+N; VDD = 3.0V, 1%THD+N

VDD = 1.8V, 10%THD+N; VDD = 1.8V, 1%THD+N

20121021

Output Power vs Supply Voltage

RL = 16Ω, from top to bottom:

THD+N = 10%; THD+N = 1%

20121022

Output Power vs Supply Voltage

RL = 32Ω, from top to bottom:

THD+N = 10%; THD+N = 1%

20121031

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LM4924

Power Dissipation vs Output Power

VDD = 1.8V, f = 1kHz, from top to bottom:

RL = 16Ω; RL = 32Ω

20121024

Power Dissipation vs Output Power

VDD = 3.0V, f = 1kHz, from top to bottom:

RL = 16Ω; RL = 32Ω

20121025

Supply Current vs Supply Voltage

20121026

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LM4924

Application Information

ELIMINATING OUTPUT COUPLING CAPACITORS

Typical single-supply audio amplifiers that drive single-ended

(SE) headphones use a coupling capacitor on each SE out-

put. This output coupling capacitor blocks the half-supply

voltage to which the output amplifiers are typically biased and

couples the audio signal to the headphones. The signal return

to circuit ground is through the headphone jack's sleeve.

The LM4924 eliminates these output coupling capacitors.

VoC is internally configured to apply a 1/2VDD bias voltage to

a stereo headphone jack's sleeve. This voltage matches the

quiescent voltage present on the VoA and VoB outputs that

drive the headphones. The headphones operate in a manner

similar to a bridge-tied-load (BTL). The same DC voltage is

applied to both headphone speaker terminals. This results in

no net DC current flow through the speaker. AC current flows

through a headphone speaker as an audio signal's output

amplitude increases on the speaker's terminal.

The headphone jack's sleeve is not connected to circuit

ground. Using the headphone output jack as a line-level out-

put will place the LM4924's bandgap 1/2VDD bias on a plug's

sleeve connection. This presents no difficulty when the ex-

ternal equipment uses capacitively coupled inputs. For the

very small minority of equipment that is DC-coupled, the

LM4924 monitors the current supplied by the amplifier that

drives the headphone jack's sleeve. If this current exceeds

500mAPK, the amplifier is shutdown, protecting the LM4924

and the external equipment.

BYPASS CAPACITOR VALUE SELECTION

Besides minimizing the input capacitor size, careful consid-

eration should be paid to value of CBYPASS, the capacitor

connected to the BYPASS pin. Since CBYPASS determines

how fast the LM4924 settles to quiescent operation, its value

is critical when minimizing turn-on pops. The slower the

LM4924's outputs ramp to their quiescent DC voltage (nomi-

nally VDD/2), the smaller the turn-on pop. Choosing CB equal

to 4.7µF along with a small value of Ci (in the range of 0.1µF

to 0.47µF), produces a click-less and pop-less shutdown

function. As discussed above, choosing Ci no larger than

necessary for the desired bandwidth helps minimize clicks

and pops. This ensures that output transients are eliminated

when power is first applied or the LM4924 resumes operation

after shutdown.

OPTIMIZING CLICK AND POP REDUCTION

PERFORMANCE

The LM4924 contains circuitry that eliminates turn-on and

shutdown transients ("clicks and pops"). For this discussion,

turn-on refers to either applying the power supply voltage or

when the micro-power shutdown mode is deactivated.

As the VDD/2 voltage present at the BYPASS pin ramps to its

final value, the LM4924's internal amplifiers are configured as

unity gain buffers. An internal current source charges the ca-

pacitor connected between the BYPASS pin and GND in a

controlled, linear manner. Ideally, the input and outputs track

the voltage applied to the BYPASS pin. The gain of the inter-

nal amplifiers remains unity until the voltage on the bypass

pin reaches VDD/2. As soon as the voltage on the bypass pin

is stable, the device becomes fully operational and the am-

plifier outputs are reconnected to their respective output pins.

Although the BYPASS pin current cannot be modified, chang-

ing the size of CBYPASS alters the device's turn-on time. There

is a linear relationship between the size of CBYPASS and the

turn-on time. Here are some typical turn-on times for various

values of CBYPASS.

AMPLIFIER CONFIGURATION EXPLANATION

As shown in Figure 1, the LM4924 has three operational am-

plifiers internally. Two of the amplifier's have externally con-

figurable gain while the other amplifier is internally fixed at the

bias point acting as a unity-gain buffer. The closed-loop gain

of the two configurable amplifiers is set by selecting the ratio

of Rf to Ri. Consequently, the gain for each channel of the IC

AV = -(Rf/Ri)

By driving the loads through outputs VO1 and VO2 with VO3

acting as a buffered bias voltage the LM4924 does not require

output coupling capacitors. The typical single-ended amplifier

configuration where one side of the load is connected to

ground requires large, expensive output coupling capacitors.

A configuration such as the one used in the LM4924 has a

major advantage over single supply, single-ended amplifiers.

Since the outputs VO1, VO2, and VO3 are all biased at 1/2

VDD, no net DC voltage exists across each load. This elimi-

nates the need for output coupling capacitors that are re-

quired in a single-supply, single-ended amplifier configura-

tion. Without output coupling capacitors in a typical single-

supply, single-ended amplifier, the bias voltage is placed

across the load resulting in both increased internal IC power

dissipation and possible loudspeaker damage.

POWER DISSIPATION

Power dissipation is a major concern when designing a suc-

cessful amplifier. A direct consequence of the increased pow-

er delivered to the load by a bridge amplifier is an increase in

internal power dissipation. The maximum power dissipation

for a given application can be derived from the power dissi-

pation graphs or from Equation 1.

PDMAX = 4(VDD) 2 / (π2RL) (1)

It is critical that the maximum junction temperature TJMAX of

150°C is not exceeded. Since the typical application is for

headphone operation (16Ω impedance) using a 3.3V supply

the maximum power dissipation is only 138mW. Therefore,

power dissipation is not a major concern.

POWER SUPPLY BYPASSING

As with any amplifier, proper supply bypassing is important

for low noise performance and high power supply rejection.

The capacitor location on the power supply pins should be as

close to the device as possible.

Typical applications employ a 3.0V regulator with 10µF tan-

talum or electrolytic capacitor and a ceramic bypass capacitor

which aid in supply stability. This does not eliminate the need

for bypassing the supply nodes of the LM4924. A bypass ca-

pacitor value in the range of 0.1µF to 1µF is recommended

for CS.

MICRO POWER SHUTDOWN

The voltage applied to the SHUTDOWN pin controls the

LM4924's shutdown function. Activate micro-power shutdown

by applying a logic-low voltage to the SHUTDOWN pin. When

active, the LM4924's micro-power shutdown feature turns off

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LM4924

the amplifier's bias circuitry, reducing the supply current. The

trigger point is 0.4V (max) for a logic-low level, and 1.5V (min)

for a logic-high level. The low 0.1µA (typ) shutdown current is

achieved by applying a voltage that is as near as ground as

possible to the SHUTDOWN pin. A voltage that is higher than

ground may increase the shutdown current.

There are a few ways to control the micro-power shutdown.

These include using a single-pole, single-throw switch, a mi-

croprocessor, or a microcontroller. When using a switch,

connect an external 100kΩ pull-up resistor between the

SHUTDOWN pin and VDD. Connect the switch between the

SHUTDOWN pin and ground. Select normal amplifier opera-

tion by opening the switch. Closing the switch connects the

SHUTDOWN pin to ground, activating micro-power shut-

down. The switch and resistor guarantee that the SHUT-

DOWN pin will not float. This prevents unwanted state

changes. In a system with a microprocessor or microcon-

troller, use a digital output to apply the control voltage to the

SHUTDOWN pin. Driving the SHUTDOWN pin with active

circuitry eliminates the pull-up resistor.

SELECTING EXTERNAL COMPONENTS

Selecting proper external components in applications using

integrated power amplifiers is critical to optimize device and

system performance. While the LM4924 is tolerant of external

component combinations, consideration to component values

must be used to maximize overall system quality.

The LM4924 is unity-gain stable which gives the designer

maximum system flexibility. The LM4924 should be used in

low gain configurations to minimize THD+N values, and max-

imize the signal to noise ratio. Low gain configurations require

large input signals to obtain a given output power. Input sig-

nals equal to or greater than 1Vrms are available from sources

such as audio codecs. Very large values should not be used

for the gain-setting resistors. Values for Ri and Rf should be

less than 1MΩ. Please refer to the section, Audio Power

Amplifier Design, for a more complete explanation of proper

gain selection

Besides gain, one of the major considerations is the closed-

loop bandwidth of the amplifier. The input coupling capacitor,

Ci, forms a first order high pass filter which limits low frequen-

cy response. This value should be chosen based on needed

frequency response and turn-on time.

SELECTION OF INPUT CAPACITOR SIZE

Amplifiying the lowest audio frequencies requires a high value

input coupling capacitor, Ci. A high value capacitor can be

expensive and may compromise space efficiency in portable

designs. In many cases, however, the headphones used in

portable systems have little ability to reproduce signals below

60Hz. Applications using headphones with this limited fre-

quency response reap little improvement by using a high

value input capacitor.

In addition to system cost and size, turn-on time is affected

by the size of the input coupling capacitor Ci. A larger input

coupling capacitor requires more charge to reach its quies-

cent DC voltage. This charge comes from the output via the

feedback Thus, by minimizing the capacitor size based on

necessary low frequency response, turn-on time can be min-

imized. A small value of Ci (in the range of 0.1µF to 0.39µF),

is recommended.

USING EXTERNAL POWERED SPEAKERS

The LM4924 is designed specifically for headphone opera-

tion. Often the headphone output of a device will be used to

drive external powered speakers. The LM4924 has a differ-

ential output to eliminate the output coupling capacitors. The

result is a headphone jack sleeve that is connected to VO3

instead of GND. For powered speakers that are designed to

have single-ended signals at the input, the click and pop cir-

cuitry will not be able to eliminate the turn-on/turn-off click and

pop. Unless the inputs to the powered speakers are fully dif-

ferential the turn-on/turn-off click and pop will be very large.

AUDIO POWER AMPLIFIER DESIGN

A 30mW/32Ω Audio Amplifier

Given:

Power Output 30mWrms

Load Impedance 32Ω

Input Level 1Vrms

Input Impedance 20kΩ

A designer must first determine the minimum supply rail to

obtain the specified output power. By extrapolating from the

Output Power vs Supply Voltage graphs in the Typical Per-

formance Characteristics section, the supply rail can be

easily found.

Since 3.3V is a standard supply voltage in most applications,

it is chosen for the supply rail in this example. Extra supply

voltage creates headroom that allows the LM4924 to repro-

duce peaks in excess of 30mW without producing audible

distortion. At this time, the designer must make sure that the

power supply choice along with the output impedance does

no violate the conditions explained in the Power Dissipa-

tion section.

Once the power dissipation equations have been addressed,

the required differential gain can be determined from Equa-

tion 2.

(2)

From Equation 2, the minimum AV is 0.98; use AV = 1. Since

the desired input impedance is 20kΩ, and with AV equal to 1,

a ratio of 1:1 results from Equation 1 for Rf to Ri. The values

are chosen with Ri = 20kΩ and Rf = 20kΩ.

The last step in this design example is setting the amplifier's

−3dB frequency bandwidth. To achieve the desired ±0.25dB

pass band magnitude variation limit, the low frequency re-

sponse must extend to at least one-fifth the lower bandwidth

limit and the high frequency response must extend to at least

five times the upper bandwidth limit. The gain variation for

both response limits is 0.17dB, well within the ±0.25dB de-

sired limit. The results are an

fL = 100Hz/5 = 20Hz (3)

and an

fH = 20kHz x 5 = 100kHz (4)

As mentioned in the Selecting Proper External Compo-

nents section, Ri and Ci create a highpass filter that sets the

amplifier's lower bandpass frequency limit. Find the coupling

capacitor's value using Equation (3).

Ci ≥ 1/(2πR ifL) (5)

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LM4924

The result is

1/(2π*20kΩ*20Hz) = 0.397µF

Use a 0.39µF capacitor, the closest standard value.

The high frequency pole is determined by the product of the

desired frequency pole, fH, and the differential gain, AV. With

an AV = 1 and fH = 100kHz, the resulting GBWP = 100kHz

which is much smaller than the LM4924 GBWP of 11MHz.

This figure displays that if a designer has a need to design an

amplifier with higher differential gain, the LM4924 can still be

used without running into bandwidth limitations.

HIGHER GAIN AUDIO AMPLIFIER

20121029

FIGURE 3.

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LM4924

The LM4924 is unity-gain stable and requires no external

components besides gain-setting resistors, input coupling ca-

pacitors, and proper supply bypassing in the typical applica-

tion. However, if a very large closed-loop differential gain is

required, a feedback capacitor (Cf) may be needed to band-

width limit the amplifier. This feedback capacitor creates a low

pass filter that eliminates possible high frequency oscillations.

Care should be taken when calculating the -3dB frequency in

that an incorrect combination of Rf and Cf will cause frequency

response roll off before 20kHz. A typical combination of feed-

back resistor and capacitor that will not produce audio band

high frequency roll off is Rf = 20kΩ and Cf = 25pF. These

components result in a -3dB point of approximately 320kHz.

REFERENCE DESIGN BOARD and LAYOUT GUIDELINES

MSOP & SD BOARDS

20121030

FIGURE 4.

(Note: RPU2 is not required. It is used for test measurement purposes only.)

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LM4924

PCB LAYOUT GUIDELINES

This section provides practical guidelines for mixed signal

PCB layout that involves various digital/analog power and

ground traces. Designers should note that these are only

"rule-of-thumb" recommendations and the actual results will

depend heavily on the final layout.

Minimization of THD

PCB trace impedance on the power, ground, and all output

traces should be minimized to achieve optimal THD perfor-

mance. Therefore, use PCB traces that are as wide as pos-

sible for these connections. As the gain of the amplifier is

increased, the trace impedance will have an ever increasing

adverse affect on THD performance. At unity-gain (0dB) the

parasitic trace impedance effect on THD performance is re-

duced but still a negative factor in the THD performance of

the LM4924 in a given application.

GENERAL MIXED SIGNAL LAYOUT RECOMMENDATION

Power and Ground Circuits

For two layer mixed signal design, it is important to isolate the

digital power and ground trace paths from the analog power

and ground trace paths. Star trace routing techniques (bring-

ing individual traces back to a central point rather than daisy

chaining traces together in a serial manner) can greatly en-

hance low level signal performance. Star trace routing refers

to using individual traces to feed power and ground to each

circuit or even device. This technique will require a greater

amount of design time but will not increase the final price of

the board. The only extra parts required may be some

jumpers.

Single-Point Power / Ground Connections

The analog power traces should be connected to the digital

traces through a single point (link). A "PI-filter" can be helpful

in minimizing high frequency noise coupling between the ana-

log and digital sections. Further, place digital and analog

power traces over the corresponding digital and analog

ground traces to minimize noise coupling.

Placement of Digital and Analog Components

All digital components and high-speed digital signal traces

should be located as far away as possible from analog com-

ponents and circuit traces.

Avoiding Typical Design / Layout Problems

Avoid ground loops or running digital and analog traces par-

allel to each other (side-by-side) on the same PCB layer.

When traces must cross over each other do it at 90 degrees.

Running digital and analog traces at 90 degrees to each other

from the top to the bottom side as much as possible will min-

imize capacitive noise coupling and cross talk.

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LM4924

Physical Dimensions inches (millimeters) unless otherwise noted

MSOP Package

Order Number LM4924MM

NS Package Number MUB10A

SD Package

Order Number LM4924SD

NS Package Number SDA10A

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LM4924

Notes

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LM4924

Notes

LM4924 2 Cell Battery, 40mW Per Channel Output Capacitor-Less (OCL) Stereo Headphone

Audio Amplifier

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