4
12
2
13
6
75
10
911
14
15 13
G
G
1A
1B
2A
2B
3A
3B
4A
4B
1Y
2Y
3Y
4Y
Copyright © 2016, Texas Instruments Incorporated
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
AM26LS32AC, AM26LS32AI
,
AM26LS32AM
AM26LS33AC
,
AM26LS33AM
SLLS115F OCTOBER 1980REVISED SEPTEMBER 2016
AM26LS32Ax, AM26LS33Ax Quadruple Differential Line Receivers
1
1 Features
1 AM26LS32A Devices Meet or Exceed the
Requirements of ANSI TIA/EIA-422-B, TIA/EIA-
423-B, and ITU Recommendations V.10 and V.11
AM26LS32A Devices Have ±7-V Common-Mode
Range With ±200-mV Sensitivity
AM26LS33A Devices Have ±15-V Common-Mode
Range With ±500-mV Sensitivity
Input Hysteresis 50 mV Typical
Operate From a Single 5-V Supply
Low-Power Schottky Circuitry
3-State Outputs
Complementary Output-Enable Inputs
Input Impedance 12 kΩMinimum
Open Input Fail-Safe
2 Applications
High-Reliability Automotive Applications
Factory Automation
ATM and Cash Counters
Smart Grids
AC and Servo Motor Drives
3 Description
The AM26LS32Ax and AM26LS33Ax devices are
quadruple differential line receivers for balanced and
unbalanced digital data transmission. The enable
function is common to all four receivers and offers a
choice of active-high or active-low input. The 3-state
outputs permit connection directly to a bus-organized
system. Fail-safe design ensures that, if the inputs
are open, the outputs always are high.
Compared to the AM26LS32 and the AM26LS33, the
AM26LS32A and AM26LS33A incorporate an
additional stage of amplification to improve sensitivity.
The input impedance has been increased, resulting in
less loading of the bus line. The additional stage has
increased propagation delay; however, this does not
affect interchangeability in most applications.
The AM26LS32AC and AM26LS33AC are
characterized for operation from 0°C to 70°C. The
AM26LS32AI is characterized for operation from
–40°C to 85°C. The AM26LS32AM and
AM26LS33AM are characterized for operation over
the full military temperature range of –55°C to 125°C.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
AM26LS3xAC
AM26LS32AI PDIP (16) 19.30 mm × 6.35 mm
SOIC (16) 9.90 mm × 3.90 mm
AM26LS32AC SO (16) 10.20 mm × 5.30 mm
TSSOP (16) 5.00 mm × 4.40 mm
AM26LS3xAM CDIP (16) 21.34 mm × 6.92 mm
LCCC (20) 8.90 mm × 8.90 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram (Positive Logic)
Pin numbers are for D, N, NS, or PW packages only.
2
AM26LS32AC, AM26LS32AI
,
AM26LS32AM
AM26LS33AC
,
AM26LS33AM
SLLS115F OCTOBER 1980REVISED SEPTEMBER 2016
www.ti.com
Product Folder Links: AM26LS32AC AM26LS32AM AM26LS33AM
Submit Documentation Feedback Copyright © 1980–2016, Texas Instruments Incorporated
Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions......................... 3
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings ............................................................ 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information ................................................. 5
6.5 Electrical Characteristics........................................... 5
6.6 Switching Characteristics.......................................... 6
6.7 Dissipation Ratings ................................................... 6
6.8 Typical Characteristics.............................................. 7
7 Parameter Measurement Information .................. 9
8 Detailed Description............................................ 11
8.1 Overview................................................................. 11
8.2 Functional Block Diagram....................................... 11
8.3 Feature Description................................................. 11
8.4 Device Functional Modes........................................ 11
9 Application and Implementation ........................ 12
9.1 Application Information .......................................... 12
9.2 Typical Application.................................................. 12
10 Power Supply Recommendations ..................... 13
11 Layout................................................................... 13
11.1 Layout Guidelines ................................................. 13
11.2 Layout Example .................................................... 14
12 Device and Documentation Support................. 15
12.1 Related Links ........................................................ 15
12.2 Receiving Notification of Documentation Updates 15
12.3 Community Resources.......................................... 15
12.4 Trademarks........................................................... 15
12.5 Electrostatic Discharge Caution............................ 15
12.6 Glossary................................................................ 15
13 Mechanical, Packaging, and Orderable
Information........................................................... 15
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (October 2007) to Revision F Page
Added Applications section, ESD Ratings table, Feature Description section, Device Functional Modes,Application
and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation
Support section, and Mechanical, Packaging, and Orderable Information section................................................................ 1
Changed RθJA values in the Thermal Information table: 73 to 75.7 for (D), 67 to 45.3 (N), 64 to 75.8 (NS), and 108 to
102.7 (PW).............................................................................................................................................................................. 5
41Y
5G
6NC
72Y
82A
92B
10GND
11NC
123B
133A
14 3Y
15 G
16 NC
17 4Y
18 4A
19 4B
20 VCC
1 NC
2 1B
3 1A
Not to scale
11B 16 VCC
21A 15 4B
31Y 14 4A
4G 13 4Y
52Y 12 G
62A 11 3Y
72B 10 3A
8GND 9 3B
Not to scale
3
AM26LS32AC, AM26LS32AI
,
AM26LS32AM
AM26LS33AC
,
AM26LS33AM
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SLLS115F OCTOBER 1980REVISED SEPTEMBER 2016
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Submit Documentation FeedbackCopyright © 1980–2016, Texas Instruments Incorporated
5 Pin Configuration and Functions
D, J, N, NS, and PW Package
16-Pin SOIC, CDIP, PDIP, SO, and TSSOP
Top View FK Package
20-Pin LCCC
Top View
NC - No internal connection
Pin Functions
PIN I/O DESCRIPTION
NAME SOIC, CDIP, PDIP,
SO, TSSOP LCCC
1A 2 3 I RS422/RS485 differential input (noninverting)
1B 1 2 I RS422/RS485 differential input (inverting)
1Y 3 4 O Logic level output
2A 6 8 I RS422/RS485 differential input (noninverting)
2B 7 9 I RS422/RS485 differential input (inverting)
2Y 5 7 O Logic level output
3A 10 13 I RS422/RS485 differential input (noninverting)
3B 9 12 I RS422/RS485 differential input (inverting)
3Y 11 14 O Logic level output
4A 14 18 I RS422/RS485 differential input (noninverting)
4B 15 19 I RS422/RS485 differential input (inverting)
4Y 13 17 O Logic level output
G 12 15 I Active-Low select
G 4 5 I Active-High select
GND 8 10 Ground
NC 1, 6, 11, 16 No internal connection
VCC 16 20 Power supply
4
AM26LS32AC, AM26LS32AI
,
AM26LS32AM
AM26LS33AC
,
AM26LS33AM
SLLS115F OCTOBER 1980REVISED SEPTEMBER 2016
www.ti.com
Product Folder Links: AM26LS32AC AM26LS32AM AM26LS33AM
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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential voltages, are with respect to the network ground terminal.
(3) Differential voltage values are at the noninverting (A) input terminals with respect to the inverting (B) input terminals.
(4) 1.6 mm (1/16 inch) from case
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply voltage, VCC(2) 7 V
Input voltage, VIAny differential input ±25 V
Other inputs 7
Differential input voltage, VID(3) ±25 V
Continuous total power dissipation See Dissipation Ratings
Case temperature, TC, FK package (60 s) 260 °C
Lead temperature(4) D or N package (10 s) 260 °C
J package (60 s) 300
Storage temperature, Tstg –65 150 °C
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.2 ESD Ratings VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±500 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±2000
6.3 Recommended Operating Conditions
MIN NOM MAX UNIT
VCC Supply voltage AM26LS32AC, AM26LS32AI, AM26LS33AC 4.75 5 5.25 V
AM26LS32AM, AM26LS33AM 4.5 5 5.5
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
VIC Common-mode input voltage AM26LS32A ±7 V
AM26LS33A ±15
IOH High-level output current –440 µA
IOL Low-level output current 8 mA
TAOperating free-air temperature AM26LS32AC, AM26LS33AC 0 70 °CAM26LS32AI –40 85
AM26LS32AM, AM26LS33AM –55 125
5
AM26LS32AC, AM26LS32AI
,
AM26LS32AM
AM26LS33AC
,
AM26LS33AM
www.ti.com
SLLS115F OCTOBER 1980REVISED SEPTEMBER 2016
Product Folder Links: AM26LS32AC AM26LS32AM AM26LS33AM
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(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.4 Thermal Information
THERMAL METRIC(1) AM26LS3xAC, AM26LS32AI AM26LS32AC
UNITD (SOIC) N (PDIP) NS (SO) PW (TSSOP)
16 PINS 16 PINS 16 PINS 16 PINS
RθJA Junction-to-ambient thermal resistance 75.7 45.3 75.8 102.7 °C/W
RθJC(top) Junction-to-case (top) thermal
resistance 35 32.7 32.9 37.8 °C/W
RθJB Junction-to-board thermal resistance 33.3 25.3 36.6 47.7 °C/W
ψJT Junction-to-top characterization
parameter 6.6 17.8 6 3 °C/W
ψJB Junction-to-board characterization
parameter 33 25.1 36.3 47.1 °C/W
(1) All typical values are at VCC = 5 V, TA= 25°C, and VIC = 0.
(2) The algebraic convention, in which the less positive (more negative) limit is designated as minimum, is used in this data sheet for
threshold levels only.
(3) Not more than one output must be shorted to ground at a time, and duration of the short circuit must not exceed one second.
6.5 Electrical Characteristics
over recommended ranges of VCC, VIC, and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
VIT+ Positive-going input threshold
voltage VO= VOHmin, IOH = –440 µA AM26LS32A 0.2 V
AM26LS33A 0.5
VIT– Negative-going input threshold
voltage VO= 0.45 V , IOL = 8 mA AM26LS32A –0.2(2) V
AM26LS33A –0.5(2)
Vhys Hysteresis voltage
(VIT+ VIT–)50 mV
VIK Enable-input clamp voltage VCC = MIN, II= –18 mA –1.5 V
VOH High-level output voltage VCC = MIN, VID = 1 V,
VI(G) = 0.8 V, IOH = –440 µA
AM26LS32AC,
AM26LS33AC 2.7
V
AM26LS32AM,
AM26LS32AI,
AM26LS33AM 2.5
VOL Low-level output voltage VCC = MIN, VID = –1 V,
VI(G) = 0.8 V IOL= 4 mA 0.4 V
IOL= 8 mA 0.45
IOZ Off-state (high-impedance
state) output current VCC = MAX VO= 2.4 V 20 µA
VO= 0.4 V –20
IILine input current VI= 15 V, other input at –10 V to 15 V 1.2 mA
VI= –15 V, other input at –15 V to 10 V –1.7
II(EN) Enable input current VI= 5.5 V 100 µA
IHHigh-level enable current VI= 2.7 V 20 µA
ILLow-level enable current VI= 0.4 V –0.36 mA
riInput resistance VIC = –15 V to 15 V, one input to ac ground 12 15 kΩ
IOS Short-circuit output current(3) VCC = MAX –15 –85 mA
ICC Supply current VCC = MAX, all outputs disabled 52 70 mA
6
AM26LS32AC, AM26LS32AI
,
AM26LS32AM
AM26LS33AC
,
AM26LS33AM
SLLS115F OCTOBER 1980REVISED SEPTEMBER 2016
www.ti.com
Product Folder Links: AM26LS32AC AM26LS32AM AM26LS33AM
Submit Documentation Feedback Copyright © 1980–2016, Texas Instruments Incorporated
(1) All typical values are at VCC = 5 V, TA= 25°C, and VIC = 0.
6.6 Switching Characteristics
CL= 15 pF, VCC = 5 V, and TA= 25°C (see Parameter Measurement Information; unless otherwise noted)
PARAMETER MIN TYP(1) MAX UNIT
tPLH Propagation delay time, low-to-high-level output 20 35 ns
tPHL Propagation delay time, high-to-low-level output 22 35 ns
tPZH Output enable time to high level 17 22 ns
tPZL Output enable time to low level 20 25 ns
tPHZ Output disable time from high level 21 30 ns
tPLZ Output disable time from low level 30 40 ns
6.7 Dissipation Ratings
PACKAGE TA25°C
POWER RATING DERATION FACTOR
ABOVE TA= 25°C TA= 70°C
POWER RATING TA= 125°C
POWER RATING
FK 1375 mW 11 mW/°C 880 mW 275 mW
J 1375 mW 11 mW/°C 880 mW 275 mW
OutputVoltage,V (V)
O
EnableGVoltage(V)
Load=8k toGNDΩ
Low-LevelOutputVotlage,V ( )
OL V
Free-AirTemperature,T ( C)
A°
Load=8k toGNDΩ
EnableGVoltage(V)
OutputVoltage,V (V)
O
High-LevelOutputCurrent,I (mA)
OH
High-LevelOutputVoltage,V (V)
OH
Low-LevelOutputCurrent,I (mA)
OL
Low-LevelOutputVoltage,V (V)
OL
7
AM26LS32AC, AM26LS32AI
,
AM26LS32AM
AM26LS33AC
,
AM26LS33AM
www.ti.com
SLLS115F OCTOBER 1980REVISED SEPTEMBER 2016
Product Folder Links: AM26LS32AC AM26LS32AM AM26LS33AM
Submit Documentation FeedbackCopyright © 1980–2016, Texas Instruments Incorporated
6.8 Typical Characteristics
Figure 1. High-Level Output Voltage
vs High-Level Output Current Figure 2. Low-Level Output Voltage
vs Low-Level Output Current
Figure 3. Low-Level Output Voltage vs Free-Air Temperature Figure 4. Output Voltage vs Enable G Voltage
Figure 5. Output Voltage vs Enable G Voltage Figure 6. Output Voltage vs Enable G Voltage
InputVoltage,V (V)
I
InputCurrent,I (mA)
I
OutputVoltage,V (V)
O
DifferentialInputVoltage,V (mV)
ID
Load=1k toΩ VCC
OutputVoltage,V (V)
O
EnableGVoltage(V)
DifferentialInputVoltage,V (mV)
ID
OutputVoltage,V (V)
O
8
AM26LS32AC, AM26LS32AI
,
AM26LS32AM
AM26LS33AC
,
AM26LS33AM
SLLS115F OCTOBER 1980REVISED SEPTEMBER 2016
www.ti.com
Product Folder Links: AM26LS32AC AM26LS32AM AM26LS33AM
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Typical Characteristics (continued)
Figure 7. Output Voltage vs Enable G Voltage Figure 8. AM26LS32A Output Voltage
vs Differential Input Voltage
Figure 9. AM26LS33A Output Voltage
vs Differential Input Voltage
The unshaded area shows requirements of paragraph 4.2.1
of ANSI Standards EIA/TIA-422-B and EIA/TIA-423-B.
Figure 10. Input Current vs Input Voltage
S1 Open
S2 Closed
10%
90%
10%
90%
0
3 V
10%
10%
90% 90%
1.3 V1.3 V
1.3 V 1.3 V
3 V
0
5 ns
Enable G
Enable G
tPZH
1.3 V
Output
VOH
0.5 V
1.4 V
tPHZ S1 Closed
S2 Closed
See Note C
5 ns
tPHL
VOH
VOL
2.5 V
–2.5 V
tPLH
S1 and S2 Closed
Input
Output
00
1.3 V 1.3 V
5 k
S1
RL= 2 k
VCC
From Output
Under Test
CL
(see Note A) See Note B
S2
Test
Point
9
AM26LS32AC, AM26LS32AI
,
AM26LS32AM
AM26LS33AC
,
AM26LS33AM
www.ti.com
SLLS115F OCTOBER 1980REVISED SEPTEMBER 2016
Product Folder Links: AM26LS32AC AM26LS32AM AM26LS33AM
Submit Documentation FeedbackCopyright © 1980–2016, Texas Instruments Incorporated
7 Parameter Measurement Information
Figure 11. Test Circuit
Figure 12. Voltage Waveforms For tPLH, tPHL
Figure 13. Voltage Waveforms For tPHZ, tPZH
100 kΩ
100 kΩ
8.3 kΩ 85 Ω
20 kΩ 960 Ω
960 Ω
Copyright © 2016, Texas Instruments Incorporated
10%
90%
10%
90%
0
3 V
10%
10%
90% 90%
1.3 V1.3 V
1.3 V 1.3 V
3 V
0
tPZL
1.3 V
S1 Closed
S2 Open
S1 Closed
S2 Closed
VOL
0.5 V
tPLZ
Output
Enable G
Enable G
5 ns 5 ns
1.4 V
10
AM26LS32AC, AM26LS32AI
,
AM26LS32AM
AM26LS33AC
,
AM26LS33AM
SLLS115F OCTOBER 1980REVISED SEPTEMBER 2016
www.ti.com
Product Folder Links: AM26LS32AC AM26LS32AM AM26LS33AM
Submit Documentation Feedback Copyright © 1980–2016, Texas Instruments Incorporated
Parameter Measurement Information (continued)
A. CL includes probe and jig capacitance.
B. All diodes are 1N3064 or equivalent.
C. Enable G is tested with G high, G is tested with G low.
Figure 14. Voltage Waveforms For tPLZ, tPZL
Figure 15. Schematics of Inputs and Outputs
4
12
2
13
6
75
10
911
14
15 13
G
G
1A
1B
2A
2B
3A
3B
4A
4B
1Y
2Y
3Y
4Y
Copyright © 2016, Texas Instruments Incorporated
11
AM26LS32AC, AM26LS32AI
,
AM26LS32AM
AM26LS33AC
,
AM26LS33AM
www.ti.com
SLLS115F OCTOBER 1980REVISED SEPTEMBER 2016
Product Folder Links: AM26LS32AC AM26LS32AM AM26LS33AM
Submit Documentation FeedbackCopyright © 1980–2016, Texas Instruments Incorporated
8 Detailed Description
8.1 Overview
The AM26LS32 is a quadruple-differential line receiver that meets the necessary requirements for NSI TIA/EIA-
422-B, TIA/EIA-423-B, and ITU Recommendation V.10 and V.11. This device allows a low-power or low-voltage
MCU to interface with heavy machinery, subsystems, and other devices through long wires of up to 1000 m,
giving any design a reliable and easy-to-use connection. As any RS422 interface, the AM26LS32 works in a
differential voltage range, which enables very good signal integrity.
8.2 Functional Block Diagram
Figure 16. Logic Diagram (Positive Logic)
8.3 Feature Description
The device can be configured using the G and G logic inputs to select receiver output. The high voltage or logic
1 on the G pin allows the device to operate on an active-high, and having a low voltage or logic 0 on the G
enables active low operation. These are simple ways to configure the logic to match that of the receiving or
transmitting controller or microprocessor.
8.4 Device Functional Modes
The receivers implemented in these RS422 devices can be configured using the G and G logic pins to be
enabled or disabled. This allows users to ignore or filter out transmissions as desired.
(1) H = High level, L = Low level, X = Irrelevant, Z = High impedance (off), ? = Indeterminate
Table 1. Function Table, Each Receiver
DIFFERENTIAL
A–B ENABLES(1) OUTPUT(1)
Y
G G
VID VIT+ H X H
X L H
VIT– VID VIT+ H X ?
X L ?
VID VIT– H X L
X L L
X L H Z
Open H X H
X L H
Copyright © 2016, Texas Instruments Incorporated
12
AM26LS32AC, AM26LS32AI
,
AM26LS32AM
AM26LS33AC
,
AM26LS33AM
SLLS115F OCTOBER 1980REVISED SEPTEMBER 2016
www.ti.com
Product Folder Links: AM26LS32AC AM26LS32AM AM26LS33AM
Submit Documentation Feedback Copyright © 1980–2016, Texas Instruments Incorporated
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
When using AM26LS32A as a receiver, the AM26LS31AC can allow multiple AM26LS32As to be used causing
an increase in the amount of outputs.
9.2 Typical Application
Figure 17 shows a configuration with no termination. Although reflections are present at the receiver inputs at a
data signaling rate of 200 kbps with no termination, the RS-422-compliant receiver reads only the input
differential voltage and produces a clean signal at the output.
RTequals the characteristic impedance of the line.
Figure 17. Application Diagram
9.2.1 Design Requirements
Resistor and capacitor (if used) termination values are shown for each laboratory experiment, but vary from
system to system. For example, the termination resistor, RT, must be within 20% of the characteristic impedance,
ZO, of the cable and can vary from about 80 Ωto 120 Ω.
9.2.2 Detailed Design Procedure
Add a VCC bypass capacitor (0.1 µF or more). Either enable (G pin) input can turn on the receivers, so connect
the desired enable to a compatible logic line output. The other enable input must be tied to the inactive state
supply rail. If the receivers must always be active, then connect both enables to the supply rail such that at least
one is set to an active-state rail. VCC must be 5 V within 10% and logic inputs must provide TTL-compatible
voltage levels A & B Inputs can lead to an external connector or can be left unconnected. The last receiver on a
cable requires termination, either on-board or use as an external resistor. Unused Y outputs can be left
unconnected.
Free-AirTemperature,T (
A°C)
High-LevelOutputVoltage,V (
OH V)
I = 440 A
OH μ
13
AM26LS32AC, AM26LS32AI
,
AM26LS32AM
AM26LS33AC
,
AM26LS33AM
www.ti.com
SLLS115F OCTOBER 1980REVISED SEPTEMBER 2016
Product Folder Links: AM26LS32AC AM26LS32AM AM26LS33AM
Submit Documentation FeedbackCopyright © 1980–2016, Texas Instruments Incorporated
Typical Application (continued)
9.2.3 Application Curve
Figure 18. High-Level Output Voltage vs Free-Air Temperature
10 Power Supply Recommendations
Place 0.1-µF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-
impedance power supplies.
11 Layout
11.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices including:
Noise can propagate into analog circuitry through the power pins of the circuit as a whole, as well as the
operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing low impedance
power sources local to the analog circuitry.
Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as close
to the device as possible. A single bypass capacitor from V+ to ground is applicable for single supply
applications.
Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds, paying attention to the flow of the ground current.
To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If
it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular as
opposed to in parallel with the noisy trace.
Place the external components as close to the device as possible. Keeping RF and RG close to the inverting
input minimizes parasitic capacitance.
Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
VCC
0.1 F
VDD
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Reduce logic signal trace
when possible
4B
4A
4Y
G
3Y
3A
3B
2B
2A
2Y
G
1Y
1A
1B
Termination Resistor
14
AM26LS32AC, AM26LS32AI
,
AM26LS32AM
AM26LS33AC
,
AM26LS33AM
SLLS115F OCTOBER 1980REVISED SEPTEMBER 2016
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Product Folder Links: AM26LS32AC AM26LS32AM AM26LS33AM
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11.2 Layout Example
Figure 19. Layout with PCB Recommendations
15
AM26LS32AC, AM26LS32AI
,
AM26LS32AM
AM26LS33AC
,
AM26LS33AM
www.ti.com
SLLS115F OCTOBER 1980REVISED SEPTEMBER 2016
Product Folder Links: AM26LS32AC AM26LS32AM AM26LS33AM
Submit Documentation FeedbackCopyright © 1980–2016, Texas Instruments Incorporated
12 Device and Documentation Support
12.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL
DOCUMENTS TOOLS &
SOFTWARE SUPPORT &
COMMUNITY
AM26LS32AC Click here Click here Click here Click here Click here
AM26LS32AI Click here Click here Click here Click here Click here
AM26LS32AM Click here Click here Click here Click here Click here
AM26LS33AC Click here Click here Click here Click here Click here
AM26LS33AM Click here Click here Click here Click here Click here
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
PACKAGE OPTION ADDENDUM
www.ti.com 24-Aug-2018
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
5962-7802003M2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-
7802003M2A
AM26LS
32AMFKB
5962-7802003MEA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-7802003ME
A
AM26LS32AMJB
5962-7802003MFA ACTIVE CFP W 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-7802003MF
A
AM26LS32AMWB
5962-7802004M2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-
7802004M2A
AM26LS
33AMFKB
5962-7802004MEA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-7802004ME
A
AM26LS33AMJB
5962-7802004MFA ACTIVE CFP W 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-7802004MF
A
AM26LS33AMWB
AM26LS32ACD ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 26LS32AC
AM26LS32ACDE4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 26LS32AC
AM26LS32ACDG4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 26LS32AC
AM26LS32ACDR ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 26LS32AC
AM26LS32ACDRE4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 26LS32AC
AM26LS32ACDRG4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 26LS32AC
AM26LS32ACN ACTIVE PDIP N 16 25 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 AM26LS32ACN
PACKAGE OPTION ADDENDUM
www.ti.com 24-Aug-2018
Addendum-Page 2
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
AM26LS32ACNSR ACTIVE SO NS 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 26LS32A
AM26LS32ACNSRG4 ACTIVE SO NS 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 26LS32A
AM26LS32ACPW ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 SA32A
AM26LS32ACPWE4 ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 SA32A
AM26LS32ACPWR ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 SA32A
AM26LS32ACPWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 SA32A
AM26LS32AID ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 26LS32AI
AM26LS32AIDE4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 26LS32AI
AM26LS32AIDG4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 26LS32AI
AM26LS32AIDR ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 26LS32AI
AM26LS32AIDRG4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 26LS32AI
AM26LS32AIN ACTIVE PDIP N 16 25 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type -40 to 85 AM26LS32AIN
AM26LS32AMFKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-
7802003M2A
AM26LS
32AMFKB
AM26LS32AMJ ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 AM26LS32AMJ
AM26LS32AMJB ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-7802003ME
A
AM26LS32AMJB
AM26LS32AMWB ACTIVE CFP W 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-7802003MF
A
AM26LS32AMWB
PACKAGE OPTION ADDENDUM
www.ti.com 24-Aug-2018
Addendum-Page 3
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
AM26LS33ACD ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 26LS33AC
AM26LS33ACDG4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 26LS33AC
AM26LS33ACDR ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 26LS33AC
AM26LS33ACDRE4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 26LS33AC
AM26LS33ACN ACTIVE PDIP N 16 25 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 AM26LS33ACN
AM26LS33AMFKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-
7802004M2A
AM26LS
33AMFKB
AM26LS33AMJ ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 AM26LS33AMJ
AM26LS33AMJB ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-7802004ME
A
AM26LS33AMJB
AM26LS33AMWB ACTIVE CFP W 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-7802004MF
A
AM26LS33AMWB
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
PACKAGE OPTION ADDENDUM
www.ti.com 24-Aug-2018
Addendum-Page 4
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF AM26LS32A, AM26LS32AM, AM26LS33A, AM26LS33AM :
Catalog: AM26LS32A, AM26LS33A
Military: AM26LS32AM, AM26LS33AM
Space: AM26LS33A-SP, AM26LS33A-SP
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
Military - QML certified for Military and Defense Applications
Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
AM26LS32ACDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
AM26LS32ACDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
AM26LS32ACPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
AM26LS32AIDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
AM26LS33ACDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 24-Feb-2016
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
AM26LS32ACDR SOIC D 16 2500 367.0 367.0 38.0
AM26LS32ACDR SOIC D 16 2500 333.2 345.9 28.6
AM26LS32ACPWR TSSOP PW 16 2000 367.0 367.0 35.0
AM26LS32AIDR SOIC D 16 2500 333.2 345.9 28.6
AM26LS33ACDR SOIC D 16 2500 333.2 345.9 28.6
PACKAGE MATERIALS INFORMATION
www.ti.com 24-Feb-2016
Pack Materials-Page 2
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Mouser Electronics
Authorized Distributor
Click to View Pricing, Inventory, Delivery & Lifecycle Information:
Texas Instruments:
AM26LS32ACDR AM26LS32ACD AM26LS32ACN AM26LS32ACNSR AM26LS32ACDG4 AM26LS32ACDRG4
AM26LS32ACDE4 AM26LS32ACDRE4 AM26LS32ACNE4 AM26LS32ACNSRG4 AM26LS32ACPW
AM26LS32ACPWE4 AM26LS32ACPWR AM26LS32ACPWRE4 AM26LS32ACPWRG4