ATmega164A/PA/324A/PA/644A/PA/1284/P megaAVR(R) Data Sheet Introduction The ATmega164A/PA/324A/PA/644A/PA/1284/P is a low power, CMOS 8-bit microcontrollers based on the AVR(R) enhanced RISC architecture. The ATmega164A/PA/324A/PA/644A/PA/1284/P is a 40/49-pins device ranging from 16 KB to 128 KB Flash, with 1 KB to 16 KB SRAM, 512 Bytes to 4 KB EEPROM. By executing instructions in a single clock cycle, the devices achieve CPU throughput approaching one million instructions per second (MIPS) per megahertz, allowing the system designer to optimize power consumption versus processing speed. Features High-performance, low-power 8-bit AVR(R) Microcontroller Advanced RISC architecture 131 powerful Instructions - most single-clock cycle execution 32 x 8 general purpose working registers Fully static operation Up to 20MIPS throughput at 20MHz On-chip 2-cycle multiplier High endurance non-volatile memory segments 16/32/64/128KBytes of In-System Self-programmable Flash program memory 512/1K/2K/4KBytes EEPROM 1/2/4/16KBytes Internal SRAM Write/Erase Cycles: 10,000 Flash/ 100,000 EEPROM Data retention: 20 years at 85C/ 100 years at 25C(1) Optional Boot Code Section with Independent Lock Bits In-System Programming by On-chip Boot Program True Read-While-Write Operation Programming Lock for Software Security QTouch(R) Library Support Capacitive touch buttons, sliders and wheels QTouch and QMatrixTM acquisition Up to 64 sense channels JTAG (IEEE std. 1149.1 Compliant) Interface Boundary-scan Capabilities According to the JTAG Standard Extensive On-chip Debug Support Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 1 ATmega164A/PA/324A/PA/644A/PA/1284/P Peripheral Features Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes One/two 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode Real Time Counter with Separate Oscillator Six PWM Channels 8-channel, 10-bit ADC Differential mode with selectable gain at 1x, 10x or 200x Byte-oriented Two-wire Serial Interface Two Programmable Serial USART Master/Slave SPI Serial Interface Programmable Watchdog Timer with Separate On-chip Oscillator On-chip Analog Comparator Interrupt and Wake-up on Pin Change Special Microcontroller Features Power-on Reset and Programmable Brown-out Detection Internal Calibrated RC Oscillator External and Internal Interrupt Sources Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby and Extended Standby I/O and Packages 32 Programmable I/O Lines 40-pin PDIP, 44-lead TQFP, 44-pad VQFN/QFN/MLF 44-pad DRQFN 49-ball VFBGA Operating Voltages 1.8 - 5.5V Speed Grades 0 - 4MHz @ 1.8 - 5.5V 0 - 10MHz @ 2.7 - 5.5V 0 - 20MHz @ 4.5 - 5.5V Power Consumption at 1MHz, 1.8V, 25C Note: Active: 0.4mA Power-down Mode: 0.1A Power-save Mode: 0.6A (Including 32kHz RTC) 1. See "Data retention" on page 17 for details. 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 2 ATmega164A/PA/324A/PA/644A/PA/1284/P Table of Contents 1 2 Pin configurations ............................................................................................................... 11 1.1 Pinout - PDIP/TQFP/VQFN/QFN/MLF for ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P 11 1.2 Pinout - DRQFN for ATmega164A/164PA/324A/324PA ................................. 12 1.3 Pinout - VFBGA for ATmega164A/164PA/324A/324PA .................................. 13 Overview .................................................................................................................................... 13 2.1 Block diagram .................................................................................................. 14 2.2 Comparison between ATmega164A, ATmega164PA, ATmega324A, ATmega324PA, ATmega644A, ATmega644PA, ATmega1284 and ATmega1284P ...................................................................................................................................... 15 2.3 Pin Descriptions............................................................................................... 15 3 Resources 4 About code examples 5 Data retention ......................................................................................................................... 17 6 Capacitive touch sensing 7 AVR CPU Core 8 9 ................................................................................................................................ 17 ....................................................................................................... 17 ............................................................................................... 17 ....................................................................................................................... 18 7.1 Overview.......................................................................................................... 18 7.2 ALU - Arithmetic Logic Unit............................................................................. 19 7.3 Status Register ................................................................................................ 19 7.4 General Purpose Register File ........................................................................ 21 7.5 Stack Pointer ................................................................................................... 22 7.6 Instruction Execution Timing ........................................................................... 23 7.7 Reset and interrupt handling ........................................................................... 24 AVR memories ....................................................................................................................... 27 8.1 Overview.......................................................................................................... 27 8.2 In-System Reprogrammable Flash Program Memory ..................................... 27 8.3 SRAM data memory ........................................................................................ 28 8.4 EEPROM data memory ................................................................................... 30 8.5 I/O memory...................................................................................................... 31 8.6 Register Description ........................................................................................ 32 System clock and clock options ................................................................................ 38 9.1 Clock systems and their distribution ................................................................ 38 9.2 Clock Sources ................................................................................................. 39 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 3 ATmega164A/PA/324A/PA/644A/PA/1284/P 9.3 Low Power Crystal Oscillator........................................................................... 41 9.4 Full swing Crystal Oscillator ............................................................................ 42 9.5 Low Frequency Crystal Oscillator .................................................................... 43 9.6 Calibrated Internal RC Oscillator ..................................................................... 44 9.7 128kHz internal oscillator ................................................................................ 45 9.8 External clock .................................................................................................. 46 9.9 Timer/Counter Oscillator.................................................................................. 46 9.10 Clock Output Buffer ......................................................................................... 47 9.11 System Clock Prescaler .................................................................................. 47 9.12 Register description ......................................................................................... 48 10 Power management and sleep modes ................................................................... 50 10.1 Overview.......................................................................................................... 50 10.2 Sleep Modes.................................................................................................... 50 10.3 BOD disable(1) ................................................................................................. 51 10.4 Idle mode......................................................................................................... 51 10.5 ADC Noise Reduction mode............................................................................ 51 10.6 Power-down mode........................................................................................... 52 10.7 Power-save mode............................................................................................ 52 10.8 Standby mode ................................................................................................. 52 10.9 Extended Standby mode ................................................................................. 52 10.10 Power Reduction Register ............................................................................... 53 10.11 Minimizing Power Consumption ...................................................................... 53 10.12 Register description ......................................................................................... 55 11 System Control and Reset ............................................................................................. 58 11.1 Resetting the AVR ........................................................................................... 58 11.2 Internal Voltage Reference.............................................................................. 62 11.3 Watchdog Timer .............................................................................................. 63 11.4 Register description ......................................................................................... 66 12 Interrupts ................................................................................................................................... 69 12.1 Overview.......................................................................................................... 69 12.2 Interrupt Vectors in ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P 69 12.3 Register description ......................................................................................... 73 13 External Interrupts .............................................................................................................. 75 13.1 Overview.......................................................................................................... 75 13.2 Register description ......................................................................................... 76 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 4 ATmega164A/PA/324A/PA/644A/PA/1284/P 14 I/O-Ports ..................................................................................................................................... 80 14.1 Overview.......................................................................................................... 80 14.2 Ports as General Digital I/O ............................................................................. 81 14.3 Alternate Port Functions .................................................................................. 85 14.4 Register description ......................................................................................... 97 15 8-bit Timer/Counter0 with PWM .................................................................................. 99 15.1 Features .......................................................................................................... 99 15.2 Overview.......................................................................................................... 99 15.3 Timer/Counter Clock Sources ....................................................................... 100 15.4 Counter Unit .................................................................................................. 100 15.5 Output Compare unit ..................................................................................... 101 15.6 Compare Match Output unit .......................................................................... 102 15.7 Modes of operation........................................................................................ 103 15.8 Timer/Counter Timing diagrams .................................................................... 107 15.9 Register description ....................................................................................... 109 16 16-bit Timer/Counter1 and Timer/Counter3(1) with PWM .......................... 115 16.1 Features ........................................................................................................ 115 16.2 Overview........................................................................................................ 115 16.3 Accessing 16-bit Registers ............................................................................ 117 16.4 Timer/Counter Clock Sources ....................................................................... 120 16.5 Prescaler Reset ............................................................................................. 120 16.6 Counter Unit .................................................................................................. 121 16.7 Input Capture Unit ......................................................................................... 122 16.8 Output Compare units ................................................................................... 123 16.9 Compare Match Output unit .......................................................................... 126 16.10 Modes of Operation ....................................................................................... 127 16.11 Timer/Counter Timing diagrams .................................................................... 134 16.12 Register description ....................................................................................... 136 17 8-bit Timer/Counter2 with PWM and asynchronous operation ............. 146 17.1 Features ........................................................................................................ 146 17.2 Overview........................................................................................................ 146 17.3 Timer/Counter clock sources ......................................................................... 147 17.4 Counter unit ................................................................................................... 148 17.5 Output Compare unit ..................................................................................... 148 17.6 Compare Match Output unit .......................................................................... 150 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 5 ATmega164A/PA/324A/PA/644A/PA/1284/P 17.7 Modes of operation........................................................................................ 151 17.8 Timer/Counter Timing diagrams .................................................................... 155 17.9 Asynchronous Operation of Timer/Counter2 ................................................. 156 17.10 Timer/Counter Prescaler ............................................................................... 158 17.11 Register description ....................................................................................... 159 18 SPI - Serial Peripheral Interface ............................................................................... 166 18.1 Features ........................................................................................................ 166 18.2 Overview........................................................................................................ 166 18.3 SS pin functionality ........................................................................................ 170 18.4 Data modes ................................................................................................... 170 18.5 Register description ....................................................................................... 172 19 USART ...................................................................................................................................... 175 19.1 Features ........................................................................................................ 175 19.2 USART1 and USART0 .................................................................................. 175 19.3 Overview........................................................................................................ 175 19.4 Clock Generation ........................................................................................... 176 19.5 Frame formats ............................................................................................... 179 19.6 USART Initialization....................................................................................... 180 19.7 Data Transmission - The USART Transmitter .............................................. 181 19.8 Data Reception - The USART Receiver ....................................................... 184 19.9 Asynchronous Data Reception ...................................................................... 188 19.10 Multi-processor Communication mode .......................................................... 191 19.11 Register description ....................................................................................... 193 19.12 Examples of Baud Rate Setting..................................................................... 198 20 USART in SPI mode .......................................................................................................... 202 20.1 Features ........................................................................................................ 202 20.2 Overview........................................................................................................ 202 20.3 Clock Generation ........................................................................................... 202 20.4 SPI Data Modes and Timing.......................................................................... 203 20.5 Frame Formats .............................................................................................. 203 20.6 Data Transfer................................................................................................. 205 20.7 AVR USART MSPIM vs. AVR SPI ................................................................ 207 20.8 Register description ....................................................................................... 208 21 Two-wire Serial Interface 21.1 .............................................................................................. 211 Features ........................................................................................................ 211 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 6 ATmega164A/PA/324A/PA/644A/PA/1284/P 21.2 Two-wire Serial Interface bus definition......................................................... 211 21.3 Data Transfer and Frame Format .................................................................. 212 21.4 Multi-master Bus Systems, Arbitration and Synchronization ......................... 214 21.5 Overview of the TWI Module ......................................................................... 217 21.6 Using the TWI................................................................................................ 219 21.7 Transmission modes ..................................................................................... 222 21.8 Multi-master Systems and Arbitration............................................................ 234 21.9 Register description ....................................................................................... 236 22 AC - Analog Comparator ............................................................................................... 240 22.1 Overview........................................................................................................ 240 22.2 Analog Comparator Multiplexed Input ........................................................... 240 22.3 Register description ....................................................................................... 241 23 ADC - Analog-to-digital converter ........................................................................... 243 23.1 Features ........................................................................................................ 243 23.2 Overview........................................................................................................ 243 23.3 Operation....................................................................................................... 244 23.4 Starting a conversion..................................................................................... 245 23.5 Prescaling and Conversion Timing ................................................................ 246 23.6 Changing Channel or Reference Selection ................................................... 249 23.7 ADC Noise Canceler ..................................................................................... 250 23.8 ADC Conversion Result................................................................................. 255 23.9 Register description ....................................................................................... 257 24 JTAG interface and on-chip debug system ....................................................... 262 24.1 Features ........................................................................................................ 262 24.2 Overview........................................................................................................ 262 24.3 TAP - Test Access Port ................................................................................ 262 24.4 TAP controller................................................................................................ 264 24.5 Using the Boundary-scan Chain .................................................................... 265 24.6 Using the On-chip Debug System ................................................................. 265 24.7 On-chip Debug Specific JTAG Instructions ................................................... 266 24.8 Using the JTAG Programming Capabilities ................................................... 266 24.9 Bibliography................................................................................................... 267 24.10 Register description ....................................................................................... 267 25 IEEE 1149.1 (JTAG) Boundary-scan 25.1 ...................................................................... 268 Features ........................................................................................................ 268 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 7 ATmega164A/PA/324A/PA/644A/PA/1284/P 25.2 Overview........................................................................................................ 268 25.3 Data Registers............................................................................................... 269 25.4 Boundary-scan Specific JTAG Instructions ................................................... 270 25.5 Boundary-scan Chain .................................................................................... 271 25.6 ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P Boundary-scan order 274 25.7 Boundary-scan Description Language Files .................................................. 275 25.8 Register description ....................................................................................... 276 26 Boot loader support - read-while-write self-programming ..................... 277 26.1 Features ........................................................................................................ 277 26.2 Overview........................................................................................................ 277 26.3 Application and Boot Loader Flash Sections ................................................. 277 26.4 Read-While-Write and No Read-While-Write Flash Sections........................ 278 26.5 Boot Loader Lock Bits ................................................................................... 280 26.6 Entering the Boot Loader Program ................................................................ 281 26.7 Addressing the Flash During Self-Programming ........................................... 282 26.8 Self-Programming the Flash .......................................................................... 283 26.9 Register description ....................................................................................... 293 27 Memory programming .................................................................................................... 295 27.1 Program And Data Memory Lock Bits ........................................................... 295 27.2 Fuse bits ........................................................................................................ 296 27.3 Signature Bytes ............................................................................................. 298 27.4 Calibration byte.............................................................................................. 298 27.5 Page Size ...................................................................................................... 298 27.6 Parallel Programming Parameters, Pin Mapping, and Commands ............... 299 27.7 Parallel programming .................................................................................... 301 27.8 Serial downloading ........................................................................................ 309 27.9 Serial Programming Instruction set ............................................................... 312 27.10 Programming via the JTAG Interface ............................................................ 314 28 Electrical characteristics (TA = -40C to 85C) ................................................ 326 28.1 DC Characteristics......................................................................................... 326 28.2 Speed grades ................................................................................................ 332 28.3 Clock characteristics...................................................................................... 333 28.4 System and reset characteristics................................................................... 334 28.5 External interrupts characteristics ................................................................. 334 28.6 SPI timing characteristics .............................................................................. 335 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 8 ATmega164A/PA/324A/PA/644A/PA/1284/P 28.7 Two-wire Serial Interface Characteristics ...................................................... 336 28.8 ADC characteristics ....................................................................................... 338 29 Electrical Characteristics - TA = -40C to 105C ............................................. 341 29.1 DC Characteristics......................................................................................... 341 30 Typical characteristics -TA = -40C to 85C ...................................................... 344 30.1 ATmega164A typical characteristics - TA = -40C to 85C ........................... 344 30.2 ATmega164PA typical characteristics - TA = -40C to 85C ......................... 371 30.3 ATmega324A typical characteristics - TA = -40C to 85C ........................... 397 30.4 ATmega324PA typical characteristics - TA = -40C to 85C ......................... 423 30.5 ATmega644A typical characteristics - TA = -40C to 85C ........................... 449 30.6 ATmega644PA typical characteristics - TA = -40C to 85C ......................... 475 30.7 ATmega1284 typical characteristics - TA = -40C to 85C............................ 501 30.8 ATmega1284P typical characteristics - TA = -40C to 85C ......................... 527 31 Typical Characteristics - TA = -40C to 105C ................................................. 553 31.1 ATmega164PA Typical Characteristics - TA = -40C to 105C ..................... 554 31.2 ATmega324PA Typical Characteristics - TA = -40C to 105C ..................... 574 31.3 ATmega644PA Typical Characteristics - TA = -40C to 105C ..................... 594 31.4 ATmega1284P typical characteristics - TA = -40C to 105C ....................... 613 32 Register summary ............................................................................................................. 636 33 Instruction set summary 34 Ordering information ............................................................................................... 640 ....................................................................................................... 643 34.1 ATmega164A................................................................................................. 643 34.2 ATmega164PA .............................................................................................. 644 34.3 ATmega324A................................................................................................. 645 34.4 ATmega324PA .............................................................................................. 646 34.5 ATmega644A................................................................................................. 647 34.6 ATmega644PA .............................................................................................. 648 34.7 ATmega1284 ................................................................................................. 649 34.8 ATmega1284P............................................................................................... 650 35 Packaging information ................................................................................................... 651 35.1 44A ................................................................................................................ 651 35.2 40P6 .............................................................................................................. 652 35.3 44M1.............................................................................................................. 653 35.4 44MC ............................................................................................................. 654 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 9 ATmega164A/PA/324A/PA/644A/PA/1284/P 35.5 36 Errata 49C2 ............................................................................................................. 655 ......................................................................................................................................... 656 36.1 Errata for ATmega164A................................................................................. 656 36.2 Errata for ATmega164PA .............................................................................. 656 36.3 Errata for ATmega324A................................................................................. 656 36.4 Errata for ATmega324PA .............................................................................. 656 36.5 Errata for ATmega644A................................................................................. 656 36.6 Errata for ATmega644PA .............................................................................. 656 36.7 Errata for ATmega1284 ................................................................................. 656 36.8 Errata for ATmega1284P............................................................................... 656 37 Data sheet revision history .......................................................................................... 657 37.1 Rev. A - 10/2018............................................................................................ 657 37.2 Rev. 8272G - 01/2015 ................................................................................... 657 37.3 Rev. 8272F - 08/2014 .................................................................................... 657 37.4 Rev. 8272E - 04/2013.................................................................................... 658 37.5 Rev. 8272D - 05/12 ....................................................................................... 658 37.6 Rev. 8272C - 06/11 ....................................................................................... 658 37.7 Rev. 8272B - 05/11........................................................................................ 658 37.8 Rev. 8272A - 01/10........................................................................................ 659 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 10 ATmega164A/PA/324A/PA/644A/PA/1284/P 1. Pin configurations 1.1 Pinout - PDIP/TQFP/VQFN/QFN/MLF for ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 1-1. Pinout (PCINT8/XCK0/T0) PB0 (PCINT9/CLKO/T1) PB1 (PCINT10/INT2/AIN0) PB2 (PCINT11/OC0A/AIN1) PB3 (PCINT12/OC0B/SS) PB4 (PCINT13/ICP3/MOSI) PB5 (PCINT14/OC3A/MISO) PB6 (PCINT15/OC3B/SCK) PB7 RESET VCC GND XTAL2 XTAL1 (PCINT24/RXD0/T3*) PD0 (PCINT25/TXD0) PD1 (PCINT26/RXD1/INT0) PD2 (PCINT27/TXD1/INT1) PD3 (PCINT28/XCK1/OC1B) PD4 (PCINT29/OC1A) PD5 (PCINT30/OC2B/ICP) PD6 PA0 (ADC0/PCINT0) PA1 (ADC1/PCINT1) PA2 (ADC2/PCINT2) PA3 (ADC3/PCINT3) PA4 (ADC4/PCINT4) PA5 (ADC5/PCINT5) PA6 (ADC6/PCINT6) PA7 (ADC7/PCINT7) AREF GND AVCC PC7 (TOSC2/PCINT23) PC6 (TOSC1/PCINT22) PC5 (TDI/PCINT21) PC4 (TDO/PCINT20) PC3 (TMS/PCINT19) PC2 (TCK/PCINT18) PC1 (SDA/PCINT17) PC0 (SCL/PCINT16) PD7 (OC2A/PCINT31) PB4 (SS/OC0B/PCINT12) PB3 (AIN1/OC0A/PCINT11) PB2 (AIN0/INT2/PCINT10) PB1 (T1/CLKO/PCINT9) PB0 (XCK0/T0/PCINT8) GND VCC PA0 (ADC0/PCINT0) PA1 (ADC1/PCINT1) PA2 (ADC2/PCINT2) PA3 (ADC3/PCINT3) TQFP/QFN/MLF (PCINT13/ICP3/MOSI) PB5 (PCINT14/OC3A/MISO) PB6 (PCINT15/OC3B/SCK) PB7 RESET VCC GND XTAL2 XTAL1 (PCINT24/RXD0/T3*) PD0 (PCINT25/TXD0) PD1 (PCINT26/RXD1/INT0) PD2 PD3 PD4 PD5 PD6 PD7 VCC GND (PCINT16/SCL) PC0 (PCINT17/SDA) PC1 (PCINT18/TCK) PC2 (PCINT19/TMS) PC3 (PCINT27/TXD1/INT1) (PCINT28/XCK1/OC1B) (PCINT29/OC1A) (PCINT30/OC2B/ICP) (PCINT31/OC2A) *T3 is only available for ATmega1284/1284P PA4 (ADC4/PCINT4) PA5 (ADC5/PCINT5) PA6 (ADC6/PCINT6) PA7 (ADC7/PCINT7) AREF GND AVCC PC7 (TOSC2/PCINT23) PC6 (TOSC1/PCINT22) PC5 (TDI/PCINT21) PC4 (TDO/PCINT20) Note: The large center pad underneath the VQFN/QFN/MLF package should be soldered to ground on the board to ensure good mechanical stability. 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 11 ATmega164A/PA/324A/PA/644A/PA/1284/P Pinout - DRQFN for ATmega164A/164PA/324A/324PA Figure 1-2. DRQFN - pinout Top view Bottom view A18 B1 B15 A17 B2 B14 B3 B4 A2 A3 A4 A5 B5 A18 A1 B15 A17 B1 B14 B2 A16 B13 A16 B13 B3 A15 B12 A15 A2 A3 A4 B4 A14 B12 A14 B11 A13 B11 A13 B5 A5 A6 A12 B10 A11 B9 A10 B8 A9 B7 A8 B6 A7 B8 A10 B9 A11 B10 A12 B7 A9 A8 B6 A6 Table 1-1. A24 B20 A23 B19 A22 B18 A21 B17 A20 B16 A19 A19 B16 A20 B17 A21 B18 A22 B19 A23 B20 A24 A1 A7 1.2 DRQFN - pinout. A1 PB5 A7 PD3 A13 PC4 A19 PA3 B1 PB6 B6 PD4 B11 PC5 B16 PA2 A2 PB7 A8 PD5 A14 PC6 A20 PA1 B2 RESET B7 PD6 B12 PC7 B17 PA0 A3 VCC A9 PD7 A15 AVCC A21 VCC B3 GND B8 VCC B13 GND B18 GND A4 XTAL2 A10 GND A16 AREF A22 PB0 B4 XTAL1 B9 PC0 B14 PA7 B19 PB1 A5 PD0 A11 PC1 A17 PA6 A23 PB2 B5 PD1 B10 PC2 B15 PA5 B20 PB3 A6 PD2 A12 PC3 A18 PA4 A24 PB4 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 12 ATmega164A/PA/324A/PA/644A/PA/1284/P 1.3 Pinout - VFBGA for ATmega164A/164PA/324A/324PA Figure 1-3. VFBGA - pinout Top view 1 3 4 5 6 7 7 6 5 4 3 2 1 A A B B C C D D E E F F G G Table 1-2. 2. 2 Bottom view BGA - pinout 1 2 3 4 5 6 7 A GND PB4 PB2 GND VCC PA2 GND B PB6 PB5 PB3 PB0 PA0 PA3 PA5 C VCC RESET PB7 PB1 PA1 PA6 AREF D GND XTAL2 PD0 GND PA4 PA7 GND E XTAL1 PD1 PD5 PD7 PC5 PC7 AVCC F PD2 PD3 PD6 PC0 PC2 PC4 PC6 G GND PD4 VCC GND PC1 PC3 GND Overview The ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 13 ATmega164A/PA/324A/PA/644A/PA/1284/P 2.1 Block diagram Figure 2-1. Block diagram PA7..0 PB7..0 VCC RESET GND Power Supervision POR / BOD & RESET PORT A (8) PORT B (8) Watchdog Timer Analog Comparator A/D Converter Watchdog Oscillator USART 0 XTAL1 Oscillator Circuits / Clock Generation EEPROM Internal Bandgap reference XTAL2 SPI 8bit T/C 0 CPU 16bit T/C 1 16bit T/C 1 JTAG/OCD 8bit T/C 2 TWI FLASH SRAM PORT C (8) TOSC2/PC7 TOSC1/PC6 USART 1 16bit T/C 3* PORT D (8) PD7..0 PC5..0 * Only available in ATmega1284/1284P The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P provide the following features: 16/32/64/128Kbytes of In-System Programmable Flash with Read-While-Write capabilities, 512/1K/2K/4Kbytes EEPROM, 1/2/4/16Kbytes SRAM, 32 general purpose I/O lines, 32 general purpose working registers, Real Time Counter (RTC), three (four for ATmega1284/1284P) flexible Timer/Counters with compare modes and PWM, 2 USARTs, a byte oriented two-wire Serial Interface, a 8-channel, 10-bit ADC with optional differential input stage with programmable gain, programmable Watchdog Timer with Internal Oscillator, an SPI serial port, IEEE std. 1149.1 compliant JTAG test interface, also used for accessing the On-chip Debug system and programming and six software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 14 ATmega164A/PA/324A/PA/644A/PA/1284/P timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except Asynchronous Timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the Crystal/Resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low power consumption. In Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue to run. Microchip offers the QTouch library for embedding capacitive touch buttons, sliders and wheels functionality into AVR microcontrollers. The patented charge-transfer signal acquisition offers robust sensing and includes fully debounced reporting of touch keys and includes Adjacent Key SuppressionTM (AKSTM) technology for unambiguous detection of key events. The easy-to-use QTouch Suite toolchain allows you to explore, develop and debug your own touch applications. The device is manufactured using the high-density nonvolatile memory technology. The On-chip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core. The boot program can use any interface to download the application program in the application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true ReadWhile-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits. 2.2 Comparison between ATmega164A, ATmega164PA, ATmega324A, ATmega324PA, ATmega644A, ATmega644PA, ATmega1284 and ATmega1284P Table 2-1. Differences between ATmega164A, ATmega164PA, ATmega324A, ATmega324PA, ATmega644A, ATmega644PA, ATmega1284 and ATmega1284P Device Flash EEPROM RAM ATmega164A 16K 512 1K ATmega164PA 16K 512 1K ATmega324A 32K 1K 2K ATmega324PA 32K 1K 2K ATmega644A 64K 2K 4K ATmega644PA 64K 2K 4K ATmega1284 128K 4K 16K ATmega1284P 128K 4K 16K 2.3 Pin Descriptions 2.3.1 VC Units bytes Digital supply voltage. 2.3.2 GND Ground. 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 15 ATmega164A/PA/324A/PA/644A/PA/1284/P 2.3.3 Port A (PA7:PA0) Port A serves as analog inputs to the Analog-to-digital Converter. Port A also serves as an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port A also serves the functions of various special features of the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P as listed on page 87. 2.3.4 Port B (PB7:PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tristated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P as listed on page 88. 2.3.5 Port C (PC7:PC0) Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tristated when a reset condition becomes active, even if the clock is not running. Port C also serves the functions of the JTAG interface, along with special features of the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P as listed on page 91. 2.3.6 Port D (PD7:PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tristated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P as listed on page 94. 2.3.7 RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in "System and reset characteristics" on page 334. Shorter pulses are not guaranteed to generate a reset. 2.3.8 XTAL1 Input to the inverting Oscillator amplifier and input to the internal clock operating circuit. 2.3.9 XTAL2 Output from the inverting Oscillator amplifier. 2.3.10 AVCC AVCC is the supply voltage pin for Port A and the Analog-to-digital Converter. It should be externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter. 2.3.11 AREF This is the analog reference pin for the Analog-to-digital Converter. 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 16 ATmega164A/PA/324A/PA/644A/PA/1284/P 3. Resources A comprehensive set of development tools, application notes and datasheets are available for download on www.microchip.com 4. About code examples This documentation contains simple code examples that briefly show how to use various parts of the device. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Confirm with the C compiler documentation for more details. The code examples assume that the part specific header file is included before compilation. For I/O registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI" instructions must be replaced with instructions that allow access to extended I/O. Typically "LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR". Note: 5. 1. Data retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85C or 100 years at 25C. 6. Capacitive touch sensing The QTouch Library provides a simple to use solution to realize touch sensitive interfaces on most AVR microcontrollers. The QTouch Library includes support for the QTouch and QMatrix acquisition methods. Touch sensing can be added to any application by linking the appropriate QTouch Library for the AVR Microcontroller. This is done by using a simple set of APIs to define the touch channels and sensors, and then calling the touch sensing API's to retrieve the channel information and determine the touch sensor states. The QTouch Library is FREE and downloadable from www.microchip.com. For implementation details and other information, refer to the QTouch Library User Guide - also available for download from the microchip website. 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 17 ATmega164A/PA/324A/PA/644A/PA/1284/P 7. AVR CPU Core 7.1 Overview This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. Figure 7-1. Block diagram of the AVR architecture Data Bus 8-bit Flash Program Memory Program Counter Status and Control 32 x 8 General Purpose Registrers Control Lines Direct Addressing Instruction Decoder Indirect Addressing Instruction Register Interrupt Unit SPI Unit Watchdog Timer ALU Analog Comparator I/O Module1 Data SRAM I/O Module 2 I/O Module n EEPROM I/O Lines In order to maximize performance and parallelism, the AVR uses a Harvard architecture - with separate memories and buses for program and data. Instructions in the program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is In-System Reprogrammable Flash memory. The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 18 ATmega164A/PA/324A/PA/644A/PA/1284/P operands are output from the Register File, the operation is executed, and the result is stored back in the Register File - in one clock cycle. Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing - enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash program memory. These added function registers are the 16-bit X-, Y-, and Zregister, described later in this section. The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation. Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word format. Every program memory address contains a 16- or 32-bit instruction. Program Flash memory space is divided in two sections, the Boot Program section and the Application Program section. Both sections have dedicated Lock bits for write and read/write protection. The SPM instruction that writes into the Application Flash memory section must reside in the Boot Program section. During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority. The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P has Extended I/O space from 0x60 - 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used. 7.2 ALU - Arithmetic Logic Unit The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU operations are divided into three main categories - arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See the "Instruction Set" section for a detailed description. 7.3 Status Register The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the AVR Instruction Set Manual. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software. 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 19 ATmega164A/PA/324A/PA/644A/PA/1284/P 7.3.1 SREG - Status Register(1) The AVR Status Register - SREG - is defined as: Bit 7 6 5 4 3 2 1 0 0x3F (0x5F) I T H S V N Z C Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SREG * Bit 7 - I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI instructions, as described in the AVR Instruction Set Manual on www.microchip.com. * Bit 6 - T: Bit Copy Storage The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction. * Bit 5 - H: Half Carry Flag The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Is useful in BCD arithmetic. * Bit 4 - S: Sign Bit, S = N V The S-bit is always an exclusive or between the Negative Flag N and the Two's Complement Overflow Flag V. * Bit 3 - V: Two's Complement Overflow Flag The Two's Complement Overflow Flag V supports two's complement arithmetic. * Bit 2 - N: Negative Flag The Negative Flag N indicates a negative result in an arithmetic or logic operation. * Bit 1 - Z: Zero Flag The Zero Flag Z indicates a zero result in an arithmetic or logic operation. * Bit 0 - C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. Note: 1. Refer to the Instruction Set Manual on www.microchip.com for more details 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 20 ATmega164A/PA/324A/PA/644A/PA/1284/P 7.4 General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: One 8-bit output operand and one 8-bit result input Two 8-bit output operands and one 8-bit result input Two 8-bit output operands and one 16-bit result input One 16-bit output operand and one 16-bit result input Figure 7-2 shows the structure of the 32 general purpose working registers in the CPU. Figure 7-2. AVR CPU General Purpose Working Registers 7 0 Addr. R0 0x00 R1 0x01 R2 0x02 ... R13 0x0D General R14 0x0E Purpose R15 0x0F Working R16 0x10 Registers R17 0x11 ... R26 0x1A X-register Low Byte R27 0x1B X-register High Byte R28 0x1C Y-register Low Byte R29 0x1D Y-register High Byte R30 0x1E Z-register Low Byte R31 0x1F Z-register High Byte Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions. As shown in Figure 7-2, each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file. 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 21 ATmega164A/PA/324A/PA/644A/PA/1284/P 7.4.1 The X-register, Y-register, and Z-register The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 7-3. Figure 7-3. The X-, Y-, and Z-registers 15 X-register XH 7 XL 0 R27 (0x1B) 15 Y-register 0 R26 (0x1A) YH 7 YL 0 R29 (0x1D) Z-register 0 7 0 7 0 R28 (0x1C) 15 ZH 7 0 R31 (0x1F) ZL 7 0 0 R30 (0x1E) In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the AVR Instruction Set Manual for details). 7.5 Stack Pointer The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. Note that the Stack is implemented as growing from higher to lower memory locations. The Stack Pointer Register always points to the top of the Stack. The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. A Stack PUSH command will decrease the Stack Pointer. The Stack in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. Initial Stack Pointer value equals the last address of the internal SRAM and the Stack Pointer must be set to point above start of the SRAM, see Figure 8-2 on page 29. See Table 7-1 for Stack Pointer details. Table 7-1. Stack Pointer instructions Instruction Stack pointer Description PUSH Decremented by 1 Data is pushed onto the stack CALL ICALL RCALL Decremented by 2 Return address is pushed onto the stack with a subroutine call or interrupt POP Incremented by 1 Data is popped from the stack RET RETI Incremented by 2 Return address is popped from the stack with return from subroutine or return from interrupt The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent, see Table 7-2 on page 23. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present. 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 22 ATmega164A/PA/324A/PA/644A/PA/1284/P 7.5.1 SPH and SPL - Stack Pointer High and Stack pointer Low Bit 15 14 13 12 11 10 9 8 0x3E (0x5E) - - - SP12 SP11 SP10 SP9 SP8 SPH 0x3D (0x5D) SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL 7 6 5 4 3 2 1 0 Read/Write Initial Value Note: 1. R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0/0(1) 0/1(1) 1/0(1) 0 0 1 1 1 1 1 1 1 1 Initial values respectively for the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P. Table 7-2. 7.5.2 R R/W Stack Pointer size Device Stack Pointer size ATmega164A/ATmega164PA SP[10:0] ATmega324A/ATmega324PA SP[11:0] ATmega644A/ATmega644PA SP[12:0] ATmega1284/ATmega1284P SP[13:0] RAMPZ - Extended Z-pointer Register for ELPM/SPM(1) Bit 7 6 5 4 3 2 1 0 RAMPZ7 RAMPZ6 RAMPZ5 RAMPZ4 RAMPZ3 RAMPZ2 RAMPZ1 RAMPZ0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 0x3B (0x5B) RAMPZ For ELPM/SPM instructions, the Z-pointer is a concatenation of RAMPZ, ZH, and ZL, as shown in Figure 7-4 on page 23. Note that LPM is not affected by the RAMPZ setting. Figure 7-4. The Z-pointer used by ELPM and SPM. Bit (Individually) 7 0 7 0 RAMPZ Bit (Z-pointer) 23 7 ZH 16 15 0 ZL 8 7 0 The actual number of bits is implementation dependent. Unused bits in an implementation will always read as zero. For compatibility with future devices, be sure to write these bits to zero. Note: 7.6 1. RAMPZ is only valid for ATmega1284/ATmega1284P. Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used. Figure 7-5 on page 24 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit. 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 23 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 7-5. The Parallel Instruction Fetches and Instruction Executions T1 T2 T3 T4 clkCPU 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch Figure 7-6 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register. Figure 7-6. Single Cycle ALU operation T1 T2 T3 T4 clkCPU Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back 7.7 Reset and interrupt handling The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt. Depending on the Program Counter value, interrupts may be automatically disabled when Boot Lock bits BLB02 or BLB12 are programmed. This feature improves software security. See the section "Memory programming" on page 295 for details. The lowest addresses in the program memory space are by default defined as the Reset and Interrupt Vectors. The complete list of vectors is shown in "Interrupts" on page 69. The list also determines the priority levels of the different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 - the External Interrupt Request 0. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL bit in the MCU Control Register (MCUCR). Refer to "Interrupts" on page 69 for more information. The Reset Vector can also be moved to the start of the Boot Flash section by programming the BOOTRST Fuse, see "Memory programming" on page 295. When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction - RETI - is executed. There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 24 ATmega164A/PA/324A/PA/644A/PA/1284/P writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the Global Interrupt Enable bit is set, and will then be executed by order of priority. The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered. When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served. Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by software. When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence. Assembly Code Example in r16, SREG ; store SREG value cli ; disable interrupts during timed sequence sbi EECR, EEMPE ; start EEPROM write sbi EECR, EEPE out SREG, r16 ; restore SREG value (I-bit) C Code Example char cSREG; cSREG = SREG; SREG value */ /* disable interrupts during timed sequence */ __disable_interrupt(); EECR |= (1< xxx ... ... ... Notes: RESET: ... ; Enable interrupts 1. Applies only to ATmega1284P. When the BOOTRST Fuse is unprogrammed, the Boot section size set to 8K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: Address 0x00000 program start 0x00001 Pointer to top of RAM 0x00002 0x00003 0x00004 0x00005 ; .org 0x1F002 0x1F002 0x1F004 ... 0x1FO36 Handler Labels RESET: CodeComments ldir16,high(RAMEND); Main outSPH,r16; Set Stack ldir16,low(RAMEND) outSPL,r16 sei; Enable interrupts xxx jmpEXT_INT0; IRQ0 Handler jmpEXT_INT1; IRQ1 Handler ......; jmpSPM_RDY; SPM Ready When the BOOTRST Fuse is programmed and the Boot section size set to 8K bytes, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: Address .org 0x0002 0x00002 0x00004 ... 0x00036 Handler ; .org 0x1F000 0x1F000 program start 0x1F001 Pointer to top of RAM 0x1F002 2018 Microchip Technology Inc. Labels CodeComments jmpEXT_INT0; IRQ0 Handler jmpEXT_INT1; IRQ1 Handler ......; jmpSPM_RDY; SPM Ready RESET: ldir16,high(RAMEND); Main outSPH,r16; Set Stack ldir16,low(RAMEND) Data Sheet Complete DS40002070A-page 72 ATmega164A/PA/324A/PA/644A/PA/1284/P 0x1F003 0x1F004 0x1F005 outSPL,r16 sei; Enable interrupts xxx When the BOOTRST Fuse is programmed, the Boot section size set to 8K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: Address ; .org 0x1F000 0x1F000 0x1F002 0x1F004 ... 0x1F036 Handler ; 0x1F03E program start 0x1F03F Pointer to top of RAM 0x1F040 0x1F041 0x1F042 0x1FO43 Labels CodeComments jmpRESET; Reset handler jmpEXT_INT0; IRQ0 Handler jmpEXT_INT1; IRQ1 Handler ......; jmpSPM_RDY; SPM Ready RESET: ldir16,high(RAMEND); Main outSPH,r16; Set Stack ldir16,low(RAMEND) outSPL,r16 sei; Enable interrupts xxx 12.2.1 Moving Interrupts Between Application and Boot Space The General Interrupt Control Register controls the placement of the Interrupt Vector table. 12.3 Register description 12.3.1 MCUCR - MCU Control Register Bit 7 6 5 4 3 2 1 0 0x35 (0x55) JTD BODS(1) BODSE(1) PUD - - IVSEL IVCE Read/Write R/W R/W R/W R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 Note: 1. MCUCR Only available in the ATmega164PA/324PA/644PA/1284P. * Bit 1 - IVSEL: Interrupt Vector Select When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash memory. When this bit is set (one), the Interrupt Vectors are moved to the beginning of the Boot Loader section of the Flash. The actual address of the start of the Boot Flash Section is determined by the BOOTSZ Fuses. Refer to the section "Memory programming" on page 295 for details. To avoid unintentional changes of Interrupt Vector tables, a special write procedure must be followed to change the IVSEL bit: 1. Write the Interrupt Vector Change Enable (IVCE) bit to one. 2. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE. Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled in the cycle IVCE is set, and they remain disabled until after the instruction following the write to IVSEL. If IVSEL is not 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 73 ATmega164A/PA/324A/PA/644A/PA/1284/P written, interrupts remain disabled for four cycles. The I-bit in the Status Register is unaffected by the automatic disabling. Note: If Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is programmed, interrupts are disabled while executing from the Application section. If Interrupt Vectors are placed in the Application section and Boot Lock bit BLB12 is programed, interrupts are disabled while executing from the Boot Loader section. Refer to the section "Memory programming" on page 295 for details on Boot Lock bits. * Bit 0 - IVCE: Interrupt Vector Change Enable The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable interrupts, as explained in the IVSEL description above. See the following Code Example. Assembly Code Example Move_interrupts: ; Get MCUCR in r16, MCUCR mov r17, r16 ; Enable change of Interrupt Vectors ori r16, (1< CSn2:0 > 1). 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 120 ATmega164A/PA/324A/PA/644A/PA/1284/P The number of system clock cycles from when the timer is enabled to the first count occurs can be from 1 to N+1 system clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024). It is possible to use the Prescaler Reset for synchronizing the Timer/Counter to program execution. However, care must be taken if the other Timer/Counter that shares the same prescaler also uses prescaling. A prescaler reset will affect the prescaler period for all Timer/Counters it is connected to. 16.6 Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 16-2 shows a block diagram of the counter and its surroundings. Figure 16-2. Counter unit block diagram DATA BUS (8-bit) TOVn (Int.Req.) TEMP (8-bit) Clock Select Count TCNTnH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) Clear Direction Control Logic clkTn Edge Detector Tn ( From Prescaler ) TOP BOTTOM Signal description (internal signals): Count Increment or decrement TCNTn by 1. Direction Select between increment and decrement. Clear Clear TCNTn (set all bits to zero). clkTn Timer/Counter clock. TOP Signalize that TCNTn has reached maximum value. BOTTOM Signalize that TCNTn has reached minimum value (zero). The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High (TCNTnH) containing the upper eight bits of the counter, and Counter Low (TCNTnL) containing the lower eight bits. The TCNTnH Register can only be indirectly accessed by the CPU. When the CPU does an access to the TCNTnH I/O location, the CPU accesses the high byte temporary register (TEMP). The temporary register is updated with the TCNTnH value when the TCNTnL is read, and TCNTnH is updated with the temporary register value when TCNTnL is written. This allows the CPU to read or write the entire 16-bit counter value within one clock cycle via the 8-bit data bus. It is important to notice that there are special cases of writing to the TCNTn Register when the counter is counting that will give unpredictable results. The special cases are described in the sections where they are of importance. Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkTn). The clkTn can be generated from an external or internal clock source, selected by the Clock Select bits (CSn2:0). When no clock source is selected (CSn2:0 = 0) the timer is stopped. However, the TCNTn value can be accessed by the CPU, independent of whether clkTn is present or not. A CPU write overrides (has priority over) all counter clear or count operations. The counting sequence is determined by the setting of the Waveform Generation mode bits (WGMn3:0) located in the Timer/Counter Control Registers A and B (TCCRnA and TCCRnB). There are close connections between how the counter behaves (counts) and how waveforms are generated on the Output Compare outputs OCnx. For more details about advanced counting sequences and waveform generation, see "Modes of Operation" on page 127. 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 121 ATmega164A/PA/324A/PA/644A/PA/1284/P The Timer/Counter Overflow Flag (TOVn) is set according to the mode of operation selected by the WGMn3:0 bits. TOVn can be used for generating a CPU interrupt. 16.7 Input Capture Unit The Timer/Counter incorporates an Input Capture unit that can capture external events and give them a timestamp indicating time of occurrence. The external signal indicating an event, or multiple events, can be applied via the ICPn pin or alternatively, via the analog-comparator unit. The time-stamps can then be used to calculate frequency, duty-cycle, and other features of the signal applied. Alternatively the time-stamps can be used for creating a log of the events. The Input Capture unit is illustrated by the block diagram shown in Figure 16-3. The elements of the block diagram that are not directly a part of the Input Capture unit are gray shaded. The small "n" in register and bit names indicates the Timer/Counter number. Figure 16-3. Input Capture unit block diagram DATA BUS (8-bit) TEMP (8-bit) ICRnH (8-bit) ICRnL (8-bit) TCNTnH (8-bit) ICRn (16-bit Register) WRITE ACO* Analog Comparator ACIC* TCNTnL (8-bit) TCNTn (16-bit Counter) ICNC ICES Noise Canceler Edge Detector ICFn (Int.Req.) ICPn When a change of the logic level (an event) occurs on the Input Capture pin (ICPn), alternatively on the Analog Comparator output (ACO), and this change confirms to the setting of the edge detector, a capture will be triggered. When a capture is triggered, the 16-bit value of the counter (TCNTn) is written to the Input Capture Register (ICRn). The Input Capture Flag (ICFn) is set at the same system clock as the TCNTn value is copied into ICRn Register. If enabled (ICIEn = 1), the Input Capture Flag generates an Input Capture interrupt. The ICFn Flag is automatically cleared when the interrupt is executed. Alternatively the ICFn Flag can be cleared by software by writing a logical one to its I/O bit location. Reading the 16-bit value in the Input Capture Register (ICRn) is done by first reading the low byte (ICRnL) and then the high byte (ICRnH). When the low byte is read the high byte is copied into the high byte temporary register (TEMP). When the CPU reads the ICRnH I/O location it will access the TEMP Register. The ICRn Register can only be written when using a Waveform Generation mode that utilizes the ICRn Register for defining the counter's TOP value. In these cases the Waveform Generation mode (WGMn3:0) bits must be set before the TOP value can be written to the ICRn Register. When writing the ICRn Register the high byte must be written to the ICRnH I/O location before the low byte is written to ICRnL. For more information on how to access the 16-bit registers refer to "Accessing 16-bit Registers" on page 117. 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 122 ATmega164A/PA/324A/PA/644A/PA/1284/P 16.7.1 Input Capture Trigger Source The main trigger source for the Input Capture unit is the Input Capture pin (ICPn). Timer/Counter1 can alternatively use the Analog Comparator output as trigger source for the Input Capture unit. The Analog Comparator is selected as trigger source by setting the Analog Comparator Input Capture (ACIC) bit in the Analog Comparator Control and Status Register (ACSR). Be aware that changing trigger source can trigger a capture. The Input Capture Flag must therefore be cleared after the change. Both the Input Capture pin (ICPn) and the Analog Comparator output (ACO) inputs are sampled using the same technique as for the Tn pin (Figure 16-1 on page 116). The edge detector is also identical. However, when the noise canceler is enabled, additional logic is inserted before the edge detector, which increases the delay by four system clock cycles. Note that the input of the noise canceler and edge detector is always enabled unless the Timer/Counter is set in a Waveform Generation mode that uses ICRn to define TOP. An Input Capture can be triggered by software by controlling the port of the ICPn pin. 16.7.2 Noise Canceler The noise canceler improves noise immunity by using a simple digital filtering scheme. The noise canceler input is monitored over four samples, and all four must be equal for changing the output that in turn is used by the edge detector. The noise canceler is enabled by setting the Input Capture Noise Canceler (ICNCn) bit in Timer/Counter Control Register B (TCCRnB). When enabled the noise canceler introduces additional four system clock cycles of delay from a change applied to the input, to the update of the ICRn Register. The noise canceler uses the system clock and is therefore not affected by the prescaler. 16.7.3 Using the Input Capture unit The main challenge when using the Input Capture unit is to assign enough processor capacity for handling the incoming events. The time between two events is critical. If the processor has not read the captured value in the ICRn Register before the next event occurs, the ICRn will be overwritten with a new value. In this case the result of the capture will be incorrect. When using the Input Capture interrupt, the ICRn Register should be read as early in the interrupt handler routine as possible. Even though the Input Capture interrupt has relatively high priority, the maximum interrupt response time is dependent on the maximum number of clock cycles it takes to handle any of the other interrupt requests. Using the Input Capture unit in any mode of operation when the TOP value (resolution) is actively changed during operation, is not recommended. Measurement of an external signal's duty cycle requires that the trigger edge is changed after each capture. Changing the edge sensing must be done as early as possible after the ICRn Register has been read. After a change of the edge, the Input Capture Flag (ICFn) must be cleared by software (writing a logical one to the I/O bit location). For measuring frequency only, the clearing of the ICFn Flag is not required (if an interrupt handler is used). 16.8 Output Compare units The 16-bit comparator continuously compares TCNTn with the Output Compare Register (OCRnx). If TCNT equals OCRnx the comparator signals a match. A match will set the Output Compare Flag (OCFnx) at the next timer clock cycle. If enabled (OCIEnx = 1), the Output Compare Flag generates an Output Compare interrupt. The OCFnx Flag is automatically cleared when the interrupt is executed. Alternatively the OCFnx Flag can be cleared by software by writing a logical one to its I/O bit location. The Waveform Generator uses the match signal to generate an output according to operating mode set by the Waveform Generation mode (WGMn3:0) bits and Compare Output mode (COMnx1:0) bits. The TOP and BOTTOM signals are used by the Waveform 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 123 ATmega164A/PA/324A/PA/644A/PA/1284/P Generator for handling the special cases of the extreme values in some modes of operation (See "Modes of Operation" on page 127). A special feature of Output Compare unit A allows it to define the Timer/Counter TOP value (i.e., counter resolution). In addition to the counter resolution, the TOP value defines the period time for waveforms generated by the Waveform Generator. Figure 16-4 shows a block diagram of the Output Compare unit. The small "n" in the register and bit names indicates the device number (n = n for Timer/Counter n), and the "x" indicates Output Compare unit (A/B/C). The elements of the block diagram that are not directly a part of the Output Compare unit are gray shaded. Figure 16-4. Output Compare unit, block diagram DATA BUS (8-bit) TEMP (8-bit) OCRnxH Buf. (8-bit) OCRnxL Buf. (8-bit) TCNTnH (8-bit) OCRnx Buffer (16-bit Register) OCRnxH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) OCRnxL (8-bit) OCRnx (16-bit Register) = (16-bit Comparator ) OCFnx (Int.Req.) TOP BOTTOM Waveform Generator WGMn3:0 OCnx COMnx1:0 The OCRnx Register is double buffered when using any of the twelve Pulse Width Modulation (PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCRnx Compare Register to either TOP or BOTTOM of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free. The OCRnx Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCRnx Buffer Register, and if double buffering is disabled the CPU will access the OCRnx directly. The content of the OCR1x (Buffer or Compare) Register is only changed by a write operation (the Timer/Counter does not update this register automatically as the TCNT1 and ICR1 Register). Therefore OCR1x is not read via the high byte temporary register (TEMP). However, it is a good practice to read the low byte first as when accessing other 16-bit registers. Writing the OCRnx Registers must be done via the TEMP Register since the compare of all 16 bits is done continuously. The high byte (OCRnxH) has to be written first. When the high byte I/O location is written by the CPU, the TEMP Register will be updated by the value written. Then when the low byte (OCRnxL) is written to the lower eight bits, the high byte will be copied into the upper 8bits of either the OCRnx buffer or OCRnx Compare Register in the same system clock cycle. For more information of how to access the 16-bit registers refer to "Accessing 16-bit Registers" on page 117. 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 124 ATmega164A/PA/324A/PA/644A/PA/1284/P 16.8.1 Force Output Compare In non-PWM Waveform Generation modes, the match output of the comparator can be forced by writing a one to the Force Output Compare (FOCnx) bit. Forcing compare match will not set the OCFnx Flag or reload/clear the timer, but the OCnx pin will be updated as if a real compare match had occurred (the COMn1:0 bits settings define whether the OCnx pin is set, cleared or toggled). 16.8.2 Compare Match Blocking by TCNTn Write All CPU writes to the TCNTn Register will block any compare match that occurs in the next timer clock cycle, even when the timer is stopped. This feature allows OCRnx to be initialized to the same value as TCNTn without triggering an interrupt when the Timer/Counter clock is enabled. 16.8.3 Using the Output Compare Unit Since writing TCNTn in any mode of operation will block all compare matches for one timer clock cycle, there are risks involved when changing TCNTn when using any of the Output Compare channels, independent of whether the Timer/Counter is running or not. If the value written to TCNTn equals the OCRnx value, the compare match will be missed, resulting in incorrect waveform generation. Do not write the TCNTn equal to TOP in PWM modes with variable TOP values. The compare match for the TOP will be ignored and the counter will continue to 0xFFFF. Similarly, do not write the TCNTn value equal to BOTTOM when the counter is downcounting. The setup of the OCnx should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OCnx value is to use the Force Output Compare (FOCnx) strobe bits in Normal mode. The OCnx Register keeps its value even when changing between Waveform Generation modes. Be aware that the COMnx1:0 bits are not double buffered together with the compare value. Changing the COMnx1:0 bits will take effect immediately. 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 125 ATmega164A/PA/324A/PA/644A/PA/1284/P Compare Match Output unit The Compare Output mode (COMnx1:0) bits have two functions. The Waveform Generator uses the COMnx1:0 bits for defining the Output Compare (OCnx) state at the next compare match. Secondly the COMnx1:0 bits control the OCnx pin output source. Figure 16-5 shows a simplified schematic of the logic affected by the COMnx1:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O Port Control Registers (DDR and PORT) that are affected by the COMnx1:0 bits are shown. When referring to the OCnx state, the reference is for the internal OCnx Register, not the OCnx pin. If a system reset occur, the OCnx Register is reset to "0". Figure 16-5. Compare Match Output unit, schematic COMnx1 COMnx0 FOCnx Waveform Generator D Q 1 OCnx D DATA BUS 16.9 0 OCnx Pin Q PORT D Q DDR clk I/O The general I/O port function is overridden by the Output Compare (OCnx) from the Waveform Generator if either of the COMnx1:0 bits are set. However, the OCnx pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction Register bit for the OCnx pin (DDR_OCnx) must be set as output before the OCnx value is visible on the pin. The port override function is generally independent of the Waveform Generation mode, but there are some exceptions. Refer to Table 16-2, Table 163 and Table 16-4 for details. The design of the Output Compare pin logic allows initialization of the OCnx state before the output is enabled. Note that some COMnx1:0 bit settings are reserved for certain modes of operation. See "Register description" on page 136. The COMnx1:0 bits have no effect on the Input Capture unit. 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 126 ATmega164A/PA/324A/PA/644A/PA/1284/P 16.9.1 Compare Output Mode and Waveform Generation The Waveform Generator uses the COMnx1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COMnx1:0 = 0 tells the Waveform Generator that no action on the OCnx Register is to be performed on the next compare match. For compare output actions in the non-PWM modes refer to Table 16-2 on page 136. For fast PWM mode refer to Table 16-3 on page 136, and for phase correct and phase and frequency correct PWM refer to Table 16-4 on page 137. A change of the COMnx1:0 bits state will have effect at the first compare match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOCnx strobe bits. 16.10 Modes of Operation The mode of operation, that is, the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Generation mode (WGMn3:0) and Compare Output mode (COMnx1:0) bits. The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do. The COMnx1:0 bits control whether the PWM output generated should be inverted or not (inverted or noninverted PWM). For non-PWM modes the COMnx1:0 bits control whether the output should be set, cleared or toggle at a compare match (See "Compare Match Output unit" on page 126). For detailed timing information refer to "Timer/Counter Timing diagrams" on page 134. 16.10.1 Normal mode The simplest mode of operation is the Normal mode (WGMn3:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 16-bit value (MAX = 0xFFFF) and then restarts from the BOTTOM (0x0000). In normal operation the Timer/Counter Overflow Flag (TOVn) will be set in the same timer clock cycle as the TCNTn becomes zero. The TOVn Flag in this case behaves like a 17th bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt that automatically clears the TOVn Flag, the timer resolution can be increased by software. There are no special cases to consider in the Normal mode, a new counter value can be written anytime. The Input Capture unit is easy to use in Normal mode. However, observe that the maximum interval between the external events must not exceed the resolution of the counter. If the interval between events are too long, the timer overflow interrupt or the prescaler must be used to extend the resolution for the capture unit. The Output Compare units can be used to generate interrupts at some given time. Using the Output Compare to generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time. 16.10.2 Clear Timer on Compare Match (CTC) mode In Clear Timer on Compare or CTC mode (WGMn3:0 = 4 or 12), the OCRnA or ICRn Register are used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNTn) matches either the OCRnA (WGMn3:0 = 4) or the ICRn (WGMn3:0 = 12). The OCRnA or ICRn define the top value for the counter, hence also its resolution. This mode allows greater control of the compare match output frequency. It also simplifies the operation of counting external events. The timing diagram for the CTC mode is shown in Figure 16-6. The counter value (TCNTn) increases until a compare match occurs with either OCRnA or ICRn, and then counter (TCNTn) is cleared. 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 127 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 16-6. CTC mode, timing diagram OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TCNTn OCnA (Toggle) Period (COMnA1:0 = 1) 1 2 3 4 An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCFnA or ICFn Flag according to the register used to define the TOP value. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing the TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature. If the new value written to OCRnA or ICRn is lower than the current value of TCNTn, the counter will miss the compare match. The counter will then have to count to its maximum value (0xFFFF) and wrap around starting at 0x0000 before the compare match can occur. In many cases this feature is not desirable. An alternative will then be to use the fast PWM mode using OCRnA for defining TOP (WGMn3:0 = 15) since the OCRnA then will be double buffered. For generating a waveform output in CTC mode, the OCnA output can be set to toggle its logical level on each compare match by setting the Compare Output mode bits to toggle mode (COMnA1:0 = 1). The OCnA value will not be visible on the port pin unless the data direction for the pin is set to output (DDR_OCnA = 1). The waveform generated will have a maximum frequency of fOCnA = fclk_I/O/2 when OCRnA is set to zero (0x0000). The waveform frequency is defined by the following equation: f clk_I/O f OCnA = --------------------------------------------------2 N 1 + OCRnA The N variable represents the prescaler factor (1, 8, 64, 256, or 1024). As for the Normal mode of operation, the TOVn Flag is set in the same timer clock cycle that the counter counts from MAX to 0x0000. 16.10.3 Fast PWM mode The fast Pulse Width Modulation or fast PWM mode (WGMn3:0 = 5, 6, 7, 14, or 15) provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM options by its single-slope operation. The counter counts from BOTTOM to TOP then restarts from BOTTOM. In non-inverting Compare Output mode, the Output Compare (OCnx) is cleared on the compare match between TCNTn and OCRnx, and set at BOTTOM. In inverting Compare Output mode output is set on compare match and cleared at BOTTOM. Due to the single-slope operation, the operating frequency of the fast PWM mode can be twice as high as the phase correct and phase and frequency correct PWM modes that use dual-slope operation. This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capacitors), hence reduces total system cost. The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICRn or OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to 0x0003), and the maximum resolution is 16-bit (ICRn or OCRnA set to MAX). The PWM resolution in bits can be calculated by using the following equation: log TOP + 1 R FPWM = ----------------------------------log 2 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 128 ATmega164A/PA/324A/PA/644A/PA/1284/P In fast PWM mode the counter is incremented until the counter value matches either one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGMn3:0 = 5, 6, or 7), the value in ICRn (WGMn3:0 = 14), or the value in OCRnA (WGMn3:0 = 15). The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in Figure 16-7. The figure shows fast PWM mode when OCRnA or ICRn is used to define TOP. The TCNTn value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNTn slopes represent compare matches between OCRnx and TCNTn. The OCnx Interrupt Flag will be set when a compare match occurs. Figure 16-7. Fast PWM mode, timing diagram OCRnx/TOP Update and TOVn Interrupt Flag Set and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period 1 2 3 4 5 6 7 8 The Timer/Counter Overflow Flag (TOVn) is set each time the counter reaches TOP. In addition the OCnA or ICFn Flag is set at the same timer clock cycle as TOVn is set when either OCRnA or ICRn is used for defining the TOP value. If one of the interrupts are enabled, the interrupt handler routine can be used for updating the TOP and compare values. When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the Compare Registers. If the TOP value is lower than any of the Compare Registers, a compare match will never occur between the TCNTn and the OCRnx. Note that when using fixed TOP values the unused bits are masked to zero when any of the OCRnx Registers are written. The procedure for updating ICRn differs from updating OCRnA when used for defining the TOP value. The ICRn Register is not double buffered. This means that if ICRn is changed to a low value when the counter is running with none or a low prescaler value, there is a risk that the new ICRn value written is lower than the current value of TCNTn. The result will then be that the counter will miss the compare match at the TOP value. The counter will then have to count to the MAX value (0xFFFF) and wrap around starting at 0x0000 before the compare match can occur. The OCRnA Register however, is double buffered. This feature allows the OCRnA I/O location to be written anytime. When the OCRnA I/O location is written the value written will be put into the OCRnA Buffer Register. The OCRnA Compare Register will then be updated with the value in the Buffer Register at the next timer clock cycle the TCNTn matches TOP. The update is done at the same timer clock cycle as the TCNTn is cleared and the TOVn Flag is set. Using the ICRn Register for defining TOP works well when using fixed TOP values. By using ICRn, the OCRnA Register is free to be used for generating a PWM output on OCnA. However, if the base PWM frequency is actively changed (by changing the TOP value), using the OCRnA as TOP is clearly a better choice due to its double buffer feature. In fast PWM mode, the compare units allow generation of PWM waveforms on the OCnx pins. Setting the COMnx1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COMnx1:0 to three (see Table on page 136). The actual OCnx value will only be visible on the port 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 129 ATmega164A/PA/324A/PA/644A/PA/1284/P pin if the data direction for the port pin is set as output (DDR_OCnx). The PWM waveform is generated by setting (or clearing) the OCnx Register at the compare match between OCRnx and TCNTn, and clearing (or setting) the OCnx Register at the timer clock cycle the counter is cleared (changes from TOP to BOTTOM). The PWM frequency for the output can be calculated by the following equation: f clk_I/O f OCnxPWM = ----------------------------------N 1 + TOP The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). The extreme values for the OCRnx Register represents special cases when generating a PWM waveform output in the fast PWM mode. If the OCRnx is set equal to BOTTOM (0x0000) the output will be a narrow spike for each TOP+1 timer clock cycle. Setting the OCRnx equal to TOP will result in a constant high or low output (depending on the polarity of the output set by the COMnx1:0 bits.) A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OCnA to toggle its logical level on each compare match (COMnA1:0 = 1). This applies only if OCR1A is used to define the TOP value (WGM13:0 = 15). The waveform generated will have a maximum frequency of fOCnA = fclk_I/O/2 when OCRnA is set to zero (0x0000). This feature is similar to the OCnA toggle in CTC mode, except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode. 16.10.4 Phase Correct PWM mode The phase correct Pulse Width Modulation or phase correct PWM mode (WGMn3:0 = 1, 2, 3, 10, or 11) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is, like the phase and frequency correct PWM mode, based on a dual-slope operation. The counter counts repeatedly from BOTTOM (0x0000) to TOP and then from TOP to BOTTOM. In non-inverting Compare Output mode, the Output Compare (OCnx) is cleared on the compare match between TCNTn and OCRnx while upcounting, and set on the compare match while downcounting. In inverting Output Compare mode, the operation is inverted. The dual-slope operation has lower maximum operation frequency than single slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. The PWM resolution for the phase correct PWM mode can be fixed to 8-, 9-, or 10-bit, or defined by either ICRn or OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to 0x0003), and the maximum resolution is 16-bit (ICRn or OCRnA set to MAX). The PWM resolution in bits can be calculated by using the following equation: log TOP + 1 R PCPWM = ----------------------------------log 2 In phase correct PWM mode the counter is incremented until the counter value matches either one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGMn3:0 = 1, 2, or 3), the value in ICRn (WGMn3:0 = 10), or the value in OCRnA (WGMn3:0 = 11). The counter has then reached the TOP and changes the count direction. The TCNTn value will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown on Figure 16-8. The figure shows phase correct PWM mode when OCRnA or ICRn is used to define TOP. The TCNTn value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNTn slopes represent compare matches between OCRnx and TCNTn. The OCnx Interrupt Flag will be set when a compare match occurs. 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 130 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 16-8. Phase Correct PWM mode, timing diagram OCRnx/TOP Update and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TOVn Interrupt Flag Set (Interrupt on Bottom) TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period 1 2 3 4 The Timer/Counter Overflow Flag (TOVn) is set each time the counter reaches BOTTOM. When either OCRnA or ICRn is used for defining the TOP value, the OCnA or ICFn Flag is set accordingly at the same timer clock cycle as the OCRnx Registers are updated with the double buffer value (at TOP). The Interrupt Flags can be used to generate an interrupt each time the counter reaches the TOP or BOTTOM value. When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the Compare Registers. If the TOP value is lower than any of the Compare Registers, a compare match will never occur between the TCNTn and the OCRnx. Note that when using fixed TOP values, the unused bits are masked to zero when any of the OCRnx Registers are written. As the third period shown in Figure 16-8 illustrates, changing the TOP actively while the Timer/Counter is running in the phase correct mode can result in an unsymmetrical output. The reason for this can be found in the time of update of the OCRnx Register. Since the OCRnx update occurs at TOP, the PWM period starts and ends at TOP. This implies that the length of the falling slope is determined by the previous TOP value, while the length of the rising slope is determined by the new TOP value. When these two values differ the two slopes of the period will differ in length. The difference in length gives the unsymmetrical result on the output. It is recommended to use the phase and frequency correct mode instead of the phase correct mode when changing the TOP value while the Timer/Counter is running. When using a static TOP value there are practically no differences between the two modes of operation. In phase correct PWM mode, the compare units allow generation of PWM waveforms on the OCnx pins. Setting the COMnx1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COMnx1:0 to three (See Table on page 137). The actual OCnx value will only be visible on the port pin if the data direction for the port pin is set as output (DDR_OCnx). The PWM waveform is generated by setting (or clearing) the OCnx Register at the compare match between OCRnx and TCNTn when the counter increments, and clearing (or setting) the OCnx Register at compare match between OCRnx and TCNTn when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: f clk_I/O f OCnxPCPWM = ---------------------------2 N TOP The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 131 ATmega164A/PA/324A/PA/644A/PA/1284/P The extreme values for the OCRnx Register represent special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCRnx is set equal to BOTTOM the output will be continuously low and if set equal to TOP the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. If OCR1A is used to define the TOP value (WGM13:0 = 11) and COM1A1:0 = 1, the OC1A output will toggle with a 50% duty cycle. 16.10.5 Phase and Frequency Correct PWM mode The phase and frequency correct Pulse Width Modulation, or phase and frequency correct PWM mode (WGMn3:0 = 8 or 9) provides a high resolution phase and frequency correct PWM waveform generation option. The phase and frequency correct PWM mode is, like the phase correct PWM mode, based on a dual-slope operation. The counter counts repeatedly from BOTTOM (0x0000) to TOP and then from TOP to BOTTOM. In non-inverting Compare Output mode, the Output Compare (OCnx) is cleared on the compare match between TCNTn and OCRnx while upcounting, and set on the compare match while downcounting. In inverting Compare Output mode, the operation is inverted. The dual-slope operation gives a lower maximum operation frequency compared to the single-slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. The main difference between the phase correct, and the phase and frequency correct PWM mode is the time the OCRnx Register is updated by the OCRnx Buffer Register, (see Figure 16-8 and Figure 16-9). The PWM resolution for the phase and frequency correct PWM mode can be defined by either ICRn or OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to 0x0003), and the maximum resolution is 16-bit (ICRn or OCRnA set to MAX). The PWM resolution in bits can be calculated using the following equation: log TOP + 1 R PFCPWM = ----------------------------------log 2 In phase and frequency correct PWM mode the counter is incremented until the counter value matches either the value in ICRn (WGMn3:0 = 8), or the value in OCRnA (WGMn3:0 = 9). The counter has then reached the TOP and changes the count direction. The TCNTn value will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct and frequency correct PWM mode is shown on Figure 16-9. The figure shows phase and frequency correct PWM mode when OCRnA or ICRn is used to define TOP. The TCNTn value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNTn slopes represent compare matches between OCRnx and TCNTn. The OCnx Interrupt Flag will be set when a compare match occurs. 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 132 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 16-9. Phase and Frequency Correct PWM mode, timing diagram OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) OCRnx/TOP Updateand TOVn Interrupt Flag Set (Interrupt on Bottom) TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period 1 2 3 4 The Timer/Counter Overflow Flag (TOVn) is set at the same timer clock cycle as the OCRnx Registers are updated with the double buffer value (at BOTTOM). When either OCRnA or ICRn is used for defining the TOP value, the OCnA or ICFn Flag set when TCNTn has reached TOP. The Interrupt Flags can then be used to generate an interrupt each time the counter reaches the TOP or BOTTOM value. When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the Compare Registers. If the TOP value is lower than any of the Compare Registers, a compare match will never occur between the TCNTn and the OCRnx. As Figure 16-9 shows the output generated is, in contrast to the phase correct mode, symmetrical in all periods. Since the OCRnx Registers are updated at BOTTOM, the length of the rising and the falling slopes will always be equal. This gives symmetrical output pulses and is therefore frequency correct. Using the ICRn Register for defining TOP works well when using fixed TOP values. By using ICRn, the OCRnA Register is free to be used for generating a PWM output on OCnA. However, if the base PWM frequency is actively changed by changing the TOP value, using the OCRnA as TOP is clearly a better choice due to its double buffer feature. In phase and frequency correct PWM mode, the compare units allow generation of PWM waveforms on the OCnx pins. Setting the COMnx1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COMnx1:0 to three (See Table 16-4 on page 137). The actual OCnx value will only be visible on the port pin if the data direction for the port pin is set as output (DDR_OCnx). The PWM waveform is generated by setting (or clearing) the OCnx Register at the compare match between OCRnx and TCNTn when the counter increments, and clearing (or setting) the OCnx Register at compare match between OCRnx and TCNTn when the counter decrements. The PWM frequency for the output when using phase and frequency correct PWM can be calculated by the following equation: f clk_I/O f OCnxPFCPWM = ---------------------------2 N TOP The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). The extreme values for the OCRnx Register represents special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCRnx is set equal to BOTTOM the output will be continuously low and if set equal to TOP the output will be set to high for non-inverted PWM mode. For inverted PWM the 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 133 ATmega164A/PA/324A/PA/644A/PA/1284/P output will have the opposite logic values. If OCR1A is used to define the TOP value (WGM13:0 = 9) and COM1A1:0 = 1, the OC1A output will toggle with a 50% duty cycle. 16.11 Timer/Counter Timing diagrams The Timer/Counter is a synchronous design and the timer clock (clkTn) is therefore shown as a clock enable signal in the following figures. The figures include information on when Interrupt Flags are set, and when the OCRnx Register is updated with the OCRnx buffer value (only for modes utilizing double buffering). Figure 1610 shows a timing diagram for the setting of OCFnx. Figure 16-10. Timer/Counter Timing diagram, setting of OCFnx, no prescaling clkI/O clkTn (clkI/O /1) TCNTn OCRnx - 1 OCRnx OCRnx OCRnx + 1 OCRnx + 2 OCRnx Value OCFnx Figure 16-11 shows the same timing data, but with the prescaler enabled. Figure 16-11. Timer/Counter Timing diagram, setting of OCFnx, with prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn OCRnx OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2 OCRnx Value OCFnx Figure 16-12 shows the count sequence close to TOP in various modes. When using phase and frequency correct PWM mode the OCRnx Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on. The same renaming applies for modes that set the TOVn Flag at BOTTOM. 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 134 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 16-12. Timer/Counter Timing diagram, no prescaling clkI/O clkTn (clkI/O /1) TCNTn (CTC and FPWM) TCNTn (PC and PFC PWM) TOP - 1 TOP BOTTOM BOTTOM + 1 TOP - 1 TOP TOP - 1 TOP - 2 TOVn (FPWM) and ICFn (if used as TOP) OCRnx (Update at TOP) New OCRnx Value Old OCRnx Value Figure 16-13 shows the same timing data, but with the prescaler enabled. Figure 16-13. Timer/Counter Timing diagram, with prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O/8) TCNTn (CTC and FPWM) TCNTn (PC and PFC PWM) TOP - 1 TOP BOTTOM BOTTOM + 1 TOP - 1 TOP TOP - 1 TOP - 2 TOVn (FPWM) and ICF n (if used as TOP) OCRnx (Update at TOP) 2018 Microchip Technology Inc. Old OCRnx Value Data Sheet Complete New OCRnx Value DS40002070A-page 135 ATmega164A/PA/324A/PA/644A/PA/1284/P 16.12 Register description 16.12.1 TCCRnA - Timer/Counter n Control Register A Bit 7 6 5 4 3 2 1 0 COMnA1 COMnA0 COMnB1 COMnB0 - - WGMn1 WGMn0 Read/Write R/W R/W R/W R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0x80) TCCRnA * Bit 7:6 - COMnA1:0: Compare Output Mode for Channel A * Bit 5:4 - COMnB1:0: Compare Output Mode for Channel B The COMnA1:0 and COMnB1:0 control the Output Compare pins (OCnA and OCnB respectively) behavior. If one or both of the COMnA1:0 bits are written to one, the OCnA output overrides the normal port functionality of the I/O pin it is connected to. If one or both of the COMnB1:0 bit are written to one, the OCnB output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to the OCnA or OCnB pin must be set in order to enable the output driver. When the OCnA or OCnB is connected to the pin, the function of the COMnx1:0 bits is dependent of the WGMn3:0 bits setting. Table 16-2 on page 136 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to a Normal or a CTC mode (non-PWM). Table 16-2. Compare Output mode, non-PWM COMnA1/COMnB1 COMnA0/COMnB0 Description 0 0 Normal port operation, OCnA/OCnB disconnected. 0 1 Toggle OCnA/OCnB on Compare Match. 1 0 Clear OCnA/OCnB on Compare Match (Set output to low level). 1 1 Set OCnA/OCnB on Compare Match (Set output to high level). Table 16-3 on page 136 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the fast PWM mode. Compare Output mode, fast PWM (1) Table 16-3. COMnA1/COMnB1 COMnA0/COMnB0 0 0 Normal port operation, OCnA/OCnB disconnected. 0 1 WGMn3:0 = 14 or 15: Toggle OC1A on Compare Match, OC1B disconnected (normal port operation). For all other WGM1 settings, normal port operation, OC1A/OC1B disconnected. 1 0 Clear OCnA/OCnB on Compare Match, set OCnA/OCnB at BOTTOM (non-inverting mode) 1 1 Set OCnA/OCnB on Compare Match, clear OCnA/OCnB at BOTTOM (inverting mode) Note: 1. Description A special case occurs when OCRnA/OCRnB equals TOP and COMnA1/COMnB1 is set. In this case the compare match is ignored, but the set or clear is done at BOTTOM. See Section "16.10.3" on page 128 for more details. 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 136 ATmega164A/PA/324A/PA/644A/PA/1284/P Table 16-4 on page 137 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the phase correct or the phase and frequency correct, PWM mode. Compare Output mode, phase correct and phase and frequency correct PWM (1) Table 16-4. COMnA1/COMnB1 COMnA0/COMnB0 0 0 Normal port operation, OCnA/OCnB disconnected. 0 1 WGMn3:0 = 9 or 11: Toggle OCnA on Compare Match, OCnB disconnected (normal port operation). For all other WGM1 settings, normal port operation, OC1A/OC1B disconnected. 1 0 Clear OCnA/OCnB on Compare Match when upcounting. Set OCnA/OCnB on Compare Match when downcounting. 1 1 Set OCnA/OCnB on Compare Match when upcounting. Clear OCnA/OCnB on Compare Match when downcounting. Note: 1. Description A special case occurs when OCRnA/OCRnB equals TOP and COMnA1/COMnB1 is set. See Section "16.10.4" on page 130 for more details. * Bit 1:0 - WGMn1:0: Waveform Generation Mode Combined with the WGMn3:2 bits found in the TCCRnB Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used, see Table 16-5 on page 138. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. (See Section "16.10" on page 127). 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 137 ATmega164A/PA/324A/PA/644A/PA/1284/P Waveform Generation mode bit description (1) Table 16-5. Mode WGMn3 WGMn2 (CTCn) WGMn1 (PWMn1) WGMn0 (PWMn0) Timer/Counter mode of operation TOP Update of OCRnx at TOVn flag set on 0 0 0 0 0 Normal 0xFFFF Immediate MAX 1 0 0 0 1 PWM, Phase Correct, 8-bit 0x00FF TOP BOTTOM 2 0 0 1 0 PWM, Phase Correct, 9-bit 0x01FF TOP BOTTOM 3 0 0 1 1 PWM, Phase Correct, 10-bit 0x03FF TOP BOTTOM 4 0 1 0 0 CTC OCRnA Immediate MAX 5 0 1 0 1 Fast PWM, 8-bit 0x00FF BOTTOM TOP 6 0 1 1 0 Fast PWM, 9-bit 0x01FF BOTTOM TOP 7 0 1 1 1 Fast PWM, 10-bit 0x03FF BOTTOM TOP 8 1 0 0 0 PWM, Phase and Frequency Correct ICRn BOTTOM BOTTOM 9 1 0 0 1 PWM, Phase and Frequency Correct OCRnA BOTTOM BOTTOM 10 1 0 1 0 PWM, Phase Correct ICRn TOP BOTTOM 11 1 0 1 1 PWM, Phase Correct OCRnA TOP BOTTOM 12 1 1 0 0 CTC ICRn Immediate MAX 13 1 1 0 1 (Reserved) - - - 14 1 1 1 0 Fast PWM ICRn BOTTOM TOP 15 1 1 1 1 Fast PWM OCRnA BOTTOM TOP Note: 1. The CTCn and PWMn1:0 bit definition names are obsolete. Use the WGMn2:0 definitions. However, the functionality and location of these bits are compatible with previous versions of the timer. 16.12.2 TCCRnB - Timer/Counter n Control Register B Bit 7 6 5 4 3 2 1 0 ICNCn ICESn - WGMn3 WGMn2 CSn2 CSn1 CSn0 Read/Write R/W R/W R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0x81) TCCRnB * Bit 7 - ICNCn: Input Capture Noise Canceler Setting this bit (to one) activates the Input Capture Noise Canceler. When the noise canceler is activated, the input from the Input Capture pin (ICPn) is filtered. The filter function requires four successive equal valued samples of the ICPn pin for changing its output. The Input Capture is therefore delayed by four Oscillator cycles when the noise canceler is enabled. * Bit 6 - ICESn: Input Capture Edge Select This bit selects which edge on the Input Capture pin (ICPn) that is used to trigger a capture event. When the ICESn bit is written to zero, a falling (negative) edge is used as trigger, and when the ICESn bit is written to one, a rising (positive) edge will trigger the capture. When a capture is triggered according to the ICESn setting, the counter value is copied into the Input Capture Register (ICRn). The event will also set the Input Capture Flag (ICFn), and this can be used to cause an Input Capture Interrupt, if this interrupt is enabled. 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 138 ATmega164A/PA/324A/PA/644A/PA/1284/P When the ICRn is used as TOP value (see description of the WGMn3:0 bits located in the TCCRnA and the TCCRnB Register), the ICPn is disconnected and consequently the Input Capture function is disabled. * Bit 5 - Reserved This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be written to zero when TCCRnB is written. * Bit 4:3 - WGMn3:2: Waveform Generation Mode See "TCCRnA - Timer/Counter n Control Register A description on page 136. * Bit 2:0 - CSn2:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter, see Figure 16-10 and Figure 16-11. Table 16-6. Clock Select bit description CSn2 CSn1 CSn0 Description 0 0 0 No clock source (Timer/Counter stopped). 0 0 1 clkI/O/1 (No prescaling) 0 1 0 clkI/O/8 (From prescaler) 0 1 1 clkI/O/64 (From prescaler) 1 0 0 clkI/O/256 (From prescaler) 1 0 1 clkI/O/1024 (From prescaler) 1 1 0 External clock source on Tn pin. Clock on falling edge. 1 1 1 External clock source on Tn pin. Clock on rising edge. If external pin modes are used for the Timer/Countern, transitions on the Tn pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting. 16.12.3 TCCRnC - Timer/Counter n Control Register C Bit 7 6 5 4 3 2 1 FOCnA FOCnB - - - - - - Read/Write R/W R/W R R R R R R Initial Value 0 0 0 0 0 0 0 0 (0x82) 0 TCCRnC * Bit 7 - FOCnA: Force Output Compare for Channel A * Bit 6 - FOCnB: Force Output Compare for Channel B The FOCnA/FOCnB bits are only active when the WGMn3:0 bits specifies a non-PWM mode. However, for ensuring compatibility with future devices, these bits must be set to zero when TCCRnA is written when operating in a PWM mode. When writing a logical one to the FOCnA/FOCnB bit, an immediate compare match is forced on the Waveform Generation unit. The OCnA/OCnB output is changed according to its COMnx1:0 bits setting. Note that the FOCnA/FOCnB bits are implemented as strobes. Therefore it is the value present in the COMnx1:0 bits that determine the effect of the forced compare. A FOCnA/FOCnB strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare match (CTC) mode using OCRnA as TOP. The FOCnA/FOCnB bits are always read as zero. 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 139 ATmega164A/PA/324A/PA/644A/PA/1284/P 16.12.4 TCNT1H and TCNT1L -Timer/Counter1 Bit 7 6 5 4 3 (0x85) TCNT1[15:8] (0x84) TCNT1[7:0] 2 1 0 TCNT1H TCNT1L Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The two Timer/Counter I/O locations (TCNT1H and TCNT1L, combined TCNT1) give direct access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See "Accessing 16-bit Registers" on page 117. Modifying the counter (TCNT1) while the counter is running introduces a risk of missing a compare match between TCNT1 and one of the OCRnx Registers. Writing to the TCNT1 Register blocks (removes) the compare match on the following timer clock for all compare units. 16.12.5 TCNT3H and TCNT3L -Timer/Counter3 Bit 7 6 5 4 3 (0x95) TCNT3[15:8] (0x94) TCNT3[7:0] 2 1 0 TCNT3H TCNT3L Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The two Timer/Counter I/O locations (TCNT3H and TCNT3L, combined TCNT3) give direct access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See "Accessing 16-bit Registers" on page 117. Modifying the counter (TCNT3) while the counter is running introduces a risk of missing a compare match between TCNT3 and one of the OCRnx Registers. Writing to the TCNT3 Register blocks (removes) the compare match on the following timer clock for all compare units. 16.12.6 OCR1AH and OCR1AL - Output Compare Register1 A Bit 7 6 5 4 3 (0x89) OCR1A[15:8] (0x88) OCR1A[7:0] 2 1 0 OCR1AH OCR1AL Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 2 1 0 16.12.7 OCR1BH and OCR1BL - Output Compare Register1 B Bit 7 6 5 4 3 (0x8B) OCR1B[15:8] (0x8A) OCR1B[7:0] OCR1BH OCR1BL Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value (TCNT1). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OCnx pin. 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 140 ATmega164A/PA/324A/PA/644A/PA/1284/P The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See "Accessing 16-bit Registers" on page 117. 16.12.8 OCR3AH and OCR3AL - Output Compare Register3 A Bit 7 6 5 4 3 (0x99) OCR3A[15:8] (0x98) OCR3A[7:0] 2 1 0 OCR3AH OCR3AL Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 2 1 0 16.12.9 OCR3BH and OCR3BL - Output Compare Register3 B Bit 7 6 5 4 3 (0x9B) OCR3B[15:8] (0x9A) OCR3B[7:0] OCR3BH OCR3BL Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value (TCNT3). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OCnx pin. The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See "Accessing 16-bit Registers" on page 117. 16.12.10ICR1H and ICR1L - Input Capture Register 1 Bit 7 6 5 4 3 (0x87) ICR1[15:8] (0x86) ICR1[7:0] 2 1 0 ICR1H ICR1L Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the ICPn pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture can be used for defining the counter TOP value. The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See "Accessing 16-bit Registers" on page 117. 16.12.11ICR3H and ICR3L - Input Capture Register 3 Bit 7 6 5 4 3 (0x97) ICR3[15:8] (0x96) ICR3[7:0] 2 1 0 ICR3H ICR3L Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 141 ATmega164A/PA/324A/PA/644A/PA/1284/P The Input Capture is updated with the counter (TCNT3) value each time an event occurs on the ICPn pin (or optionally on the Analog Comparator output for Timer/Counter3). The Input Capture can be used for defining the counter TOP value. The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See "Accessing 16-bit Registers" on page 117. 16.12.12TIMSK1 - Timer/Counter1 Interrupt Mask Register Bit 7 6 5 4 3 2 1 0 (0x6F) - - ICIE1 - - OCIE1B OCIE1A TOIE1 Read/Write R R R/W R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TIMSK1 * Bit 7:6 - Reserved These bits are unused and will always read as zero. * Bit 5 - ICIE1: Timer/Counter1, Input Capture Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt Vector (see "Interrupts" on page 69) is executed when the ICF1 Flag, located in TIFR1, is set. * Bit 4:3 - Reserved These bits are unused and will always read as zero. * Bit 2 - OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Output Compare B Match interrupt is enabled. The corresponding Interrupt Vector (see "Interrupts" on page 69) is executed when the OCF1B Flag, located in TIFR1, is set. * Bit 1 - OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Output Compare A Match interrupt is enabled. The corresponding Interrupt Vector (see "Interrupts" on page 69) is executed when the OCF1A Flag, located in TIFR1, is set. * Bit 0 - TOIE1: Timer/Counter1, Overflow Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Overflow interrupt is enabled. The corresponding Interrupt Vector (See Section "11.3" on page 63) is executed when the TOV1 Flag, located in TIFR1, is set. 16.12.13TIMSK3 - Timer/Counter3 Interrupt Mask Register Bit 7 6 5 4 3 2 1 0 (0x71) - - ICIE3 - - OCIE3B OCIE3A TOIE3 Read/Write R R R/W R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TIMSK3 * Bit 7:6 - Reserved These bits are unused and will always read as zero. 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 142 ATmega164A/PA/324A/PA/644A/PA/1284/P * Bit 5 - ICIE3: Timer/Counter3, Input Capture Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt Vector (See "Interrupts" on page 69) is executed when the ICF3 Flag, located in TIFR3, is set. * Bit 4:3 - Reserved These bits are unused and will always read as zero. * Bit 2 - OCIE3B: Timer/Counter3, Output Compare B Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter3 Output Compare B Match interrupt is enabled. The corresponding Interrupt Vector (See "Interrupts" on page 69) is executed when the OCF3B Flag, located in TIFR3, is set. * Bit 1 - OCIE3A: Timer/Counter3, Output Compare A Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter3 Output Compare A Match interrupt is enabled. The corresponding Interrupt Vector (See "Interrupts" on page 69) is executed when the OCF3A Flag, located in TIFR3, is set. * Bit 0 - TOIE3: Timer/Counter3, Overflow Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter3 Overflow interrupt is enabled. The corresponding Interrupt Vector (See "Watchdog Timer" on page 63) is executed when the TOV3 Flag, located in TIFR3, is set. 16.12.14TIFR1 - Timer/Counter1 Interrupt Flag Register Bit 7 6 5 4 3 2 1 0 0x16 (0x36) - - ICF1 - - OCF1B OCF1A TOV1 Read/Write R R R/W R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TIFR1 * Bit 7:6 - Reserved These bits are unused and will always read as zero. * Bit 5 - ICF1: Timer/Counter1, Input Capture Flag This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register (ICR1) is set by the WGMn3:0 to be used as the TOP value, the ICF1 Flag is set when the counter reaches the TOP value. ICF1 is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively, ICF1 can be cleared by writing a logic one to its bit location. * Bit 4:3 - Reserved These bits are unused and will always read as zero. * Bit 2 - OCF1B: Timer/Counter1, Output Compare B Match Flag This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output Compare Register B (OCR1B). Note that a Forced Output Compare (FOC1B) strobe will not set the OCF1B Flag. OCF1B is automatically cleared when the Output Compare Match B Interrupt Vector is executed. Alternatively, OCF1B can be cleared by writing a logic one to its bit location. 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 143 ATmega164A/PA/324A/PA/644A/PA/1284/P * Bit 1 - OCF1A: Timer/Counter1, Output Compare A Match Flag This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output Compare Register A (OCR1A). Note that a Forced Output Compare (FOC1A) strobe will not set the OCF1A Flag. OCF1A is automatically cleared when the Output Compare Match A Interrupt Vector is executed. Alternatively, OCF1A can be cleared by writing a logic one to its bit location. * Bit 0 - TOV1: Timer/Counter1, Overflow Flag The setting of this flag is dependent of the WGMn3:0 bits setting. In Normal and CTC modes, the TOV1 Flag is set when the timer overflows. Refer to Table 16-5 on page 138 for the TOV1 Flag behavior when using another WGMn3:0 bit setting. TOV1 is automatically cleared when the Timer/Counter1 Overflow Interrupt Vector is executed. Alternatively, TOV1 can be cleared by writing a logic one to its bit location. 16.12.15TIFR3 - Timer/Counter3 Interrupt Flag Register Bit 7 6 5 4 3 2 1 0 0x18 (0x38) - - ICF3 - - OCF3B OCF3A TOV3 Read/Write R R R/W R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TIFR3 * Bit 7:6 - Reserved These bits are unused and will always read as zero. * Bit 5 - ICF3: Timer/Counter3, Input Capture Flag This flag is set when a capture event occurs on the ICP3 pin. When the Input Capture Register (ICR1) is set by the WGMn3:0 to be used as the TOP value, the ICF3 Flag is set when the counter reaches the TOP value. ICF3 is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively, ICF3 can be cleared by writing a logic one to its bit location. * Bit 4:3 - Reserved These bits are unused and will always read as zero. * Bit 2 - OCF3B: Timer/Counter3, Output Compare B Match Flag This flag is set in the timer clock cycle after the counter (TCNT3) value matches the Output Compare Register B (OCR3B). Note that a Forced Output Compare (FOC3B) strobe will not set the OCF3B Flag. OCF3B is automatically cleared when the Output Compare Match B Interrupt Vector is executed. Alternatively, OCF3B can be cleared by writing a logic one to its bit location. * Bit 1 - OCF3A: Timer/Counter3, Output Compare A Match Flag This flag is set in the timer clock cycle after the counter (TCNT3) value matches the Output Compare Register A (OCR3A). Note that a Forced Output Compare (FOC3A) strobe will not set the OCF3A Flag. OCF3A is automatically cleared when the Output Compare Match A Interrupt Vector is executed. Alternatively, OCF3A can be cleared by writing a logic one to its bit location. 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 144 ATmega164A/PA/324A/PA/644A/PA/1284/P * Bit 0 - TOV3: Timer/Counter1, Overflow Flag The setting of this flag is dependent of the WGMn3:0 bits setting. In Normal and CTC modes, the TOV3 Flag is set when the timer overflows. Refer to Table 16-5 on page 138 for the TOV3 Flag behavior when using another WGMn3:0 bit setting. TOV3 is automatically cleared when the Timer/Counter3 Overflow Interrupt Vector is executed. Alternatively, TOV3 can be cleared by writing a logic one to its bit location. 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 145 ATmega164A/PA/324A/PA/644A/PA/1284/P 17. 8-bit Timer/Counter2 with PWM and asynchronous operation 17.1 Features * * * * * * * Overview Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module. A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 16-12.. For the actual placement of I/O pins, see "Pin configurations" on page 11. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the "Register description" on page 159. The Power Reduction Timer/Counter2 bit, PRTIM2, in "PRR0 - Power Reduction Register 0" on page 56 must be written to zero to enable Timer/Counter2 module. Figure 17-1. 8-bit Timer/Counter block diagram Count TOVn (Int.Req.) Clear Direction Control Logic clkTn TOSC1 T/C Oscillator TOP BOTTOM TOSC2 Prescaler clkI/O Timer/Counter TCNTn = =0 OCnA (Int.Req.) Waveform Generation = OCnA OCRnA Fixed TOP Value DATA BUS 17.2 Single channel counter Clear Timer on Compare Match (Auto Reload) Glitch-free, phase correct Pulse Width Modulator (PWM) Frequency generator 10-bit clock prescaler Overflow and Compare Match Interrupt Sources (TOV2, OCF2A and OCF2B) Allows clocking from external 32kHz watch crystal independent of the I/O clock Waveform Generation = OCRnB OCnB (Int.Req.) Synchronized Status flags Synchronization Unit OCnB clkI/O clkASY Status flags ASSRn TCCRnA 2018 Microchip Technology Inc. asynchronous mode select (ASn) TCCRnB Data Sheet Complete DS40002070A-page 146 ATmega164A/PA/324A/PA/644A/PA/1284/P 17.2.1 Registers The Timer/Counter (TCNT2) and Output Compare Register (OCR2A and OCR2B) are 8-bit registers. Interrupt request (abbreviated to Int.Req.) signals are all visible in the Timer Interrupt Flag Register (TIFR2). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK2). TIFR2 and TIMSK2 are not shown in the figure. The Timer/Counter can be clocked internally, via the prescaler, or asynchronously clocked from the TOSC1/2 pins, as detailed later in this section. The asynchronous operation is controlled by the Asynchronous Status Register (ASSR). The Clock Select logic block controls which clock source the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is referred to as the timer clock (clkT2). The double buffered Output Compare Register (OCR2A and OCR2B) are compared with the Timer/Counter value at all times. The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency output on the Output Compare pins (OC2A and OC2B). See "Output Compare unit" on page 148 for details. The compare match event will also set the Compare Flag (OCF2A or OCF2B) which can be used to generate an Output Compare interrupt request. 17.2.2 Definitions Many register and bit references in this document are written in general form. A lower case "n" replaces the Timer/Counter number, in this case 2. However, when using the register or bit defines in a program, the precise form must be used, that is, TCNT2 for accessing Timer/Counter2 counter value and so on. The definitions in Table 17-1 are also used extensively throughout the section. Table 17-1. 17.3 Definitions BOTTOM The counter reaches the BOTTOM when it becomes zero (0x00). MAX The counter reaches its MAXimum when it becomes 0xFF (decimal 255). TOP The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be the fixed value 0xFF (MAX) or the value stored in the OCR2A Register. The assignment is dependent on the mode of operation. Timer/Counter clock sources The Timer/Counter can be clocked by an internal synchronous or an external asynchronous clock source. The clock source clkT2 is by default equal to the MCU clock, clkI/O. When the AS2 bit in the ASSR Register is written to logic one, the clock source is taken from the Timer/Counter Oscillator connected to TOSC1 and TOSC2. For details on asynchronous operation, see "ASSR - Asynchronous Status Register" on page 163. For details on clock sources and prescaler, see "Timer/Counter Prescaler" on page 158. 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 147 ATmega164A/PA/324A/PA/644A/PA/1284/P 17.4 Counter unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 17-2 shows a block diagram of the counter and its surrounding environment. Figure 17-2. Counter Unit block diagram TOVn (Int.Req.) DATA BUS TOSC1 count TCNTn clear clk Tn Control Logic Prescaler T/C Oscillator direction bottom TOSC2 top clkI/O Signal description (internal signals): count Increment or decrement TCNT2 by 1. direction Selects between increment and decrement. clear Clear TCNT2 (set all bits to zero). clkTn Timer/Counter clock, referred to as clkT2 in the following. top Signalizes that TCNT2 has reached maximum value. bottom Signalizes that TCNT2 has reached minimum value (zero). Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkT2). clkT2 can be generated from an external or internal clock source, selected by the Clock Select bits (CS22:0). When no clock source is selected (CS22:0 = 0) the timer is stopped. However, the TCNT2 value can be accessed by the CPU, regardless of whether clkT2 is present or not. A CPU write overrides (has priority over) all counter clear or count operations. The counting sequence is determined by the setting of the WGM21 and WGM20 bits located in the Timer/Counter Control Register (TCCR2A) and the WGM22 located in the Timer/Counter Control Register B (TCCR2B). There are close connections between how the counter behaves (counts) and how waveforms are generated on the Output Compare outputs OC2A and OC2B. For more details about advanced counting sequences and waveform generation, see "Modes of operation" on page 151. The Timer/Counter Overflow Flag (TOV2) is set according to the mode of operation selected by the WGM22:0 bits. TOV2 can be used for generating a CPU interrupt. 17.5 Output Compare unit The 8-bit comparator continuously compares TCNT2 with the Output Compare Register (OCR2A and OCR2B). Whenever TCNT2 equals OCR2A or OCR2B, the comparator signals a match. A match will set the Output Compare Flag (OCF2A or OCF2B) at the next timer clock cycle. If the corresponding interrupt is enabled, the Output Compare Flag generates an Output Compare interrupt. The Output Compare Flag is automatically cleared when the interrupt is executed. Alternatively, the Output Compare Flag can be cleared by software by writing a logical one to its I/O bit location. The Waveform Generator uses the match signal to generate an output according to operating mode set by the WGM22:0 bits and Compare Output mode (COM2x1:0) bits. The max and bottom signals are used by the Waveform Generator for handling the special cases of the extreme values in some modes of operation (see "Modes of operation" on page 151). Figure 16-10 on page 134 shows a block diagram of the Output Compare unit. 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 148 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 17-3. Output Compare unit, block diagram DATA BUS OCRnx TCNTn = (8-bit Comparator ) OCFnx (Int.Req.) top bottom Waveform Generator OCnx FOCn WGMn1:0 COMnX1:0 The OCR2x Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR2x Compare Register to either top or bottom of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free. The OCR2x Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR2x Buffer Register, and if double buffering is disabled the CPU will access the OCR2x directly. 17.5.1 Force Output Compare In non-PWM waveform generation modes, the match output of the comparator can be forced by writing a one to the Force Output Compare (FOC2x) bit. Forcing compare match will not set the OCF2x Flag or reload/clear the timer, but the OC2x pin will be updated as if a real compare match had occurred (the COM2x1:0 bits settings define whether the OC2x pin is set, cleared or toggled). 17.5.2 Compare Match Blocking by TCNT2 Write All CPU write operations to the TCNT2 Register will block any compare match that occurs in the next timer clock cycle, even when the timer is stopped. This feature allows OCR2x to be initialized to the same value as TCNT2 without triggering an interrupt when the Timer/Counter clock is enabled. 17.5.3 Using the Output Compare Unit Since writing TCNT2 in any mode of operation will block all compare matches for one timer clock cycle, there are risks involved when changing TCNT2 when using the Output Compare channel, independently of whether the Timer/Counter is running or not. If the value written to TCNT2 equals the OCR2x value, the compare match will be missed, resulting in incorrect waveform generation. Similarly, do not write the TCNT2 value equal to BOTTOM when the counter is downcounting. The setup of the OC2x should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC2x value is to use the Force Output Compare (FOC2x) strobe bit in Normal mode. The OC2x Register keeps its value even when changing between Waveform Generation modes. 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 149 ATmega164A/PA/324A/PA/644A/PA/1284/P Be aware that the COM2x1:0 bits are not double buffered together with the compare value. Changing the COM2x1:0 bits will take effect immediately. 17.6 Compare Match Output unit The Compare Output mode (COM2x1:0) bits have two functions. The Waveform Generator uses the COM2x1:0 bits for defining the Output Compare (OC2x) state at the next compare match. Also, the COM2x1:0 bits control the OC2x pin output source. Figure 17-4 shows a simplified schematic of the logic affected by the COM2x1:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O Port Control Registers (DDR and PORT) that are affected by the COM2x1:0 bits are shown. When referring to the OC2x state, the reference is for the internal OC2x Register, not the OC2x pin. Figure 17-4. Compare Match Output unit, schematic COMnx1 COMnx0 FOCnx Waveform Generator D Q 1 OCnx DATA BUS D 0 OCnx Pin Q PORT D Q DDR clk I/O The general I/O port function is overridden by the Output Compare (OC2x) from the Waveform Generator if either of the COM2x1:0 bits are set. However, the OC2x pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction Register bit for the OC2x pin (DDR_OC2x) must be set as output before the OC2x value is visible on the pin. The port override function is independent of the Waveform Generation mode. The design of the Output Compare pin logic allows initialization of the OC2x state before the output is enabled. Note that some COM2x1:0 bit settings are reserved for certain modes of operation. See "Register description" on page 159. 17.6.1 Compare Output Mode and Waveform Generation The Waveform Generator uses the COM2x1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COM2x1:0 = 0 tells the Waveform Generator that no action on the OC2x Register is to be performed on the next compare match. For compare output actions in the non-PWM modes refer to Table 17-5 on page 160. For fast PWM mode, refer to Table 17-6 on page 160, and for phase correct PWM refer to Table 17-7 on page 161. A change of the COM2x1:0 bits state will have effect at the first compare match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOC2x strobe bits. 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 150 ATmega164A/PA/324A/PA/644A/PA/1284/P 17.7 Modes of operation The mode of operation, that is, the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Generation mode (WGM22:0) and Compare Output mode (COM2x1:0) bits. The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do. The COM2x1:0 bits control whether the PWM output generated should be inverted or not (inverted or noninverted PWM). For non-PWM modes the COM2x1:0 bits control whether the output should be set, cleared, or toggled at a compare match (See "Compare Match Output unit" on page 150). For detailed timing information refer to "Timer/Counter Timing diagrams" on page 155. 17.7.1 Normal Mode The simplest mode of operation is the Normal mode (WGM22:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bottom (0x00). In normal operation the Timer/Counter Overflow Flag (TOV2) will be set in the same timer clock cycle as the TCNT2 becomes zero. The TOV2 Flag in this case behaves like a ninth bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt that automatically clears the TOV2 Flag, the timer resolution can be increased by software. There are no special cases to consider in the Normal mode, a new counter value can be written anytime. The Output Compare unit can be used to generate interrupts at some given time. Using the Output Compare to generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time. 17.7.2 Clear Timer on Compare Match (CTC) Mode In Clear Timer on Compare or CTC mode (WGM22:0 = 2), the OCR2A Register is used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT2) matches the OCR2A. The OCR2A defines the top value for the counter, hence also its resolution. This mode allows greater control of the compare match output frequency. It also simplifies the operation of counting external events. The timing diagram for the CTC mode is shown in Table 17-5 on page 151. The counter value (TCNT2) increases until a compare match occurs between TCNT2 and OCR2A, and then counter (TCNT2) is cleared. Figure 17-5. CTC mode, timing diagram OCnx Interrupt Flag Set TCNTn OCnx (Toggle) Period (COMnx1:0 = 1) 1 2 3 4 An interrupt can be generated each time the counter value reaches the TOP value by using the OCF2A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature. If the new value written to OCR2A is lower than the current value of TCNT2, the counter will miss the compare match. The counter will then have to count to its maximum value (0xFF) and wrap around starting at 0x00 before the compare match can occur. 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 151 ATmega164A/PA/324A/PA/644A/PA/1284/P For generating a waveform output in CTC mode, the OC2A output can be set to toggle its logical level on each compare match by setting the Compare Output mode bits to toggle mode (COM2A1:0 = 1). The OC2A value will not be visible on the port pin unless the data direction for the pin is set to output. The waveform generated will have a maximum frequency of fOC2A = fclk_I/O/2 when OCR2A is set to zero (0x00). The waveform frequency is defined by the following equation: f clk_I/O f OCnx = -------------------------------------------------2 N 1 + OCRnx The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). As for the Normal mode of operation, the TOV2 Flag is set in the same timer clock cycle that the counter counts from MAX to 0x00. 17.7.3 Fast PWM mode The fast Pulse Width Modulation or fast PWM mode (WGM22:0 = 3 or 7) provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM option by its single-slope operation. The counter counts from BOTTOM to TOP then restarts from BOTTOM. TOP is defined as 0xFF when WGM22:0 = 3, and OCR2A when WGM22:0 = 7. In non-inverting Compare Output mode, the Output Compare (OC2x) is cleared on the compare match between TCNT2 and OCR2x, and set at BOTTOM. In inverting Compare Output mode, the output is set on compare match and cleared at BOTTOM. Due to the single-slope operation, the operating frequency of the fast PWM mode can be twice as high as the phase correct PWM mode that uses dual-slope operation. This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capacitors), and therefore reduces total system cost. In fast PWM mode, the counter is incremented until the counter value matches the TOP value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in Figure 17-6 on page 152. The TCNT2 value is in the timing diagram shown as a histogram for illustrating the singleslope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes represent compare matches between OCR2x and TCNT2. Figure 17-6. Fast PWM mode, timing diagram OCRnx Interrupt Flag Set OCRnx Update and TOVn Interrupt Flag Set TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period 1 2 3 4 5 6 7 The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches TOP. If the interrupt is enabled, the interrupt handler routine can be used for updating the compare value. 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 152 ATmega164A/PA/324A/PA/644A/PA/1284/P In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC2x pin. Setting the COM2x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM2x1:0 to three. TOP is defined as 0xFF when WGM2:0 = 3, and OCR2A when WGM2:0 = 7 (See Table 17-3 on page 159). The actual OC2x value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is generated by setting (or clearing) the OC2x Register at the compare match between OCR2x and TCNT2, and clearing (or setting) the OC2x Register at the timer clock cycle the counter is cleared (changes from TOP to BOTTOM). The PWM frequency for the output can be calculated by the following equation: f clk_I/O f OCnxPWM = -----------------N 256 The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). The extreme values for the OCR2A Register represent special cases when generating a PWM waveform output in the fast PWM mode. If the OCR2A is set equal to BOTTOM, the output will be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR2A equal to MAX will result in a constantly high or low output (depending on the polarity of the output set by the COM2A1:0 bits.) A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC2x to toggle its logical level on each compare match (COM2x1:0 = 1). The waveform generated will have a maximum frequency of foc2 = fclk_I/O/2 when OCR2A is set to zero. This feature is similar to the OC2A toggle in CTC mode, except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode. 17.7.4 Phase Correct PWM mode The phase correct PWM mode (WGM22:0 = 1 or 5) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly from BOTTOM to TOP and then from TOP to BOTTOM. TOP is defined as 0xFF when WGM22:0 = 1, and OCR2A when WGM22:0 = 5. In non-inverting Compare Output mode, the Output Compare (OC2x) is cleared on the compare match between TCNT2 and OCR2x while upcounting, and set on the compare match while downcounting. In inverting Output Compare mode, the operation is inverted. The dual-slope operation has lower maximum operation frequency than single slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. In phase correct PWM mode the counter is incremented until the counter value matches TOP. When the counter reaches TOP, it changes the count direction. The TCNT2 value will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown on Figure 17-7. The TCNT2 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes noninverted and inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes represent compare matches between OCR2x and TCNT2. 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 153 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 17-7. Phase Correct PWM mode, timing diagram OCnx Interrupt Flag Set OCRnx Update TOVn Interrupt Flag Set TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period 1 2 3 The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches BOTTOM. The Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC2x pin. Setting the COM2x1:0 bits to two will produce a non-inverted PWM. An inverted PWM output can be generated by setting the COM2x1:0 to three. TOP is defined as 0xFF when WGM2:0 = 3, and OCR2A when WGM2:0 = 7 (See Table 17-4 on page 160). The actual OC2x value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is generated by clearing (or setting) the OC2x Register at the compare match between OCR2x and TCNT2 when the counter increments, and setting (or clearing) the OC2x Register at compare match between OCR2x and TCNT2 when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: f clk_I/O f OCnxPCPWM = -----------------N 510 The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). The extreme values for the OCR2A Register represent special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCR2A is set equal to BOTTOM, the output will be continuously low and if set equal to MAX the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. At the very start of period 2 in Figure 17-7 on page 154 OCnx has a transition from high to low even though there is no Compare Match. The point of this transition is to guarantee symmetry around BOTTOM. There are two cases that give a transition without Compare Match. OCR2A changes its value from MAX, like in Figure 17-7 on page 154. When the OCR2A value is MAX the OCn pin value is the same as the result of a down-counting compare match. To ensure symmetry around BOTTOM the OCn value at MAX must correspond to the result of an up-counting Compare Match The timer starts counting from a value higher than the one in OCR2A, and for that reason misses the Compare Match and hence the OCn change that would have happened on the way up 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 154 ATmega164A/PA/324A/PA/644A/PA/1284/P 17.8 Timer/Counter Timing diagrams The following figures show the Timer/Counter in synchronous mode, and the timer clock (clkT2) is therefore shown as a clock enable signal. In asynchronous mode, clkI/O should be replaced by the Timer/Counter Oscillator clock. The figures include information on when Interrupt Flags are set. Figure 17-8 on page 155 contains timing data for basic Timer/Counter operation. The figure shows the count sequence close to the MAX value in all modes other than phase correct PWM mode. Figure 17-8. Timer/Counter Timing diagram, no prescaling clkI/O clkTn (clkI/O /1) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Figure 17-9 on page 155 shows the same timing data, but with the prescaler enabled. Figure 17-9. Timer/Counter Timing diagram, with prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Figure 17-10 on page 156 shows the setting of OCF2A in all modes except CTC mode. 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 155 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 17-10. Timer/Counter Timing diagram, setting of OCF2A, with prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2 OCRnx Value OCRnx OCFnx Figure 17-11 on page 156 shows the setting of OCF2A and the clearing of TCNT2 in CTC mode. Figure 17-11. Timer/Counter Timing diagram, Clear Timer on Compare Match mode, with prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn (CTC) TOP - 1 TOP OCRnx BOTTOM BOTTOM + 1 TOP OCFnx 17.9 Asynchronous Operation of Timer/Counter2 When Timer/Counter2 operates asynchronously, some considerations must be taken. Warning: When switching between asynchronous and synchronous clocking of Timer/Counter2, the Timer Registers TCNT2, OCR2x, and TCCR2x might be corrupted. A safe procedure for switching clock source is: 1. Disable the Timer/Counter2 interrupts by clearing OCIE2x and TOIE2. 2. Select clock source by setting AS2 as appropriate. 3. Write new values to TCNT2, OCR2x, and TCCR2x. 4. To switch to asynchronous operation: Wait for TCN2UB, OCR2xUB, and TCR2xUB. 5. Clear the Timer/Counter2 Interrupt Flags. 6. Enable interrupts, if needed. The CPU main clock frequency must be more than four times the Oscillator frequency When writing to one of the registers TCNT2, OCR2x, or TCCR2x, the value is transferred to a temporary register, and latched after two positive edges on TOSC1. The user should not write a new value before the contents of the temporary register have been transferred to its destination. Each of the five mentioned 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 156 ATmega164A/PA/324A/PA/644A/PA/1284/P registers have their individual temporary register, which means that e.g. writing to TCNT2 does not disturb an OCR2x write in progress. To detect that a transfer to the destination register has taken place, the Asynchronous Status Register - ASSR has been implemented When entering Power-save or ADC Noise Reduction mode after having written to TCNT2, OCR2x, or TCCR2x, the user must wait until the written register has been updated if Timer/Counter2 is used to wake up the device. Otherwise, the MCU will enter sleep mode before the changes are effective. This is particularly important if any of the Output Compare2 interrupt is used to wake up the device, since the Output Compare function is disabled during writing to OCR2x or TCNT2. If the write cycle is not finished, and the MCU enters sleep mode before the corresponding OCR2xUB bit returns to zero, the device will never receive a compare match interrupt, and the MCU will not wake up If Timer/Counter2 is used to wake the device up from Power-save or ADC Noise Reduction mode, precautions must be taken if the user wants to re-enter one of these modes: The interrupt logic needs one TOSC1 cycle to be reset. If the time between wake-up and re-entering sleep mode is less than one TOSC1 cycle, the interrupt will not occur, and the device will fail to wake up. If the user is in doubt whether the time before re-entering Power-save or ADC Noise Reduction mode is sufficient, the following algorithm can be used to ensure that one TOSC1 cycle has elapsed: 1. Write a value to TCCR2x, TCNT2, or OCR2x. 2. Wait until the corresponding Update Busy Flag in ASSR returns to zero. 3. Enter Power-save or ADC Noise Reduction mode. When the asynchronous operation is selected, the 32.768kHz Oscillator for Timer/Counter2 is always running, except in Power-down and Standby modes. After a Power-up Reset or wake-up from Powerdown or Standby mode, the user should be aware of the fact that this Oscillator might take as long as one second to stabilize. The user is advised to wait for at least one second before using Timer/Counter2 after power-up or wake-up from Power-down or Standby mode. The contents of all Timer/Counter2 Registers must be considered lost after a wake-up from Power-down or Standby mode due to unstable clock signal upon start-up, no matter whether the Oscillator is in use or a clock signal is applied to the TOSC1 pin Description of wake up from Power-save or ADC Noise Reduction mode when the timer is clocked asynchronously: When the interrupt condition is met, the wake up process is started on the following cycle of the timer clock, that is, the timer is always advanced by at least one before the processor can read the counter value. After wake-up, the MCU is halted for four cycles, it executes the interrupt routine, and resumes execution from the instruction following SLEEP Reading of the TCNT2 Register shortly after wake-up from Power-save may give an incorrect result. Since TCNT2 is clocked on the asynchronous TOSC clock, reading TCNT2 must be done through a register synchronized to the internal I/O clock domain. Synchronization takes place for every rising TOSC1 edge. When waking up from Power-save mode, and the I/O clock (clkI/O) again becomes active, TCNT2 will read as the previous value (before entering sleep) until the next rising TOSC1 edge. The phase of the TOSC clock after waking up from Power-save mode is essentially unpredictable, as it depends on the wake-up time. The recommended procedure for reading TCNT2 is thus as follows: 1. Write any value to either of the registers OCR2x or TCCR2x. 2. Wait for the corresponding Update Busy Flag to be cleared. 3. Read TCNT2. During asynchronous operation, the synchronization of the Interrupt Flags for the asynchronous timer takes 3 processor cycles plus one timer cycle. The timer is therefore advanced by at least one before the processor can read the timer value causing the setting of the Interrupt Flag. The Output Compare pin is changed on the timer clock and is not synchronized to the processor clock 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 157 ATmega164A/PA/324A/PA/644A/PA/1284/P 17.10 Timer/Counter Prescaler Figure 17-12. Prescaler for Timer/Counter2 PSRASY clkT2S/1024 clkT2S/256 clkT2S/128 AS2 clkT2S/64 10-BIT T/C PRESCALER Clear clkT2S/32 TOSC1 clkT2S clkT2S/8 clkI/O 0 CS20 CS21 CS22 TIMER/COUNTER2 CLOCK SOURCE clkT2 The clock source for Timer/Counter2 is named clkT2S. clkT2S is by default connected to the main system I/O clock clkIO. By setting the AS2 bit in ASSR, Timer/Counter2 is asynchronously clocked from the TOSC1 pin. This enables use of Timer/Counter2 as a Real Time Counter (RTC). When AS2 is set, pins TOSC1 and TOSC2 are disconnected from Port C. A crystal can then be connected between the TOSC1 and TOSC2 pins to serve as an independent clock source for Timer/Counter2. The Oscillator is optimized for use with a 32.768kHz crystal. By setting the EXCLK bit in the ASSR a 32kHz external clock can be applied. See "ASSR - Asynchronous Status Register" on page 163 for details. For Timer/Counter2, the possible prescaled selections are: clkT2S/8, clkT2S/32, clkT2S/64, clkT2S/128, clkT2S/256, and clkT2S/1024. Additionally, clkT2S as well as 0 (stop) may be selected. Setting the PSRASY bit in GTCCR resets the prescaler. This allows the user to operate with a predictable prescaler. 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 158 ATmega164A/PA/324A/PA/644A/PA/1284/P 17.11 Register description 17.11.1 TCCR2A - Timer/Counter Control Register A Bit 7 6 5 4 3 2 1 0 COM2A1 COM2A0 COM2B1 COM2B0 - - WGM21 WGM20 Read/Write R/W R/W R/W R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0xB0) TCCR2A * Bits 7:6 - COM2A1:0: Compare Match Output A Mode These bits control the Output Compare pin (OC2A) behavior. If one or both of the COM2A1:0 bits are set, the OC2A output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to the OC2A pin must be set in order to enable the output driver. When OC2A is connected to the pin, the function of the COM2A1:0 bits depends on the WGM22:0 bit setting. Table 17-2 shows the COM2A1:0 bit functionality when the WGM22:0 bits are set to a normal or CTC mode (non-PWM). Table 17-2. Compare Output mode, non-PWM mode COM2A1 COM2A0 Description 0 0 Normal port operation, OC2A disconnected. 0 1 Toggle OC2A on Compare Match 1 0 Clear OC2A on Compare Match 1 1 Set OC2A on Compare Match Table 17-3 shows the COM2A1:0 bit functionality when the WGM21:0 bits are set to fast PWM mode. Table 17-3. Compare Output mode, fast PWM mode (1) COM2A1 COM2A0 0 0 Normal port operation, OC2A disconnected. 0 1 WGM22 = 0: Normal Port Operation, OC0A Disconnected. WGM22 = 1: Toggle OC2A on Compare Match. 1 0 Clear OC2A on Compare Match, set OC2A at BOTTOM, (non-inverting mode). 1 1 Set OC2A on Compare Match, clear OC2A at BOTTOM, (inverting mode). Note: 1. Description A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case, the Compare Match is ignored, but the set or clear is done at BOTTOM. See "Fast PWM mode" on page 152 for more details. Table 17-4 shows the COM2A1:0 bit functionality when the WGM22:0 bits are set to phase correct PWM mode. 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 159 ATmega164A/PA/324A/PA/644A/PA/1284/P Table 17-4. Compare Output mode, phase correct PWM mode (1) COM2A1 COM2A0 0 0 Normal port operation, OC2A disconnected. 0 1 WGM22 = 0: Normal Port Operation, OC2A Disconnected. WGM22 = 1: Toggle OC2A on Compare Match. 1 0 Clear OC2A on Compare Match when up-counting. Set OC2A on Compare Match when down-counting. 1 1 Set OC2A on Compare Match when up-counting. Clear OC2A on Compare Match when down-counting. Note: 1. Description A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case, the Compare Match is ignored, but the set or clear is done at TOP. See "Phase Correct PWM mode" on page 153 for more details. * Bits 5:4 - COM2B1:0: Compare Match Output B Mode These bits control the Output Compare pin (OC2B) behavior. If one or both of the COM2B1:0 bits are set, the OC2B output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to the OC2B pin must be set in order to enable the output driver. When OC2B is connected to the pin, the function of the COM2B1:0 bits depends on the WGM22:0 bit setting. Table 17-5 shows the COM2B1:0 bit functionality when the WGM22:0 bits are set to a normal or CTC mode (non-PWM). Table 17-5. Compare Output mode, non-PWM mode COM2B1 COM2B0 Description 0 0 Normal port operation, OC2B disconnected. 0 1 Toggle OC2B on Compare Match 1 0 Clear OC2B on Compare Match 1 1 Set OC2B on Compare Match Table 17-6 shows the COM2B1:0 bit functionality when the WGM22:0 bits are set to fast PWM mode. Table 17-6. Compare Output mode, fast PWM mode (1) COM2B1 COM2B0 0 0 Normal port operation, OC2B disconnected. 0 1 Reserved 1 0 Clear OC2B on Compare Match, set OC2B at BOTTOM, (non-inverting mode). 1 1 Set OC2B on Compare Match, clear OC2B at BOTTOM, (inverting mode). Note: 1. Description A special case occurs when OCR2B equals TOP and COM2B1 is set. In this case, the Compare Match is ignored, but the set or clear is done at BOTTOM. See "Fast PWM mode" on page 152 for more details. 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 160 ATmega164A/PA/324A/PA/644A/PA/1284/P Table 17-7 shows the COM2B1:0 bit functionality when the WGM22:0 bits are set to phase correct PWM mode. Compare Output mode, phase correct PWM mode (1) Table 17-7. COM2B1 COM2B0 0 0 Normal port operation, OC2B disconnected. 0 1 Reserved 1 0 Clear OC2B on Compare Match when up-counting. Set OC2B on Compare Match when down-counting. 1 1 Set OC2B on Compare Match when up-counting. Clear OC2B on Compare Match when down-counting. Note: 1. Description A special case occurs when OCR2B equals TOP and COM2B1 is set. In this case, the Compare Match is ignored, but the set or clear is done at TOP. See "Phase Correct PWM mode" on page 153 for more details. * Bits 3:2 - Reserved These bits are reserved and will always read as zero. * Bits 1:0 - WGM21:0: Waveform Generation Mode Combined with the WGM22 bit found in the TCCR2B Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used, see Table 17-8. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare Match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes (see "Modes of operation" on page 151). Table 17-8. Waveform Generation mode bit description Timer/Counter Mode of Operation TOP Update of OCRx at TOV Flag Set on(1)(2) Mode WGM2 WGM1 WGM0 0 0 0 0 Normal 0xFF Immediate MAX 1 0 0 1 PWM, Phase Correct 0xFF TOP BOTTOM 2 0 1 0 CTC OCRA Immediate MAX 3 0 1 1 Fast PWM 0xFF BOTTOM MAX 4 1 0 0 Reserved - - - 5 1 0 1 PWM, Phase Correct OCRA TOP BOTTOM 6 1 1 0 Reserved - - - 7 1 1 1 Fast PWM OCRA BOTTOM TOP Notes: 1. 2. MAX= 0xFF BOTTOM= 0x00 17.11.2 TCCR2B - Timer/Counter Control Register B Bit 7 6 5 4 3 2 1 0 FOC2A FOC2B - - WGM22 CS22 CS21 CS20 Read/Write W W R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0xB1) 2018 Microchip Technology Inc. Data Sheet Complete TCCR2B DS40002070A-page 161 ATmega164A/PA/324A/PA/644A/PA/1284/P * Bit 7 - FOC2A: Force Output Compare A The FOC2A bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR2B is written when operating in PWM mode. When writing a logical one to the FOC2A bit, an immediate Compare Match is forced on the Waveform Generation unit. The OC2A output is changed according to its COM2A1:0 bits setting. Note that the FOC2A bit is implemented as a strobe. Therefore it is the value present in the COM2A1:0 bits that determines the effect of the forced compare. A FOC2A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR2A as TOP. The FOC2A bit is always read as zero. * Bit 6 - FOC2B: Force Output Compare B The FOC2B bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR2B is written when operating in PWM mode. When writing a logical one to the FOC2B bit, an immediate Compare Match is forced on the Waveform Generation unit. The OC2B output is changed according to its COM2B1:0 bits setting. Note that the FOC2B bit is implemented as a strobe. Therefore it is the value present in the COM2B1:0 bits that determines the effect of the forced compare. A FOC2B strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR2B as TOP. The FOC2B bit is always read as zero. * Bits 5:4 - Reserved These bits are reserved and will always read as zero. * Bit 3 - WGM22: Waveform Generation Mode See the description in the "TCCR2A - Timer/Counter Control Register A" on page 159. * Bit 2:0 - CS22:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter, see Table 17-9 on page 162. Table 17-9. Clock Select bit description CS22 CS21 CS20 Description 0 0 0 No clock source (Timer/Counter stopped). 0 0 1 clkT2S/(No prescaling) 0 1 0 clkT2S/8 (From prescaler) 0 1 1 clkT2S/32 (From prescaler) 1 0 0 clkT2S/64 (From prescaler) 1 0 1 clkT2S/128 (From prescaler) 1 1 0 clkT2S/256 (From prescaler) 1 1 1 clkT2S/1024 (From prescaler) 17.11.3 TCNT2 - Timer/Counter Register Bit 7 6 5 (0xB2) 4 3 2 1 0 TCNT2[7:0] TCNT2 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 162 ATmega164A/PA/324A/PA/644A/PA/1284/P The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8bit counter. Writing to the TCNT2 Register blocks (removes) the Compare Match on the following timer clock. Modifying the counter (TCNT2) while the counter is running, introduces a risk of missing a Compare Match between TCNT2 and the OCR2x Registers. 17.11.4 OCR2A - Output Compare Register A Bit 7 6 5 4 (0xB3) 3 2 1 0 OCR2A[7:0] OCR2A Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The Output Compare Register A contains an 8-bit value that is continuously compared with the counter value (TCNT2). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC2A pin. 17.11.5 OCR2B - Output Compare Register B Bit 7 6 5 4 (0xB4) 3 2 1 0 OCR2B[7:0] OCR2B Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The Output Compare Register B contains an 8-bit value that is continuously compared with the counter value (TCNT2). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC2B pin. 17.11.6 ASSR - Asynchronous Status Register Bit 7 6 5 4 3 2 1 0 (0xB6) - EXCLK AS2 TCN2UB OCR2AUB OCR2BUB TCR2AUB TCR2BUB Read/Write R R/W R/W R R R R R Initial Value 0 0 0 0 0 0 0 0 ASSR * Bit 6 - EXCLK: Enable External Clock Input When EXCLK is written to one, and asynchronous clock is selected, the external clock input buffer is enabled and an external clock can be input on Timer Oscillator 1 (TOSC1) pin instead of a 32kHz crystal. Writing to EXCLK should be done before asynchronous operation is selected. Note that the crystal Oscillator will only run when this bit is zero. * Bit 5 - AS2: Asynchronous Timer/Counter2 When AS2 is written to zero, Timer/Counter2 is clocked from the I/O clock, clkI/O. When AS2 is written to one, Timer/Counter2 is clocked from a crystal Oscillator connected to the Timer Oscillator 1 (TOSC1) pin. When the value of AS2 is changed, the contents of TCNT2, OCR2A, OCR2B, TCCR2A and TCCR2B might be corrupted. * Bit 4 - TCN2UB: Timer/Counter2 Update Busy When Timer/Counter2 operates asynchronously and TCNT2 is written, this bit becomes set. When TCNT2 has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that TCNT2 is ready to be updated with a new value. * Bit 3 - OCR2AUB: Output Compare Register2 Update Busy When Timer/Counter2 operates asynchronously and OCR2A is written, this bit becomes set. When OCR2A has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that OCR2A is ready to be updated with a new value. 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 163 ATmega164A/PA/324A/PA/644A/PA/1284/P * Bit 2 - OCR2BUB: Output Compare Register2 Update Busy When Timer/Counter2 operates asynchronously and OCR2B is written, this bit becomes set. When OCR2B has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that OCR2B is ready to be updated with a new value. * Bit 1 - TCR2AUB: Timer/Counter Control Register2 Update Busy When Timer/Counter2 operates asynchronously and TCCR2A is written, this bit becomes set. When TCCR2A has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that TCCR2A is ready to be updated with a new value. * Bit 0 - TCR2BUB: Timer/Counter Control Register2 Update Busy When Timer/Counter2 operates asynchronously and TCCR2B is written, this bit becomes set. When TCCR2B has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that TCCR2B is ready to be updated with a new value. If a write is performed to any of the five Timer/Counter2 Registers while its update busy flag is set, the updated value might get corrupted and cause an unintentional interrupt to occur. The mechanisms for reading TCNT2, OCR2A, OCR2B, TCCR2A and TCCR2B are different. When reading TCNT2, the actual timer value is read. When reading OCR2A, OCR2B, TCCR2A and TCCR2B the value in the temporary storage register is read. 17.11.7 TIMSK2 - Timer/Counter2 Interrupt Mask Register Bit 7 6 5 4 3 2 1 0 (0x70) - - - - - OCIE2B OCIE2A TOIE2 Read/Write R R R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TIMSK2 * Bit 2 - OCIE2B: Timer/Counter2 Output Compare Match B Interrupt Enable When the OCIE2B bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Compare Match B interrupt is enabled. The corresponding interrupt is executed if a compare match in Timer/Counter2 occurs, that is, when the OCF2B bit is set in the Timer/Counter 2 Interrupt Flag Register - TIFR2. * Bit 1 - OCIE2A: Timer/Counter2 Output Compare Match A Interrupt Enable When the OCIE2A bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Compare Match A interrupt is enabled. The corresponding interrupt is executed if a compare match in Timer/Counter2 occurs, that is, when the OCF2A bit is set in the Timer/Counter 2 Interrupt Flag Register - TIFR2. * Bit 0 - TOIE2: Timer/Counter2 Overflow Interrupt Enable When the TOIE2 bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter2 occurs, that is, when the TOV2 bit is set in the Timer/Counter2 Interrupt Flag Register - TIFR2. 17.11.8 TIFR2 - Timer/Counter2 Interrupt Flag Register Bit 7 6 5 4 3 2 1 0 0x17 (0x37) - - - - - OCF2B OCF2A TOV2 Read/Write R R R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 2018 Microchip Technology Inc. Data Sheet Complete TIFR2 DS40002070A-page 164 ATmega164A/PA/324A/PA/644A/PA/1284/P * Bit 2 - OCF2B: Output Compare Flag 2 B The OCF2B bit is set (one) when a compare match occurs between the Timer/Counter2 and the data in OCR2B - Output Compare Register2. OCF2B is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF2B is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE2B (Timer/Counter2 Compare match Interrupt Enable), and OCF2B are set (one), the Timer/Counter2 Compare match Interrupt is executed. * Bit 1 - OCF2A: Output Compare Flag 2 A The OCF2A bit is set (one) when a compare match occurs between the Timer/Counter2 and the data in OCR2A - Output Compare Register2. OCF2A is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF2A is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE2A (Timer/Counter2 Compare match Interrupt Enable), and OCF2A are set (one), the Timer/Counter2 Compare match Interrupt is executed. * Bit 0 - TOV2: Timer/Counter2 Overflow Flag The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV2 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE2A (Timer/Counter2 Overflow Interrupt Enable), and TOV2 are set (one), the Timer/Counter2 Overflow interrupt is executed. In PWM mode, this bit is set when Timer/Counter2 changes counting direction at 0x00. 17.11.9 GTCCR - General Timer/Counter Control Register Bit 7 6 5 4 3 2 1 0 0x23 (0x43) TSM - - - - - PSRASY PSRSYNC Read/Write R/W R R R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 GTCCR * Bit 7 - TSM: Timer/Counter Synchronization mode Writing the TSM bit to one, activates the Timer/Counter Synchronization mode. In this mode, the value that is written to the PSRASY and PSRSYNC bits is kept, hence keeping the corresponding prescaler reset signals asserted. This ensures that the corresponding Timer/Counters are halted and can be configured to the same value without the risk of one of them advancing during configuration. When the TSM bit is written to zero, the PSRASY and PSRSYNC bits are cleared by hardware, and the Timer/Counters start counting simultaneously. * Bit 1 - PSRASY: Prescaler Reset Timer/Counter2 When this bit is one, the Timer/Counter2 prescaler will be reset. This bit is normally cleared immediately by hardware. If the bit is written when Timer/Counter2 is operating in asynchronous mode, the bit will remain one until the prescaler has been reset. The bit will not be cleared by hardware if the TSM bit is set. Refer to the description of the "Bit 7 - TSM: Timer/Counter Synchronization Mode" on this page for a description of the Timer/Counter Synchronization mode. * Bit 0 - PSRSYNC: Prescaler Reset When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers. 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 165 ATmega164A/PA/324A/PA/644A/PA/1284/P 18. SPI - Serial Peripheral Interface 18.1 Features * * * * * * * * Overview The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P and peripheral devices or between several AVR devices. USART can also be used in Master SPI mode, see "USART in SPI mode" on page 202. The Power Reduction SPI bit, PRSPI, in "PRR0 - Power Reduction Register 0" on page 56 must be written to zero to enable SPI module. Figure 18-1. SPI block diagram (1) DIVIDER /2/4/8/16/32/64/128 SPI2X SPI2X 18.2 Full-duplex, three-wire synchronous data transfer Master or Slave operation LSB first or MSB first data transfer Seven programmable bit rates End of Transmission Interrupt flag Write Collision flag protection Wake-up from Idle mode Double speed (CK/2) Master SPI mode Note: 1. Refer to Figure 1-1 on page 11, and Table 14-6 on page 88 for SPI pin placement. 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 166 ATmega164A/PA/324A/PA/644A/PA/1284/P The interconnection between Master and Slave CPUs with SPI is shown in Figure 18-2. The system consists of two shift Registers, and a Master clock generator. The SPI Master initiates the communication cycle when pulling low the Slave Select SS pin of the desired Slave. Master and Slave prepare the data to be sent in their respective shift Registers, and the Master generates the required clock pulses on the SCK line to interchange data. Data is always shifted from Master to Slave on the Master Out - Slave In, MOSI, line, and from Slave to Master on the Master In - Slave Out, MISO, line. After each data packet, the Master will synchronize the Slave by pulling high the Slave Select, SS, line. When configured as a Master, the SPI interface has no automatic control of the SS line. This must be handled by user software before communication can start. When this is done, writing a byte to the SPI Data Register starts the SPI clock generator, and the hardware shifts the eight bits into the Slave. After shifting one byte, the SPI clock generator stops, setting the end of Transmission Flag (SPIF). If the SPI Interrupt Enable bit (SPIE) in the SPCR Register is set, an interrupt is requested. The Master may continue to shift the next byte by writing it into SPDR, or signal the end of packet by pulling high the Slave Select, SS line. The last incoming byte will be kept in the Buffer Register for later use. When configured as a Slave, the SPI interface will remain sleeping with MISO tri-stated as long as the SS pin is driven high. In this state, software may update the contents of the SPI Data Register, SPDR, but the data will not be shifted out by incoming clock pulses on the SCK pin until the SS pin is driven low. As one byte has been completely shifted, the end of Transmission Flag, SPIF is set. If the SPI Interrupt Enable bit, SPIE, in the SPCR Register is set, an interrupt is requested. The Slave may continue to place new data to be sent into SPDR before reading the incoming data. The last incoming byte will be kept in the Buffer Register for later use. Figure 18-2. SPI Master-slave interconnection SHIFT ENABLE The system is single buffered in the transmit direction and double buffered in the receive direction. This means that bytes to be transmitted cannot be written to the SPI Data Register before the entire shift cycle is completed. When receiving data, however, a received character must be read from the SPI Data Register before the next character has been completely shifted in. Otherwise, the first byte is lost. In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure correct sampling of the clock signal, the minimum low and high periods should be: Low period: longer than two CPU clock cycles. High period: longer than two CPU clock cycles. When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to Table 18-1. For more details on automatic port overrides, refer to "Alternate Port Functions" on page 85. 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 167 ATmega164A/PA/324A/PA/644A/PA/1284/P Table 18-1. Pin SPI pin overrides (1) Direction, Master SPI Direction, Slave SPI MOSI User Defined Input MISO Input User Defined SCK User Defined Input SS User Defined Input Note: 1. See "Alternate Functions of Port B" on page 88 for a detailed description of how to define the direction of the user defined SPI pins. The following code examples show how to initialize the SPI as a Master and how to perform a simple transmission. DDR_SPI in the examples must be replaced by the actual Data Direction Register controlling the SPI pins. DD_MOSI, DD_MISO and DD_SCK must be replaced by the actual data direction bits for these pins. For example, if MOSI is placed on pin PB5, replace DD_MOSI with DDB5 and DDR_SPI with DDRB. Assembly Code Example (1) SPI_MasterInit: ; Set MOSI and SCK output, all others input ldi r17,(1<>8); UBRRnL = (unsigned char)baud; /* Enable receiver and transmitter */ UCSRnB = (1<> 1) & 0x01; return ((resh << 8) | resl); } Note: 1. See "About code examples" on page 17. The receive function example reads all the I/O Registers into the Register File before any computation is done. This gives an optimal receive buffer utilization since the buffer location read will be free to accept new data as early as possible. 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 186 ATmega164A/PA/324A/PA/644A/PA/1284/P 19.8.3 Receive Compete Flag and Interrupt The USART Receiver has one flag that indicates the Receiver state. The Receive Complete (RXCn) Flag indicates if there are unread data present in the receive buffer. This flag is one when unread data exist in the receive buffer, and zero when the receive buffer is empty (i.e., does not contain any unread data). If the Receiver is disabled (RXENn = 0), the receive buffer will be flushed and consequently the RXCn bit will become zero. When the Receive Complete Interrupt Enable (RXCIEn) in UCSRnB is set, the USART Receive Complete interrupt will be executed as long as the RXCn Flag is set (provided that global interrupts are enabled). When interrupt-driven data reception is used, the receive complete routine must read the received data from UDRn in order to clear the RXCn Flag, otherwise a new interrupt will occur once the interrupt routine terminates. 19.8.4 Receiver Error Flags The USART Receiver has three Error Flags: Frame Error (FEn), Data OverRun (DORn) and Parity Error (UPEn). All can be accessed by reading UCSRnA. Common for the Error Flags is that they are located in the receive buffer together with the frame for which they indicate the error status. Due to the buffering of the Error Flags, the UCSRnA must be read before the receive buffer (UDRn), since reading the UDRn I/O location changes the buffer read location. Another equality for the Error Flags is that they can not be altered by software doing a write to the flag location. However, all flags must be set to zero when the UCSRnA is written for upward compatibility of future USART implementations. None of the Error Flags can generate interrupts. The Frame Error (FEn) Flag indicates the state of the first stop bit of the next readable frame stored in the receive buffer. The FEn Flag is zero when the stop bit was correctly read (as one), and the FEn Flag will be one when the stop bit was incorrect (zero). This flag can be used for detecting out-of-sync conditions, detecting break conditions and protocol handling. The FEn Flag is not affected by the setting of the USBSn bit in UCSRnC since the Receiver ignores all, except for the first, stop bits. For compatibility with future devices, always set this bit to zero when writing to UCSRnA. The Data OverRun (DORn) Flag indicates data loss due to a receiver buffer full condition. A Data OverRun occurs when the receive buffer is full (two characters), it is a new character waiting in the Receive Shift Register, and a new start bit is detected. If the DORn Flag is set there was one or more serial frame lost between the frame last read from UDRn, and the next frame read from UDRn. For compatibility with future devices, always write this bit to zero when writing to UCSRnA. The DORn Flag is cleared when the frame received was successfully moved from the Shift Register to the receive buffer. The Parity Error (UPEn) Flag indicates that the next frame in the receive buffer had a Parity Error when received. If Parity Check is not enabled the UPEn bit will always be read zero. For compatibility with future devices, always set this bit to zero when writing to UCSRnA. For more details see "Parity Bit Calculation" on page 180 and "Parity Checker" on page 187. 19.8.5 Parity Checker The Parity Checker is active when the high USART Parity mode (UPMn1) bit is set. Type of Parity Check to be performed (odd or even) is selected by the UPMn0 bit. When enabled, the Parity Checker calculates the parity of the data bits in incoming frames and compares the result with the parity bit from the serial frame. The result of the check is stored in the receive buffer together with the received data and stop bits. The Parity Error (UPEn) Flag can then be read by software to check if the frame had a Parity Error. The UPEn bit is set if the next character that can be read from the receive buffer had a Parity Error when received and the Parity Checking was enabled at that point (UPMn1 = 1). This bit is valid until the receive buffer (UDRn) is read. 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 187 ATmega164A/PA/324A/PA/644A/PA/1284/P 19.8.6 Disabling the Receiver In contrast to the Transmitter, disabling of the Receiver will be immediate. Data from ongoing receptions will therefore be lost. When disabled (that is, the RXENn is set to zero) the Receiver will no longer override the normal function of the RxDn port pin. The Receiver buffer FIFO will be flushed when the Receiver is disabled. Remaining data in the buffer will be lost 19.8.7 Flushing the Receive Buffer The receiver buffer FIFO will be flushed when the Receiver is disabled, that is, the buffer will be emptied of its contents. Unread data will be lost. If the buffer has to be flushed during normal operation, due to for instance an error condition, read the UDRn I/O location until the RXCn Flag is cleared. The following code example shows how to flush the receive buffer. Assembly Code Example (1) USART_Flush: sbis ret in rjmp UCSRnA, RXCn r16, UDRn USART_Flush C Code Example (1) void USART_Flush( void ) { unsigned char dummy; while ( UCSRnA & (1<2 CPU clock cycles for fck <12MHz, 3 CPU clock cycles for fck 12MHz. High:>2 CPU clock cycles for fck <12MHz, 3 CPU clock cycles for fck 12MHz. 27.8.2 Serial Programming Algorithm When writing serial data to the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P, data is clocked on the rising edge of SCK. When reading data from the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P, data is clocked on the falling edge of SCK. See Figure 27-12 for timing details. To program and verify the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P in the serial programming mode, the following sequence is recommended (see four byte instruction formats in Table 27-17): 1. Power-up sequence: Apply power between VCC and GND while RESET and SCK are set to "0". In some systems, the programmer can not guarantee that SCK is held low during power-up. In this case, RESET must be given a positive pulse of at least two CPU clock cycles duration after SCK has been set to "0". 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 310 ATmega164A/PA/324A/PA/644A/PA/1284/P 2. Wait for at least 20ms and enable serial programming by sending the Programming Enable serial instruction to pin MOSI. 3. The serial programming instructions will not work if the communication is out of synchronization. When in sync. the second byte (0x53), will echo back when issuing the third byte of the Programming Enable instruction. Whether the echo is correct or not, all four bytes of the instruction must be transmitted. If the 0x53 did not echo back, give RESET a positive pulse and issue a new Programming Enable command. 4. The Flash is programmed one page at a time. The memory page is loaded one byte at a time by supplying the seven LSB of the address and data together with the Load Program Memory Page instruction. To ensure correct loading of the page, the data low byte must be loaded before data high byte is applied for a given address. The Program Memory Page is stored by loading the Write Program Memory Page instruction with the address lines 15..8. Before issuing this command, make sure the instruction Load Extended Address Byte has been used to define the MSB of the address. The extended address byte is stored until the command is re-issued, that is, the command needs only be issued for the first page, and when crossing the 64KWord boundary. If polling (RDY/BSY) is not used, the user must wait at least tWD_FLASH before issuing the next page. (See Table 27-16.) Accessing the serial programming interface before the Flash write operation completes can result in incorrect programming. 5. The EEPROM array is programmed one byte at a time by supplying the address and data together with the appropriate Write instruction. An EEPROM memory location is first automatically erased before new data is written. If polling is not used, the user must wait at least tWD_EEPROM before issuing the next byte. (See Table 27-16.) In a chip erased device, no 0xFFs in the data file(s) need to be programmed. 6. Any memory location can be verified by using the Read instruction which returns the content at the selected address at serial output MISO. When reading the Flash memory, use the instruction Load Extended Address Byte to define the upper address byte, which is not included in the Read Program Memory instruction. The extended address byte is stored until the command is re-issued, that is, the command needs only be issued for the first page, and when crossing the 64KWord boundary. 7. At the end of the programming session, RESET can be set high to commence normal operation. 8. Power-off sequence (if needed): Set RESET to "1". Turn VCC power off. Table 27-16. Minimum wait delay before writing the next flash or EEPROM location Symbol Minimum wait delay tWD_FLASH 4.5ms tWD_EEPROM 3.6ms tWD_ERASE 9.0ms 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 311 ATmega164A/PA/324A/PA/644A/PA/1284/P 27.9 Serial Programming Instruction set Table 27-17 and Figure 27-11 on page 313 describes the Instruction set. Table 27-17. Serial programming instruction set (hexadecimal values) Instruction format Instruction/operation Byte 1 Byte 2 Byte 3 Byte 4 Programming Enable $AC $53 $00 $00 Chip Erase (Program Memory/EEPROM) $AC $80 $00 $00 Poll RDY/BSY $F0 $00 $00 data byte out Load Extended Address byte (1) $4D $00 Extended addr $00 Load Program Memory Page, High byte $48 $00 addr LSB high data byte in Load Program Memory Page, Low byte $40 $00 addr LSB Load Instructions Load EEPROM Memory Page (page access) $C1 $00 Read Program Memory, High byte $28 addr MSB addr LSB high data byte out Read Program Memory, Low byte $20 addr MSB addr LSB low data byte out Read Instructions data byte in (5) Read EEPROM Memory Read Lock bits 0000 000aa low data byte in (2) $A0 (3) $58 Read Signature Byte Read Fuse bits (3) Read Fuse High bits (3) Read Extended Fuse Bits (3) Read Calibration Byte 0000 00aa (2) $00 aaaa aaaa (2) $00 data byte out data byte out 0000 000aa (2) $30 $00 data byte out $50 $00 $00 data byte out $58 $08 $00 data byte out $50 $08 $00 data byte out $38 $00 $00 data byte out $4C addr MSB Write Instructions (5) Write Program Memory Page (6) Write EEPROM Memory $C0 0000 00aa (2) 0000 00aa (2) addr LSB $00 aaaa aaaa (2) data byte in aaaa aa00 (2) $00 Write EEPROM Memory Page (page access) $C2 Write Lock bits (3)(4) $AC $E0 $00 data byte in $AC $A0 $00 data byte in $AC $A8 $00 data byte in $AC $A4 $00 data byte in Write Fuse bits (3)(4) Write Fuse High bits (3)(4) Write Extended Fuse Bits (3)(4) Notes: 1. 2. 3. 4. 5. 6. Not all instructions are applicable for all parts. a = address. Bits are programmed `0', unprogrammed `1'. To ensure future compatibility, unused Fuses and Lock bits should be unprogrammed (`1'). Refer to the corresponding section for Fuse and Lock bits, Calibration and Signature bytes and Page size. Instructions accessing program memory use a word address. This address may be random within the page range. Note: See www.microchip.com for Application Notes regarding programming and programmers. If the LSB in RDY/BSY data byte out is `1', a programming operation is still pending. Wait until this bit returns `0' before the next instruction is carried out. 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 312 ATmega164A/PA/324A/PA/644A/PA/1284/P Within the same page, the low data byte must be loaded prior to the high data byte. After data is loaded to the page buffer, program the EEPROM page, see Figure 27-11. Figure 27-11. Serial programming instruction example Serial Programming Instruction Load Program Memory Page (High/Low Byte)/ Load EEPROM Memory Page (page access) Byte 1 Byte 2 Adr A drr MSB MS MSB Bit 15 B Byte 3 Write Program Memory Page/ Write EEPROM Memory Page Byte 1 Byte 4 Byte 2 Adr LSB Adr MSB Bit 15 B 0 Byte 3 Byte 4 Adr A dr LSB LS SB 0 Page Buffer Page Offset Page 0 Page 1 Page 2 Page Number Page N-1 Program Memory/ EEPROM Memory 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 313 ATmega164A/PA/324A/PA/644A/PA/1284/P 27.9.1 Serial Programming Characteristics For characteristics of the Serial Programming module see "SPI timing characteristics" on page 335. Figure 27-12. Serial programming waveforms SERIAL DATA INPUT (MOSI) MSB LSB SERIAL DATA OUTPUT (MISO) MSB LSB SERIAL CLOCK INPUT (SCK) SAMPLE 27.10 Programming via the JTAG Interface Programming through the JTAG interface requires control of the four JTAG specific pins: TCK, TMS, TDI, and TDO. Control of the reset and clock pins is not required. To be able to use the JTAG interface, the JTAGEN Fuse must be programmed. The device is default shipped with the fuse programmed. In addition, the JTD bit in MCUCR must be cleared. Alternatively, if the JTD bit is set, the external reset can be forced low. Then, the JTD bit will be cleared after two chip clocks, and the JTAG pins are available for programming. This provides a means of using the JTAG pins as normal port pins in Running mode while still allowing In-System Programming via the JTAG interface. Note that this technique can not be used when using the JTAG pins for Boundary-scan or On-chip Debug. In these cases the JTAG pins must be dedicated for this purpose. During programming the clock frequency of the TCK Input must be less than the maximum frequency of the chip. The System Clock Prescaler can not be used to divide the TCK Clock Input into a sufficiently low frequency. As a definition in this datasheet, the LSB is shifted in and out first of all Shift Registers. 27.10.1 Programming Specific JTAG Instructions The Instruction Register is 4-bit wide, supporting up to 16 instructions. The JTAG instructions useful for programming are listed below. The OPCODE for each instruction is shown behind the instruction name in hex format. The text describes which Data Register is selected as path between TDI and TDO for each instruction. The Run-Test/Idle state of the TAP controller is used to generate internal clocks. It can also be used as an idle state between JTAG sequences. The state machine sequence for changing the instruction word is shown in Figure 27-13 on page 315. 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 314 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 27-13. State machine sequence for changing the instruction word 1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 1 Select-IR Scan 0 1 0 1 Capture-DR Capture-IR 0 0 0 Shift-DR 1 1 Exit1-DR 1 Exit1-IR 0 0 0 Pause-DR 0 Pause-IR 1 1 0 Exit2-DR Exit2-IR 1 1 Update-DR 1 0 Shift-IR 1 0 1 Update-IR 0 1 0 27.10.2 AVR_RESET (0xC) The AVR specific public JTAG instruction for setting the AVR device in the Reset mode or taking the device out from the Reset mode. The TAP controller is not reset by this instruction. The one bit Reset Register is selected as Data Register. Note that the reset will be active as long as there is a logic "one" in the Reset Chain. The output from this chain is not latched. The active states are: Shift-DR: The Reset Register is shifted by the TCK input 27.10.3 PROG_ENABLE (0x4) The AVR specific public JTAG instruction for enabling programming via the JTAG port. The 16-bit Programming Enable Register is selected as Data Register. The active states are the following: Shift-DR: The programming enable signature is shifted into the Data Register Update-DR: The programming enable signature is compared to the correct value, and Programming mode is entered if the signature is valid 27.10.4 PROG_COMMANDS (0x5) The AVR specific public JTAG instruction for entering programming commands via the JTAG port. The 15-bit Programming Command Register is selected as Data Register. The active states are the following: 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 315 ATmega164A/PA/324A/PA/644A/PA/1284/P Capture-DR: The result of the previous command is loaded into the Data Register Shift-DR: The Data Register is shifted by the TCK input, shifting out the result of the previous command and shifting in the new command Update-DR: The programming command is applied to the Flash inputs Run-Test/Idle: One clock cycle is generated, executing the applied command 27.10.5 PROG_PAGELOAD (0x6) The AVR specific public JTAG instruction to directly load the Flash data page via the JTAG port. An 8-bit Flash Data Byte Register is selected as the Data Register. This is physically the eight LSBs of the Programming Command Register. The active states are the following: Shift-DR: The Flash Data Byte Register is shifted by the TCK input Update-DR: The content of the Flash Data Byte Register is copied into a temporary register. A write sequence is initiated that within 11 TCK cycles loads the content of the temporary register into the Flash page buffer. The AVR automatically alternates between writing the low and the high byte for each new Update-DR state, starting with the low byte for the first Update-DR encountered after entering the PROG_PAGELOAD command. The Program Counter is pre-incremented before writing the low byte, except for the first written byte. This ensures that the first data is written to the address set up by PROG_COMMANDS, and loading the last location in the page buffer does not make the program counter increment into the next page 27.10.6 PROG_PAGEREAD (0x7) The AVR specific public JTAG instruction to directly capture the Flash content via the JTAG port. An 8-bit Flash Data Byte Register is selected as the Data Register. This is physically the eight LSBs of the Programming Command Register. The active states are the following: Capture-DR: The content of the selected Flash byte is captured into the Flash Data Byte Register. The AVR automatically alternates between reading the low and the high byte for each new Capture-DR state, starting with the low byte for the first Capture-DR encountered after entering the PROG_PAGEREAD command. The Program Counter is post-incremented after reading each high byte, including the first read byte. This ensures that the first data is captured from the first address set up by PROG_COMMANDS, and reading the last location in the page makes the program counter increment into the next page Shift-DR: The Flash Data Byte Register is shifted by the TCK input 27.10.7 Data Registers The Data Registers are selected by the JTAG instruction registers described in section "Programming Specific JTAG Instructions" on page 314. The Data Registers relevant for programming operations are: Reset Register Programming Enable Register Programming Command Register Flash Data Byte Register 27.10.8 Reset Register The Reset Register is a Test Data Register used to reset the part during programming. It is required to reset the part before entering Programming mode. A high value in the Reset Register corresponds to pulling the external reset low. The part is reset as long as there is a high value present in the Reset Register. Depending on the Fuse settings for the clock options, the part will remain reset for a Reset Time-out period (refer to "Clock Sources" on page 39) after releasing the Reset 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 316 ATmega164A/PA/324A/PA/644A/PA/1284/P Register. The output from this Data Register is not latched, so the reset will take place immediately, as shown in Figure 25-2 on page 270. 27.10.9 Programming Enable Register The Programming Enable Register is a 16-bit register. The contents of this register is compared to the programming enable signature, binary code 0b1010_0011_0111_0000. When the contents of the register is equal to the programming enable signature, programming via the JTAG port is enabled. The register is reset to 0 on Power-on Reset, and should always be reset when leaving Programming mode. Figure 27-14. Programming enable register TDI D A T A 0xA370 = D Q Programming Enable ClockDR & PROG_ENABLE TDO 27.10.10Programming Command Register The Programming Command Register is a 15-bit register. This register is used to serially shift in programming commands, and to serially shift out the result of the previous command, if any. The JTAG Programming Instruction Set is shown in Table 27-18 on page 318. The state sequence when shifting in the programming commands is illustrated in Figure 27-16 on page 321. Figure 27-15. Programming command register TDI S T R O B E S A D D R E S S / D A T A Flash EEPROM Fuses Lock Bits TDO 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 317 ATmega164A/PA/324A/PA/644A/PA/1284/P Table 27-18. JTAG programming instruction. Set a = address high bits, b = address low bits, c = address extended bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don't care Instruction TDI sequence TDO sequence 0100011_10000000 xxxxxxx_xxxxxxxx 0110001_10000000 xxxxxxx_xxxxxxxx 0110011_10000000 xxxxxxx_xxxxxxxx 0110011_10000000 xxxxxxx_xxxxxxxx 1b. Poll for Chip Erase Complete 0110011_10000000 xxxxxox_xxxxxxxx 2a. Enter Flash Write 0100011_00010000 xxxxxxx_xxxxxxxx 2b. Load Address Extended High Byte 0001011_cccccccc xxxxxxx_xxxxxxxx 2c. Load Address High Byte 0000111_aaaaaaaa xxxxxxx_xxxxxxxx 2d. Load Address Low Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx 2e. Load Data Low Byte 0010011_iiiiiiii xxxxxxx_xxxxxxxx 2f. Load Data High Byte 0010111_iiiiiiii xxxxxxx_xxxxxxxx 0110111_00000000 xxxxxxx_xxxxxxxx 1110111_00000000 xxxxxxx_xxxxxxxx 0110111_00000000 xxxxxxx_xxxxxxxx 0110111_00000000 xxxxxxx_xxxxxxxx 0110101_00000000 xxxxxxx_xxxxxxxx 0110111_00000000 xxxxxxx_xxxxxxxx 0110111_00000000 xxxxxxx_xxxxxxxx 2i. Poll for Page Write Complete 0110111_00000000 xxxxxox_xxxxxxxx 3a. Enter Flash Read 0100011_00000010 xxxxxxx_xxxxxxxx 3b. Load Address Extended High Byte 0001011_cccccccc xxxxxxx_xxxxxxxx 3c. Load Address High Byte 0000111_aaaaaaaa xxxxxxx_xxxxxxxx 3d. Load Address Low Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx 0110010_00000000 xxxxxxx_xxxxxxxx 0110110_00000000 xxxxxxx_oooooooo Low byte 0110111_00000000 xxxxxxx_oooooooo High byte 4a. Enter EEPROM Write 0100011_00010001 xxxxxxx_xxxxxxxx 4b. Load Address High Byte 0000111_aaaaaaaa xxxxxxx_xxxxxxxx 4c. Load Address Low Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx 4d. Load Data Byte 0010011_iiiiiiii xxxxxxx_xxxxxxxx 0110111_00000000 xxxxxxx_xxxxxxxx 1110111_00000000 xxxxxxx_xxxxxxxx 0110111_00000000 xxxxxxx_xxxxxxxx 1a. Chip Erase 2g. Latch Data 2h. Write Flash Page 3e. Read Data Low and High Byte 4e. Latch Data 2018 Microchip Technology Inc. Data Sheet Complete Notes (2) (10) (1) (1) (2) (10) (10) (1) DS40002070A-page 318 ATmega164A/PA/324A/PA/644A/PA/1284/P Table 27-18. JTAG programming instruction. (Continued) Set (Continued) a = address high bits, b = address low bits, c = address extended bits, H = 0 - Low byte, 1 High Byte, o = data out, i = data in, x = don't care Instruction TDI sequence TDO sequence 0110011_00000000 xxxxxxx_xxxxxxxx 0110001_00000000 xxxxxxx_xxxxxxxx 0110011_00000000 xxxxxxx_xxxxxxxx 0110011_00000000 xxxxxxx_xxxxxxxx 4g. Poll for Page Write Complete 0110011_00000000 xxxxxox_xxxxxxxx 5a. Enter EEPROM Read 0100011_00000011 xxxxxxx_xxxxxxxx 5b. Load Address High Byte 0000111_aaaaaaaa xxxxxxx_xxxxxxxx 5c. Load Address Low Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx 0110011_bbbbbbbb xxxxxxx_xxxxxxxx 0110010_00000000 xxxxxxx_xxxxxxxx 0110011_00000000 xxxxxxx_oooooooo 0100011_01000000 xxxxxxx_xxxxxxxx 0010011_iiiiiiii xxxxxxx_xxxxxxxx 0111011_00000000 xxxxxxx_xxxxxxxx 0111001_00000000 xxxxxxx_xxxxxxxx 0111011_00000000 xxxxxxx_xxxxxxxx 0111011_00000000 xxxxxxx_xxxxxxxx 0111011_00000000 xxxxxox_xxxxxxxx (2) 0010011_iiiiiiii xxxxxxx_xxxxxxxx (3) 0110111_00000000 xxxxxxx_xxxxxxxx 0110101_00000000 xxxxxxx_xxxxxxxx 0110111_00000000 xxxxxxx_xxxxxxxx 0110111_00000000 xxxxxxx_xxxxxxxx 0110111_00000000 xxxxxox_xxxxxxxx (2) 0010011_iiiiiiii xxxxxxx_xxxxxxxx (3) 0110011_00000000 xxxxxxx_xxxxxxxx 0110001_00000000 xxxxxxx_xxxxxxxx 0110011_00000000 xxxxxxx_xxxxxxxx 0110011_00000000 xxxxxxx_xxxxxxxx 6j. Poll for Fuse Write Complete 0110011_00000000 xxxxxox_xxxxxxxx 7a. Enter Lock Bit Write 0100011_00100000 xxxxxxx_xxxxxxxx 0010011_11iiiiii xxxxxxx_xxxxxxxx 0110011_00000000 xxxxxxx_xxxxxxxx 0110001_00000000 xxxxxxx_xxxxxxxx 0110011_00000000 xxxxxxx_xxxxxxxx 0110011_00000000 xxxxxxx_xxxxxxxx 0110011_00000000 xxxxxox_xxxxxxxx 4f. Write EEPROM Page 5d. Read Data Byte 6a. Enter Fuse Write 6b. Load Data Low Byte (6) 6c. Write Fuse Extended Byte 6d. Poll for Fuse Write Complete 6e. Load Data Low Byte (7) 6f. Write Fuse High Byte 6g. Poll for Fuse Write Complete 6h. Load Data Low Byte (7) 6i. Write Fuse Low Byte 7b. Load Data Byte (9) 7c. Write Lock Bits 7d. Poll for Lock Bit Write complete 2018 Microchip Technology Inc. Data Sheet Complete Notes (1) (2) (10) (3) (1) (1) (1) (2) (4) (1) (2) DS40002070A-page 319 ATmega164A/PA/324A/PA/644A/PA/1284/P Table 27-18. JTAG programming instruction. (Continued) Set (Continued) a = address high bits, b = address low bits, c = address extended bits, H = 0 - Low byte, 1 High Byte, o = data out, i = data in, x = don't care Instruction TDI sequence TDO sequence 8a. Enter Fuse/Lock Bit Read 0100011_00000100 xxxxxxx_xxxxxxxx 0111010_00000000 xxxxxxx_xxxxxxxx 0111011_00000000 xxxxxxx_oooooooo 0111110_00000000 xxxxxxx_xxxxxxxx 0111111_00000000 xxxxxxx_oooooooo 0110010_00000000 xxxxxxx_xxxxxxxx 0110011_00000000 xxxxxxx_oooooooo 0110110_00000000 xxxxxxx_xxxxxxxx 0110111_00000000 xxxxxxx_xxoooooo 0111010_00000000 xxxxxxx_xxxxxxxx (5) 0111110_00000000 xxxxxxx_oooooooo Fuse Ext. byte 0110010_00000000 xxxxxxx_oooooooo Fuse High byte 0110110_00000000 xxxxxxx_oooooooo Fuse Low byte 0110111_00000000 xxxxxxx_oooooooo Lock bits 9a. Enter Signature Byte Read 0100011_00001000 xxxxxxx_xxxxxxxx 9b. Load Address Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx 0110010_00000000 xxxxxxx_xxxxxxxx 0110011_00000000 xxxxxxx_oooooooo 10a. Enter Calibration Byte Read 0100011_00001000 xxxxxxx_xxxxxxxx 10b. Load Address Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx 0110110_00000000 xxxxxxx_xxxxxxxx 0110111_00000000 xxxxxxx_oooooooo 0100011_00000000 xxxxxxx_xxxxxxxx 0110011_00000000 xxxxxxx_xxxxxxxx 8b. Read Extended Fuse Byte (6) 8c. Read Fuse High Byte (7) 8d. Read Fuse Low Byte (8) 8e. Read Lock Bits (9) 8f. Read Fuses and Lock Bits 9c. Read Signature Byte 10c. Read Calibration Byte 11a. Load No Operation Command Notes: Notes (5) 1. This command sequence is not required if the seven MSB are correctly set by the previous command sequence (which is normally the case). 2. Repeat until o = "1". 3. Set bits to "0" to program the corresponding Fuse, "1" to unprogram the Fuse. 4. Set bits to "0" to program the corresponding Lock bit, "1" to leave the Lock bit unchanged. 5. "0" = programmed, "1" = unprogrammed. 6. The bit mapping for Fuses Extended byte is listed in Table 27-3 on page 296. 7. The bit mapping for Fuses High byte is listed in Table 27-4 on page 297. 8. The bit mapping for Fuses Low byte is listed in Table 27-5 on page 297. 9. The bit mapping for Lock bits byte is listed in Table 27-1 on page 295. 10. Address bits exceeding PCMSB and EEAMSB (Table 27-7 and Table 27-8) are don't care. 11. All TDI and TDO sequences are represented by binary digits (0b...). 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 320 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 27-16. State machine sequence for changing/reading the data word 1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 1 Select-IR Scan 0 1 0 1 Capture-DR Capture-IR 0 0 Shift-DR Shift-IR 0 1 Exit1-DR 1 Exit1-IR 0 0 Pause-DR 0 0 Pause-IR 1 1 0 Exit2-DR Exit2-IR 1 1 Update-DR 1 0 1 1 0 1 Update-IR 0 1 0 27.10.11Flash Data Byte Register The Flash Data Byte Register provides an efficient way to load the entire Flash page buffer before executing Page Write, or to read out/verify the content of the Flash. A state machine sets up the control signals to the Flash and senses the strobe signals from the Flash, thus only the data words need to be shifted in/out. The Flash Data Byte Register actually consists of the 8-bit scan chain and a 8-bit temporary register. During page load, the Update-DR state copies the content of the scan chain over to the temporary register and initiates a write sequence that within 11 TCK cycles loads the content of the temporary register into the Flash page buffer. The AVR automatically alternates between writing the low and the high byte for each new Update-DR state, starting with the low byte for the first Update-DR encountered after entering the PROG_PAGELOAD command. The Program Counter is pre-incremented before writing the low byte, except for the first written byte. This ensures that the first data is written to the address set up by PROG_COMMANDS, and loading the last location in the page buffer does not make the Program Counter increment into the next page. During Page Read, the content of the selected Flash byte is captured into the Flash Data Byte Register during the Capture-DR state. The AVR automatically alternates between reading the low and the high byte for each new Capture-DR state, starting with the low byte for the first Capture-DR encountered after entering the PROG_PAGEREAD command. The Program Counter is post-incremented after reading each high byte, including the first read byte. This ensures that the first data is captured from the first address set up by PROG_COMMANDS, and reading the last location in the page makes the program counter increment into the next page. 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 321 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 27-17. Flash data byte register STROBES TDI State Machine ADDRESS Flash EEPROM Fuses Lock Bits D A T A TDO The state machine controlling the Flash Data Byte Register is clocked by TCK. During normal operation in which eight bits are shifted for each Flash byte, the clock cycles needed to navigate through the TAP controller automatically feeds the state machine for the Flash Data Byte Register with sufficient number of clock pulses to complete its operation transparently for the user. However, if too few bits are shifted between each Update-DR state during page load, the TAP controller should stay in the Run-Test/Idle state for some TCK cycles to ensure that there are at least 11 TCK cycles between each Update-DR state. 27.10.12Programming Algorithm All references below of type "1a", "1b", and so on, refer to Table 27-18 on page 318. 27.10.13Entering Programming Mode 1. Enter JTAG instruction AVR_RESET and shift 1 in the Reset Register. 2. Enter instruction PROG_ENABLE and shift 0b1010_0011_0111_0000 in the Programming Enable Register. 27.10.14Leaving Programming Mode 1. Enter JTAG instruction PROG_COMMANDS. 2. Disable all programming instructions by using no operation instruction 11a. 3. Enter instruction PROG_ENABLE and shift 0b0000_0000_0000_0000 in the programming Enable Register. 4. Enter JTAG instruction AVR_RESET and shift 0 in the Reset Register. 27.10.15Performing Chip Erase 1. Enter JTAG instruction PROG_COMMANDS. 2. Start Chip Erase using programming instruction 1a. 3. Poll for Chip Erase complete using programming instruction 1b, or wait for tWLRH_CE (refer to Table 27-14 on page 308). 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 322 ATmega164A/PA/324A/PA/644A/PA/1284/P 27.10.16Programming the Flash Before programming the Flash a Chip Erase must be performed, see "Performing Chip Erase" on page 322. 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Flash write using programming instruction 2a. 3. Load address Extended High byte using programming instruction 2b. 4. Load address High byte using programming instruction 2c. 5. Load address Low byte using programming instruction 2d. 6. Load data using programming instructions 2e, 2f, and 2g. 7. Repeat steps 5 and 6 for all instruction words in the page. 8. Write the page using programming instruction 2h. 9. Poll for Flash write complete using programming instruction 2i, or wait for tWLRH (refer to Table 27-14 on page 308). 10. Repeat steps 3 to 9 until all data have been programmed. A more efficient data transfer can be achieved using the PROG_PAGELOAD instruction: 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Flash write using programming instruction 2a. 3. Load the page address using programming instructions 2b, 2c, and 2d. PCWORD (refer to Table 27-7 on page 298) is used to address within one page and must be written as 0. 4. Enter JTAG instruction PROG_PAGELOAD. 5. Load the entire page by shifting in all instruction words in the page byte-by-byte, starting with the LSB of the first instruction in the page and ending with the MSB of the last instruction in the page. Use UpdateDR to copy the contents of the Flash Data Byte Register into the Flash page location and to autoincrement the Program Counter before each new word. 6. Enter JTAG instruction PROG_COMMANDS. 7. Write the page using programming instruction 2h. 8. Poll for Flash write complete using programming instruction 2i, or wait for tWLRH (refer to Table 27-14 on page 308). 9. Repeat steps 3 to 8 until all data have been programmed. 27.10.17Reading the Flash 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Flash read using programming instruction 3a. 3. Load address using programming instructions 3b, 3c, and 3d. 4. Read data using programming instruction 3e. 5. Repeat steps 3 and 4 until all data have been read. A more efficient data transfer can be achieved using the PROG_PAGEREAD instruction: 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Flash read using programming instruction 3a. 3. Load the page address using programming instructions 3b, 3c, and 3d. PCWORD (refer to Table 27-7 on page 298) is used to address within one page and must be written as 0. 4. Enter JTAG instruction PROG_PAGEREAD. 5. Read the entire page (or Flash) by shifting out all instruction words in the page (or Flash), starting with the LSB of the first instruction in the page (Flash) and ending with the MSB of the last instruction in the page (Flash). The Capture-DR state both captures the data from the Flash, and also auto-increments the 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 323 ATmega164A/PA/324A/PA/644A/PA/1284/P program counter after each word is read. Note that Capture-DR comes before the shift-DR state. Hence, the first byte which is shifted out contains valid data. 6. Enter JTAG instruction PROG_COMMANDS. 7. Repeat steps 3 to 6 until all data have been read. 27.10.18Programming the EEPROM Before programming the EEPROM a Chip Erase must be performed, See "Performing Chip Erase" on page 322. 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable EEPROM write using programming instruction 4a. 3. Load address High byte using programming instruction 4b. 4. Load address Low byte using programming instruction 4c. 5. Load data using programming instructions 4d and 4e. 6. Repeat steps 4 and 5 for all data bytes in the page. 7. Write the data using programming instruction 4f. 8. Poll for EEPROM write complete using programming instruction 4g, or wait for tWLRH (refer to Table 27-14 on page 308). 9. Repeat steps 3 to 8 until all data have been programmed. Note that the PROG_PAGELOAD instruction can not be used when programming the EEPROM. 27.10.19Reading the EEPROM 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable EEPROM read using programming instruction 5a. 3. Load address using programming instructions 5b and 5c. 4. Read data using programming instruction 5d. 5. Repeat steps 3 and 4 until all data have been read. Note that the PROG_PAGEREAD instruction can not be used when reading the EEPROM. 27.10.20Programming the Fuses 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Fuse write using programming instruction 6a. 3. Load data high byte using programming instructions 6b. A bit value of "0" will program the corresponding fuse, a "1" will unprogram the fuse. 4. Write Fuse High byte using programming instruction 6c. 5. Poll for Fuse write complete using programming instruction 6d, or wait for tWLRH (refer to Table 27-14 on page 308). 6. Load data low byte using programming instructions 6e. A "0" will program the fuse, a "1" will unprogram the fuse. 7. Write Fuse low byte using programming instruction 6f. 8. Poll for Fuse write complete using programming instruction 6g, or wait for tWLRH (refer to Table 27-14 on page 308). 27.10.21Programming the Lock Bits 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Lock bit write using programming instruction 7a. 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 324 ATmega164A/PA/324A/PA/644A/PA/1284/P 3. Load data using programming instructions 7b. A bit value of "0" will program the corresponding lock bit, a "1" will leave the lock bit unchanged. 4. Write Lock bits using programming instruction 7c. 5. Poll for Lock bit write complete using programming instruction 7d, or wait for tWLRH (refer to Table 27-14 on page 308). 27.10.22Reading the Fuses and Lock Bits 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Fuse/Lock bit read using programming instruction 8a. 3. To read all Fuses and Lock bits, use programming instruction 8e. To only read Fuse High byte, use programming instruction 8b. To only read Fuse Low byte, use programming instruction 8c. To only read Lock bits, use programming instruction 8d. 27.10.23Reading the Signature Bytes 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Signature byte read using programming instruction 9a. 3. Load address 0x00 using programming instruction 9b. 4. Read first signature byte using programming instruction 9c. 5. Repeat steps 3 and 4 with address 0x01 and address 0x02 to read the second and third signature bytes, respectively. 27.10.24Reading the Calibration Byte 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Calibration byte read using programming instruction 10a. 3. Load address 0x00 using programming instruction 10b. 4. Read the calibration byte using programming instruction 10c. 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 325 ATmega164A/PA/324A/PA/644A/PA/1284/P 28. Electrical characteristics (TA = -40C to 85C) Absolute maximum ratings* *NOTICE: Operating temperature ................................... -55C to +125C Storage temperature ...................................... -65C to +150C Voltage on any pin except RESET with respect to ground................................-0.5V to VCC + 0.5V Voltage on RESET with respect to ground...... -0.5V to +13.0V Maximum operating voltage .............................................. 6.0V Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC current per I/O pin .................................................. 40.0mA DC current VCC and GND pins .................................. 200.0mA 28.1 DC Characteristics Table 28-1. TA = -40C to 85C, VCC = 1.8V to 5.5V (unless otherwise noted) Symbol Parameter Condition Min. VIL Input Low Voltage, Except XTAL1 and Reset pin VCC = 1.8V - 2.4V VCC = 2.4V - 5.5V -0.5 -0.5 0.2VCC(1) 0.3VCC(1) VIL1 Input Low Voltage, XTAL1 pin VCC = 1.8V - 5.5V -0.5 0.1VCC(1) VIL2 Input Low Voltage, RESET pin VCC = 1.8V - 5.5V -0.5 0.1VCC(1) VIH Input High Voltage, Except XTAL1 and RESET pins VCC = 1.8V - 2.4V VCC = 2.4V - 5.5V 0.7VCC(2) 0.6VCC(2) VCC + 0.5 VCC + 0.5 VIH1 Input High Voltage, XTAL1 pin VCC = 1.8V - 2.4V VCC = 2.4V - 5.5V 0.8VCC(2) 0.7VCC(2) VCC + 0.5 VCC + 0.5 VIH2 Input High Voltage, RESET pin VCC = 1.8V - 5.5V 0.9VCC(2) VCC + 0.5 VOL Output Low Voltage(3) IOL = 20mA, VCC = 5V IOL = 10mA, VCC = 3V VOH Output High Voltage(4) IOH = -20mA, VCC = 5V IOH = -10mA, VCC = 3V IIL Input Leakage Current I/O Pin VCC = 5.5V, pin low (absolute value) 1 IIH Input Leakage Current I/O Pin VCC = 5.5V, pin high (absolute value) 1 RRST Reset Pull-up Resistor 30 60 RPU I/O Pin Pull-up Resistor 20 50 2018 Microchip Technology Inc. Typ. Max. Units V 0.9 0.6 4.2 2.3 A Data Sheet Complete k DS40002070A-page 326 ATmega164A/PA/324A/PA/644A/PA/1284/P Table 28-1. TA = -40C to 85C, VCC = 1.8V to 5.5V (unless otherwise noted) Symbol Parameter Condition VACIO Analog Comparator Input Offset Voltage VCC = 5V IACLK Analog Comparator Input Leakage Current VCC = 5V Vin = VCC/2 tACID Analog Comparator Propagation Delay VCC = 2.7V VCC = 4.0V Notes: Min. Vin = VCC/2 Typ. Max. Units <10 40 mV 50 nA -50 750 500 ns 1. "Max." means the highest value where the pin is ensured to be read as low. 2. "Min." means the lowest value where the pin is ensured to be read as high. 3. Although each I/O port can sink more than the test conditions (20mA at VCC = 5V, 10mA at VCC = 3V) under steady state conditions (non-transient), the following must be observed: 1.)The sum of all IOL, for ports PB0-PB7, XTAL2, PD0-PD7 should not exceed 100mA. 2.)The sum of all IOH, for ports PA0-PA3, PC0-PC7 should not exceed 100mA. If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test condition. 4. Although each I/O port can source more than the test conditions (20mA at VCC = 5V, 10mA at VCC = 3V) under steady state conditions (non-transient), the following must be observed: 1.)The sum of all IOL, for ports PB0-PB7, XTAL2, PD0-PD7 should not exceed 100mA. 2.)The sum of all IOH, for ports PA0-PA3, PC0-PC7 should not exceed 100mA. If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current greater than the listed test condition. 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 327 ATmega164A/PA/324A/PA/644A/PA/1284/P 28.1.1 ATmega164A DC characteristics Table 28-2. Symbol TA = -40C to 85C, VCC = 1.8V to 5.5V (unless otherwise noted) Parameter Power Supply Current (1) ICC Power-save mode (3) Power-down mode (3) Notes: Typ.(2) Max. Active 1MHz, VCC = 2V 0.3 0.55 Active 4MHz, VCC = 3V 1.4 3.5 Active 8MHz, VCC = 5V 4.8 12 Idle 1MHz, VCC = 2V 0.07 0.5 Idle 4MHz, VCC = 3V 0.25 1.5 Idle 8MHz, VCC = 5V 1.0 5.5 32kHz TOSC enabled, VCC = 1.8V 0.5 32kHz TOSC enabled, VCC = 3V 0.6 WDT enabled, VCC = 3V 5.0 15 WDT disabled, VCC = 3V 0.17 3.0 Typ. (2) Max. Active 1MHz, VCC = 2V 0.3 0.5 Active 4MHz, VCC = 3V 1.4 2.7 Active 8MHz, VCC = 5V 4.8 9.0 Idle 1MHz, VCC = 2V 0.07 0.15 Idle 4MHz, VCC = 3V 0.25 0.7 Idle 8MHz, VCC = 5V) 1.0 5.0 32kHz TOSC enabled, VCC = 1.8V 0.5 32kHz TOSC enabled, VCC = 3V 0.6 WDT enabled, VCC = 3V 5.0 8.0 WDT disabled, VCC = 3V 0.17 2.0 Condition Min. Units mA A 1. All bits set in the "PRR0 - Power Reduction Register 0" on page 56. 2. Typical values at 25C. Maximum values are test limits in production. 3. The current consumption values include input leakage current. 28.1.2 ATmega164PA DC characteristics Table 28-3. Symbol TA = -40C to 85C, VCC = 1.8V to 5.5V (unless otherwise noted) Parameter Condition Power Supply Current (1) ICC Power-save mode (3) Power-down mode (3) Notes: Min. Units mA A 1. All bits set in the "PRR0 - Power Reduction Register 0" on page 56. 2. Typical values at 25C. Maximum values are test limits in production. 3. The current consumption values include input leakage current. 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 328 ATmega164A/PA/324A/PA/644A/PA/1284/P 28.1.3 ATmega324A DC characteristics Table 28-4. Symbol TA = -40C to 85C, VCC = 1.8V to 5.5V (unless otherwise noted) Parameter Power Supply Current (1) ICC Power-save mode (3) Power-down mode (3) Notes: Typ. (2) Max. Active 1MHz, VCC = 2V 0.3 0.55 Active 4MHz, VCC = 3V 1.5 3.5 Active 8MHz, VCC = 5V 5.2 12 Idle 1MHz, VCC = 2V 0.06 0.5 Idle 4MHz, VCC = 3V 0.35 1.5 Idle 8MHz, VCC = 5V 1.3 5.5 32kHz TOSC enabled, VCC = 1.8V 0.5 32kHz TOSC enabled, VCC = 3V 0.6 WDT enabled, VCC = 3V 4.2 15 WDT disabled, VCC = 3V 0.15 3.0 Typ. (2) Max. Active 1MHz, VCC = 2V 0.3 0.5 Active 4MHz, VCC = 3V 1.5 2.7 Active 8MHz, VCC = 5V 5.2 9 Idle 1MHz, VCC = 2V 0.06 0.15 Idle 4MHz, VCC = 3V 0.35 0.7 Idle 8MHz, VCC = 5V 1.3 5.0 32kHz TOSC enabled, VCC = 1.8V 0.5 32kHz TOSC enabled, VCC = 3V 0.6 WDT enabled, VCC = 3V 4.2 8.0 WDT disabled, VCC = 3V 0.15 2.0 Condition Min. Units mA A 1. All bits set in the "PRR0 - Power Reduction Register 0" on page 56. 2. Typical values at 25C. Maximum values are test limits in production. 3. The current consumption values include input leakage current. 28.1.4 ATmega324PA DC characteristics Table 28-5. Symbol TA = -40C to 85C, VCC = 1.8V to 5.5V (unless otherwise noted) Parameter Condition Power Supply Current (1) ICC Power-save mode (3) Power-down mode (3) Notes: Min. Units mA A 1. All bits set in the "PRR0 - Power Reduction Register 0" on page 56. 2. Typical values at 25C. Maximum values are test limits in production. 3. The current consumption values include input leakage current. 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 329 ATmega164A/PA/324A/PA/644A/PA/1284/P 28.1.5 ATmega644A DC characteristics Table 28-6. Symbol TA = -40C to 85C, VCC = 1.8V to 5.5V (unless otherwise noted) Parameter Power Supply Current (1) ICC Power-save mode (3) Power-down mode (3) Notes: Typ. (2) Max. Active 1MHz, VCC = 2V 0.38 0.5 Active 4MHz, VCC = 3V 1.8 2.7 Active 8MHz, VCC = 5V 5.6 9.0 Idle 1MHz, VCC = 2V 0.06 0.15 Idle 4MHz, VCC = 3V 0.2 0.7 Idle 8MHz, VCC = 5V 1.1 2.5 32kHz TOSC enabled, VCC = 1.8V 0.5 32kHz TOSC enabled, VCC = 3V 0.6 WDT enabled, VCC = 3V 4.2 20 WDT disabled, VCC = 3V 0.15 3.0 Typ. (2) Max. Active 1MHz, VCC = 2V 0.38 0.5 Active 4MHz, VCC = 3V 1.8 2.7 Active 8MHz, VCC = 5V 5.6 9.0 Idle 1MHz, VCC = 2V 0.06 0.15 Idle 4MHz, VCC = 3V 0.2 0.7 Idle 8MHz, VCC = 5V 1.1 4.0 32kHz TOSC enabled, VCC = 1.8V 0.5 32kHz TOSC enabled, VCC = 3V 0.6 WDT enabled, VCC = 3V 4.2 8.0 WDT disabled, VCC = 3V 0.15 2.0 Condition Min. Units mA A 1. All bits set in the "PRR0 - Power Reduction Register 0" on page 56. 2. Typical values at 25C. Maximum values are test limits in production. 3. The current consumption values include input leakage current. 28.1.6 ATmega644PA DC characteristics Table 28-7. Symbol TA = -40C to 85C, VCC = 1.8V to 5.5V (unless otherwise noted) Parameter Condition Power Supply Current (1) ICC Power-save mode (3) Power-down mode (3) Notes: Min. Units mA A 1. All bits set in the "PRR0 - Power Reduction Register 0" on page 56. 2. Typical values at 25C. Maximum values are test limits in production. 3. The current consumption values include input leakage current. 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 330 ATmega164A/PA/324A/PA/644A/PA/1284/P 28.1.7 ATmega1284 DC characteristics Table 28-8. Symbol TA = -40C to 85C, VCC = 1.8V to 5.5V (unless otherwise noted) Parameter Power Supply Current (1) ICC Power-save mode (3) Power-down mode (3) Notes: Typ. (2) Max. Active 1MHz, VCC = 2V 0.38 0.55 Active 4MHz, VCC = 3V 1.8 3.5 Active 8MHz, VCC = 5V 5.6 12 Idle 1MHz, VCC = 2V 0.06 0.5 Idle 4MHz, VCC = 3V 0.2 1.5 Idle 8MHz, VCC = 5V 1.1 5.5 32kHz TOSC enabled, VCC = 1.8V 0.5 32kHz TOSC enabled, VCC = 3V 0.6 WDT enabled, VCC = 3V 4.2 15 WDT disabled, VCC = 3V 0.15 3.0 Typ. (2) Max. Active 1MHz, VCC = 2V 0.38 0.5 Active 4MHz, VCC = 3V 1.8 2.9 Active 8MHz, VCC = 5V 5.6 9.0 Idle 1MHz, VCC = 2V 0.06 0.15 Idle 4MHz, VCC = 3V 0.2 0.7 Idle 8MHz, VCC = 5V 1.1 5.0 32kHz TOSC enabled, VCC = 1.8V 0.5 32kHz TOSC enabled, VCC = 3V 0.6 WDT enabled, VCC = 3V 4.2 10 WDT disabled, VCC = 3V 0.15 5 Condition Min. Units mA A 1. All bits set in the "PRR0 - Power Reduction Register 0" on page 56. 2. Typical values at 25C. Maximum values are test limits in production. 3. The current consumption values include input leakage current. 28.1.8 ATmega1284P DC characteristics Table 28-9. Symbol TA = -40C to 85C, VCC = 1.8V to 5.5V (unless otherwise noted) Parameter Condition Power Supply Current (1) ICC Power-save mode (3) Power-down mode (3) Notes: Min. Units mA A 1. All bits set in the "PRR0 - Power Reduction Register 0" on page 56. 2. Typical values at 25C. Maximum values are test limits in production. 3. The current consumption values include input leakage current. 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 331 ATmega164A/PA/324A/PA/644A/PA/1284/P 28.2 Speed grades Maximum frequency is depending on VCC. As shown in Figure 28-1, the maximum frequency vs. VCC curve is linear between 1.8V < VCC < 2.7V and between 2.7V < VCC < 4.5V. Figure 28-1. Maximum frequency vs. VCC, ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P 20MHz 10MHz Safe operating area 4MHz 1.8V 2018 Microchip Technology Inc. 2.7V 4.5V Data Sheet Complete 5.5V DS40002070A-page 332 ATmega164A/PA/324A/PA/644A/PA/1284/P 28.3 Clock characteristics Table 28-10. Calibration accuracy of internal RC oscillator Factory calibration User calibration Notes: Frequency VCC 8.0MHz 3V 7.3 - 8.1MHz 1.8 - 5.5V (1) Temperature Calibration accuracy 25C 10% -40C - 85C 1% 1. Voltage range for ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P. 28.3.1 External clock drive waveforms Figure 28-2. External clock drive waveforms. V IH1 V IL1 28.3.2 External clock drive Table 28-11. External clock drive VCC = 1.8 - 5.5V VCC = 2.7 - 5.5V VCC = 4.5 - 5.5V Symbol Parameter 1/tCLCL Oscillator Frequency tCLCL Clock Period 250 100 50 tCHCX High Time 100 40 20 tCLCX Low Time 100 40 20 tCLCH Rise Time 2.0 1.6 0.5 tCHCL Fall Time 2.0 1.6 0.5 tCLCL Change in period from one clock cycle to the next 2 2 2 2018 Microchip Technology Inc. Min. Max. Min. Max. Min. Max. Units 0 4 0 10 0 20 MHz Data Sheet Complete ns s % DS40002070A-page 333 ATmega164A/PA/324A/PA/644A/PA/1284/P 28.4 System and reset characteristics Table 28-12. Symbol Reset, Brown-out and Internal Voltage Reference characteristics Parameter Condition Power-on Reset Threshold Voltage (rising) VPOT Power-on Reset Threshold Voltage (falling) VRST RESET Pin Threshold Voltage tRST Minimum pulse width on RESET Pin VHYST (1) Min. Typ. Max. 1.1 1.4 1.6 0.6 1.3 1.6 0.2VCC Units V 0.9VCC 2.5 s Brown-out Detector Hysteresis 50 mV tBOD Min Pulse Width on Brown-out Reset 2 s VBG Bandgap reference voltage VCC= 2.7V, TA = 25C tBG Bandgap reference start-up time IBG Bandgap reference current consumption 1.0 1.1 1.2 V VCC= 2.7V, TA = 25C 40 70 s VCC= 2.7V, TA = 25C 10 A Notes: 1. The Power-on Reset will not work unless the supply voltage has been below VPOT (falling). Table 28-13. BODLEVEL fuse coding (1). BODLEVEL 2:0 Fuses Min. VBOT Typ. VBOT 111 Max. VBOT Units BOD disabled 110 1.7 1.8 2.0 101 2.5 2.7 2.9 100 4.1 4.3 4.5 V 011 010 Reserved 001 000 Note: 1. VBOT may be below nominal minimum operating voltage for some devices. For devices where this is the case, the device is tested down to VCC = VBOT during the production test. This guarantees that a Brown-Out Reset will occur before VCC drops to a voltage where correct operation of the microcontroller is no longer ensured. The test is performed using BODLEVEL = 101 and BODLEVEL = 110. 28.5 External interrupts characteristics Table 28-14. Symbol tINT Asynchronous external interrupt characteristics Parameter Condition Minimum pulse width for asynchronous external interrupt 2018 Microchip Technology Inc. Data Sheet Complete Min. Typ. 50 Max. Units ns DS40002070A-page 334 ATmega164A/PA/324A/PA/644A/PA/1284/P 28.6 SPI timing characteristics See Figure 28-3 on page 335 and Figure 28-4 on page 336 for details. Table 28-15. SPI timing parameters Description Mode 1 SCK period Master See Table 18-5 on page 173 2 SCK high/low Master 50% duty cycle 3 Rise/Fall time Master 3.6 4 Setup Master 10 5 Hold Master 10 6 Out to SCK Master 0.5 x tsck 7 SCK to out Master 10 8 SCK to out high Master 10 9 SS low to out Slave 15 10 SCK period Slave 4 x tck Slave 2 x tck 11 SCK high/low (1) Min. 12 Rise/Fall time Slave 13 Setup Slave 10 14 Hold Slave tck 15 SCK to out Slave 16 SCK to SS high Slave 17 SS high to tri-state Slave 18 SS low to SCK Slave Note: 1. Figure 28-3. Typ. Max. Unit ns 1600 15 20 10 20 In SPI Programming mode the minimum SCK high/low period is: - 2 tCLCL for fCK < 12MHz - 3 tCLCL for fCK > 12MHz SPI interface timing requirements (Master mode) SS 6 1 SCK (CPOL = 0) 2 2 SCK (CPOL = 1) 4 MISO (Data Input) 5 3 MSB ... LSB 8 7 MOSI (Data Output) 2018 Microchip Technology Inc. MSB ... Data Sheet Complete LSB DS40002070A-page 335 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 28-4. SPI interface timing requirements (Slave mode) SS 10 9 16 SCK (CPOL = 0) 11 11 SCK (CPOL = 1) 13 MOSI (Data Input) 14 12 MSB ... LSB 15 MISO (Data Output) 28.7 17 MSB ... LSB X Two-wire Serial Interface Characteristics Table 28-16 describes the requirements for devices connected to the two-wire Serial Bus. The ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P two-wire Serial Interface meets or exceeds these requirements under the noted conditions. Timing symbols refer to Figure 28-5. Table 28-16. Symbol VIL VIH Vhys (1) VOL (1) tr (1) tof (1) tSP (1) two-wire serial bus requirements Parameter Min. Max. Input Low-voltage -0.5 0.3VCC Input High-voltage 0.7 VCC Hysteresis of Schmitt Trigger Inputs Output Low-voltage Output Fall Time from VIHmin to VILmax Ci (1) Capacitance for each I/O Pin fSCL SCL Clock Frequency tLOW 3mA sink current 10pF < Cb < 400pF (3) Value of Pull-up resistor Hold Time (repeated) START Condition Low Period of the SCL Clock 2018 Microchip Technology Inc. (2) 0 - Units V 0.4 300 20 + 0.1Cb (2)(3) 250 0 0.1VCC < Vi < 0.9VCC VCC + 0.5 (2)(3) 20 + 0.1Cb Spikes Suppressed by Input Filter Input Current each I/O Pin tHD;STA 0.05 VCC Rise Time for both SDA and SCL Ii Rp Condition 50 ns (2) -10 10 A - 10 pF fCK(4) > max(16fSCL, 250kHz)(5) 0 400 kHz fSCL 100kHz V CC - 0.4V ---------------------------3mA 1000ns ------------------Cb fSCL > 100kHz V CC - 0.4V ---------------------------3mA 300ns ---------------Cb fSCL 100kHz 4.0 - fSCL > 100kHz 0.6 - fSCL 100kHz 4.7 - fSCL > 100kHz 1.3 - Data Sheet Complete s DS40002070A-page 336 ATmega164A/PA/324A/PA/644A/PA/1284/P Table 28-16. two-wire serial bus requirements (Continued) Symbol Parameter tHIGH High period of the SCL clock tSU;STA Set-up time for a repeated START condition tHD;DAT Data hold time tSU;DAT Data setup time tSU;STO Setup time for STOP condition tBUF Bus free time between a STOP and START condition Notes: 1. 2. 3. 4. 5. Condition Min. Max. fSCL 100kHz 4.0 - fSCL > 100kHz 0.6 - fSCL 100kHz 4.7 - fSCL > 100kHz 0.6 - fSCL 100kHz 0 3.45 fSCL > 100kHz 0 0.9 fSCL 100kHz 250 - fSCL > 100kHz 100 - fSCL 100kHz 4.0 - fSCL > 100kHz 0.6 - fSCL 100kHz 4.7 - fSCL > 100kHz 1.3 - Units s ns s In ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P, this parameter is characterized and not 100% tested. Required only for fSCL > 100kHz. Cb = capacitance of one bus line in pF. fCK = CPU clock frequency. This requirement applies to all ATmega324 two-wire Serial Interface operation. Other devices connected to the two-wire Serial Bus need only obey the general fSCL requirement. Figure 28-5. Two-wire serial bus timing tof tHIGH tr tLOW tLOW SCL tSU;STA tHD;STA tHD;DAT tSU;DAT SDA tSU;STO tBUF 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 337 ATmega164A/PA/324A/PA/644A/PA/1284/P 28.8 ADC characteristics Table 28-17. Symbol ADC characteristics, single ended channel Typ. (1) Max. (1) Condition Resolution Single Ended Conversion 10 Single Ended Conversion VREF = 4V, VCC = 4V, ADC clock = 200kHz 1.9 Single Ended Conversion VREF = 4V, VCC = 4V, ADC clock = 1MHz 3.25 Single Ended Conversion VREF = 4V, VCC = 4V, ADC clock = 200kHz Noise Reduction Mode 1.9 Single Ended Conversion VREF = 4V, VCC = 4V, ADC clock = 1MHz Noise Reduction Mode 3.25 Integral Non-Linearity (INL) Single Ended Conversion VREF = 4V, VCC = 4V, ADC clock = 200kHz 1.1 Differential Non-Linearity (DNL) Single Ended Conversion VREF = 4V, VCC = 4V, ADC clock = 200kHz 0.3 Gain Error Single Ended Conversion VREF = 4V, VCC = 4V, ADC clock = 200kHz 1.6 Offset Error Single Ended Conversion VREF = 4V, VCC = 4V, ADC clock = 200kHz -1.5 Conversion Time Free Running Conversion 13 260 s Clock Frequency Single Ended Conversion 50 1000 kHz VCC - 0.3 VCC + 0.3 1.0 AVCC GND VREF Absolute accuracy (Including INL, DNL, quantization error, gain and offset error) AVCC Analog Supply Voltage VREF Reference Voltage VIN Min. (1) Parameter Input Voltage Units Bits LSB Input Bandwidth 38.5 V kHz VINT1 Internal Voltage Reference 1.1V 1.0 1.1 1.2 VINT2 Internal Voltage Reference 2.56V, VCC > 2.7V 2.33 2.56 2.79 RREF Reference Input Resistance 32 k RAIN Analog Input Resistance 100 M Notes: V 1. Values are guidelines only. 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 338 ATmega164A/PA/324A/PA/644A/PA/1284/P Table 28-18. ADC characteristics, differential channels Symbol Parameter Resolution Absolute Accuracy (Including INL, DNL Quantization Error and Offset Error) Integral Non-linearity (INL) Differential Non-linearity (DNL) 2018 Microchip Technology Inc. Condition Min. (1) Typ. (1) Gain = 1x 10 Gain = 10x 10 Gain = 200x 7 Gain = 1x VCC = 5V, VREF = 4V ADC clock = 200kHz 19 Gain = 10x VCC = 5V, VREF = 4V ADC clock = 200kHz 19 Gain = 200x VCC = 5V, VREF = 4V ADC clock = 200kHz 12 Gain = 1x VCC = 5V, VREF = 4V ADC clock = 200kHz 2 Gain = 10x VCC = 5V, VREF = 4V ADC clock = 200kHz 4 Gain = 200x VCC = 5V, VREF = 4V ADC clock = 200kHz 11 Gain = 1x VCC = 5V, VREF = 4V ADC clock = 200kHz 1 Gain = 10x VCC = 5V, VREF = 4V ADC clock = 200kHz 1.5 Gain = 200x VCC = 5V, VREF = 4V ADC clock = 200kHz 11 Data Sheet Complete Max. (1) Units Bits LSB DS40002070A-page 339 ATmega164A/PA/324A/PA/644A/PA/1284/P Table 28-18. ADC characteristics, differential channels (Continued) Symbol Parameter Condition Min. (1) Typ. (1) Max. (1) Units Gain = 1x 18 VCC = 5V, VREF = 4V ADC clock = 200kHz Gain = 10x Gain Error 19 VCC = 5V, VREF = 4V ADC clock = 200kHz Gain = 200x 1.5 VCC = 5V, VREF = 4V ADC clock = 200kHz LSB Gain = 1x -1 VCC = 5V, VREF = 4V ADC clock = 200kHz Gain = 10x Offset Error -1 VCC = 5V, VREF = 4V ADC clock = 200kHz Gain = 200x 1 VCC = 5V, VREF = 4V ADC clock = 200kHz Conversion Time 13 260 s Clock Frequency 50 1000 kHz VCC - 0.3 VCC + 0.3 2.0 AVCC - 0.5 Input Differential Voltage 0 AVCC ADC Conversion Output -511 511 AVCC Analog Supply Voltage VREF Reference Voltage VIN Input Bandwidth 4 Internal Voltage Reference 1.1V 1.0 1.1 1.2 VINT2 Internal Voltage Reference 2.56V 2.33 2.56 2.79 RREF Reference Input Resistance Note: LSB kHz VINT1 32 V V k 1. Values are guidelines only. 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 340 ATmega164A/PA/324A/PA/644A/PA/1284/P 29. Electrical Characteristics - TA = -40C to 105C Absolute Maximum Ratings* *NOTICE: Operating Temperature .................................. -55C to +125C Storage Temperature...................................... -65C to +150C Voltage on any Pin except RESET with respect to Ground ................................ -0.5V to VCC+0.5V Voltage on RESET with respect to Ground ..... -0.5V to +13.0V Maximum Operating Voltage............................................. 6.0V Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Current per I/O Pin................................................ 40.0 mA DC Current VCC and GND Pins ................................ 200.0 mA 29.1 DC Characteristics TA = -40C to 105C, VCC = 1.8V to 5.5V (unless otherwise noted) Symbol Parameter Condition Min. VIL Input Low Voltage, Except XTAL1 and Reset pin VCC = 1.8V - 2.4V VCC = 2.4V - 5.5V VIL1 Input Low Voltage, XTAL1 pin VIL2 Max. Units -0.5 -0.5 0.2VCC(1) 0.3VCC(1) V VCC = 1.8V - 5.5V -0.5 0.1VCC(1) V Input Low Voltage, RESET pin VCC = 1.8V - 5.5V -0.5 0.1VCC(1) V VIH Input High Voltage, Except XTAL1 and RESET pins VCC = 1.8V - 2.4V VCC = 2.4V - 5.5V 0.7VCC(2) 0.6VCC(3) VCC + 0.5 VCC + 0.5 V VIH1 Input High Voltage, XTAL1 pin VCC = 1.8V - 2.4V VCC = 2.4V - 5.5V 0.8VCC(2) 0.7VCC(2) VCC + 0.5 VCC + 0.5 V VIH2 Input High Voltage, RESET pin VCC = 1.8V - 5.5V 0.9VCC(2) VCC + 0.5 V VOL Output Low Voltage(3), Port B (except RESET) IOL =10 mA, VCC = 5V IOL =5 mA, VCC = 3V 1.0 0.7 V VOH Output High Voltage(4), Port B (except RESET) IOH = -20 mA, VCC = 5V IOH = -10 mA, VCC = 3V IIL Input Leakage Current I/O Pin 1 A IIH Input Leakage Current I/O Pin 1 A RRST Reset Pull-up Resistor 30 60 k RPU I/O Pin Pull-up Resistor 20 50 k VACIO Analog Comparator Input Offset Voltage VCC = 5V Vin = VCC/2 40 mV IACLK Analog Comparator Input Leakage Current VCC = 5V Vin = VCC/2 50 nA 2018 Microchip Technology Inc. Typ. 4.0 2.1 -50 Data Sheet Complete V DS40002070A-page 341 ATmega164A/PA/324A/PA/644A/PA/1284/P Note: 1. "Max" means the highest value where the pin is ensured to be read as low 2. "Min" means the lowest value where the pin is ensured to be read as high 3. Although each I/O port can sink more than the test conditions (20mA at VCC = 5V, 10mA at VCC = 3V) under steady state conditions (non-transient), the following must be observed: 1.)The sum of all IOL, for ports PB0-PB7, XTAL2, PD0-PD7 should not exceed 100 mA. 2.)The sum of all IOL, for ports PA0-PA3, PC0-PC7 should not exceed 100 mA. If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test condition. 4. Although each I/O port can source more than the test conditions (20mA at VCC = 5V, 10mA at VCC = 3V) under steady state conditions (non-transient), the following must be observed: 1.)The sum of all IOH, for ports PB0-PB7, XTAL2, PD0-PD7 should not exceed 100 mA. 2.)The sum of all IOH, for ports PA0-PA3, PC0-PC7 should not exceed 100 mA. If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current greater than the listed test condition. 29.1.1 ATmega164PA DC Characteristics Table 29-1. Symbol TA = -40C to 105C, VCC = 1.8V to 5.5V (unless otherwise noted) Parameter Power Supply Current(1) ICC Power-down mode(2) Notes: Min. Typ. Max. Units Active 1 MHz, VCC = 2V 0.7 mA Active 4 MHz, VCC = 3V 3 mA Active 8 MHz, VCC = 5V 11 mA Idle 1 MHz, VCC = 2V 0.17 mA Idle 4 MHz, VCC = 3V 0.85 mA Idle 8 MHz, VCC = 5V 6 mA WDT enabled, VCC = 3V 15 A WDT disabled, VCC = 3V 5 A Max. Units Active 1 MHz, VCC = 2V 0.7 mA Active 4 MHz, VCC = 3V 3 mA Active 8 MHz, VCC = 5V 11 mA Idle 1 MHz, VCC = 2V 0.17 mA Idle 4 MHz, VCC = 3V 0.85 mA Idle 8 MHz, VCC = 5V 6 mA WDT enabled, VCC = 3V 15 A WDT disabled, VCC = 3V 5 A 1. All bits set in the "PRR0 - Power Reduction Register 0" on page 56 2. The current consumption values include input leakage current. 29.1.2 ATmega324PA DC Characteristics Table 29-2. Symbol TA = -40C to 105C, VCC = 1.8V to 5.5V (unless otherwise noted) Parameter Power Supply Current(1) ICC Power-down mode(2) Notes: Condition Condition Min. Typ. 1. All bits set in the "PRR0 - Power Reduction Register 0" on page 56 2. The current consumption values include input leakage current. 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 342 ATmega164A/PA/324A/PA/644A/PA/1284/P 29.1.3 ATmega644PA DC Characteristics Table 29-3. Symbol TA = -40C to 105C, VCC = 1.8V to 5.5V (unless otherwise noted) Parameter Power Supply Current(1) ICC Power-down mode(2) Notes: Condition Min. Typ. Max. Units Active 1 MHz, VCC = 2V 0.7 mA Active 4 MHz, VCC = 3V 3 mA Active 8 MHz, VCC = 5V 11 mA Idle 1 MHz, VCC = 2V 0.17 mA Idle 4 MHz, VCC = 3V 0.85 mA Idle 8 MHz, VCC = 5V 6 mA WDT enabled, VCC = 3V 15 A WDT disabled, VCC = 3V 5 A Max. Units Active 1 MHz, VCC = 2V 0.8 mA Active 4 MHz, VCC = 3V 3 mA Active 8 MHz, VCC = 5V 11 mA Idle 1 MHz, VCC = 2V 0.17 mA Idle 4 MHz, VCC = 3V 0.85 mA Idle 8 MHz, VCC = 5V 6 mA WDT enabled, VCC = 3V 18 A WDT disabled, VCC = 3V 13 A 1. All bits set in the "PRR0 - Power Reduction Register 0" on page 56 The current consumption values include input leakage current. 2. The current consumption values include input leakage current 29.1.4 ATmega1284P DC Characteristics Table 29-4. Symbol TA = -40C to 105C, VCC = 1.8V to 5.5V (unless otherwise noted) Parameter Power Supply Current(1) ICC Power-down mode(2) Notes: Condition Min. Typ. 1. All bits set in the "PRR0 - Power Reduction Register 0" on page 56 2. The current consumption values include input leakage current. 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 343 ATmega164A/PA/324A/PA/644A/PA/1284/P 30. Typical characteristics -TA = -40C to 85C The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with rail-to-rail output is used as clock source. All Active- and Idle current consumption measurements are done with all bits in the PRR registers set and thus, the corresponding I/O modules are turned off. Also the Analog Comparator is disabled during these measurements. The power consumption in Power-down mode is independent of clock selection. The current consumption is a function of several factors such as: operating voltage, operating frequency, loading of I/O pins, switching rate of I/O pins, code executed and ambient temperature. The dominating factors are operating voltage and frequency. The current drawn from capacitive loaded pins may be estimated (for one pin) as CL x VCC x f where CL = load capacitance, VCC = operating voltage and f = average switching frequency of I/O pin. The parts are characterized at frequencies higher than test limits. Parts are not guaranteed to function properly at frequencies higher than the ordering code indicates. The difference between current consumption in Power-down mode with Watchdog Timer enabled and Powerdown mode with Watchdog Timer disabled represents the differential current drawn by the Watchdog Timer. 30.1 ATmega164A typical characteristics - TA = -40C to 85C 30.1.1 Active supply current Figure 30-1. ATmega164A: Active supply current vs. low frequency (0.1 - 1.0MHz) 1.2 5.5V 1.0 5.0V ICC [mA] 0.8 4.5V 4.0V 0.6 3.3V 0.4 2.7V 1.8V 0.2 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency [MHz] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 344 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-2. ATmega164A: Active supply current vs. frequency (1 - 20MHz) 12 5.5V 10 5.0V 4.5V ICC [mA] 8 4.0V 6 4 3.3V 2.7V 2 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency [MHz] ATmega164A: Active supply current vs. VCC (internal RC oscillator, 8MHz) Figure 30-3. 6 85C 25C -40C 5 ICC [mA] 4 3 2 1 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 345 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-4. ATmega164A: Active supply current vs. VCC (internal RC oscillator, 1MHz) 1.2 85C 25C -40C 1.0 ICC [mA] 0.8 0.6 0.4 0.2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] ATmega164A: Active supply current vs. VCC (internal RC oscillator, 128kHz) Figure 30-5. 0.25 -40C 25C 85C ICC [mA] 0.20 0.15 0.10 0.05 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 346 ATmega164A/PA/324A/PA/644A/PA/1284/P 30.1.2 Idle supply current Figure 30-6. ATmega164A: Idle supply current vs. VCC (0.1 - 1.0MHz) 0.20 5.5V 5.0V 4.5V 0.15 ICC [mA] 4.0V 3.3V 0.10 2.7V 1.8V 0.05 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency [MHz] ATmega164A: Idle supply current vs. VCC (1 - 20MHz) Figure 30-7. 3.0 5.5V 2.5 5.0V ICC [mA] 2.0 4.5V 1.5 4.0V 1.0 3.3V 0.5 2.7V 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency [MHz] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 347 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-8. ATmega164A: Idle supply current vs. VCC (internal RC oscillator, 8MHz) 1.2 85C 25C -40C 1.0 ICC [mA] 0.8 0.6 0.4 0.2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] ATmega164A: Idle supply current vs. VCC (internal RC oscillator, 1MHz) Figure 30-9. 0.35 -40C 25C 85C 0.30 ICC [mA] 0.25 0.20 0.15 0.10 0.05 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 348 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-10. ATmega164A: Idle supply current vs. VCC (internal RC oscillator, 128kHz) 0.12 -40C 0.10 25C 85C ICC [mA] 0.08 0.06 0.04 0.02 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 349 ATmega164A/PA/324A/PA/644A/PA/1284/P 30.1.3 Supply current of I/O modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register. See "PRR0 - Power Reduction Register 0" on page 56 for details. Table 30-1. PRR bit Additional current consumption for the different I/O modules (absolute values) Typical numbers VCC = 2V, F = 1MHz VCC = 3V, F = 4MHz VCC = 5V, F = 8MHz PRUSART1 3.1A 20.9A 96.7A PRUSART0 2.9A 21.6A 101A PRTWI 6.1A 44A 205.8A PRTIM2 5.9A 40.1A 182A PRTIM1 3.7A 26.1A 113.2A PRTIM0 1.4A 9.4A 38.8A PRADC 11.7A 55.5A 249.5A PRSPI 5.1A 37.9A 195.5A Table 30-2. PRR bit Additional current consumption (percentage) in Active and Idle mode Additional current consumption compared to Active with external clock (see Figure 30-50 on page 371 and Figure 30-51 on page 371) Additional current consumption compared to Idle with external clock (see Figure 30-55 on page 373 and Figure 30-56 on page 374) PRUSART1 1.5% 7.4% PRUSART0 1.5% 7.5% PRTWI 3.2% 15.4% PRTIM2 2.9% 14.0% PRTIM1 1.8% 8.8% PRTIM0 0.7% 3.1% PRADC 4.4% 20.9% PRSPI 2.9% 13.8% It is possible to calculate the typical current consumption based on the numbers from Table 30-4 on page 376 for other VCC and frequency settings than listed in Table 30-3 on page 376. Exam p l e Calculate the expected current consumption in idle mode with TIMER1, ADC, and SPI enabled at VCC = 2.0V and F = 1MHz. From Table 30-4 on page 376, third column, we see that we need to add 8.8% for the TIMER1, 20.9% for the ADC, and 13.8% for the SPI module. Reading from Figure 30-55 on page 373, we find that the idle current consumption is ~0.073mA at VCC = 2.0V and F = 1MHz. The total current consumption in idle mode with TIMER1, ADC, and SPI enabled, gives: I CC total 0.073 mA (1+ 0.088 + 0.209 + 0.138) 0.10 mA 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 350 ATmega164A/PA/324A/PA/644A/PA/1284/P 30.1.4 Power-down supply current Figure 30-11. ATmega164A: Power-down supply current vs. VCC (watchdog timer disabled) 1.6 85C 1.4 1.2 ICC [A] 1.0 0.8 0.6 0.4 25C -40C 0.2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-12. ATmega164A: Power-down supply current vs. VCC (watchdog timer enabled) 10 -40C 25C 85C ICC [A] 8 6 4 2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 351 ATmega164A/PA/324A/PA/644A/PA/1284/P 30.1.5 Power-save supply current Figure 30-13. ATmega164A: Power-save supply current vs. VCC (watchdog timer disabled and 32kHz crystal oscillator running) 1.8 1.5 25C ICC [A] 1.2 0.9 0.6 0.3 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 30.1.6 Standby supply current Figure 30-14. ATmega164A: Standby supply current vs. VCC (watchdog timer disabled) 0.20 6MHz_xtal 6MHz_res 0.18 0.16 ICC [mA] 0.14 4MHz_res 4MHz_xtal 0.12 0.10 2MHz_res 2MHz_xtal 1MHz_res 0.08 0.06 450kHz_res 0.04 0.02 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 352 ATmega164A/PA/324A/PA/644A/PA/1284/P 30.1.7 Pin pull-up Figure 30-15. ATmega164A: I/O pin pull-up resistor current vs. Input voltage (VCC = 1.8V) 50 45 40 IOP [A] 35 30 25 20 15 25C 85C -40C 10 5 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 VOP [V] Figure 30-16. ATmega164A: I/O pin pull-up resistor current vs. input voltage (VCC = 2.7V) 80 70 60 IOP [A] 50 40 30 20 25C 85C -40C 10 0 0 0.5 1.0 1.5 2.0 2.5 3.0 VOP [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 353 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-17. ATmega164A: I/O pin pull-up resistor current vs. input voltage (VCC = 5V) 140 120 IOP [A] 100 80 60 40 25C 20 85C -40C 0 0 1 2 3 4 5 6 VOP [V] Figure 30-18. ATmega164A: Reset pull-up resistor current vs. reset pin voltage (VCC = 1.8V) 35 30 IRESET [A] 25 20 15 10 25C -40C 85C 5 0 0 0.5 1.0 1.5 2.0 VRESET [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 354 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-19. ATmega164A: Reset pull-up resistor current vs. reset pin voltage (VCC = 2.7V) 60 50 IRESET [A] 40 30 20 25C -40C 85C 10 0 0 0.5 1.0 1.5 2.0 2.5 3.0 VRESET [V] Figure 30-20. ATmega164A: Reset pull-up resistor current vs. reset pin voltage (VCC = 5V) 120 100 IRESET [A] 80 60 40 25C -40C 85C 20 0 0 1 2 3 4 5 6 VRESET [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 355 ATmega164A/PA/324A/PA/644A/PA/1284/P 30.1.8 Pin driver strength Figure 30-21. ATmega164A: I/O pin output voltage vs. sink current (VCC = 3V) 1.0 85C 0.8 25C VOL [V] 0.6 -40C 0.4 0.2 0 0 4 8 12 16 20 IOL [mA] Figure 30-22. ATmega164A: I/O pin output voltage vs. sink current (VCC = 5V) 0.6 85C 0.5 25C VOL [V] 0.4 -40C 0.3 0.2 0.1 0 0 4 8 12 16 20 IOL [mA] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 356 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-23. ATmega164A: I/O pin output voltage vs. source current (VCC = 3V) 3.5 3.0 VOH [V] 2.5 -40C 25C 85C 2.0 1.5 1.0 0.5 0 0 4 8 12 16 20 IOH [mA] Figure 30-24. ATmega164A: I/O pin output voltage vs. source current (VCC = 5V) 5.1 5.0 4.9 VOH [V] 4.8 4.7 4.6 -40C 4.5 25C 4.4 85C 4.3 0 4 8 12 16 20 IOH [mA] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 357 ATmega164A/PA/324A/PA/644A/PA/1284/P 30.1.9 Pin threshold and hysteresis Figure 30-25. ATmega164A: I/O pin input threshold vs. VCC (VIH I/O pin read as `1') 3.0 85C 25C -40C 2.5 Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-26. ATmega164A: I/O pin input threshold vs. VCC (VIL, I/O pin read as `0') 2.5 85C 25C -40C Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 358 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-27. ATmega164A: I/O pin input hysteresis vs. VCC 0.6 -40C 25C 85C Input hysteresis [mV] 0.5 0.4 0.3 0.2 0.1 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-28. ATmega164A: Reset pin input threshold vs. VCC (VIH I/O pin read as `1') 2.5 -40C 25C 85C Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 359 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-29. ATmega164A: Reset pin input threshold vs. VCC (VIL, I/O pin read as `0') 2.5 85C 25C -40C Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-30. ATmega164A: Reset pin input hysteresis vs. VCC 0.7 Input hysteresis [mV] 0.6 0.5 0.4 0.3 0.2 -40C 25C 85C 0.1 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 360 ATmega164A/PA/324A/PA/644A/PA/1284/P 30.1.10 BOD threshold Figure 30-31. ATmega164A: BOD threshold vs. temperature (VBOT = 4.3V) 4.34 Rising Vcc 4.32 Threshold [V] 4.30 4.28 4.26 Falling Vcc 4.24 4.22 4.20 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 70 80 90 Temperature [C] Figure 30-32. ATmega164A: BOD threshold vs. temperature (VBOT = 2.7V) 2.78 Rising Vcc 2.76 Threshold [V] 2.74 2.72 2.70 Falling Vcc 2.68 2.66 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 Temperature [C] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 361 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-33. ATmega164A: BOD threshold vs. temperature (VBOT = 1.8V) 1.850 Rising Vcc 1.845 1.840 Threshold [V] 1.835 1.830 1.825 1.820 1.815 Falling Vcc 1.810 1.805 1.80 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [C] Figure 30-34. ATmega164A: Calibrated bandgap voltage vs. VCC 1.109 1.107 Bandgap voltage [V] 1.105 1.103 25C 85C 1.101 1.099 1.097 1.095 1.093 1.091 1.5 -40C 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 362 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-35. ATmega164A: Bandgap voltage vs. temperature. 1.087 1.8V 3.6V 2.7V 4.5V 1.085 Bandgap voltage [V] 1.083 1.081 5.5V 1.079 1.077 1.075 1.073 1.071 1.069 1.067 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [C] 30.1.11 Internal oscillator speed Figure 30-36. ATmega164A: Watchdog oscillator frequency vs. temperature 134 132 FRC [kHz] 130 128 126 2.1V 2.7V 3.3V 4.0V 5.5V 124 122 120 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [C] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 363 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-37. ATmega164A: Watchdog oscillator frequency vs. VCC 135 132 FRC [kHz] -40C 129 25C 126 123 85C 120 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-38. ATmega164A: Calibrated 8MHz RC oscillator vs. VCC 8.4 85C 8.2 FRC [MHz] 8.0 25C 7.8 -40C 7.6 7.4 7.2 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 364 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-39. ATmega164A: Calibrated 8MHz RC oscillator vs. temperature 8.3 5.0V 3.0V 8.2 FRC [MHz] 8.1 8.0 7.9 7.8 7.7 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [C] Figure 30-40. ATmega164A: Calibrated 8MHz RC oscillator vs. OSCCAL value 16 85C 25C -40C 14 FRC [MHz] 12 10 8 6 4 2 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL [X1] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 365 ATmega164A/PA/324A/PA/644A/PA/1284/P 30.1.12 Current consumption of peripheral units Figure 30-41. ATmega164A: ADC current vs. VCC (AREF = AVCC) 320 -40C 85C 25C 280 240 ICC [A] 200 160 120 80 40 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-42. ATmega164A: Analog comparator current vs. VCC 100 90 -40C 80 25C 85C ICC [A] 70 60 50 40 30 20 10 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 366 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-43. ATmega164A: AREF external reference current vs. VCC 200 25C 85C -40C ICC [A] 160 120 80 40 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-44. ATmega164A: Brownout detector current vs. VCC 27 85C 25C -40C 24 21 ICC [A] 18 15 12 9 6 3 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 367 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-45. ATmega164A: Programming current vs. VCC 12 -40C 25C 85C 10 ICC [mA] 8 6 4 2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-46. ATmega164A: Watchdog timer current vs. VCC 9 -40C 8 25C 85C 7 ICC [A] 6 5 4 3 2 1 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 368 ATmega164A/PA/324A/PA/644A/PA/1284/P 30.1.13 Current consumption in reset and reset pulsewidth Figure 30-47. ATmega164A: Reset supply current vs. low frequency (0.1 - 1.0MHz) 0.10 5.5V 0.08 5.0V ICC [mA] 4.5V 0.06 4.0V 3.3V 0.04 2.7V 1.8V 0.02 0 0 0.2 0.4 0.6 0.8 1.0 Frequency [MHz] Figure 30-48. ATmega164A: Reset supply current vs. frequency (1 - 20MHz) 1.8 5.5V 1.5 5.0V 4.5V ICC [mA] 1.2 0.9 4.0V 0.6 3.3V 0.3 2.7V 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency [MHz] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 369 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-49. ATmega164A: Minimum reset pulsewidth vs. VCC 1600 1400 Pulsewidth [ns] 1200 1000 800 600 400 85C 25C -40C 200 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 370 ATmega164A/PA/324A/PA/644A/PA/1284/P 30.2 ATmega164PA typical characteristics - TA = -40C to 85C 30.2.1 Active supply current Figure 30-50. ATmega164PA: Active supply current vs. low frequency (0.1 - 1.0MHz) 1.2 5.5V 1.0 5.0V ICC [mA] 0.8 4.5V 4.0V 0.6 3.3V 0.4 2.7V 1.8V 0.2 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency [MHz] Figure 30-51. ATmega164PA: Active supply current vs. frequency (1 - 20MHz) 12 5.5V 10 5.0V 4.5V ICC [mA] 8 4.0V 6 4 3.3V 2.7V 2 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency [MHz] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 371 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-52. ATmega164PA: Active supply current vs. VCC (internal RC oscillator, 8MHz) 6 85C 25C -40C 5 ICC [mA] 4 3 2 1 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-53. ATmega164PA: Active supply current vs. VCC (internal RC oscillator, 1MHz) 1.2 85C 25C -40C 1.0 ICC [mA] 0.8 0.6 0.4 0.2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 372 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-54. ATmega164PA: Active supply current vs. VCC (internal RC oscillator, 128kHz) 0.25 -40C 25C 85C ICC [mA] 0.20 0.15 0.10 0.05 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 30.2.2 Idle supply current Figure 30-55. ATmega164PA: Idle supply current vs. VCC (0.1 - 1.0MHz) 0.20 5.5V 5.0V 4.5V 0.15 ICC [mA] 4.0V 3.3V 0.10 2.7V 1.8V 0.05 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency [MHz] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 373 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-56. ATmega164PA: Idle supply current vs. VCC (1 - 20MHz) 3.0 5.5V 2.5 5.0V ICC [mA] 2.0 4.5V 1.5 4.0V 1.0 3.3V 0.5 2.7V 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency [MHz] Figure 30-57. ATmega164PA: Idle supply current vs. VCC (internal RC oscillator, 8MHz) 1.2 85C 25C -40C 1.0 ICC [mA] 0.8 0.6 0.4 0.2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 374 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-58. ATmega164PA: Idle supply current vs. VCC (internal RC oscillator, 1MHz) 0.35 -40C 25C 85C 0.30 ICC [mA] 0.25 0.20 0.15 0.10 0.05 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-59. ATmega164PA: Idle supply current vs. VCC (internal RC oscillator, 128kHz) 0.12 -40C 0.10 25C 85C ICC [mA] 0.08 0.06 0.04 0.02 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 375 ATmega164A/PA/324A/PA/644A/PA/1284/P 30.2.3 Supply current of I/O modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register. See "PRR0 - Power Reduction Register 0" on page 56 for details. Table 30-3. PRR bit Additional current consumption for the different I/O modules (absolute values) Typical numbers VCC = 2V, F = 1MHz VCC = 3V, F = 4MHz VCC = 5V, F = 8MHz PRUSART1 3.1A 20.9A 96.7A PRUSART0 2.9A 21.6A 101A PRTWI 6.1A 44A 205.8A PRTIM2 5.9A 40.1A 182A PRTIM1 3.7A 26.1A 113.2A PRTIM0 1.4A 9.4A 38.8A PRADC 11.7A 55.5A 249.5A PRSPI 5.1A 37.9A 195.5A Table 30-4. PRR bit Additional current consumption (percentage) in Active and Idle mode Additional current consumption compared to Active with external clock (see Figure 30-50 on page 371 and Figure 30-51 on page 371) Additional current consumption compared to Idle with external clock (see Figure 30-55 on page 373 and Figure 30-56 on page 374) PRUSART1 1.5% 7.4% PRUSART0 1.5% 7.5% PRTWI 3.2% 15.4% PRTIM2 2.9% 14.0% PRTIM1 1.8% 8.8% PRTIM0 0.7% 3.1% PRADC 4.4% 20.9% PRSPI 2.9% 13.8% It is possible to calculate the typical current consumption based on the numbers from Table 30-4 on page 376 for other VCC and frequency settings than listed in Table 30-3 on page 376. Exam p l e Calculate the expected current consumption in idle mode with TIMER1, ADC, and SPI enabled at VCC = 2.0V and F = 1MHz. From Table 30-4 on page 376, third column, we see that we need to add 8.8% for the TIMER1, 20.9% for the ADC, and 13.8% for the SPI module. Reading from Figure 30-55 on page 373, we find that the idle current consumption is ~0.073mA at VCC = 2.0V and F = 1MHz. The total current consumption in idle mode with TIMER1, ADC, and SPI enabled, gives: I CC total 0.073mA (1+ 0.088 + 0.209 + 0.138) 0.105mA 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 376 ATmega164A/PA/324A/PA/644A/PA/1284/P 30.2.4 Power-down supply current Figure 30-60. ATmega164PA: Power-down supply current vs. VCC (watchdog timer disabled) 1.6 85C 1.4 1.2 ICC [A] 1.0 0.8 0.6 0.4 25C -40C 0.2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-61. ATmega164PA: Power-down supply current vs. VCC (watchdog timer enabled) 10 -40C 25C 85C ICC [A] 8 6 4 2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 377 ATmega164A/PA/324A/PA/644A/PA/1284/P 30.2.5 Power-save supply current Figure 30-62. ATmega164PA: Power-save supply current vs. VCC (watchdog timer disabled and 32kHz crystal oscillator running) 1.8 1.5 25C ICC [A] 1.2 0.9 0.6 0.3 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 30.2.6 Standby supply current Figure 30-63. ATmega164PA: Standby supply current vs. VCC (watchdog timer disabled) 0.20 6MHz_xtal 6MHz_res 0.18 0.16 ICC [mA] 0.14 4MHz_res 4MHz_xtal 0.12 0.10 2MHz_res 2MHz_xtal 1MHz_res 0.08 0.06 450kHz_res 0.04 0.02 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 378 ATmega164A/PA/324A/PA/644A/PA/1284/P 30.2.7 Pin pull-up Figure 30-64. ATmega164PA: I/O pin pull-up resistor current vs. input voltage (VCC = 1.8V) 50 45 40 IOP [A] 35 30 25 20 15 25C 85C -40C 10 5 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 VOP [V] Figure 30-65. ATmega164PA: I/O pin pull-up resistor current vs. input voltage (VCC = 2.7V) 80 70 60 IOP [A] 50 40 30 20 25C 85C -40C 10 0 0 0.5 1.0 1.5 2.0 2.5 3.0 VOP [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 379 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-66. ATmega164PA: I/O pin pull-up resistor current vs. input voltage (VCC = 5V) 140 120 IOP [A] 100 80 60 40 25C 20 85C -40C 0 0 1 2 3 4 5 6 VOP [V] Figure 30-67. ATmega164PA: Reset pull-up resistor current vs. reset pin voltage (VCC = 1.8V) 35 30 IRESET [A] 25 20 15 10 25C -40C 85C 5 0 0 0.5 1.0 1.5 2.0 VRESET [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 380 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-68. ATmega164PA: Reset pull-up resistor current vs. reset pin voltage (VCC = 2.7V) 60 50 IRESET [A] 40 30 20 25C -40C 85C 10 0 0 0.5 1.0 1.5 2.0 2.5 3.0 VRESET [V] Figure 30-69. ATmega164PA: Reset pull-up resistor current vs. reset pin voltage (VCC = 5V) 120 100 IRESET [A] 80 60 40 25C -40C 85C 20 0 0 1 2 3 4 5 6 VRESET [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 381 ATmega164A/PA/324A/PA/644A/PA/1284/P 30.2.8 Pin driver strength Figure 30-70. ATmega164PA: I/O pin output voltage vs. sink current (VCC = 3V) 1.0 85C 0.8 25C VOL [V] 0.6 -40C 0.4 0.2 0 0 4 8 12 16 20 IOL [mA] Figure 30-71. ATmega164PA: I/O pin output voltage vs. sink current (VCC = 5V) 0.6 85C 0.5 25C VOL [V] 0.4 -40C 0.3 0.2 0.1 0 0 4 8 12 16 20 IOL [mA] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 382 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-72. ATmega164PA: I/O pin output voltage vs. source current (VCC = 3V) 3.5 3.0 VOH [V] 2.5 -40C 25C 85C 2.0 1.5 1.0 0.5 0 0 4 8 12 16 20 IOH [mA] Figure 30-73. ATmega164PA: I/O pin output voltage vs. source current (VCC = 5V) 5.1 5.0 4.9 VOH [V] 4.8 4.7 4.6 -40C 4.5 25C 4.4 85C 4.3 0 4 8 12 16 20 IOH [mA] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 383 ATmega164A/PA/324A/PA/644A/PA/1284/P 30.2.9 Pin threshold and hysteresis Figure 30-74. ATmega164PA: I/O pin input threshold vs. VCC (VIH , I/O pin read as `1') 3.0 85C 25C -40C 2.5 Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-75. ATmega164PA: I/O pin input threshold vs. VCC (VIL, I/O pin read as `0') 2.5 85C 25C -40C Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 384 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-76. ATmega164PA: I/O pin input hysteresis vs. VCC 0.6 -40C 25C 85C Input hysteresis [mV] 0.5 0.4 0.3 0.2 0.1 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-77. ATmega164PA: Reset pin input threshold vs. VCC (VIH , I/O pin read as `1') 2.5 -40C 25C 85C Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 385 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-78. ATmega164PA: Reset pin input threshold vs. VCC (VIL, I/O pin read as `0') 2.5 85C 25C -40C Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-79. ATmega164PA: Reset pin input hysteresis vs. VCC 0.7 Input hysteresis [mV] 0.6 0.5 0.4 0.3 0.2 -40C 25C 85C 0.1 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 386 ATmega164A/PA/324A/PA/644A/PA/1284/P 30.2.10 BOD threshold Figure 30-80. ATmega164PA: BOD threshold vs. temperature (VBOT = 4.3V) 4.34 Rising Vcc 4.32 Threshold [V] 4.30 4.28 4.26 Falling Vcc 4.24 4.22 4.20 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 80 90 Temperature [C] Figure 30-81. ATmega164PA: BOD threshold vs. temperature (VBOT = 2.7V) 2.78 Rising Vcc 2.76 Threshold [V] 2.74 2.72 2.70 Falling Vcc 2.68 2.66 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 Temperature [C] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 387 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-82. ATmega164PA: BOD threshold vs. temperature (VBOT = 1.8V) 1.850 Rising Vcc 1.845 1.840 Threshold [V] 1.835 1.830 1.825 1.820 1.815 Falling Vcc 1.810 1.805 1.80 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [C] Figure 30-83. ATmega164PA: Calibrated bandgap voltage vs. VCC 1.109 1.107 Bandgap voltage [V] 1.105 1.103 25C 85C 1.101 1.099 1.097 1.095 1.093 1.091 1.5 -40C 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 388 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-84. ATmega164PA: Bandgap voltage vs. temperature 1.087 1.8V 3.6V 2.7V 4.5V 1.085 Bandgap voltage [V] 1.083 1.081 5.5V 1.079 1.077 1.075 1.073 1.071 1.069 1.067 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [C] 30.2.11 Internal oscillator speed Figure 30-85. ATmega164PA: Watchdog oscillator frequency vs. temperature 134 132 FRC [kHz] 130 128 126 2.1V 2.7V 3.3V 4.0V 5.5V 124 122 120 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [C] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 389 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-86. ATmega164PA: Watchdog oscillator frequency vs. VCC 135 132 FRC [kHz] -40C 129 25C 126 123 85C 120 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-87. ATmega164PA: Calibrated 8MHz RC oscillator vs. VCC 8.4 85C 8.2 FRC [MHz] 8.0 25C 7.8 -40C 7.6 7.4 7.2 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 390 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-88. ATmega164PA: Calibrated 8MHz RC oscillator vs. temperature 8.3 5.0V 3.0V 8.2 FRC [MHz] 8.1 8.0 7.9 7.8 7.7 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [C] Figure 30-89. ATmega164PA: Calibrated 8MHz RC oscillator vs. OSCCAL value 16 85C 25C -40C 14 FRC [MHz] 12 10 8 6 4 2 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL [X1] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 391 ATmega164A/PA/324A/PA/644A/PA/1284/P 30.2.12 Current consumption of peripheral units Figure 30-90. ATmega164PA: ADC current vs. VCC (AREF = AVCC) 320 -40C 85C 25C 280 240 ICC [A] 200 160 120 80 40 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-91. ATmega164PA: Analog comparator current vs. VCC 100 90 -40C 80 25C 85C ICC [A] 70 60 50 40 30 20 10 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 392 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-92. ATmega164PA: AREF external reference current vs. VCC 200 25C 85C -40C ICC [A] 160 120 80 40 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-93. ATmega164PA: Brownout detector current vs. VCC 27 85C 25C -40C 24 21 ICC [A] 18 15 12 9 6 3 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 393 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-94. ATmega164PA: Programming current vs. VCC 12 -40C 25C 85C 10 ICC [mA] 8 6 4 2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-95. ATmega164PA: Watchdog timer current vs. VCC 9 -40C 8 25C 85C 7 ICC [A] 6 5 4 3 2 1 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 394 ATmega164A/PA/324A/PA/644A/PA/1284/P 30.2.13 Current consumption in reset and reset pulsewidth Figure 30-96. ATmega164PA: Reset supply current vs. low frequency (0.1 - 1.0MHz) 0.10 5.5V 0.08 5.0V ICC [mA] 4.5V 0.06 4.0V 3.3V 0.04 2.7V 1.8V 0.02 0 0 0.2 0.4 0.6 0.8 1.0 Frequency [MHz] Figure 30-97. ATmega164PA: Reset supply current vs. frequency (1 - 20MHz) 1.8 5.5V 1.5 5.0V 4.5V ICC [mA] 1.2 0.9 4.0V 0.6 3.3V 0.3 2.7V 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency [MHz] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 395 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-98. ATmega164PA: Minimum reset pulsewidth vs. VCC 1600 1400 Pulsewidth [ns] 1200 1000 800 600 400 85C 25C -40C 200 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 396 ATmega164A/PA/324A/PA/644A/PA/1284/P 30.3 ATmega324A typical characteristics - TA = -40C to 85C 30.3.1 Active supply current Figure 30-99. ATmega324A: Active supply current vs. low frequency (0.1 - 1.0MHz) I CC [mA] 1.2 5.5V 1.0 5.0V 0.8 4.5V 4.0V 0.6 3.3V 2.7V 0.4 1.8V 0.2 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency [MHz] Figure 30-100. ATmega324A: Active supply current vs. frequency (1 - 20MHz) ICC [mA] 14 5.5V 12 5.0V 10 4.5V 8 4.0V 6 3.3V 4 2.7V 2 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency [MHz] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 397 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-101. ATmega324A: Active supply current vs. VCC (internal RC oscillator, 8MHz) 7 85C 25C -40C 6 ICC [mA] 5 4 3 2 1 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-102. ATmega324A: Active supply current vs. VCC (internal RC oscillator, 1MHz) 1.6 85C 25C -40C ICC [mA] 1.2 0.8 0.4 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 398 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-103. ATmega324A: Active supply current vs. VCC (internal RC oscillator, 128kHz) 0.25 -40C 25C 85C ICC [mA] 0.20 0.15 0.10 0.05 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 30.3.2 Idle supply current Figure 30-104. ATmega324A: Idle supply current vs. VCC (0.1 - 1.0MHz) 5.5V 0.25 5.0V 0.20 4.5V ICC [mA] 4.0V 0.15 3.3V 2.7V 0.10 1.8V 0.05 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency [MHz] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 399 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-105. ATmega324A: Idle supply current vs. VCC (1 - 20MHz) 4 5.5V 5.0V 3 ICC [mA] 4.5V 2 4.0V 3.3V 1 2.7V 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency [MHz] Figure 30-106. ATmega324A: Idle supply current vs. VCC (internal RC oscillator, 8MHz) 1.8 85C 25C -40C 1.5 ICC [mA] 1.2 0.9 0.6 0.3 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 400 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-107. ATmega324A: Idle supply current vs. VCC (internal RC oscillator, 1MHz) 85C 25C -40C 0.6 0.5 ICC [mA] 0.4 0.3 0.2 0.1 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-108. ATmega324A: Idle supply current vs. VCC (internal RC oscillator, 128kHz) 0.12 -40C 25C 85C 0.10 ICC [mA] 0.08 0.06 0.04 0.02 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 401 ATmega164A/PA/324A/PA/644A/PA/1284/P 30.3.3 Supply current of I/O modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register. See "PRR0 - Power Reduction Register 0" on page 56 for details. Table 30-5. PRR bit Additional current consumption for the different I/O modules (absolute values) Typical numbers in VCC = 2V, F = 1MHz VCC = 3V, F = 4MHz VCC = 5V, F = 8MHz PRUSART1 3.1A 21.5A 100.0A PRUSART0 3.0A 21.0A 98.2A PRTWI 6.4A 45.7A 214.5A PRTIM2 5.6A 37.7A 165.8A PRTIM1 3.6A 24.8A 107.0A PRTIM0 1.7A 10.4A 43.2A PRADC 11.8A 59.2A 257.0A PRSPI 5.3A 40.1A 206.8A Table 30-6. Additional current consumption (percentage) in Active and Idle mode Additional current consumption compared to Active with external clock (see Figure 30-148 on page 423 and Figure 30-149 on page 423) Additional current consumption compared to Idle with external clock (see Figure 30-153 on page 425 and Figure 30-154 on page 426) PRUSART1 1.4% 5.3% PRUSART0 1.4% 5.2% PRTWI 3.0% 11.3% PRTIM2 2.5% 9.1% PRTIM1 1.6% 6.0% PRTIM0 0.7% 2.5% PRADC 4.2% 14.8% PRSPI 2.7% 10.3% PRR bit It is possible to calculate the typical current consumption based on the numbers from Table 30-8 on page 428 for other VCC and frequency settings than listed in Table 30-7 on page 428. Exam p l e Calculate the expected current consumption in idle mode with TIMER1, ADC, and SPI enabled at VCC = 2.0V and F = 1MHz. From Table 30-8 on page 428, third column, we see that we need to add 6.0% for the TIMER1, 14.8% for the ADC, and 10.3% for the SPI module. Reading from Figure 30-153 on page 425, we find that the idle current consumption is ~0.078mA at VCC = 2.0V and F = 1MHz. The total current consumption in idle mode with TIMER1, ADC, and SPI enabled, gives: I CC total 0.078mA (1+ 0.060 + 0.148 + 0.103) 0.102mA 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 402 ATmega164A/PA/324A/PA/644A/PA/1284/P 30.3.4 Power-down supply current Figure 30-109. ATmega324A: Power-down supply current vs. VCC (watchdog timer disabled) 1.2 85C 1.0 ICC [A] 0.8 0.6 0.4 25C -40C 0.2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-110. ATmega324A: Power-down supply current vs. VCC (watchdog timer enabled) 10 -40C 85C 25C 8 ICC [A] 6 4 2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 403 ATmega164A/PA/324A/PA/644A/PA/1284/P 30.3.5 Power-save supply current Figure 30-111. ATmega324A: Power-save supply current vs. VCC (watchdog timer disabled and 32kHz crystal oscillator running) 2.50 85C ICC [A] 2.00 1.50 25C -40C 1.00 0.50 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 30.3.6 Standby supply current Figure 30-112. ATmega324A: Standby supply current vs. VCC (watchdog timer disabled) 0.18 6MHz_res 6MHz_xtal 0.16 0.14 4MHz_res 4MHz_xtal ICC [mA] 0.12 0.10 2MHz_res 0.08 2MHz_xtal 0.06 450kHz_res 0.04 0.02 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 404 ATmega164A/PA/324A/PA/644A/PA/1284/P 30.3.7 Pin pull-up Figure 30-113. ATmega324A: I/O pin pull-up resistor current vs. input voltage (VCC = 1.8V) 50 40 IOP [A] 30 20 25C -40C 85C 10 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 VOP [V] Figure 30-114. ATmega324A: I/O pin pull-up resistor current vs. input voltage (VCC = 2.7V) 80 70 60 IOP [A] 50 40 30 25C 20 85C 10 -40C 0 0 0.5 1.0 1.5 2.0 2.5 3.0 VOP [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 405 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-115. ATmega324A: I/O pin pull-up resistor current vs. input voltage (VCC = 5V) 140 120 IOP [A] 100 80 60 25C 40 85C 20 -40C 0 0 1 2 3 4 5 6 VOP [V] Figure 30-116. ATmega324A: Reset pull-up resistor current vs. reset pin voltage (VCC = 1.8V) 35 30 IRESET [A] 25 20 15 10 25C 5 -40C 85C 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 VRESET [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 406 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-117. ATmega324A: Reset pull-up resistor current vs. reset pin voltage (VCC = 2.7V) 60 50 IRESET [A] 40 30 20 25C -40C 85C 10 0 0 0.5 1.0 1.5 2.0 2.5 3.0 VRESET [V] Figure 30-118. ATmega324A: Reset pull-up resistor current vs. reset pin voltage (VCC = 5V) 120 100 IRESET [A] 80 60 40 25C 20 -40C 85C 0 0 1 2 3 4 5 6 VRESET [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 407 ATmega164A/PA/324A/PA/644A/PA/1284/P 30.3.8 Pin driver strength Figure 30-119. ATmega324A: I/O pin output voltage vs. sink current (VCC = 3V) 1.0 85C 0.8 25C VOL [V] 0.6 -40C 0.4 0.2 0 5 8 11 14 17 20 IOL [mA] Figure 30-120. ATmega324A: I/O pin output voltage vs. sink current (VCC = 5V) 0.6 85C 0.5 25C VOL [V] 0.4 -40C 0.3 0.2 0.1 0 5 8 11 14 17 20 IOL [mA] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 408 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-121. ATmega324A: I/O pin output voltage vs. source current (VCC = 3V) 3.0 2.5 -40C 25C 85C VOH [V] 2.0 1.5 1.0 0.5 0 5 8 11 14 17 20 IOH [mA] Figure 30-122. ATmega324A: I/O pin output voltage vs. source current (VCC = 5V) 4.9 4.8 VOH [V] 4.7 4.6 -40C 4.5 25C 4.4 85C 4.3 5 8 11 14 17 20 IOH [mA] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 409 ATmega164A/PA/324A/PA/644A/PA/1284/P 30.3.9 Pin threshold and hysteresis Figure 30-123. ATmega324A: I/O pin input threshold vs. VCC (VIH , I/O pin read as `1') 85C 3.0 -40C 25C 2.5 Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-124. ATmega324A: I/O pin input threshold vs. VCC (VIL, I/O pin read as `0') -40C 85C 25C 2.5 Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 410 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-125. ATmega324A: I/O pin input hysteresis vs. VCC 0.6 85C 25C 0.5 Input hysteresis [mV] -40C 0.4 0.3 0.2 0.1 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-126. ATmega324A: Reset pin input , threshold vs. VCC (VIH , I/O pin read as `1') -40C 85C 25C 2.5 Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 411 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-127. ATmega324A: Reset pin input threshold vs. VCC (VIL, I/O pin read as `0') -40C 25C 2.5 85C Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-128. ATmega324A: Reset pin input hysteresis vs. VCC 0.7 Input hysteresis [mV] 0.6 0.5 0.4 0.3 0.2 -40C 25C 85C 0.1 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 412 ATmega164A/PA/324A/PA/644A/PA/1284/P 30.3.10 BOD threshold Figure 30-129. ATmega324A: BOD threshold vs. temperature (VBOT = 4.3V) 4.40 Rising Vcc 4.38 Threshold [V] 4.36 4.34 4.32 Falling Vcc 4.30 4.28 -40 -20 0 20 40 60 80 100 Temperature [C] Figure 30-130. ATmega324A: BOD threshold vs. temperature (VBOT = 2.7V) 2.80 Rising Vcc 2.78 Threshold [V] 2.76 2.74 Falling Vcc 2.72 2.70 2.68 2.66 -40 -20 0 20 40 60 80 100 Temperature [C] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 413 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-131. ATmega324A: BOD threshold vs. temperature (VBOT = 1.8V) 1.86 Rising Vcc Threshold [V] 1.84 1.82 Falling Vcc 1.80 1.78 1.76 -40 -20 0 20 40 60 80 100 Temperature [C] Figure 30-132. ATmega324A: Calibrated bandgap voltage vs. VCC 1.098 1.096 Bandgap voltage [V] 1.094 1.092 85C 25C 1.090 1.088 1.086 1.084 1.082 1.080 -40C 1.078 1.076 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Vcc [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 414 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-133. ATmega324A: Bandgap voltage vs. temperature 1.097 1.8V 3.6V 2.7V 4.5V 1.095 Bandgap voltage [V] 1.093 1.091 5.5V 1.089 1.087 1.085 1.083 1.081 1.079 1.077 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [C] 30.3.11 Internal oscillator speed Figure 30-134. ATmega324A: Watchdog oscillator frequency vs. temperature 122 FRC [kHz] 119 116 2.1V 2.7V 3.3V 4.0V 5.5V 113 110 -40 -20 0 20 40 60 80 100 Temperature [C] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 415 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-135. ATmega324A: Watchdog oscillator frequency vs. VCC 123 -40C FRC [kHz] 120 25C 117 114 85C 111 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-136. ATmega324A: Calibrated 8MHz RC oscillator vs. VCC 8.6 85C 8.2 FRC [MHz] 25C 7.8 -40C 7.4 7.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 416 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-137. ATmega324A: Calibrated 8MHz RC oscillator vs. temperature 8.6 5.0V 3.0V FRC [MHz] 8.3 8.0 7.7 7.4 -40 -20 0 20 40 60 80 100 Temperature [C] Figure 30-138. ATmega324A: Calibrated 8MHz RC oscillator vs. OSCCAL value 16 85C 25C -40C 14 12 FRC [MHz] 10 8 6 4 2 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL (X1) 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 417 ATmega164A/PA/324A/PA/644A/PA/1284/P 30.3.12 Current consumption of peripheral units Figure 30-139. ATmega324A: ADC current vs. VCC (AREF = AVCC) 300 25C 85C -40C 250 ICC [A] 200 150 100 50 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-140. ATmega324A: Analog comparator current vs. VCC 90 -40C 80 25C 70 85C ICC [A] 60 50 40 30 20 10 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 418 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-141. ATmega324A: AREF external reference current vs. VCC 25C 85C -40C 200 160 ICC [A] 120 80 40 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-142. ATmega324A: Brownout detector current vs. VCC 25 85C 25C -40C 20 ICC [A] 15 10 5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 419 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-143. ATmega324A: Programming current vs. VCC 14 25C -40C 85C 12 ICC [mA] 10 8 6 4 2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-144. ATmega324A: Watchdog timer current vs. VCC 9 -40C 25C 85C ICC [A] 7 5 3 1 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 420 ATmega164A/PA/324A/PA/644A/PA/1284/P 30.3.13 Current consumption in reset and reset pulsewidth Figure 30-145. ATmega324A: Reset supply current vs. low frequency (0.1 - 1.0MHz) 0.14 5.5V 0.12 5.0V 0.10 I CC [mA] 4.5V 0.08 4.0V 0.06 3.3V 2.7V 0.04 1.8V 0.02 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency [MHz] Figure 30-146. ATmega324A: Reset supply current vs. frequency (1 - 20MHz) 2.5 5.5V 2.0 5.0V 4.5V I CC [mA] 1.5 4.0V 1.0 3.3V 0.5 2.7V 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency [MHz] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 421 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-147. ATmega324A: Minimum reset pulsewidth vs. VCC 1800 1500 Pulsewidth [ns] 1200 900 600 85C 25C -40C 300 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 V CC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 422 ATmega164A/PA/324A/PA/644A/PA/1284/P 30.4 ATmega324PA typical characteristics - TA = -40C to 85C 30.4.1 Active supply current Figure 30-148. ATmega324PA: Active supply current vs. low frequency (0.1 - 1.0MHz) I CC [mA] 1.2 5.5V 1.0 5.0V 0.8 4.5V 4.0V 0.6 3.3V 2.7V 0.4 1.8V 0.2 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency [MHz] Figure 30-149. ATmega324PA: Active supply current vs. frequency (1 - 20MHz) ICC [mA] 14 5.5V 12 5.0V 10 4.5V 8 4.0V 6 3.3V 4 2.7V 2 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency [MHz] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 423 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-150. ATmega324PA: Active supply current vs. VCC (internal RC oscillator, 8MHz) 7 85C 25C -40C 6 ICC [mA] 5 4 3 2 1 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-151. ATmega324PA: Active supply current vs. VCC (internal RC oscillator, 1MHz) 1.6 85C 25C -40C ICC [mA] 1.2 0.8 0.4 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 424 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-152. ATmega324PA: Active supply current vs. VCC (internal RC oscillator, 128kHz) 0.25 -40C 25C 85C ICC [mA] 0.20 0.15 0.10 0.05 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 30.4.2 Idle supply current Figure 30-153. ATmega324PA: Idle supply current vs. VCC (0.1 - 1.0MHz) 5.5V 0.25 5.0V 0.20 4.5V ICC [mA] 4.0V 0.15 3.3V 2.7V 0.10 1.8V 0.05 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency [MHz] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 425 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-154. ATmega324PA: Idle supply current vs. VCC (1 - 20MHz) 4 5.5V 5.0V 3 ICC [mA] 4.5V 2 4.0V 3.3V 1 2.7V 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency [MHz] Figure 30-155. ATmega324PA: Idle supply current vs. VCC (internal RC oscillator, 8MHz) 1.8 85C 25C -40C 1.5 ICC [mA] 1.2 0.9 0.6 0.3 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 426 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-156. ATmega324PA: Idle supply current vs. VCC (internal RC oscillator, 1MHz) 85C 25C -40C 0.6 0.5 ICC [mA] 0.4 0.3 0.2 0.1 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-157. ATmega324PA: Idle supply current vs. VCC (internal RC oscillator, 128kHz) 0.12 -40C 25C 85C 0.10 ICC [mA] 0.08 0.06 0.04 0.02 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 427 ATmega164A/PA/324A/PA/644A/PA/1284/P 30.4.3 Supply current of I/O modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register. See "PRR0 - Power Reduction Register 0" on page 56 for details. Table 30-7. PRR bit Additional current consumption for the different I/O modules (absolute values) Typical numbers in VCC = 2V, F = 1MHz VCC = 3V, F = 4MHz VCC = 5V, F = 8MHz PRUSART1 3.1A 21.5A 100.0A PRUSART0 3.0A 21.0A 98.2A PRTWI 6.4A 45.7A 214.5A PRTIM2 5.6A 37.7A 165.8A PRTIM1 3.6A 24.8A 107.0A PRTIM0 1.7A 10.4A 43.2A PRADC 11.8A 59.2A 257.0A PRSPI 5.3A 40.1A 206.8A Table 30-8. Additional current consumption (percentage) in Active and Idle mode Additional current consumption compared to Active with external clock (see Figure 30-148 on page 423 and Figure 30-149 on page 423) Additional current consumption compared to Idle with external clock (see Figure 30-153 on page 425 and Figure 30-154 on page 426) PRUSART1 1.4% 5.3% PRUSART0 1.4% 5.2% PRTWI 3.0% 11.3% PRTIM2 2.5% 9.1% PRTIM1 1.6% 6.0% PRTIM0 0.7% 2.5% PRADC 4.2% 14.8% PRSPI 2.7% 10.3% PRR bit It is possible to calculate the typical current consumption based on the numbers from Table 30-8 on page 428 for other VCC and frequency settings than listed in Table 30-7 on page 428. Exam p l e Calculate the expected current consumption in idle mode with TIMER1, ADC, and SPI enabled at VCC = 2.0V and F = 1MHz. From Table 30-8 on page 428, third column, we see that we need to add 6.0% for the TIMER1, 14.8% for the ADC, and 10.3% for the SPI module. Reading from Figure 30-153 on page 425, we find that the idle current consumption is ~0.078mA at VCC = 2.0V and F = 1MHz. The total current consumption in idle mode with TIMER1, ADC, and SPI enabled, gives: I CC total 0.078mA (1+ 0.060 + 0.148 + 0.103) 0.102mA 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 428 ATmega164A/PA/324A/PA/644A/PA/1284/P 30.4.4 Power-down Supply Current Figure 30-158. ATmega324PA: Power-down supply current vs. VCC (watchdog timer disabled) 1.2 85C 1.0 ICC [A] 0.8 0.6 0.4 25C -40C 0.2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-159. ATmega324PA: Power-down supply current vs. VCC (watchdog timer enabled) 10 -40C 85C 25C 8 ICC [A] 6 4 2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 429 ATmega164A/PA/324A/PA/644A/PA/1284/P 30.4.5 Power-save supply current Figure 30-160. ATmega324PA: Power-save supply current vs. VCC (watchdog timer disabled and 32kHz crystal oscillator running) 2.50 85C ICC [A] 2.00 1.50 25C -40C 1.00 0.50 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 30.4.6 Standby supply current Figure 30-161. ATmega324PA: Standby supply current vs. VCC (watchdog timer disabled) 0.18 6MHz_res 6MHz_xtal 0.16 0.14 4MHz_res 4MHz_xtal ICC [mA] 0.12 0.10 2MHz_res 0.08 2MHz_xtal 0.06 450kHz_res 0.04 0.02 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 430 ATmega164A/PA/324A/PA/644A/PA/1284/P 30.4.7 Pin pull-up Figure 30-162. ATmega324PA: I/O pin pull-up resistor current vs. input voltage (VCC = 1.8V) 50 40 IOP [A] 30 20 25C -40C 85C 10 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 VOP [V] Figure 30-163. ATmega324PA: I/O pin pull-up resistor current vs. input voltage (VCC = 2.7V) 80 70 60 IOP [A] 50 40 30 25C 20 85C 10 -40C 0 0 0.5 1.0 1.5 2.0 2.5 3.0 VOP [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 431 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-164. ATmega324PA: I/O pin pull-up resistor current vs. input voltage (VCC = 5V) 140 120 IOP [A] 100 80 60 25C 40 85C 20 -40C 0 0 1 2 3 4 5 6 VOP [V] Figure 30-165. ATmega324PA: Reset pull-up resistor current vs. reset pin voltage (VCC = 1.8V) 35 30 IRESET [A] 25 20 15 10 25C 5 -40C 85C 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 VRESET [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 432 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-166. ATmega324PA: Reset pull-up resistor current vs. reset pin voltage (VCC = 2.7V) 60 50 IRESET [A] 40 30 20 25C -40C 85C 10 0 0 0.5 1.0 1.5 2.0 2.5 3.0 VRESET [V] Figure 30-167. ATmega324PA: Reset pull-up resistor current vs. reset pin voltage (VCC = 5V) 120 100 IRESET [A] 80 60 40 25C 20 -40C 85C 0 0 1 2 3 4 5 6 VRESET [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 433 ATmega164A/PA/324A/PA/644A/PA/1284/P 30.4.8 Pin driver strength Figure 30-168. ATmega324PA: I/O pin output voltage vs. sink current (VCC = 3V) 1.0 85C 0.8 25C VOL [V] 0.6 -40C 0.4 0.2 0 5 8 11 14 17 20 IOL [mA] Figure 30-169. ATmega324PA: I/O pin output voltage vs. sink current (VCC = 5V) 0.6 85C 0.5 25C VOL [V] 0.4 -40C 0.3 0.2 0.1 0 5 8 11 14 17 20 IOL [mA] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 434 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-170. ATmega324PA: I/O pin output voltage vs. source current (VCC = 3V) 3.0 2.5 -40C 25C 85C VOH [V] 2.0 1.5 1.0 0.5 0 5 8 11 14 17 20 IOH [mA] Figure 30-171. ATmega324PA: I/O pin output voltage vs. source current (VCC = 5V) 4.9 4.8 VOH [V] 4.7 4.6 -40C 4.5 25C 4.4 85C 4.3 5 8 11 14 17 20 IOH [mA] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 435 ATmega164A/PA/324A/PA/644A/PA/1284/P 30.4.9 Pin threshold and hysteresis Figure 30-172. ATmega324PA: I/O pin input threshold vs. VCC (VIH , I/O pin read as `1') 85C 3.0 -40C 25C 2.5 Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-173. ATmega324PA: I/O pin input threshold vs. VCC (VIL, I/O pin read as `0') -40C 85C 25C 2.5 Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 436 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-174. ATmega324PA: I/O pin input hysteresis vs. VCC 0.6 85C 25C 0.5 Input hysteresis [mV] -40C 0.4 0.3 0.2 0.1 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-175. ATmega324PA: Reset pin input threshold vs. VCC (VIH , I/O pin read as `1') , -40C 85C 25C 2.5 Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 437 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-176. ATmega324PA: Reset pin input threshold vs. VCC (VIL, I/O pin read as `0') -40C 25C 2.5 85C Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-177. ATmega324PA: Reset pin input hysteresis vs. VCC 0.7 Input hysteresis [mV] 0.6 0.5 0.4 0.3 0.2 -40C 25C 85C 0.1 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 438 ATmega164A/PA/324A/PA/644A/PA/1284/P 30.4.10 BOD threshold Figure 30-178. ATmega324PA: BOD threshold vs. temperature (VBOT = 4.3V). 4.40 Rising Vcc 4.38 Threshold [V] 4.36 4.34 4.32 Falling Vcc 4.30 4.28 -40 -20 0 20 40 60 80 100 Temperature [C] Figure 30-179. ATmega324PA: BOD threshold vs. temperature (VBOT = 2.7V) 2.80 Rising Vcc 2.78 Threshold [V] 2.76 2.74 Falling Vcc 2.72 2.70 2.68 2.66 -40 -20 0 20 40 60 80 100 Temperature [C] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 439 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-180. ATmega324PA: BOD threshold vs. temperature (VBOT = 1.8V) 1.86 Rising Vcc Threshold [V] 1.84 1.82 Falling Vcc 1.80 1.78 1.76 -40 -20 0 20 40 60 80 100 Temperature [C] Figure 30-181. ATmega324PA: Calibrated bandgap voltage vs. VCC 1.098 1.096 Bandgap voltage [V] 1.094 1.092 85C 25C 1.090 1.088 1.086 1.084 1.082 1.080 -40C 1.078 1.076 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Vcc [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 440 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-182. ATmega324PA: Bandgap voltage vs. temperature 1.097 1.8V 3.6V 2.7V 4.5V 1.095 Bandgap voltage [V] 1.093 1.091 5.5V 1.089 1.087 1.085 1.083 1.081 1.079 1.077 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [C] 30.4.11 Internal oscillator speed Figure 30-183. ATmega324PA: Watchdog oscillator frequency vs. temperature 122 FRC [kHz] 119 116 2.1V 2.7V 3.3V 4.0V 5.5V 113 110 -40 -20 0 20 40 60 80 100 Temperature [C] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 441 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-184. ATmega324PA: Watchdog oscillator frequency vs. VCC 123 -40C FRC [kHz] 120 25C 117 114 85C 111 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-185. ATmega324PA: Calibrated 8MHz RC oscillator vs. VCC 8.6 85C 8.2 FRC [MHz] 25C 7.8 -40C 7.4 7.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 442 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-186. ATmega324PA: Calibrated 8MHz RC oscillator vs. temperature 8.6 5.0V 3.0V FRC [MHz] 8.3 8.0 7.7 7.4 -40 -20 0 20 40 60 80 100 Temperature [C] Figure 30-187. ATmega324PA: Calibrated 8MHz RC oscillator vs. OSCCAL value 16 85C 25C -40C 14 12 FRC [MHz] 10 8 6 4 2 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL (X1) 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 443 ATmega164A/PA/324A/PA/644A/PA/1284/P 30.4.12 Current consumption of peripheral units Figure 30-188. ATmega324PA: ADC current vs. VCC (AREF = AVCC) 300 25C 85C -40C 250 ICC [A] 200 150 100 50 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-189. ATmega324PA: Analog comparator current vs. VCC 90 -40C 80 25C 70 85C ICC [A] 60 50 40 30 20 10 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 444 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-190. ATmega324PA: AREF external reference current vs. VCC 25C 85C -40C 200 160 ICC [A] 120 80 40 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-191. ATmega324PA: Brownout detector current vs. VCC 25 85C 25C -40C 20 ICC [A] 15 10 5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 445 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-192. ATmega324PA: Programming current vs. VCC 14 25C -40C 85C 12 ICC [mA] 10 8 6 4 2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-193. ATmega324PA: Watchdog timer current vs. VCC 9 -40C 25C 85C ICC [A] 7 5 3 1 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 446 ATmega164A/PA/324A/PA/644A/PA/1284/P 30.4.13 Current consumption in reset and reset pulsewidth Figure 30-194. ATmega324PA: Reset supply current vs. low frequency (0.1 - 1.0MHz) 0.14 5.5V 0.12 5.0V 0.10 I CC [mA] 4.5V 0.08 4.0V 0.06 3.3V 2.7V 0.04 1.8V 0.02 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency [MHz] Figure 30-195. ATmega324PA: Reset supply current vs. frequency (1 - 20MHz) 2.5 5.5V 2.0 5.0V 4.5V I CC [mA] 1.5 4.0V 1.0 3.3V 0.5 2.7V 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency [MHz] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 447 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-196. ATmega324PA: Minimum reset pulsewidth vs. VCC 1800 1500 Pulsewidth [ns] 1200 900 600 85C 25C -40C 300 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 V CC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 448 ATmega164A/PA/324A/PA/644A/PA/1284/P 30.5 ATmega644A typical characteristics - TA = -40C to 85C 30.5.1 Active supply current Figure 30-197. ATmega644A: Active supply current vs. low frequency (0.1 - 1.0MHz) 1.2 5.5V 1.0 5.0V 4.5V ICC [mA] 0.8 4.0V 0.6 3.3V 2.7V 0.4 1.8V 0.2 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency [MHz] Figure 30-198. ATmega644A: Active supply current vs. frequency (1 - 20MHz) ICC [mA] 14 5.5V 12 5.0V 10 4.5V 8 4.0V 6 3.3V 4 2.7V 2 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency [MHz] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 449 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-199. ATmega644A: Active supply current vs. VCC (internal RC oscillator, 8MHz) 7 85C 25C -40C 6 ICC [mA] 5 4 3 2 1 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-200. ATmega644A: Active supply current vs. VCC (internal RC oscillator, 1MHz) 1.4 85C 25C -40C 1.2 ICC [mA] 1.0 0.8 0.6 0.4 0.2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 450 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-201. ATmega644A: Active supply current vs. VCC (internal RC oscillator, 128kHz) 0.22 -40C 25C 85C 0.20 0.18 ICC [mA] 0.16 0.14 0.12 0.10 0.08 0.06 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 30.5.2 Idle supply current Figure 30-202. ATmega644A: Idle supply current vs. VCC (0.1 - 1.0MHz) 0.24 5.5V 0.20 5.0V 4.5V 4.0V ICC [mA] 0.16 3.3V 2.7V 0.12 0.08 1.8V 0.04 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency [MHz] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 451 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-203. ATmega644A: Idle supply current vs. VCC (1 - 20MHz) 3.0 5.5V 5.0V 2.5 4.5V ICC [mA] 2.0 4.0V 1.5 1.0 3.3V 2.7V 0.5 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency [MHz] Figure 30-204. ATmega644A: Idle supply current vs. VCC (internal RC oscillator, 8MHz) 1.4 85C 25C -40C 1.2 ICC [mA] 1.0 0.8 0.6 0.4 0.2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 452 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-205. ATmega644A: Idle supply current vs. VCC (internal RC oscillator, 1MHz) 0.35 85C 25C -40C 0.30 ICC [mA] 0.25 0.20 0.15 0.10 0.05 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-206. ATmega644A: Idle supply current vs. VCC (internal RC oscillator, 128kHz) 0.12 -40C 25C 85C 0.10 ICC [mA] 0.08 0.06 0.04 0.02 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 453 ATmega164A/PA/324A/PA/644A/PA/1284/P 30.5.3 Supply current of I/O modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register. See "PRR0 - Power Reduction Register 0" on page 56 for details. Table 30-9. PRR bit Additional Current Consumption for the different I/O modules (absolute values) Typical numbers in VCC = 2V, F = 1MHz VCC = 3V, F = 4MHz VCC = 5V, F = 8MHz PRUSART1 5.9A 37.3A 149A PRUSART0 6.7A 40A 157.1A PRTWI 9.5A 58.9A 239.5A PRTIM2 12A 74.3A 297.6A PRTIM1 6.6A 41.4A 170.3A PRTIM0 3.1A 19.5A 78.6A PRADC 16.2A 75.4A 301.4A PRSPI 9.3A 56.6A 226.3A Table 30-10. Additional current consumption (percentage) in Active and Idle mode Additional current consumption compared to Active with external clock (see Figure 30-246 on page 475 and Figure 30-247 on page 475) Additional current consumption compared to Idle with external clock (see Figure 30-251 on page 477 and Figure 30-252 on page 478) PRUSART1 1.6% 8.1% PRUSART0 1.8% 8.8% PRTWI 2.6% 12.9% PRTIM2 3.3% 16.3% PRTIM1 1.9% 9.1% PRTIM0 0.9% 4.3% PRADC 3.65% 17.9% PRSPI 2.5% 12.4% PRR bit It is possible to calculate the typical current consumption based on the numbers from Table 30-12 on page 480 for other VCC and frequency settings than listed in Table 30-11 on page 480. Exam p l e Calculate the expected current consumption in idle mode with TIMER1, ADC, and SPI enabled at VCC = 2.0V and F = 1MHz. From Table 30-12 on page 480, third column, we see that we need to add 9.1% for the TIMER1, 17.9% for the ADC, and 12.4% for the SPI module. Reading from Figure 30-251 on page 477, we find that the idle current consumption is ~0.078mA at VCC = 2.0V and F = 1MHz. The total current consumption in idle mode with TIMER1, ADC, and SPI enabled, gives: I CC total 0.070mA (1+ 0.091 + 0.179 + 0.124) 0.091mA 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 454 ATmega164A/PA/324A/PA/644A/PA/1284/P 30.5.4 Power-down supply current Figure 30-207. ATmega644A: Power-down supply current vs. VCC (watchdog timer disabled) 2.5 85C 2.0 ICC [A] 1.5 1.0 0.5 25C -40C 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-208. ATmega644A: Power-down supply current vs. VCC (watchdog timer enabled) 9 85C 8 -40C 25C ICC [A] 7 6 5 4 3 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 455 ATmega164A/PA/324A/PA/644A/PA/1284/P 30.5.5 Power-save supply current Figure 30-209. ATmega644A: Power-save supply current vs. VCC (watchdog timer disabled and 32kHz crystal oscillator running) 2.5 85C 2.0 Icc [A] 1.5 1.0 0.5 25C -40C 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 30.5.6 Standby supply current Figure 30-210. ATmega644A: Standby supply current vs. VCC (watchdog timer disabled) 0.16 6MHz_res 6MHz_xtal 0.14 4MHz_res 0.12 4MHz_xtal ICC [mA] 0.10 0.08 2MHz_res 0.06 2MHz_xtal 1MHz_res 450kHz_res 0.04 0.02 0 1.7 2.2 2.7 3.2 3.7 4.2 4.7 5.2 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 456 ATmega164A/PA/324A/PA/644A/PA/1284/P 30.5.7 Pin pull-up Figure 30-211. ATmega644A: I/O pin pull-up resistor current vs. input voltage (VCC = 1.8V) 50 45 40 35 IOP [A] 30 25 20 15 10 25C 85C -40C 5 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 VOP [V] Figure 30-212. ATmega644A: I/O pin pull-up resistor current vs. input voltage (VCC = 2.7V) 80 70 60 IOP [A] 50 40 30 20 25C 85C -40C 10 0 0 0.5 1.0 1.5 2.0 2.5 3.0 VOP [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 457 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-213. ATmega644A: I/O pin pull-up resistor current vs. input voltage (VCC = 5V) 140 120 IOP [A] 100 80 60 40 25C 85C -40C 20 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VOP [V] Figure 30-214. ATmega644A: g Reset pull-uppresistor current vs. reset pin g (voltage (V ) CC = 1.8V) 35 30 IRESET [A] 25 20 15 10 25C -40C 85C 5 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 VRESET [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 458 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-215. ATmega644A: Reset pull-up resistor current vs. reset pin voltage (VCC = 2.7V) 60 50 IRESET [A] 40 30 20 25C -40C 85C 10 0 0 0.5 1.0 1.5 2.0 2.5 3.0 VRESET [V] Figure 30-216. ATmega644A: Reset pull-up resistor current vs. reset pin voltage (VCC = 5V) 120 100 IRESET [A] 80 60 40 25C -40C 85C 20 0 0 1 2 3 4 5 VRESET [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 459 ATmega164A/PA/324A/PA/644A/PA/1284/P 30.5.8 Pin driver strength Figure 30-217. ATmega644A: I/O pin output voltage vs. sink current (VCC = 3V) 0.9 85C 0.8 0.7 25C 0.6 VOL [V] -40C 0.5 0.4 0.3 0.2 0.1 0 0 2 4 6 8 10 12 14 16 18 20 IOL [mA] Figure 30-218. ATmega644A: I/O pin output voltage vs. sink current (VCC = 5V) 0.6 85C 0.5 25C VOL [V] 0.4 -40C 0.3 0.2 0.1 0 0 2 4 6 8 10 12 14 16 18 20 IOL [mA] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 460 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-219. ATmega644A: I/O pin output voltage vs. source current (VCC = 3V) 3.5 3.0 VOH [V] 2.5 -40C 25C 85C 2.0 1.5 1.0 0.5 0 0 2 4 6 8 10 12 14 16 18 20 IOH [mA] Figure 30-220. ATmega644A: I/O pin output voltage vs. source current (VCC = 5V) 5.1 5.0 4.9 VOH [V] 4.8 4.7 4.6 -40C 4.5 25C 4.4 85C 4.3 0 2 4 6 8 10 12 14 16 18 20 IOH [mA] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 461 ATmega164A/PA/324A/PA/644A/PA/1284/P 30.5.9 Pin threshold and hysteresis Figure 30-221. ATmega644A: I/O pin input threshold vs. VCC (VIH , I/O pin read as `1') 3.0 85C -40C 25C 2.5 Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-222. ATmega644A: I/O pin input threshold vs. VCC (VIL, I/O pin read as `0') 2.5 85C 25C -40C Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 462 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-223. ATmega644A: I/O pin input hysteresis vs. VCC 0.60 25C 85C -40C 0.55 Input Hysteresis [mV] 0.50 0.45 0.40 0.35 0.30 0.25 0.20 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-224. ATmega644A: Reset pin input threshold vs. VCC (VIH , I/O pin read as `1') 2.5 -40C 25C 85C Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 463 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-225. ATmega644A: Reset pin input threshold vs. VCC (VIL, I/O pin read as `0') 2.5 85C 25C -40C Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-226. ATmega644A: Reset pin input hysteresis vs. VCC 0.7 Input hysteresis [mV] 0.6 0.5 0.4 0.3 0.2 -40C 25C 85C 0.1 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 464 ATmega164A/PA/324A/PA/644A/PA/1284/P 30.5.10 BOD threshold Figure 30-227. ATmega644A: BOD threshold vs. temperature (VBOT = 4.3V) 4.35 Rising Vcc Threshold [V] 4.32 4.29 Falling Vcc 4.26 4.23 4.20 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 80 90 100 Temperature [C] Figure 30-228. ATmega644A: BOD threshold vs. temperature (VBOT = 2.7V) 2.77 Rising Vcc 2.75 Threshold [V] 2.73 2.71 Falling Vcc 2.69 2.67 2.65 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 Temperature [C] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 465 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-229. ATmega644A: BOD threshold vs. temperature (VBOT = 1.8V) 1.84 1.83 Rising Vcc Threshold [V] 1.82 1.81 1.80 Falling Vcc 1.79 1.78 1.77 1.76 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 Temperature [C] Figure 30-230. ATmega644A: Calibrated bandgap voltage vs. VCC 1.086 1.084 Bandgap voltage [V] 1.082 85C 25C 1.080 1.078 1.076 1.074 1.072 1.070 1.068 1.066 1.5 -40C 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 466 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-231. ATmega644A: Bandgap voltage vs. temperature 1.087 1.8V 3.6V 2.7V 4.5V 1.085 Bandgap voltage [V] 1.083 1.081 5.5V 1.079 1.077 1.075 1.073 1.071 1.069 1.067 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [C] 30.5.11 Internal oscillator speed Figure 30-232. ATmega644A: Watchdog oscillator frequency vs. temperature 119 118 117 116 FRC [kHz] 115 114 113 2.1V 112 2.7V 3.3V 4.0V 5.5V 111 110 109 108 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 Temperature [C] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 467 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-233. ATmega644A: Watchdog oscillator frequency vs. VCC 119 118 117 -40C 116 FRC [kHz] 115 25C 114 113 112 111 110 85C 109 108 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-234. ATmega644A: Calibrated 8MHz RC oscillator vs. VCC 8.4 85C 8.2 25C FRC [MHz] 8.0 -40C 7.8 7.6 7.4 7.2 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 468 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-235. ATmega644A: Calibrated 8MHz RC oscillator vs. temperature 8.4 5.0V 8.3 3.0V 8.2 FRC [MHz] 8.1 8.0 7.9 7.8 7.7 7.6 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 Temperature [C] Figure 30-236. ATmega644A: Calibrated 8MHz RC oscillator vs. OSCCAL value 16 85C 25C -40C 14 12 FRC [MHz] 10 8 6 4 2 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 OSCCAL [X1] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 469 ATmega164A/PA/324A/PA/644A/PA/1284/P 30.5.12 Current consumption of peripheral units Figure 30-237. ATmega644A: ADC current vs. VCC (AREF = AVCC) 250 25C 85C -40C 200 ICC [A] 150 100 50 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VCC [V] Figure 30-238. ATmega644A: Analog comparator current vs. VCC 90 -40C 80 25C 85C ICC [A] 70 60 50 40 30 20 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 470 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-239. ATmega644A: AREF external reference current vs. VCC 200 25C 85C -40C 160 ICC [A] 120 80 40 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-240. ATmega644A: Brownout detector current vs. VCC 24 85C 22 25C -40C ICC [A] 20 18 16 14 12 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 471 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-241. ATmega644A: Programming current vs. VCC -40C 16 14 12 ICC [mA] 10 25C 8 85C 6 4 2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-242. ATmega644A: Watchdog timer current vs. VCC 9 8 -40C 7 25C 85C ICC [A] 6 5 4 3 2 1 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 472 ATmega164A/PA/324A/PA/644A/PA/1284/P 30.5.13 Current consumption in reset and reset pulsewidth Figure 30-243. ATmega644A: Reset supply current vs. low frequency (0.1 - 1.0MHz) 0.10 5.5V 5.0V 0.08 ICC [mA] 4.5V 4.0V 0.06 3.3V 0.04 2.7V 1.8V 0.02 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency [MHz] Figure 30-244. ATmega644A: Reset supply current vs. frequency (1 - 20MHz) 2.00 5.5V 1.75 5.0V 1.50 4.5V ICC [mA] 1.25 1.00 4.0V 0.75 3.3V 0.50 2.7V 0.25 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency [MHz] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 473 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-245. ATmega644A: Minimum reset pulsewidth vs. VCC 1800 1600 Pulsewidth [ns] 1400 1200 1000 800 600 85C 25C -40C 400 200 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 474 ATmega164A/PA/324A/PA/644A/PA/1284/P 30.6 ATmega644PA typical characteristics - TA = -40C to 85C 30.6.1 Active supply current Figure 30-246. ATmega644PA: Active supply current vs. low frequency (0.1 - 1.0MHz) 1.2 5.5V 1.0 5.0V 4.5V ICC [mA] 0.8 4.0V 0.6 3.3V 2.7V 0.4 1.8V 0.2 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency [MHz] Figure 30-247. ATmega644PA: Active supply current vs. frequency (1 - 20MHz) ICC [mA] 14 5.5V 12 5.0V 10 4.5V 8 4.0V 6 3.3V 4 2.7V 2 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency [MHz] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 475 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-248. ATmega644PA: Active supply current vs. VCC (internal RC oscillator, 8MHz) 7 85C 25C -40C 6 ICC [mA] 5 4 3 2 1 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-249. ATmega644PA: Active supply current vs. VCC (internal RC oscillator, 1MHz) 1.4 85C 25C -40C 1.2 ICC [mA] 1.0 0.8 0.6 0.4 0.2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 476 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-250. ATmega644PA: Active supply current vs. VCC (internal RC oscillator, 128kHz) 0.22 -40C 25C 85C 0.20 0.18 ICC [mA] 0.16 0.14 0.12 0.10 0.08 0.06 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 30.6.2 Idle supply current Figure 30-251. ATmega644PA: Idle supply current vs. VCC (0.1 - 1.0MHz) 0.24 5.5V 0.20 5.0V 4.5V 4.0V ICC [mA] 0.16 3.3V 2.7V 0.12 0.08 1.8V 0.04 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency [MHz] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 477 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-252. ATmega644PA: Idle supply current vs. VCC (1 - 20MHz) 3.0 5.5V 5.0V 2.5 4.5V ICC [mA] 2.0 4.0V 1.5 1.0 3.3V 2.7V 0.5 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency [MHz] Figure 30-253. ATmega644PA: Idle supply current vs. VCC (internal RC oscillator, 8MHz) 1.4 85C 25C -40C 1.2 ICC [mA] 1.0 0.8 0.6 0.4 0.2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 478 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-254. ATmega644PA: Idle supply current vs. VCC (internal RC oscillator, 1MHz) 0.35 85C 25C -40C 0.30 ICC [mA] 0.25 0.20 0.15 0.10 0.05 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-255. ATmega644PA: Idle supply current vs. VCC (internal RC oscillator, 128kHz) 0.12 -40C 25C 85C 0.10 ICC [mA] 0.08 0.06 0.04 0.02 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 479 ATmega164A/PA/324A/PA/644A/PA/1284/P 30.6.3 Supply current of I/O modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register. See "PRR0 - Power Reduction Register 0" on page 56 for details. Table 30-11. PRR bit Additional current consumption for the different I/O modules (absolute values) Typical numbers in VCC = 2V, F = 1MHz VCC = 3V, F = 4MHz VCC = 5V, F = 8MHz PRUSART1 5.9A 37.3A 149A PRUSART0 6.7A 40A 157.1A PRTWI 9.5A 58.9A 239.5A PRTIM2 12A 74.3A 297.6A PRTIM1 6.6A 41.4A 170.3A PRTIM0 3.1A 19.5A 78.6A PRADC 16.2A 75.4A 301.4A PRSPI 9.3A 56.6A 226.3A Table 30-12. Additional current consumption (percentage) in Active and Idle mode Additional current consumption compared to Active with external clock (see Figure 30-246 on page 475 and Figure 30-247 on page 475) Additional current consumption compared to Idle with external clock (see Figure 30-251 on page 477 and Figure 30-252 on page 478) PRUSART1 1.6% 8.1% PRUSART0 1.8% 8.8% PRTWI 2.6% 12.9% PRTIM2 3.3% 16.3% PRTIM1 1.9% 9.1% PRTIM0 0.9% 4.3% PRADC 3.65% 17.9% PRSPI 2.5% 12.4% PRR bit It is possible to calculate the typical current consumption based on the numbers from Table 30-12 on page 480 for other VCC and frequency settings than listed in Table 30-11 on page 480. Exam p l e Calculate the expected current consumption in idle mode with TIMER1, ADC, and SPI enabled at VCC = 2.0V and F = 1MHz. From Table 30-12 on page 480, third column, we see that we need to add 9.1% for the TIMER1, 17.9% for the ADC, and 12.4% for the SPI module. Reading from Figure 30-251 on page 477, we find that the idle current consumption is ~0.078mA at VCC = 2.0V and F = 1MHz. The total current consumption in idle mode with TIMER1, ADC, and SPI enabled, gives: I CC total 0.070mA (1+ 0.091 + 0.179 + 0.124) 0.091mA 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 480 ATmega164A/PA/324A/PA/644A/PA/1284/P 30.6.4 Power-down supply current Figure 30-256. ATmega644PA: Power-down supply current vs. VCC (watchdog timer disabled) 2.5 85C 2.0 ICC [A] 1.5 1.0 0.5 25C -40C 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-257. ATmega644PA: Power-down supply current vs. VCC (watchdog timer enabled) 9 85C 8 -40C 25C ICC [A] 7 6 5 4 3 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 481 ATmega164A/PA/324A/PA/644A/PA/1284/P 30.6.5 Power-save supply current Figure 30-258. ATmega644PA: Power-save supply current vs. VCC (watchdog timer disabled and 32kHz crystal oscillator running) 2.5 85C 2.0 Icc [A] 1.5 1.0 0.5 25C -40C 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 30.6.6 Standby supply current Figure 30-259. ATmega644PA: Standby supply current vs. VCC (watchdog timer disabled) 0.16 6MHz_res 6MHz_xtal 0.14 4MHz_res 0.12 4MHz_xtal ICC [mA] 0.10 0.08 2MHz_res 0.06 2MHz_xtal 1MHz_res 450kHz_res 0.04 0.02 0 1.7 2.2 2.7 3.2 3.7 4.2 4.7 5.2 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 482 ATmega164A/PA/324A/PA/644A/PA/1284/P 30.6.7 Pin pull-up Figure 30-260. ATmega644PA: I/O pin pull-up resistor current vs. input voltage (VCC = 1.8V) 50 45 40 35 IOP [A] 30 25 20 15 10 25C 85C -40C 5 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 VOP [V] Figure 30-261. ATmega644PA: I/O pin pull-up resistor current vs. input voltage (VCC = 2.7V) 80 70 60 IOP [A] 50 40 30 20 25C 85C -40C 10 0 0 0.5 1.0 1.5 2.0 2.5 3.0 VOP [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 483 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-262. ATmega644PA: I/O pin pull-up resistor current vs. input voltage (VCC = 5V) 140 120 IOP [A] 100 80 60 40 25C 85C -40C 20 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VOP [V] Figure 30-263. ATmega644PA: Reset pull-up g p resistor current vs. reset gpin ( voltage) (VCC = 1.8V) 35 30 IRESET [A] 25 20 15 10 25C -40C 85C 5 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 VRESET [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 484 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-264. ATmega644PA: Reset pull-up resistor current vs. reset pin voltage (VCC = 2.7V) 60 50 IRESET [A] 40 30 20 25C -40C 85C 10 0 0 0.5 1.0 1.5 2.0 2.5 3.0 VRESET [V] Figure 30-265. ATmega644PA: Reset pull-up resistor current vs. reset pin voltage (VCC = 5V) 120 100 IRESET [A] 80 60 40 25C -40C 85C 20 0 0 1 2 3 4 5 VRESET [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 485 ATmega164A/PA/324A/PA/644A/PA/1284/P 30.6.8 Pin driver strength Figure 30-266. ATmega644PA: I/O pin output voltage vs. sink current (VCC = 3V) 0.9 85C 0.8 0.7 25C 0.6 VOL [V] -40C 0.5 0.4 0.3 0.2 0.1 0 0 2 4 6 8 10 12 14 16 18 20 IOL [mA] Figure 30-267. ATmega644PA: I/O pin output voltage vs. sink current (VCC = 5V) 0.6 85C 0.5 25C VOL [V] 0.4 -40C 0.3 0.2 0.1 0 0 2 4 6 8 10 12 14 16 18 20 IOL [mA] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 486 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-268. ATmega644PA: I/O pin output voltage vs. source current (VCC = 3V) 3.5 3.0 VOH [V] 2.5 -40C 25C 85C 2.0 1.5 1.0 0.5 0 0 2 4 6 8 10 12 14 16 18 20 IOH [mA] Figure 30-269. ATmega644PA: I/O pin output voltage vs. source current (VCC = 5V) 5.1 5.0 4.9 VOH [V] 4.8 4.7 4.6 -40C 4.5 25C 4.4 85C 4.3 0 2 4 6 8 10 12 14 16 18 20 IOH [mA] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 487 ATmega164A/PA/324A/PA/644A/PA/1284/P 30.6.9 Pin threshold and hysteresis Figure 30-270. ATmega644PA: I/O pin input threshold vs. VCC (VIH , I/O pin read as `1') 3.0 85C -40C 25C 2.5 Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-271. ATmega644PA: I/O pin input threshold vs. VCC (VIL, I/O pin read as `0') 2.5 85C 25C -40C Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 488 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-272. ATmega644PA: I/O pin input hysteresis vs. VCC 0.60 25C 85C -40C 0.55 Input Hysteresis [mV] 0.50 0.45 0.40 0.35 0.30 0.25 0.20 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-273. ATmega644PA: Reset pin input threshold vs. VCC (VIH , I/O pin read as `1') 2.5 -40C 25C 85C Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 489 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-274. ATmega644PA: Reset pin input threshold vs. VCC (VIL, I/O pin read as `0') 2.5 85C 25C -40C Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-275. ATmega644PA: Reset pin input hysteresis vs. VCC 0.7 Input hysteresis [mV] 0.6 0.5 0.4 0.3 0.2 -40C 25C 85C 0.1 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 490 ATmega164A/PA/324A/PA/644A/PA/1284/P 30.6.10 BOD threshold Figure 30-276. ATmega644PA: BOD threshold vs. temperature (VBOT = 4.3V) 4.35 Rising Vcc Threshold [V] 4.32 4.29 Falling Vcc 4.26 4.23 4.20 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 90 100 Temperature [C] Figure 30-277. ATmega644PA: BOD threshold vs. temperature (VBOT = 2.7V) 2.77 Rising Vcc 2.75 Threshold [V] 2.73 2.71 Falling Vcc 2.69 2.67 2.65 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 Temperature [C] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 491 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-278. ATmega644PA: BOD threshold vs. temperature (VBOT = 1.8V) 1.84 1.83 Rising Vcc Threshold [V] 1.82 1.81 1.80 Falling Vcc 1.79 1.78 1.77 1.76 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 Temperature [C] Figure 30-279. ATmega644PA: Calibrated bandgap voltage vs. VCC 1.086 1.084 Bandgap voltage [V] 1.082 85C 25C 1.080 1.078 1.076 1.074 1.072 1.070 1.068 1.066 1.5 -40C 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 492 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-280. ATmega324PA: Bandgap voltage vs. temperature 1.087 1.8V 3.6V 2.7V 4.5V 1.085 Bandgap voltage [V] 1.083 1.081 5.5V 1.079 1.077 1.075 1.073 1.071 1.069 1.067 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [C] 30.6.11 Internal oscillator speed Figure 30-281. ATmega644PA: Watchdog oscillator frequency vs. temperature 119 118 117 116 FRC [kHz] 115 114 113 2.1V 112 2.7V 3.3V 4.0V 5.5V 111 110 109 108 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 Temperature [C] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 493 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-282. ATmega644PA: Watchdog oscillator orequency vs. VCC 119 118 117 -40C 116 FRC [kHz] 115 25C 114 113 112 111 110 85C 109 108 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-283. ATmega644PA: Calibrated 8MHz RC oscillator vs. VCC 8.4 85C 8.2 25C FRC [MHz] 8.0 -40C 7.8 7.6 7.4 7.2 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 494 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-284. ATmega644PA: Calibrated 8MHz RC oscillator vs. temperature 8.4 5.0V 8.3 3.0V 8.2 FRC [MHz] 8.1 8.0 7.9 7.8 7.7 7.6 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 Temperature [C] Figure 30-285. ATmega644PA: Calibrated 8MHz RC oscillator vs. OSCCAL value 16 85C 25C -40C 14 12 FRC [MHz] 10 8 6 4 2 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 OSCCAL [X1] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 495 ATmega164A/PA/324A/PA/644A/PA/1284/P 30.6.12 Current consumption of peripheral units Figure 30-286. ATmega644PA: ADC current vs. VCC (AREF = AVCC) 250 25C 85C -40C 200 ICC [A] 150 100 50 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VCC [V] Figure 30-287. ATmega644PA: Analog comparator current vs. VCC 90 -40C 80 25C 85C ICC [A] 70 60 50 40 30 20 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 496 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-288. ATmega644PA: AREF external reference current vs. VCC 200 25C 85C -40C 160 ICC [A] 120 80 40 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-289. ATmega644PA: Brownout detector current vs. VCC 24 85C 22 25C -40C ICC [A] 20 18 16 14 12 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 497 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-290. ATmega644PA: Programming current vs. VCC -40C 16 14 12 ICC [mA] 10 25C 8 85C 6 4 2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-291. ATmega644PA: Watchdog timer current vs. VCC 9 8 -40C 7 25C 85C ICC [A] 6 5 4 3 2 1 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 498 ATmega164A/PA/324A/PA/644A/PA/1284/P 30.6.13 Current consumption in reset and reset pulsewidth Figure 30-292. ATmega644PA: Reset supply current vs. low frequency (0.1 - 1.0MHz) 0.10 5.5V 5.0V 0.08 ICC [mA] 4.5V 4.0V 0.06 3.3V 0.04 2.7V 1.8V 0.02 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency [MHz] Figure 30-293. ATmega644PA: Reset supply current vs. frequency (1 - 20MHz) 2.00 5.5V 1.75 5.0V 1.50 4.5V ICC [mA] 1.25 1.00 4.0V 0.75 3.3V 0.50 2.7V 0.25 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency [MHz] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 499 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-294. ATmega644PA: Minimum reset pulsewidth vs. VCC 1800 1600 Pulsewidth [ns] 1400 1200 1000 800 600 85C 25C -40C 400 200 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 500 ATmega164A/PA/324A/PA/644A/PA/1284/P 30.7 ATmega1284 typical characteristics - TA = -40C to 85C 30.7.1 Active supply current ICC [mA] Figure 30-295. ATmega1284: Active supply current vs. low frequency (0.1 - 1.0MHz) 1.6 5.5V 1.4 5.0V 1.2 4.5V 1.0 4.0V 0.8 3.3V 0.6 2.7V 0.4 1.8V 0.2 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency [MHz] Figure 30-296. ATmega1284: Active supply current vs. frequency (1 - 20MHz) 20 5.5V 18 5.0V 16 4.5V ICC [mA] 14 12 4.0V 10 8 3.3V 6 2.7V 4 2 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency [MHz] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 501 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-297. ATmega1284: Active supply current vs. VCC (internal RC oscillator, 8MHz) 9 85C 25C -40C 8 7 ICC [mA] 6 5 4 3 2 1 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-298. ATmega1284: Active supply current vs. VCC (internal RC oscillator, 1MHz) 1.8 85C 25C -40C 1.5 ICC [mA] 1.2 0.9 0.6 0.3 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 502 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-299. ATmega1284: Active supply current vs. VCC (internal RC oscillator, 128kHz) 0.28 -40C 25C 85C 0.24 ICC [mA] 0.20 0.16 0.12 0.08 0.04 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 30.7.2 Idle supply current Figure 30-300. ATmega1284: Idle supply current vs. low frequency (0.1 - 1.0MHz) 0.24 5.5V 0.21 5.0V 0.18 4.5V 4.0V 3.6V ICC [mA] 0.15 0.12 2.7V 0.09 1.8V 0.06 0.03 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency [MHz] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 503 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-301. ATmega1284: Idle supply current vs. frequency (1 - 20MHz) 3.0 5.5V 2.5 5.0V 4.5V ICC [mA] 2.0 1.5 4.0V 1.0 3.3V 2.7V 0.5 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency [MHz] Figure 30-302. ATmega1284: Idle supply current vs. VCC (internal RC oscillator, 8MHz) 1.4 85C 1.2 25C -40C ICC [mA] 1.0 0.8 0.6 0.4 0.2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 504 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-303. ATmega1284: Idle supply current vs. VCC (internal RC oscillator, 1MHz) 0.42 85C 25C -40C 0.36 ICC [mA] 0.30 0.24 0.18 0.12 0.06 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-304. ATmega1284: Idle supply current vs. VCC (internal RC oscillator, 128kHz) 0.12 -40C 85C 25C 0.10 ICC [mA] 0.08 0.06 0.04 0.02 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 505 ATmega164A/PA/324A/PA/644A/PA/1284/P 30.7.3 Supply current of I/O modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register. See "PRR0 - Power Reduction Register 0" on page 56 for details. Table 30-13. PRR bit Additional current consumption for the different I/O modules (absolute values) Typical numbers in VCC = 2V, F = 1MHz VCC = 3V, F = 4MHz VCC = 5V, F = 8MHz PRUSART1 3.0A 19.2A 87.7A PRUSART0 2.9A 19.2A 88.5A PRTWI 7.5A 49.3A 230.3A PRTIM3 4.0A 24.7A 105.5A PRTIM2 6.0A 39.7A 176.3A PRTIM1 4.2A 26.4A 113.7A PRTIM0 1.7A 11.6A 54.3A PRADC 13.5A 54.7A 273A PRSPI 5.7A 40.6A 212.2A Table 30-14. Additional current consumption (percentage) in Active and Idle mode Additional current consumption compared to Active with external clock (see Figure 30-295 on page 501 and Figure 30-296 on page 501) Additional current consumption compared to Idle with external clock (see Figure 30-300 on page 503 and Figure 30-301 on page 504) PRUSART1 0.9% 6.0% PRUSART0 0.9% 6.0% PRTWI 2.3% 15.4% PRTIM3 1.1% 7.5% PRTIM2 1.8% 12.1% PRTIM1 1.2% 8.0% PRTIM0 0.5% 3.6% PRTADC 3.0% 19.8% PRSPI 2.0% 13.2% PRR bit It is possible to calculate the typical current consumption based on the numbers from Table 30-12 on page 480 for other VCC and frequency settings than listed in Table 30-11 on page 480. Exam p l e Calculate the expected current consumption in idle mode with TIMER1, ADC, and SPI enabled at VCC = 2.0V and F = 1MHz. From Table 30-12 on page 480, third column, we see that we need to add 8.0% for the TIMER1, 19.8% for the ADC, and 13.2% for the SPI module. Reading from Figure 30-301 on page 504, we find that the idle current consumption is ~0.075mA at VCC = 2.0V and F = 1MHz. The total current consumption in idle mode with TIMER1, ADC, and SPI enabled, gives: I CC total 0.075mA (1+ 0.08 + 0.198 + 0.132) 0.106mA 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 506 ATmega164A/PA/324A/PA/644A/PA/1284/P 30.7.4 Power-down supply current Figure 30-305. ATmega1284: Power-down supply current vs. VCC (watchdog timer disabled) 4.0 85C 3.5 3.0 ICC [A] 2.5 2.0 1.5 1.0 0.5 0 1.5 25C -40C 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-306. ATmega1284: Power-down supply current vs. VCC (watchdog timer enabled) 11.0 85C 10.2 9.4 ICC [A] 8.6 -40C 25C 7.8 7.0 6.2 5.4 4.6 3.8 3.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 507 ATmega164A/PA/324A/PA/644A/PA/1284/P 30.7.5 Power-save supply current Figure 30-307. ATmega1284: Power-save supply current vs. VCC (watchdog timer disabled and 32kHz crystal oscillator running) 5.0 85C 4.5 4.0 ICC [A] 3.5 3.0 2.5 2.0 1.5 25C -40C 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 30.7.6 Standby supply current Figure 30-308. ATmega1284: Standby supply current vs. VCC (watchdog timer disabled) 0.25 6MHz_xtal ICC [mA] 0.20 6MHz_res 4MHz_xtal 4MHz_res 2MHz_xtal 0.15 0.10 2MHz_res 1MHz_res 450kHz_res 0.05 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 508 ATmega164A/PA/324A/PA/644A/PA/1284/P 30.7.7 Pin pull-up Figure 30-309. ATmega1284: I/O pin pull-up resistor current vs. input voltage (VCC = 1.8V) 35 30 IRESET [A] 25 20 15 10 -40C 25C 85C 5 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 VRESET [V] Figure 30-310. ATmega1284: I/O pin pull-up resistor current vs. input voltage (VCC = 2.7V) 80 70 60 IOP [A] 50 40 30 20 -40C 25C 85C 10 0 0 0.5 1.0 1.5 2.0 2.5 3.0 VOP [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 509 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-311. ATmega1284: I/O pin pull-up resistor current vs. input voltage (VCC = 5V) 140 120 IOP [A] 100 80 60 40 -40C 25C 85C 20 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VOP [V] Figure 30-312. ATmega1284: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V) 35 30 IRESET [A] 25 20 15 10 -40C 25C 85C 5 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 VRESET [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 510 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-313. ATmega1284: Reset pull-up resistor current vs. reset pin voltage (VCC = 2.7V) 60 50 IRESET [A] 40 30 20 25C -40C 85C 10 0 0 0.5 1.0 1.5 2.0 2.5 3.0 VRESET [V] Figure 30-314. ATmega1284: Reset pull-up resistor current vs. reset pin voltage (VCC = 5V) 120 100 IRESET [A] 80 60 40 20 -40C 25C 85C 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VRESET [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 511 ATmega164A/PA/324A/PA/644A/PA/1284/P 30.7.8 Pin driver strength Figure 30-315. ATmega1284: I/O pin output voltage vs. sink current (VCC = 2.7V) 1.2 85C VOL [V] 1.0 0.8 25C 0.6 -40C 0.4 0.2 0 0 2 4 6 8 10 12 14 16 18 20 IOL [mA] Figure 30-316. ATmega1284: I/O pin output voltage vs. sink current (VCC = 3V) 0.9 85C 0.8 0.7 25C VOL [V] 0.6 -40C 0.5 0.4 0.3 0.2 0.1 0 0 2 4 6 8 10 12 14 16 18 20 IOL [mA] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 512 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-317. ATmega1284: I/O pin output voltage vs. sink current (VCC = 5V) 0.6 85C 0.5 25C VOL [V] 0.4 -40C 0.3 0.2 0.1 0 0 2 4 6 8 10 12 14 16 18 20 IOL [mA] Figure 30-318. ATmega1284: I/O pin output voltage vs. source current (VCC = 2.7V) 3.0 VOH [V] 2.5 2.0 -40C 25C 1.5 85C 1.0 0.5 0 0 2 4 6 8 10 12 14 16 18 20 IOH [mA] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 513 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-319. ATmega1284: I/O pin output voltage vs. source current (VCC = 3V) 3.5 3.0 VOH [V] 2.5 -40C 25C 85C 2.0 1.5 1.0 0.5 0 0 2 4 6 8 10 12 14 16 18 20 IOH [mA] 30.7.9 Pin threshold and hysteresis Figure 30-320. ATmega1284: I/O pin input threshold vs. VCC (VIH , I/O pin read as `1') 3.0 85C 25C -40C 2.5 Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 514 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-321. ATmega1284: I/O pin input threshold vs. VCC (VIL, I/O pin read as `0') 2.5 85C -40C 25C Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-322. ATmega1284: I/O pin input hysteresis vs. VCC 0.60 Input hysteresis [mV] 0.55 85C 25C -40C 0.50 0.45 0.40 0.35 0.30 0.25 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 515 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-323. ATmega1284: Reset pin input threshold vs. VCC (VIH , I/O pin read as `1') -40C 85C 25C 2.5 Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-324. ATmega1284: Reset pin input threshold vs. VCC (VIL, I/O pin read as `0') 2.5 -40C 85C 25C Threshold (V) 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC (V) 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 516 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-325. ATmega1284: Reset pin input hysteresis vs. VCC 0.6 Input hysteresis [mV] 0.5 0.4 0.3 0.2 0.1 -40C 25C 85C 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 30.7.10 BOD threshold Figure 30-326. ATmega1284: BOD threshold vs. temperature (VBOT = 4.3V) 4.37 Rising Vcc 4.35 Threshold [V] 4.33 4.31 Falling Vcc 4.29 4.27 4.25 4.23 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [C] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 517 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-327. ATmega1284: BOD threshold vs. temperature (VBOT = 2.7V) 2.78 Rising Vcc 2.76 Threshold [V] 2.74 2.72 2.70 Falling Vcc 2.68 2.66 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 70 80 90 Temperature [C] Figure 30-328. ATmega1284: BOD threshold vs. temperature (VBOT = 1.8V) 1.84 Rising Vcc 1.83 Threshold [V] 1.82 1.81 Falling Vcc 1.80 1.79 1.78 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 Temperature [C] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 518 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-329. ATmega1284: Calibrated bandgap voltage vs. VCC 1.120 Bandgap voltage [V] 1.115 85C 25C 1.110 1.105 1.100 1.095 -40C 1.090 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Vcc [V] Figure 30-330. ATmega1284: Bandgap voltage vs. temperature 1.120 1.8V 3.3V 5.0V 5.5V Bandgap voltage [V] 1.115 1.110 1.105 1.100 1.095 1.090 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [C] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 519 ATmega164A/PA/324A/PA/644A/PA/1284/P 30.7.11 Internal oscillator speed Figure 30-331. ATmega1284: Watchdog oscillator frequency vs. temperature 123 122 121 FRC [kHz] 120 119 118 117 2.7V 116 3.3V 4.0V 5.5V 115 114 113 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [C] Figure 30-332. ATmega1284: Watchdog oscillator frequency vs. VCC 124 122 FRC [kHz] -40C 120 25C 118 116 85C 114 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 520 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-333. ATmega1284: Calibrated 8MHz RC oscillator vs. VCC 8.6 85C 8.4 25C FRC [MHz] 8.2 8.0 -40C 7.8 7.6 7.4 7.2 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-334. ATmega1284: Calibrated 8MHz RC oscillator vs. temperature 8.3 5.5V 8.2 3.3V 2.7V FRC [MHz] 8.1 1.8V 8.0 7.9 7.8 7.7 7.6 7.5 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [C] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 521 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-335. ATmega1284: Calibrated 8MHz RC oscillator vs. OSCCAL value 16 85C 25C -40C 14 FRC [MHz] 12 10 8 6 4 2 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL [X1] 30.7.12 Current consumption of peripheral units Figure 30-336. ATmega1284: ADC current vs. VCC (AREF = AVCC) 280 -40C 25C 85C 260 240 ICC [A] 220 200 180 160 140 120 100 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 522 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-337. ATmega1284: Analog comparator current vs. VCC 85 -40C 25C 85C 75 ICC [A] 65 55 45 35 25 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-338. ATmega1284: AREF external reference current vs. VCC 200 85C 25C -40C 180 ICC [A] 160 140 120 100 80 60 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 523 ATmega164A/PA/324A/PA/644A/PA/1284/P ICC [A] Figure 30-339. ATmega1284: Brownout detector current vs. VCC 25 85C 23 25C 21 -40C 19 17 15 13 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-340. ATmega1284: Programming current vs. VCC 14 -40C 12 ICC [mA] 10 25C 8 85C 6 4 2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 524 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-341. ATmega1284: Watchdog timer current vs. VCC 8.5 -40C 7.5 25C 85C ICC [A] 6.5 5.5 4.5 3.5 2.5 1.5 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 30.7.13 Current consumption in reset and reset pulsewidth Figure 30-342. ATmega1284: Reset supply current vs. low frequency (0.1 - 1.0MHz) 0.10 5.5V 5.0V 0.08 ICC [mA] 4.5V 4.0V 0.06 3.3V 0.04 2.7V 1.8V 0.02 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency [MHz] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 525 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-343. ATmega1284: Reset supply current vs. frequency (1 - 20MHz) 1.6 5.5V 1.4 5.0V 1.2 4.5V ICC [mA] 1.0 0.8 4.0V 0.6 3.3V 0.4 2.7V 0.2 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency [MHz] Figure 30-344. ATmega1284: Minimum reset pulsewidth vs. VCC 1800 1600 Pulsewidth [ns] 1400 1200 1000 800 600 400 85C 25C -40C 200 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 526 ATmega164A/PA/324A/PA/644A/PA/1284/P 30.8 ATmega1284P typical characteristics - TA = -40C to 85C 30.8.1 Active supply current ICC [mA] Figure 30-345. ATmega1284P: Active supply current vs. low frequency (0.1 - 1.0MHz) 1.6 5.5V 1.4 5.0V 1.2 4.5V 1.0 4.0V 0.8 3.3V 0.6 2.7V 0.4 1.8V 0.2 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency [MHz] Figure 30-346. ATmega1284P: Active supply current vs. frequency (1 - 20MHz) 20 5.5V 18 5.0V 16 4.5V ICC [mA] 14 12 4.0V 10 8 3.3V 6 2.7V 4 2 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency [MHz] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 527 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-347. ATmega1284P: Active supply current vs. VCC (internal RC oscillator, 8MHz) 9 85C 25C -40C 8 7 ICC [mA] 6 5 4 3 2 1 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-348. ATmega1284P: Active supply current vs. VCC (internal RC oscillator, 1MHz) 1.8 85C 25C -40C 1.5 ICC [mA] 1.2 0.9 0.6 0.3 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 528 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-349. ATmega1284P: Active supply current vs. VCC (internal RC oscillator, 128kHz) 0.28 -40C 25C 85C 0.24 ICC [mA] 0.20 0.16 0.12 0.08 0.04 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 30.8.2 Idle supply current Figure 30-350. ATmega1284P: Idle supply current vs. low frequency (0.1 - 1.0MHz) 0.24 5.5V 0.21 5.0V 0.18 4.5V 4.0V 3.6V ICC [mA] 0.15 0.12 2.7V 0.09 1.8V 0.06 0.03 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency [MHz] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 529 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-351. ATmega1284P: Idle supply current vs. frequency (1 - 20MHz) 3.0 5.5V 2.5 5.0V 4.5V ICC [mA] 2.0 1.5 4.0V 1.0 3.3V 2.7V 0.5 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency [MHz] Figure 30-352. ATmega1284P: Idle supply current vs. VCC (internal RC oscillator, 8MHz) 1.4 85C 1.2 25C -40C ICC [mA] 1.0 0.8 0.6 0.4 0.2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 530 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-353. ATmega1284P: Idle supply current vs. VCC (internal RC oscillator, 1MHz) 0.42 85C 25C -40C 0.36 ICC [mA] 0.30 0.24 0.18 0.12 0.06 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-354. ATmega1284P: Idle supply current vs. VCC (internal RC oscillator, 128kHz) 0.12 -40C 85C 25C 0.10 ICC [mA] 0.08 0.06 0.04 0.02 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 531 ATmega164A/PA/324A/PA/644A/PA/1284/P 30.8.3 Supply current of I/O modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register. See "PRR0 - Power Reduction Register 0" on page 56 for details. Table 30-15. PRR bit Additional current consumption for the different I/O modules (absolute values) Typical numbers in VCC = 2V, F = 1MHz VCC = 3V, F = 4MHz VCC = 5V, F = 8MHz PRUSART1 3.0A 19.2A 87.7A PRUSART0 2.9A 19.2A 88.5A PRTWI 7.5A 49.3A 230.3A PRTIM3 4.0A 24.7A 105.5A PRTIM2 6.0A 39.7A 176.3A PRTIM1 4.2A 26.4A 113.7A PRTIM0 1.7A 11.6A 54.3A PRADC 13.5A 54.7A 273A PRSPI 5.7A 40.6A 212.2A Table 30-16. Additional Current Consumption (percentage) in Active and Idle mode Additional current consumption compared to Active with external clock (see Figure 30-295 on page 501 and Figure 30-296 on page 501) Additional current consumption compared to Idle with external clock (see Figure 30-300 on page 503 and Figure 30-301 on page 504) PRUSART1 0.9% 6.0% PRUSART0 0.9% 6.0% PRTWI 2.3% 15.4% PRTIM3 1.1% 7.5% PRTIM2 1.8% 12.1% PRTIM1 1.2% 8.0% PRTIM0 0.5% 3.6% PRTADC 3.0% 19.8% PRSPI 2.0% 13.2% PRR bit It is possible to calculate the typical current consumption based on the numbers from Table 30-12 on page 480 for other VCC and frequency settings than listed in Table 30-11 on page 480. Exam p l e Calculate the expected current consumption in idle mode with TIMER1, ADC, and SPI enabled at VCC = 2.0V and F = 1MHz. From Table 30-12 on page 480, third column, we see that we need to add 8.0% for the TIMER1, 19.8% for the ADC, and 13.2% for the SPI module. Reading from Figure 30-301 on page 504, we find that the idle current consumption is ~0.075 mA at VCC = 2.0V and F = 1MHz. The total current consumption in idle mode with TIMER1, ADC, and SPI enabled, gives: I CC total 0.075 mA (1+ 0.08 + 0.198 + 0.132) 0.106 mA 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 532 ATmega164A/PA/324A/PA/644A/PA/1284/P 30.8.4 Power-down supply current Figure 30-355. ATmega1284P: Power-down supply current vs. VCC (watchdog timer disabled) 4.0 85C 3.5 3.0 ICC [A] 2.5 2.0 1.5 1.0 0.5 0 1.5 25C -40C 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-356. ATmega1284P: Power-down supply current vs. VCC (watchdog timer enabled) 11.0 85C 10.2 9.4 ICC [A] 8.6 -40C 25C 7.8 7.0 6.2 5.4 4.6 3.8 3.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 533 ATmega164A/PA/324A/PA/644A/PA/1284/P 30.8.5 Power-save supply current Figure 30-357. ATmega1284P: Power-save supply current vs. VCC (watchdog timer disabled and 32kHz crystal oscillator running) 5.0 85C 4.5 4.0 ICC [A] 3.5 3.0 2.5 2.0 1.5 25C -40C 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 30.8.6 Standby supply current Figure 30-358. ATmega1284P: Standby supply current vs. VCC (watchdog timer disabled) 0.25 6MHz_xtal ICC [mA] 0.20 6MHz_res 4MHz_xtal 4MHz_res 2MHz_xtal 0.15 0.10 2MHz_res 1MHz_res 450kHz_res 0.05 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 534 ATmega164A/PA/324A/PA/644A/PA/1284/P 30.8.7 Pin pull-up Figure 30-359. ATmega1284P: I/O pin pull-up resistor current vs. input voltage (VCC = 1.8V) 35 30 IRESET [A] 25 20 15 10 -40C 25C 85C 5 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 VRESET [V] Figure 30-360. ATmega1284P: I/O pin pull-up resistor current vs. input voltage (VCC = 2.7V) 80 70 60 IOP [A] 50 40 30 20 -40C 25C 85C 10 0 0 0.5 1.0 1.5 2.0 2.5 3.0 VOP [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 535 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-361. ATmega1284P: I/O pin pull-up resistor current vs. input voltage (VCC = 5V) 140 120 IOP [A] 100 80 60 40 -40C 25C 85C 20 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VOP [V] Figure 30-362. ATmega1284P: Reset pull-up resistor current vs. reset pin voltage (VCC = 1.8V) 35 30 IRESET [A] 25 20 15 10 -40C 25C 85C 5 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 VRESET [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 536 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-363. ATmega1284P: Reset pull-up resistor current vs. reset pin voltage (VCC = 2.7V) 60 50 IRESET [A] 40 30 20 25C -40C 85C 10 0 0 0.5 1.0 1.5 2.0 2.5 3.0 VRESET [V] Figure 30-364. ATmega1284P: Reset pull-up resistor current vs. reset pin voltage (VCC = 5V) 120 100 IRESET [A] 80 60 40 20 -40C 25C 85C 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VRESET [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 537 ATmega164A/PA/324A/PA/644A/PA/1284/P 30.8.8 Pin driver strength Figure 30-365. ATmega1284P: I/O pin output voltage vs. sink current (VCC = 2.7V) 1.2 85C VOL [V] 1.0 0.8 25C 0.6 -40C 0.4 0.2 0 0 2 4 6 8 10 12 14 16 18 20 IOL [mA] Figure 30-366. ATmega1284P: I/O pin output voltage vs. sink current (VCC = 3V) 0.9 85C 0.8 0.7 25C VOL [V] 0.6 -40C 0.5 0.4 0.3 0.2 0.1 0 0 2 4 6 8 10 12 14 16 18 20 IOL [mA] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 538 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-367. ATmega1284P: I/O pin output voltage vs. sink current (VCC = 5V) 0.6 85C 0.5 25C VOL [V] 0.4 -40C 0.3 0.2 0.1 0 0 2 4 6 8 10 12 14 16 18 20 IOL [mA] Figure 30-368. ATmega1284P: I/O pin output voltage vs. source current (VCC = 2.7V) 3.0 VOH [V] 2.5 2.0 -40C 25C 1.5 85C 1.0 0.5 0 0 2 4 6 8 10 12 14 16 18 20 IOH [mA] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 539 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-369. ATmega1284P: I/O pin output voltage vs. source current (VCC = 3V) 3.5 3.0 VOH [V] 2.5 -40C 25C 85C 2.0 1.5 1.0 0.5 0 0 2 4 6 8 10 12 14 16 18 20 IOH [mA] 30.8.9 Pin threshold and hysteresis Figure 30-370. ATmega1284P: I/O pin input threshold vs. VCC (VIH , I/O pin read as `1') 3.0 85C 25C -40C 2.5 Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 540 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-371. ATmega1284P: I/O pin input threshold vs. VCC (VIL, I/O pin read as `0') 2.5 85C -40C 25C Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-372. ATmega1284P: I/O pin input hysteresis vs. VCC 0.60 Input hysteresis [mV] 0.55 85C 25C -40C 0.50 0.45 0.40 0.35 0.30 0.25 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 541 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-373. ATmega1284P: Reset pin input threshold vs. VCC (VIH , I/O pin read as `1') -40C 85C 25C 2.5 Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-374. ATmega1284P: Reset pin input threshold vs. VCC (VIL, I/O pin read as `0') 2.5 -40C 85C 25C Threshold (V) 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC (V) 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 542 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-375. ATmega1284P: Reset pin input hysteresis vs. VCC 0.6 Input hysteresis [mV] 0.5 0.4 0.3 0.2 0.1 -40C 25C 85C 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 30.8.10 BOD threshold Figure 30-376. ATmega1284P: BOD threshold vs. temperature (VBOT = 4.3V) 4.37 Rising Vcc 4.35 Threshold [V] 4.33 4.31 Falling Vcc 4.29 4.27 4.25 4.23 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [C] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 543 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-377. ATmega1284P: BOD threshold vs. temperature (VBOT = 2.7V) 2.78 Rising Vcc 2.76 Threshold [V] 2.74 2.72 2.70 Falling Vcc 2.68 2.66 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 80 90 Temperature [C] Figure 30-378. ATmega1284P: BOD threshold vs. temperature (VBOT = 1.8V) 1.84 Rising Vcc 1.83 Threshold [V] 1.82 1.81 Falling Vcc 1.80 1.79 1.78 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 Temperature [C] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 544 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-379. ATmega1284P: Calibrated bandgap voltage vs. VCC 1.120 Bandgap voltage [V] 1.115 85C 25C 1.110 1.105 1.100 1.095 -40C 1.090 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Vcc [V] Figure 30-380. ATmega1284P: Bandgap voltage vs. temperature 1.120 1.8V 3.3V 5.0V 5.5V Bandgap voltage [V] 1.115 1.110 1.105 1.100 1.095 1.090 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [C] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 545 ATmega164A/PA/324A/PA/644A/PA/1284/P 30.8.11 Internal oscillator speed Figure 30-381. ATmega1284P: Watchdog oscillator frequency vs. temperature 123 122 121 FRC [kHz] 120 119 118 117 2.7V 116 3.3V 4.0V 5.5V 115 114 113 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [C] Figure 30-382. ATmega1284P: Watchdog oscillator frequency vs. VCC 124 122 FRC [kHz] -40C 120 25C 118 116 85C 114 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 546 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-383. ATmega1284P: Calibrated 8MHz RC oscillator vs. VCC 8.6 85C 8.4 25C FRC [MHz] 8.2 8.0 -40C 7.8 7.6 7.4 7.2 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-384. ATmega1284P: Calibrated 8MHz RC oscillator vs. temperature 8.3 5.5V 8.2 3.3V 2.7V FRC [MHz] 8.1 1.8V 8.0 7.9 7.8 7.7 7.6 7.5 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [C] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 547 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-385. ATmega1284P: Calibrated 8MHz RC oscillator vs. OSCCAL value 16 85C 25C -40C 14 FRC [MHz] 12 10 8 6 4 2 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL [X1] 30.8.12 Current consumption of peripheral units Figure 30-386. ATmega1284P: ADC current vs. VCC (AREF = AVCC) 280 -40C 25C 85C 260 240 ICC [A] 220 200 180 160 140 120 100 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 548 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-387. ATmega1284P: Analog comparator current vs. VCC 85 -40C 25C 85C 75 ICC [A] 65 55 45 35 25 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-388. ATmega1284P: AREF external reference current vs. VCC 200 85C 25C -40C 180 ICC [A] 160 140 120 100 80 60 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 549 ATmega164A/PA/324A/PA/644A/PA/1284/P ICC [A] Figure 30-389. ATmega1284P: Brownout detector current vs. VCC 25 85C 23 25C 21 -40C 19 17 15 13 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-390. ATmega1284P: Programming current vs. VCC 14 -40C 12 ICC [mA] 10 25C 8 85C 6 4 2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 550 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-391. ATmega1284P: Watchdog timer current vs. VCC 8.5 -40C 7.5 25C 85C ICC [A] 6.5 5.5 4.5 3.5 2.5 1.5 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 30.8.13 Current consumption in reset and reset pulsewidth Figure 30-392. ATmega1284P: Reset supply current vs. low frequency (0.1 - 1.0MHz) 0.10 5.5V 5.0V 0.08 ICC [mA] 4.5V 4.0V 0.06 3.3V 0.04 2.7V 1.8V 0.02 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency [MHz] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 551 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-393. ATmega1284P: Reset supply current vs. frequency (1 - 20MHz) 1.6 5.5V 1.4 5.0V 1.2 4.5V ICC [mA] 1.0 0.8 4.0V 0.6 3.3V 0.4 2.7V 0.2 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency [MHz] Figure 30-394. ATmega1284P: Minimum reset pulsewidth vs. VCC 1800 1600 Pulsewidth [ns] 1400 1200 1000 800 600 400 85C 25C -40C 200 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 552 ATmega164A/PA/324A/PA/644A/PA/1284/P 31. Typical Characteristics - TA = -40C to 105C The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with rail-to-rail output is used as clock source. All Active- and Idle current consumption measurements are done with all bits in the PRR registers set and thus, the corresponding I/O modules are turned off. Also the Analog Comparator is disabled during these measurements. The power consumption in Power-down mode is independent of clock selection. The current consumption is a function of several factors such as: operating voltage, operating frequency, loading of I/O pins, switching rate of I/O pins, code executed and ambient temperature. The dominating factors are operating voltage and frequency. The current drawn from capacitive loaded pins may be estimated (for one pin) as CL*VCC*f where CL = load capacitance, VCC = operating voltage and f = average switching frequency of I/O pin. The parts are characterized at frequencies higher than test limits. Parts are not guaranteed to function properly at frequencies higher than the ordering code indicates. The difference between current consumption in Power-down mode with Watchdog Timer enabled and Powerdown mode with Watchdog Timer disabled represents the differential current drawn by the Watchdog Timer. 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 553 ATmega164A/PA/324A/PA/644A/PA/1284/P 31.1 ATmega164PA Typical Characteristics - TA = -40C to 105C 31.1.1 Active supply current Figure 31-1. ATmega164PA: Active supply current vs. VCC (internal RC oscillator, 8MHz) >&@ ,&& >P$@ 9&& >9@ Figure 31-2. ATmega164PA: Active supply current vs. VCC (internal RC oscillator, 1MHz) >&@ ,&& >P$@ 9&& >9@ 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 554 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-3. ATmega164PA: Active supply current vs. VCC (internal RC oscillator, 128kHz) >&@ ,&& >P$@ 9&& >9@ 31.1.2 Idle supply current Figure 31-4. ATmega164PA: Idle supply current vs. VCC (internal RC oscillator, 8MHz) >&@ ,&& >P$@ 2018 Microchip Technology Inc. 9&& >9@ Data Sheet Complete DS40002070A-page 555 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-5. ATmega164PA: Idle supply current vs. VCC (internal RC oscillator, 1MHz) >&@ ,&& >P$@ Figure 31-6. 9&& >9@ ATmega164PA: Idle supply current vs. VCC (internal RC oscillator, 128kHz) >&@ ,&&>P$@ 9&& >9@ 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 556 ATmega164A/PA/324A/PA/644A/PA/1284/P 31.1.3 Power-down supply current Figure 31-7. ATmega164PA: Power-down supply current vs. VCC (watchdog timer disabled) >&@ ,&& >X$@ Figure 31-8. 9&& >9@ ATmega164PA: Power-down supply current vs. VCC (watchdog timer enabled) ,&& >X$@ >&@ 9&& >9@ 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 557 ATmega164A/PA/324A/PA/644A/PA/1284/P 31.1.4 Pin pull-up Figure 31-9. ATmega164PA: I/O pin pull-up resistor current vs. input voltage (VCC = 1.8V) >&@ ,23 >X$@ 923 >9@ Figure 31-10. ATmega164PA: I/O pin pull-up resistor current vs. input voltage (VCC = 2.7V) >&@ ,23 >X$@ 923 >9@ 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 558 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-11. ATmega164PA: I/O pin pull-up resistor current vs. input voltage (VCC = 5V) >&@ ,23 >X$@ 923 >9@ Figure 31-12. ATmega164PA: Reset pull-up resistor current vs. reset pin voltage (VCC = 1.8V) 9FF9 >&@ ,5( 6 (7 >X$@ 2018 Microchip Technology Inc. 95( 6 (7 >9@ Data Sheet Complete DS40002070A-page 559 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-13. ATmega164PA: Reset pull-up resistor current vs. reset pin voltage (VCC = 2.7V) >&@ ,5( 6 (7 >X$@ 95( 6 (7 >9@ Figure 31-14. ATmega164PA: Reset pull-up resistor current vs. reset pin voltage (VCC = 5V) >&@ ,5( 6 (7 >X$@ 95( 6 (7 >9@ 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 560 ATmega164A/PA/324A/PA/644A/PA/1284/P 31.1.5 Pin driver strength Figure 31-15. ATmega164PA: I/O pin output voltage vs. sink current (VCC = 3V) >&@ 92/ >9@ ,2/ >P$@ Figure 31-16. ATmega164PA: I/O pin output voltage vs. sink current (VCC = 5V) 92/ >9@ 2018 Microchip Technology Inc. ,2/ >P$@ Data Sheet Complete DS40002070A-page 561 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-17. ATmega164PA: I/O pin output voltage vs. source current (VCC = 3V) >&@ 92+ >9@ ,2+ >P$@ Figure 31-18. ATmega164PA: I/O pin output voltage vs. source current (VCC = 5V) 92+ >9@ >&@ 2018 Microchip Technology Inc. ,2+ >P$@ Data Sheet Complete DS40002070A-page 562 ATmega164A/PA/324A/PA/644A/PA/1284/P 31.1.6 Pin threshold and hysteresis Figure 31-19. ATmega164PA: I/O pin input threshold vs. VCC (VIH , I/O pin read as `1') >&@ 7KUHVKROG>9@ 9&& >9@ Figure 31-20. ATmega164PA: I/O pin input threshold vs. VCC (VIL, I/O pin read as `0') >&@ 7KUHVKROG>9@ 2018 Microchip Technology Inc. 9&& >9@ Data Sheet Complete DS40002070A-page 563 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-21. ATmega164PA: I/O pin input hysteresis vs. VCC ,QSXW+\VWHUHVLV>P9@ >&@ 9&& >9@ Figure 31-22. ATmega164PA: Reset pin input threshold vs. VCC (VIH , I/O pin read as `1') >&@ 7KUHVKROG>9@ 2018 Microchip Technology Inc. 9&& >9@ Data Sheet Complete DS40002070A-page 564 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-23. ATmega164PA: Reset pin input threshold vs. VCC (VIL, I/O pin read as `0') >&@ 7KUHVKROG>9@ 9&& >9@ Figure 31-24. ATmega164PA: Reset pin input hysteresis vs. VCC >&@ ,QSXW+\VWHUHVLV>P9@ 2018 Microchip Technology Inc. 9&& >9@ Data Sheet Complete DS40002070A-page 565 ATmega164A/PA/324A/PA/644A/PA/1284/P 31.1.7 BOD threshold Figure 31-25. ATmega164PA: BOD threshold vs. temperature (VBOT = 4.3V) 7KUHVKROG>9@ 5LVLQJ9FF )DOOLQJ9FF 7HPSHUDWXUH>&@ Figure 31-26. ATmega164PA: BOD threshold vs. temperature (VBOT = 2.7V) 7KUHVKROG>9 5LVLQJ9FF )DOOLQJ9FF 2018 Microchip Technology Inc. 7HPSHUDWXUH>&@ Data Sheet Complete DS40002070A-page 566 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-27. ATmega164PA: BOD threshold vs. temperature (VBOT = 1.8V) 7KUHVKROG>9@ 5LVLQJ9FF )DOOLQJ9FF 7HPSHUDWXUH>&@ Figure 31-28. ATmega164PA: Calibrated bandgap voltage vs. VCC %DQGJDS9ROWDJH>9@ >&@ 9FF>9@ 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 567 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-29. ATmega164PA: Bandgap voltage vs. temperature >9@ %DQGJDS9ROWDJH 9 7HPSHUDWXUH >&@ 31.1.8 Internal oscillator speed Figure 31-30. ATmega164PA: Watchdog oscillator frequency vs. temperature >9@ )5& N+]@ 2018 Microchip Technology Inc. 7HPSHUDWXUH>&@ Data Sheet Complete DS40002070A-page 568 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-31. ATmega164PA: Watchdog oscillator frequency vs. VCC >&@ )5& >N+]@ 9&& >9@ Figure 31-32. ATmega164PA: Calibrated 8MHz RC oscillator vs. VCC >&@ )5& >0+]@ 2018 Microchip Technology Inc. 9&& >9@ Data Sheet Complete DS40002070A-page 569 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-33. ATmega164PA: Calibrated 8MHz RC oscillator vs. temperature 9 9 )5& >0+]@ 7HPSHUDWXUH>&@ Figure 31-34. ATmega164PA: Calibrated 8MHz RC oscillator vs. OSCCAL value >&@ )5& >0+]@ 26& &$/>;@ 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 570 ATmega164A/PA/324A/PA/644A/PA/1284/P 31.1.9 Current consumption of peripheral units Figure 31-35. ATmega164PA: ADC current vs. VCC (AREF = AVCC) ,&& >X$@ 9&& >9@ Figure 31-36. ATmega164PA: Analog comparator current vs. VCC >&@ ,&& >X$@ 2018 Microchip Technology Inc. 9&& >9@ Data Sheet Complete DS40002070A-page 571 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-37. ATmega164PA: AREF external reference current vs. VCC >&@ ,&& >X$@ 9&& >9@ Figure 31-38. ATmega164PA: Brownout detector current vs. VCC >&@ ,&& >X$@ 2018 Microchip Technology Inc. 9&& >9@ Data Sheet Complete DS40002070A-page 572 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-39. ATmega164PA: Programming current vs. VCC >&@ ,&& >P$@ 9&& >9@ Figure 31-40. ATmega164PA: Watchdog timer current vs. VCC ,&& >X$@ 2018 Microchip Technology Inc. 9&& >9@ Data Sheet Complete DS40002070A-page 573 ATmega164A/PA/324A/PA/644A/PA/1284/P 31.1.10 Current consumption in reset and reset pulsewidth Figure 31-41. ATmega164PA: Minimum reset pulsewidth vs. VCC 3XOVHZLGWK>QV@ 9&& >9@ 31.2.1 ATmega324PA Typical Characteristics - TA = -40C to 105C Active Supply Current Figure 31-42. Active Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) 7 105 C 85 C 25 C -40 C 6 5 ICC (mA) 31.2 4 3 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 574 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-43. Active Supply Current vs. VCC (Internal RC Oscillator, 1 MHz) 1.6 105 C 85 C 25 C -40 C 1.4 1.2 ICC (mA) 1 0.8 0.6 0.4 0.2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 31-44. Active Supply Current vs. VCC (Internal RC Oscillator, 128 kHz) 0.25 -40 C 25 C 105 C 85 C ICC (mA) 0.2 0.15 0.1 0.05 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 575 ATmega164A/PA/324A/PA/644A/PA/1284/P Idle Supply Current Figure 31-45. Idle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) 1.8 105 C 85 C 25 C -40 C 1.6 1.4 ICC (mA) 1.2 1 0.8 0.6 0.4 0.2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 31-46. Idle Supply Current vs. VCC (Internal RC Oscillator, 1 MHz) 0.7 105 C 85 C 25 C -40 C 0.6 0.5 ICC (mA) 31.2.2 0.4 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 576 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-47. Idle Supply Current vs. VCC (Internal RC Oscillator, 128 kHz) 0.12 -40 C 105 C 25 C 85 C 0.1 ICC (mA) 0.08 0.06 0.04 0.02 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Power-down Supply Current Figure 31-48. Power-down Supply Current vs. VCC (Watchdog Timer Disabled) 3 105 C 2.5 2 ICC (uA) 31.2.3 1.5 85 C 1 0.5 25 C -40 C 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 577 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-49. Power-down Supply Current vs. VCC (Watchdog Timer Enabled) 10 105 C -40 C 85 C 25 C ICC (uA) 8 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Pin Pull-up Figure 31-50. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8V) 50 45 40 35 IOP (uA) 31.2.4 30 25 20 15 25 C 85 C -40 C 105 C 10 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VOP (V) 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 578 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-51. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V) 80 70 60 IOP (uA) 50 40 30 20 25 C 85 C 105 C -40 C 10 0 0 0.5 1 1.5 2 2.5 3 VOP (V) Figure 31-52. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V) 140 120 IOP (uA) 100 80 60 40 25 C 85 C 105 C -40 C 20 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VOP (V) 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 579 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-53. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V) 35 30 IRESET (uA) 25 20 15 10 -40 C 25 C 85 C 105 C 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 VRESET (V) Figure 31-54. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) 60 50 IRESET (uA) 40 30 20 25 C -40 C 85 C 105 C 10 0 0 0.5 1 1.5 2 2.5 3 VRESET (V) 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 580 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-55. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V) 120 100 IRESET (uA) 80 60 40 25 C -40 C 85 C 105 C 20 0 0 1 2 3 4 5 VRESET (V) Pin Driver Strength Figure 31-56. I/O Pin Output Voltage vs. Sink Current (VCC = 3V) 1 105 C 0.9 85 C 0.8 0.7 VOL (V) 31.2.5 25 C 0.6 -40 C 0.5 0.4 0.3 0.2 0.1 0 0 4 8 12 16 20 Load current (mA) 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 581 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-57. I/O Pin Output Voltage vs. Sink Current (VCC = 5V) 0.6 105 C 85 C 0.5 25 C VOL (V) 0.4 -40 C 0.3 0.2 0.1 0 0 4 8 12 16 20 Load current (mA) Figure 31-58. I/O Pin Output Voltage vs. Source Current (VCC = 3V) 3.5 3 VOH (V) 2.5 -40 C 25 C 85 C 105 C 2 1.5 1 0.5 0 0 4 8 12 16 20 Load current (mA) 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 582 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-59. I/O Pin Output Voltage vs. Source Current (VCC = 5V) 5 4.9 VOH (V) 4.8 4.7 4.6 -40 C 4.5 25 C 4.4 85 C 105 C 4.3 0 4 8 12 16 20 Load current (mA) Pin Threshold and Hysteresis Figure 31-60. I/O Pin Input Threshold vs. VCC (VIH , I/O Pin Read as `1') 3 -40 C 25 C 85 C 105 C 2.5 Threshold (V) 31.2.6 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 583 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-61. I/O Pin Input Threshold vs. VCC (VIL, I/O Pin Read as `0') 2.5 105 C 85 C 25 C -40 C Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 31-62. I/O Pin Input Hysteresis vs. VCC 0.6 -40 C 25 C 85 C 105 C Input Hysteresis (mV) 0.5 0.4 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 584 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-63. Reset Pin Input Threshold vs. VCC (VIH , I/O Pin Read as `1') 2.5 -40 C 25 C 85 C 105 C Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 31-64. Reset Pin Input Threshold vs. VCC (VIL, I/O Pin Read as `0') 2.5 105 C 85 C 25 C -40 C Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 585 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-65. Reset Pin Input Hysteresis vs. VCC 0.7 Input Hysteresis (mV) 0.6 0.5 0.4 0.3 0.2 -40 C 25 C 85 C 105 C 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 90 100 110 VCC (V) BOD Threshold Figure 31-66. BOD Threshold vs. Temperature (VCC = 4.3V) 4.4 Rising Vcc 4.38 Threshold (V) 31.2.7 4.36 4.34 4.32 Falling Vcc 4.3 4.28 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 Temperature (C) 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 586 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-67. BOD Threshold vs. Temperature (VCC = 2.7V) 2.79 Rising Vcc Threshold (V) 2.77 2.75 2.73 2.71 Falling Vcc 2.69 2.67 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 60 70 80 90 100 110 Temperature (C) Figure 31-68. BOD Threshold vs. Temperature (VCC = 1.8V) 1.85 Rising Vcc 1.84 Threshold (V) 1.83 1.82 Falling Vcc 1.81 1.8 1.79 1.78 -40 -30 -20 -10 0 10 20 30 40 50 Temperature (C) 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 587 ATmega164A/PA/324A/PA/644A/PA/1284/P Internal Oscillator Speed Figure 31-69. Watchdog Oscillator Frequency vs. Temperature 122 120 FRC (kHz) 118 116 114 1.8 V 2.7 V 3.3 V 4.0 V 5.5 V 112 110 108 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 Temperature (C) Figure 31-70. Watchdog Oscillator Frequency vs. VCC 122 FRC (kHz) 31.2.8 120 -40 C 118 25 C 116 114 85 C 112 105 C 110 108 106 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 588 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-71. Calibrated 8 MHz RC Oscillator vs. VCC 8.6 105 C 85 C 8.4 FRC (MHz) 8.2 25 C 8 7.8 7.6 -40 C 7.4 7.2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 31-72. Calibrated 8 MHz RC Oscillator vs. Temperature 8.6 5.0 V 3.0 V 8.4 FRC (MHz) 8.2 8 7.8 7.6 7.4 7.2 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 Temperature (C) 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 589 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-73. Calibrated 8 MHz RC Oscillator vs. OSCCAL Value 14 105 C 85 C 25 C -40 C 12 FRC (MHz) 10 8 6 4 2 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL (X1) Current Consumption of Peripheral Units Figure 31-74. ADC Current vs. VCC (AREF = AVCC) 300 25 C -40 C 85 C 105 C 250 200 ICC (uA) 31.2.9 150 100 50 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 590 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-75. Analog Comparator Current vs. VCC 90 -40 C 25 C 105 C 85 C 80 70 ICC (uA) 60 50 40 30 20 10 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 31-76. AREF External Reference Current vs. VCC 200 25 C 105 C 85 C -40 C ICC (uA) 160 120 80 40 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 591 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-77. Brownout Detector Current vs. VCC 30 105 C 85 C 25 C -40 C 25 ICC (uA) 20 15 10 5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 31-78. Programming Current vs. VCC 14 25 C -40 C 85 C 105 C 12 ICC (mA) 10 8 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 592 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-79. Watchdog Timer Current vs. VCC 9 -40 C 25 C 85 C 105 C 8 7 ICC (uA) 6 5 4 3 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Current Consumption in Reset and Reset Pulsewidth Figure 31-80. Minimum Reset Pulsewidth vs. Vcc 1800 1500 Pulsewidth (ns) 31.2.10 1200 900 600 105 C 85 C 25 C -40 C 300 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 593 ATmega164A/PA/324A/PA/644A/PA/1284/P Active Supply Current Figure 31-81. Active Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) 7 105 C 85 C 25 C -40 C 6 5 ICC (mA) 31.3.1 ATmega644PA Typical Characteristics - TA = -40C to 105C 4 3 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 31-82. Active Supply Current vs. VCC (Internal RC Oscillator, 1 MHz) 1.4 105 C 85 C 25 C -40 C 1.2 1 ICC (mA) 31.3 0.8 0.6 0.4 0.2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 594 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-83. Active Supply Current vs. VCC (Internal RC Oscillator, 128 kHz) 0.24 -40 C 25 C 105 C 85 C 0.21 0.18 ICC (mA) 0.15 0.12 0.09 0.06 0.03 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Idle Supply Current Figure 31-84. Idle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) 1.4 105 C 85 C 25 C -40 C 1.2 1 ICC (mA) 31.3.2 0.8 0.6 0.4 0.2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 595 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-85. Idle Supply Current vs. VCC (Internal RC Oscillator, 1 MHz) 105 C 85 C 25 C -40 C 0.36 0.3 ICC (mA) 0.24 0.18 0.12 0.06 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 31-86. Idle Supply Current vs. VCC (Internal RC Oscillator, 128 kHz) 105 C 85 C 25 C -40 C 0.36 0.3 ICC (mA) 0.24 0.18 0.12 0.06 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 596 ATmega164A/PA/324A/PA/644A/PA/1284/P Power-down Supply Current Figure 31-87. Power-down Supply Current vs. VCC (Watchdog Timer Disabled) 6 105 C 5 ICC (uA) 4 3 85 C 2 1 25 C -40 C 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 31-88. Power-down Supply Current vs. VCC (Watchdog Timer Enabled) 14 105 C 12 10 ICC (uA) 31.3.3 85 C -40 C 25 C 8 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 597 ATmega164A/PA/324A/PA/644A/PA/1284/P Pin Pull-up Figure 31-89. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8V) 50 IOP (uA) 40 30 20 10 25 C 85 C -40 C 105 C 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 VOP (V) Figure 31-90. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V) 80 70 60 50 IOP (uA) 31.3.4 40 30 20 25 C 85 C -40 C 105 C 10 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 VOP (V) 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 598 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-91. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V) 140 120 IOP (uA) 100 80 60 40 25 C 85 C -40 C 105 C 20 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VOP (V) Figure 31-92. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V) 35 30 IRESET (uA) 25 20 15 10 25 C -40 C 85 C 105 C 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 VRESET (V) 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 599 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-93. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) 60 50 IRESET (uA) 40 30 20 25 C -40 C 85 C 105 C 10 0 0 0.5 1 1.5 2 2.5 3 VRESET (V) Figure 31-94. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V) 110 100 90 80 IRESET (uA) 70 60 50 40 30 25 C -40 C 85 C 105 C 20 10 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VRESET (V) 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 600 ATmega164A/PA/324A/PA/644A/PA/1284/P Pin Driver Strength Figure 31-95. I/O Pin Output Voltage vs. Sink Current (VCC = 3V) 1 105 C 85 C 0.9 0.8 0.7 25 C VOL (V) 0.6 -40 C 0.5 0.4 0.3 0.2 0.1 0 0 2 4 6 8 10 12 14 16 18 20 Load current (mA) Figure 31-96. I/O Pin Output Voltage vs. Sink Current (VCC = 5V) 0.6 105 C 85 C 0.5 25 C 0.4 VOL (V) 31.3.5 -40 C 0.3 0.2 0.1 0 0 2 4 6 8 10 12 14 16 18 20 Load current (mA) 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 601 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-97. I/O Pin Output Voltage vs. Source Current (VCC = 3V) 3.1 2.9 VOH (V) 2.7 2.5 -40 C 2.3 25 C 2.1 85 C 105 C 1.9 1.7 0 2 4 6 8 10 12 14 16 18 20 Load current (mA) Figure 31-98. I/O Pin Output Voltage vs. Source Current (VCC = 5V) 5.1 5 VOH (V) 4.9 4.8 4.7 4.6 -40 C 4.5 25 C 85 C 105 C 4.4 4.3 0 2 4 6 8 10 12 14 16 18 20 Load current (mA) 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 602 ATmega164A/PA/324A/PA/644A/PA/1284/P Pin Threshold and Hysteresis Figure 31-99. I/O Pin Input Threshold vs. VCC (VIH , I/O Pin Read as `1') 105 C 85 C 25 C -40 C 3 2.7 Threshold (V) 2.4 2.1 1.8 1.5 1.2 0.9 0.6 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 31-100. I/O Pin Input Threshold vs. VCC (VIL, I/O Pin Read as `0') 2.5 105 C 85 C 25 C -40 C 2 Threshold (V) 31.3.6 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 603 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-101. I/O Pin Input Hysteresis vs. VCC 0.6 -40 C 25 C 85 C 105 C Input Hysteresis (mV) 0.5 0.4 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 31-102. Reset Pin Input Threshold vs. VCC (VIH , I/O Pin Read as `1') 2.4 -40 C 25 C 85 C 105 C 2.1 Threshold (V) 1.8 1.5 1.2 0.9 0.6 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 604 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-103. Reset Pin Input Threshold vs. VCC (VIL, I/O Pin Read as `0') 2.4 105 C 85 C 25 C -40 C 2.1 Threshold (V) 1.8 1.5 1.2 0.9 0.6 0.3 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 31-104. Reset Pin Input Hysteresis vs. VCC 0.7 Input Hysteresis (mV) 0.6 0.5 0.4 0.3 0.2 -40 C 25 C 85 C 105 C 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 605 ATmega164A/PA/324A/PA/644A/PA/1284/P BOD Threshold Figure 31-105. BOD Threshold vs. Temperature (VCC = 4.3V) 4.37 Rising Vcc 4.35 Threshold (V) 4.33 4.31 4.29 Falling Vcc 4.27 4.25 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 Temperature (C) Figure 31-106. BOD Threshold vs. Temperature (VCC = 2.7V) 2.775 Rising Vcc 2.755 2.735 Threshold (V) 31.3.7 2.715 Falling Vcc 2.695 2.675 2.655 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 Temperature (C) 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 606 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-107. BOD Threshold vs. Temperature (VCC = 1.8V) 1.825 Rising Vcc Threshold (V) 1.815 1.805 1.795 Falling Vcc 1.785 1.775 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 Temperature (C) Internal Oscillator Speed Figure 31-108. Watchdog Oscillator Frequency vs. Temperature 120 118 116 FRC (kHz) 31.3.8 114 112 2.1 V 110 3.3 V 4.5 V 5.5 V 108 106 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 Temperature (C) 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 607 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-109. Watchdog Oscillator Frequency vs. VCC 120 FRC (kHz) 118 116 -40 C 114 25 C 112 110 85 C 108 105 C 106 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 31-110. Calibrated 8 MHz RC Oscillator vs. VCC 8.4 105 C 85 C 8.3 8.2 25 C FRC (MHz) 8.1 8 7.9 -40 C 7.8 7.7 7.6 7.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 608 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-111. Calibrated 8 MHz RC Oscillator vs. Temperature 8.4 5.5 V 4.5 V 3.6 V 2.7 V 8.3 8.2 FRC (MHz) 8.1 1.8 V 8 7.9 7.8 7.7 7.6 7.5 7.4 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 Temperature (C) Figure 31-112. Calibrated 8 MHz RC Oscillator vs. OSCCAL Value 16 105 C 85 C 25 C -40 C 14 FRC (MHz) 12 10 8 6 4 2 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL (X1) 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 609 ATmega164A/PA/324A/PA/644A/PA/1284/P Current Consumption of Peripheral Units Figure 31-113. ADC Current vs. VCC (AREF = AVCC) 250 105 C 85 C 25 C -40 C 225 ICC (uA) 200 175 150 125 100 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 31-114. Analog Comparator Current vs. VCC 90 -40 C 80 25 C 85 C 105 C 70 ICC (uA) 31.3.9 60 50 40 30 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 610 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-115. AREF External Reference Current vs. VCC 200 105 C 85 C 25 C -40 C 175 150 ICC (uA) 125 100 75 50 25 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 31-116. Brownout Detector Current vs. VCC 25 105 C 85 C 25 C -40 C ICC (uA) 22 19 16 13 10 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 611 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-117. Programming Current vs. VCC -40 C 16 14 12 ICC (mA) 10 25 C 8 85 C 105 C 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 31-118. Watchdog Timer Current vs. VCC 8 -40 C 25 C 85 C 105 C 7 6 ICC (uA) 5 4 3 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 612 ATmega164A/PA/324A/PA/644A/PA/1284/P 31.3.10 Current Consumption in Reset and Reset Pulsewidth Figure 31-119. Minimum Reset Pulsewidth vs. Vcc 1800 1600 Pulsewidth (ns) 1400 1200 1000 800 600 105 C 85 C 25 C -40 C 400 200 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 31.4 ATmega1284P typical characteristics - TA = -40C to 105C 31.4.1 Active supply current Figure 31-120. ATmega1284P: Active supply current vs. VCC (internal RC oscillator, 8MHz) ,&& >P$@ & & & & 9&& >9@ 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 613 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-121. ATmega1284P: Active supply current vs. VCC (internal RC oscillator, 1MHz) >&@ ,&& >P$@ 9&& >9@ . Figure 31-122. ATmega1284P: Active supply current vs. VCC (internal RC oscillator, 128kHz) >&@ ,&& >P$@ & 9&& >9@ . 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 614 ATmega164A/PA/324A/PA/644A/PA/1284/P 31.4.2 Idle supply current Figure 31-123. ATmega1284P: Idle supply current vs. VCC (internal RC oscillator, 8MHz) & & & & ,&& >P$@ 9&& >9@ Figure 31-124. ATmega1284P: Idle supply current vs. VCC (internal RC oscillator, 1MHz) ,&& >P$@ >&@ 9&& >9@ 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 615 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-125. ATmega1284P: Idle supply current vs. VCC (internal RC oscillator, 128kHz) >&@ ,&& >P$@ 9&& >9@ 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 616 ATmega164A/PA/324A/PA/644A/PA/1284/P 31.4.3 Power-down supply current Figure 31-126. ATmega1284P: Power-down supply current vs. VCC (watchdog timer disabled) & ,&& >X$@ & & & 9&& >9@ Figure 31-127. ATmega1284P: Power-down supply current vs. VCC (watchdog timer enabled) ,&& >X$@ >&@ 9&& >9@ 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 617 ATmega164A/PA/324A/PA/644A/PA/1284/P 31.4.4 Power-save supply current Figure 31-128. ATmega1284P: Power-save supply current vs. VCC (watchdog timer disabled and 32kHz crystal oscillator running) * DD <"> >&@ 7DD <7> 31.4.5 Pin pull-up Figure 31-129. ATmega1284P: I/O pin pull-up resistor current vs. input voltage (VCC = 1.8V) ,23 >X$@ >&@ 923 >9@ 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 618 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-130. ATmega1284P: I/O pin pull-up resistor current vs. input voltage (VCC = 2.7V) ,23 >X$@ >&@ 923 >9@ Figure 31-131. ATmega1284P: I/O pin pull-up resistor current vs. input voltage (VCC = 5V) ,23 >X$ >&@ 923 >9@ 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 619 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-132. ATmega1284P: Reset pull-up resistor current vs. reset pin voltage (VCC = 1.8V) ,5( 6 (7 >X$@ >&@ 95(6( 7 >9@ Figure 31-133. ATmega1284P: Reset pull-up resistor current vs. reset pin voltage (VCC = 2.7V) ,5( 6 (7 >X$@ >&@ 95(6( 7 >9@ 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 620 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-134. ATmega1284P: Reset pull-up resistor current vs. reset pin voltage (VCC = 5V) ,5( 6 (7 >X$@ >&@ 95(6( 7 >9@ 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 621 ATmega164A/PA/324A/PA/644A/PA/1284/P 31.4.6 Pin driver strength Figure 31-135. ATmega1284P: I/O pin output voltage vs. sink current (VCC = 2.7V) 92/ >9@ >&@ , 2/ >P$@ Figure 31-136. ATmega1284P: I/O pin output voltage vs. sink current (VCC = 3V) 92/ >9@ >&@ , 2/ >P$@ 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 622 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-137. ATmega1284P: I/O pin output voltage vs. sink current (VCC = 5V) >&@ 92/ >9@ , 2/ >P$@ Figure 31-138. ATmega1284P: I/O pin output voltage (VOH) vs. source current (VCC = 2.7V) 92+ >9@ >&@ , 2+ >P$@ 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 623 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-139. ATmega1284P: I/O pin output voltage vs. source current (VCC = 3V) 92+ >9@ >&@ , 2+>P$@ 31.4.7 Pin threshold and hysteresis Figure 31-140. ATmega1284P: I/O pin input threshold vs. VCC (VIH , I/O pin read as `1') 7KUHVKROG>9@ >&@ 9&& >9@ 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 624 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-141. ATmega1284P: I/O pin input threshold vs. VCC (VIL, I/O pin read as `0') >&@ 7KUHVKROG>9@ 9&& >9@ Figure 31-142. ATmega1284P: I/O pin input hysteresis vs. VCC ,QSXW+\VWHUHVLV P9 >&@ 9&& >9@ 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 625 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-143. ATmega1284P: Reset pin input threshold vs. VCC (VIH , I/O pin read as `1') 7KUHVKROG>9@ >&@ 9&& >9@ Figure 31-144. ATmega1284P: Reset pin input threshold vs. VCC (VIL, I/O pin read as `0') 7KUHVKROG>9@ >&@ 9&& >9@ 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 626 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-145. ATmega1284P: Reset pin input hysteresis vs. VCC ,QSXW+\VWHUHVLV>P9@ >&@ 9&& >9@ 31.4.8 BOD threshold Figure 31-146. ATmega1284P: BOD threshold vs. temperature (VBOT = 4.3V) 7KUHVKROG>9@ 5LVLQJ9FF )DOOLQJ9FF 7HPSHUDWXUH>&@ 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 627 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-147. ATmega1284P: BOD threshold vs. temperature (VBOT = 2.7V) 7KUHVKROG>9@ 5LVLQJ9FF )DOOLQJ9FF 7HPSHUDWXUH>&@ Figure 31-148. ATmega1284P: BOD threshold vs. temperature (VBOT = 1.8V) 7KUHVKROG>9@ 5LVLQJ9FF )DOOLQJ9FF 7HPSHUDWXUH>&@ 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 628 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-149. ATmega1284P: Calibrated bandgap voltage vs. VCC %DQGJDS9ROWDJH>9@ >&@ 9FF>9@ Figure 31-150. ATmega1284P: Bandgap voltage vs. temperature %DQGJDS9ROWDJH>9@ >9@ 7HPSHUDWXUH>&@ 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 629 ATmega164A/PA/324A/PA/644A/PA/1284/P 31.4.9 Internal oscillator speed Figure 31-151. ATmega1284P: Watchdog oscillator frequency vs. temperature )5& >N+]@ >9@ 7HPSHUDWXUH>&@ Figure 31-152. ATmega1284P: Watchdog oscillator frequency vs. VCC )5& >N+]@ >9@ 7HPSHUDWXUH>&@ 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 630 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-153. ATmega1284P: Calibrated 8MHz RC oscillator vs. VCC >&@ )5& >0+]@ 9&& >9@ Figure 31-154. ATmega1284P: Calibrated 8MHz RC oscillator vs. temperature )5& >0+]@ >9@ 7HPSHUDWXUH >&@ 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 631 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-155. ATmega1284P: Calibrated 8MHz RC oscillator vs. OSCCAL value ) 5&>0+]@ >&@ 26& &$/>;@ 31.4.10 Current consumption of peripheral units Figure 31-156. ATmega1284P: ADC current vs. VCC (AREF = AVCC) >&@ ,&& >X$@ 9&& >9@ 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 632 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-157. ATmega1284P: Analog comparator current vs. VCC >&@ ,&& > X$@ 9&& >9@ Figure 31-158. ATmega1284P: AREF external reference current vs. VCC >&@ ,&& >X$@ 9&& >9@ 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 633 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-159. ATmega1284P: Brownout detector current vs. VCC ,&&>X$@ >&@ 9&& >9@ Figure 31-160. ATmega1284P: Programming current vs. VCC ,&& >P$@ >&@ 2018 Microchip Technology Inc. 9&& >9@ Data Sheet Complete DS40002070A-page 634 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-161. ATmega1284P: Watchdog timer current vs. VCC ,&& >X$@ 9&& >9@ 31.4.11 Current consumption in reset and reset pulsewidth Figure 31-162. ATmega1284P: Minimum reset pulsewidth vs. VCC 3XOVHZLGWK>QV@ >&@ 9&& >9@ 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 635 ATmega164A/PA/324A/PA/644A/PA/1284/P 32. Register summary Address (0xFF) Bit 7 Bit 6 Bit 5 Bit 4 Reserved Name - - - - Bit 3 Bit 2 Bit 1 Bit 0 - - - (0xFE) Reserved - - - - - - - - (0xFD) Reserved - - - - - - - - (0xFC) Reserved - - - - - - - - (0xFB) Reserved - - - - - - - (0xFA) Reserved - - - - - - - (0xF9) Reserved - - - - - - - (0xF8) Reserved - - - - - - - - (0xF7) Reserved - - - - - - - - (0xF6) Reserved - - - - - - - - (0xF5) Reserved - - - - - - - (0xF4) Reserved - - - - - - - - (0xF3) Reserved - - - - - - - - (0xF2) Reserved - - - - - - - - (0xF1) Reserved - - - - - - - (0xF0) Reserved - - - - - - - (0xEF) Reserved - - - - - - - (0xEE) Reserved - - - - - - - - (0xED) Reserved - - - - - - - - (0xEC) Reserved - - - - - - - - (0xEB) Reserved - - - - - - - (0xEA) Reserved - - - - - - - - (0xE9) Reserved - - - - - - - - (0xE8) Reserved - - - - - - - - (0xE7) Reserved - - - - - - - (0xE6) Reserved - - - - - - - - (0xE5) Reserved - - - - - - - - (0xE4) Reserved - - - - - - - - (0xE3) Reserved - - - - - - - (0xE2) Reserved - - - - - - - (0xE1) Reserved - - - - - - - (0xE0) Reserved - - - - - - - (0xDF) Reserved - - - - - - - - (0xDE) Reserved - - - - - - - - (0xDD) Reserved - - - - - - - - (0xDC) Reserved - - - - - - - (0xDB) Reserved - - - - - - - - (0xDA) Reserved - - - - - - - - (0xD9) Reserved - - - - - - - - (0xD8) Reserved - - - - - - - - (0xD7) Reserved - - - - - - - - (0xD6) Reserved - - - - - - - - (0xD5) Reserved - - - - - - - - (0xD4) Reserved - - - - - - - - (0xD3) Reserved - - - - - - - - (0xD2) Reserved - - - - - - - - (0xD1) Reserved - - - - - - - - (0xD0) Reserved - - - - - - - - (0xCF) Reserved - - - - - - - - (0xCE) UDR1 (0xCD) UBRR1H (0xCC) UBRR1L (0xCB) - - - USART1 I/O Data Register - - - Reserved - - - (0xCA) UCSR1C UMSEL11 UMSEL10 (0xC9) UCSR1B RXCIE1 TXCIE1 (0xC8) UCSR1A RXC1 TXC1 (0xC7) Reserved - - Page 193 USART1 Baud Rate Register High Byte 197/210 USART1 Baud Rate Register Low Byte 197/210 - - - - - UPM11 UPM10 USBS1 UCSZ11/UDORD0(5) UCSZ10/UCPHA0(5) UCPOL1 195/209 UDRIE1 RXEN1 TXEN1 UCSZ12 RXB81 TXB81 194/208 UDRE1 FE1 DOR1 UPE1 U2X1 MPCM1 193/208 - - - - - - - - - - - - (0xC6) UDR0 (0xC5) UBRR0H USART0 I/O Data Register (0xC4) UBRR0L (0xC3) Reserved - - (0xC2) UCSR0C UMSEL01 UMSEL00 (0xC1) UCSR0B RXCIE0 TXCIE0 193 USART0 Baud Rate Register High Byte 197/210 USART0 Baud Rate Register Low Byte 2018 Microchip Technology Inc. 197/210 - - - - - UPM01 UPM00 USBS0 UCSZ01/UDORD0(5) UCSZ00/UCPHA0(5) UCPOL0 195/209 UDRIE0 RXEN0 TXEN0 UCSZ02 RXB80 TXB80 194/208 Data Sheet Complete DS40002070A-page 636 ATmega164A/PA/324A/PA/644A/PA/1284/P Address (0xC0) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page UCSR0A Name RXC0 TXC0 UDRE0 FE0 DOR0 UPE0 U2X0 MPCM0 193/208 (0xBF) Reserved - - - - - - - - (0xBE) Reserved - - - - - - - - (0xBD) TWAMR TWAM6 TWAM5 TWAM4 TWAM3 TWAM2 TWAM1 TWAM0 - 239 (0xBC) TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN - TWIE 236 (0xBB) TWDR (0xBA) TWAR TWA6 TWA5 TWA4 TWA3 two-wire Serial Interface Data Register TWA2 TWA1 TWA0 TWGCE 238 239 (0xB9) TWSR TWS7 TWS6 TWS5 TWS4 TWS3 - TWPS1 TWPS0 237 (0xB8) TWBR (0xB7) Reserved - - - - - - - - two-wire Serial Interface Bit Rate Register 236 (0xB6) ASSR - EXCLK AS2 TCN2UB OCR2AUB OCR2BUB TCR2AUB TCR2BUB (0xB5) Reserved - - - - - - - - (0xB4) OCR2B Timer/Counter2 Output Compare Register B 163 (0xB3) OCR2A Timer/Counter2 Output Compare Register A 163 (0xB2) TCNT2 Timer/Counter2 (8 Bit) (0xB1) TCCR2B FOC2A FOC2B - - WGM22 CS22 CS21 CS20 161 159 163 162 (0xB0) TCCR2A COM2A1 COM2A0 COM2B1 COM2B0 - - WGM21 WGM20 (0xAF) Reserved - - - - - - - - (0xAE) Reserved - - - - - - - - (0xAD) Reserved - - - - - - - - (0xAC) Reserved - - - - - - - - (0xAB) Reserved - - - - - - - - (0xAA) Reserved - - - - - - - - (0xA9) Reserved - - - - - - - - (0xA8) Reserved - - - - - - - - (0xA7) Reserved - - - - - - - - (0xA6) Reserved - - - - - - - - (0xA5) Reserved - - - - - - - - (0xA4) Reserved - - - - - - - - (0xA3) Reserved - - - - - - - - (0xA2) Reserved - - - - - - - - (0xA1) Reserved - - - - - - - - (0xA0) Reserved - - - - - - - - (0x9F) Reserved - - - - - - - - (0x9E) Reserved - - - - - - - - (0x9D) Reserved - - - - - - - - (0x9C) Reserved - - - - - - - - (0x9B) OCR3BH Timer/Counter3 - Output Compare Register B High Byte(7) 140 (0x9A) OCR3BL Timer/Counter3 - Output Compare Register B Low Byte(7) 140 (0x99) OCR3AH Timer/Counter3 - Output Compare Register A High Byte(7) 140 (0x98) OCR3AL Timer/Counter3 - Output Compare Register A Low Byte(7) 140 (0x97) ICR3H Timer/Counter3 - Input Capture Register High Byte(7) 141 (0x96) ICR3L Timer/Counter3 - Input Capture Register Low Byte(7) 141 (0x95) TCNT3H Timer/Counter3 - Counter Register High Byte(7) 140 (0x94) TCNT3L Timer/Counter3 - Counter Register Low Byte(7) (0x93) Reserved - - - (0x92) TCCR3C FOC3A FOC3B - - - - - - 139 (0x91) TCCR3B ICNC3 ICES3 - WGM33 WGM32 CS32 CS31 CS30 138 136 - - - 140 - - (0x90) TCCR3A COM3A1 COM3A0 COM3B1 COM3B0 - - WGM31 WGM30 (0x8F) Reserved - - - - - - - - (0x8E) Reserved - - - - - - - - (0x8D) Reserved - - - - - - - - (0x8C) Reserved - - - - - - - - (0x8B) OCR1BH Timer/Counter1 - Output Compare Register B High Byte 140 (0x8A) OCR1BL Timer/Counter1 - Output Compare Register B Low Byte 140 (0x89) OCR1AH Timer/Counter1 - Output Compare Register A High Byte 140 (0x88) OCR1AL Timer/Counter1 - Output Compare Register A Low Byte 140 (0x87) ICR1H Timer/Counter1 - Input Capture Register High Byte 141 (0x86) ICR1L Timer/Counter1 - Input Capture Register Low Byte 141 (0x85) TCNT1H Timer/Counter1 - Counter Register High Byte 140 (0x84) TCNT1L Timer/Counter1 - Counter Register Low Byte (0x83) Reserved - - - (0x82) TCCR1C FOC1A FOC1B - - - - - - 139 (0x81) TCCR1B ICNC1 ICES1 - WGM13 WGM12 CS12 CS11 CS10 138 - - - 140 - - (0x80) TCCR1A COM1A1 COM1A0 COM1B1 COM1B0 - - WGM11 WGM10 136 (0x7F) DIDR1 - - - - - - AIN1D AIN0D 242 (0x7E) DIDR0 ADC7D ADC6D ADC5D ADC4D ADC3D ADC2D ADC1D ADC0D 261 (0x7D) Reserved - - - - - - - - 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 637 ATmega164A/PA/324A/PA/644A/PA/1284/P Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (0x7C) ADMUX Name REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 Page 257 (0x7B) ADCSRB - ACME - - - ADTS2 ADTS1 ADTS0 241 (0x7A) ADCSRA ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 258 (0x79) ADCH ADC Data Register High byte (0x78) ADCL ADC Data Register Low byte (0x77) Reserved - - - - - - - - (0x76) Reserved - - - - - - - - (0x75) Reserved - - - - - - - - (0x74) Reserved - - - - - - - - (0x73) PCMSK3 PCINT31 PCINT30 PCINT29 PCINT28 PCINT27 PCINT26 PCINT25 PCINT24 (0x72) Reserved - - - - - - - - 259 259 78 (0x71) TIMSK3 - - ICIE3 - - OCIE3B OCIE3A TOIE3 142 (0x70) TIMSK2 - - - - - OCIE2B OCIE2A TOIE2 164 (0x6F) TIMSK1 - - ICIE1 - - OCIE1B OCIE1A TOIE1 142 (0x6E) TIMSK0 - - - - - OCIE0B OCIE0A TOIE0 113 (0x6D) PCMSK2 PCINT23 PCINT22 PCINT21 PCINT20 PCINT19 PCINT18 PCINT17 PCINT16 78 (0x6C) PCMSK1 PCINT15 PCINT14 PCINT13 PCINT12 PCINT11 PCINT10 PCINT9 PCINT8 78 (0x6B) PCMSK0 PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 79 (0x6A) Reserved - - - - - - - - (0x69) EICRA - - ISC21 ISC20 ISC11 ISC10 ISC01 ISC00 75 (0x68) PCICR - - - - PCIE3 PCIE2 PCIE1 PCIE0 77 (0x67) Reserved - - - - - - - - (0x66) OSCCAL (0x65) PRR1 - - - - Oscillator Calibration Register - - - --PRTIM3 57 48 (0x64) PRR0 PRTWI PRTIM2 PRTIM0 PRUSART1 PRTIM1 PRSPI PRUSART0 PRADC 56 (0x63) Reserved - - - - - - - - (0x62) Reserved (0x61) CLKPR (0x60) WDTCSR - - - - - - - - CLKPCE - - - CLKPS3 CLKPS2 CLKPS1 CLKPS0 48 WDIF WDIE WDP3 WDCE WDE WDP2 WDP1 WDP0 67 I T H S V N Z C 19 0x3F (0x5F) SREG 0x3E (0x5E) SPH SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 20 0x3D (0x5D) SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 20 0x3C (0x5C) Reserved - - - - - - - - 0x3B (0x5B) Reserved - - - - - - - - 0x3A (0x5A) Reserved - - - - - - - - 0x39 (0x59) Reserved - - - - - - - - 0x38 (0x58) Reserved - - - - - - - - 0x37 (0x57) SPMCSR SPMIE RWWSB SIGRD RWWSRE BLBSET PGWRT PGERS SPMEN 0x36 (0x56) Reserved - - - - - - - - 293 0x35 (0x55) MCUCR JTD BODS(6) BODSE(6) PUD - - IVSEL IVCE 97/276 0x34 (0x54) MCUSR - - - JTRF WDRF BORF EXTRF PORF 66/276 0x33 (0x53) SMCR - - - - SM2 SM1 SM0 SE 55 0x32 (0x52) Reserved - - - - - - - - 0x31 (0x51) OCDR 0x30 (0x50) ACSR ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 0x2F (0x4F) Reserved - - - - - - - - On-Chip Debug Register 267 SPI 0 Data Register 258 0x2E (0x4E) SPDR 0x2D (0x4D) SPSR SPIF0 WCOL0 - - - - - SPI2X0 173 0x2C (0x4C) SPCR SPIE0 SPE0 DORD0 MSTR0 CPOL0 CPHA0 SPR01 SPR00 172 0x2B (0x4B) GPIOR2 General Purpose I/O Register 2 0x2A (0x4A) GPIOR1 General Purpose I/O Register 1 0x29 (0x49) Reserved 0x28 (0x48) OCR0B Timer/Counter0 Output Compare Register B 113 0x27 (0x47) OCR0A Timer/Counter0 Output Compare Register A 113 0x26 (0x46) TCNT0 Timer/Counter0 (8 Bit) 0x25 (0x45) TCCR0B FOC0A FOC0B - - WGM02 CS02 - - - - 174 37 37 - - - - 113 CS01 CS00 112 0x24 (0x44) TCCR0A COM0A1 COM0A0 COM0B1 COM0B0 - - WGM01 WGM00 113 0x23 (0x43) GTCCR TSM - - - - - PSRASY PSRSYNC 165 0x22 (0x42) EEARH - - - - 0x21 (0x41) EEARL EEPROM Address Register Low Byte 0x20 (0x40) EEDR EEPROM Data Register 0x1F (0x3F) EECR EEPROM Address Register High Byte - - EEPM1 EEPM0 EERIE 32 32 32 EEMPE EEPE EERE General Purpose I/O Register 0 32 0x1E (0x3E) GPIOR0 0x1D (0x3D) EIMSK - - - - - INT2 INT1 INT0 76 0x1C (0x3C) EIFR - - - - - INTF2 INTF1 INTF0 76 0x1B (0x3B) PCIFR - - - - PCIF3 PCIF2 PCIF1 PCIF0 77 0x1A (0x3A) Reserved - - - - - - - - 0x19 (0x39) Reserved - - - - - - - - 2018 Microchip Technology Inc. Data Sheet Complete 37 DS40002070A-page 638 ATmega164A/PA/324A/PA/644A/PA/1284/P Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 0x18 (0x38) Address TIFR3 Name - - ICF3 - - OCF3B OCF3A TOV3 144 0x17 (0x37) TIFR2 - - - - - OCF2B OCF2A TOV2 164 0x16 (0x36) TIFR1 - - ICF1 - - OCF1B OCF1A TOV1 143 0x15 (0x35) TIFR0 - - - - - OCF0B OCF0A TOV0 114 0x14 (0x34) Reserved - - - - - - - - 0x13 (0x33) Reserved - - - - - - - - 0x12 (0x32) Reserved - - - - - - - - 0x11 (0x31) Reserved - - - - - - - - 0x10 (0x30) Reserved - - - - - - - - 0x0F (0x2F) Reserved - - - - - - - - 0x0E (0x2E) Reserved - - - - - - - - 0x0D (0x2D) Reserved - - - - - - - - 0x0C (0x2C) Reserved - - - - - - - - 0x0B (0x2B) PORTD PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 98 0x0A (0x2A) DDRD DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 98 98 0x09 (0x29) PIND PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 0x08 (0x28) PORTC PORTC7 PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 98 0x07 (0x27) DDRC DDC7 DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 98 0x06 (0x26) PINC 0x05 (0x25) PORTB PINC7 PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 98 PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 97 0x04 (0x24) DDRB DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 97 0x03 (0x23) PINB PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 98 0x02 (0x22) PORTA PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 97 0x01 (0x21) DDRA DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 97 0x00 (0x20) PINA PINA7 PINA6 PINA5 PINA4 PINA3 PINA2 PINA1 PINA0 97 Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O registers within the address range $00 - $1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers 0x00 to 0x1F only. 4. When using the I/O specific commands IN and OUT, the I/O addresses $00 - $3F must be used. When addressing I/O registers as data space using LD and ST instructions, $20 must be added to these addresses. The ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from $60 - $FF, only the ST/STS/STD and LD/LDS/LDD instructions can be used. 5. USART in SPI Master Mode. 6. Only available in the ATmega164PA/324PA/644PA/1284P. 7. Only available in the ATmega1284/1284P 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 639 ATmega164A/PA/324A/PA/644A/PA/1284/P 33. Instruction set summary Mnemonics Operands Description Operation Flags #Clocks ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers Rd Rd + Rr Z,C,N,V,H 1 ADC Rd, Rr Add with Carry two Registers Rd Rd + Rr + C Z,C,N,V,H 1 ADIW Rdl,K Add Immediate to Word Rdh:Rdl Rdh:Rdl + K Z,C,N,V,S 2 SUB Rd, Rr Subtract two Registers Rd Rd - Rr Z,C,N,V,H 1 SUBI Rd, K Subtract Constant from Register Rd Rd - K Z,C,N,V,H 1 1 SBC Rd, Rr Subtract with Carry two Registers Rd Rd - Rr - C Z,C,N,V,H SBCI Rd, K Subtract with Carry Constant from Reg. Rd Rd - K - C Z,C,N,V,H 1 SBIW Rdl,K Subtract Immediate from Word Rdh:Rdl Rdh:Rdl - K Z,C,N,V,S 2 AND Rd, Rr Logical AND Registers Rd Rd Rr Z,N,V 1 ANDI Rd, K Logical AND Register and Constant Rd Rd K Z,N,V 1 OR Rd, Rr Logical OR Registers Rd Rd v Rr Z,N,V 1 ORI Rd, K Logical OR Register and Constant Rd Rd v K Z,N,V 1 EOR Rd, Rr Exclusive OR Registers Rd Rd Rr Z,N,V 1 COM Rd One's Complement Rd 0xFF Rd Z,C,N,V 1 NEG Rd Two's Complement Rd 0x00 Rd Z,C,N,V,H 1 SBR Rd,K Set Bit(s) in Register Rd Rd v K Z,N,V 1 CBR Rd,K Clear Bit(s) in Register Rd Rd (0xFF - K) Z,N,V 1 INC Rd Increment Rd Rd + 1 Z,N,V 1 DEC Rd Decrement Rd Rd 1 Z,N,V 1 TST Rd Test for Zero or Minus Rd Rd Rd Z,N,V 1 CLR Rd Clear Register Rd Rd Rd Z,N,V 1 SER Rd Set Register Rd 0xFF None 1 MUL Rd, Rr Multiply Unsigned R1:R0 Rd x Rr Z,C 2 MULS Rd, Rr Multiply Signed R1:R0 Rd x Rr Z,C 2 MULSU Rd, Rr Multiply Signed with Unsigned R1:R0 Rd x Rr Z,C 2 FMUL Rd, Rr Fractional Multiply Unsigned R1:R0 (Rd x Rr) << 1 Z,C 2 FMULS Rd, Rr Fractional Multiply Signed R1:R0 (Rd x Rr) << 1 Z,C 2 FMULSU Rd, Rr Fractional Multiply Signed with Unsigned R1:R0 (Rd x Rr) << 1 Z,C 2 Relative Jump PC PC + k + 1 None 2 Indirect Jump to (Z) PC Z None 2 Direct Jump PC k None 3 Relative Subroutine Call PC PC + k + 1 None 3 Indirect Call to (Z) PC Z None 3 BRANCH INSTRUCTIONS RJMP k IJMP JMP k RCALL k ICALL Direct Subroutine Call PC k None 4 RET Subroutine Return PC STACK None 4 RETI Interrupt Return PC STACK I Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC PC + 2 or 3 None CP Rd,Rr Compare Rd Rr Z, N,V,C,H CPC Rd,Rr Compare with Carry Rd Rr C Z, N,V,C,H 1 CPI Rd,K Compare Register with Immediate Rd K Z, N,V,C,H 1 CALL CPSE k 4 1/2/3 1 SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC PC + 2 or 3 None 1/2/3 SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1) PC PC + 2 or 3 None 1/2/3 SBIC P, b Skip if Bit in I/O Register Cleared if (P(b)=0) PC PC + 2 or 3 None 1/2/3 SBIS P, b Skip if Bit in I/O Register is Set if (P(b)=1) PC PC + 2 or 3 None 1/2/3 BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PCPC+k + 1 None 1/2 BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PCPC+k + 1 None 1/2 BREQ k Branch if Equal if (Z = 1) then PC PC + k + 1 None 1/2 BRNE k Branch if Not Equal if (Z = 0) then PC PC + k + 1 None 1/2 BRCS k Branch if Carry Set if (C = 1) then PC PC + k + 1 None 1/2 BRCC k Branch if Carry Cleared if (C = 0) then PC PC + k + 1 None 1/2 BRSH k Branch if Same or Higher if (C = 0) then PC PC + k + 1 None 1/2 BRLO k Branch if Lower if (C = 1) then PC PC + k + 1 None 1/2 BRMI k Branch if Minus if (N = 1) then PC PC + k + 1 None 1/2 BRPL k Branch if Plus if (N = 0) then PC PC + k + 1 None 1/2 BRGE k Branch if Greater or Equal, Signed if (N V= 0) then PC PC + k + 1 None 1/2 BRLT k Branch if Less Than Zero, Signed if (N V= 1) then PC PC + k + 1 None 1/2 BRHS k Branch if Half Carry Flag Set if (H = 1) then PC PC + k + 1 None 1/2 BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC PC + k + 1 None 1/2 BRTS k Branch if T Flag Set if (T = 1) then PC PC + k + 1 None 1/2 BRTC k Branch if T Flag Cleared if (T = 0) then PC PC + k + 1 None 1/2 BRVS k Branch if Overflow Flag is Set if (V = 1) then PC PC + k + 1 None 1/2 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 640 ATmega164A/PA/324A/PA/644A/PA/1284/P Mnemonics Operands Description Operation Flags #Clocks BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC PC + k + 1 None 1/2 BRIE k Branch if Interrupt Enabled if ( I = 1) then PC PC + k + 1 None 1/2 BRID k Branch if Interrupt Disabled if ( I = 0) then PC PC + k + 1 None 1/2 BIT AND BIT-TEST INSTRUCTIONS SBI P,b Set Bit in I/O Register I/O(P,b) 1 None 2 CBI P,b Clear Bit in I/O Register I/O(P,b) 0 None 2 LSL Rd Logical Shift Left Rd(n+1) Rd(n), Rd(0) 0 Z,C,N,V 1 LSR Rd Logical Shift Right Rd(n) Rd(n+1), Rd(7) 0 Z,C,N,V 1 ROL Rd Rotate Left Through Carry Rd(0)C,Rd(n+1) Rd(n),CRd(7) Z,C,N,V 1 ROR Rd Rotate Right Through Carry Rd(7)C,Rd(n) Rd(n+1),CRd(0) Z,C,N,V 1 ASR Rd Arithmetic Shift Right Rd(n) Rd(n+1), n=0..6 Z,C,N,V 1 SWAP Rd Swap Nibbles Rd(3..0)Rd(7..4),Rd(7..4)Rd(3..0) None 1 BSET s Flag Set SREG(s) 1 SREG(s) 1 BCLR s Flag Clear SREG(s) 0 SREG(s) 1 BST Rr, b Bit Store from Register to T T Rr(b) T 1 BLD Rd, b Bit load from T to Register Rd(b) T None 1 SEC Set Carry C1 C 1 CLC Clear Carry C0 C 1 SEN Set Negative Flag N1 N 1 CLN Clear Negative Flag N0 N 1 SEZ Set Zero Flag Z1 Z 1 CLZ Clear Zero Flag Z0 Z 1 SEI Global Interrupt Enable I1 I 1 CLI Global Interrupt Disable I 0 I 1 SES Set Signed Test Flag S1 S 1 1 CLS Clear Signed Test Flag S0 S SEV Set Twos Complement Overflow. V1 V 1 CLV Clear Twos Complement Overflow V0 V 1 SET Set T in SREG T1 T 1 CLT Clear T in SREG T0 T 1 SEH CLH Set Half Carry Flag in SREG Clear Half Carry Flag in SREG H1 H0 H H 1 1 None 1 None 1 DATA TRANSFER INSTRUCTIONS MOV Rd, Rr Move Between Registers MOVW Rd, Rr Copy Register Word Rd Rr Rd+1:Rd Rr+1:Rr LDI Rd, K Load Immediate Rd K None 1 LD Rd, X Load Indirect Rd (X) None 2 LD Rd, X+ Load Indirect and Post-Inc. Rd (X), X X + 1 None 2 LD Rd, - X Load Indirect and Pre-Dec. X X - 1, Rd (X) None 2 LD Rd, Y Load Indirect Rd (Y) None 2 LD Rd, Y+ Load Indirect and Post-Inc. Rd (Y), Y Y + 1 None 2 LD Rd, - Y Load Indirect and Pre-Dec. Y Y - 1, Rd (Y) None 2 LDD Rd,Y+q Load Indirect with Displacement Rd (Y + q) None 2 LD Rd, Z Load Indirect Rd (Z) None 2 LD Rd, Z+ Load Indirect and Post-Inc. Rd (Z), Z Z+1 None 2 LD Rd, -Z Load Indirect and Pre-Dec. Z Z - 1, Rd (Z) None 2 LDD Rd, Z+q Load Indirect with Displacement Rd (Z + q) None 2 LDS Rd, k Load Direct from SRAM Rd (k) None 2 ST X, Rr Store Indirect (X) Rr None 2 ST X+, Rr Store Indirect and Post-Inc. (X) Rr, X X + 1 None 2 2 ST - X, Rr Store Indirect and Pre-Dec. X X - 1, (X) Rr None ST Y, Rr Store Indirect (Y) Rr None 2 ST Y+, Rr Store Indirect and Post-Inc. (Y) Rr, Y Y + 1 None 2 ST - Y, Rr Store Indirect and Pre-Dec. Y Y - 1, (Y) Rr None 2 STD Y+q,Rr Store Indirect with Displacement (Y + q) Rr None 2 ST Z, Rr Store Indirect (Z) Rr None 2 ST Z+, Rr Store Indirect and Post-Inc. (Z) Rr, Z Z + 1 None 2 ST -Z, Rr Store Indirect and Pre-Dec. Z Z - 1, (Z) Rr None 2 STD Z+q,Rr Store Indirect with Displacement (Z + q) Rr None 2 STS k, Rr Store Direct to SRAM (k) Rr None 2 Load Program Memory R0 (Z) None 3 LPM LPM Rd, Z Load Program Memory Rd (Z) None 3 LPM Rd, Z+ Load Program Memory and Post-Inc Rd (Z), Z Z+1 None 3 Store Program Memory (Z) R1:R0 None - In Port Rd P None 1 1 SPM IN Rd, P OUT P, Rr Out Port P Rr None PUSH Rr Push Register on Stack STACK Rr None 2 POP Rd Pop Register from Stack Rd STACK None 2 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 641 ATmega164A/PA/324A/PA/644A/PA/1284/P Mnemonics Operands Description Operation Flags #Clocks MCU CONTROL INSTRUCTIONS NOP No Operation SLEEP Sleep (see specific descr. for Sleep function) None 1 WDR BREAK Watchdog Reset Break (see specific descr. for WDR/timer) For On-chip Debug Only None None 1 N/A 2018 Microchip Technology Inc. None Data Sheet Complete 1 DS40002070A-page 642 ATmega164A/PA/324A/PA/644A/PA/1284/P 34. Ordering information 34.1 ATmega164A Speed [MHz] (3) 20 Notes: Power supply 1.8 - 5.5V Ordering code(2) ATmega164A-AU ATmega164A-AUR(5) ATmega164A-PU ATmega164A-MU ATmega164A-MUR(5) ATmega164A-MCH(4) ATmega164A-MCHR(4)(5) ATmega164A-CU ATmega164A-CUR(5) Package(1) 44A 44A 40P6 44M1 44M1 44MC 44MC 49C2 49C2 Operational range Industrial (-40oC to 85oC) 1. This device can also be supplied in wafer form. Contact your local sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. For Speed vs. VCC see "Speed grades" on page 332. 4. NiPdAu Lead Finish. 5. Tape & Reel. Package Type 44A 44-lead, Thin (1.0mm) Plastic Gull Wing Quad Flat Package (TQFP) 40P6 40-pin, 0.600" Wide, Plastic Dual Inline Package (PDIP) 44M1 44-pad, 7 x 7 x 1.0mm body, lead pitch 0.50mm, Thermally Enhanced Plastic Very Thin Quad Flat No-Lead (VQFN) 44MC 44-lead (2-row Staggered), 5 x 5 x 1.0mm body, 2.60 x 2.60mm Exposed Pad, Quad Flat No-Lead Package (QFN) 49C2 49-ball, (7 x 7 Array) 0.65mm Pitch, 5 x 5 x 1mm, Very Thin, Fine-Pitch Ball Grid Array Package (VFBGA) 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 643 ATmega164A/PA/324A/PA/644A/PA/1284/P 34.2 ATmega164PA Speed [MHz] (3) 20 20 Notes: Power supply Ordering code (2) Package (1) Operational range 1.8 - 5.5V ATmega164PA-AU ATmega164PA-AUR(5) ATmega164PA-PU ATmega164PA-MU ATmega164PA-MUR(5) ATmega164PA-MCH(4) ATmega164PA-MCHR(4)(5) ATmega164PA-CU ATmega164PA-CUR(5) 44A 44A 40P6 44M1 44M1 44MC 44MC 49C2 49C2 Industrial (-40oC to 85oC) 1.8 - 5.5V ATmega164PA-AN ATmega164PA-ANR(5) ATmega164PA-PN ATmega164PA-MN ATmega164PA-MNR(5) 44A 44A 40P6 44M1 44M1 Industrial (-40oC to 105oC) 1. This device can also be supplied in wafer form. Contact your local sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. For Speed vs. VCC see "Speed grades" on page 332. 4. NiPdAu Lead Finish. 5. Tape & Reel. Package Type 44A 44-lead, Thin (1.0mm) Plastic Gull Wing Quad Flat Package (TQFP) 40P6 40-pin, 0.600" Wide, Plastic Dual Inline Package (PDIP) 44M1 44-pad, 7 x 7 x 1.0mm body, lead pitch 0.50mm, Thermally Enhanced Plastic Very Thin Quad Flat No-Lead (VQFN) 44MC 44-lead (2-row Staggered), 5 x 5 x 1.0mm body, 2.60 x 2.60mm Exposed Pad, Quad Flat No-Lead Package (QFN) 49C2 49-ball, (7 x 7 Array) 0.65mm Pitch, 5 x 5 x 1mm, Very Thin, Fine-Pitch Ball Grid Array Package (VFBGA) 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 644 ATmega164A/PA/324A/PA/644A/PA/1284/P 34.3 ATmega324A Speed [MHz] (3) 20 Notes: Power supply 1.8 - 5.5V Ordering code (2) ATmega324A-AU ATmega324A-AUR(5) ATmega324A-PU ATmega324A-MU ATmega324A-MUR(5) ATmega324A-MCH(4) ATmega324A-MCHR(4)(5) ATmega324A-CU ATmega324A-CUR(5) Package (1) 44A 44A 40P6 44M1 44M1 44MC 44MC 49C2 49C2 Operational range Industrial (-40oC to 85oC) 1. This device can also be supplied in wafer form. Contact your local sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. For Speed vs. VCC see "Speed grades" on page 332. 4. NiPdAu Lead Finish. 5. Tape & Reel. Package Type 44A 44-lead, Thin (1.0mm) Plastic Gull Wing Quad Flat Package (TQFP) 40P6 40-pin, 0.600" Wide, Plastic Dual Inline Package (PDIP) 44M1 44-pad, 7 x 7 x 1.0mm body, lead pitch 0.50mm, Thermally Enhanced Plastic Very Thin Quad Flat No-Lead (VQFN) 44MC 44-lead (2-row Staggered), 5 x 5 x 1.0mm body, 2.60 x 2.60mm Exposed Pad, Quad Flat No-Lead Package (QFN) 49C2 49-ball, (7 x 7 Array) 0.65mm Pitch, 5 x 5 x 1mm, Very Thin, Fine-Pitch Ball Grid Array Package (VFBGA) 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 645 ATmega164A/PA/324A/PA/644A/PA/1284/P 34.4 ATmega324PA Speed [MHz] (3) 20 20 Notes: Power supply Ordering code (2) Package (1) Operational range 1.8 - 5.5V ATmega324PA-AU ATmega324PA-AUR(5) ATmega324PA-PU ATmega324PA-MU ATmega324PA-MUR(5) ATmega324PA-MCH(4) ATmega324PA-MCHR(4)(5) ATmega324PA-CU ATmega324PA-CUR(5) 44A 44A 40P6 44M1 44M1 44MC 44MC 49C2 49C2 Industrial (-40oC to 85oC) 1.8 - 5.5V ATmega324PA-AN ATmega324PA-ANR(5) ATmega324PA-PN ATmega324PA-MN ATmega324PA-MNR(5) 44A 44A 40P6 44M1 44M1 Industrial (-40oC to 105oC) 1. This device can also be supplied in wafer form. Contact your local sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. For Speed vs. VCC see "Speed grades" on page 332. 4. NiPdAu Lead Finish. 5. Tape & Reel. Package Type 44A 44-lead, Thin (1.0mm) Plastic Gull Wing Quad Flat Package (TQFP) 40P6 40-pin, 0.600" Wide, Plastic Dual Inline Package (PDIP) 44M1 44-pad, 7 x 7 x 1.0mm body, lead pitch 0.50mm, Thermally Enhanced Plastic Very Thin Quad Flat No-Lead (VQFN) 44MC 44-lead (2-row Staggered), 5 x 5 x 1.0mm body, 2.60 x 2.60mm Exposed Pad, Quad Flat No-Lead Package (QFN) 49C2 49-ball, (7 x 7 Array) 0.65mm Pitch, 5 x 5 x 1mm, Very Thin, Fine-Pitch Ball Grid Array Package (VFBGA) 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 646 ATmega164A/PA/324A/PA/644A/PA/1284/P 34.5 ATmega644A Speed [MHz](3) 20 Notes: Power supply 1.8 - 5.5V Ordering code(2) ATmega644A-AU ATmega644A-AUR(4) ATmega644A-PU ATmega644A-MU ATmega644A-MUR(4) Package(1) 44A 44A 40P6 44M1 44M1 Operational range Industrial (-40oC to 85oC) 1. This device can also be supplied in wafer form. Contact your local sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. For Speed vs. VCC see "Speed grades" on page 332. 4. Taper & Reel. Package Type 44A 44-lead, Thin (1.0mm) Plastic Gull Wing Quad Flat Package (TQFP) 40P6 40-pin, 0.600" Wide, Plastic Dual Inline Package (PDIP) 44M1 44-pad, 7 x 7 x 1.0mm body, lead pitch 0.5 mm, Thermally Enhanced Plastic Very Thin Quad Flat No-Lead (VQFN) 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 647 ATmega164A/PA/324A/PA/644A/PA/1284/P 34.6 ATmega644PA Speed [MHz] (3) 20 20 Notes: Power supply Ordering code (2) Package (1) 1.8 - 5.5V ATmega644PA-AU ATmega644PA-AUR(4) ATmega644PA-PU ATmega644PA-MU ATmega644PA-MUR(4) 44A 44A 40P6 44M1 44M1 Industrial (-40oC to 85oC) 1.8 - 5.5V ATmega644PA-AN ATmega644PA-ANR(4) ATmega644PA-PN ATmega644PA-MN ATmega644PA-MNR(4) 44A 44A 40P6 44M1 44M1 Industrial (-40oC to 105oC) Operational range 1. This device can also be supplied in wafer form. Contact your local sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. For Speed vs. VCC see "Speed grades" on page 332. 4. Taper & Reel. Package Type 44A 44-lead, Thin (1.0mm) Plastic Gull Wing Quad Flat Package (TQFP) 40P6 40-pin, 0.600" Wide, Plastic Dual Inline Package (PDIP) 44M1 44-pad, 7 x 7 x 1.0mm body, lead pitch 0.50mm, Thermally Enhanced Plastic Very Thin Quad Flat No-Lead (VQFN) 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 648 ATmega164A/PA/324A/PA/644A/PA/1284/P 34.7 ATmega1284 Speed [MHz](3) 20 Notes: Power supply 1.8 - 5.5V Ordering code(2) ATmega1284-AU ATmega1284-AUR(4) ATmega1284-PU ATmega1284-MU ATmega1284-MUR(4) Package(1) 44A 44A 40P6 44M1 44M1 Operational range Industrial (-40oC to 85oC) 1. This device can also be supplied in wafer form. Contact your local sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. For Speed vs. VCC see "Speed grades" on page 332. 4. Tape & Reel. Package Type 44A 44-lead, Thin (1.0mm) Plastic Gull Wing Quad Flat Package (TQFP) 40P6 40-pin, 0.600" Wide, Plastic Dual Inline Package (PDIP) 44M1 44-pad, 7 x 7 x 1.0mm body, lead pitch 0.50mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 649 ATmega164A/PA/324A/PA/644A/PA/1284/P 34.8 ATmega1284P Speed [MHz] (3) 20 20 Notes: Power supply Ordering code (2) Package (1) 1.8 - 5.5V ATmega1284P-AU ATmega1284P-AUR(4) ATmega1284P-PU ATmega1284P-MU ATmega1284P-MUR(4) 44A 44A 40P6 44M1 44M1 Industrial (-40oC to 85oC) 1.8 - 5.5V ATmega1284P-AN ATmega1284P-ANR(4) ATmega1284P-PN ATmega1284P-MN ATmega1284P-MNR(4) 44A 44A 40P6 44M1 44M1 Industrial (-40oC to 105oC) Operational range 1. This device can also be supplied in wafer form. Contact your local sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. For Speed vs. VCC see "Speed grades" on page 332. 4. Tape & Reel. Package Type 44A 44-lead, Thin (1.0mm) Plastic Gull Wing Quad Flat Package (TQFP) 40P6 40-pin, 0.600" Wide, Plastic Dual Inline Package (PDIP) 44M1 44-pad, 7 x 7 x 1.0mm body, lead pitch 0.50mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 650 ATmega164A/PA/324A/PA/644A/PA/1284/P 35. Packaging information 35.1 44A PIN 1 IDENTIFIER PIN 1 B e E1 E A1 A2 D1 D C 0~7 A L COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10mm maximum. SYMBOL MIN NOM MAX A - - 1.20 A1 0.05 - 0.15 A2 0.95 1.00 1.05 D 11.75 12.00 12.25 D1 9.90 10.00 10.10 E 11.75 12.00 12.25 10.10 E1 9.90 10.00 B 0.300.37 0.45 C 0.09 (0.17) 0.20 L 0.45 0.60 0.75 e NOTE Note 2 Note 2 0.80 TYP 06/02/2014 44A, 44-lead, 10 x 10mm body size, 1.0mm body thickness, 0.8 mm lead pitch, thin profile plastic quad flat package (TQFP) 2018 Microchip Technology Inc. Data Sheet Complete 44A C DS40002070A-page 651 ATmega164A/PA/324A/PA/644A/PA/1284/P 35.2 40P6 D PIN 1 E1 A SEATING PLANE A1 L B B1 e E 0 ~ 15 C COMMON DIMENSIONS (Unit of Measure = mm) REF MIN NOM MAX A - - 4.826 A1 0.381 - - D 52.070 - 52.578 E 15.240 - 15.875 E1 13.462 - 13.970 B 0.356 - 0.559 B1 1.041 - 1.651 L 3.048 - 3.556 C 0.203 - 0.381 eB 15.494 - 17.526 SYMBOL eB Notes: 1. This package conforms to JEDEC reference MS-011, Variation AC. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25mm (0.010"). e NOTE Note 2 Note 2 2.540 TYP 13/02/2014 40P6, 40-lead (0.600"/15.24mm Wide) Plastic Dual Inline Package (PDIP) 2018 Microchip Technology Inc. Data Sheet Complete 40P6 C DS40002070A-page 652 ATmega164A/PA/324A/PA/644A/PA/1284/P 35.3 44M1 D D Marked Pin# 1 I D Marked Pin# 1 I D E E SE ATING PLAN E SE ATING A1PLAN E TOP VIE W A1 A3 TOP VIE W L L A K Pin #1 Co rner D2 D2 Pin #1 Co rner 1 1 2 2 3 3 E2 E2 Option A Option A Option B Option B K K A3 A K e b e b B OT TOM VIE W Option C Option C SIDE VIEW SIDE VIEW Pin #1 Triangle Pin #1 Triangle Pin #1 Cham fer Pin #1 (C 0.30) Cham fer (C 0.30) Pin #1 Pin Notch #1 (0.20 R) Notch (0.20 R) B OT TOM VIE W Note: JEDEC Standard MO-220, Fig . 1 (S AW Singulation) VKKD-3 . Note: JEDEC Standard MO-220, Fig . 1 (S AW Singulation) VKKD-3 . COMMON DIMENSIONS (Unit of Measure = mm) COMMON DIMENSIONS (Unit of Measure = mm) MIN MAX NOT E NOM SYMBOL MIN MAX NOT E NOM SYMBOLA 0.80 0.90 1.00 A 0.80 0.90 1.00 A1 - 0.02 0.05 A1 - 0.02 0.05 A3 0.20 REF A3 0.20 REF b 0.18 0.23 0.30 b 0.18 0.23 0.30 D 6.90 7.00 7.10 D 6.90 7.00 7.10 D2 5.00 5.20 5.40 D2 5.00 5.20 5.40 6.90 7.00 7.10 E 6.90 7.00 7.10 E E2 5.00 5.20 5.40 E2 5.00 5.20 5.40 e 0.50 BSC e 0.50 BSC L 0.59 0.64 0.69 L 0.59 0.64 0.69 K 0.20 0.26 0.41 K 0.20 0.26 0.41 TITLE TITLE 44M1, 44-pad, x 1.0mm body, lead 44M1, 44-pad, 7 x77xx71.0mm body, lead pitch 0.50mm, 5.20mm exposed pad, thermally pitch 0.50mm, 5.20mm exposed pad, thermally enhanced plastic very thin quad flat no enhanced plastic very thin quad flat no lead package (VQFN) lead package (VQFN) 2018 Microchip Technology Inc. Data Sheet Complete GPCGPC ZWSZWS 9/26/08 02/13/2014 DRAWING NO. DRAWING NO. REV. REV. 44M1 44M1 H H DS40002070A-page 653 ATmega164A/PA/324A/PA/644A/PA/1284/P 35.4 44MC C Pin 1 ID D SIDE VIEW y A1 E A TOP VIEW eT/2 A19 eR A24 B20 B16 A1 A18 COMMON DIMENSIONS (Unit of Measure = mm) B1 B15 b R0.20 0.40 SYMBOL MIN NOM MAX A 0.80 0.90 1.00 A1 0.00 0.02 0.05 b 0.18 0.23 0.30 D2 eT C B5 B11 A6 A13 B10 B6 A12 0.20 REF D 4.90 5.00 5.10 D2 2.55 2.60 2.65 E 4.90 5.00 5.10 E2 2.55 2.60 2.65 eT - 0.70 - eR - 0.40 - A7 L L E2 L BOTTOM VIEW Note: NOTE 1. The terminal #1 ID is a Laser-marked Feature. K 0.45 - - L 0.30 0.35 0.40 y 0.00 - 0.075 TITLE 44MC, 44QFN (2-Row Staggered), 5 x 5 x 1.00mm Body, 2.60 x 2.60mm Exposed Pad, Quad Flat No Lead Package 2018 Microchip Technology Inc. Data Sheet Complete 9/13/07 DRA WING NO . REV . 44MC A DS40002070A-page 654 ATmega164A/PA/324A/PA/644A/PA/1284/P 35.5 49C2 E A1 BALL ID 0.10 D A1 TOP VIEW A A2 SIDE VIEW E1 G e F E D D1 COMMON DIMENSIONS (Unit of Measure = mm) C B SYMBOL A 1 A1 BALL CORNER 2 3 4 5 b 6 7 e 49 - O0.35 0.05 BOTTOM VIEW MIN NOM MAX A - - 1.00 A1 0.20 - - A2 0.65 - - D 4.90 5.00 5.10 D1 E 4.90 3.90 BSC 5.00 5.10 E1 b NOTE 3.90 BSC 0.30 0.35 e 0.40 0.65 BSC 3/14/08 TITLE 49C2, 49-ball (7 x 7 array), 0.65mm pitch, 5.0 x 5.0 x 1.0mm, very thin, fine-pitch ball grid array package (VFBGA) 2018 Microchip Technology Inc. Data Sheet Complete GPC CBD DRAWING NO. 49C2 REV. A DS40002070A-page 655 ATmega164A/PA/324A/PA/644A/PA/1284/P 36. Errata 36.1 Errata for ATmega164A 36.1.1 Rev. E No known Errata. 36.2 Errata for ATmega164PA 36.2.1 Rev. E No known Errata. 36.3 Errata for ATmega324A 36.3.1 Rev. F No known Errata. 36.4 Errata for ATmega324PA 36.4.1 Rev. F No known Errata. 36.5 Errata for ATmega644A 36.5.1 Rev. F No known Errata. 36.6 Errata for ATmega644PA 36.6.1 Rev. F No known Errata. 36.7 Errata for ATmega1284 36.7.1 Rev. B No known Errata. 36.8 Errata for ATmega1284P 36.8.1 Rev. B No known Errata. 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 656 ATmega164A/PA/324A/PA/644A/PA/1284/P 37. Data sheet revision history Note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 37.1 Rev. A - 10/2018 1. 37.2 Updated the data sheet to Microchip style. New Microchip document number. Previous version was Atmel data sheet rev. 8272G. Rev. 8272G - 01/2015 1. Updated Table 1-2 on page 13, Table 8-1 on page 33, Table 10-1 on page 50, Table 14-3 on page 87, Table 19-4 on page 195, Table 19-11 on page 200 and Table 28-16 on page 336 for formatting consistency errors Updated "Ordering information" on page 643: 2. Added ordering information for ATmega164PA @105C; ATmega324PA @ 105C; ATmega324PA @105C; ATmega644PA @ 105C and ATmega1284P @ 105C 3. 37.3 Updated the "Packaging information" on page 651: Replaced the drawing "44M1" on page 653 by a correct package Rev. 8272F - 08/2014 1. Updated text in Section 13.2.8 "PCMSK1 - Pin Change Mask Register 1" on page 78 to: "If PCINT15:8 is set and the PCIE1 bit in PCICR is set, pin change interrupt is enabled on the corresponding I/O pin." 2. Corrected description of PAGEMSB in Table 26-9 on page 289. The device has 64 words in a page and not 128. 3. Corrected description of PAGEMSB in Table 26-12 on page 290. PAGESMB is 5 and the device has 64 words in a page and not 128. The page require six bits and not seven. 4. Corrected values in Table 26-16 on page 292. PAGEMSB is 6. ZPAGEMSB is Z7 and PCPAGE is Z15:Z8 5. Corrected value for PCPAGE in Table 27-7 on page 298. The correct value is PC[14:7] 6. Updated description in Table 17-2 on page 159 to "Normal port operation, OC2A disconnected." 7. Updated Assembly code examples on for "Watchdog Timer" on page 63. and onwards "out WDTCSR, r16" changed to "sts WDTCSR, r16" "in r16, WDTCSR" changed to "lds r16, WDTCSR" "idi r16, WDTCSR" changed to "lds r16, WDTCSR" 8. Updated addresses 0x65 and 0x64 in Section 32. "Register summary" on page 636. 9. Removed notes 5 and 6 from Table 28-16 on page 336. 10. Corrected values in Section 33. "Instruction set summary" on page 640.Changed clock values for RCALL and ICALL to 2, for Call, Ret and RETI to 4. Also changed values in Section 7.7.1 "Interrupt response time" on page 26. 11. Address for reset label and onwards changed in Interrupt Vector Addresses. 12. Updated layout, footer and back page according to template 0205/2014 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 657 ATmega164A/PA/324A/PA/644A/PA/1284/P 37.4 Rev. 8272E - 04/2013 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 37.5 3. 4. 5. 6. Updated the Assembly code example for WDT_off (p.56) following the ej# 705736. Added note in "16-bit Timer/Counter1 and Timer/Counter3(1) with PWM" on page 115. Added "Prescaler Reset" on page 120. Corrected three typo for Waveform generation mode (WGM) instead of MGM. Updated Table 23-6 on page 261. ADC Auto Trigger Source Selections, ADTS=0b011, the statement is Timer/Counter0 Compare Match A. Updated Table 27-18 on page 318. Command for 6d Poll for Fuse Write Complete: 0111011_00000000 Updated the table notes of the Table 28-1 on page 326. Updated "Register summary" on page 636. Added table note 7: Only available in ATmega1284/1284P. Updated "Power-down mode" on page 52. Updated "Overview" on page 75. Corrected references for Bit 2, Bit 1, and Bit 0 in Section "UCSRnC - USART MSPIM Control and Status Register n C" on page 209. Several small corrections throughout the whole document made according to the template Notes in Table 27-17 on page 312 have been corrected Note (1) in Table 28-3 on page 328 is added Rev. 8272C - 06/11 1. 37.7 Updated descriptive text on page 6 to indicate that ATmega1284/1284P has four T/Cs. Rev. 8272D - 05/12 1. 2. 37.6 Updated Figure 1-1 on page 11 and Figure 2-1 on page 14: T3 and T/C3 only available in ATmega1284/1284P. Updated "ATmega1284P DC characteristics" on page 331. Rev. 8272B - 05/11 1. 2. 3. 4. 5. 6. Added Atmel QTouch Library Support and QTouch Sensing Capability Features. Replaced the Figure 1-1 on page 11 by an updated "Pinout" that includes Timer/Counter3. Replaced the Figure 7-1 on page 18 by an updated "Block diagram of the AVR architecture" that includes Timer/Counter3. Added "RAMPZ - Extended Z-pointer Register for ELPM/SPM(1)" on page 23. Added "PRR1 - Power Reduction Register 1" on page 57. Renamed PRR to "PRR0 - Power Reduction Register 0" on page 56. 7. Updated "PCIFR - Pin Change Interrupt Flag Register" on page 77. PCICR replaces EIMSR in the PCIF3, PCIF2, PCIF1 and PCIF0 bit description. 8. Updated "PCMSK3 - Pin Change Mask Register 3" on page 78. PCIE3 replaces PCIE2 in the bit description. 9. Updated "Alternate Functions of Port B" on page 88 to include Timer/Counter3 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 658 ATmega164A/PA/324A/PA/644A/PA/1284/P 37.8 10. Updated "Alternate Functions of Port D" on page 94 to include Timer/Counter3 11. Added "TCNT3H and TCNT3L -Timer/Counter3" on page 140 12. Added "OCR3AH and OCR3AL - Output Compare Register3 A" on page 141 13. Added "OCR3BH and OCR3BL - Output Compare Register3 B" on page 141 14. Added "TIMSK3 - Timer/Counter3 Interrupt Mask Register" on page 142 15. Updated All "SPI - Serial Peripheral Interface" "Register description" to reflect ATmega1284 and ATmega1284P. 16. Updated "Addressing the Flash During Self-Programming" on page 282 to include RAMPZ register. 17. Updated Table 27-16 on page 311. tWD_EEPROM is 3.6ms instead of 9ms. 18. BODS and BODSE bits denoted as R/W 19. Description of external pin modes below table 16-9 removed. 20. Updated "Register summary" on page 636 to include Timer/Counter3. 21. Updated the datasheet with Atmel new style guide. Rev. 8272A - 01/10 1. Initial revision (Based on the ATmega164PA/324PA/644PA/1284P datasheet 8252G-AVR-11/09 and on the ATmega644 datasheet 2593N-AVR-09/09). 2. Changes done: Non-picoPower devices added: ATmega164A/324A/644A/1284 Updated Table 2-1 on page 15 Updated Table 10-1 on page 50 Updated "Sleep Modes" on page 50 and "BOD disable(1)" on page 51 Updated "Register description" on page 75 Updated "USART" on page 175 and "USART in SPI mode" on page 202 Updated "Signature Bytes" on page 298 and "Page Size" on page 298 Added "DC Characteristics" on page 326 for non-picoPower devices. Added "ATmega164A typical characteristics - TA = -40C to 85C" on page 344 Added "ATmega324A typical characteristics - TA = -40C to 85C" on page 397 Added "ATmega644A typical characteristics - TA = -40C to 85C" on page 449 Added "ATmega1284 typical characteristics - TA = -40C to 85C" on page 501 Added "Ordering information" on page 643 for non-picoPower devices Added "Errata for ATmega164A" on page 656 Added "Errata for ATmega324A" on page 656 Added "Errata for ATmega644PA" on page 656 Added "Errata for ATmega1284" on page 656 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 659 ATmega164A/PA/324A/PA/644A/PA/1284/P The Microchip Web Site Microchip provides online support via our web site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: * Product Support - Data sheets and errata, application notes and sample programs, design resources, user's guides and hardware support documents, latest software releases and archived software * General Technical Support - Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing * Business of Microchip - Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives Customer Change Notification Service Microchip's customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under "Design Support", click on "Customer Change Notification" and follow the registration instructions. Customer Support Users of Microchip products can receive assistance through several channels: * * * * Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Customers should contact their distributor, representative or Field Application Engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://microchip.com/support 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 660 ATmega164A/PA/324A/PA/644A/PA/1284/P Note the following details of the code protection feature on Microchip devices: * Microchip products meet the specification contained in their particular Microchip Data Sheet. * Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. * There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. * Microchip is willing to work with the customer who is concerned about the integrity of their code. * Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 == 2018 Microchip Technology Inc. The Microchip name and logo, the Microchip logo, AnyRate, AVR, AVR logo, AVR Freaks, BitCloud, chipKIT, chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq, Kleer, LANCheck, LINK MD, maXStylus, maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip Designer, QTouch, SAM-BA, SpyNIC, SST, SST Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. ClockWorks, The Embedded Control Solutions Company, EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch, Precision Edge, and Quiet-Wire are registered trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. (c) 2018, Microchip Technology Incorporated, All Rights Reserved. ISBN: 978-1-5224-3637-9 Data Sheet Complete DS40002070A-page 661 Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://www.microchip.com/ support Web Address: www.microchip.com Australia - Sydney Tel: 61-2-9868-6733 India - Bangalore Tel: 91-80-3090-4444 China - Beijing Tel: 86-10-8569-7000 India - New Delhi Tel: 91-11-4160-8631 Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 China - Chengdu Tel: 86-28-8665-5511 India - Pune Tel: 91-20-4121-0141 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 China - Chongqing Tel: 86-23-8980-9588 Japan - Osaka Tel: 81-6-6152-7160 Finland - Espoo Tel: 358-9-4520-820 China - Dongguan Tel: 86-769-8702-9880 Japan - Tokyo Tel: 81-3-6880- 3770 China - Guangzhou Tel: 86-20-8755-8029 Korea - Daegu Tel: 82-53-744-4301 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 China - Hangzhou Tel: 86-571-8792-8115 Korea - Seoul Tel: 82-2-554-7200 China - Hong Kong SAR Tel: 852-2943-5100 Malaysia - Kuala Lumpur Tel: 60-3-7651-7906 China - Nanjing Tel: 86-25-8473-2460 Malaysia - Penang Tel: 60-4-227-8870 China - Qingdao Tel: 86-532-8502-7355 Philippines - Manila Tel: 63-2-634-9065 China - Shanghai Tel: 86-21-3326-8000 Singapore Tel: 65-6334-8870 China - Shenyang Tel: 86-24-2334-2829 Taiwan - Hsin Chu Tel: 886-3-577-8366 China - Shenzhen Tel: 86-755-8864-2200 Taiwan - Kaohsiung Tel: 886-7-213-7830 Israel - Ra'anana Tel: 972-9-744-7705 China - Suzhou Tel: 86-186-6233-1526 Taiwan - Taipei Tel: 886-2-2508-8600 China - Wuhan Tel: 86-27-5980-5300 Thailand - Bangkok Tel: 66-2-694-1351 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 China - Xian Tel: 86-29-8833-7252 Vietnam - Ho Chi Minh Tel: 84-28-5448-2100 Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Austin, TX Tel: 512-257-3370 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Novi, MI Tel: 248-848-4000 Houston, TX Tel: 281-894-5983 Indianapolis Noblesville, IN Tel: 317-773-8323 Fax: 317-773-5453 Tel: 317-536-2380 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Tel: 951-273-7800 Raleigh, NC Tel: 919-844-7510 New York, NY Tel: 631-435-6000 San Jose, CA Tel: 408-735-9110 Tel: 408-436-4270 Canada - Toronto Tel: 905-695-1980 Fax: 905-695-2078 DS40002070A-page 662 China - Xiamen Tel: 86-592-2388138 China - Zhuhai Tel: 86-756-3210040 Germany - Garching Tel: 49-8931-9700 Germany - Haan Tel: 49-2129-3766400 Germany - Heilbronn Tel: 49-7131-67-3636 Germany - Karlsruhe Tel: 49-721-625370 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Germany - Rosenheim Tel: 49-8031-354-560 Italy - Padova Tel: 39-049-7625286 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Norway - Trondheim Tel: 47-7288-4388 Poland - Warsaw Tel: 48-22-3325737 Romania - Bucharest Tel: 40-21-407-87-50 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 Sweden - Gothenberg Tel: 46-31-704-60-40 Sweden - Stockholm Tel: 46-8-5090-4654 UK - Wokingham Tel: 44-118-921-5800 Fax: 44-118-921-5820 2018 Microchip Technology Inc.