Rev. 1.0 6/12 Copyright © 2012 by Silicon Laboratories Si8900/1/2
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si8900/1/2
ISOLATED MONITORING ADC
Features
Applications
Description
The Si8900/1/2 series of isolated monitoring ADCs are useful as linear
signal galvanic isolators, level shifters, and/or ground loop eliminators in
many applications including power-delivery systems and solar inverters.
These devices integrate a 10-bit SAR ADC subsystem, supervisory state
machine and isolated UART (Si8900), I2C/SMbus port (Si8901), or SPI
Port (Si8902) in a single package. Based on Silicon Labs’ proprietary
CMOS isolation technology, ordering options include a choice of 2.5 or
5 kV isolation ratings. All products are safety certified by UL, CSA, and
VDE (pending). The Si8900/1/2 devices offer a typical common-mode
transient immunity performance of 45 kV/µs for robust performance in
noisy and h igh-voltage environme nts. Devices in this fam ily are available
in 16-pin SOIC wide-body packages.
Safety Approval (Pending)
ADC
3 input channels
10-bit resolution
2 µs conversion time
Isolated serial I/O port
UART (Si8900)
I2C/SMbus (Si8901)
2.5 MHz SPI port (Si8902)
Transient immunity:
45 kV/µs (typ)
Temperature range:
–40 to +85 °C
>60-year life at rated working
voltage
CSA component notice 5A
approval
IEC 60950, 61010, 60601
VDE/IEC 60747-5-2
UL1577 recognized
Up to 5 kVrms for 1 minute
I s o l a t e d d a t a ac q u i s i t i o n
AC mains monitor
Solar inverters
Isolated temp/humidity sensing
Switch mode power systems
Telemetry
UL 1577 recognized
Up t o 5 kVrms f o r 1 m i n u t e
CSA component notice 5A
approval
IEC 60950, 61010, 60601
VDE certification conformity
IED 60747-5-2 (V DE 0884 Part 2)
Ordering Information:
See page 25.
Pin Assignments
VDDB
NC
NC
SCL
SDA
NC
VDDB
GNDB
Si8901
VDDA
VREF
RST
AIN0
AIN1
AIN2
RSDA
GNDA
AIN2
VDDB
NC
NC
Rx
Tx
NC
VDDB
GNDB
Si8900
VDDA
VREF
AIN0
AIN1
NC
RST
GNDA
VDDB
NC
SDO
SCLK
SDI
EN
VDDB
GNDB
Si8902
VDDA
RST
NC
VREF
AIN0
AIN1
AIN2
GNDA
Si8900/1/2
2 Rev. 1.0
Si8900/1/2
Rev. 1.0 3
TABLE OF CONTENTS
Section Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Regulatory Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
4. ADC Data Transmission Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
4.1. UART (Si8900) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
4.2. I2C/SMBus (Si8901) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
4.3. SPI Port (Si8902) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4.4. Master Controller Firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
5. Si8900/1/2 Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
6. Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
6.1. Isolated Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
6.2. Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
6.3. Application Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
7. Device Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
8. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
9. Package Outline: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
10. Land Pattern: 16-Pin Wide-Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
11. Top Marking: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
11.1. Si8900/1/2 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
11.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Document Change List: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Si8900/1/2
4 Rev. 1.0
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter Symbol Conditions Min Typ Max Units
Input Side Supply Voltage VDDA With respect to GND1 2.7 — 3.6 V
Input Side Supply Curr en t IDDA VDDA = 3.3 V, Si890x active — 10 13.3 mA
VDDA = 3.3 V, Si890x idle — 8.6 11.4
Output Side Supply Voltage VDDB With respect to GND2 2.7 — 5.5 V
Output Side Supply Current IDDB VDDB = 3.3 V to 5.5 V, Si890x active — 4.4 5.8 mA
VDDB = 3.3 V to 5.5 V, Si890x idle — 3.3 3.9
Operating Temperature TA–40 — +85 °C
Table 2. Electrical Specifications
Parameter Symbol Test Conditions Min Typ Max U nits
ADC
Resolution R 10 bits
Integral Nonlinearity INL VREF = 2.4 V — ±0.5 ±1 LSB
Differential Nonlinearity DNL VREF = 2.4 V,
Guaranteed Monotonic —±0.5±1LSB
Offset Error OFS –2 0 +2 L SB
Full Scale Error FSE –2 0 +2 LSB
Offset Tempco TOS —45—ppm/°C
Input Voltage Range VIN 0V
REF V
Sampling Capacitance CIN —5—pF
Input MUX Impedance RMUX —5—k
Power Supply
Rejection PSRR — –70 — dB
Reference Vo ltage VREF Default VREF =V
DDA 0—V
DDA V
VREF Supply Current IVREF —12—µA
ADC Conversion Time tCONV 2µs
Si8900/1/2
Rev. 1.0 5
Reset and Undervoltage Lockout
Power-on RESET
Voltage Threshold High VRSTH — — 1.8 V
Power-on RESET
Voltage Threshold Low VRSTL 1.7 — — V
VDDA Power-On Reset Ramp
Time tRAMP Time from VDDA = 0 V
to VDDA > VRST ——1ms
Power-On Reset
Delay Time tPOR tRAMP < 1 ms 0.3 ms
Output Side UVLO Threshold UVLO — 2.3 — V
Output side UVLO
Hysteresis H—100—mV
Digital Inputs
Logic High Level Input Voltage VIH 0.7 x VDDB ——V
Logic Low Level Input Voltage VIL ——0.6V
Logic Input Current IIN VIN = 0 V or VDD –10 +10 µA
Input Capacitance CIN —15—pF
Digital Outputs
Logic High Level Output Voltage VOH VDDB =5V,
IOH =–4mA VDDB–0.4 4.8 — V
VDDB =3.3V,
IOH =–4mA 3.1 — — V
Logic Low Level Output Voltage VOL VDDB = 3.3 to 5 V,
IOL =4mA —0.20.4V
Digital Output Series Impedance ROUT —85—
Serial Ports
UART Bit Rate 60 — 234 kbps
SMBus/I2C Bit Rate Slave
Address = 1111000x — — 240 kbps
SPI Port — — 2.5 Mbps
Table 2. Electrical Specifications (Continued)
Parameter Symbol Test Conditions Min Typ Max U nits
Si8900/1/2
6 Rev. 1.0
Figure 1. SPI Port Timing Characteristics
SPI Port Timing
EN Falling Edge to SCLK Rising
Edge tSE 80 — — ns
Last Clock Edge to /EN Rising tSD 80 — — ns
EN Falling to SDO Valid tSEZ — — 160 ns
EN Rising to SDO High-Z tSDZ — — 160 ns
SCLK High Time tCKH 200 — — ns
SCLK Low Time tCKL 200 — — ns
SDI Valid to SCLK Sample Edge tSIS 80 — — ns
SCLK Sample Edge to SDI
Change tSIH 80 — — ns
SCLK Shift Edge to SDO
Change tSOH — — 160 ns
Table 2. Electrical Specifications (Continued)
Parameter Symbol Test Conditions Min Typ Max U nits
tSEZ tSOH
tSIS tSIH
tCLKH
tSDZ
SCLK
SDI
SDO
EN
tCKLtSE tSD
Si8900/1/2
Rev. 1.0 7
Figure 2. (WB SOIC-16) Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN EN 60747-5-2
Figure 3. (NB SOIC-16) Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN EN 60747-5-2
Table 3. Thermal Characteristics
Parameter Symbol Test Condition WB SOIC-16 NB SOIC-16 Unit
IC Junction-to- Air T herm a l
Resistance JA 100 105 ºC/W
0 20015010050
500
400
200
100
0
Temperature (ºC)
Safety-Limiting Current (mA)
450
300
370
220
VDD1, VDD2 = 2.70 V
VDD1, VDD2 = 3.6 V
VDD1, VDD2 = 5.5 V
0 20015010050
500
400
200
100
0
Temperature (ºC)
Safety-Limiting Current (mA)
430
300
360
210
VDD1, VDD2 = 2.70 V
VDD1, VDD2 = 3.6 V
VDD1, VDD2 = 5.5 V
Si8900/1/2
8 Rev. 1.0
Table 4. Absolute Maximum Ratings
Parameter Symbol Min Typ Max Units
Storage Temperature TSTG –65 — 150 °C
Ambient Temperature under Bias TA–40 — 85 °C
Input-Side Supply Voltage VDDA –0.5 — 6.0 V
Output-Side Supply Voltage VDDB –0.5 — 6.0 V
Input/Output Voltage VI–0.5 — VDD +0.5 V
Output Current Drive IO—— 10 mA
Lead Solder Temperat ur e (1 0 s ) — — 260 °C
Maximum Isolation Voltage — — 6500 VRMS
*Note: Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be
restricted to conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Si8900/1/2
Rev. 1.0 9
2. Regulatory Information
The Si8900/1/2 family is certified by Underwriters Laboratories, CSA International, and VDE. Table 5 summarizes
the certification levels supported.
Table 5. Regulatory Information
CSA
The Si89xx is certified und er CSA Component Acceptance Notice 5A. For more details, see File 232873.
61010-1: Up to 600 VRMS reinforced insulation working voltage; up to 600 VRMS basic insulation working voltage.
60950-1: Up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage.
60601-1: Up to 125 VRMS reinforced insulation working voltage; up to 380 VRMS basic insulation working voltage.
VDE
The Si89xx is certified according to IEC 60747-5-2. For more details, see File 5006301-4880-0001.
60747-5-2: Up to 1200 Vpeak for basic insul ation working voltage.
60950-1: Up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage.
UL
The Si89xx is certified under UL1577 component recognition program. For more details, see File E257455.
Rated up to 5000 VRMS isolation voltage for basic protection.
Si8900/1/2
10 Rev. 1.0
3. Functional Description
The Si8900/1/2 (Figure 4) are isolated monitoring ADCs that convert linear input signals into digital format and
transmit the resulting data through an on-chip isolated serial port to an external master processor (typically a
microcontroller). The Si890x access protocol is simple: The master configures and controls the start of ADC
conversion by writing a configuration register (CNFG_0) Command Byte to the Si8 90x. The master then acquires
ADC conversion data by reading the Si890x serial port. Devices in this series differ only in the ty pe of serial port.
Options include a UART with on-chip baud rate generator that operates at 234 kbps max (Si8900), an SMBus/I2C
port that operates at 240 kbps max (Si8901), and an SPI Port that operates at 2.5 MHz max (Si8902).
The integrated ADC subsystem consists of a three-channel analog input multiplexer (MUX) followed by a series
gain amplifier (selectable 1x or 0.5x gain) and 10-bit SAR ADC. Serial-port-accessible ADC options allow the user
to select an internal or external voltage reference, set the programmable gain amplifier (PGA), and select the ADC
MUX address. The master can configure the Si890x to return ADC data on-demand (Demand Mode) or
continuously (Burst Mode). For more information, see "CNFG_0 Command Byte" on page 18.
Figure 4. Si8900/1/2 Block Diagrams
VDDA
GNDA
AIN0
AIN1
AIN2
VREF
Si8900
ADCSubsystem
UART
PGAMUX 10‐Bit
ADC
ISOLATION
Tx
Rx
GNDB
VDDB
All
Blocks
RxData
TxData
VREF
StateMachine/
UserRegisters
VDDA
GND1
AIN0
AIN1
AIN2
VREF
Si8902
ADCSubsystem
SPIPort
PGAMUX 10‐Bit
ADC
ISOLATION
SCK
GND2
VDDB
All
Blocks
RxData
TxData
VREF
StateMachine/
UserRegisters
SDI
SDO
VDDA
GNDA
AIN0
AIN1
AIN2
VREF
Si8901
ADCSubsystem
SMBus/
I2C
PGAMUX 10‐Bit
ADC
ISOLATION
SDA
SCL
GNDB
VDDB
All
Blocks
RxData
TxData
VREF
StateMachine/
UserRegisters
RSDA
RST
RST
RST
EN
Si8900/1/2
Rev. 1.0 11
4. ADC Data Transmission Modes
The master can access ADC read-on ly regi sters ADC_H and ADC_L using eith er Deman d Mode or Burs t Mode. In
Demand Mode (MODE = 1), the master triggers individual A/D conversions “on-demand”. In Burst Mode
(MODE = 0), the Si890x performs ADC conversions continuously.
Figure 5. ADC Demand Mode Operation
Referring to Figure 5A, a Demand Mode ADC read is initiated when the master writes a Command Byte to the
Si8900. (The Command Byte is a copy of the CNFG_0 register that has been properly configured by the master.)
Upon receipt of the Command Byte, the Si8900 updates its CNFG_0 register and triggers the start of an ADC
conversion, at which time the master may immediately begin reading ADC conve rsion data from the Si8900 UART.
The ADC conversion data packet contains a copy of the Command Byte for verification and two-bytes of ADC
conversion d ata. The Si8901 (Fig ure 5B) A DC read transa ction is identic al to that o f the Si8 900 wit h the exce ptio n
of the added I2C/SMBus Slave Address byte (Si8901 Slave Address is 0xF0). The Si8902 Demand Mode ADC
read transaction (Figure 5C) is the same as that of the Si8900, except the master must wait 8 µs after the
transmission of the Command Byte before reading the Si8902 SPI port because byte transmission time is two
times shorter versus the Si8900/01.
C)Si8901DemandModeADCRead
B)Si8900DemandModeADCRead
MastertoSlave
SlavetoMaster
CNFG_0
Command
Byte
tCONV
MasterwritesCNFG_0
CommandBytetoSi8900Rx
MasterreadsupdatedCNFG_0andADC
DataFromSi8900(Txoutput)
MODE=1
ADC_H ADC_L
CNFG_0
Command
Byte
MastertoSlave
SlavetoMaster
MasterreadsSlaveAddress,updatedCNFG_0
andADCDatafromSi8901(SDApin)
MODE=1
ADC_H
tCONV
ADC_L
CNFG_0
Command
Byte
CNFG_0
Command
Byte
CNFG_0
Command
Byte tCONV
D)Si8902DemandModeADCRead
MasterwritesCNFG_0
CommandBytetoSi8902SDI
MasterreadsupdatedCNFG_0and
ADCDatafromSi8902SDO
MastertoSlave
SlavetoMaster
MODE=1
ADC_H ADC_L
CNFG_0
Command
Byte
SlaveAddress
MasterwritesSlaveAddressand
CNFG_0CommandBytetoSi8901SDA
Themastermustwait8µS
(track‐and‐holdtime)before
readingADCdatapacket.
Slave
Address
Si8900/1/2
12 Rev. 1.0
The Burst Mode ADC transactions for the Si8900 (Figure 6A) and Si8901 (F igure 6B) are subst antially the sam e. A
Burst Mode ADC read is initiated when the master writes a CNFG_0 (MODE = 0) Command Byte to the Si8900/1,
which updates the CNFG_0 register and triggers the ADC continuously. Like the Demand Mode example, the
Si8901 has a Slave Address byte prior to the CNFG_0 Command Byte. When using the Si8901, the master must
write the I2C port address prior to reading the serial port. The Si8902 Burst Mode (Figure 6C) is similar to that of
the Si8900/1, except the master must wait 8 µs before reading the first Burst M ode ADC da ta packet. After reading
the first Burst Mode ADC data packet, the master may read all ADC data packets that follow without delay.
Figure 6. ADC Burst Mode Operation
A)Si8900ADCBurstMode(MODE=0)
MastertoSlave
SlavetoMaster
CNFG_0
Command
Byte0
tCONV
MasterwritesCNFG_0
CommandBytetoSi8900Rx
MasterreadsupdatedCNFG_0CommandByteandADCdatafromSi8900Tx
MODE=0
ADC_H
Data
ADC_L
Data
ADC_H
Data
ADC_L
Data
tCONV
CNFG_0
Command
Byte
tCONV
B)Si8901ADCBurstMode(MODE=0)
MastertoSlave
SlavetoMaster
MODE=0tCONV
MasterreadsSlaveAddress,updatedCNFG_0andADCdatafromSi8901SDA
ADC_H
Data
ADC_L
Data
ADC_H
Data
ADC_L
Data
tCONV tCONV
CNFG_0
Command
Byte0
CNFG_0
Command
Byte
MasterwritesSlaveAddress&CNFG_0
CommandBytetoSi8901SDA
SlaveAddress
Read
SlaveAddrress
Write
C)Si8902ADCBurstMode(MODE=0)
MastertoSlave
SlavetoMaster
MasterwritesCNFG_0Command
BytetoSi8902SDI
CNFG_0
Command
Byte
MasterreadsupdatedCNFG_0andADCdatafromSi8902SDO
MODE=0
ADC_H
Data
ADC_L
Data
ADC_H
Data
ADC_L
Data
CNFG_0
Command
Byte
tCONV tCONV
tCONV
Si8900/1/2
Rev. 1.0 13
4.1. UART (Si8900)
The UART is a two-wire interface (Tx, Rx) and operates as an asynchronous, full-duplex serial port with internal
auto baud rate generator that measures the period of incoming data stream and automatically adjusts the internal
baud rate generator to match. The auto baud rate detection and matching optimizes UART timing for minimum bit
error rate. For more information, see “AN635: AC Line Monitoring Using the Si890x Family of Isolated ADCs”.
There are a total of 10 bits per data read/write: One start bit, eight data bits (LSB first), and one stop bit with data
transmitted LSB first as shown in Figure 7. Figure 8A and Figure 8B show master/Si8900 ADC read transactions
for Demand Mode and Burst Mode, respectively.
Figure 7. UART Data Byte
Figure 8. Si8900 ADC Read Operation
D7
D6D5
D4
D3
D2
D1D0
StartBit
MARK
SPACE
BITTIMES
BITSAMPLING
STOPBIT
Si8900/1/2
14 Rev. 1.0
4.2. I2C/SMBus (Si8901)
The I2C/SMBus serial port is a two-wire serial bus where data line SDA is bidirectional and clock line SCL is
unidirectional. Reads and writes to this interface by the master are byte-oriented, with the I2C/SMBus master
controlling the serial data rates up to 240 kbps. The SDA and SCL lines must be pulled high through pull-up
resistors of 5 k or less. An Si8901 ADC read transaction begins with a START condition (“S” or Repeated START
condition “SR”), which is defined as a high-to-low transition on SDA while SCL is high (Figure 9). The master
terminates a tran sm issio n with a STOP condition (P), defined as a low-to-high transition on SDA while SCL is high.
The data on SDA must remain stable during the high peri od of the SCL clock pulse because such changes in either
line will be interpreted as a control command (e.g., S, P SR). SDA and SCL idle in the high state when the bus is
not busy. Acknowledge bits (Figure 10) provide detection of successful data transfers, whereas unsuccessful
transfers co nclude wit h a not-ackn owledge bit (NAC K). Both the master and the Si8901 generate ACK and NACK
bits. An ACK bit is generated when the receiving device pulls SDA low before the rising edge of the acknowledged
related (ninth) SCL pulse and maintains it low during the high period of the clock pulse. A NACK bit is generated
when the receiver allows SDA to be pulled high before the rising edge of the acknowledged related SCL pulse and
maintains it high during the high period of the clock pulse. An unsuccessful data transfer occurs if a receiving
device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master
attempts communication at a later time. Figure 11A shows the I2C Slave Address Byte and CNFG_0 byte for the
Si8901. Figure 11B and Figure 11C show master/Si8901 ADC read transactions for Demand Mode and Burst
Mode, respectively.
Figure 9. Start and Stop Conditions
Figure 10. Acknowledge Cycle
SDA
SCL
SSRP
SDA
SCL
SNotAcknowledge(NACK)
Acknowledge(ACK)
12 9
Si8900/1/2
Rev. 1.0 15
Figure 11. Si8901 ADC Read Operation
Figure 12. Master Connection to Si8902
MastertoSlave
SlavetoMaster
A)Si8901CNFG_0Write
B)Si8901DemandModeADCRead
Ss6 s5 s4 s3 s2 s1 A1A
START
ACK
ACK
Si8901CNFG_0WriteData
Write
MX0
PGA
P
VREF
STOP
R/W=0
D7D6D5D4D3D2D1D0
MX1
MODE
1
D7D6D5D4D3D2D1D0
ACK
ADCData
STOP
ACK
D7D6D5D4D3D2D1D0 D7D6D5D4D3D2D1D0
C)Si8901BurstModeADCRead
Si8901SlaveAddress
s0
ACK
Si8901CNFG_0ReadData
D7D6D5D4D3D2D1D0
Ss6 s5 s4 s3 s2 s1 A A
START
ACK
ACK
Si8901CNFG_0WriteData
Write
P
STOP
R/W=0
D7D6D5D4D3D2D1D0
D7D6D5D4D3D2D1D0
Si8901Write
SlaveAddress
s0
START
ACK
ACK
Si8901CNFG_0WriteData
Write
STOP
D7D6D5D4D3D2D1D0
D7D6D5D4D3D2D1D0
Si8901SlaveAddress
STOP
Si8901SlaveAddress=0xF0
START
Read
D7D6D5D4D3D2D1D0
Si8901Read
SlaveAddress
START
ACK
ACK
D7D6D5D4D3D2D1D0 D7D6D5D4D3D2D1D0
ACK
Si8901CNFG_0
ReadData
D7D6D5D4D3D2D1D0
PeriodicADCData
P
START
Read
D7D6D5D4D3D2D1D0
Si8901Read
SlaveAddress
START
‐
1
MX0
PGA
VREF
MX1
MODE=1
1‐
A A
0 0 0 P
MX1
MX0
D9
D8
A
D7
D6
D5
D4
D3
D2
D1
D0
S 1
MX0
PGA
VREF
MX1
MODE=1
1S s6 s5 s4 s3 s2 s1
R/W=1
s0 ‐1
S 1 A
MX0
PGA
VREF
MX1
MODE=0
1A
Ss6 s5 s4 s3 s2 s1
R/W=1
s0 ‐0 0 0
MX1
MX0
D9
D8
A
D7
D6
D5
D4
D3
D2
D1
D0
1A
Ss6 s5 s4 s3 s2 s1 A A P
R/W=0
s0 1
MX0
PGA
VREF
MX1
MODE=0
1‐
MASTER S
i
8902
MOSI
MISO
SCLK
SDI
SDO
SCLK
/EN
76543210
SPIShiftRegister
ReceiveBuffer
BaudRate
Generator
ENorPx.y
7 6 5 4 3 2 1 0
SPIShiftRegister
ReceiveBuffer
Si8900/1/2
16 Rev. 1.0
4.3. SPI Port (Si8902)
Figure 13. Si8902 Data/Clock Timing
The Serial Peripher al Interface (SPI po rt) is a slave mode, full- duplex, synchron ous, 4-wire ser ial bus that connect s
to the master as shown in Figure 12. The master's clock and data timing must match the Si8902 timing shown
Figure 12 (for more information about clock and data timing, please see the “SPI Port” section of Table 2 on
page 6).
As shown in Figure 13, an SPI bus transaction begins with the master driving EN low and maintaining this state for
the duration of the read transaction(s). The master transmits da ta fro m its mas ter-out/slave-in terminal (MOSI) to
the Si8902 serial read/write input terminal (SDI). The Si8902 transmits data to the master from its serial data-out
terminal (SDO) to the master-in/slave-out terminal (MISO), and data transfer ends when the master returns /EN to
the high state. Figure 14A shows the Si8902 CNFG_0 Command Byte format, while Figures 14B and 14C show
Si8902 Demand Mode and Burst Mode ADC reads.
MSB Bit6Bit5Bit4Bit3Bit2Bit1Bit0
MSB Bit6Bit5Bit4Bit3Bit2Bit1Bit0
SCLK
SDI
SDO
EN
Si8900/1/2
Rev. 1.0 17
Figure 14. Si8902 ADC Read Operation
4.4. Master Controller Firmware
The user's master contr oller must in clude firmware to m anage the Si890x Dema nd and Burst oper ating modes and
serial port control. In some cases, the master controller may also require a firmware moving average function to
reduce noise. For more information on master controller firmware, see AN638, available for download at
www.silabs.com/isolation.
MastertoSlave
SlavetoMaster
B)Si8902ADCDemandModeRead
ADCData
1 0
MX1
MX0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D7D6D5D4D3D2D1D0
A)Si8902CNFG_0CommandByte
CNFG_0Write
CommandByte
D7D6D5D4D3D2D1D0
C)Si8902ADCBurstModeRead
Si8902CNFG_0ReadByte
D7D6D5D4D3D2D1D0
CNFG_0Write
CommandByte
MX0
PGA
VREF
D7D6D5D4D3D2D1D0
MX1
MODE
11
D7D6D5D4D3D2D1D0
PeriodicADCData
CNFG_0Write
CommandByte
Si8902CNFG_0
ReadByte
‐
MX0
PGA
VREF
MX1
MODE=1
11 ‐
MX0
PGA
VREF
MX1
MODE=1
1‐10 0
MX0
PGA
VREF
MX1
MODE=0
11 ‐
D7D6D5D4D3D2D1D0
8µS
Delay
8µS
Delay D7D0D7D0
1
MX1
MX0
D9
D8
D7
D6
0 0
D5
D4
D3
D2
D1
D0
0
1
MX1
MX0
D9
D8
D7
D6
MX0
PGA
VREF
MX1
MODE=0
1‐100
D5
D4
D3
D2
D1
D0
0
D7D0D7D0 D7D0
Si8900/1/2
18 Rev. 1.0
5. Si8900/1/2 Configuration Registers
CNFG_0 Command Byte
BitD7D6D5D4D3D2D1D0
Name 1 1 MX1 MX0 VREF — MODE PGA
Type R/W R/W R/W R/W R/W R/W R/W R/W
Default 11111111
Bit Name Function
7:6 1,1 Internal use. These bits are alwa ys set to 1.
5:4 MX1, MX0 ADC MUX Address.
ADC MUX address selection is controlled by MX1, MX0 as follows:
3VREFADC Voltage Reference Source
VDD is selected as the refere n ce vo ltage when this bit is set to 1. An ext er n ally co n-
nected voltage reference generator is selected when this bit is reset to 0.
2 — Not used.
1MODEADC Read Mode
ADC Demand Mode read is enabled when this bit is 1, and Burst Mode is enabled
when this bit is 0. For more information on Demand and Burst mode operation,
please see "ADC Data Transmission Modes" on page 11.
0PGAPGA Gain Set
PGA gain is 1 when this bit is set to 1. PGA gain is 0.5 when this bit is reset to 0.
MX1 MX0 Selected ADC MUX Channel
1 1 Not Used
10 AIN2
01 AIN1
00 AIN0
Si8900/1/2
Rev. 1.0 19
ADC_H Byte
BitD7D6D5D4D3D2D1D0
Name 1 0 MX1 MX0 D9 D8 D7 D6
Type RRRRRRRR
Default ————————
Bit Name Function
7:6 1,0 Internal use. These bits are always set to 1,0.
5:4 MX1, MX0 ADC MUX Address
ADC input MUX address for the converted data in ADC_H, ADC_L.
3:0 D9: D6 ADC conversion data bits D9:D6
Most significant 4 bits of ADC conver sio n data.
ADC_L Byte
BitD7D6D5D4D3D2D1D0
Name 0 D5D4D3D2D1D0 0
Type RRRRRRRR
Default ————————
Bit Name Function
7 0 Internal use. This bit is always set to 0.
6:1 D5:D0 ADC Conversion Data Bits D5:D0
Least significant 6 bits of ADC conversion data.
0 0 Internal use. This bit is always set to 0.
Si8900/1/2
20 Rev. 1.0
6. Applications
6.1. Isolated Outputs
The Si890x serial outputs are internally isolated from the device input side. To ensure safety in the end-user
application, high vo lt age cir cuit s ( i.e., cir cuit s with >30 VAC) must be physically separated from the safety extr a-low
voltage circuits (i.e., circuits with <30 VAC) by a certain distance (creepage/clearance). If a component straddles
this isolation barrier, it must meet those creepage/clearance requirements and also provide a sufficiently large
high-volt age breakdown protection rating (commonly referr ed to as working volt age protection ). Tables published in
the component standards (UL1577, IEC60747, CSA 5A) are readily accepted by certification bodies to provide
proof for end-system specifications requirements. Refer to the end-system specification (61010-1, 60950-1, 60601-
1, etc.) requirements before starting any circuit design that uses galvanic isolation. To enhance the robustness of a
design, it is further recommended that the user also include 100 resistors in series with the Si890x inputs and
outputs if the system is excessively noisy. The nominal impedance of an isolated Si890x output channel is
approximately 50 and is a combination of the value of the on-chip series termination resistor and channel
resistance of the output driver FET. When driving loads where transmission line effects are a factor, output pins
should be appropriately terminated with controlled-impedance PCB traces.
The Si890x supply inputs must be bypassed with a parallel combination of 10 µF and 0.1 µF capacitors at VDDA
and VDDB as shown in Figure 15A. The capacitors should be placed as close to the package as possible. The
Si890x uses the VDDA su pply as its internal ADC voltage referen ce by defa ult. A precision ex ternal re ferenc e can
be installed as shown in Figure 15A and must be bypassed with a parallel combination of 0.1 µF and 4.7 µF
capacitors. (Note that the CNFG_0 VREF bit must be set to 0 when using the external reference.) The Si890x has
an on-chip power on reset circuit (POR) that maintains the device in its reset state until VDDA has stabilized. A
2k pull- up resistor on RST is strongly recommended to reduce the possibility of external noise coupling into the
reset input. The Si8901 will also require a 5 k pull-up resistor to VDDA on the RSDA input.
Figure 15. Si890x Installation
Figure 15B shows the required PCB ground configuration, where an 8 mm (min) “keep-out area” is provided to
ensure adequate creepage and clearance distances between the two grounds. PCB metal traces cannot be
present or cross through the keep-out area on the PCB top, bottom, or internal layer.
Si890x
GNDA GNDB
0.1µF 4.7µF
VDDA
Si890x
VREF
RST
RSDA
VDDA
GNDA
VDDB
GNDB
VREF
2K
VDDA
5K
Si8901
Only
0.1µF
10µF
2.7Vto3.6V
0.1µF
10µF
2.5Vto5.5V
8mm
(min) GNDB
GNDA
Keep‐outArea
(Nometalinthisarea)
BoardEdge
BoardEdge
AB
OptionalExternalVREF
Si8900/1/2
Rev. 1.0 21
6.2. Device Reset
During power-up, the Si890x is held in the reset state by the internal power-on reset signal (POR) until VDDA
settles above VRST. When this condition is met, a delay is initiated that maintains the Si890x in the reset state for
time period tPOR, after which the reset signal is driven high allowing the Si890x to start-up. Note the maximum
allowable VDD ramp time (i.e. time from 0 V to VDDA settled above VRST) is 1 ms. Slower ramp times may cause
the Si890x to be released from reset before VDDA reaches the VRST level.
Figure 16 shows typical VDDA monitor reset timing where the internal reset is driven low (Si890x in reset) when
VDDA falls below VRST (e.g., during a power down or VDDA brownout). The internal reset is released to its high
state when VDDA again settles above VRST. External circuitry can also be used to force a reset event by driving
the external R ST input low. A 2 k pull-up resistor on RST is recommended to avoid erroneous reset events from
external noise coupling to the RST input.
Figure 16. Si890x Power-on and Monitor Reset
VDDA
Monitor
Reset
Power‐OnReset
tPOR
VRSTH
V
DDA
VDDA(min)
VDDA
VRSTL
Internal
RESET
Si8900/1/2
22 Rev. 1.0
6.3. Application Example
Figure 17 shows the Si8900 operating as a single-phase ac line voltage and current monitor. The VDDA dc bias
circuit uses a low-cost 3.3 V linear regulator referenced to the neutral (white wire). The ac current is measured on
ADC input AIN0. The ac line voltage is scaled by resistors R17 and R18 and level-shifted by the 1.5 V VREF. AC
line current is measured using differential amplifier U1 connected across shunt resistor R1. Data is transferred to
the external controller or processor via the isolated UART.
Figure 17. AC Line Monitor Application Example
U1
LowCost
DualOpAmp
R1
C1
U2
3.3V
LDO
C4 C5
Si8900
AIN0
VDDA
GNDA
AIN1
WHITE
BLACK
D1
TX
RX
VDDB
GNDB
External
MasterController
OutputSide
BiasSupply
C2
1.5V
R2 R3
R6
R5
R7
R8
R9
1.5V
R11
C3
1.5V
R12
R13 R14
R15
R4
Single‐Phase
ACLine
R10
R17
R18
Si8900/1/2
Rev. 1.0 23
7. Device Pin Assignments
Figure 18. Si8900/1/2 Pinout (16SOW)
Table 6. Si8900/1/2 Pin Assignments
Pin Si8900
Pin Si8901
Pin Si8902
Pin Description
1 VDDA Input side VDD bias voltage (typically 3.3 V)
2VREFRST
Si8900/1: External voltage reference input.
Si8902: Active low reset.
3 AIN0 AIN0 NC Si890 0: ADC an a log inpu t ch an ne l 0.
Si8901: ADC analog inpu t ch an ne l 0.
Si8902: No connection
4 AIN1 AIN1 VREF Si8900: ADC analog input channel 1.
Si8901: ADC analog inpu t ch an ne l 1.
Si8902: External VREF in.
5 AIN2 AIN2 AIN0 Si8900: ADC analog input channel 2.
Si8901: ADC analog inpu t ch an ne l 2.
Si8902: ADC analog inpu t ch an ne l 0.
6NCRST
AIN1 Si8900: No Connection.
Si8901: Active low reset.
Si8902: ADC analog inpu t ch an ne l 1.
7RST
RSDA AIN2 Si8900: Active low reset.
Si8901: RSDA bias resistor (typically 5 k).
Si8902: ADC analog inpu t ch an ne l 2.
8 GNDA Input side ground
9 GNDB Output side ground
10 VDDB Output side VDD bias voltage (2.7 V to 5.5 V )
11 NC EN Si8900/1: No connection. Si8902: SPI Port Enable.
12 Tx SDA SDI Si8900: UART unidirectional transmit output.
Si8901: I2C Bidirectional data input/output.
Si8902: SPI port Serial data in.
13 Rx SCL SCLK Si8900: UART unidirectional receive input.
Si8901: I2C port unidirectional serial clock input.
Si8902: SPI port unidirectional serial clock input.
AIN2
VDDB
NC
NC
Rx
Tx
NC
VDDB
GNDB
Si8900
VDDA
VREF
AIN0
AIN1
NC
RST
GNDA
VDDB
NC
NC
SCL
SDA
NC
VDDB
GNDB
Si8901
VDDA
VREF
RST
AIN0
AIN1
AIN2
RSDA
GNDA
VDDB
NC
SDO
SCLK
SDI
EN
VDDB
GNDB
Si8902
VDDA
RST
NC
VREF
AIN0
AIN1
AIN2
GNDA
Si8900/1/2
24 Rev. 1.0
14 NC SDO Si8900/1: No connection.
Si8902: SPI port Serial data out (SDO)
15 NC No connection
16 VDDB Si8900/1/2: Output side VDD bias voltage (2.7 V to 5.5 V).
Table 6. Si8900/1/2 Pin Assignments (Continued)
Pin Si8900
Pin Si8901
Pin Si8902
Pin Description
Si8900/1/2
Rev. 1.0 25
8. Ordering Guide
Table 7. Product Ordering Information1,2,3
Part Number (OPN) Serial Port Package Isolation Rating Temp Range
Si8900B-A01-GS UART WB SOIC 2.5 kV –40 to +85 °C
Si8900D-A01-GS UART WB SOIC 5.0 kV –40 to +85 °C
Si8901B-A01-GS I2C/SMBus WB SOIC 2.5 kV –40 to +85 °C
Si8901D-A01-GS I2C/SMBus WB SOIC 5.0 kV –40 to +85 °C
Si8902B-A01-GS SPI Port WB SOIC 2.5 kV –40 to +85 °C
Si8902D-A01-GS SPI Port WB SOIC 5.0 kV –40 to +85 °C
Notes:
1. Add an “R” suffix to the part number to specify the tape and reel option. Example: “Si8900AB-A-ISR”.
2. All packages are RoHS-compliant.
3. Moisture sensitivity level is MSL3 for wide-body SOIC-16 package with peak reflow temperatures of 260 °C according
to the JEDEC industry standard classifications and peak solder temperatures.
Si8900/1/2
26 Rev. 1.0
9. Package Outline: 16-Pin Wide Body SOIC
Figure 19 illustrates the package details for the Si8900/1/2 Digital Isolator. Table 8 lists the values for the
dimensions shown in the illustration.
Figure 19. 16-Pin Wide Body SOIC
Table 8. Package Diagram Dimensions
Symbol
Millimeters
Min Max
A — 2.65
A1 0.1 0.3
D 10.3 BSC
E 10.3 BSC
E1 7.5 BSC
b0.310.51
c0.200.33
e 1.27 BSC
h0.250.75
L 0.4 1.27
0° 7°
Si8900/1/2
Rev. 1.0 27
10. Land Pattern: 16-Pin Wide-Body SOIC
Figure 20 illustrates the rec ommended land pattern details for the Si8900/1/2 in a 16-pin wide-body SOIC. Table 9
lists the values for the dimensions shown in the illustration.
Figure 20. 16-Pin SOIC Land Pattern
Table 9. 16-Pin Wide Body SOIC Land Pattern Dimensions
Dimension Feature (mm)
C1 Pad Column Spacing 9.40
E Pad Row Pitch 1.27
X1 Pad Width 0.60
Y1 Pad Length 1.90
Notes:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P1032X265-16AN
for Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card
fabrication tolerance of 0.05 mm is assumed.
Si8900/1/2
28 Rev. 1.0
11. Top Marking: 16-Pin Wide Body SOIC
11.1. Si8900/1/2 Top Marking
11.2. Top Marking Explanation
Line 1 Marking:
Base Part Number
Ordering Options
(See Ordering Gui de fo r mo re
information).
Si89 = Isolator product series
Serial Port
0=UART
1=I
2C
2 = SPI
Y = Channel Configuration
X = # of data channels (3, 2, 1)
Y = # of reverse channels (1, 0)
V = Insulation rating
B = 2.5 kV; D = 5.0 kV
Line 2 Marking: YY = Year
WW = Workweek Assigned by assembly subcontractor. Corresponds to the
year and workweek of the mold date.
TTTTTT = Mfg Code Manufacturing code from assembly house
Line 3 Marking:
Circle = 1.5 m m Diameter
(Center-Justified) “e3” Pb-Free Symbol
Country of Origin ISO Code
Abbreviation TW = Taiwan
Si89XYOV
YYWWTTTTTT
TW
e3
Si8900/1/2
Rev. 1.0 29
DOCUMENT CHANGE LIST:
Revision 0.5 to Revision 1.0
No changes.
Si8900/1/2
30 Rev. 1.0
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