LM5110-3SD/NOPB - NATIONAL SEMICONDUCTOR

LM5110

LM5110 Dual 5A Compound Gate Driver with Negative Output Voltage Capability

Literature Number: SNVS255A

LM5110

Dual 5A Compound Gate Driver with Negative Output

Voltage Capability

General Description

The LM5110 Dual Gate Driver replaces industry standard

gate drivers with improved peak output current and effi-

ciency. Each “compound” output driver stage includes MOS

and bipolar transistors operating in parallel that together sink

more than 5A peak from capacitive loads. Combining the

unique characteristics of MOS and bipolar devices reduces

drive current variation with voltage and temperature. Sepa-

rate input and output ground pins provide Negative Drive

Capability allowing the user to drive MOSFET gates with

positive and negative VGS voltages. The gate driver control

inputs are referenced to a dedicated input ground (IN_REF).

The gate driver outputs swing from V

to the output ground

which can be negative with respect to IN_REF. The

ability to hold MOSFET gates off with a negative VGS volt-

age reduces losses when driving low threshold voltage

MOSFETs often used as synchronous rectifiers. When driv-

ing with conventional positive only gate voltage, the IN_REF

and V

pins are connected together and referenced to a

common ground. Under-voltage lockout protection and a

shutdown input pin are also provided. The drivers can be

operated in parallel with inputs and outputs connected to

double the drive current capability. This device is available in

the SOIC-8 and the thermally-enhanced LLP-10 packages.

Features

nIndependently drives two N-Channel MOSFETs

nCompound CMOS and bipolar outputs reduce output

current variation

n5A sink/3A source current capability

nTwo channels can be connected in parallel to double the

drive current

nIndependent inputs (TTL compatible)

nFast propagation times (25 ns typical)

nFast rise and fall times (14 ns/12 ns rise/fall with 2 nF

load)

nDedicated input ground pin (IN_REF) for split supply or

single supply operation

nOutputs swing from V

to V

which can be negative

relative to input ground

nAvailable in dual non-inverting, dual inverting and

combination configurations

nShutdown input provides low power mode

nSupply rail under-voltage lockout protection

nPin-out compatible with industry standard gate drivers

Typical Applications

nSynchronous Rectifier Gate Drivers

nSwitch-mode Power Supply Gate Driver

nSolenoid and Motor Drivers

nPower Level Shifter

Package

nSOIC-8

nLLP-10 (4 mmx4mm)

Ordering Information

Order Number Package Type NSC Package Drawing Supplied As

LM5110-1/2/3 M SOIC-8 M08A Shipped in anti-static units

LM5110-1/2/3 MX SOIC-8 M08A 2500 shipped in Tape & Reel

LM5110-1/2/3 SD LLP-10 SDC10A 1000 shipped in Tape & Reel

LM5110-1/2/3 SDX LLP-10 SDC10A 4500 shipped in Tape & Reel

October 2003

LM5110 Dual 5A Compound Gate Driver with Negative Output Voltage Capability

Pin Configurations

20079201

SOIC-8

20079202

LLP-10

NC - NOT CONNECTED

Block Diagram

20079203

Block Diagram of LM5110

LM5110

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Typical Application

20079204

Simplified Power Converter Using Synchronous Rectifiers

with Negative Off Gate Voltage

LM5110

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Pin Description

Description Name Description Application Information

SOIC-8 LLP-10

1 1 IN_REF Ground reference for control

inputs

Connect to V

for standard positive only output

voltage swing. Connect to system logic ground

reference for positive and negative output voltage

swing.

2 2 IN_A ‘A’ side control input TTL compatible thresholds.

33V

Power ground of the driver

outputs

Connect to either power ground or a negative gate

drive supply.

4 4 IN_B ‘B’ side control input TTL compatible thresholds.

5 7 OUT_B Output for the ‘B’ side driver. Capable of sourcing 3A and sinking 5A. Voltage

swing of this output is from V

to V

68V

Positive supply Locally decouple to V

and IN_REF.

7 9 OUT_A. Output for the ‘A’ side driver. Capable of sourcing 3A and sinking 5A. Voltage

swing of this output is from V

to V

8 10 nSHDN Shutdown input pin Pull below 1.5V to activate low power shutdown

mode.

Note: Pins 5 and 6 are No Connect for LLP-10 package.

Configuration Table

Part Number “A” Output Configuration “B” Output Configuration Package

LM5110-1M Non-Inverting Non-Inverting SOIC- 8

LM5110-2M Inverting Inverting SOIC- 8

LM5110-3M Inverting Non-Inverting SOIC- 8

LM5110-1SD Non-Inverting Non-Inverting LLP-10

LM5110-2SD Inverting Inverting LLP-10

LM5110-3SD Inverting Non-Inverting LLP-10

LM5110

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Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

to V

−0.3V to 15V

to IN_REF −0.3V to 15V

IN to IN_REF, nSHDN to IN_REF −0.3V to 15V

IN_REF to V

−0.3V to 5V

Storage Temperature Range, (T

STG

) −55˚C to +150˚C

Maximum Junction Temperature,

(max)) +150˚C

Operating Junction Temperature +125˚C

ESD Rating 2kV

Electrical Characteristics

= −40˚C to +125˚C, V

= 12V, V

= IN_REF = 0V, nSHDN = V

, No Load on OUT_A or OUT_B, unless otherwise

specified.

Symbol Parameter Conditions Min Typ Max Units

Operating Range V

−IN_REF and V

−V

3.5 14 V

CCR

Under Voltage Lockout

(rising)

−IN_REF 2.3 2.9 3.5 V

CCH

Under Voltage Lockout

Hysteresis 230 mV

Supply Current (I

) IN_A = IN_B = 0V (5110-1) 1 2

IN_A = IN_B = V

(5110-2) 12

IN_A = V

,IN_B=0V

(5110-3) 12

CCSD

Shutdown Current (I

) nSHDN = 0V 18 25 µA

CONTROL INPUTS

Logic High 1.75 2.2 V

Logic Low 0.8 1.35 V

HYS Input Hysteresis 400 mV

Input Current Low IN_A=IN_B=V

(5110-1-2-3) −1 0.1 1

µA

Input Current High IN_A=IN_B=V

(5110-1) 10 18 25

IN_A=IN_B=V

(5110-2) −1 0.1 1

IN_A=V

(5110-3) -1 0.1 1

IN_B=V

(5110-3) 10 18 25

SHUTDOWN INPUT

ISD Pull-up Current nSHDN=0V −18 −25 µA

VSDR Shutdown Threshold nSHDN rising 0.8 1.5 2.2 V

VSDH Shutdown Hysteresis 165 mV

OUTPUT DRIVERS

Output Resistance High I

OUT

= −10 mA 30 50 Ω

Output Resistance Low I

OUT

= + 10 mA 1.4 2.5 Ω

Source

Peak Source Current OUTA/OUTB = V

/2,

200 ns Pulsed Current 3A

Sink

Peak Sink Current OUTA/OUTB = V

/2,

200 ns Pulsed Current 5A

LM5110

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Electrical Characteristics (Continued)

= −40˚C to +125˚C, V

= 12V, V

= IN_REF = 0V, nSHDN = V

, No Load on OUT_A or OUT_B, unless otherwise

specified.

Symbol Parameter Conditions Min Typ Max Units

SWITCHING CHARACTERISTICS

td1 Propagation Delay Time Low to

High, IN rising (IN to OUT)

LOAD

= 2 nF, see Figure

125 40 ns

td2 Propagation Delay Time High to

Low, IN falling (IN to OUT)

LOAD

= 2 nF, see Figure

125 40 ns

Rise Time C

LOAD

= 2.0 nF, see Figure

114 25 ns

Fall Time C

LOAD

= 2 nF, see Figure

112 25 ns

LATCHUP PROTECTION

AEC - Q100, Method 004 T

= 150˚C 500 mA

Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device

is intended to be functional. For guaranteed specifications and test conditions, see the Electrical Characteristics.

Timing Waveforms

20079205

(a)

20079206

(b)

FIGURE 1. (a) Inverting, (b) Non-Inverting

LM5110

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Typical Performance Characteristics

Supply Current vs Frequency Supply Current vs Capacitive Load

20079210 20079211

Rise and Fall Time vs Supply Voltage Rise and Fall Time vs Temperature

20079212 20079213

Rise and Fall Time vs Capacitive Load Delay Time vs Supply Voltage

20079214 20079215

LM5110

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Typical Performance Characteristics (Continued)

Delay Time vs Temperature RDSON vs Supply Voltage

20079216 20079217

UVLO Thresholds and Hysteresis vs Temperature

20079218

Detailed Operating Description

LM5110 dual gate driver consists of two independent and

identical driver channels with TTL compatible logic inputs

and high current totem-pole outputs that source or sink

current to drive MOSFET gates. The driver output consist of

a compound structure with MOS and bipolar transistor oper-

ating in parallel to optimize current capability over a wide

output voltage and operating temperature range. The bipolar

device provides high peak current at the critical threshold

region of the MOSFET VGS while the MOS devices provide

rail-to-rail output swing. The totem pole output drives the

MOSFET gate between the gate drive supply voltage V

and the power ground potential at the V

pin.

The control inputs of the drivers are high impedance CMOS

buffers with TTL compatible threshold voltages. The nega-

tive supply of the input buffer is connected to the input

ground pin IN_REF. An internal level shifting circuit connects

the logic input buffers to the totem pole output drivers. The

level shift circuit and separate input/output ground pins pro-

vide the option of single supply or split supply configurations.

When driving MOSFET gates from a single positive supply,

the IN_REF and V

pins are both connected to the power

ground. The LM5110 pinout was designed for compatibility

with industry standard gate drivers in single supply gate

driver applications. Pin 1 (IN_REF) on the LM5110 is a

no-connect on standard driver IC’s. Connecting pin 1 to pin 3

) on the printed circuit board accommodates the pin-out

of both the LM5110 and competitive drivers.

The isolated input/output grounds provide the capability to

drive the MOSFET to a negative VGS voltage for a more

robust and reliable off state. In split supply configuration, the

IN_REF pin is connected to the ground of the controller

which drives the LM5110 inputs. The V

pin is connected to

a negative bias supply that can range from the IN-REF as

much as 14V below the V

gate drive supply. The maxi-

mum recommended voltage difference between V

and

IN_REF or between V

and V

is 14V. The minimum

voltage difference between V

and IN_REF is 3.5V.

Enhancement mode MOSFETs do not inherently require a

negative bias on the gate to turn off the FET. However,

certain applications may benefit from the capability of nega-

tive VGS voltage during turn-off including:

1. when the gate voltages cannot be held safely below the

threshold voltage due to transients or coupling in the

printed circuit board.

LM5110

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Detailed Operating Description

(Continued)

2. when driving low threshold MOSFETs at high junction

temperatures

3. when high switching speeds produce capacitive gate-

drain current that lifts the internal gate potential of the

MOSFET

The two driver channels of the LM5110 are designed as

identical cells. Transistor matching inherent to integrated

circuit manufacturing ensures that the ac and dc perfor-

mance of the channels are nearly identical. Closely matched

propagation delays allow the dual driver to be operated as a

single driver if inputs and output pins are connected. The

drive current capability in parallel operation is 2X the drive of

either channel. Small differences in switching speed be-

tween the driver channels will produce a transient current

(shoot-through) in the output stage when two output pins are

connected to drive a single load. The efficiency loss for

parallel operation has been characterized at various loads,

supply voltages and operating frequencies. The power dis-

sipation in the LM5110 increases by less than 1% relative to

the dual driver configuration when operated as a single

driver with inputs and outputs connected.

An Under-voltage lockout (UVLO) circuit is included in the

LM5110, which senses the voltage difference between V

and the input ground pin, IN_REF. When the V

to IN_REF

voltage difference falls below 2.7V both driver channels are

disabled. The driver will resume normal operation when the

to IN_REF differential voltage exceeds approximately

2.9V. UVLO hysteresis prevents chattering during brown-out

conditions.

The Shutdown pin (nSHDN) is a TTL compatible logic input

provided to enable/disable both driver channels. When

nSHDN is in the logic low state, the LM5110 is switched to a

low power standby mode with total supply current less than

25 µA. This function can be effectively used for start-up,

thermal overload, or short circuit fault protection. It is recom-

mended that this pin be connected to V

when the shut-

down function is not being used. The shutdown pin has an

internal 18µA current source pull-up to V

The input pins of non-inverting drivers have an internal 18µA

current source pull-down to IN-REF. The input pins of invert-

ing driver channels have neither pull-up nor pull-down cur-

rent sources.

The LM5110 is available in dual non-inverting (-1), dual

inverting (-2) and the combination inverting plus non-

inverting (-3) configurations. All three configurations are of-

fered in the SOIC-8 and LLP-10 plastic packages.

Layout Considerations

Attention must be given to board layout when using LM5110.

Some important considerations include:

1. A Low ESR/ESL capacitor must be connected close to

the IC and between the V

and V

pins to support

high peak currents being drawn from V

during turn-on

of the MOSFET.

2. Proper grounding is crucial. The drivers need a very low

impedance path for current return to ground avoiding

inductive loops. The two paths for returning current to

ground are a) between LM5110 IN-REF pin and the

ground of the circuit that controls the driver inputs, b)

between LM5110 V

pin and the source of the power

MOSFET being driven. All these paths should be as

short as possible to reduce inductance and be as wide

as possible to reduce resistance. All these ground paths

should be kept distinctly separate to avoid coupling be-

tween the high current output paths and the logic signals

that drive the LM5110. A good method is to dedicate one

copper plane in a multi-layered PCB to provide a com-

mon ground surface.

3. With the rise and fall times in the range of 10 ns to 30 ns,

care is required to minimize the lengths of current car-

rying conductors to reduce their inductance and EMI

from the high di/dt transients generated by the LM5110.

4. The LM5110 SOIC footprint is compatible with other

industry standard drivers. Simply connect IN_REF pin of

the LM5110 to V

(pin 1 to pin 3) to operate the LM5110

in a standard single supply configuration.

5. If either channel is not being used, the respective input

pin (IN_A or IN_B) should be connected to either

IN_REF or V

to avoid spurious output signals. If the

shutdown feature is not used, the nSHDN pin should be

connected to V

to avoid erratic behavior that would

result if system noise were coupled into a floating

’nSHDN’ pin.

Thermal Performance

INTRODUCTION

The primary goal of thermal management is to maintain the

integrated circuit (IC) junction temperature (T

) below a

specified maximum operating temperature to ensure reliabil-

ity. It is essential to estimate the maximum T

of IC compo-

nents in worst case operating conditions. The junction tem-

perature is estimated based on the power dissipated in the

IC and the junction to ambient thermal resistance θ

for the

IC package in the application board and environment. The

is not a given constant for the package and depends on

the printed circuit board design and the operating environ-

ment.

DRIVE POWER REQUIREMENT CALCULATIONS IN

LM5110

The LM5110 dual low side MOSFET driver is capable of

sourcing/sinking 3A/5A peak currents for short intervals to

drive a MOSFET without exceeding package power dissipa-

tion limits. High peak currents are required to switch the

MOSFET gate very quickly for operation at high frequencies.

LM5110

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Thermal Performance (Continued)

The schematic above shows a conceptual diagram of the

LM5110 output and MOSFET load. Q1 and Q2 are the

switches within the gate driver. R

is the gate resistance of

the external MOSFET, and C

is the equivalent gate capaci-

tance of the MOSFET. The gate resistance Rg is usually very

small and losses in it can be neglected. The equivalent gate

capacitance is a difficult parameter to measure since it is the

combination of C

(gate to source capacitance) and C

(gate to drain capacitance). Both of these MOSFET capaci-

tances are not constants and vary with the gate and drain

voltage. The better way of quantifying gate capacitance is

the total gate charge Q

in coloumbs. Q

combines the

charge required by C

and C

for a given gate drive

voltage V

GATE

Assuming negligible gate resistance, the total power dissi-

pated in the MOSFET driver due to gate charge is approxi-

mated by

DRIVER

GATE

Where

= switching frequency of the MOSFET.

As an example, consider the MOSFET MTD6N15 whose

gate charge specified as 30 nC for V

GATE

= 12V.

The power dissipation in the driver due to charging and

discharging of MOSFET gate capacitances at switching fre-

quency of 300 kHz and V

GATE

of 12V is equal to

DRIVER

= 12V x 30 nC x 300 kHz = 0.108W.

If both channels of the LM5110 are operating at equal fre-

quency with equivalent loads, the total losses will be twice as

this value which is 0.216W.

In addition to the above gate charge power dissipation, -

transient power is dissipated in the driver during output

transitions. When either output of the LM5110 changes state,

current will flow from V

to V

for a very brief interval of

time through the output totem-pole N and P channel

MOSFETs. The final component of power dissipation in the

driver is the power associated with the quiescent bias cur-

rent consumed by the driver input stage and Under-voltage

lockout sections.

Characterization of the LM5110 provides accurate estimates

of the transient and quiescent power dissipation compo-

nents. At 300 kHz switching frequency and 30 nC load used

in the example, the transient power will be 8 mW. The 1 mA

nominal quiescent current and 12V V

GATE

supply produce a

12 mW typical quiescent power.

Therefore the total power dissipation

= 0.216 + 0.008 + 0.012 = 0.236W.

We know that the junction temperature is given by

xθ

Or the rise in temperature is given by

RISE

−T

xθ

For SOIC-8 package θ

is estimated as 170˚C/W for the

conditions of natural convection.

Therefore T

RISE

is equal to

RISE

= 0.236 x 170 = 40.1˚C

For LLP-10 package, the integrated circuit die is attached to

leadframe die pad which is soldered directly to the printed

circuit board. This substantially decreases the junction to

ambient thermal resistance (θ

). θ

as low as 40˚C/W is

achievable with the LLP10 package. The resulting T

RISE

for

the dual driver example above is thereby reduced to just 9.5

degrees.

CONTINUOUS CURRENT RATING OF LM5110

The LM5110 can deliver pulsed source/sink currents of 3A

and 5A to capacitive loads. In applications requiring continu-

ous load current (resistive or inductive loads), package

power dissipation, limits the LM5110 current capability far

below the 5A sink/3A source capability. Rated continuous

current can be estimated both when sourcing current to or

sinking current from the load. For example when sinking, the

maximum sink current can be calculated as

where R

(on) is the on resistance of lower MOSFET in the

output stage of LM5110.

Consider T

(max) of 125˚C and θ

of 170˚C/W for an SO-8

package under the condition of natural convection and no air

flow. If the ambient temperature (T

) is 60˚C, and the R

D-

20079207

FIGURE 2.

LM5110

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Thermal Performance (Continued)

(on) of the LM5110 output at T

(max) is 2.5Ω, this equation

yields I

SINK

(max) of 391mA which is much smaller than 5A

peak pulsed currents.

Similarly, the maximum continuous source current can be

calculated as

where V

DIODE

is the voltage drop across hybrid output stage

which varies over temperature and can be assumed to be

about 1.1V at T

(max) of 125˚C. Assuming the same param-

eters as above, this equation yields I

SOURCE

(max) of 347mA.

LM5110

www.national.com11

Physical Dimensions inches (millimeters)

unless otherwise noted

NOTES: UNLESS OTHERWISE SPECIFIED

1. STANDARD LEAD FINISH TO BE 200 MICROINCHES/5.08 MICROMETERS MINIMUM LEAD/TIN(SOLDER) ON

COPPER.

2. DIMENSION DOES NOT INCLUDE MOLD FLASH.

3. REFERENCE JEDEC REGISTRATION MS-012, VARIATION AA, DATED MAY 1990.

8-Lead SOIC Package

NS Package Number M08A

LM5110

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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

NOTES: UNLESS OTHERWISE SPECIFIED

1. FOR SOLDER THICKNESS AND COMPOSITION, SEE “SOLDER INFORMATION” IN THE PACKAGING SECTION OF

THE NATIONAL SEMICONDUCTOR WEB PAGE (www.national.com).

2. MAXIMUM ALLOWABLE METAL BURR ON LEAD TIPS AT THE PACKAGE EDGES IS 76 MICRONS.

3. NO JEDEC REGISTRATION AS OF MAY 2003.

10-Lead LLP Package

NS Package Number SDC10A

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LM5110 Dual 5A Compound Gate Driver with Negative Output Voltage Capability

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