PIC16(L)F1508/9 Data Sheet 20-Pin Flash, 8-Bit Microcontrollers with nanoWatt XLP Technology 2011 Microchip Technology Inc. Preliminary DS41609A Note the following details of the code protection feature on Microchip devices: * Microchip products meet the specification contained in their particular Microchip Data Sheet. * Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. * There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. * Microchip is willing to work with the customer who is concerned about the integrity of their code. * Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2011, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-61341-726-3 Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS41609A-page 2 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 20-Pin Flash, 8-Bit Microcontrollers with nanoWatt XLP Technology High-Performance RISC CPU: * C Compiler Optimized Architecture * Only 49 Instructions * Up to 14 Kbytes Linear Program Memory Addressing * Up to 512 bytes Linear Data Memory Addressing * Operating Speed: - DC - 20 MHz clock input - DC - 200 ns instruction cycle * Interrupt Capability with Automatic Context Saving * 16-Level Deep Hardware Stack with Optional Overflow/Underflow Reset * Direct, Indirect and Relative Addressing modes: - Two full 16-bit File Select Registers (FSRs) - FSRs can read program and data memory Flexible Oscillator Structure: * 16 MHz Internal Oscillator Block: - Factory calibrated to 1%, typical - Software selectable frequency range from 16 MHz to 31 kHz * 31 kHz Low-Power Internal Oscillator * Three External Clock modes up to 20 MHz Special Microcontroller Features: * Operating Voltage Range: - 1.8V to 3.6V (PIC16LF1508/9) - 2.3V to 5.5V (PIC16F1508/9) * Self-Programmable under Software Control * Power-on Reset (POR) * Power-up Timer (PWRT) * Programmable Low-Power Brown-Out Reset (LPBOR) * Extended Watchdog Timer (WDT): - Programmable period from 1 ms to 256s * Programmable Code Protection * In-Circuit Serial ProgrammingTM (ICSPTM) via Two Pins * Enhanced Low-Voltage Programming (LVP) * In-Circuit Debug (ICD) via two pins * Power-Saving Sleep mode: - Low-Power Sleep mode - Low-Power BOR (LPBOR) * Integrated Temperature Indicator * 128 Bytes High-Endurance Flash - 100,000 write Flash endurance (minimum) 2011 Microchip Technology Inc. Extreme Low-Power Management with nanoWatt XLP (PIC16LF1508/9): * Standby Current: - 25 nA @ 1.8V, typical * Watchdog Timer Current: - 300 nA @ 1.8V, typical * Operating Current: - 30 A/MHz @ 1.8V, typical * Timer1 Oscillator Current: - 600 nA @ 32 kHz, 1.8V, typical Peripheral Features: * Analog-to-Digital Converter (ADC): - 10-bit resolution - 12 external channels - 3 internal channels: - Fixed Voltage Reference - Digital-to-Analog Converter - Temperature Indicator channel - Auto acquisition capability - Conversion available during Sleep * 2 Comparators: - Rail-to-rail inputs - Power mode control - Software controllable hysteresis * Voltage Reference module: - Fixed Voltage Reference (FVR) with 1.024V, 2.048V and 4.096V output levels - Up to 1 rail-to-rail resistive 5-bit DAC with positive reference selection * 18 I/O Pins (1 Input-only Pin): - High current sink/source 25 mA/25 mA - Individually programmable weak pull-ups - Individually programmable interrupt-on-change (IOC) pins * Timer0: 8-Bit Timer/Counter with 8-Bit Programmable Prescaler * Enhanced Timer1: - 16-bit timer/counter with prescaler - External Gate Input mode * Timer2: 8-Bit Timer/Counter with 8-Bit Period Register, Prescaler and Postscaler * Four 10-bit PWM modules * Master Synchronous Serial Port (MSSP) with SPI and I2CTM with: - 7-bit address masking - SMBus/PMBusTM compatibility Preliminary DS41609A-page 3 PIC16(L)F1508/9 Peripheral Features (Continued): * Numerically Controlled Oscillator (NCO): - 20-bit accumulator - 16-bit increment - True linear frequency control - High-speed clock input - Selectable Output modes - Fixed Duty Cycle (FDC) mode - Pulse Frequency (PF) mode * Complementary Waveform Generator (CWG): - 8 selectable signal sources - Selectable falling and rising edge dead-band control - Polarity control - 4 auto-shutdown sources - Multiple input sources: PWM, CLC, NCO * Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) - RS-232, RS-485 and LIN compatible - Auto-Baud Detect - Auto-wake-up on Start * 4 Configurable Logic Cell (CLC) modules: - 16 selectable input source signals - Four inputs per module - Software control of combinational/sequential logic/state/clock functions - AND/OR/XOR/D Flop/D Latch/SR/JK - External or internal inputs/outputs - Operation while in Sleep DS41609A-page 4 Preliminary Debug(1) XLP PIC12(L)F1501 (1) 1024 64 6 4 1 1 2/1 4 -- -- 1 2 PIC16(L)F1503 (2) 2048 128 12 8 2 1 2/1 4 -- 1 1 2 PIC16(L)F1507 (3) 2048 128 18 12 -- -- 2/1 4 -- -- 1 2 PIC16(L)F1508 (4) 4096 256 18 12 2 1 2/1 4 1 1 1 4 PIC16(L)F1509 (4) 8192 512 18 12 2 1 2/1 4 1 1 1 4 Note 1: I - Debugging, Integrated on Chip; H - Debugging, Requires Debug Header. 2: One pin is input-only. Data Sheet Index: (Unshaded devices are described in this document.) 1: Future Product PIC12(L)F1501 Data Sheet, 8-Pin Flash, 8-bit Microcontrollers. 2: DS41607 PIC16(L)F1503 Data Sheet, 14-Pin Flash, 8-bit Microcontrollers. 3: DS41586 PIC16(L)F1507 Data Sheet, 20-Pin Flash, 8-bit Microcontrollers. 4: DS41609 PIC16(L)F1508/1509 Data Sheet, 20-Pin Flash, 8-bit Microcontrollers. NCO CLC CWG MSSP (I2C/SPI) EUSART PWM Timers (8/16-bit) DAC Comparators 10-bit ADC (ch) I/O's(2) Data SRAM (bytes) Program Memory Flash (words) Device Data Sheet Index PIC12(L)F1501/PIC16(F)L150X Family Types 1 1 1 1 1 H H H I/H I/H -- -- -- Y Y 2011 Microchip Technology Inc. PIC16(L)F1508/9 FIGURE 1: 20-PIN PDIP, SOIC, SSOP PACKAGE DIAGRAM FOR PIC16(L)F1508/9 PDIP, SOIC, SSOP 20 2 19 VSS RA0/ICSPDAT RA4 3 4 18 RA1/ICSPCLK MCLR/VPP/RA3 17 RA2 RC5 5 RC4 6 RC3 7 RC6 8 PIC16LF1508/9 1 RA5 PIC16F1508/9 VDD 16 RC0 15 RC1 14 RC2 13 RB4 RC7 9 12 RB5 RB7 10 11 RB6 Note: See Table 1 for location of all peripheral functions. 20-PIN QFN PACKAGE DIAGRAM FOR PIC16(L)F1508/9 VSS VDD RA5 RA4 QFN 4x4 RA0/ICSPDAT FIGURE 2: 20 19 18 17 16 MCLR/VPP/RA3 1 RC5 2 RC4 3 RC3 4 8 RB6 RA1/ICSPCLK 14 RA2 13 RC0 12 RC1 11 RC2 9 10 RB4 7 RB5 6 RB7 5 RC7 RC6 PIC16F1508/9 PIC16LF1508/9 15 Note: See Table 1 for location of all peripheral functions. 2011 Microchip Technology Inc. Preliminary DS41609A-page 5 PIC16(L)F1508/9 -- -- RA1 18 15 AN1 VREF+ C1IN0C2IN0- -- -- RA2 17 14 AN2 DACOUT2 C1OUT T0CKI RA3 4 1 -- -- -- RA4 3 20 AN3 -- RA5 2 19 -- RB4 13 10 RB5 12 9 RB6 11 RB7 -- -- -- -- IOC Y ICSPDAT ICDDAT -- -- -- CLC4IN1 -- IOC Y ICSPCLK ICDCLK -- -- CWG1FLT -- CLC1(1) PWM3 INT/ IOC Y -- T1G(2) -- SS(2) -- -- CLC1IN0 -- IOC Y MCLR VPP -- SOSCO T1G(1) -- -- -- -- -- -- IOC Y CLKOUT OSC2 -- -- SOSCI T1CKI -- -- -- NCO1CLK -- -- IOC Y CLKIN OSC1 AN10 -- -- -- -- SDA/SDI -- -- CLC3IN0 -- IOC Y -- AN11 -- -- -- RX/DT -- -- -- CLC4IN0 -- IOC Y -- 8 -- -- -- -- -- SCL/SCK -- -- -- -- IOC Y -- 10 7 -- -- -- -- TX/CK -- -- -- CLC3 -- IOC Y -- RC0 16 13 AN4 -- C2IN+ -- -- -- -- -- CLC2 -- -- -- -- RC1 15 12 AN5 -- C1IN1C2IN1- -- -- -- -- NCO1(1) -- PWM4 -- -- -- RC2 14 11 AN6 -- C1IN2C2IN2- -- -- -- -- -- -- -- -- -- -- RC3 7 4 AN7 -- C1IN3- -- -- -- -- -- CLC2IN0 PWM2 -- -- -- RC4 6 3 -- -- C2OUT -- -- -- CWG1B -- CLC4 CLC2IN1 -- -- -- -- RC5 5 2 -- -- -- -- -- -- CWG1A -- CLC1(2) PWM1 -- -- -- CLC3IN1 -- -- -- -- MSSP Basic EUSART C1IN+ Pull-up Timers DACOUT1 Interrupt Comparator AN0 PWM Reference 16 CLC A/D 19 NCO 20-Pin QFN RA0 CWG 20-Pin PDIP/SOIC/SSOP 20-PIN ALLOCATION TABLE (PIC16(L)F1508/9) I/O TABLE 1: -- (1) -- (2) RC6 8 5 AN8 -- -- -- -- SS RC7 9 6 AN9 -- -- -- -- SDO -- -- CLC1IN1 -- -- -- -- VDD 1 18 -- -- -- -- -- -- -- -- -- -- -- -- VDD 20 17 -- -- -- -- -- -- -- -- -- -- -- -- VSS 1: 2: Default location for peripheral pin function. Alternate location can be selected using the APFCON register. Alternate location for peripheral pin function selected by the APFCON register. VSS Note DS41609A-page 6 Preliminary NCO1 2011 Microchip Technology Inc. PIC16(L)F1508/9 Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 9 2.0 Enhanced Mid-Range CPU ........................................................................................................................................................ 15 3.0 Memory Organization ................................................................................................................................................................. 17 4.0 Device Configuration .................................................................................................................................................................. 43 5.0 Oscillator Module (With Fail-Safe Clock Monitor)....................................................................................................................... 49 6.0 Resets ........................................................................................................................................................................................ 65 7.0 Interrupts .................................................................................................................................................................................... 73 8.0 Power-Down Mode (Sleep) ........................................................................................................................................................ 87 9.0 Watchdog Timer ......................................................................................................................................................................... 91 10.0 Flash Program Memory Control ................................................................................................................................................. 95 11.0 I/O Ports ................................................................................................................................................................................... 111 12.0 Interrupt-On-Change ................................................................................................................................................................ 125 13.0 Fixed Voltage Reference (FVR) ............................................................................................................................................... 131 14.0 Temperature Indicator Module ................................................................................................................................................. 133 15.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 135 16.0 Digital-to-Analog Converter (DAC) Module .............................................................................................................................. 149 17.0 Comparator Module.................................................................................................................................................................. 153 18.0 Timer0 Module ......................................................................................................................................................................... 163 19.0 Timer1 Module with Gate Control............................................................................................................................................. 167 20.0 Timer2 Module ......................................................................................................................................................................... 179 21.0 Master Synchronous Serial Port Module.................................................................................................................................. 183 22.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 237 23.0 Pulse Width Modulation (PWM) Module................................................................................................................................... 265 24.0 Configurable Logic Cell (CLC).................................................................................................................................................. 271 25.0 Numerically Controlled Oscillator (NCO) Module ..................................................................................................................... 287 26.0 Complementary Waveform Generator (CWG) Module ............................................................................................................ 297 27.0 In-Circuit Serial ProgrammingTM (ICSPTM) ............................................................................................................................... 313 28.0 Instruction Set Summary .......................................................................................................................................................... 315 29.0 Electrical Specifications............................................................................................................................................................ 329 30.0 DC and AC Characteristics Graphs and Charts ....................................................................................................................... 357 31.0 Development Support............................................................................................................................................................... 359 32.0 Packaging Information.............................................................................................................................................................. 363 Appendix A: Data Sheet Revision History.......................................................................................................................................... 373 Index .................................................................................................................................................................................................. 375 The Microchip Web Site ..................................................................................................................................................................... 381 Customer Change Notification Service .............................................................................................................................................. 381 Customer Support .............................................................................................................................................................................. 381 Reader Response .............................................................................................................................................................................. 382 Product Identification System ............................................................................................................................................................ 383 2011 Microchip Technology Inc. Preliminary DS41609A-page 7 PIC16(L)F1508/9 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: * Microchip's Worldwide Web site; http://www.microchip.com * Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS41609A-page 8 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 1.0 DEVICE OVERVIEW Reference Table 1-1 for peripherals available per device. The PIC16(L)F1508/9 are described within this data sheet. They are available in 14-pin packages. Figure 1-1 shows a block diagram of the PIC16(L)F1508/9 devices. Tables 1-2 shows the pinout descriptions. PIC16LF1501 PIC16F1503 PIC16LF1503 PIC16F1507 PIC16LF1507 PIC16F1508/9 PIC16LF1508/9 DEVICE PERIPHERAL SUMMARY PIC16F1501 TABLE 1-1: Analog-to-Digital Converter (ADC) Complementary Wave Generator (CWG) Digital-to-Analog Converter (DAC) Peripheral Enhanced Universal Synchronous/Asynchronous Receiver/Transmitter (EUSART) Fixed Voltage Reference (FVR) Numerically Controlled Oscillator (NCO) Temperature Indicator Comparators C1 C2 Configurable Logic Cell (CLC) CLC1 CLC2 CLC3 CLC4 Master Synchronous Serial Ports MSSP1 PWM Modules PWM1 PWM2 PWM3 PWM4 Timer0 Timer1 Timer2 Timers 2011 Microchip Technology Inc. Preliminary DS41609A-page 9 PIC16(L)F1508/9 FIGURE 1-1: PIC16(L)F1508/9 BLOCK DIAGRAM Program Flash Memory RAM OSC2/CLKOUT OSC1/CLKIN Timing Generation PORTA CPU INTRC Oscillator PORTB (Figure 2-1) MCLR C1 EUSART CLC1 C2 Temp. Indicator Note DS41609A-page 10 ADC 10-Bit 1: 2: PORTC CLC2 CLC3 FVR CLC4 Timer0 Timer1 Timer2 CWG1 NCO1 PWM1 PWM2 PWM3 PWM4 MSSP1 DAC See applicable chapters for more information on peripherals. See Table 1-1 for peripherals available on specific devices. Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 TABLE 1-2: PIC16(L)F1508/9 PINOUT DESCRIPTION Name RA0/AN0/C1IN+/DACOUT1/ ICSPDAT/ICDDAT RA1/AN1/CLC4IN1/VREF+/ C1IN0-/C2IN0-/ICSPCLK/ ICDCLK RA2/AN2/C1OUT/DACOUT2/ T0CKI/INT/PWM3/CLC1(1)/ CWG1FLT RA3/CLC1IN0/VPP/T1G(2)/SS(2)/ MCLR RA4/AN3/SOSCO/ CLKOUT/T1G RA5/CLKIN/T1CKI/NCO1CLK/ SOSCI Function Input Type RA0 TTL AN0 AN Output Type Description CMOS General purpose I/O. -- A/D Channel input. C1IN+ AN -- Comparator positive input. DACOUT1 -- AN Digital-to-Analog Converter output. ICSPDAT ST CMOS ICSPTM Data I/O. ICDDAT ST CMOS In-Circuit Debug data. RA1 TTL CMOS General purpose I/O. AN1 AN -- A/D Channel input. CLC4IN1 ST -- Configurable Logic Cell source input. VREF+ AN -- A/D Positive Voltage Reference input. C1IN0- AN -- Comparator negative input. C2IN0- AN -- Comparator negative input. ICSPCLK ST -- ICSP Programming Clock. ICDCLK ST -- In-Circuit Debug Clock. RA2 ST AN2 AN C1OUT -- DACOUT2 -- CMOS General purpose I/O. -- A/D Channel input. CMOS Comparator output. AN Digital-to-Analog Converter output. T0CKI ST -- Timer0 clock input. INT ST -- External interrupt. PWM3 -- CMOS PWM output. CLC1 -- CMOS Configurable Logic Cell source output. CWG1FLT ST -- Complementary Waveform Generator Fault input. RA3 TTL -- General purpose input with IOC and WPU. CLC1IN0 ST -- Configurable Logic Cell source input. VPP HV -- Programming voltage. T1G ST -- Timer1 Gate input. SS ST -- Slave Select input. MCLR ST -- Master Clear with internal pull-up. RA4 TTL CMOS General purpose I/O. AN3 AN -- SOSCO XTAL XTAL CLKOUT -- T1G ST A/D Channel input. Secondary Oscillator Connection. CMOS FOSC/4 output. -- Timer1 Gate input. RA5 TTL CLKIN CMOS CMOS General purpose I/O. -- T1CKI ST -- Timer1 clock input. NCO1CLK ST -- Numerically Controlled Oscillator Clock source input. SOSCI XTAL XTAL External clock input (EC mode). Secondary Oscillator Connection. Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2CTM = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Default location for peripheral pin function. Alternate location can be selected using the APFCON register. 2: Alternate location for peripheral pin function selected by the APFCON register. 2011 Microchip Technology Inc. Preliminary DS41609A-page 11 PIC16(L)F1508/9 TABLE 1-2: PIC16(L)F1508/9 PINOUT DESCRIPTION (CONTINUED) Name RB4/AN10/CLC3IN0/SDA/SDI RB5/AN11/CLC4IN0/RX/DT RB6/SCL/SCK RB7/CLC3/TX/CK RC0/AN4/CLC2/C2IN+ RC1/AN5/C1IN1-/C2IN1-/PWM4/ NCO1(1) RC2/AN6/C1IN2-/C2IN2- RC3/AN7/C1IN3-/PWM2/ CLC2IN0 RC4/C2OUT/CLC2IN1/CLC4/ CWG1B Function Input Type RB4 TTL Output Type Description CMOS General purpose I/O. AN10 AN -- A/D Channel input. CLC3IN0 ST -- Configurable Logic Cell source input. SDA I2C OD I2C data input/output. SDI CMOS -- SPI data input. RB5 TTL AN11 AN CMOS General purpose I/O. -- A/D Channel input. CLC4IN0 ST -- Configurable Logic Cell source input. RX ST -- USART asynchronous input. DT ST CMOS USART synchronous data. RB6 TTL CMOS General purpose I/O. SCL I2C SCK ST RB7 TTL CLC3 -- CMOS Configurable Logic Cell source output. OD I2CTM clock. CMOS SPI clock. CMOS General purpose I/O. TX -- CMOS USART asynchronous transmit. CK ST CMOS USART synchronous clock. RC0 TTL CMOS General purpose I/O. AN4 AN CLC2 -- C2IN+ AN RC1 TTL AN5 AN -- A/D Channel input. C1IN1- AN -- Comparator negative input. C2IN1- AN -- Comparator negative input. -- A/D Channel input. CMOS Configurable Logic Cell source output. -- Comparator positive input. CMOS General purpose I/O. PWM4 -- CMOS PWM output. NCO1 -- CMOS Numerically Controlled Oscillator is source output. RC2 TTL AN6 AN -- A/D Channel input. C1IN2- AN -- Comparator negative input. C2IN2- AN -- Comparator negative input. RC3 TTL AN7 AN C1IN3- AN PWM2 -- CLC2IN0 ST RC4 TTL CMOS General purpose I/O. CMOS General purpose I/O. -- A/D Channel input. -- Comparator negative input. CMOS PWM output. -- Configurable Logic Cell source input. CMOS General purpose I/O. C2OUT -- CLC2IN1 ST CMOS Comparator output. CLC4 -- CMOS Configurable Logic Cell source output. CWG1B -- CMOS CWG complementary output. -- Configurable Logic Cell source input. Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2CTM = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Default location for peripheral pin function. Alternate location can be selected using the APFCON register. 2: Alternate location for peripheral pin function selected by the APFCON register. DS41609A-page 12 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 TABLE 1-2: PIC16(L)F1508/9 PINOUT DESCRIPTION (CONTINUED) Name RC5/PWM1/CLC1(2)/ CWG1A RC6/AN8/NCO1(2)/CLC3IN1/ SS(1) Function Input Type RC5 TTL Output Type Description CMOS General purpose I/O. PWM1 -- CMOS PWM output. CLC1 -- CMOS Configurable Logic Cell source output. CWG1A -- CMOS CWG primary output. RC6 TTL CMOS General purpose I/O. AN8 AN NCO1 -- CLC3IN1 ST -- Configurable Logic Cell source input. SS ST -- Slave Select input. RC7 TTL AN9 AN -- A/D Channel input. CLC1IN1 ST -- Configurable Logic Cell source input. SDO -- VDD VDD Power -- Positive supply. VSS VSS Power -- Ground reference. RC7/AN9/CLC1IN1/SDO -- A/D Channel input. CMOS Numerically Controlled Oscillator source output. CMOS General purpose I/O. CMOS SPI data output. Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2CTM = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Default location for peripheral pin function. Alternate location can be selected using the APFCON register. 2: Alternate location for peripheral pin function selected by the APFCON register. 2011 Microchip Technology Inc. Preliminary DS41609A-page 13 PIC16(L)F1508/9 NOTES: DS41609A-page 14 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 2.0 ENHANCED MID-RANGE CPU This family of devices contain an enhanced mid-range 8-bit CPU core. The CPU has 49 instructions. Interrupt capability includes automatic context saving. The hardware stack is 16 levels deep and has Overflow and Underflow Reset capability. Direct, Indirect, and Relative addressing modes are available. Two File Select Registers (FSRs) provide the ability to read program and data memory. * * * * Automatic Interrupt Context Saving 16-level Stack with Overflow and Underflow File Select Registers Instruction Set 2.1 Automatic Interrupt Context Saving During interrupts, certain registers are automatically saved in Shadow registers and restored when returning from the interrupt. This saves stack space and user code. See Section 7.5 "Automatic Context Saving", for more information. 2.2 16-Level Stack with Overflow and Underflow These devices have an external stack memory 15 bits wide and 16 words deep. A Stack Overflow or Underflow will set the appropriate bit (STKOVF or STKUNF) in the PCON register, and if enabled will cause a software Reset. See section Section 3.4 "Stack" for more details. 2.3 File Select Registers There are two 16-bit File Select Registers (FSR). FSRs can access all file registers and program memory, which allows one Data Pointer for all memory. When an FSR points to program memory, there is one additional instruction cycle in instructions using INDF to allow the data to be fetched. General purpose memory can now also be addressed linearly, providing the ability to access contiguous data larger than 80 bytes. There are also new instructions to support the FSRs. See Section 3.5 "Indirect Addressing" for more details. 2.4 Instruction Set There are 49 instructions for the enhanced mid-range CPU to support the features of the CPU. See Section 28.0 "Instruction Set Summary" for more details. 2011 Microchip Technology Inc. Preliminary DS41609A-page 15 PIC16(L)F1508/9 FIGURE 2-1: CORE BLOCK DIAGRAM 15 Configuration 15 MUX Flash Program Memory Program Bus 16-Level 8 Level Stack Stack (13-bit) (15-bit) 14 Instruction Instruction Reg reg 8 Data Bus Program Counter RAM Program Memory Read (PMR) 12 RAM Addr Addr MUX Indirect Addr 12 12 Direct Addr 7 5 BSR FSR Reg reg 15 FSR0reg Reg FSR FSR1 Reg FSR reg 15 STATUS Reg reg STATUS 8 3 CLKIN CLKOUT Instruction Decodeand & Decode Control Timing Generation Internal Oscillator Block DS41609A-page 16 MUX Power-up Timer Power-on Reset Watchdog Timer Brown-out Reset VDD ALU 8 W Reg VSS Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 3.0 MEMORY ORGANIZATION These devices contain the following types of memory: * Program Memory - Configuration Words - Device ID - User ID - Flash Program Memory * Data Memory - Core Registers - Special Function Registers - General Purpose RAM - Common RAM TABLE 3-1: The following features are associated with access and control of program memory and data memory: * PCL and PCLATH * Stack * Indirect Addressing 3.1 Program Memory Organization The enhanced mid-range core has a 15-bit program counter capable of addressing 32K x 14 program memory space. Table 3-1 shows the memory sizes implemented. Accessing a location above these boundaries will cause a wrap-around within the implemented memory space. The Reset vector is at 0000h and the interrupt vector is at 0004h (See Figure 3-1). DEVICE SIZES AND ADDRESSES Program Memory Space (Words) Last Program Memory Address High-Endurance Flash Memory Address Range (1) PIC16F1508 PIC16LF1508 4,096 0FFFh 0F80h-0FFFh PIC16F1509 PIC16LF1509 8,192 1FFFh 1F80h-1FFFh Device Note 1: High-endurance Flash applies to low byte of each address in the range. 2011 Microchip Technology Inc. Preliminary DS41609A-page 17 PIC16(L)F1508/9 FIGURE 3-1: PROGRAM MEMORY MAP AND STACK FOR PIC16(L)F1508 FIGURE 3-2: PC<14:0> CALL, CALLW RETURN, RETLW Interrupt, RETFIE On-chip Program Memory PROGRAM MEMORY MAP AND STACK FOR PIC16(L)F1509 PC<14:0> CALL, CALLW RETURN, RETLW Interrupt, RETFIE 15 15 Stack Level 0 Stack Level 1 Stack Level 0 Stack Level 1 Stack Level 15 Stack Level 15 Reset Vector 0000h Reset Vector 0000h Interrupt Vector 0004h 0005h Interrupt Vector 0004h 0005h Page 0 Page 0 07FFh 0800h 07FFh 0800h Page 1 Rollover to Page 0 0FFFh 1000h On-chip Program Memory Page 1 0FFFh 1000h Page 2 Page 3 Rollover to Page 0 Rollover to Page 1 DS41609A-page 18 Rollover to Page 3 7FFFh Preliminary 17FFh 1800h 1FFFh 2000h 7FFFh 2011 Microchip Technology Inc. PIC16(L)F1508/9 3.1.1 READING PROGRAM MEMORY AS DATA There are two methods of accessing constants in program memory. The first method is to use tables of RETLW instructions. The second method is to set an FSR to point to the program memory. 3.1.1.1 RETLW Instruction The RETLW instruction can be used to provide access to tables of constants. The recommended way to create such a table is shown in Example 3-1. EXAMPLE 3-1: constants BRW RETLW RETLW RETLW RETLW DATA0 DATA1 DATA2 DATA3 RETLW INSTRUCTION 3.1.1.2 Indirect Read with FSR The program memory can be accessed as data by setting bit 7 of the FSRxH register and reading the matching INDFx register. The MOVIW instruction will place the lower 8 bits of the addressed word in the W register. Writes to the program memory cannot be performed via the INDF registers. Instructions that access the program memory via the FSR require one extra instruction cycle to complete. Example 3-2 demonstrates accessing the program memory via an FSR. The HIGH directive will set bit<7> if a label points to a location in program memory. EXAMPLE 3-2: ;Add Index in W to ;program counter to ;select data ;Index0 data ;Index1 data my_function ;... LOTS OF CODE... MOVLW DATA_INDEX call constants ;... THE CONSTANT IS IN W ACCESSING PROGRAM MEMORY VIA FSR constants RETLW DATA0 ;Index0 data RETLW DATA1 ;Index1 data RETLW DATA2 RETLW DATA3 my_function ;... LOTS OF CODE... MOVLW LOW constants MOVWF FSR1L MOVLW HIGH constants MOVWF FSR1H MOVIW 0[FSR1] ;THE PROGRAM MEMORY IS IN W The BRW instruction makes this type of table very simple to implement. If your code must remain portable with previous generations of microcontrollers, then the BRW instruction is not available so the older table read method must be used. 2011 Microchip Technology Inc. Preliminary DS41609A-page 19 PIC16(L)F1508/9 3.2 Data Memory Organization 3.2.1 The data memory is partitioned in 32 memory banks with 128 bytes in a bank. Each bank consists of (Figure 3-3): * * * * 12 core registers 20 Special Function Registers (SFR) Up to 80 bytes of General Purpose RAM (GPR) 16 bytes of common RAM The core registers contain the registers that directly affect the basic operation. The core registers occupy the first 12 addresses of every data memory bank (addresses x00h/x08h through x0Bh/x8Bh). These registers are listed below in Table 3-2. For detailed information, see Table 3-8. TABLE 3-2: The active bank is selected by writing the bank number into the Bank Select Register (BSR). Unimplemented memory will read as `0'. All data memory can be accessed either directly (via instructions that use the file registers) or indirectly via the two File Select Registers (FSR). See Section 3.5 "Indirect Addressing" for more information. Data memory uses a 12-bit address. The upper 7-bits of the address define the Bank address and the lower 5-bits select the registers/RAM in that bank. DS41609A-page 20 CORE REGISTERS Preliminary CORE REGISTERS Addresses BANKx x00h or x80h x01h or x81h x02h or x82h x03h or x83h x04h or x84h x05h or x85h x06h or x86h x07h or x87h x08h or x88h x09h or x89h x0Ah or x8Ah x0Bh or x8Bh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON 2011 Microchip Technology Inc. PIC16(L)F1508/9 3.2.1.1 STATUS Register The STATUS register, shown in Register 3-1, contains: * the arithmetic status of the ALU * the Reset status The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. REGISTER 3-1: U-0 It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect any Status bits. For other instructions not affecting any Status bits (Refer to Section 28.0 "Instruction Set Summary"). Note 1: The C and DC bits operate as Borrow and Digit Borrow out bits, respectively, in subtraction. STATUS: STATUS REGISTER U-0 -- For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as `000u u1uu' (where u = unchanged). -- U-0 R-1/q R-1/q R/W-0/u R/W-0/u R/W-0/u -- TO PD Z DC(1) C(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-5 Unimplemented: Read as `0' bit 4 TO: Time-Out bit 1 = After power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred bit 3 PD: Power-Down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit Carry/Digit Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1) 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result bit 0 C: Carry/Borrow bit(1) (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two's complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register. 2011 Microchip Technology Inc. Preliminary DS41609A-page 21 PIC16(L)F1508/9 3.2.2 SPECIAL FUNCTION REGISTER FIGURE 3-3: The Special Function Registers are registers used by the application to control the desired operation of peripheral functions in the device. The Special Function Registers occupy the 20 bytes after the core registers of every data memory bank (addresses x0Ch/x8Ch through x1Fh/x9Fh). The registers associated with the operation of the peripherals are described in the appropriate peripheral chapter of this data sheet. 3.2.3 7-bit Bank Offset 0Bh 0Ch GENERAL PURPOSE RAM Core Registers (12 bytes) Special Function Registers (20 bytes maximum) 1Fh 20h Linear Access to GPR The general purpose RAM can be accessed in a non-banked method via the FSRs. This can simplify access to large memory structures. See Section 3.5.2 "Linear Data Memory" for more information. 3.2.4 Memory Region 00h There are up to 80 bytes of GPR in each data memory bank. The Special Function Registers occupy the 20 bytes after the core registers of every data memory bank (addresses x0Ch/x8Ch through x1Fh/x9Fh). 3.2.3.1 BANKED MEMORY PARTITIONING General Purpose RAM (80 bytes maximum) COMMON RAM There are 16 bytes of common RAM accessible from all banks. 6Fh 70h Common RAM (16 bytes) 7Fh 3.2.5 DEVICE MEMORY MAPS The memory maps for PIC16(L)F1508/9 are as shown in Table 3-5 and Table 3-6. DS41609A-page 22 Preliminary 2011 Microchip Technology Inc. 2011 Microchip Technology Inc. TABLE 3-3: PIC16(L)F1508 MEMORY MAP, BANK 1-7 BANK 0 000h BANK 1 080h Core Registers (Table 3-2) Preliminary 00Bh 00Ch 00Dh 00Eh 00Fh 010h 011h 012h 013h 014h 015h 016h 017h 018h 019h 01Ah 01Bh 01Ch 01Dh 01Eh 01Fh 020h PORTA PORTB PORTC -- -- PIR1 PIR2 PIR3 -- TMR0 TMR1L TMR1H T1CON T1GCON TMR2 PR2 T2CON -- -- -- Core Registers (Table 3-2) 08Bh 08Ch 08Dh 08Eh 08Fh 090h 091h 092h 093h 094h 095h 096h 097h 098h 099h 09Ah 09Bh 09Ch 09Dh 09Eh 09Fh 0A0h Legend: ADCON0 ADCON1 ADCON2 Core Registers (Table 3-2) 10Bh 10Ch 10Dh 10Eh 10Fh 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh 11Fh 120h General Purpose Register 80 Bytes 0EFh 0F0h Common RAM 07Fh TRISA TRISB TRISC -- -- PIE1 PIE2 PIE3 -- OPTION_REG PCON WDTCON -- OSCCON OSCSTAT ADRESL ADRESH 0FFh Common RAM (Accesses 70h - 7Fh) BANK 3 180h LATA LATB LATC -- -- CM1CON0 CM1CON1 CM2CON0 CM2CON1 CMOUT BORCON FVRCON DACCON0 DACCON1 -- -- -- APFCON -- -- Core Registers (Table 3-2) 18Bh 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh 1A0h General Purpose Register 80 Bytes 16Fh 170h 17Fh Common RAM (Accesses 70h - 7Fh) = Unimplemented data memory locations, read as `0'. BANK 4 200h ANSELA ANSELB ANSELC -- -- PMADRL PMADRH PMDATL PMDATH PMCON1 PMCON2 VREGCON -- RCREG TXREG SPBRG SPBRGH RCSTA TXSTA BAUDCON Core Registers (Table 3-2) 20Bh 20Ch 20Dh 20Eh 20Fh 210h 211h 212h 213h 214h 215h 216h 217h 218h 219h 21Ah 21Bh 21Ch 21Dh 21Eh 21Fh 220h Unimplemented Read as `0' 1EFh 1F0h 1FFh Common RAM (Accesses 70h - 7Fh) BANK 5 280h WPUA WPUB -- -- -- SSP1BUF SSP1ADD SSP1MSK SSP1STAT SSP1CON1 SSP1CON2 SSP1CON3 -- -- -- -- -- -- -- -- Core Registers (Table 3-2) 28Bh 28Ch 28Dh 28Eh 28Fh 290h 291h 292h 293h 294h 295h 296h 297h 298h 299h 29Ah 29Bh 29Ch 29Dh 29Eh 29Fh 2A0h Unimplemented Read as `0' 26Fh 270h 27Fh Common RAM (Accesses 70h - 7Fh) BANK 6 300h -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Core Registers (Table 3-2) 30Bh 30Ch 30Dh 30Eh 30Fh 310h 311h 312h 313h 314h 315h 316h 317h 318h 319h 31Ah 31Bh 31Ch 31Dh 31Eh 31Fh 320h Unimplemented Read as `0' 2EFh 2F0h 2FFh Common RAM (Accesses 70h - 7Fh) BANK 7 380h -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Core Registers (Table 3-2) 38Bh 38Ch 38Dh 38Eh 38Fh 390h 391h 392h 393h 394h 395h 396h 397h 398h 399h 39Ah 39Bh 39Ch 39Dh 39Eh 39Fh 3A0h Unimplemented Read as `0' 36Fh 370h 37Fh Common RAM (Accesses 70h - 7Fh) -- -- -- -- -- IOCAP IOCAN IOCAF IOCBP IOCBN IOCBF -- -- -- -- -- -- -- -- -- Unimplemented Read as `0' 3EFh 3F0h 3FFh Common RAM (Accesses 70h - 7Fh) DS41609A-page 23 PIC16(L)F1508/9 General Purpose Register 80 Bytes 06Fh 070h BANK 2 100h PIC16(L)F1509 MEMORY MAP, BANK 1-7 BANK 0 000h BANK 1 080h Core Registers (Table 3-2) Preliminary 00Bh 00Ch 00Dh 00Eh 00Fh 010h 011h 012h 013h 014h 015h 016h 017h 018h 019h 01Ah 01Bh 01Ch 01Dh 01Eh 01Fh BANK 2 100h Core Registers (Table 3-2) BANK 3 180h Core Registers (Table 3-2) PORTA PORTB PORTC -- -- PIR1 PIR2 PIR3 -- TMR0 TMR1L TMR1H T1CON T1GCON TMR2 PR2 T2CON 08Bh 08Ch 08Dh 08Eh 08Fh 090h 091h 092h 093h 094h 095h 096h 097h 098h 099h 09Ah 09Bh 09Ch TRISA TRISB TRISC -- -- PIE1 PIE2 PIE3 -- OPTION_REG PCON WDTCON -- OSCCON OSCSTAT ADRESL ADRESH 10Bh 10Ch 10Dh 10Eh 10Fh 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11Ah 11Bh 11Ch -- -- -- 09Dh 09Eh 09Fh ADCON0 ADCON1 ADCON2 11Dh 11Eh 11Fh LATA LATB LATC -- -- CM1CON0 CM1CON1 CM2CON0 CM2CON1 CMOUT BORCON FVRCON DACCON0 DACCON1 -- -- -- APFCON -- -- BANK 4 200h Core Registers (Table 3-2) 18Bh 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh ANSELA ANSELB ANSELC -- -- PMADRL PMADRH PMDATL PMDATH PMCON1 PMCON2 VREGCON -- RCREG TXREG SPBRG SPBRGH RCSTA TXSTA BAUDCON BANK 5 280h Core Registers (Table 3-2) 20Bh 20Ch 20Dh 20Eh 20Fh 210h 211h 212h 213h 214h 215h 216h 217h 218h 219h 21Ah 21Bh 21Ch 21Dh 21Eh 21Fh WPUA WPUB -- -- -- SSP1BUF SSP1ADD SSP1MSK SSP1STAT SSP1CON1 SSP1CON2 SSP1CON3 -- -- -- -- -- -- -- -- Core Registers (Table 3-2) 28Bh 28Ch 28Dh 28Eh 28Fh 290h 291h 292h 293h 294h 295h 296h 297h 298h 299h 29Ah 29Bh 29Ch 29Dh 29Eh 29Fh -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0A0h 020h General Purpose Register 80 Bytes General Purpose Register 80 Bytes 0EFh 0F0h 06Fh 070h 2011 Microchip Technology Inc. Common RAM 07Fh Legend: 0FFh Common RAM (Accesses 70h - 7Fh) 120h 16Fh 170h 17Fh General Purpose Register 80 Bytes Common RAM (Accesses 70h - 7Fh) = Unimplemented data memory locations, read as `0'. 1A0h 1EFh 1F0h 1FFh General Purpose Register 80 Bytes Common RAM (Accesses 70h - 7Fh) 220h 26Fh 270h 27Fh General Purpose Register 80 Bytes Common RAM (Accesses 70h - 7Fh) BANK 6 300h 2A0h 2EFh 2F0h 2FFh Core Registers (Table 3-2) 30Bh 30Ch 30Dh 30Eh 30Fh 310h 311h 312h 313h 314h 315h 316h 317h 318h 319h 31Ah 31Bh 31Ch 31Dh 31Eh 31Fh 320h General Purpose Register 80 Bytes Common RAM (Accesses 70h - 7Fh) BANK 7 380h -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- General Purpose Register 16Bytes Core Registers (Table 3-2) 38Bh 38Ch 38Dh 38Eh 38Fh 390h 391h 392h 393h 394h 395h 396h 397h 398h 399h 39Ah 39Bh 39Ch 39Dh 39Eh 39Fh 37Fh Common RAM (Accesses 70h - 7Fh) IOCBP IOCBN IOCBF -- -- -- -- -- -- -- -- -- 3A0h Unimplemented Read as `0' Unimplemented Read as `0' 36Fh 370h -- -- -- -- -- IOCAP IOCAN IOCAF 3EFh 3F0h 3FFh Common RAM (Accesses 70h - 7Fh) PIC16(L)F1508/9 DS41609A-page 24 TABLE 3-4: 2011 Microchip Technology Inc. TABLE 3-5: PIC16(L)F1508/9 MEMORY MAP, BANK 8-23 BANK 8 400h BANK 9 480h Core Registers (Table 3-2) Core Registers (Table 3-2) Preliminary 40Bh 40Ch 40Dh 40Eh 40Fh 410h 411h 412h 413h 414h 415h 416h 417h 418h 419h 41Ah 41Bh 41Ch 41Dh 41Eh 41Fh 420h 48Bh 48Ch 48Dh 48Eh 48Fh 490h 491h 492h 493h 494h 495h 496h 497h 498h 499h 49Ah 49Bh 49Ch 49Dh 49Eh 49Fh 4A0h -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Unimplemented Read as `0' 46Fh 470h 47Fh 4EFh 4F0h 4FFh Common RAM (Accesses 70h - 7Fh) Core Registers (Table 3-2 ) DS41609A-page 25 87Fh Legend: Common RAM (Accesses 70h - 7Fh) 56Fh 570h 57Fh 8FFh 5EFh 5F0h 5FFh = Unimplemented data memory locations, read as `0'. 64Fh 650h 67Fh 6EFh 6F0h 6FFh 76Fh 770h 77Fh 78Bh 78Ch 78Dh 78Eh 78Fh 790h 791h 792h 793h 794h 795h 796h 797h 798h 799h 79Ah 79Bh 79Ch 79Dh 79Eh 79Fh 7A0h 7EFh 7F0h 7FFh BANK 23 Core Registers (Table 3-2) B8Bh B8Ch Unimplemented Read as `0' B7Fh Common RAM (Accesses 70h - 7Fh) B80h Core Registers (Table 3-2) B6Fh B70h -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Unimplemented Read as `0' BANK 22 Unimplemented Read as `0' AFFh Common RAM (Accesses 70h - 7Fh) B0Bh B0Ch Common RAM (Accesses 70h - 7Fh) Core Registers (Table 3-2) Unimplemented Read as `0' Core Registers (Table 3-2) AEFh AF0h -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- B00h A8Bh A8Ch Common RAM (Accesses 70h - 7Fh) 70Bh 70Ch 70Dh 70Eh 70Fh 710h 711h 712h 713h 714h 715h 716h 717h 718h 719h 71Ah 71Bh 71Ch 71Dh 71Eh 71Fh 720h BANK 21 Unimplemented Read as `0' A7Fh Common RAM (Accesses 70h - 7Fh) BANK 15 780h Core Registers (Table 3-2) Unimplemented Read as `0' Core Registers (Table 3-2) A6Fh A70h -- -- -- -- -- CWG1DBR CWG1DBF CWG1CON0 CWG1CON1 CWG1CON2 -- -- -- -- -- -- -- -- -- -- A80h A0Bh A0Ch Common RAM (Accesses 70h - 7Fh) 68Bh 68Ch 68Dh 68Eh 68Fh 690h 691h 692h 693h 694h 695h 696h 697h 698h 699h 69Ah 69Bh 69Ch 69Dh 69Eh 69Fh 6A0h BANK 20 Unimplemented Read as `0' 9FFh Common RAM (Accesses 70h - 7Fh) BANK 14 700h Core Registers (Table 3-2) Unimplemented Read as `0' Core Registers (Table 3-2) 9EFh 9F0h -- -- -- -- -- PWM1DCL PWM1DCH PWM1CON PWM2DCL PWM2DCH PWM2CON PWM3DCL PWM3DCH PWM3CON PWM4DCL PWM4DCH PWM4CON -- -- -- A00h 98Bh 98Ch Common RAM (Accesses 70h - 7Fh) 60Bh 60Ch 60Dh 60Eh 60Fh 610h 611h 612h 613h 614h 615h 616h 617h 618h 619h 61Ah 61Bh 61Ch 61Dh 61Eh 61Fh 620h BANK 19 Unimplemented Read as `0' 97Fh Common RAM (Accesses 70h - 7Fh) BANK 13 680h Core Registers (Table 3-2) Unimplemented Read as `0' Core Registers (Table 3-2) 96Fh 970h -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 980h 90Bh 90Ch Common RAM (Accesses 70h - 7Fh) 58Bh 58Ch 58Dh 58Eh 58Fh 590h 591h 592h 593h 594h 595h 596h 597h 598h 599h 59Ah 59Bh 59Ch 59Dh 59Eh 59Fh 5A0h BANK 18 Unimplemented Read as `0' 8EFh 8F0h Common RAM (Accesses 70h - 7Fh) BANK 12 600h Core Registers (Table 3-2) Unimplemented Read as `0' Core Registers (Table 3-2) Unimplemented Read as `0' -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 900h 88Bh 88Ch 86Fh 870h 50Bh 50Ch 50Dh 50Eh 50Fh 510h 511h 512h 513h 514h 515h 516h 517h 518h 519h 51Ah 51Bh 51Ch 51Dh 51Eh 51Fh 520h BANK 17 880h 80Bh 80Ch Core Registers (Table 3-2) Unimplemented Read as `0' BANK 16 800h -- -- -- -- -- -- -- -- -- -- -- -- NCO1ACCL NCO1ACCH NCO1ACCU NCO1INCL NCO1INCH -- NCO1CON NCO1CLK BANK 11 580h Common RAM (Accesses 70h - 7Fh) Unimplemented Read as `0' BEFh BF0h BFFh Common RAM (Accesses 70h - 7Fh) PIC16(L)F1508/9 Common RAM (Accesses 70h - 7Fh) BANK 10 500h PIC16(L)F1508/9 MEMORY MAP, BANK 24-31 BANK 24 C00h BANK 25 C80h Core Registers (Table 3-2) Preliminary C0Bh C0Ch C0Dh C0Eh C0Fh C10h C11h C12h C13h C14h C15h C16h C17h C18h C19h C1Ah C1Bh C1Ch C1Dh C1Eh C1Fh C20h -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Core Registers (Table 3-2) C8Bh C8Ch C8Dh C8Eh C8Fh C90h C91h C92h C93h C94h C95h C96h C97h C98h C99h C9Ah C9Bh C9Ch C9Dh C9Eh C9Fh CA0h Unimplemented Read as `0' C6Fh C70h 2011 Microchip Technology Inc. CFFh Legend: Common RAM (Accesses 70h - 7Fh) BANK 26 D00h -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Core Registers (Table 3-2) D0Bh D0Ch D0Dh D0Eh D0Fh D10h D11h D12h D13h D14h D15h D16h D17h D18h D19h D1Ah D1Bh D1Ch D1Dh D1Eh D1Fh D20h Unimplemented Read as `0' CEFh CF0h CFFh Common RAM (Accesses 70h - 7Fh) BANK 27 D80h -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Core Registers (Table 3-2) D8Bh D8Ch D8Dh D8Eh D8Fh D90h D91h D92h D93h D94h D95h D96h D97h D98h D99h D9Ah D9Bh D9Ch D9Dh D9Eh D9Fh DA0h Unimplemented Read as `0' D6Fh D70h D7Fh Common RAM (Accesses 70h - 7Fh) = Unimplemented data memory locations, read as `0'. BANK 28 E00h -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Core Registers (Table 3-2) E0Bh E0Ch E0Dh E0Eh E0Fh E10h E11h E12h E13h E14h E15h E16h E17h E18h E19h E1Ah E1Bh E1Ch E1Dh E1Eh E1Fh E20h Unimplemented Read as `0' DEFh DF0h DFFh Common RAM (Accesses 70h - 7Fh) BANK 29 E80h -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Core Registers (Table 3-2) E8Bh E8Ch E8Dh E8Eh E8Fh E90h E91h E92h E93h E94h E95h E96h E97h E98h E99h E9Ah E9Bh E9Ch E9Dh E9Eh E9Fh EA0h Unimplemented Read as `0' E6Fh E70h E7Fh Common RAM (Accesses 70h - 7Fh) BANK 30 F00h -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BANK 31 F80h Core Registers (Table 3-2) Core Registers (Table 3-2) F0Bh F0Ch F0Dh F0Eh F0Fh F10h F11h F12h F13h F14h F15h F16h F17h See Table 3-7 for F18h register mapping F19h details F1Ah F1Bh F1Ch F1Dh F1Eh F1Fh F20h F8Bh F8Ch F8Dh F8Eh F8Fh F90h F91h F92h F93h F94h F95h F96h F97h See Table 3-7 for F98h register mapping F99h details F9Ah F9Bh F9Ch F9Dh F9Eh F9Fh FA0h F6Fh F70h FEFh FF0h Unimplemented Read as `0' EEFh EF0h EFFh Common RAM (Accesses 70h - 7Fh) F7Fh Common RAM (Accesses 70h - 7Fh) FFFh Common RAM (Accesses 70h - 7Fh) PIC16(L)F1508/9 DS41609A-page 26 TABLE 3-6: PIC16(L)F1508/9 TABLE 3-7: PIC16(L)F1508/9 MEMORY MAP, BANK 30-31 Bank 31 Bank 30 F0Ch F0Dh F0Eh F0Fh F10h F11h F12h F13h F14h F15h F16h F17h F18h F19h F1Ah F1Bh F1Ch F1Dh F1Eh F1Fh F20h F21h F22h F23h F24h F25h F26h F27h F2Ah F2Bh F2Ch F2Dh F2Eh F2Fh F31h F31h F32h F6Fh Legend: F8Ch -- -- -- CLCDATA CLC1CON CLC1POL CLC1SEL0 CLC1SEL1 CLC1GLS0 CLC1GLS1 CLC1GLS2 CLC1GLS3 CLC2CON CLC2POL CLC2SEL0 CLC2SEL1 CLC2GLS0 CLC2GLS1 CLC2GLS2 CLC2GLS3 CLC3CON CLC3POL CLC3SEL0 CLC3SEL1 CLC3GLS0 CLC3GLS1 CLC3GLS2 CLC3GLS3 CLC4CON CLC4POL CLC4SEL0 CLC4SEL1 CLC4GLS0 CLC4GLS1 CLC4GLS2 CLC4GLS3 Unimplemented Read as `0' FE3h FE4h FE5h FE6h FE7h FE8h FE9h FEAh FEBh FECh FEDh FEEh FEFh STATUS_SHAD WREG_SHAD BSR_SHAD PCLATH_SHAD FSR0L_SHAD FSR0H_SHAD FSR1L_SHAD FSR1H_SHAD -- STKPTR TOSL TOSH Unimplemented Read as `0' = Unimplemented data memory locations, read as `0'. 2011 Microchip Technology Inc. Preliminary DS41609A-page 27 PIC16(L)F1508/9 3.2.6 CORE FUNCTION REGISTERS SUMMARY The Core Function registers listed in Table 3-8 can be addressed from any Bank. TABLE 3-8: Addr Name CORE FUNCTION REGISTERS SUMMARY Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 0-31 x00h or INDF0 x80h Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx uuuu uuuu x01h or INDF1 x81h Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx uuuu uuuu x02h or PCL x82h Program Counter (PC) Least Significant Byte 0000 0000 0000 0000 ---1 1000 ---q quuu x03h or STATUS x83h -- -- -- TO PD Z DC C x04h or FSR0L x84h Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu x05h or FSR0H x85h Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 x06h or FSR1L x86h Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu x07h or FSR1H x87h Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000 ---0 0000 ---0 0000 0000 0000 uuuu uuuu -000 0000 -000 0000 0000 0000 0000 0000 x08h or BSR x88h -- x09h or WREG x89h -- BSR<4:0> Working Register x0Ah or PCLATH x8Ah -- x0Bh or INTCON x8Bh GIE Legend: -- Write Buffer for the upper 7 bits of the Program Counter PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as `0', r = reserved. Shaded locations are unimplemented, read as `0'. DS41609A-page 28 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 TABLE 3-9: Address SPECIAL FUNCTION REGISTER SUMMARY Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 0 00Ch PORTA -- -- RA5 RA4 RA3 RA2 RA1 RA0 --xx xxxx --xx xxxx 00Dh PORTB RB7 RB6 RB5 RB4 -- -- -- -- xxxx ---- xxxx ---- 00Eh PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx xxxx xxxx 00Fh -- Unimplemented -- -- 010h -- Unimplemented -- -- 011h PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF -- TMR2IF TMR1IF 0000 0-00 0000 0-00 012h PIR2 OSFIF C2IF C1IF -- BCL1IF NCO1IF -- -- 000- -0-- 000- -0-- 013h PIR3 -- -- -- -- CLC4IF CLC3IF CLC2IF CLC1IF ---- 0000 ---- 0000 014h -- Unimplemented 015h TMR0 Holding Register for the 8-bit Timer0 Count xxxx xxxx uuuu uuuu 016h TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Count xxxx xxxx uuuu uuuu 017h TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Count 018h T1CON 019h T1GCON 01Ah TMR2 Timer2 Module Register 01Bh PR2 Timer2 Period Register 01Ch T2CON 01Dh -- Unimplemented -- -- 01Eh -- Unimplemented -- -- 01Fh -- Unimplemented -- -- -- TMR1CS<1:0> TMR1GE T1GPOL -- T1CKPS<1:0> T1GTM T1GSPM T1OSCEN T1SYNC T1GGO/ DONE T1GVAL -- xxxx xxxx uuuu uuuu -- TMR1ON T1GSS<1:0> 0000 00-0 uuuu uu-u 0000 0x00 uuuu uxuu 0000 0000 0000 0000 1111 1111 1111 1111 T2OUTPS<3:0> TMR2ON T2CKPS<1:0> -000 0000 -000 0000 Bank 1 08Ch TRISA -- -- TRISA5 TRISA4 --(2) TRISA2 TRISA1 TRISA0 --11 1111 --11 1111 08Dh TRISB TRISB7 TRISB6 TRISB5 TRISB4 -- -- -- -- 1111 ---- 1111 ---- 08Eh TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111 08Fh -- Unimplemented -- -- 090h -- Unimplemented -- -- 091h PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE -- TMR2IE TMR1IE 0000 0-00 0000 0-00 092h PIE2 OSFIE C2IE C1IE -- BCL1IE NCO1IE -- -- 000- 00-- 000- 00-- 093h PIE3 -- -- -- -- CLC4IE CLC3IE CLC2IE CLC1IE ---- 0000 ---- 0000 094h -- 095h OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA STKOVF STKUNF -- RWDT -- -- Unimplemented 096h PCON 097h WDTCON 098h -- 099h OSCCON -- 09Ah OSCSTAT SOSCR 09Bh ADRESL 09Ch ADRESH 09Dh ADCON0 -- 09Eh ADCON1 ADFM 09Fh ADCON2 -- RMCLR PS<2:0> RI POR WDTPS<4:0> BOR 00-1 11qq qq-q qquu SWDTEN --01 0110 --01 0110 Unimplemented -- IRCF<3:0> -- OSTS HFIOFR -- -- -- SCS<1:0> LFIOFR -- 1111 1111 1111 1111 -- -011 1-00 -011 1-00 HFIOFS 0-q0 --00 q-qq --qq xxxx xxxx uuuu uuuu A/D Result Register High xxxx xxxx uuuu uuuu CHS<4:0> ADCS<2:0> TRIGSEL<3:0> GO/DONE -- -- -- -- ADON ADPREF<1:0> -- -- -000 0000 -000 0000 0000 --00 0000 --00 0000 ---- 0000 ---- Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as `0'. Note 1: PIC16F1508/9 only. 2: Unimplemented, read as `1'. 2011 Microchip Technology Inc. Preliminary DS41609A-page 29 PIC16(L)F1508/9 TABLE 3-9: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 2 10Ch LATA -- -- LATA5 LATA4 -- LATA2 LATA1 LATA0 --xx -xxx --uu -uuu 10Dh LATB LATB7 LATB6 LATB5 LATB4 -- -- -- -- xxxx ---- uuuu ---- 10Eh LATC LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 xxxx xxxx uuuu uuuu 10Fh -- Unimplemented -- -- 110h -- Unimplemented -- -- 111h CM1CON0 C1ON C1OUT 112h CM1CON1 C1INTP C1INTN 113h CM2CON0 C2ON C2OUT 114h CM2CON1 C2INTP C2INTN 115h CMOUT -- -- -- -- -- -- 116h BORCON SBOREN BORFS -- -- -- -- 117h FVRCON FVREN FVRRDY TSEN TSRNG 118h DACCON0 DACEN -- DACOE1 DACOE2 119h DACCON1 -- 11Ah to 11Ch -- C1OE C1POL -- C1PCH<1:0> C2OE C1SP -- C2POL -- C2PCH<1:0> C1HYS C1NCH<2:0> C2SP -- C2HYS MC2OUT -- -- -- 0000 -000 0000 -000 ---- --00 ---- --00 BORRDY 10-- ---q uu-- ---u -- DACR<4:0> 0q00 0000 0q00 0000 0-00 -0-- 0-00 -0----0 0000 ---0 0000 Unimplemented -- 0000 -100 0000 -100 MC1OUT ADFVR<1:0> DACPSS 0000 -100 0000 -100 0000 -000 0000 -000 C2SYNC C2NCH<2:0> CDAFVR<1:0> -- C1SYNC -- -- -- SSSEL T1GSEL -- CLC1SEL NCO1SEL -- 11Dh APFCON 11Eh -- Unimplemented -- -- 11Fh -- Unimplemented -- -- ---0 0-00 ---0 0-00 Bank 3 18Ch ANSELA -- -- -- ANSA4 -- ANSA2 ANSA1 ANSA0 ---1 -111 ---1 -111 18Dh ANSELB -- -- ANSB5 ANSB4 -- -- -- -- --11 ---- --11 ---- 18Eh ANSELC ANSC7 ANSC6 -- -- ANSC3 ANSC2 ANSC1 ANSC0 11-- 1111 11-- 1111 18Fh -- Unimplemented -- -- 190h -- Unimplemented -- -- 191h PMADRL Flash Program Memory Address Register Low Byte 192h PMADRH 193h PMDATL 194h PMDATH -- -- 195h PMCON1 --(2) CFGS 196h PMCON2 197h VREGCON(1) -- 0000 0000 0000 0000 Flash Program Memory Address Register High Byte -000 0000 -000 0000 Flash Program Memory Read Data Register Low Byte xxxx xxxx uuuu uuuu Flash Program Memory Read Data Register High Byte LWLO FREE --xx xxxx --uu uuuu WRERR WREN WR RD 0000 x000 0000 q000 -- -- VREGPM Reserved ---- --01 ---- --01 Flash Program Memory Control Register 2 -- -- -- 0000 0000 0000 0000 -- 198h -- Unimplemented 199h RCREG USART Receive Data Register 0000 0000 0000 0000 19Ah TXREG USART Transmit Data Register 0000 0000 0000 0000 19Bh SPBRGL Baud Rate Generator Data Register Low 0000 0000 0000 0000 19Ch SPBRGH Baud Rate Generator Data Register High 19Dh RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x 19Eh TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010 19Fh BAUDCON ABDOVF RCIDL -- SCKP BRG16 -- WUE ABDEN 01-0 0-00 01-0 0-00 -- -- 0000 0000 0000 0000 Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as `0'. Note 1: PIC16F1508/9 only. 2: Unimplemented, read as `1'. DS41609A-page 30 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 TABLE 3-9: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 4 20Ch WPUA -- -- WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 --11 1111 --11 1111 20Dh WPUB WPUB7 WPUB6 WPUB5 WPUB4 -- -- -- -- 1111 ---- 1111 ---- 20Eh to 210h -- Unimplemented 211h SSP1BUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu 212h SSP1ADD ADD<7:0> 0000 0000 0000 0000 213h SSP1MSK MSK<7:0> 214h SSP1STAT SMP CKE D/A P 215h SSP1CON1 WCOL SSPOV SSPEN CKP 216h SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 0000 217h SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000 0000 0000 0000 218h to 21Fh -- S -- 1111 1111 1111 1111 R/W UA BF 0000 0000 0000 0000 SSPM<3:0> 0000 0000 0000 0000 -- Unimplemented -- -- -- Unimplemented -- -- -- Unimplemented -- -- -- Unimplemented -- -- Bank 5 28Ch to 29Fh Bank 6 30Ch to 31Fh Bank 7 38Ch to 390h 391h IOCAP -- -- IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 --00 0000 --00 0000 392h IOCAN -- -- IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 --00 0000 --00 0000 393h IOCAF -- -- IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 --00 0000 --00 0000 394h IOCBP IOCBP7 IOCBP6 IOCBP5 IOCBP4 -- -- -- -- 0000 ---- 0000 ---- 395h IOCBN IOCBN7 IOCBN6 IOCBN5 IOCBN4 -- -- -- -- 0000 ---- 0000 ---- 396h IOCBF IOCBF7 IOCBF6 IOCBF5 IOCBF4 -- -- -- -- 0000 ---- 0000 ---- 397h to 39Fh -- Unimplemented -- -- -- Unimplemented -- -- -- Unimplemented -- -- Bank 8 40Ch to 41Fh Bank 9 48Ch to 497h 498h NCO1ACCL NCO1ACC<7:0> 0000 0000 0000 0000 499h NCO1ACCH NCO1ACC<15:8> 0000 0000 0000 0000 49Ah NCO1ACCU NCO1ACC<19:16> 0000 0000 0000 0000 49Bh NCO1INCL NCO1INC<7:0> 0000 0000 0000 0000 49Ch NCO1INCH NCO1INC<15:8> 0000 0000 0000 0000 49Dh -- 49Eh NCO1CON 49Fh NCO1CLK Unimplemented N1EN N1OE N1PWS<2:0> -- N1OUT N1POL -- -- -- -- -- -- N1PFM N1CKS<1:0> -- 0000 ---0 0000 ---0 0000 --00 0000 --00 Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as `0'. Note 1: PIC16F1508/9 only. 2: Unimplemented, read as `1'. 2011 Microchip Technology Inc. Preliminary DS41609A-page 31 PIC16(L)F1508/9 TABLE 3-9: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Value on POR, BOR Value on all other Resets Unimplemented -- -- Unimplemented -- -- Unimplemented -- -- Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bank 10 50Ch to 51Fh -- Bank 11 58Ch to 59Fh -- Bank 12 60Ch to 610h -- 611h PWM1DCL 612h PWM1DCH 613h PWM1CON0 614h PWM2DCL 615h PWM2DCH 616h PWM2CON0 617h PWM3DCL 618h PWM3DCH 619h PWM3CON0 61Ah PWM4DCL 61Bh PWM4DCH 61Ch PWM4CON0 61Dh to 61Fh -- PWM1DCL<7:6> -- -- -- -- -- -- PWM1DCH<7:0> PWM1EN xxxx xxxx uuuu uuuu PWM1OE PWM1OUT PWM1POL -- -- -- -- 0000 ---- 0000 ---- -- -- -- -- -- 00-- ---- 00-- ---- -- -- -- -- 0000 ---- 0000 ---- -- -- -- -- 00-- ---- 00-- ---- -- -- -- -- 0000 ---- 0000 ---- -- -- -- -- 00-- ---- 00-- ---- -- -- -- PWM2DCL<7:6> -- PWM2DCH<7:0> PWM2EN PWM2OE PWM2OUT PWM2POL PWM3DCL<7:6> -- -- xxxx xxxx uuuu uuuu PWM3DCH<7:0> PWM3EN PWM3OE PWM3OUT PWM3POL PWM4DCL<7:6> -- -- xxxx xxxx uuuu uuuu PWM4DCH<7:0> PWM4EN 00-- ---- 00-- ---- PWM4OE PWM4OUT PWM4POL -- xxxx xxxx uuuu uuuu 0000 ---- 0000 ---- Unimplemented -- -- Unimplemented -- -- Bank 13 68Ch to 690h -- 691h CWG1DBR -- -- CWG1DBR<5:0> 692h CWG1DBF -- -- CWG1DBF<5:0> 693h CWG1CON0 G1EN G1OEB 694h CWG1CON1 695h CWG1CON2 696h to 69Fh -- G1ASDLB<1:0> G1ASE G1ARSEN G1OEA G1POLB G1ASDLA<1:0> -- -- G1POLA -- G1ASDC2 Unimplemented -- --00 0000 --00 0000 --xx xxxx --xx xxxx -- G1CS0 G1IS<2:0> 0000 0--0 0000 0--0 0000 -000 0000 -000 G1ASDC1 G1ASDSFLT G1ASDSCLC2 00-- --00 00-- --00 -- -- Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as `0'. Note 1: PIC16F1508/9 only. 2: Unimplemented, read as `1'. DS41609A-page 32 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 TABLE 3-9: Address Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on POR, BOR Value on all other Resets Unimplemented -- -- Unimplemented -- -- Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Banks 14-29 x0Ch/ x8Ch -- x1Fh/ x9Fh -- Bank 30 F0Ch to F0Eh -- F0Fh CLCDATA -- -- -- -- F10h CLC1CON LC1EN LC1OE LC1OUT LC1INTP F11h CLC1POL LC1POL -- -- -- F12h CLC1SEL0 -- LC1D2S<2:0> -- LC1D1S<2:0> F13h CLC1SEL1 -- LC1D4S<2:0> -- LC1D3S<2:0> F14h CLC1GLS0 LC1G1D4T LC1G1D4N LC1G1D3T LC1G1D3N LC1G1D2T LC1G1D2N LC1G1D1T LC1G1D1N xxxx xxxx uuuu uuuu F15h CLC1GLS1 LC1G2D4T LC1G2D4N LC1G2D3T LC1G2D3N LC1G2D2T LC1G2D2N LC1G2D1T LC1G2D1N xxxx xxxx uuuu uuuu F16h CLC1GLS2 LC1G3D4T LC1G3D4N LC1G3D3T LC1G3D3N LC1G3D2T LC1G3D2N LC1G3D1T LC1G3D1N xxxx xxxx uuuu uuuu F17h CLC1GLS3 LC1G4D4T LC1G4D4N LC1G4D3T LC1G4D3N LC1G4D2T LC1G4D2N LC1G4D1T LC1G4D1N xxxx xxxx uuuu uuuu F18h CLC2CON LC2EN LC2OE LC2OUT LC2INTP F19h CLC2POL LC2POL -- -- -- F1Ah CLC2SEL0 -- LC2D2S<2:0> -- LC2D1S<2:0> F1Bh CLC2SEL1 -- LC2D4S<2:0> -- LC2D3S<2:0> F1Ch CLC2GLS0 LC2G1D4T LC2G1D4N LC2G1D3T LC2G1D3N LC2G1D2T LC2G1D2N LC2G1D1T LC2G1D1N xxxx xxxx uuuu uuuu F1Dh CLC2GLS1 LC2G2D4T LC2G2D4N LC2G2D3T LC2G2D3N LC2G2D2T LC2G2D2N LC2G2D1T LC2G2D1N xxxx xxxx uuuu uuuu F1Eh CLC2GLS2 LC2G3D4T LC2G3D4N LC2G3D3T LC2G3D3N LC2G3D2T LC2G3D2N LC2G3D1T LC2G3D1N xxxx xxxx uuuu uuuu F1Fh CLC2GLS3 LC2G4D4T LC2G4D4N LC2G4D3T LC2G4D3N LC2G4D2T LC2G4D2N LC2G4D1T LC2G4D1N xxxx xxxx uuuu uuuu F20h CLC3CON LC3EN LC3OE LC3OUT LC3INTP F21h CLC3POL LC3POL -- -- -- F22h CLC3SEL0 -- LC3D2S<2:0> -- LC3D1S<2:0> F23h CLC3SEL1 -- LC3D4S<2:0> -- LC3D3S<2:0> F24h CLC3GLS0 LC3G1D4T LC3G1D4N LC3G1D3T LC3G1D3N LC3G1D2T LC3G1D2N LC3G1D1T LC3G1D1N xxxx xxxx uuuu uuuu F25h CLC3GLS1 LC3G2D4T LC3G2D4N LC3G2D3T LC3G2D3N LC3G2D2T LC3G2D2N LC3G2D1T LC3G2D1N xxxx xxxx uuuu uuuu F26h CLC3GLS2 LC3G3D4T LC3G3D4N LC3G3D3T LC3G3D3N LC3G3D2T LC3G3D2N LC3G3D1T LC3G3D1N xxxx xxxx uuuu uuuu F27h CLC3GLS3 LC3G4D4T LC3G4D4N LC3G4D3T LC3G4D3N LC3G4D2T LC3G4D2N LC3G4D1T LC3G4D1N xxxx xxxx uuuu uuuu F28h CLC4CON LC4EN LC4OE LC4OUT LC4INTP F29h CLC4POL LC4POL -- -- -- F2Ah CLC4SEL0 -- LC4D2S<2:0> -- LC4D1S<2:0> F2Bh CLC4SEL1 -- LC4D4S<2:0> -- LC4D3S<2:0> F2Ch CLC4GLS0 LC4G1D4T LC4G1D4N LC4G1D3T LC4G1D3N LC4G1D2T LC4G1D2N LC4G1D1T LC4G1D1N xxxx xxxx uuuu uuuu F2Dh CLC4GLS1 LC4G2D4T LC4G2D4N LC4G2D3T LC4G2D3N LC4G2D2T LC4G2D2N LC4G2D1T LC4G2D1N xxxx xxxx uuuu uuuu F2Eh CLC4GLS2 LC4G3D4T LC4G3D4N LC4G3D3T LC4G3D3N LC4G3D2T LC4G3D2N LC4G3D1T LC4G3D1N xxxx xxxx uuuu uuuu F2Fh CLC4GLS3 LC4G4D4T LC4G4D4N LC4G4D3T LC4G4D3N LC4G4D2T LC4G4D2N LC4G4D1T LC4G4D1N xxxx xxxx uuuu uuuu -- Unimplemented F30h to F6Fh MLC4OUT MLC3OUT LC1INTN MLC2OUT LC1G4POL LC1G3POL LC1G2POL LC2INTN LC4INTN -xxx -xxx -uuu -uuu 0000 0000 0000 0000 LC2G1POL 0--- xxxx 0--- uuuu -xxx -xxx -uuu -uuu -xxx -xxx -uuu -uuu 0000 0000 0000 0000 LC3G1POL 0--- xxxx 0--- uuuu -xxx -xxx -uuu -uuu -xxx -xxx -uuu -uuu LC4MODE<2:0> LC4G4POL LC4G3POL LC4G2POL 0--- xxxx 0--- uuuu -xxx -xxx -uuu -uuu LC3MODE<2:0> LC3G4POL LC3G3POL LC3G2POL ---- 0000 ---- 0000 0000 0000 0000 0000 LC1G1POL LC2MODE<2:0> LC2G4POL LC2G3POL LC2G2POL LC3INTN MLC1OUT LC1MODE<2:0> 0000 0000 0000 0000 LC4G1POL 0--- xxxx 0--- uuuu -xxx -xxx -uuu -uuu -xxx -xxx -uuu -uuu -- -- Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as `0'. Note 1: PIC16F1508/9 only. 2: Unimplemented, read as `1'. 2011 Microchip Technology Inc. Preliminary DS41609A-page 33 PIC16(L)F1508/9 TABLE 3-9: Address Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets -- -- Bank 31 F8Ch -- FE3h -- FE4h STATUS_ Unimplemented -- -- -- -- -- Z_SHAD DC_SHAD C_SHAD ---- -xxx ---- -uuu SHAD FE5h WREG_ Working Register Shadow xxxx xxxx uuuu uuuu SHAD FE6h BSR_ -- -- -- Bank Select Register Shadow ---x xxxx ---u uuuu SHAD FE7h PCLATH_ -- Program Counter Latch High Register Shadow -xxx xxxx uuuu uuuu SHAD FE8h FSR0L_ Indirect Data Memory Address 0 Low Pointer Shadow xxxx xxxx uuuu uuuu Indirect Data Memory Address 0 High Pointer Shadow xxxx xxxx uuuu uuuu Indirect Data Memory Address 1 Low Pointer Shadow xxxx xxxx uuuu uuuu Indirect Data Memory Address 1 High Pointer Shadow xxxx xxxx uuuu uuuu SHAD FE9h FSR0H_ SHAD FEAh FSR1L_ SHAD FEBh FSR1H_ SHAD FECh -- FEDh STKPTR FEEh TOSL FEFh TOSH Unimplemented -- -- -- -- Current Stack Pointer Top-of-Stack Low byte -- -- ---1 1111 ---1 1111 xxxx xxxx uuuu uuuu Top-of-Stack High byte -xxx xxxx -uuu uuuu Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as `0'. Note 1: PIC16F1508/9 only. 2: Unimplemented, read as `1'. DS41609A-page 34 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 3.3 PCL and PCLATH 3.3.2 The Program Counter (PC) is 15 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<14:8>) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. Figure 3-4 shows the five situations for the loading of the PC. FIGURE 3-4: 14 LOADING OF PC IN DIFFERENT SITUATIONS PCH PCL 0 PC 6 7 8 0 PCLATH Instruction with PCL as Destination ALU Result 14 PCH PCL 0 PC 6 4 0 PCLATH GOTO, CALL PCH PCL 0 6 7 0 CALLW W 14 PCH PCL BRW 15 PC + W 14 PCH PCL PC If using BRW, load the W register with the desired unsigned address and execute BRW. The entire PC will be loaded with the address PC + 1 + W. 0 BRA 15 PC + OPCODE <8:0> 3.3.1 BRANCHING The branching instructions add an offset to the PC. This allows relocatable code and code that crosses page boundaries. There are two forms of branching, BRW and BRA. The PC will have incremented to fetch the next instruction in both cases. When using either branching instruction, a PCL memory boundary may be crossed. 0 PC COMPUTED FUNCTION CALLS A computed function CALL allows programs to maintain tables of functions and provide another way to execute state machines or look-up tables. When performing a table read using a computed function CALL, care should be exercised if the table location crosses a PCL memory boundary (each 256-byte block). 3.3.4 8 PCLATH 3.3.3 The CALLW instruction enables computed calls by combining PCLATH and W to form the destination address. A computed CALLW is accomplished by loading the W register with the desired address and executing CALLW. The PCL register is loaded with the value of W and PCH is loaded with PCLATH. OPCODE <10:0> 14 A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When performing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256-byte block). Refer to Application Note AN556, "Implementing a Table Read" (DS00556). If using the CALL instruction, the PCH<2:0> and PCL registers are loaded with the operand of the CALL instruction. PCH<6:3> is loaded with PCLATH<6:3>. 11 PC COMPUTED GOTO If using BRA, the entire PC will be loaded with PC + 1 +, the signed value of the operand of the BRA instruction. MODIFYING PCL Executing any instruction with the PCL register as the destination simultaneously causes the Program Counter PC<14:8> bits (PCH) to be replaced by the contents of the PCLATH register. This allows the entire contents of the program counter to be changed by writing the desired upper 7 bits to the PCLATH register. When the lower 8 bits are written to the PCL register, all 15 bits of the program counter will change to the values contained in the PCLATH register and those being written to the PCL register. 2011 Microchip Technology Inc. Preliminary DS41609A-page 35 PIC16(L)F1508/9 3.4 Stack 3.4.1 The stack is available through the TOSH, TOSL and STKPTR registers. STKPTR is the current value of the Stack Pointer. TOSH:TOSL register pair points to the TOP of the stack. Both registers are read/writable. TOS is split into TOSH and TOSL due to the 15-bit size of the PC. To access the stack, adjust the value of STKPTR, which will position TOSH:TOSL, then read/write to TOSH:TOSL. STKPTR is 5 bits to allow detection of overflow and underflow. All devices have a 16-level x 15-bit wide hardware stack (refer to Figures 3-5 through 3-8). The stack space is not part of either program or data space. The PC is PUSHed onto the stack when CALL or CALLW instructions are executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation. The stack operates as a circular buffer if the STVREN bit is programmed to `0` (Configuration Words). This means that after the stack has been PUSHed sixteen times, the seventeenth PUSH overwrites the value that was stored from the first PUSH. The eighteenth PUSH overwrites the second PUSH (and so on). The STKOVF and STKUNF flag bits will be set on an Overflow/Underflow, regardless of whether the Reset is enabled. Note: Care should be taken when modifying the STKPTR while interrupts are enabled. During normal program operation, CALL, CALLW and Interrupts will increment STKPTR while RETLW, RETURN, and RETFIE will decrement STKPTR. At any time STKPTR can be inspected to see how much stack is left. The STKPTR always points at the currently used place on the stack. Therefore, a CALL or CALLW will increment the STKPTR and then write the PC, and a return will unload the PC and then decrement the STKPTR. Note 1: There are no instructions/mnemonics called PUSH or POP. These are actions that occur from the execution of the CALL, CALLW, RETURN, RETLW and RETFIE instructions or the vectoring to an interrupt address. FIGURE 3-5: ACCESSING THE STACK Reference Figure 3-5 through Figure 3-8 for examples of accessing the stack. ACCESSING THE STACK EXAMPLE 1 TOSH:TOSL 0x0F STKPTR = 0x1F Stack Reset Disabled (STVREN = 0) 0x0E 0x0D 0x0C 0x0B 0x0A Initial Stack Configuration: 0x09 After Reset, the stack is empty. The empty stack is initialized so the Stack Pointer is pointing at 0x1F. If the Stack Overflow/Underflow Reset is enabled, the TOSH/TOSL registers will return `0'. If the Stack Overflow/Underflow Reset is disabled, the TOSH/TOSL registers will return the contents of stack address 0x0F. 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 0x00 TOSH:TOSL DS41609A-page 36 0x1F 0x0000 Preliminary STKPTR = 0x1F Stack Reset Enabled (STVREN = 1) 2011 Microchip Technology Inc. PIC16(L)F1508/9 FIGURE 3-6: ACCESSING THE STACK EXAMPLE 2 0x0F 0x0E 0x0D 0x0C 0x0B 0x0A 0x09 This figure shows the stack configuration after the first CALL or a single interrupt. If a RETURN instruction is executed, the return address will be placed in the Program Counter and the Stack Pointer decremented to the empty state (0x1F). 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 TOSH:TOSL FIGURE 3-7: 0x00 Return Address STKPTR = 0x00 ACCESSING THE STACK EXAMPLE 3 0x0F 0x0E 0x0D 0x0C After seven CALLs or six CALLs and an interrupt, the stack looks like the figure on the left. A series of RETURN instructions will repeatedly place the return addresses into the Program Counter and pop the stack. 0x0B 0x0A 0x09 0x08 0x07 TOSH:TOSL 2011 Microchip Technology Inc. 0x06 Return Address 0x05 Return Address 0x04 Return Address 0x03 Return Address 0x02 Return Address 0x01 Return Address 0x00 Return Address Preliminary STKPTR = 0x06 DS41609A-page 37 PIC16(L)F1508/9 FIGURE 3-8: ACCESSING THE STACK EXAMPLE 4 TOSH:TOSL 3.4.2 0x0F Return Address 0x0E Return Address 0x0D Return Address 0x0C Return Address 0x0B Return Address 0x0A Return Address 0x09 Return Address 0x08 Return Address 0x07 Return Address 0x06 Return Address 0x05 Return Address 0x04 Return Address 0x03 Return Address 0x02 Return Address 0x01 Return Address 0x00 Return Address When the stack is full, the next CALL or an interrupt will set the Stack Pointer to 0x10. This is identical to address 0x00 so the stack will wrap and overwrite the return address at 0x00. If the Stack Overflow/Underflow Reset is enabled, a Reset will occur and location 0x00 will not be overwritten. STKPTR = 0x10 OVERFLOW/UNDERFLOW RESET If the STVREN bit in Configuration Words is programmed to `1', the device will be reset if the stack is PUSHed beyond the sixteenth level or POPed beyond the first level, setting the appropriate bits (STKOVF or STKUNF, respectively) in the PCON register. 3.5 Indirect Addressing The INDFn registers are not physical registers. Any instruction that accesses an INDFn register actually accesses the register at the address specified by the File Select Registers (FSR). If the FSRn address specifies one of the two INDFn registers, the read will return `0' and the write will not occur (though Status bits may be affected). The FSRn register value is created by the pair FSRnH and FSRnL. The FSR registers form a 16-bit address that allows an addressing space with 65536 locations. These locations are divided into three memory regions: * Traditional Data Memory * Linear Data Memory * Program Flash Memory DS41609A-page 38 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 FIGURE 3-9: INDIRECT ADDRESSING 0x0000 0x0000 Traditional Data Memory 0x0FFF 0x0FFF 0x1000 Reserved 0x1FFF 0x2000 Linear Data Memory 0x29AF 0x29B0 FSR Address Range Reserved 0x7FFF 0x8000 0x0000 Program Flash Memory 0xFFFF Note: 0x7FFF Not all memory regions are completely implemented. Consult device memory tables for memory limits. 2011 Microchip Technology Inc. Preliminary DS41609A-page 39 PIC16(L)F1508/9 3.5.1 TRADITIONAL DATA MEMORY The traditional data memory is a region from FSR address 0x000 to FSR address 0xFFF. The addresses correspond to the absolute addresses of all SFR, GPR and common registers. FIGURE 3-10: TRADITIONAL DATA MEMORY MAP Direct Addressing 4 BSR 0 6 Indirect Addressing From Opcode 0 7 0 Bank Select Location Select 0x00 FSRxH 0 0 0 7 FSRxL 0 0 Bank Select 00000 00001 00010 11111 Bank 0 Bank 1 Bank 2 Bank 31 Location Select 0x7F DS41609A-page 40 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 3.5.2 3.5.3 LINEAR DATA MEMORY The linear data memory is the region from FSR address 0x2000 to FSR address 0x29AF. This region is a virtual region that points back to the 80-byte blocks of GPR memory in all the banks. Unimplemented memory reads as 0x00. Use of the linear data memory region allows buffers to be larger than 80 bytes because incrementing the FSR beyond one bank will go directly to the GPR memory of the next bank. The 16 bytes of common memory are not included in the linear data memory region. FIGURE 3-11: 7 FSRnH 0 0 1 LINEAR DATA MEMORY MAP 0 7 FSRnL To make constant data access easier, the entire program Flash memory is mapped to the upper half of the FSR address space. When the MSB of FSRnH is set, the lower 15 bits are the address in program memory which will be accessed through INDF. Only the lower 8 bits of each memory location is accessible via INDF. Writing to the program Flash memory cannot be accomplished via the FSR/INDF interface. All instructions that access program Flash memory via the FSR/INDF interface will require one additional instruction cycle to complete. FIGURE 3-12: 7 1 0 PROGRAM FLASH MEMORY FSRnH PROGRAM FLASH MEMORY MAP 0 Location Select Location Select 0x2000 7 FSRnL 0x8000 0 0x0000 0x020 Bank 0 0x06F 0x0A0 Bank 1 0x0EF 0x120 Program Flash Memory (low 8 bits) Bank 2 0x16F 0xF20 Bank 30 0x29AF 2011 Microchip Technology Inc. 0xF6F Preliminary 0xFFFF 0x7FFF DS41609A-page 41 PIC16(L)F1508/9 NOTES: DS41609A-page 42 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 4.0 DEVICE CONFIGURATION Device configuration consists of Configuration Words, Code Protection and Device ID. 4.1 Configuration Words There are several Configuration Word bits that allow different oscillator and memory protection options. These are implemented as Configuration Word 1 at 8007h and Configuration Word 2 at 8008h. Note: The DEBUG bit in Configuration Words is managed automatically by device development tools including debuggers and programmers. For normal device operation, this bit should be maintained as a '1'. 2011 Microchip Technology Inc. Preliminary DS41609A-page 43 PIC16(L)F1508/9 REGISTER 4-1: CONFIG1: CONFIGURATION WORD 1 R/P-1 R/P-1 R/P-1 FCMEN IESO CLKOUTEN R/P-1 R/P-1 BOREN<1:0> U-1 -- bit 13 R/P-1 R/P-1 R/P-1 CP MCLRE PWRTE bit 8 R/P-1 R/P-1 R/P-1 R/P-1 WDTE<1:0> R/P-1 FOSC<2:0> bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as `1' `0' = Bit is cleared `1' = Bit is set -n = Value when blank or after Bulk Erase bit 13 FCMEN: Fail-Safe Clock Monitor Enable bit 1 = Fail-Safe Clock Monitor is enabled 0 = Fail-Safe Clock Monitor is disabled bit 12 IESO: Internal External Switchover bit 1 = Internal/External Switchover mode is enabled 0 = Internal/External Switchover mode is disabled bit 11 CLKOUTEN: Clock Out Enable bit 1 = CLKOUT function is disabled. I/O function on the CLKOUT pin 0 = CLKOUT function is enabled on the CLKOUT pin bit 10-9 BOREN<1:0>: Brown-out Reset Enable bits(1) 11 = BOR enabled 10 = BOR enabled during operation and disabled in Sleep 01 = BOR controlled by SBOREN bit of the BORCON register 00 = BOR disabled bit 8 Unimplemented: Read as `1' bit 7 CP: Code Protection bit(2) 1 = Program memory code protection is disabled 0 = Program memory code protection is enabled bit 6 MCLRE: MCLR/VPP Pin Function Select bit If LVP bit = 1: This bit is ignored. If LVP bit = 0: 1 = MCLR/VPP pin function is MCLR; Weak pull-up enabled. 0 = MCLR/VPP pin function is digital input; MCLR internally disabled; Weak pull-up under control of WPUE3 bit. bit 5 PWRTE: Power-Up Timer Enable bit 1 = PWRT disabled 0 = PWRT enabled bit 4-3 WDTE<1:0>: Watchdog Timer Enable bits 11 = WDT enabled 10 = WDT enabled while running and disabled in Sleep 01 = WDT controlled by the SWDTEN bit in the WDTCON register 00 = WDT disabled bit 2-0 FOSC<2:0>: Oscillator Selection bits 111 = ECH:External clock, High-Power mode: on CLKIN pin 110 = ECM: External clock, Medium-Power mode: on CLKIN pin 101 = ECL: External clock, Low-Power mode: on CLKIN pin 100 = INTOSC oscillator: I/O function on CLKIN pin 011 = EXTRC oscillator: External RC circuit connected to CLKIN pin 010 = HS oscillator: High-speed crystal/resonator connected between OSC1 and OSC2 pins 001 = XT oscillator: Crystal/resonator connected between OSC1 and OSC2 pins 000 = LP oscillator: Low-power crystal connected between OSC1 and OSC2 pins Note 1: 2: Enabling Brown-out Reset does not automatically enable Power-up Timer. Once enabled, code-protect can only be disabled by bulk erasing the device. DS41609A-page 44 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 REGISTER 4-2: CONFIG2: CONFIGURATION WORD 2 R/P-1 LVP R/P-1 DEBUG (3) R/P-1 R/P-1 R/P-1 U-1 LPBOR BORV STVREN -- bit 13 bit 8 U-1 U-1 U-1 U-1 U-1 U-1 -- -- -- -- -- -- R/P-1 R/P-1 WRT<1:0> bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as `1' `0' = Bit is cleared `1' = Bit is set -n = Value when blank or after Bulk Erase bit 13 LVP: Low-Voltage Programming Enable bit(1) 1 = Low-voltage programming enabled 0 = High-voltage on MCLR must be used for programming bit 12 DEBUG: In-Circuit Debugger Mode bit(3) 1 = In-Circuit Debugger disabled, ICSPCLK and ICSPDAT are general purpose I/O pins 0 = In-Circuit Debugger enabled, ICSPCLK and ICSPDAT are dedicated to the debugger bit 11 LPBOR: Low-Power BOR Enable bit 1 = Low-Power Brown-out Reset is disabled 0 = Low-Power Brown-out Reset is enabled bit 10 BORV: Brown-out Reset Voltage Selection bit(2) 1 = Brown-out Reset voltage (Vbor), low trip point selected. 0 = Brown-out Reset voltage (Vbor), high trip point selected. bit 9 STVREN: Stack Overflow/Underflow Reset Enable bit 1 = Stack Overflow or Underflow will cause a Reset 0 = Stack Overflow or Underflow will not cause a Reset bit 8-2 Unimplemented: Read as `1' bit 1-0 WRT<1:0>: Flash Memory Self-Write Protection bits 2 kW Flash memory: 11 = Write protection off 10 = 000h to 1FFh write-protected, 200h to 7FFh may be modified 01 = 000h to 3FFh write-protected, 400h to 7FFh may be modified 00 = 000h to 7FFh write-protected, no addresses may be modified Note 1: 2: 3: The LVP bit cannot be programmed to `0' when Programming mode is entered via LVP. See Vbor parameter for specific trip point voltages. The DEBUG bit in Configuration Words is managed automatically by device development tools including debuggers and programmers. For normal device operation, this bit should be maintained as a '1'. 2011 Microchip Technology Inc. Preliminary DS41609A-page 45 PIC16(L)F1508/9 4.2 Code Protection Code protection allows the device to be protected from unauthorized access. Internal access to the program memory is unaffected by any code protection setting. 4.2.1 PROGRAM MEMORY PROTECTION The entire program memory space is protected from external reads and writes by the CP bit in Configuration Words. When CP = 0, external reads and writes of program memory are inhibited and a read will return all `0's. The CPU can continue to read program memory, regardless of the protection bit settings. Writing the program memory is dependent upon the write protection setting. See Section 4.3 "Write Protection" for more information. 4.3 Write Protection Write protection allows the device to be protected from unintended self-writes. Applications, such as bootloader software, can be protected while allowing other regions of the program memory to be modified. The WRT<1:0> bits in Configuration Words define the size of the program memory block that is protected. 4.4 User ID Four memory locations (8000h-8003h) are designated as ID locations where the user can store checksum or other code identification numbers. These locations are readable and writable during normal execution. See Section 10.4 "User ID, Device ID and Configuration Word Access" for more information on accessing these memory locations. For more information on checksum calculation, see the "PIC12(L)F1501/PIC16(L)F150X Memory Programming Specification" (DS41573). DS41609A-page 46 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 4.5 Device ID and Revision ID The memory location 8006h is where the Device ID and Revision ID are stored. The upper nine bits hold the Device ID. The lower five bits hold the Revision ID. See Section 10.4 "User ID, Device ID and Configuration Word Access" for more information on accessing these memory locations. Development tools, such as device programmers and debuggers, may be used to read the Device ID and Revision ID. REGISTER 4-3: DEVICEID: DEVICE ID REGISTER R R R R R R DEV<8:3> bit 13 R R bit 8 R R R DEV<2:0> R R R REV<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `1' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared P = Programmable bit bit 13-5 DEV<8:0>: Device ID bits Device bit 4-0 DEVICEID<13:0> Values DEV<8:0> REV<4:0> PIC16F1508 10 1101 001 x xxxx PIC16LF1508 10 1101 111 x xxxx PIC16F1509 10 1101 010 x xxxx PIC16LF1509 10 1101 000 x xxxx REV<4:0>: Revision ID bits These bits are used to identify the revision (see Table under DEV<8:0> above). 2011 Microchip Technology Inc. Preliminary DS41609A-page 47 PIC16(L)F1508/9 NOTES: DS41609A-page 48 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 5.0 OSCILLATOR MODULE (WITH FAIL-SAFE CLOCK MONITOR) 5.1 Overview The oscillator module has a wide variety of clock sources and selection features that allow it to be used in a wide range of applications while maximizing performance and minimizing power consumption. Figure 5-1 illustrates a block diagram of the oscillator module. Clock sources can be supplied from external oscillators, quartz crystal resonators, ceramic resonators and Resistor-Capacitor (RC) circuits. In addition, the system clock source can be supplied from one of two internal oscillators, with a choice of speeds selectable via software. Additional clock features include: * Selectable system clock source between external or internal sources via software. * Two-Speed Start-up mode, which minimizes latency between external oscillator start-up and code execution. * Fail-Safe Clock Monitor (FSCM) designed to detect a failure of the external clock source (LP, XT, HS, EC or RC modes) and switch automatically to the internal oscillator. * Oscillator Start-up Timer (OST) ensures stability of crystal oscillator sources * Fast start-up oscillator allows internal circuits to power-up and stabilize before switching to the 16 MHz HFINTOSC 2011 Microchip Technology Inc. The oscillator module can be configured in one of eight clock modes. 1. 2. 3. 4. 5. 6. 7. 8. ECL - External Clock Low-Power mode (0 MHz to 0.5 MHz) ECM - External Clock Medium-Power mode (0.5 MHz to 4 MHz) ECH - External Clock High-Power mode (4 MHz to 20 MHz) LP - 32 kHz Low-Power Crystal mode. XT - Medium Gain Crystal or Ceramic Resonator Oscillator mode (up to 4 MHz) HS - High Gain Crystal or Ceramic Resonator mode (4 MHz to 20 MHz) RC - External Resistor-Capacitor (RC) INTOSC - Internal oscillator (31 kHz to 16 MHz) Clock Source modes are selected by the FOSC<2:0> bits in the Configuration Words. The FOSC bits determine the type of oscillator that will be used when the device is first powered. The EC clock mode relies on an external logic level signal as the device clock source. The LP, XT, and HS clock modes require an external crystal or resonator to be connected to the device. Each mode is optimized for a different frequency range. The RC clock mode requires an external resistor and capacitor to set the oscillator frequency. The INTOSC internal oscillator block produces a low and high-frequency clock source, designated LFINTOSC and HFINTOSC. (See Internal Oscillator Block, Figure 5-1). A wide selection of device clock frequencies may be derived from these two clock sources. Preliminary DS41609A-page 49 PIC16(L)F1508/9 FIGURE 5-1: SIMPLIFIED PIC(R) MCU CLOCK SOURCE BLOCK DIAGRAM CLKIN/ OSC1/ SOSCI/ T1CKI Primary Clock Primary Oscillator (OSC) Sleep Secondary Clock Secondary Oscillator (SOSC) IRCF<3:0> CPU and MUX CLKOUT / OSC2 SOSCO/ T1G Peripherals INTOSC 16 MHz Primary OSC Start-Up OSC 31 kHz Source DS41609A-page 50 Postscaler Start-up Control Logic MUX 4 16 MHz 8 MHz 4 MHz 2 MHz 1 MHz 500 kHz 250 kHz 125 kHz 62.5 kHz 31.25 kHz 31 kHz Clock Control 3 FOSC<2:0> 2 SCS<1:0> WDT, PWRT and other Modules Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 5.2 Clock Source Types Clock sources can be classified as external or internal. External clock sources rely on external circuitry for the clock source to function. Examples are: oscillator modules (EC mode), quartz crystal resonators or ceramic resonators (LP, XT and HS modes) and Resistor-Capacitor (RC) mode circuits. Internal clock sources are contained within the oscillator module. The internal oscillator block has two internal oscillators that are used to generate the internal system clock sources: the 16 MHz High-Frequency Internal Oscillator and the 31 kHz Low-Frequency Internal Oscillator (LFINTOSC). The Oscillator Start-up Timer (OST) is disabled when EC mode is selected. Therefore, there is no delay in operation after a Power-on Reset (POR) or wake-up from Sleep. Because the PIC(R) MCU design is fully static, stopping the external clock input will have the effect of halting the device while leaving all data intact. Upon restarting the external clock, the device will resume operation as if no time had elapsed. FIGURE 5-2: 5.2.1 An external clock source can be used as the device system clock by performing one of the following actions: * Program the FOSC<2:0> bits in the Configuration Words to select an external clock source that will be used as the default system clock upon a device Reset. * Write the SCS<1:0> bits in the OSCCON register to switch the system clock source to: - Secondary oscillator during run-time, or - An external clock source determined by the value of the FOSC bits. See Section 5.3 "Clock Switching"for more information. 5.2.1.1 EC Mode The External Clock (EC) mode allows an externally generated logic level signal to be the system clock source. When operating in this mode, an external clock source is connected to the OSC1 input. OSC2/CLKOUT is available for general purpose I/O or CLKOUT. Figure 5-2 shows the pin connections for EC mode. EC mode has 3 power modes to select from through Configuration Words: PIC(R) MCU FOSC/4 or I/O(1) Note 1: EXTERNAL CLOCK SOURCES OSC1/CLKIN Clock from Ext. System The system clock can be selected between external or internal clock sources via the System Clock Select (SCS) bits in the OSCCON register. See Section 5.3 "Clock Switching" for additional information. 5.2.1.2 EXTERNAL CLOCK (EC) MODE OPERATION OSC2/CLKOUT Output depends upon CLKOUTEN bit of the Configuration Words. LP, XT, HS Modes The LP, XT and HS modes support the use of quartz crystal resonators or ceramic resonators connected to OSC1 and OSC2 (Figure 5-3). The three modes select a low, medium or high gain setting of the internal inverter-amplifier to support various resonator types and speed. LP Oscillator mode selects the lowest gain setting of the internal inverter-amplifier. LP mode current consumption is the least of the three modes. This mode is designed to drive only 32.768 kHz tuning-fork type crystals (watch crystals). XT Oscillator mode selects the intermediate gain setting of the internal inverter-amplifier. XT mode current consumption is the medium of the three modes. This mode is best suited to drive resonators with a medium drive level specification. HS Oscillator mode selects the highest gain setting of the internal inverter-amplifier. HS mode current consumption is the highest of the three modes. This mode is best suited for resonators that require a high drive setting. Figure 5-3 and Figure 5-4 show typical circuits for quartz crystal and ceramic resonators, respectively. * High power, 4-20 MHz (FOSC = 111) * Medium power, 0.5-4 MHz (FOSC = 110) * Low power, 0-0.5 MHz (FOSC = 101) 2011 Microchip Technology Inc. Preliminary DS41609A-page 51 PIC16(L)F1508/9 FIGURE 5-3: QUARTZ CRYSTAL OPERATION (LP, XT OR HS MODE) FIGURE 5-4: CERAMIC RESONATOR OPERATION (XT OR HS MODE) PIC(R) MCU PIC(R) MCU OSC1/CLKIN C1 C1 To Internal Logic Quartz Crystal C2 OSC1/CLKIN RS(1) RF(2) Sleep RP(3) OSC2/CLKOUT A series resistor (RS) may be required for quartz crystals with low drive level. 2: The value of RF varies with the Oscillator mode selected (typically between 2 M to 10 M. Note 1: Quartz crystal characteristics vary according to type, package and manufacturer. The user should consult the manufacturer data sheets for specifications and recommended application. 2: Always verify oscillator performance over the VDD and temperature range that is expected for the application. 3: For oscillator design assistance, reference the following Microchip Applications Notes: DS41609A-page 52 RF(2) C2 Ceramic RS(1) Resonator Note 1: * AN826, "Crystal Oscillator Basics and Crystal Selection for rfPIC(R) and PIC(R) Devices" (DS00826) * AN849, "Basic PIC(R) Oscillator Design" (DS00849) * AN943, "Practical PIC(R) Oscillator Analysis and Design" (DS00943) * AN949, "Making Your Oscillator Work" (DS00949) To Internal Logic Note 1: Sleep OSC2/CLKOUT A series resistor (RS) may be required for ceramic resonators with low drive level. 2: The value of RF varies with the Oscillator mode selected (typically between 2 M to 10 M. 3: An additional parallel feedback resistor (RP) may be required for proper ceramic resonator operation. 5.2.1.3 Oscillator Start-up Timer (OST) If the oscillator module is configured for LP, XT or HS modes, the Oscillator Start-up Timer (OST) counts 1024 oscillations from OSC1. This occurs following a Power-on Reset (POR) and when the Power-up Timer (PWRT) has expired (if configured), or a wake-up from Sleep. During this time, the program counter does not increment and program execution is suspended. The OST ensures that the oscillator circuit, using a quartz crystal resonator or ceramic resonator, has started and is providing a stable system clock to the oscillator module. In order to minimize latency between external oscillator start-up and code execution, the Two-Speed Clock Start-up mode can be selected (see Section 5.4 "Two-Speed Clock Start-up Mode"). Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 5.2.1.4 5.2.1.5 Secondary Oscillator External RC Mode The secondary oscillator is a separate crystal oscillator that is associated with the Timer1 peripheral. It is optimized for timekeeping operations with a 32.768 kHz crystal connected between the SOSCO and SOSCI device pins. The external Resistor-Capacitor (RC) modes support the use of an external RC circuit. This allows the designer maximum flexibility in frequency choice while keeping costs to a minimum when clock accuracy is not required. The secondary oscillator can be used as an alternate system clock source and can be selected during run-time using clock switching. Refer to Section 5.3 "Clock Switching" for more information. The RC circuit connects to OSC1. OSC2/CLKOUT is available for general purpose I/O or CLKOUT. The function of the OSC2/CLKOUT pin is determined by the CLKOUTEN bit in Configuration Words. FIGURE 5-5: Figure 5-6 shows the external RC mode connections. QUARTZ CRYSTAL OPERATION (SECONDARY OSCILLATOR) FIGURE 5-6: VDD OSC1/CLKIN SOSCI VSS FOSC/4 or I/O(1) SOSCO OSC2/CLKOUT Recommended values: 10 k REXT 100 k, <3V 3 k REXT 100 k, 3-5V CEXT > 20 pF, 2-5V Note 1: Quartz crystal characteristics vary according to type, package and manufacturer. The user should consult the manufacturer data sheets for specifications and recommended application. 2: Always verify oscillator performance over the VDD and temperature range that is expected for the application. 3: For oscillator design assistance, reference the following Microchip Applications Notes: * AN826, "Crystal Oscillator Basics and Crystal Selection for rfPIC(R) and PIC(R) Devices" (DS00826) * AN849, "Basic PIC(R) Oscillator Design" (DS00849) * AN943, "Practical PIC(R) Oscillator Analysis and Design" (DS00943) * AN949, "Making Your Oscillator Work" (DS00949) * TB097, "Interfacing a Micro Crystal MS1V-T1K 32.768 kHz Tuning Fork Crystal to a PIC16F690/SS" (DS91097) * AN1288, "Design Practices for Low-Power External Oscillators" (DS01288) 2011 Microchip Technology Inc. Internal Clock CEXT To Internal Logic 32.768 kHz Quartz Crystal C2 PIC(R) MCU REXT PIC(R) MCU C1 EXTERNAL RC MODES Note 1: Output depends upon CLKOUTEN bit of the Configuration Words. The RC oscillator frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values and the operating temperature. Other factors affecting the oscillator frequency are: * threshold voltage variation * component tolerances * packaging variations in capacitance The user also needs to take into account variation due to tolerance of external RC components used. Preliminary DS41609A-page 53 PIC16(L)F1508/9 5.2.2 INTERNAL CLOCK SOURCES 5.2.2.2 The device may be configured to use the internal oscillator block as the system clock by performing one of the following actions: * Program the FOSC<2:0> bits in Configuration Words to select the INTOSC clock source, which will be used as the default system clock upon a device Reset. * Write the SCS<1:0> bits in the OSCCON register to switch the system clock source to the internal oscillator during run-time. See Section 5.3 "Clock Switching"for more information. In INTOSC mode, OSC1/CLKIN is available for general purpose I/O. OSC2/CLKOUT is available for general purpose I/O or CLKOUT. The function of the OSC2/CLKOUT pin is determined by the CLKOUTEN bit in Configuration Words. The internal oscillator block has two independent oscillators that provides the internal system clock source. 1. 2. The HFINTOSC (High-Frequency Internal Oscillator) is factory calibrated and operates at 16 MHz. The LFINTOSC (Low-Frequency Internal Oscillator) is uncalibrated and operates at 31 kHz. 5.2.2.1 HFINTOSC The High-Frequency Internal Oscillator (HFINTOSC) is a factory calibrated 16 MHz internal clock source. LFINTOSC The Low-Frequency Internal Oscillator (LFINTOSC) is an uncalibrated 31 kHz internal clock source. The output of the LFINTOSC connects to a postscaler and multiplexer (see Figure 5-1). Select 31 kHz, via software, using the IRCF<3:0> bits of the OSCCON register. See Section 5.2.2.4 "Internal Oscillator Clock Switch Timing" for more information. The LFINTOSC is also the frequency for the Power-up Timer (PWRT), Watchdog Timer (WDT) and Fail-Safe Clock Monitor (FSCM). The LFINTOSC is enabled by selecting 31 kHz (IRCF<3:0> bits of the OSCCON register = 000) as the system clock source (SCS bits of the OSCCON register = 1x), or when any of the following are enabled: * Configure the IRCF<3:0> bits of the OSCCON register for the desired LF frequency, and * FOSC<2:0> = 100, or * Set the System Clock Source (SCS) bits of the OSCCON register to `1x' Peripherals that use the LFINTOSC are: * Power-up Timer (PWRT) * Watchdog Timer (WDT) * Fail-Safe Clock Monitor (FSCM) The Low-Frequency Internal Oscillator Ready bit (LFIOFR) of the OSCSTAT register indicates when the LFINTOSC is running. The output of the HFINTOSC connects to a postscaler and multiplexer (see Figure 5-1). The frequency derived from the HFINTOSC can be selected via software using the IRCF<3:0> bits of the OSCCON register. See Section 5.2.2.4 "Internal Oscillator Clock Switch Timing" for more information. The HFINTOSC is enabled by: * Configure the IRCF<3:0> bits of the OSCCON register for the desired HF frequency, and * FOSC<2:0> = 100, or * Set the System Clock Source (SCS) bits of the OSCCON register to `1x'. A fast start-up oscillator allows internal circuits to power-up and stabilize before switching to HFINTOSC. The High-Frequency Internal Oscillator Ready bit (HFIOFR) of the OSCSTAT register indicates when the HFINTOSC is running. The High-Frequency Internal Oscillator Stable bit (HFIOFS) of the OSCSTAT register indicates when the HFINTOSC is running within 0.5% of its final value. DS41609A-page 54 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 5.2.2.3 Internal Oscillator Frequency Selection 5.2.2.4 The system clock speed can be selected via software using the Internal Oscillator Frequency Select bits IRCF<3:0> of the OSCCON register. The output of the 16 MHz HFINTOSC and 31 kHz LFINTOSC connects to a postscaler and multiplexer (see Figure 5-1). The Internal Oscillator Frequency Select bits IRCF<3:0> of the OSCCON register select the frequency output of the internal oscillators. One of the following frequencies can be selected via software: Note: 2. 3. 4. 5. 6. 7. IRCF<3:0> bits of the OSCCON register are modified. If the new clock is shut down, a clock start-up delay is started. Clock switch circuitry waits for a falling edge of the current clock. The current clock is held low and the clock switch circuitry waits for a rising edge in the new clock. The new clock is now active. The OSCSTAT register is updated as required. Clock switch is complete. See Figure 5-7 for more details. Following any Reset, the IRCF<3:0> bits of the OSCCON register are set to `0111' and the frequency selection is set to 500 kHz. The user can modify the IRCF bits to select a different frequency. The IRCF<3:0> bits of the OSCCON register allow duplicate selections for some frequencies. These duplicate choices can offer system design trade-offs. Lower power consumption can be obtained when changing oscillator sources for a given frequency. Faster transition times can be obtained between frequency changes that use the same oscillator source. 2011 Microchip Technology Inc. When switching between the HFINTOSC and the LFINTOSC, the new oscillator may already be shut down to save power (see Figure 5-7). If this is the case, there is a delay after the IRCF<3:0> bits of the OSCCON register are modified before the frequency selection takes place. The OSCSTAT register will reflect the current active status of the HFINTOSC and LFINTOSC oscillators. The sequence of a frequency selection is as follows: 1. * HFINTOSC - 16 MHz - 8 MHz - 4 MHz - 2 MHz - 1 MHz - 500 kHz (default after Reset) - 250 kHz - 125 kHz - 62.5 kHz - 31.25 kHz * LFINTOSC - 31 kHz Internal Oscillator Clock Switch Timing If the internal oscillator speed is switched between two clocks of the same source, there is no start-up delay before the new frequency is selected. Clock switching time delays are shown in Table 5-1. Start-up delay specifications are located in the oscillator tables of Section 29.0 "Electrical Specifications". Preliminary DS41609A-page 55 PIC16(L)F1508/9 FIGURE 5-7: HFINTOSC INTERNAL OSCILLATOR SWITCH TIMING LFINTOSC (FSCM and WDT disabled) HFINTOSC Start-up Time 2-cycle Sync Running LFINTOSC IRCF <3:0> 0 0 System Clock HFINTOSC LFINTOSC (Either FSCM or WDT enabled) HFINTOSC 2-cycle Sync Running LFINTOSC 0 IRCF <3:0> 0 System Clock LFINTOSC HFINTOSC LFINTOSC turns off unless WDT or FSCM is enabled LFINTOSC Start-up Time 2-cycle Sync Running HFINTOSC IRCF <3:0> =0 0 System Clock DS41609A-page 56 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 5.3 Clock Switching 5.3.3 SECONDARY OSCILLATOR The system clock source can be switched between external and internal clock sources via software using the System Clock Select (SCS) bits of the OSCCON register. The following clock sources can be selected using the SCS bits: The secondary oscillator is a separate crystal oscillator associated with the Timer1 peripheral. It is optimized for timekeeping operations with a 32.768 kHz crystal connected between the SOSCO and SOSCI device pins. * Default system oscillator determined by FOSC bits in Configuration Words * Secondary oscillator 32 kHz crystal * Internal Oscillator Block (INTOSC) The secondary oscillator is enabled using the T1OSCEN control bit in the T1CON register. See Section 19.0 "Timer1 Module with Gate Control" for more information about the Timer1 peripheral. 5.3.1 5.3.4 SYSTEM CLOCK SELECT (SCS) BITS The System Clock Select (SCS) bits of the OSCCON register selects the system clock source that is used for the CPU and peripherals. * When the SCS bits of the OSCCON register = 00, the system clock source is determined by value of the FOSC<2:0> bits in the Configuration Words. * When the SCS bits of the OSCCON register = 01, the system clock source is the secondary oscillator. * When the SCS bits of the OSCCON register = 1x, the system clock source is chosen by the internal oscillator frequency selected by the IRCF<3:0> bits of the OSCCON register. After a Reset, the SCS bits of the OSCCON register are always cleared. Note: SECONDARY OSCILLATOR READY (SOSCR) BIT The user must ensure that the secondary oscillator is ready to be used before it is selected as a system clock source. The Secondary Oscillator Ready (SOSCR) bit of the OSCSTAT register indicates whether the secondary oscillator is ready to be used. After the SOSCR bit is set, the SCS bits can be configured to select the secondary oscillator. Any automatic clock switch, which may occur from Two-Speed Start-up or Fail-Safe Clock Monitor, does not update the SCS bits of the OSCCON register. The user can monitor the OSTS bit of the OSCSTAT register to determine the current system clock source. When switching between clock sources, a delay is required to allow the new clock to stabilize. These oscillator delays are shown in Table 5-1. 5.3.2 OSCILLATOR START-UP TIME-OUT STATUS (OSTS) BIT The Oscillator Start-up Time-out Status (OSTS) bit of the OSCSTAT register indicates whether the system clock is running from the external clock source, as defined by the FOSC<2:0> bits in the Configuration Words, or from the internal clock source. In particular, OSTS indicates that the Oscillator Start-up Timer (OST) has timed out for LP, XT or HS modes. The OST does not reflect the status of the secondary oscillator. 2011 Microchip Technology Inc. Preliminary DS41609A-page 57 PIC16(L)F1508/9 5.4 Two-Speed Clock Start-up Mode 5.4.1 Two-Speed Start-up mode provides additional power savings by minimizing the latency between external oscillator start-up and code execution. In applications that make heavy use of the Sleep mode, Two-Speed Start-up will remove the external oscillator start-up time from the time spent awake and can reduce the overall power consumption of the device. This mode allows the application to wake-up from Sleep, perform a few instructions using the INTOSC internal oscillator block as the clock source and go back to Sleep without waiting for the external oscillator to become stable. Two-Speed Start-up provides benefits when the oscillator module is configured for LP, XT, or HS modes. The Oscillator Start-up Timer (OST) is enabled for these modes and must count 1024 oscillations before the oscillator can be used as the system clock source. TWO-SPEED START-UP MODE CONFIGURATION Two-Speed Start-up mode is configured by the following settings: * IESO (of the Configuration Words) = 1; Internal/External Switchover bit (Two-Speed Start-up mode enabled). * SCS (of the OSCCON register) = 00. * FOSC<2:0> bits in the Configuration Words configured for LP, XT or HS mode. Two-Speed Start-up mode is entered after: * Power-on Reset (POR) and, if enabled, after Power-up Timer (PWRT) has expired, or * Wake-up from Sleep. If the oscillator module is configured for any mode other than LP, XT or HS mode, then Two-Speed Start-up is disabled. This is because the external clock oscillator does not require any stabilization time after POR or an exit from Sleep. If the OST count reaches 1024 before the device enters Sleep mode, the OSTS bit of the OSCSTAT register is set and program execution switches to the external oscillator. However, the system may never operate from the external oscillator if the time spent awake is very short. Note: Executing a SLEEP instruction will abort the oscillator start-up time and will cause the OSTS bit of the OSCSTAT register to remain clear. TABLE 5-1: OSCILLATOR SWITCHING DELAYS Switch From Switch To Frequency Oscillator Delay Sleep/POR LFINTOSC HFINTOSC 31 kHz 31.25 kHz-16 MHz Oscillator Warm-up Delay (TWARM) Sleep/POR EC, RC DC - 20 MHz 2 cycles LFINTOSC EC, RC DC - 20 MHz 1 cycle of each Sleep/POR Secondary Oscillator, 32 kHz-20 MHz LP, XT, HS 1024 Clock Cycles (OST) Any clock source HFINTOSC 31.25 kHz-16 MHz 2 s (approx.) Any clock source LFINTOSC 31 kHz 1 cycle of each Any clock source Secondary Oscillator 32 kHz DS41609A-page 58 Preliminary 1024 Clock Cycles (OST) 2011 Microchip Technology Inc. PIC16(L)F1508/9 5.4.2 1. 2. 3. 4. 5. 6. 7. TWO-SPEED START-UP SEQUENCE 5.4.3 Wake-up from Power-on Reset or Sleep. Instructions begin execution by the internal oscillator at the frequency set in the IRCF<3:0> bits of the OSCCON register. OST enabled to count 1024 clock cycles. OST timed out, wait for falling edge of the internal oscillator. OSTS is set. System clock held low until the next falling edge of new clock (LP, XT or HS mode). System clock is switched to external clock source. FIGURE 5-8: CHECKING TWO-SPEED CLOCK STATUS Checking the state of the OSTS bit of the OSCSTAT register will confirm if the microcontroller is running from the external clock source, as defined by the FOSC<2:0> bits in the Configuration Words, or the internal oscillator. TWO-SPEED START-UP INTOSC TOST OSC1 0 1 1022 1023 OSC2 Program Counter PC - N PC + 1 PC System Clock 2011 Microchip Technology Inc. Preliminary DS41609A-page 59 PIC16(L)F1508/9 5.5 Fail-Safe Clock Monitor 5.5.3 The Fail-Safe Clock Monitor (FSCM) allows the device to continue operating should the external oscillator fail. The FSCM can detect oscillator failure any time after the Oscillator Start-up Timer (OST) has expired. The FSCM is enabled by setting the FCMEN bit in the Configuration Words. The FSCM is applicable to all external Oscillator modes (LP, XT, HS, EC, RC and secondary oscillator). FIGURE 5-9: FSCM BLOCK DIAGRAM External Clock LFINTOSC Oscillator / 64 31 kHz (~32 s) 488 Hz (~2 ms) S Q R Q Sample Clock 5.5.1 The Fail-Safe condition is cleared after a Reset, executing a SLEEP instruction or changing the SCS bits of the OSCCON register. When the SCS bits are changed, the OST is restarted. While the OST is running, the device continues to operate from the INTOSC selected in OSCCON. When the OST times out, the Fail-Safe condition is cleared and the device will be operating from the external clock source. The Fail-Safe condition must be cleared before the OSFIF flag can be cleared. 5.5.4 Clock Monitor Latch RESET OR WAKE-UP FROM SLEEP The FSCM is designed to detect an oscillator failure after the Oscillator Start-up Timer (OST) has expired. The OST is used after waking up from Sleep and after any type of Reset. The OST is not used with the EC or RC Clock modes so that the FSCM will be active as soon as the Reset or wake-up has completed. When the FSCM is enabled, the Two-Speed Start-up is also enabled. Therefore, the device will always be executing code while the OST is operating. Clock Failure Detected Note: FAIL-SAFE DETECTION The FSCM module detects a failed oscillator by comparing the external oscillator to the FSCM sample clock. The sample clock is generated by dividing the LFINTOSC by 64. See Figure 5-9. Inside the fail detector block is a latch. The external clock sets the latch on each falling edge of the external clock. The sample clock clears the latch on each rising edge of the sample clock. A failure is detected when an entire half-cycle of the sample clock elapses before the external clock goes low. 5.5.2 FAIL-SAFE CONDITION CLEARING Due to the wide range of oscillator start-up times, the Fail-Safe circuit is not active during oscillator start-up (i.e., after exiting Reset or Sleep). After an appropriate amount of time, the user should check the Status bits in the OSCSTAT register to verify the oscillator start-up and that the system clock switchover has successfully completed. FAIL-SAFE OPERATION When the external clock fails, the FSCM switches the device clock to an internal clock source and sets the bit flag OSFIF of the PIR2 register. Setting this flag will generate an interrupt if the OSFIE bit of the PIE2 register is also set. The device firmware can then take steps to mitigate the problems that may arise from a failed clock. The system clock will continue to be sourced from the internal clock source until the device firmware successfully restarts the external oscillator and switches back to external operation. The internal clock source chosen by the FSCM is determined by the IRCF<3:0> bits of the OSCCON register. This allows the internal oscillator to be configured before a failure occurs. DS41609A-page 60 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 FIGURE 5-10: FSCM TIMING DIAGRAM Sample Clock Oscillator Failure System Clock Output Clock Monitor Output (Q) Failure Detected OSCFIF Test Note: Test Test The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. 2011 Microchip Technology Inc. Preliminary DS41609A-page 61 PIC16(L)F1508/9 5.6 Oscillator Control Registers REGISTER 5-1: U-0 OSCCON: OSCILLATOR CONTROL REGISTER R/W-0/0 R/W-1/1 R/W-1/1 R/W-1/1 IRCF<3:0> -- U-0 R/W-0/0 R/W-0/0 SCS<1:0> -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 Unimplemented: Read as `0' bit 6-3 IRCF<3:0>: Internal Oscillator Frequency Select bits 1111 = 16 MHz 1110 = 8 MHz 1101 = 4 MHz 1100 = 2 MHz 1011 = 1 MHz 1010 = 500 kHz(1) 1001 = 250 kHz(1) 1000 = 125 kHz(1) 0111 = 500 kHz (default upon Reset) 0110 = 250 kHz 0101 = 125 kHz 0100 = 62.5 kHz 001x = 31.25 kHz 000x = 31 kHz LF bit 2 Unimplemented: Read as `0' bit 1-0 SCS<1:0>: System Clock Select bits 1x = Internal oscillator block 01 = Secondary oscillator 00 = Clock determined by FOSC<2:0> in Configuration Words. Note 1: Duplicate frequency derived from HFINTOSC. DS41609A-page 62 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 REGISTER 5-2: OSCSTAT: OSCILLATOR STATUS REGISTER R-1/q U-0 R-q/q R-0/q U-0 U-0 R-0/q R-0/q SOSCR -- OSTS HFIOFR -- -- LFIOFR HFIOFS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Conditional bit 7 SOSCR: Secondary Oscillator Ready bit If T1OSCEN = 1: 1 = Secondary oscillator is ready 0 = Secondary oscillator is not ready If T1OSCEN = 0: 1 = Timer1 clock source is always ready bit 6 Unimplemented: Read as `0' bit 5 OSTS: Oscillator Start-up Time-out Status bit 1 = Running from the clock defined by the FOSC<2:0> bits of the Configuration Words 0 = Running from an internal oscillator (FOSC<2:0> = 100) bit 4 HFIOFR: High-Frequency Internal Oscillator Ready bit 1 = HFINTOSC is ready 0 = HFINTOSC is not ready bit 3-2 Unimplemented: Read as `0' bit 1 LFIOFR: Low-Frequency Internal Oscillator Ready bit 1 = LFINTOSC is ready 0 = LFINTOSC is not ready bit 0 HFIOFS: High-Frequency Internal Oscillator Stable bit 1 = HFINTOSC 16 MHz Oscillator is stable and is driving the INTOSC 0 = HFINTOSC 16 MHz is not stable, the Start-up Oscillator is driving INTOSC TABLE 5-2: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page OSCCON -- OSCSTAT SOSCR -- OSTS HFIOFR -- -- LFIOFR HFIOFS 63 PIE2 OSFIE C2IE C1IE -- BCL1IE NCO1IE -- -- 80 PIR2 OSFIF C2IF C1IF -- BCL1IF NCO1IF -- -- 83 T1OSCEN T1SYNC -- TMR1ON 175 TMR1CS<1:0> T1CON Legend: CONFIG1 Legend: -- T1CKPS<1:0> SCS<1:0> 62 -- = unimplemented location, read as `0'. Shaded cells are not used by clock sources. TABLE 5-3: Name IRCF<3:0> Bits SUMMARY OF CONFIGURATION WORD WITH CLOCK SOURCES Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 IESO CLKOUTEN 13:8 -- -- FCMEN 7:0 CP MCLRE PWRTE Bit 10/2 Bit 9/1 BOREN<1:0> WDTE<1:0> FOSC<2:0> Bit 8/0 -- Register on Page 44 -- = unimplemented location, read as `0'. Shaded cells are not used by clock sources. 2011 Microchip Technology Inc. Preliminary DS41609A-page 63 PIC16(L)F1508/9 NOTES: DS41609A-page 64 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 6.0 RESETS There are multiple ways to reset this device: * * * * * * * * * Power-on Reset (POR) Brown-out Reset (BOR) Low-Power Brown-out Reset (LPBOR) MCLR Reset WDT Reset RESET instruction Stack Overflow Stack Underflow Programming mode exit To allow VDD to stabilize, an optional Power-up Timer can be enabled to extend the Reset time after a BOR or POR event. A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 6-1. FIGURE 6-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT ICSPTM Programming Mode Exit RESET Instruction Stack Pointer MCLRE MCLR Sleep WDT Time-out Device Reset Power-on Reset VDD Brown-out Reset R PWRT Done LPBOR Reset PWRTE LFINTOSC BOR Active(1) Note 1: See Table 6-1 for BOR active conditions. 2011 Microchip Technology Inc. Preliminary DS41609A-page 65 PIC16(L)F1508/9 6.1 Power-on Reset (POR) 6.2 Brown-Out Reset (BOR) The POR circuit holds the device in Reset until VDD has reached an acceptable level for minimum operation. Slow rising VDD, fast operating speeds or analog performance may require greater than minimum VDD. The PWRT, BOR or MCLR features can be used to extend the start-up period until all device operation conditions have been met. The BOR circuit holds the device in Reset when VDD reaches a selectable minimum level. Between the POR and BOR, complete voltage range coverage for execution protection can be implemented. 6.1.1 * * * * POWER-UP TIMER (PWRT) The Power-up Timer provides a nominal 64 ms timeout on POR or Brown-out Reset. The device is held in Reset as long as PWRT is active. The PWRT delay allows additional time for the VDD to rise to an acceptable level. The Power-up Timer is enabled by clearing the PWRTE bit in Configuration Words. The Power-up Timer starts after the release of the POR and BOR. For additional information, refer to Application Note AN607, "Power-up Trouble Shooting" (DS00607). TABLE 6-1: The Brown-out Reset module has four operating modes controlled by the BOREN<1:0> bits in Configuration Words. The four operating modes are: BOR is always on BOR is off when in Sleep BOR is controlled by software BOR is always off Refer to Table 6-1 for more information. The Brown-out Reset voltage level is selectable by configuring the BORV bit in Configuration Words. A VDD noise rejection filter prevents the BOR from triggering on small events. If VDD falls below VBOR for a duration greater than parameter TBORDC, the device will reset. See Figure 6-2 for more information. BOR OPERATING MODES Instruction Execution upon: Release of POR or Wake-up from Sleep BOREN<1:0> SBOREN Device Mode BOR Mode 11 X X Active Waits for BOR ready(1) (BORRDY = 1) 10 X Awake Active Sleep Disabled Waits for BOR ready (BORRDY = 1) 1 01 00 X Active Waits for BOR ready(1) (BORRDY = 1) Begins immediately (BORRDY = x) 0 X Disabled X X Disabled Note 1: In these specific cases, "release of POR" and "wake-up from Sleep," there is no delay in start-up. The BOR ready flag, (BORRDY = 1), will be set before the CPU is ready to execute instructions because the BOR circuit is forced on by the BOREN<1:0> bits. 6.2.1 BOR IS ALWAYS ON When the BOREN bits of Configuration Words are programmed to `11', the BOR is always on. The device start-up will be delayed until the BOR is ready and VDD is higher than the BOR threshold. BOR protection is active during Sleep. The BOR does not delay wake-up from Sleep. 6.2.2 BOR IS OFF IN SLEEP When the BOREN bits of Configuration Words are programmed to `10', the BOR is on, except in Sleep. The device start-up will be delayed until the BOR is ready and VDD is higher than the BOR threshold. DS41609A-page 66 BOR protection is not active during Sleep. The device wake-up will be delayed until the BOR is ready. 6.2.3 BOR CONTROLLED BY SOFTWARE When the BOREN bits of Configuration Words are programmed to `01', the BOR is controlled by the SBOREN bit of the BORCON register. The device start-up is not delayed by the BOR ready condition or the VDD level. BOR protection begins as soon as the BOR circuit is ready. The status of the BOR circuit is reflected in the BORRDY bit of the BORCON register. BOR protection is unchanged by Sleep. Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 FIGURE 6-2: BROWN-OUT SITUATIONS VDD VBOR Internal Reset TPWRT(1) VDD VBOR Internal Reset < TPWRT TPWRT(1) VDD VBOR Internal Reset Note 1: TPWRT(1) TPWRT delay only if PWRTE bit is programmed to `0'. REGISTER 6-1: BORCON: BROWN-OUT RESET CONTROL REGISTER R/W-1/u R/W-0/u U-0 U-0 U-0 U-0 U-0 R-q/u SBOREN BORFS -- -- -- -- -- BORRDY bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7 SBOREN: Software Brown-out Reset Enable bit If BOREN <1:0> in Configuration Words 01: SBOREN is read/write, but has no effect on the BOR. If BOREN <1:0> in Configuration Words = 01: 1 = BOR Enabled 0 = BOR Disabled bit 6 BORFS: Brown-out Reset Fast Start bit(1) If BOREN<1:0> = 11 (Always on) or BOREN<1:0> = 00 (Always off) BORFS is Read/Write, but has no effect. If BOREN <1:0> = 10 (Disabled in Sleep) or BOREN<1:0> = 01 (Under software control): 1 = Band gap is forced on always (covers sleep/wake-up/operating cases) 0 = Band gap operates normally, and may turn off bit 5-1 Unimplemented: Read as `0' bit 0 BORRDY: Brown-out Reset Circuit Ready Status bit 1 = The Brown-out Reset circuit is active 0 = The Brown-out Reset circuit is inactive Note 1: BOREN<1:0> bits are located in Configuration Words. 2011 Microchip Technology Inc. Preliminary DS41609A-page 67 PIC16(L)F1508/9 6.3 Low-Power Brown-out Reset (LPBOR) 6.5 The Low-Power Brown-Out Reset (LPBOR) is an essential part of the Reset subsystem. Refer to Figure 6-1 to see how the BOR interacts with other modules. The LPBOR is used to monitor the external VDD pin. When too low of a voltage is detected, the device is held in Reset. When this occurs, a register bit (BOR) is changed to indicate that a BOR Reset has occurred. The same bit is set for both the BOR and the LPBOR. Refer to Register 6-2. 6.3.1 ENABLING LPBOR The LPBOR is controlled by the LPBOR bit of Configuration Words. When the device is erased, the LPBOR module defaults to disabled. 6.3.1.1 LPBOR Module Output The output of the LPBOR module is a signal indicating whether or not a Reset is to be asserted. This signal is OR'd together with the Reset signal of the BOR module to provide the generic BOR signal which goes to the PCON register and to the power control block. 6.4 MCLR Watchdog Timer (WDT) Reset The Watchdog Timer generates a Reset if the firmware does not issue a CLRWDT instruction within the time-out period. The TO and PD bits in the STATUS register are changed to indicate the WDT Reset. See Section 9.0 "Watchdog Timer" for more information. 6.6 RESET Instruction A RESET instruction will cause a device Reset. The RI bit in the PCON register will be set to `0'. See Table 6-4 for default conditions after a RESET instruction has occurred. 6.7 Stack Overflow/Underflow Reset The device can reset when the Stack Overflows or Underflows. The STKOVF or STKUNF bits of the PCON register indicate the Reset condition. These Resets are enabled by setting the STVREN bit in Configuration Words. See Section 3.4.2 "Overflow/Underflow Reset" for more information. 6.8 Programming Mode Exit Upon exit of Programming mode, the device will behave as if a POR had just occurred. The MCLR is an optional external input that can reset the device. The MCLR function is controlled by the MCLRE bit of Configuration Words and the LVP bit of Configuration Words (Table 6-2). 6.9 TABLE 6-2: The Power-up Timer is controlled by the PWRTE bit of Configuration Words. MCLR CONFIGURATION MCLRE LVP MCLR 0 0 Disabled 1 0 Enabled x 1 Enabled 6.4.1 MCLR ENABLED A Reset does not drive the MCLR pin low. MCLR DISABLED When MCLR is disabled, the pin functions as a general purpose input and the internal weak pull-up is under software control. See Section 11.2 "PORTA Registers" for more information. DS41609A-page 68 Start-up Sequence Upon the release of a POR or BOR, the following must occur before the device will begin executing: The device has a noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. 6.4.2 The Power-up Timer optionally delays device execution after a BOR or POR event. This timer is typically used to allow VDD to stabilize before allowing the device to start running. 6.10 When MCLR is enabled and the pin is held low, the device is held in Reset. The MCLR pin is connected to VDD through an internal weak pull-up. Note: Power-Up Timer 1. 2. Power-up Timer runs to completion (if enabled). MCLR must be released (if enabled). The total time-out will vary based on oscillator configuration and Power-up Timer configuration. See Section 5.0 "Oscillator Module (With Fail-Safe Clock Monitor)" for more information. The Power-up Timer runs independently of MCLR Reset. If MCLR is kept low long enough, the Power-up Timer will expire. Upon bringing MCLR high, the device will begin execution immediately (see Figure 6-3). This is useful for testing purposes or to synchronize more than one device operating in parallel. Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 FIGURE 6-3: RESET START-UP SEQUENCE VDD Internal POR TPWRT Power-Up Timer MCLR TMCLR Internal RESET Internal Oscillator Oscillator FOSC External Clock (EC) CLKIN FOSC 2011 Microchip Technology Inc. Preliminary DS41609A-page 69 PIC16(L)F1508/9 6.11 Determining the Cause of a Reset Upon any Reset, multiple bits in the STATUS and PCON registers are updated to indicate the cause of the Reset. Table 6-3 and Table 6-4 show the Reset conditions of these registers. TABLE 6-3: RESET STATUS BITS AND THEIR SIGNIFICANCE STKOVF STKUNF RWDT RMCLR RI POR BOR TO PD Condition 0 0 1 1 1 0 x 1 1 Power-on Reset 0 0 1 1 1 0 x 0 x Illegal, TO is set on POR 0 0 1 1 1 0 x x 0 Illegal, PD is set on POR 0 0 u 1 1 u 0 1 1 Brown-out Reset u u 0 u u u u 0 u WDT Reset u u u u u u u 0 0 WDT Wake-up from Sleep u u u u u u u 1 0 Interrupt Wake-up from Sleep u u u 0 u u u u u MCLR Reset during normal operation u u u 0 u u u 1 0 MCLR Reset during Sleep u u u u 0 u u u u RESET Instruction Executed 1 u u u u u u u u Stack Overflow Reset (STVREN = 1) u 1 u u u u u u u Stack Underflow Reset (STVREN = 1) TABLE 6-4: RESET CONDITION FOR SPECIAL REGISTERS(2) Program Counter STATUS Register PCON Register Power-on Reset 0000h ---1 1000 00-- 110x MCLR Reset during normal operation 0000h ---u uuuu uu-- 0uuu MCLR Reset during Sleep 0000h ---1 0uuu uu-- 0uuu WDT Reset 0000h ---0 uuuu uu-- uuuu WDT Wake-up from Sleep PC + 1 ---0 0uuu uu-- uuuu Brown-out Reset 0000h ---1 1uuu 00-- 11u0 ---1 0uuu uu-- uuuu ---u uuuu uu-- u0uu Condition Interrupt Wake-up from Sleep RESET Instruction Executed PC + 1 (1) 0000h Stack Overflow Reset (STVREN = 1) 0000h ---u uuuu 1u-- uuuu Stack Underflow Reset (STVREN = 1) 0000h ---u uuuu u1-- uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as `0'. Note 1: When the wake-up is due to an interrupt and Global Interrupt Enable bit (GIE) is set, the return address is pushed on the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1. 2: If a Status bit is not implemented, that bit will be read as `0'. DS41609A-page 70 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 6.12 Power Control (PCON) Register The Power Control (PCON) register contains flag bits to differentiate between a: * * * * * * * Power-on Reset (POR) Brown-out Reset (BOR) Reset Instruction Reset (RI) MCLR Reset (RMCLR) Watchdog Timer Reset (RWDT) Stack Underflow Reset (STKUNF) Stack Overflow Reset (STKOVF) The PCON register bits are shown in Register 6-2. REGISTER 6-2: PCON: POWER CONTROL REGISTER R/W/HS-0/q R/W/HS-0/q U-0 STKOVF STKUNF -- R/W/HC-1/q R/W/HC-1/q RWDT R/W/HC-1/q R/W/HC-q/u R/W/HC-q/u RI POR BOR RMCLR bit 7 bit 0 Legend: HC = Bit is cleared by hardware HS = Bit is set by hardware R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7 STKOVF: Stack Overflow Flag bit 1 = A Stack Overflow occurred 0 = A Stack Overflow has not occurred or cleared by firmware bit 6 STKUNF: Stack Underflow Flag bit 1 = A Stack Underflow occurred 0 = A Stack Underflow has not occurred or cleared by firmware bit 5 Unimplemented: Read as `0' bit 4 RWDT: Watchdog Timer Reset Flag bit 1 = A Watchdog Timer Reset has not occurred or set by firmware 0 = A Watchdog Timer Reset has occurred (cleared by hardware) bit 3 RMCLR: MCLR Reset Flag bit 1 = A MCLR Reset has not occurred or set by firmware 0 = A MCLR Reset has occurred (cleared by hardware) bit 2 RI: RESET Instruction Flag bit 1 = A RESET instruction has not been executed or set by firmware 0 = A RESET instruction has been executed (cleared by hardware) bit 1 POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset occurs) 2011 Microchip Technology Inc. Preliminary DS41609A-page 71 PIC16(L)F1508/9 TABLE 6-5: SUMMARY OF REGISTERS ASSOCIATED WITH RESETS Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page BORCON SBOREN BORFS -- -- -- -- -- BORRDY 67 PCON STKOVF STKUNF -- RWDT RMCLR RI POR BOR 71 STATUS -- -- -- TO PD Z DC C 21 WDTCON -- -- SWDTEN 93 WDTPS<4:0> Legend: -- = unimplemented bit, reads as `0'. Shaded cells are not used by Resets. Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. TABLE 6-6: Name CONFIG1 CONFIG2 Legend: Bits SUMMARY OF CONFIGURATION WORD WITH RESETS Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 -- CLKOUTEN Bit 10/2 13:8 -- -- -- 7:0 CP MCLRE PWRTE 13:8 -- -- LVP DEBUG LPBOR BORV 7:0 -- -- -- -- -- -- Bit 9/1 BOREN<1:0> WDTE<1:0> Bit 8/0 -- FOSC<2:0> STVREN -- WRT<1:0> Register on Page 44 45 -- = unimplemented location, read as `0'. Shaded cells are not used by Resets. DS41609A-page 72 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 7.0 INTERRUPTS The interrupt feature allows certain events to preempt normal program flow. Firmware is used to determine the source of the interrupt and act accordingly. Some interrupts can be configured to wake the MCU from Sleep mode. This chapter contains the following information for Interrupts: * * * * * Operation Interrupt Latency Interrupts During Sleep INT Pin Automatic Context Saving Many peripherals produce interrupts. Refer to the corresponding chapters for details. A block diagram of the interrupt logic is shown in Figure 7-1. FIGURE 7-1: INTERRUPT LOGIC TMR0IF TMR0IE Peripheral Interrupts (TMR1IF) PIR1<0> (TMR1IF) PIR1<0> Wake-up (If in Sleep mode) INTF INTE IOCIF IOCIE Interrupt to CPU PEIE PIRn<7> PIEn<7> 2011 Microchip Technology Inc. GIE Preliminary DS41609A-page 73 PIC16(L)F1508/9 7.1 Operation 7.2 Interrupts are disabled upon any device Reset. They are enabled by setting the following bits: * GIE bit of the INTCON register * Interrupt Enable bit(s) for the specific interrupt event(s) * PEIE bit of the INTCON register (if the Interrupt Enable bit of the interrupt event is contained in the PIE1, PIE2 and PIE3 registers) Interrupt Latency Interrupt latency is defined as the time from when the interrupt event occurs to the time code execution at the interrupt vector begins. The latency for synchronous interrupts is 3 or 4 instruction cycles. For asynchronous interrupts, the latency is 3 to 5 instruction cycles, depending on when the interrupt occurs. See Figure 7-2 and Figure 7.3 for more details. The INTCON, PIR1, PIR2 and PIR3 registers record individual interrupts via interrupt flag bits. Interrupt flag bits will be set, regardless of the status of the GIE, PEIE and individual interrupt enable bits. The following events happen when an interrupt event occurs while the GIE bit is set: * Current prefetched instruction is flushed * GIE bit is cleared * Current Program Counter (PC) is pushed onto the stack * Critical registers are automatically saved to the Shadow registers (See "Section 7.5 "Automatic Context Saving".") * PC is loaded with the interrupt vector 0004h The firmware within the Interrupt Service Routine (ISR) should determine the source of the interrupt by polling the interrupt flag bits. The interrupt flag bits must be cleared before exiting the ISR to avoid repeated interrupts. Because the GIE bit is cleared, any interrupt that occurs while executing the ISR will be recorded through its interrupt flag, but will not cause the processor to redirect to the interrupt vector. The RETFIE instruction exits the ISR by popping the previous address from the stack, restoring the saved context from the Shadow registers and setting the GIE bit. For additional information on a specific interrupt's operation, refer to its peripheral chapter. Note 1: Individual interrupt flag bits are set, regardless of the state of any other enable bits. 2: All interrupts will be ignored while the GIE bit is cleared. Any interrupt occurring while the GIE bit is clear will be serviced when the GIE bit is set again. DS41609A-page 74 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 FIGURE 7-2: INTERRUPT LATENCY Fosc Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CLKR Interrupt Sampled during Q1 Interrupt GIE PC Execute PC-1 PC 1 Cycle Instruction at PC PC+1 0004h 0005h Inst(PC) NOP NOP Inst(0004h) PC+1/FSR ADDR New PC/ PC+1 0004h 0005h Inst(PC) NOP NOP Inst(0004h) FSR ADDR PC+1 PC+2 0004h 0005h INST(PC) NOP NOP NOP Inst(0004h) Inst(0005h) FSR ADDR PC+1 0004h 0005h INST(PC) NOP NOP Inst(0004h) Interrupt GIE PC Execute PC-1 PC 2 Cycle Instruction at PC Interrupt GIE PC Execute PC-1 PC 3 Cycle Instruction at PC Interrupt GIE PC Execute PC-1 PC 3 Cycle Instruction at PC 2011 Microchip Technology Inc. Preliminary PC+2 NOP NOP DS41609A-page 75 PIC16(L)F1508/9 FIGURE 7-3: INT PIN INTERRUPT TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 FOSC CLKOUT (3) INT pin (1) (1) INTF Interrupt Latency (2) (4) GIE INSTRUCTION FLOW PC Instruction Fetched Instruction Executed Note 1: PC Inst (PC) Inst (PC - 1) PC + 1 Inst (PC + 1) Inst (PC) PC + 1 -- Forced NOP 0004h 0005h Inst (0004h) Inst (0005h) Forced NOP Inst (0004h) INTF flag is sampled here (every Q1). 2: Asynchronous interrupt latency = 3-5 TCY. Synchronous latency = 3-4 TCY, where TCY = instruction cycle time. Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction. 3: For minimum width of INT pulse, refer to AC specifications in Section 29.0 "Electrical Specifications". 4: INTF is enabled to be set any time during the Q4-Q1 cycles. DS41609A-page 76 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 7.3 Interrupts During Sleep Some interrupts can be used to wake from Sleep. To wake from Sleep, the peripheral must be able to operate without the system clock. The interrupt source must have the appropriate Interrupt Enable bit(s) set prior to entering Sleep. On waking from Sleep, if the GIE bit is also set, the processor will branch to the interrupt vector. Otherwise, the processor will continue executing instructions after the SLEEP instruction. The instruction directly after the SLEEP instruction will always be executed before branching to the ISR. Refer to Section 8.0 "PowerDown Mode (Sleep)" for more details. 7.4 INT Pin The INT pin can be used to generate an asynchronous edge-triggered interrupt. This interrupt is enabled by setting the INTE bit of the INTCON register. The INTEDG bit of the OPTION_REG register determines on which edge the interrupt will occur. When the INTEDG bit is set, the rising edge will cause the interrupt. When the INTEDG bit is clear, the falling edge will cause the interrupt. The INTF bit of the INTCON register will be set when a valid edge appears on the INT pin. If the GIE and INTE bits are also set, the processor will redirect program execution to the interrupt vector. 7.5 Automatic Context Saving Upon entering an interrupt, the return PC address is saved on the stack. Additionally, the following registers are automatically saved in the Shadow registers: * * * * * W register STATUS register (except for TO and PD) BSR register FSR registers PCLATH register Upon exiting the Interrupt Service Routine, these registers are automatically restored. Any modifications to these registers during the ISR will be lost. If modifications to any of these registers are desired, the corresponding Shadow register should be modified and the value will be restored when exiting the ISR. The Shadow registers are available in Bank 31 and are readable and writable. Depending on the user's application, other registers may also need to be saved. 2011 Microchip Technology Inc. Preliminary DS41609A-page 77 PIC16(L)F1508/9 7.6 Interrupt Control Registers 7.6.1 Note: INTCON REGISTER The INTCON register is a readable and writable register, that contains the various enable and flag bits for TMR0 register overflow, interrupt-on-change and external INT pin interrupts. REGISTER 7-1: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. INTCON: INTERRUPT CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-0/0 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 GIE: Global Interrupt Enable bit 1 = Enables all active interrupts 0 = Disables all interrupts bit 6 PEIE: Peripheral Interrupt Enable bit 1 = Enables all active peripheral interrupts 0 = Disables all peripheral interrupts bit 5 TMR0IE: Timer0 Overflow Interrupt Enable bit 1 = Enables the Timer0 interrupt 0 = Disables the Timer0 interrupt bit 4 INTE: INT External Interrupt Enable bit 1 = Enables the INT external interrupt 0 = Disables the INT external interrupt bit 3 IOCIE: Interrupt-on-Change Enable bit 1 = Enables the interrupt-on-change 0 = Disables the interrupt-on-change bit 2 TMR0IF: Timer0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed 0 = TMR0 register did not overflow bit 1 INTF: INT External Interrupt Flag bit 1 = The INT external interrupt occurred 0 = The INT external interrupt did not occur bit 0 IOCIF: Interrupt-on-Change Interrupt Flag bit(1) 1 = When at least one of the interrupt-on-change pins changed state 0 = None of the interrupt-on-change pins have changed state Note 1: The IOCIF Flag bit is read-only and cleared when all the interrupt-on-change flags in the IOCBF register have been cleared by software. DS41609A-page 78 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 7.6.2 PIE1 REGISTER The PIE1 register contains the interrupt enable bits, as shown in Register 7-2. REGISTER 7-2: Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 TMR1GIE ADIE RCIE TXIE SSP1IE -- TMR2IE TMR1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 TMR1GIE: Timer1 Gate Interrupt Enable bit 1 = Enables the Timer1 gate acquisition interrupt 0 = Disables the Timer1 gate acquisition interrupt bit 6 ADIE: A/D Converter (ADC) Interrupt Enable bit 1 = Enables the ADC interrupt 0 = Disables the ADC interrupt bit 5 RCIE: USART Receive Interrupt Enable bit 1 = Enables the USART receive interrupt 0 = Disables the USART receive interrupt bit 4 TXIE: USART Transmit Interrupt Enable bit 1 = Enables the USART transmit interrupt 0 = Disables the USART transmit interrupt bit 3 SSP1IE: Synchronous Serial Port (MSSP) Interrupt Enable bit 1 = Enables the MSSP interrupt 0 = Disables the MSSP interrupt bit 2 Unimplemented: Read as `0' bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the Timer2 to PR2 match interrupt 0 = Disables the Timer2 to PR2 match interrupt bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit 1 = Enables the Timer1 overflow interrupt 0 = Disables the Timer1 overflow interrupt 2011 Microchip Technology Inc. Preliminary DS41609A-page 79 PIC16(L)F1508/9 7.6.3 PIE2 REGISTER The PIE2 register contains the interrupt enable bits, as shown in Register 7-3. REGISTER 7-3: Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 U-0 U-0 OSFIE C2IE C1IE -- BCL1IE NCO1IE -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 OSFIE: Oscillator Fail Interrupt Enable bit 1 = Enables the Oscillator Fail interrupt 0 = Disables the Oscillator Fail interrupt bit 6 C2IE: Comparator C2 Interrupt Enable bit 1 = Enables the Comparator C2 interrupt 0 = Disables the Comparator C2 interrupt bit 5 C1IE: Comparator C1 Interrupt Enable bit 1 = Enables the Comparator C1 interrupt 0 = Disables the Comparator C1 interrupt bit 4 Unimplemented: Read as `0' bit 3 BCL1IE: MSSP Bus Collision Interrupt Enable bit 1 = Enables the MSSP Bus Collision Interrupt 0 = Disables the MSSP Bus Collision Interrupt bit 2 NCO1IE: Numerically Controlled Oscillator Interrupt Enable bit 1 = Enables the NCO interrupt 0 = Disables the NCO interrupt bit 1-0 Unimplemented: Read as `0' DS41609A-page 80 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 7.6.4 PIE3 REGISTER The PIE3 register contains the interrupt enable bits, as shown in Register 7-4. REGISTER 7-4: Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 -- -- -- -- CLC4IE CLC3IE CLC2IE CLC1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-4 Unimplemented: Read as `0' bit 3 CLC4IE: Configurable Logic Block 4 Interrupt Enable bit 1 = Enables the CLC 4 interrupt 0 = Disables the CLC 4 interrupt bit 2 CLC3IE: Configurable Logic Block 3 Interrupt Enable bit 1 = Enables the CLC 3 interrupt 0 = Disables the CLC 3 interrupt bit 1 CLC2IE: Configurable Logic Block 2 Interrupt Enable bit 1 = Enables the CLC 2 interrupt 0 = Disables the CLC 2 interrupt bit 0 CLC1IE: Configurable Logic Block 1 Interrupt Enable bit 1 = Enables the CLC 1 interrupt 0 = Disables the CLC 1 interrupt 2011 Microchip Technology Inc. Preliminary DS41609A-page 81 PIC16(L)F1508/9 7.6.5 PIR1 REGISTER The PIR1 register contains the interrupt flag bits, as shown in Register 7-5. REGISTER 7-5: Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 TMR1GIF ADIF RCIF TXIF SSP1IF -- TMR2IF TMR1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 TMR1GIF: Timer1 Gate Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 6 ADIF: A/D Converter Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 5 RCIF: USART Receive Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 4 TXIF: USART Transmit Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 3 SSP1IF: Synchronous Serial Port (MSSP) Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 2 Unimplemented: Read as `0' bit 1 TMR2IF: Timer2 to PR2 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending DS41609A-page 82 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 7.6.6 PIR2 REGISTER The PIR2 register contains the interrupt flag bits, as shown in Register 7-6. REGISTER 7-6: Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 U-0 U-0 OSFIF C2IF C1IF -- BCL1IF NCO1IF -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 OSFIF: Oscillator Fail Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 6 C2IF: Numerically Controlled Oscillator Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 5 C1IF: Numerically Controlled Oscillator Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 4 Unimplemented: Read as `0' bit 3 BCL1IF: MSSP Bus Collision Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 2 NCO1IF: Numerically Controlled Oscillator Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 1-0 Unimplemented: Read as `0' 2011 Microchip Technology Inc. Preliminary DS41609A-page 83 PIC16(L)F1508/9 7.6.7 PIR3 REGISTER The PIR3 register contains the interrupt flag bits, as shown in Register 7-7. REGISTER 7-7: Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. PIR3: PERIPHERAL INTERRUPT REQUEST REGISTER 3 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 -- -- -- -- CLC4IF CLC3IF CLC2IF CLC1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-4 Unimplemented: Read as `0' bit 3 CLC4IF: Configurable Logic Block 4 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 2 CLC3IF: Configurable Logic Block 3 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 1 CLC2IF: Configurable Logic Block 2 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 0 CLC1IF: Configurable Logic Block 1 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending DS41609A-page 84 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 TABLE 7-1: Name INTCON SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 78 OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PIE1 TMR1GIE ADIE RCIE TXIE PSA PS<2:0> SSP1IE -- TMR2IE 165 TMR1IE 79 PIE2 OSFIE C2IE C1IE -- BCL1IE NCO1IE -- -- 80 PIE3 -- -- -- -- CLC4IE CLC4IE CLC2IE CLC1IE 81 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF -- TMR2IF TMR1IF 82 PIR2 OSFIF C2IF C1IF -- BCL1IF NCO1IF -- -- 83 PIR3 -- -- -- -- CLC4IF CLC3IF CLC2IF CLC1IF 84 Legend: -- = unimplemented location, read as `0'. Shaded cells are not used by interrupts. 2011 Microchip Technology Inc. Preliminary DS41609A-page 85 PIC16(L)F1508/9 NOTES: DS41609A-page 86 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 8.0 POWER-DOWN MODE (SLEEP) The Power-Down mode is entered by executing a SLEEP instruction. Upon entering Sleep mode, the following conditions exist: 1. 2. 3. 4. 5. 6. 7. 8. WDT will be cleared but keeps running, if enabled for operation during Sleep. PD bit of the STATUS register is cleared. TO bit of the STATUS register is set. CPU clock is disabled. 31 kHz LFINTOSC is unaffected and peripherals that operate from it may continue operation in Sleep. ADC is unaffected, if the dedicated FRC clock is selected. I/O ports maintain the status they had before SLEEP was executed (driving high, low or highimpedance). Resets other than WDT are not affected by Sleep mode. Refer to individual chapters for more details on peripheral operation during Sleep. To minimize current consumption, the following conditions should be considered: * * * * * * I/O pins should not be floating External circuitry sinking current from I/O pins Internal circuitry sourcing current from I/O pins Current draw from pins with internal weak pull-ups Modules using 31 kHz LFINTOSC CWG, NCO and CLC modules using HFINTOSC I/O pins that are high-impedance inputs should be pulled to VDD or VSS externally to avoid switching currents caused by floating inputs. Examples of internal circuitry that might be sourcing current include the FVR module. See Section 13.0 "Fixed Voltage Reference (FVR)" for more information on this module. 2011 Microchip Technology Inc. 8.1 Wake-up from Sleep The device can wake-up from Sleep through one of the following events: 1. External Reset input on MCLR pin, if enabled 2. BOR Reset, if enabled 3. POR Reset 4. Watchdog Timer, if enabled 5. Any external interrupt 6. Interrupts by peripherals capable of running during Sleep (see individual peripheral for more information) The first three events will cause a device Reset. The last three events are considered a continuation of program execution. To determine whether a device Reset or wake-up event occurred, refer to Section 6.11 "Determining the Cause of a Reset". When the SLEEP instruction is being executed, the next instruction (PC + 1) is prefetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be enabled. Wake-up will occur regardless of the state of the GIE bit. If the GIE bit is disabled, the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is enabled, the device executes the instruction after the SLEEP instruction, the device will then call the Interrupt Service Routine. In cases where the execution of the instruction following SLEEP is not desirable, the user should have a NOP after the SLEEP instruction. The WDT is cleared when the device wakes up from Sleep, regardless of the source of wake-up. 8.1.1 WAKE-UP USING INTERRUPTS When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: * If the interrupt occurs before the execution of a SLEEP instruction - SLEEP instruction will execute as a NOP. - WDT and WDT prescaler will not be cleared - TO bit of the STATUS register will not be set - PD bit of the STATUS register will not be cleared. * If the interrupt occurs during or after the execution of a SLEEP instruction - SLEEP instruction will be completely executed - Device will immediately wake-up from Sleep - WDT and WDT prescaler will be cleared - TO bit of the STATUS register will be set - PD bit of the STATUS register will be cleared Preliminary DS41609A-page 87 PIC16(L)F1508/9 Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. FIGURE 8-1: WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CLKIN(1) T1OSC(3) CLKOUT(2) Interrupt Latency (4) Interrupt flag GIE bit (INTCON reg.) Processor in Sleep Instruction Flow PC Instruction Fetched Instruction Executed Note 1: 2: 3: 4: PC Inst(PC) = Sleep Inst(PC - 1) PC + 1 PC + 2 PC + 2 Inst(PC + 1) Inst(PC + 2) Sleep Inst(PC + 1) PC + 2 Forced NOP 0004h 0005h Inst(0004h) Inst(0005h) Forced NOP Inst(0004h) External clock. High, Medium, Low mode assumed. CLKOUT is shown here for timing reference. T1OSC; See Section 29.0 "Electrical Specifications". GIE = 1 assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution will continue in-line. DS41609A-page 88 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 8.2 Low-Power Sleep Mode 8.2.2 The PIC16F1508/9 device contains an internal Low Dropout (LDO) voltage regulator, which allows the device I/O pins to operate at voltages up to 5.5V while the internal device logic operates at a lower voltage. The LDO and its associated reference circuitry must remain active when the device is in Sleep mode. The PIC16F1508/9 allows the user to optimize the operating current in Sleep, depending on the application requirements. A Low-Power Sleep mode can be selected by setting the VREGPM bit of the VREGCON register. With this bit set, the LDO and reference circuitry are placed in a low-power state when the device is in Sleep. 8.2.1 SLEEP CURRENT VS. WAKE-UP TIME In the default operating mode, the LDO and reference circuitry remain in the normal configuration while in Sleep. The device is able to exit Sleep mode quickly since all circuits remain active. In Low-Power Sleep mode, when waking up from Sleep, an extra delay time is required for these circuits to return to the normal configuration and stabilize. The Low-Power Sleep mode is beneficial for applications that stay in Sleep mode for long periods of time. The Normal mode is beneficial for applications that need to wake from Sleep quickly and frequently. 2011 Microchip Technology Inc. PERIPHERAL USAGE IN SLEEP Some peripherals that can operate in Sleep mode will not operate properly with the Low-Power Sleep mode selected. The LDO will remain in the Normal Power mode when those peripherals are enabled. The LowPower Sleep mode is intended for use with these peripherals: * * * * Brown-Out Reset (BOR) Watchdog Timer (WDT) External interrupt pin/Interrupt-on-change pins Timer1 (with external clock source) The Complementary Waveform Generator (CWG), the Numerically Controlled Oscillator (NCO) and the Configurable Logic Cell (CLC) modules can utilize the HFINTOSC oscillator as either a clock source or as an input source. Under certain conditions, when the HFINTOSC is selected for use with the CWG, NCO or CLC modules, the HFINTOSC will remain active during Sleep. This will have a direct effect on the Sleep mode current. Please refer to sections 24.5 "Operation During Sleep", 25.7 "Operation In Sleep" and 26.10 "Operation During Sleep" for more information. Note: Preliminary The PIC16LF1508/9 does not have a configurable Low-Power Sleep mode. PIC16LF1508/9 is an unregulated device and is always in the lowest power state when in Sleep, with no wake-up time penalty. This device has a lower maximum VDD and I/O voltage than the PIC16F1508/9. See Section 29.0 "Electrical Specifications" for more information. DS41609A-page 89 PIC16(L)F1508/9 VREGCON: VOLTAGE REGULATOR CONTROL REGISTER(1) REGISTER 8-1: U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-1/1 -- -- -- -- -- -- VREGPM Reserved bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-2 Unimplemented: Read as `0' bit 1 VREGPM: Voltage Regulator Power Mode Selection bit 1 = Low-Power Sleep mode enabled in Sleep Draws lowest current in Sleep, slower wake-up 0 = Normal Power mode enabled in Sleep Draws higher current in Sleep, faster wake-up bit 0 Reserved: Read as `1'. Maintain this bit set. Note 1: PIC16F1508/9 only. TABLE 8-1: SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 78 IOCAF -- -- IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 127 IOCAN -- -- IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 127 IOCAP -- -- IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 127 IOCBF IOCBF7 IOCBF6 IOCBF5 IOCBF4 -- -- -- -- 128 IOCBN IOCBN7 IOCBN6 IOCBN5 IOCBN4 -- -- -- -- 128 IOCBP IOCBP7 IOCBP6 IOCBP5 IOCBP4 -- -- -- -- 128 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE -- TMR2IE TMR1IE 79 PIE2 OSFIE C2IE C1IE -- BCL1IE NCO1IE -- -- 80 PIE3 -- -- -- -- CLC4IE CLC4IE CLC2IE CLC1IE 81 TMR2IF TMR1IF 82 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF -- PIR2 OSFIF C2IF C1IF -- BCL1IF NCO1IF -- -- 83 PIR3 -- -- -- -- CLC4IF CLC3IF CLC2IF CLC1IF 84 STATUS -- -- -- TO PD Z DC C 21 WDTCON -- -- SWDTEN 93 WDTPS<4:0> Legend: -- = unimplemented, read as `0'. Shaded cells are not used in Power-Down mode. DS41609A-page 90 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 9.0 WATCHDOG TIMER The Watchdog Timer is a system timer that generates a Reset if the firmware does not issue a CLRWDT instruction within the time-out period. The Watchdog Timer is typically used to recover the system from unexpected events. The WDT has the following features: * Independent clock source * Multiple operating modes - WDT is always on - WDT is off when in Sleep - WDT is controlled by software - WDT is always off * Configurable time-out period is from 1 ms to 256 seconds (typical) * Multiple Reset conditions * Operation during Sleep FIGURE 9-1: WATCHDOG TIMER BLOCK DIAGRAM WDTE<1:0> = 01 SWDTEN WDTE<1:0> = 11 LFINTOSC 23-bit Programmable Prescaler WDT WDT Time-out WDTE<1:0> = 10 Sleep 2011 Microchip Technology Inc. WDTPS<4:0> Preliminary DS41609A-page 91 PIC16(L)F1508/9 9.1 Independent Clock Source 9.3 Time-Out Period The WDT derives its time base from the 31 kHz LFINTOSC internal oscillator. Time intervals in this chapter are based on a nominal interval of 1 ms. See Section 29.0 "Electrical Specifications" for the LFINTOSC tolerances. The WDTPS bits of the WDTCON register set the time-out period from 1 ms to 256 seconds (nominal). After a Reset, the default time-out period is 2 seconds. 9.2 The WDT is cleared when any of the following conditions occur: WDT Operating Modes The Watchdog Timer module has four operating modes controlled by the WDTE<1:0> bits in Configuration Words. See Table 9-1. 9.4 Clearing the WDT When the WDTE bits of Configuration Words are set to `11', the WDT is always on. * * * * * * WDT protection is active during Sleep. See Table 9-2 for more information. 9.2.2 9.5 9.2.1 WDT IS ALWAYS ON WDT IS OFF IN SLEEP When the WDTE bits of Configuration Words are set to `10', the WDT is on, except in Sleep. WDT protection is not active during Sleep. 9.2.3 WDT CONTROLLED BY SOFTWARE When the WDTE bits of Configuration Words are set to `01', the WDT is controlled by the SWDTEN bit of the WDTCON register. WDT protection is unchanged by Sleep. See Table 9-1 for more details. TABLE 9-1: WDT OPERATING MODES WDTE<1:0> SWDTEN Device Mode WDT Mode 11 X X Active 10 X Awake Active Sleep Disabled 1 01 0 00 TABLE 9-2: X X X Any Reset CLRWDT instruction is executed Device enters Sleep Device wakes up from Sleep Oscillator fail WDT is disabled Operation During Sleep When the device enters Sleep, the WDT is cleared. If the WDT is enabled during Sleep, the WDT resumes counting. When the device exits Sleep, the WDT is cleared again. The WDT remains clear until the OST, if enabled, completes. See Section 5.0 "Oscillator Module (With Fail-Safe Clock Monitor)" for more information on the OST. When a WDT time-out occurs while the device is in Sleep, no Reset is generated. Instead, the device wakes up and resumes operation. The TO and PD bits in the STATUS register are changed to indicate the event. The RWDT bit in the PCON register can also be used. See Section 3.0 "Memory Organization" for more information. Active Disabled Disabled WDT CLEARING CONDITIONS Conditions WDT WDTE<1:0> = 00 WDTE<1:0> = 01 and SWDTEN = 0 WDTE<1:0> = 10 and enter Sleep Cleared CLRWDT Command Oscillator Fail Detected Exit Sleep + System Clock = INTOSC, EXTCLK Change INTOSC divider (IRCF bits) DS41609A-page 92 Unaffected Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 9.6 Watchdog Control Register REGISTER 9-1: WDTCON: WATCHDOG TIMER CONTROL REGISTER U-0 U-0 -- -- R/W-0/0 R/W-1/1 R/W-0/0 R/W-1/1 R/W-1/1 WDTPS<4:0> bit 7 R/W-0/0 SWDTEN bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-6 Unimplemented: Read as `0' bit 5-1 WDTPS<4:0>: Watchdog Timer Period Select bits(1) Bit Value = Prescale Rate 00000 = 1:32 (Interval 1 ms nominal) 00001 = 1:64 (Interval 2 ms nominal) 00010 = 1:128 (Interval 4 ms nominal) 00011 = 1:256 (Interval 8 ms nominal) 00100 = 1:512 (Interval 16 ms nominal) 00101 = 1:1024 (Interval 32 ms nominal) 00110 = 1:2048 (Interval 64 ms nominal) 00111 = 1:4096 (Interval 128 ms nominal) 01000 = 1:8192 (Interval 256 ms nominal) 01001 = 1:16384 (Interval 512 ms nominal) 01010 = 1:32768 (Interval 1s nominal) 01011 = 1:65536 (Interval 2s nominal) (Reset value) 01100 = 1:131072 (217) (Interval 4s nominal) 01101 = 1:262144 (218) (Interval 8s nominal) 01110 = 1:524288 (219) (Interval 16s nominal) 01111 = 1:1048576 (220) (Interval 32s nominal) 10000 = 1:2097152 (221) (Interval 64s nominal) 10001 = 1:4194304 (222) (Interval 128s nominal) 10010 = 1:8388608 (223) (Interval 256s nominal) 10011 = Reserved. Results in minimum interval (1:32) * * * 11111 = Reserved. Results in minimum interval (1:32) bit 0 Note 1: SWDTEN: Software Enable/Disable for Watchdog Timer bit If WDTE<1:0> = 00: This bit is ignored. If WDTE<1:0> = 01: 1 = WDT is turned on 0 = WDT is turned off If WDTE<1:0> = 1x: This bit is ignored. Times are approximate. WDT time is based on 31 kHz LFINTOSC. 2011 Microchip Technology Inc. Preliminary DS41609A-page 93 PIC16(L)F1508/9 TABLE 9-3: SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER Name Bit 7 OSCCON Bit 6 -- PCON Bit 5 Bit 4 Bit 3 IRCF<3:0> STKUNF -- RWDT STATUS -- -- -- TO WDTCON -- -- CONFIG1 Legend: Bit 0 SCS<1:0> RMCLR RI POR PD Z DC WDTPS<4:0> Register on Page 62 BOR 71 C 21 SWDTEN 93 x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by Watchdog Timer. TABLE 9-4: Name Bit 1 -- STKOVF Legend: Bit 2 SUMMARY OF CONFIGURATION WORD WITH WATCHDOG TIMER Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 13:8 -- -- FCMEN IESO CLKOUTEN 7:0 CP MCLRE PWRTE WDTE<1:0> Bit 10/2 Bit 9/1 BOREN<1:0> FOSC<2:0> Bit 8/0 -- Register on Page 44 -- = unimplemented location, read as `0'. Shaded cells are not used by Watchdog Timer. DS41609A-page 94 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 10.0 FLASH PROGRAM MEMORY CONTROL The Flash program memory is readable and writable during normal operation over the full VDD range. Program memory is indirectly addressed using Special Function Registers (SFRs). The SFRs used to access program memory are: * * * * * * PMCON1 PMCON2 PMDATL PMDATH PMADRL PMADRH Control bits RD and WR initiate read and write, respectively. These bits cannot be cleared, only set, in software. They are cleared by hardware at completion of the read or write operation. The inability to clear the WR bit in software prevents the accidental, premature termination of a write operation. The WREN bit, when set, will allow a write operation to occur. On power-up, the WREN bit is clear. The WRERR bit is set when a write operation is interrupted by a Reset during normal operation. In these situations, following Reset, the user can check the WRERR bit and execute the appropriate error handling routine. The PMCON2 register is a write-only register. Attempting to read the PMCON2 register will return all `0's. When accessing the program memory, the PMDATH:PMDATL register pair forms a 2-byte word that holds the 14-bit data for read/write, and the PMADRH:PMADRL register pair forms a 2-byte word that holds the 15-bit address of the program memory location being read. The write time is controlled by an on-chip timer. The write/ erase voltages are generated by an on-chip charge pump. The Flash program memory can be protected in two ways; by code protection (CP bit in Configuration Words) and write protection (WRT<1:0> bits in Configuration Words). 0)(1), disables access, reading Code protection (CP = and writing, to the Flash program memory via external device programmers. Code protection does not affect the self-write and erase functionality. Code protection can only be reset by a device programmer performing a Bulk Erase to the device, clearing all Flash program memory, Configuration bits and User IDs. To enable writes to the program memory, a specific pattern (the unlock sequence), must be written to the PMCON2 register. The required unlock sequence prevents inadvertent writes to the program memory write latches and Flash program memory. 10.2 It is important to understand the Flash program memory structure for erase and programming operations. Flash program memory is arranged in rows. A row consists of a fixed number of 14-bit program memory words. A row is the minimum size that can be erased by user software. After a row has been erased, the user can reprogram all or a portion of this row. Data to be written into the program memory row is written to 14-bit wide data write latches. These write latches are not directly accessible to the user, but may be loaded via sequential writes to the PMDATH:PMDATL register pair. Note: Write protection prohibits self-write and erase to a portion or all of the Flash program memory as defined by the bits WRT<1:0>. Write protection does not affect a device programmers ability to read, write or erase the device. Note 1: Code protection of the entire Flash program memory array is enabled by clearing the CP bit of Configuration Words. 10.1 PMADRL and PMADRH Registers The PMADRH:PMADRL register pair can address up to a maximum of 32K words of program memory. When selecting a program address value, the MSB of the address is written to the PMADRH register and the LSB is written to the PMADRL register. 10.1.1 If the user wants to modify only a portion of a previously programmed row, then the contents of the entire row must be read and saved in RAM prior to the erase. Then, new data and retained data can be written into the write latches to reprogram the row of Flash program memory. However, any unprogrammed locations can be written without first erasing the row. In this case, it is not necessary to save and rewrite the other previously programmed locations. See Table 10-1 for Erase Row size and the number of write latches for Flash program memory. TABLE 10-1: FLASH MEMORY ORGANIZATION BY DEVICE Device PMCON1 AND PMCON2 REGISTERS PMCON1 is the control register for Flash program memory accesses. 2011 Microchip Technology Inc. Flash Program Memory Overview PIC16(L)F1508 PIC16(L)F1509 Preliminary Row Erase (words) Write Latches (words) 32 32 DS41609A-page 95 PIC16(L)F1508/9 FIGURE 10-1: 10.2.1 READING THE FLASH PROGRAM MEMORY FLASH PROGRAM MEMORY READ FLOWCHART To read a program memory location, the user must: 1. 2. 3. Write the desired address to the PMADRH:PMADRL register pair. Clear the CFGS bit of the PMCON1 register. Then, set control bit RD of the PMCON1 register. Once the read control bit is set, the program memory Flash controller will use the second instruction cycle to read the data. This causes the second instruction immediately following the "BSF PMCON1,RD" instruction to be ignored. The data is available in the very next cycle, in the PMDATH:PMDATL register pair; therefore, it can be read as two bytes in the following instructions. PMDATH:PMDATL register pair will hold this value until another read or until it is written to by the user. Note: The two instructions following a program memory read are required to be NOPs. This prevents the user from executing a two-cycle instruction on the next instruction after the RD bit is set. Start Read Operation Select Program or Configuration Memory (CFGS) Select Word Address (PMADRH:PMADRL) Initiate Read operation (RD = 1) Instruction Fetched ignored NOP execution forced Instruction Fetched ignored NOP execution forced Data read now in PMDATH:PMDATL End Read Operation DS41609A-page 96 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 FIGURE 10-2: FLASH PROGRAM MEMORY READ CYCLE EXECUTION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC Flash ADDR Flash Data PC + 1 INSTR (PC) INSTR(PC - 1) executed here PC +3 PC+3 PMADRH,PMADRL INSTR (PC + 1) BSF PMCON1,RD executed here PMDATH,PMDATL INSTR(PC + 1) instruction ignored Forced NOP executed here PC + 4 INSTR (PC + 3) INSTR(PC + 2) instruction ignored Forced NOP executed here PC + 5 INSTR (PC + 4) INSTR(PC + 3) executed here INSTR(PC + 4) executed here RD bit PMDATH PMDATL Register EXAMPLE 10-1: FLASH PROGRAM MEMORY READ * This code block will read 1 word of program * memory at the memory address: PROG_ADDR_HI : PROG_ADDR_LO * data will be returned in the variables; * PROG_DATA_HI, PROG_DATA_LO BANKSEL MOVLW MOVWF MOVLW MOVWF PMADRL PROG_ADDR_LO PMADRL PROG_ADDR_HI PMADRH ; Select Bank for PMCON registers ; ; Store LSB of address ; ; Store MSB of address BCF BSF NOP NOP PMCON1,CFGS PMCON1,RD ; ; ; ; Do not select Configuration Space Initiate read Ignored (Figure 10-2) Ignored (Figure 10-2) MOVF MOVWF MOVF MOVWF PMDATL,W PROG_DATA_LO PMDATH,W PROG_DATA_HI ; ; ; ; Get LSB of word Store in user location Get MSB of word Store in user location 2011 Microchip Technology Inc. Preliminary DS41609A-page 97 PIC16(L)F1508/9 10.2.2 FLASH MEMORY UNLOCK SEQUENCE FIGURE 10-3: The unlock sequence is a mechanism that protects the Flash program memory from unintended self-write programming or erasing. The sequence must be executed and completed without interruption to successfully complete any of the following operations: * Row Erase * Load program memory write latches * Write of program memory write latches to program memory * Write of program memory write latches to User IDs FLASH PROGRAM MEMORY UNLOCK SEQUENCE FLOWCHART Start Unlock Sequence Write 055h to PMCON2 The unlock sequence consists of the following steps: Write 0AAh to PMCON2 1. Write 55h to PMCON2 Initiate Write or Erase operation (WR = 1) 2. Write AAh to PMCON2 3. Set the WR bit in PMCON1 4. NOP instruction 5. NOP instruction Once the WR bit is set, the processor will always force two NOP instructions. When an Erase Row or Program Row operation is being performed, the processor will stall internal operations (typical 2 ms), until the operation is complete and then resume with the next instruction. When the operation is loading the program memory write latches, the processor will always force the two NOP instructions and continue uninterrupted with the next instruction. Instruction Fetched ignored NOP execution forced Instruction Fetched ignored NOP execution forced End Unlock Sequence Since the unlock sequence must not be interrupted, global interrupts should be disabled prior to the unlock sequence and re-enabled after the unlock sequence is completed. DS41609A-page 98 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 10.2.3 ERASING FLASH PROGRAM MEMORY FIGURE 10-4: While executing code, program memory can only be erased by rows. To erase a row: 1. 2. 3. 4. 5. Load the PMADRH:PMADRL register pair with any address within the row to be erased. Clear the CFGS bit of the PMCON1 register. Set the FREE and WREN bits of the PMCON1 register. Write 55h, then AAh, to PMCON2 (Flash programming unlock sequence). Set control bit WR of the PMCON1 register to begin the erase operation. See Example 10-2. After the "BSF PMCON1,WR" instruction, the processor requires two cycles to set up the erase operation. The user must place two NOP instructions immediately following the WR bit set instruction. The processor will halt internal operations for the typical 2 ms erase time. This is not Sleep mode as the clocks and peripherals will continue to run. After the erase cycle, the processor will resume operation with the third instruction after the PMCON1 write instruction. FLASH PROGRAM MEMORY ERASE FLOWCHART Start Erase Operation Disable Interrupts (GIE = 0) Select Program or Configuration Memory (CFGS) Select Row Address (PMADRH:PMADRL) Select Erase Operation (FREE = 1) Enable Write/Erase Operation (WREN = 1) Unlock Sequence Figure 10-3 (FIGURE x-x) CPU stalls while Erase operation completes (2ms typical) Disable Write/Erase Operation (WREN = 0) Re-enable Interrupts (GIE = 1) End Erase Operation 2011 Microchip Technology Inc. Preliminary DS41609A-page 99 PIC16(L)F1508/9 EXAMPLE 10-2: ERASING ONE ROW OF PROGRAM MEMORY Required Sequence ; This row erase routine assumes the following: ; 1. A valid address within the erase row is loaded in ADDRH:ADDRL ; 2. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F (common RAM) BCF BANKSEL MOVF MOVWF MOVF MOVWF BCF BSF BSF INTCON,GIE PMADRL ADDRL,W PMADRL ADDRH,W PMADRH PMCON1,CFGS PMCON1,FREE PMCON1,WREN MOVLW MOVWF MOVLW MOVWF BSF NOP NOP 55h PMCON2 0AAh PMCON2 PMCON1,WR BCF BSF DS41609A-page 100 PMCON1,WREN INTCON,GIE ; Disable ints so required sequences will execute properly ; Load lower 8 bits of erase address boundary ; Load upper 6 bits of erase address boundary ; Not configuration space ; Specify an erase operation ; Enable writes ; ; ; ; ; ; ; ; ; ; Start of required sequence to initiate erase Write 55h Write AAh Set WR bit to begin erase NOP instructions are forced as processor starts row erase of program memory. The processor stalls until the erase process is complete after erase processor continues with 3rd instruction ; Disable writes ; Enable interrupts Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 10.2.4 WRITING TO FLASH PROGRAM MEMORY Program memory is programmed using the following steps: 1. 2. 3. 4. Load the address in PMADRH:PMADRL of the row to be programmed. Load each write latch with data. Initiate a programming operation. Repeat steps 1 through 3 until all data is written. The following steps should be completed to load the write latches and program a row of program memory. These steps are divided into two parts. First, each write latch is loaded with data from the PMDATH:PMDATL using the unlock sequence with LWLO = 1. When the last word to be loaded into the write latch is ready, the LWLO bit is cleared and the unlock sequence executed. This initiates the programming operation, writing all the latches into Flash program memory. Note: Before writing to program memory, the word(s) to be written must be erased or previously unwritten. Program memory can only be erased one row at a time. No automatic erase occurs upon the initiation of the write. Program memory can be written one or more words at a time. The maximum number of words written at one time is equal to the number of write latches. See Figure 10-5 (row writes to program memory with 32 write latches) for more details. The write latches are aligned to the Flash row address boundary defined by the upper 10-bits of PMADRH:PMADRL, (PMADRH<6:0>:PMADRL<7:5>) with the lower 5-bits of PMADRL, (PMADRL<4:0>) determining the write latch being loaded. Write operations do not cross these boundaries. At the completion of a program memory write operation, the data in the write latches is reset to contain 0x3FFF. The special unlock sequence is required to load a write latch with data or initiate a Flash programming operation. If the unlock sequence is interrupted, writing to the latches or program memory will not be initiated. 1. 2. 3. Set the WREN bit of the PMCON1 register. Clear the CFGS bit of the PMCON1 register. Set the LWLO bit of the PMCON1 register. When the LWLO bit of the PMCON1 register is `1', the write sequence will only load the write latches and will not initiate the write to Flash program memory. 4. Load the PMADRH:PMADRL register pair with the address of the location to be written. 5. Load the PMDATH:PMDATL register pair with the program memory data to be written. 6. Execute the unlock sequence (Section 10.2.2 "Flash Memory Unlock Sequence"). The write latch is now loaded. 7. Increment the PMADRH:PMADRL register pair to point to the next location. 8. Repeat steps 5 through 7 until all but the last write latch has been loaded. 9. Clear the LWLO bit of the PMCON1 register. When the LWLO bit of the PMCON1 register is `0', the write sequence will initiate the write to Flash program memory. 10. Load the PMDATH:PMDATL register pair with the program memory data to be written. 11. Execute the unlock sequence (Section 10.2.2 "Flash Memory Unlock Sequence"). The entire program memory latch content is now written to Flash program memory. Note: The program memory write latches are reset to the blank state (0x3FFF) at the completion of every write or erase operation. As a result, it is not necessary to load all the program memory write latches. Unloaded latches will remain in the blank state. An example of the complete write sequence is shown in Example 10-3. The initial address is loaded into the PMADRH:PMADRL register pair; the data is loaded using indirect addressing. 2011 Microchip Technology Inc. Preliminary DS41609A-page 101 7 BLOCK WRITES TO FLASH PROGRAM MEMORY WITH 32 WRITE LATCHES 6 0 7 5 4 PMADRH - r9 r8 r7 r6 r5 7 0 PMADRL r4 r3 r2 r1 r0 c4 c3 c2 c1 c0 5 - 0 7 PMDATH 6 0 PMDATL 8 14 10 Program Memory Write Latches 5 14 Write Latch #0 00h PMADRL<4:0> Preliminary 14 CFGS = 0 2011 Microchip Technology Inc. PMADRH<6:0> :PMADRL<7:5> Row Address Decode 14 14 Write Latch #1 01h 14 Write Latch #30 Write Latch #31 1Eh 1Fh 14 14 14 Row Addr Addr Addr Addr 000h 0000h 0001h 001Eh 001Fh 001h 0020h 0021h 003Eh 003Fh 002h 0040h 0041h 005Eh 005Fh 3FEh 7FC0h 7FC1h 7FDEh 7FDFh 3FFh 7FE0h 7FE1h 7FFEh 7FFFh Flash Program Memory 400h CFGS = 1 8000h - 8003h 8004h - 8005h 8006h 8007h - 8008h 8009h - 801Fh USER ID 0 - 3 reserved DEVICEID REVID Configuration Words reserved Configuration Memory PIC16(L)F1508/9 DS41609A-page 102 FIGURE 10-5: PIC16(L)F1508/9 FIGURE 10-6: FLASH PROGRAM MEMORY WRITE FLOWCHART Start Write Operation Determine number of words to be written into Program or Configuration Memory. The number of words cannot exceed the number of words per row. (word_cnt) Disable Interrupts (GIE = 0) Select Program or Config. Memory (CFGS) Select Row Address (PMADRH:PMADRL) Enable Write/Erase Operation (WREN = 1) Load the value to write (PMDATH:PMDATL) Update the word counter (word_cnt--) Last word to write ? Yes No Unlock Sequence (Figure10-3 x-x) Figure Select Write Operation (FREE = 0) No delay when writing to Program Memory Latches Load Write Latches Only (LWLO = 1) Increment Address (PMADRH:PMADRL++) Write Latches to Flash (LWLO = 0) Unlock Sequence (Figure10-3 x-x) Figure CPU stalls while Write operation completes (2ms typical) Disable Write/Erase Operation (WREN = 0) Re-enable Interrupts (GIE = 1) End Write Operation 2011 Microchip Technology Inc. Preliminary DS41609A-page 103 PIC16(L)F1508/9 EXAMPLE 10-3: ; ; ; ; ; ; ; WRITING TO FLASH PROGRAM MEMORY This write routine assumes the following: 1. 64 bytes of data are loaded, starting at the address in DATA_ADDR 2. Each word of data to be written is made up of two adjacent bytes in DATA_ADDR, stored in little endian format 3. A valid starting address (the least significant bits = 00000) is loaded in ADDRH:ADDRL 4. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F (common RAM) BCF BANKSEL MOVF MOVWF MOVF MOVWF MOVLW MOVWF MOVLW MOVWF BCF BSF BSF INTCON,GIE PMADRH ADDRH,W PMADRH ADDRL,W PMADRL LOW DATA_ADDR FSR0L HIGH DATA_ADDR FSR0H PMCON1,CFGS PMCON1,WREN PMCON1,LWLO ; ; ; ; ; ; ; ; ; ; ; ; ; Disable ints so required sequences will execute properly Bank 3 Load initial address MOVIW MOVWF MOVIW MOVWF FSR0++ PMDATL FSR0++ PMDATH ; Load first data byte into lower ; ; Load second data byte into upper ; MOVF XORLW ANDLW BTFSC GOTO PMADRL,W 0x1F 0x1F STATUS,Z START_WRITE ; Check if lower bits of address are '00000' ; Check if we're on the last of 32 addresses ; ; Exit if last of 32 words, ; MOVLW MOVWF MOVLW MOVWF BSF NOP 55h PMCON2 0AAh PMCON2 PMCON1,WR ; ; ; ; ; ; ; ; PMADRL,F LOOP ; Still loading latches Increment address ; Write next latches PMCON1,LWLO ; No more loading latches - Actually start Flash program ; memory write 55h PMCON2 0AAh PMCON2 PMCON1,WR ; ; ; ; ; ; ; ; ; ; ; ; ; Load initial data address Load initial data address Not configuration space Enable writes Only Load Write Latches Required Sequence LOOP NOP INCF GOTO Required Sequence START_WRITE BCF MOVLW MOVWF MOVLW MOVWF BSF NOP NOP BCF BSF DS41609A-page 104 PMCON1,WREN INTCON,GIE Start of required write sequence: Write 55h Write AAh Set WR bit to begin write NOP instructions are forced as processor loads program memory write latches Start of required write sequence: Write 55h Write AAh Set WR bit to begin write NOP instructions are forced as processor writes all the program memory write latches simultaneously to program memory. After NOPs, the processor stalls until the self-write process in complete after write processor continues with 3rd instruction Disable writes Enable interrupts Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 10.3 Modifying Flash Program Memory FIGURE 10-7: When modifying existing data in a program memory row, and data within that row must be preserved, it must first be read and saved in a RAM image. Program memory is modified using the following steps: 1. 2. 3. 4. 5. 6. 7. Load the starting address of the row to be modified. Read the existing data from the row into a RAM image. Modify the RAM image to contain the new data to be written into program memory. Load the starting address of the row to be rewritten. Erase the program memory row. Load the write latches with data from the RAM image. Initiate a programming operation. FLASH PROGRAM MEMORY MODIFY FLOWCHART Start Modify Operation Read Operation (Figure10-2 x.x) Figure An image of the entire row read must be stored in RAM Modify Image The words to be modified are changed in the RAM image Erase Operation (Figure10-4 x.x) Figure WRITE Operation use RAM image (Figure10-5 x.x) Figure End Modify Operation 2011 Microchip Technology Inc. Preliminary DS41609A-page 105 PIC16(L)F1508/9 10.4 User ID, Device ID and Configuration Word Access Instead of accessing program memory, the User ID's, Device ID/Revision ID and Configuration Words can be accessed when CFGS = 1 in the PMCON1 register. This is the region that would be pointed to by PC<15> = 1, but not all addresses are accessible. Different access may exist for reads and writes. Refer to Table 10-2. When read access is initiated on an address outside the parameters listed in Table 10-2, the PMDATH:PMDATL register pair is cleared, reading back `0's. TABLE 10-2: USER ID, DEVICE ID AND CONFIGURATION WORD ACCESS (CFGS = 1) Address Function Read Access Write Access 8000h-8003h 8006h 8007h-8008h User IDs Device ID/Revision ID Configuration Words 1 and 2 Yes Yes Yes Yes No No EXAMPLE 10-4: CONFIGURATION WORD AND DEVICE ID ACCESS * This code block will read 1 word of program memory at the memory address: * PROG_ADDR_LO (must be 00h-08h) data will be returned in the variables; * PROG_DATA_HI, PROG_DATA_LO BANKSEL MOVLW MOVWF CLRF PMADRL PROG_ADDR_LO PMADRL PMADRH ; Select correct Bank ; ; Store LSB of address ; Clear MSB of address BSF BCF BSF NOP NOP BSF PMCON1,CFGS INTCON,GIE PMCON1,RD INTCON,GIE ; ; ; ; ; ; Select Configuration Space Disable interrupts Initiate read Executed (See Figure 10-2) Ignored (See Figure 10-2) Restore interrupts MOVF MOVWF MOVF MOVWF PMDATL,W PROG_DATA_LO PMDATH,W PROG_DATA_HI ; ; ; ; Get LSB of word Store in user location Get MSB of word Store in user location DS41609A-page 106 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 10.5 Write Verify It is considered good programming practice to verify that program memory writes agree with the intended value. Since program memory is stored as a full page then the stored program memory contents are compared with the intended data stored in RAM after the last write is complete. FIGURE 10-8: FLASH PROGRAM MEMORY VERIFY FLOWCHART Start Verify Operation This routine assumes that the last row of data written was from an image saved in RAM. This image will be used to verify the data currently stored in Flash Program Memory. Read Operation (Figure x.x) Figure 10-2 PMDAT = RAM image ? Yes No No Fail Verify Operation Last Word ? Yes End Verify Operation 2011 Microchip Technology Inc. Preliminary DS41609A-page 107 PIC16(L)F1508/9 10.6 Flash Program Memory Control Registers REGISTER 10-1: R/W-x/u PMDATL: PROGRAM MEMORY DATA LOW BYTE REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u PMDAT<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 PMDAT<7:0>: Read/write value for Least Significant bits of program memory REGISTER 10-2: PMDATH: PROGRAM MEMORY DATA HIGH BYTE REGISTER U-0 U-0 -- -- R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u PMDAT<13:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-6 Unimplemented: Read as `0' bit 5-0 PMDAT<13:8>: Read/write value for Most Significant bits of program memory REGISTER 10-3: R/W-0/0 PMADRL: PROGRAM MEMORY ADDRESS LOW BYTE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 PMADR<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 PMADR<7:0>: Specifies the Least Significant bits for program memory address REGISTER 10-4: U-1 PMADRH: PROGRAM MEMORY ADDRESS HIGH BYTE REGISTER R/W-0/0 R/W-0/0 -- R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 PMADR<14:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 Unimplemented: Read as `1' bit 6-0 PMADR<14:8>: Specifies the Most Significant bits for program memory address DS41609A-page 108 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 REGISTER 10-5: PMCON1: PROGRAM MEMORY CONTROL 1 REGISTER U-1(1) R/W-0/0 R/W-0/0 R/W/HC-0/0 R/W/HC-x/q(2) R/W-0/0 R/S/HC-0/0 R/S/HC-0/0 -- CFGS LWLO FREE WRERR WREN WR RD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared HC = Bit is cleared by hardware bit 7 Unimplemented: Read as `1' bit 6 CFGS: Configuration Select bit 1 = Access Configuration, User ID and Device ID Registers 0 = Access Flash program memory bit 5 LWLO: Load Write Latches Only bit(3) 1 = Only the addressed program memory write latch is loaded/updated on the next WR command 0 = The addressed program memory write latch is loaded/updated and a write of all program memory write latches will be initiated on the next WR command bit 4 FREE: Program Flash Erase Enable bit 1 = Performs an erase operation on the next WR command (hardware cleared upon completion) 0 = Performs a write operation on the next WR command bit 3 WRERR: Program/Erase Error Flag bit 1 = Condition indicates an improper program or erase sequence attempt or termination (bit is set automatically on any set attempt (write `1') of the WR bit). 0 = The program or erase operation completed normally. bit 2 WREN: Program/Erase Enable bit 1 = Allows program/erase cycles 0 = Inhibits programming/erasing of program Flash bit 1 WR: Write Control bit 1 = Initiates a program Flash program/erase operation. The operation is self-timed and the bit is cleared by hardware once operation is complete. The WR bit can only be set (not cleared) in software. 0 = Program/erase operation to the Flash is complete and inactive. bit 0 RD: Read Control bit 1 = Initiates a program Flash read. Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in software. 0 = Does not initiate a program Flash read. Note 1: 2: 3: Unimplemented bit, read as `1'. The WRERR bit is automatically set by hardware when a program memory write or erase operation is started (WR = 1). The LWLO bit is ignored during a program memory erase operation (FREE = 1). 2011 Microchip Technology Inc. Preliminary DS41609A-page 109 PIC16(L)F1508/9 REGISTER 10-6: W-0/0 PMCON2: PROGRAM MEMORY CONTROL 2 REGISTER W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 Program Memory Control Register 2 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 Flash Memory Unlock Pattern bits To unlock writes, a 55h must be written first, followed by an AAh, before setting the WR bit of the PMCON1 register. The value written to this register is used to unlock the writes. There are specific timing requirements on these writes. TABLE 10-3: SUMMARY OF REGISTERS ASSOCIATED WITH FLASH PROGRAM MEMORY Register on Page Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 78 PMCON1 -- CFGS LWLO FREE WRERR WREN WR RD 109 PMCON2 Program Memory Control Register 2 110 PMADRL PMADRL<7:0> 108 -- PMADRH PMADRH<6:0> PMDATL -- PMDATH Legend: CONFIG1 CONFIG2 Legend: -- 108 PMDATH<5:0> 108 -- = unimplemented location, read as `0'. Shaded cells are not used by Flash program memory module. TABLE 10-4: Name 108 PMDATL<7:0> SUMMARY OF CONFIGURATION WORD WITH FLASH PROGRAM MEMORY Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 IESO CLKOUTEN Bit 10/2 13:8 -- -- FCMEN 7:0 CP MCLRE PWRTE 13:8 -- -- LVP DEBUG LPBOR BORV 7:0 -- -- -- -- -- -- Bit 9/1 Bit 8/0 BOREN<1:0> WDTE<1:0> -- FOSC<2:0> STVREN WRT<1:0> -- Register on Page 44 45 -- = unimplemented location, read as `0'. Shaded cells are not used by Flash program memory. DS41609A-page 110 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 11.0 I/O PORTS FIGURE 11-1: GENERIC I/O PORT OPERATION Each port has three standard registers for its operation. These registers are: * TRISx registers (data direction) * PORTx registers (reads the levels on the pins of the device) * LATx registers (output latch) Read LATx D Some ports may have one or more of the following additional registers. These registers are: Write LATx Write PORTx * ANSELx (analog select) * WPUx (weak pull-up) Q CK VDD Data Register In general, when a peripheral is enabled on a port pin, that pin cannot be used as a general purpose output. However, the pin can still be read. Data Bus I/O pin Read PORTx To peripherals ANSELx Device PORTB PORTC PORT AVAILABILITY PER DEVICE PORTA TABLE 11-1: TRISx PIC16(L)F1508/9 VSS The Data Latch (LATx registers) is useful for read-modify-write operations on the value that the I/O pins are driving. A write operation to the LATx register has the same effect as a write to the corresponding PORTx register. A read of the LATx register reads of the values held in the I/O PORT latches, while a read of the PORTx register reads the actual I/O pin value. Ports that support analog inputs have an associated ANSELx register. When an ANSEL bit is set, the digital input buffer associated with that bit is disabled. Disabling the input buffer prevents analog signal levels on the pin between a logic high and low from causing excessive current in the logic input circuitry. A simplified model of a generic I/O port, without the interfaces to other peripherals, is shown in Figure 11-1. 2011 Microchip Technology Inc. Preliminary DS41609A-page 111 PIC16(L)F1508/9 11.1 Alternate Pin Function The Alternate Pin Function Control register is used to steer specific peripheral input and output functions between different pins. The APFCON register is shown in Register 11-1. For this device family, the following functions can be moved between different pins. * * * * SS T1G CLC1 NCO1 These bits have no effect on the values of any TRIS register. PORT and TRIS overrides will be routed to the correct pin. The unselected pin will be unaffected. REGISTER 11-1: APFCON: ALTERNATE PIN FUNCTION CONTROL REGISTER U-0 U-0 U-0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 -- -- -- SSSEL T1GSEL -- CLC1SEL NCO1SEL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-5 Unimplemented: Read as `0' bit 4 SSSEL: Pin Selection bit 1 = SS function is on RA3 0 = SS function is on RC6 bit 3 T1GSEL: Pin Selection bit 1 = T1G function is on RA3 0 = T1G function is on RA4 bit 2 Unimplemented: Read as `0' bit 1 CLC1SEL: Pin Selection bit 1 = CLC1 function is on RC5 0 = CLC1 function is on RA2 bit 0 NCO1SEL: Pin Selection bit 1 = NCO1 function is on RA6 0 = NCO1 function is on RC1 DS41609A-page 112 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 11.2 PORTA Registers 11.2.2 PORTA is a 6-bit wide, bidirectional port. The corresponding data direction register is TRISA (Register 11-3). Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., disable the output driver). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., enables output driver and puts the contents of the output latch on the selected pin). The exception is RA3, which is input only and its TRIS bit will always read as `1'. Example 11-1 shows how to initialize an I/O port. Reading the PORTA register (Register 11-2) reads the status of the pins, whereas writing to it will write to the PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch (LATA). Each PORTA pin is multiplexed with other functions. The pins, their combined functions and their output priorities are shown in Table 11-2. When multiple outputs are enabled, the actual pin control goes to the peripheral with the highest priority. Analog input functions, such as ADC and comparator inputs, are not shown in the priority lists. These inputs are active when the I/O pin is set for Analog mode using the ANSELx registers. Digital output functions may control the pin when it is in Analog mode with the priority shown below in Table 11-2. TABLE 11-2: Function Priority(1) RA0 ICSPDAT DACOUT1 RA0 RA1 RA1 RA2 DACOUT2 CLC1(2) C1OUT PWM3 RA2 RA3 None RA4 CLKOUT SOSCO RA4 RA5 SOSCI RA5 ANSELA REGISTER The ANSELA register (Register 11-5) is used to configure the Input mode of an I/O pin to analog. Setting the appropriate ANSELA bit high will cause all digital reads on the pin to be read as `0' and allow analog functions on the pin to operate correctly. The state of the ANSELA bits has no effect on digital output functions. A pin with TRIS clear and ANSEL set will still operate as a digital output, but the Input mode will be analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected port. Note: Note 1: 2: 3: Priority listed from highest to lowest. Default pin (see APFCON register). Alternate pin (see APFCON register). The ANSELA bits default to the Analog mode after Reset. To use any pins as digital general purpose or peripheral inputs, the corresponding ANSEL bits must be initialized to `0' by user software. EXAMPLE 11-1: BANKSEL CLRF BANKSEL CLRF BANKSEL CLRF BANKSEL MOVLW MOVWF PORTA OUTPUT PRIORITY Pin Name The TRISA register (Register 11-3) controls the PORTA pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the TRISA register are maintained set when using them as analog inputs. I/O pins configured as analog input always read `0'. 11.2.1 PORTA FUNCTIONS AND OUTPUT PRIORITIES INITIALIZING PORTA PORTA PORTA LATA LATA ANSELA ANSELA TRISA B'00111000' TRISA ; ;Init PORTA ;Data Latch ; ; ;digital I/O ; ;Set RA<5:3> as inputs ;and set RA<2:0> as ;outputs 2011 Microchip Technology Inc. Preliminary DS41609A-page 113 PIC16(L)F1508/9 REGISTER 11-2: PORTA: PORTA REGISTER U-0 U-0 R/W-x/x R/W-x/x R-x/x R/W-x/x R/W-x/x R/W-x/x -- -- RA5 RA4 RA3 RA2 RA1 RA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-6 Unimplemented: Read as `0' bit 5-0 RA<5:0>: PORTA I/O Value bits(1) 1 = Port pin is > VIH 0 = Port pin is < VIL Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return of actual I/O pin values. REGISTER 11-3: TRISA: PORTA TRI-STATE REGISTER U-0 U-0 R/W-1/1 R/W-1/1 U-1 R/W-1/1 R/W-1/1 R/W-1/1 -- -- TRISA5 TRISA4 --(1) TRISA2 TRISA1 TRISA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-6 Unimplemented: Read as `0' bit 5-4 TRISA<5:4>: PORTA Tri-State Control bit 1 = PORTA pin configured as an input (tri-stated) 0 = PORTA pin configured as an output bit 3 Unimplemented: Read as `1' bit 2-0 TRISA<2:0>: PORTA Tri-State Control bit 1 = PORTA pin configured as an input (tri-stated) 0 = PORTA pin configured as an output Note 1: Unimplemented, read as `1'. DS41609A-page 114 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 REGISTER 11-4: LATA: PORTA DATA LATCH REGISTER U-0 U-0 R/W-x/u R/W-x/u U-0 R/W-x/u R/W-x/u R/W-x/u -- -- LATA5 LATA4 -- LATA2 LATA1 LATA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-6 Unimplemented: Read as `0' bit 5-4 LATA<5:4>: RA<5:4> Output Latch Value bits(1) bit 3 Unimplemented: Read as `0' bit 2-0 LATA<2:0>: RA<2:0> Output Latch Value bits(1) Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return of actual I/O pin values. REGISTER 11-5: ANSELA: PORTA ANALOG SELECT REGISTER U-0 U-0 U-0 R/W-1/1 U-0 R/W-1/1 R/W-1/1 R/W-1/1 -- -- -- ANSA4 -- ANSA2 ANSA1 ANSA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-5 Unimplemented: Read as `0' bit 4 ANSA4: Analog Select between Analog or Digital Function on pins RA4, respectively 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled. 0 = Digital I/O. Pin is assigned to port or digital special function. bit 3 Unimplemented: Read as `0' bit 2-0 ANSA<2:0>: Analog Select between Analog or Digital Function on pins RA<2:0>, respectively 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled. 0 = Digital I/O. Pin is assigned to port or digital special function. Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. 2011 Microchip Technology Inc. Preliminary DS41609A-page 115 PIC16(L)F1508/9 REGISTER 11-6: WPUA: WEAK PULL-UP PORTA REGISTER U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 -- -- WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-6 Unimplemented: Read as `0' bit 5-0 WPUA<5:0>: Weak Pull-up Register bits(3) 1 = Pull-up enabled 0 = Pull-up disabled Note 1: 2: 3: Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled. The weak pull-up device is automatically disabled if the pin is configured as an output. For the WPUA3 bit, when MCLRE = 1, weak pull-up is internally enabled, but not reported here. TABLE 11-3: Name SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Bit 7 Bit 6 Bit 5 Bit 4 ANSELA -- -- -- APFCON -- -- -- LATA Bit 0 Register on Page ANSA1 ANSA0 115 CLC1SEL NCO1SEL 112 Bit 3 Bit 2 Bit 1 ANSA4 -- ANSA2 SSSEL T1GSEL -- LATA2 LATA1 LATA0 -- -- LATA5 LATA4 -- WPUEN INTEDG TMR0CS TMR0SE PSA PORTA -- -- RA5 RA4 RA3 RA2 RA1 RA0 114 TRISA -- -- TRISA5 TRISA4 --(1) TRISA2 TRISA1 TRISA0 114 -- -- WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 116 OPTION_REG WPUA Legend: Note 1: CONFIG1 Legend: 165 x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by PORTA. Unimplemented, read as `1'. TABLE 11-4: Name 115 PS<2:0> SUMMARY OF CONFIGURATION WORD WITH PORTA Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 IESO CLKOUTEN 13:8 -- -- FCMEN 7:0 CP MCLRE PWRTE Bit 10/2 WDTE<1:0> Bit 9/1 BOREN<1:0> FOSC<2:0> Bit 8/0 -- Register on Page 44 -- = unimplemented location, read as `0'. Shaded cells are not used by PORTA. DS41609A-page 116 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 11.3 PORTB Registers 11.3.2 PORTB is a 4-bit wide, bidirectional port. The corresponding data direction register is TRISB (Register 11-3). Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., disable the output driver). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., enables output driver and puts the contents of the output latch on the selected pin). Example 11-1 shows how to initialize an I/O port. Reading the PORTB register (Register 11-2) reads the status of the pins, whereas writing to it will write to the PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch (LATB). Each PORTB pin is multiplexed with other functions. The pins, their combined functions and their output priorities are shown in Table 11-2. When multiple outputs are enabled, the actual pin control goes to the peripheral with the highest priority. Analog input functions, such as ADC and comparator inputs, are not shown in the priority lists. These inputs are active when the I/O pin is set for Analog mode using the ANSELx registers. Digital output functions may control the pin when it is in Analog mode with the priority shown below in Table 11-2. TABLE 11-5: Pin Name The TRISB register (Register 11-3) controls the PORTB pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the TRISB register are maintained set when using them as analog inputs. I/O pins configured as analog input always read `0'. 11.3.1 ANSELB REGISTER The ANSELB register (Register 11-5) is used to configure the Input mode of an I/O pin to analog. Setting the appropriate ANSELB bit high will cause all digital reads on the pin to be read as `0' and allow analog functions on the pin to operate correctly. PORTB FUNCTIONS AND OUTPUT PRIORITIES Note 1: 2: 3: PORTB OUTPUT PRIORITY Function Priority(1) RB4 SDA RB4 RB5 RB5 RB6 SCL SCK RB6 RB7 CLC3 TX RB7 Priority listed from highest to lowest. Default pin (see APFCON register). Alternate pin (see APFCON register). The state of the ANSELB bits has no effect on digital output functions. A pin with TRIS clear and ANSEL set will still operate as a digital output, but the Input mode will be analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected port. Note: The ANSELB bits default to the Analog mode after Reset. To use any pins as digital general purpose or peripheral inputs, the corresponding ANSEL bits must be initialized to `0' by user software. 2011 Microchip Technology Inc. Preliminary DS41609A-page 117 PIC16(L)F1508/9 REGISTER 11-7: PORTB: PORTB REGISTER R/W-x/x R/W-x/x R/W-x/x R/W-x/x U-0 U-0 U-0 U-0 RB7 RB6 RB5 RB4 -- -- -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-4 RB<7:4>: PORTB I/O Value bits(1) 1 = Port pin is > VIH 0 = Port pin is < VIL bit 3-0 Unimplemented: Read as `0' Note 1: Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is return of actual I/O pin values. REGISTER 11-8: TRISB: PORTB TRI-STATE REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 U-0 U-0 U-0 U-0 TRISB7 TRISB6 TRISB5 TRISB4 -- -- -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-4 RB<7:4>: PORTB Tri-State Control bits 1 = PORTB pin configured as an input (tri-stated) 0 = PORTB pin configured as an output bit 3-0 Unimplemented: Read as `0' DS41609A-page 118 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 REGISTER 11-9: LATB: PORTB DATA LATCH REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u U-0 U-0 U-0 U-0 LATB7 LATB6 LATB5 LATB4 -- -- -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-4 LATB<7:4>: RB<7:4> Output Latch Value bits(1) bit 3-0 Unimplemented: Read as `0' Note 1: Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is return of actual I/O pin values. REGISTER 11-10: ANSELB: PORTB ANALOG SELECT REGISTER U-0 U-0 R/W-1/1 R/W-1/1 U-0 U-0 U-0 U-0 -- -- ANSB5 ANSB4 -- -- -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-6 Unimplemented: Read as `0' bit 5-4 ANSB<5:4>: Analog Select between Analog or Digital Function on pins RB<5:4>, respectively 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled. 0 = Digital I/O. Pin is assigned to port or digital special function. bit 3-0 Unimplemented: Read as `0' Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. 2011 Microchip Technology Inc. Preliminary DS41609A-page 119 PIC16(L)F1508/9 REGISTER 11-11: WPUB: WEAK PULL-UP PORTB REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 U-0 U-0 U-0 U-0 WPUB7 WPUB6 WPUB5 WPUB4 -- -- -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-4 WPUB<7:4>: Weak Pull-up Register bits 1 = Pull-up enabled 0 = Pull-up disabled bit 3-0 Unimplemented: Read as `0' Note 1: 2: Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled. The weak pull-up device is automatically disabled if the pin is configured as an output. TABLE 11-6: Name SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page -- -- ANSB5 ANSB4 -- -- -- -- 119 ANSELB APFCON LATB OPTION_REG PORTB -- -- -- SSSEL T1GSEL -- CLC1SEL NCO1SEL 112 LATB7 LATB6 LATB5 LATB4 -- -- -- -- 119 WPUEN INTEDG TMR0CS TMR0SE PSA RB7 RB6 RB5 RB4 -- -- -- -- PS<2:0> 165 118 TRISB TRISB7 TRISB6 TRISB5 TRISB4 -- -- -- -- 118 WPUB WPUB7 WPUB6 WPUB5 WPUB4 -- -- -- -- 120 Legend: Note 1: x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by PORTB. Unimplemented, read as `1'. TABLE 11-7: Name CONFIG1 Legend: SUMMARY OF CONFIGURATION WORD WITH PORTB Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 IESO CLKOUTEN 13:8 -- -- FCMEN 7:0 CP MCLRE PWRTE Bit 10/2 WDTE<1:0> Bit 9/1 BOREN<1:0> FOSC<2:0> Bit 8/0 -- Register on Page 44 -- = unimplemented location, read as `0'. Shaded cells are not used by PORTB. DS41609A-page 120 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 11.4 PORTC Registers 11.4.2 PORTC is a 8-bit wide, bidirectional port. The corresponding data direction register is TRISC (Register 11-13). Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). Example 11-1 shows how to initialize an I/O port. Reading the PORTC register (Register 11-12) reads the status of the pins, whereas writing to it will write to the PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch (LATC). Each PORTC pin is multiplexed with other functions. The pins, their combined functions and their output priorities are shown in Table 11-8. When multiple outputs are enabled, the actual pin control goes to the peripheral with the highest priority. Analog input and some digital input functions are not included in the output priority list. These input functions can remain active when the pin is configured as an output. Certain digital input functions override other port functions and are included in the output priority list. TABLE 11-8: Pin Name The TRISC register (Register 11-13) controls the PORTC pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the TRISC register are maintained set when using them as analog inputs. I/O pins configured as analog input always read `0'. 11.4.1 ANSELC REGISTER The ANSELC register (Register 11-15) is used to configure the Input mode of an I/O pin to analog. Setting the appropriate ANSELC bit high will cause all digital reads on the pin to be read as `0' and allow analog functions on the pin to operate correctly. The state of the ANSELC bits has no effect on digital output functions. A pin with TRIS clear and ANSELC set will still operate as a digital output, but the Input mode will be analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected port. Note: The ANSELC bits default to the Analog mode after Reset. To use any pins as digital general purpose or peripheral inputs, the corresponding ANSEL bits must be initialized to `0' by user software. 2011 Microchip Technology Inc. PORTC FUNCTIONS AND OUTPUT PRIORITIES Function Priority(1) RC0 CLC2 RC0 RC1 NCO1(2) PWM4 RC1 RC2 RC2 RC3 PWM2 RC3 RC4 CWG1B CLC4 C2OUT RC4 RC5 CWG1A CLC1(3) PWM1 RC5 RC6 NCO1(3) RC6 RC7 SDO RC7 Note 1: 2: 3: Preliminary PORTC OUTPUT PRIORITY Priority listed from highest to lowest. Default pin (see APFCON register). Alternate pin (see APFCON register). DS41609A-page 121 PIC16(L)F1508/9 REGISTER 11-12: PORTC: PORTC REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 RC<7:0>: PORTC General Purpose I/O Pin bits 1 = Port pin is > VIH 0 = Port pin is < VIL REGISTER 11-13: TRISC: PORTC TRI-STATE REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 TRISC<7:0>: PORTC Tri-State Control bits 1 = PORTC pin configured as an input (tri-stated) 0 = PORTC pin configured as an output REGISTER 11-14: LATC: PORTC DATA LATCH REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 Note 1: LATC<7:0>: PORTC Output Latch Value bits(1) Writes to PORTC are actually written to corresponding LATC register. Reads from PORTC register is return of actual I/O pin values. DS41609A-page 122 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 REGISTER 11-15: ANSELC: PORTC ANALOG SELECT REGISTER R/W-1/1 R/W-1/1 U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 ANSC7 ANSC6 -- -- ANSC3 ANSC2 ANSC1 ANSC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-6 ANSC<7:6>: Analog Select between Analog or Digital Function on pins RC<7:6>, respectively 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled. 0 = Digital I/O. Pin is assigned to port or digital special function. bit 5-4 Unimplemented: Read as `0' bit 3-0 ANSC<3:0>: Analog Select between Analog or Digital Function on pins RC<3:0>, respectively 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled. 0 = Digital I/O. Pin is assigned to port or digital special function. Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. TABLE 11-9: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSELC ANSC7 ANSC6 -- -- ANSC3 ANSC2 ANSC1 ANSC0 123 LATC LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 122 RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 122 TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 122 Name PORTC TRISC Legend: x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by PORTC. 2011 Microchip Technology Inc. Preliminary DS41609A-page 123 PIC16(L)F1508/9 NOTES: DS41609A-page 124 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 12.0 INTERRUPT-ON-CHANGE 12.3 The PORTA and PORTB pins can be configured to operate as Interrupt-On-Change (IOC) pins. An interrupt can be generated by detecting a signal that has either a rising edge or a falling edge. Any individual port pin, or combination of port pins, can be configured to generate an interrupt. The interrupt-on-change module has the following features: * * * * Interrupt-on-Change enable (Master Switch) Individual pin configuration Rising and falling edge detection Individual pin interrupt flags The IOCAFx and IOCBFx bits located in the IOCAF and IOCBF registers, respectively, are status flags that correspond to the interrupt-on-change pins of the associated port. If an expected edge is detected on an appropriately enabled pin, then the status flag for that pin will be set, and an interrupt will be generated if the IOCIE bit is set. The IOCIF bit of the INTCON register reflects the status of all IOCAFx and IOCBFx bits. 12.4 Clearing Interrupt Flags The individual status flags, (IOCAFx and IOCBFx bits), can be cleared by resetting them to zero. If another edge is detected during this clearing operation, the associated status flag will be set at the end of the sequence, regardless of the value actually being written. Figure 12-1 is a block diagram of the IOC module. 12.1 Interrupt Flags Enabling the Module To allow individual port pins to generate an interrupt, the IOCIE bit of the INTCON register must be set. If the IOCIE bit is disabled, the edge detection on the pin will still occur, but an interrupt will not be generated. In order to ensure that no detected edge is lost while clearing flags, only AND operations masking out known changed bits should be performed. The following sequence is an example of what should be performed. 12.2 Individual Pin Configuration EXAMPLE 12-1: For each port pin, a rising edge detector and a falling edge detector are present. To enable a pin to detect a rising edge, the associated bit of the IOCxP register is set. To enable a pin to detect a falling edge, the associated bit of the IOCxN register is set. MOVLW XORWF ANDWF A pin can be configured to detect rising and falling edges simultaneously by setting both associated bits of the IOCxP and IOCxN registers, respectively. 12.5 CLEARING INTERRUPT FLAGS (PORTA EXAMPLE) 0xff IOCAF, W IOCAF, F Operation in Sleep The interrupt-on-change interrupt sequence will wake the device from Sleep mode, if the IOCIE bit is set. If an edge is detected while in Sleep mode, the IOCxF register will be updated prior to the first instruction executed out of Sleep. 2011 Microchip Technology Inc. Preliminary DS41609A-page 125 PIC16(L)F1508/9 FIGURE 12-1: INTERRUPT-ON-CHANGE BLOCK DIAGRAM (PORTA EXAMPLE) IOCANx D Q4Q1 Q CK Edge Detect R RAx IOCAPx D Data Bus = 0 or 1 Q Write IOCAFx CK D S Q To Data Bus IOCAFx CK IOCIE R Q2 From all other IOCAFx individual Pin Detectors Q1 Q2 Q3 Q4 Q4Q1 DS41609A-page 126 Q1 Q1 Q2 Q2 Q3 Q4 Q4Q1 IOC interrupt to CPU core Q3 Q4 Q4 Q4Q1 Preliminary Q4Q1 2011 Microchip Technology Inc. PIC16(L)F1508/9 12.6 Interrupt-On-Change Registers REGISTER 12-1: IOCAP: INTERRUPT-ON-CHANGE PORTA POSITIVE EDGE REGISTER U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 -- -- IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-6 Unimplemented: Read as `0' bit 5-0 IOCAP<5:0>: Interrupt-on-Change PORTA Positive Edge Enable bits 1 = Interrupt-on-Change enabled on the pin for a positive going edge. IOCAFx bit and IOCIF flag will be set upon detecting an edge. 0 = Interrupt-on-Change disabled for the associated pin. REGISTER 12-2: IOCAN: INTERRUPT-ON-CHANGE PORTA NEGATIVE EDGE REGISTER U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 -- -- IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-6 Unimplemented: Read as `0' bit 5-0 IOCAN<5:0>: Interrupt-on-Change PORTA Negative Edge Enable bits 1 = Interrupt-on-Change enabled on the pin for a negative going edge. IOCAFx bit and IOCIF flag will be set upon detecting an edge. 0 = Interrupt-on-Change disabled for the associated pin. REGISTER 12-3: IOCAF: INTERRUPT-ON-CHANGE PORTA FLAG REGISTER U-0 U-0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 -- -- IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared HS - Bit is set in hardware bit 7-6 Unimplemented: Read as `0' bit 5-0 IOCAF<5:0>: Interrupt-on-Change PORTA Flag bits 1 = An enabled change was detected on the associated pin. Set when IOCAPx = 1 and a rising edge was detected on RAx, or when IOCANx = 1 and a falling edge was detected on RAx. 0 = No change was detected, or the user cleared the detected change. 2011 Microchip Technology Inc. Preliminary DS41609A-page 127 PIC16(L)F1508/9 REGISTER 12-4: IOCBP: INTERRUPT-ON-CHANGE PORTB POSITIVE EDGE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 U-0 U-0 IOCBP7 IOCBP6 IOCBP5 IOCBP4 -- -- -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-4 IOCBP<7:4>: Interrupt-on-Change PORTB Positive Edge Enable bits 1 = Interrupt-on-Change enabled on the pin for a positive going edge. IOCBFx bit and IOCIF flag will be set upon detecting an edge. 0 = Interrupt-on-Change disabled for the associated pin. bit 3-0 Unimplemented: Read as `0' REGISTER 12-5: IOCBN: INTERRUPT-ON-CHANGE PORTB NEGATIVE EDGE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 U-0 U-0 IOCBN7 IOCBN6 IOCBN5 IOCBN4 -- -- -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-4 IOCBN<7:4>: Interrupt-on-Change PORTB Negative Edge Enable bits 1 = Interrupt-on-Change enabled on the pin for a negative going edge. IOCBFx bit and IOCIF flag will be set upon detecting an edge. 0 = Interrupt-on-Change disabled for the associated pin. bit 3-0 Unimplemented: Read as `0' REGISTER 12-6: IOCBF: INTERRUPT-ON-CHANGE PORTB FLAG REGISTER R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 U-0 U-0 U-0 U-0 IOCBF7 IOCBF6 IOCBF5 IOCBF4 -- -- -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared HS - Bit is set in hardware bit 7-4 IOCBF<7:4>: Interrupt-on-Change PORTB Flag bits 1 = An enabled change was detected on the associated pin. Set when IOCBPx = 1 and a rising edge was detected on RBx, or when IOCBNx = 1 and a falling edge was detected on RBx. 0 = No change was detected, or the user cleared the detected change. bit 3-0 Unimplemented: Read as `0' DS41609A-page 128 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 TABLE 12-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPT-ON-CHANGE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSELA -- -- -- ANSA4 -- ANSA2 ANSA1 ANSA0 115 INTCON Name GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 78 IOCAF -- -- IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 127 IOCAN -- -- IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 127 IOCAP -- -- IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 127 IOCBF IOCBF7 IOCBF6 IOCBF5 IOCBF4 -- -- -- -- 128 IOCBN IOCBN7 IOCBN6 IOCBN5 IOCBN4 -- -- -- -- 128 IOCBP IOCBP7 IOCBP6 IOCBP5 IOCBP4 -- -- -- -- 128 TRISA -- -- TRISA5 TRISA4 --(1) TRISA2 TRISA1 TRISA0 114 TRISB7 TRISB6 TRISB5 TRISB4 -- -- -- -- 118 TRISB Legend: Note 1: -- = unimplemented location, read as `0'. Shaded cells are not used by interrupt-on-change. Unimplemented, read as `1'. 2011 Microchip Technology Inc. Preliminary DS41609A-page 129 PIC16(L)F1508/9 NOTES: DS41609A-page 130 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 13.0 FIXED VOLTAGE REFERENCE (FVR) The Fixed Voltage Reference, or FVR, is a stable voltage reference, independent of VDD, with 1.024V, 2.048V or 4.096V selectable output levels. The output of the FVR can be configured to supply a reference voltage to the following: * ADC input channel * Comparator positive input * Comparator negative input The FVR can be enabled by setting the FVREN bit of the FVRCON register. 13.1 Independent Gain Amplifier The output of the FVR supplied to the ADC and Comparators is routed through a programmable gain amplifier. Each amplifier can be programmed for a gain of 1x, 2x or 4x, to produce the three possible voltage levels. FIGURE 13-1: The ADFVR<1:0> bits of the FVRCON register are used to enable and configure the gain amplifier settings for the reference supplied to the ADC module. Reference Section 15.0 "Analog-to-Digital Converter (ADC) Module" for additional information. The CDAFVR<1:0> bits of the FVRCON register are used to enable and configure the gain amplifier settings for the reference supplied to the comparator modules. Reference Section 17.0 "Comparator Module" for additional information. 13.2 FVR Stabilization Period When the Fixed Voltage Reference module is enabled, it requires time for the reference and amplifier circuits to stabilize. Once the circuits stabilize and are ready for use, the FVRRDY bit of the FVRCON register will be set. See Section 29.0 "Electrical Specifications" for the minimum delay requirement. VOLTAGE REFERENCE BLOCK DIAGRAM ADFVR<1:0> CDAFVR<1:0> 2 X1 X2 X4 FVR BUFFER1 (To ADC Module) X1 X2 X4 FVR BUFFER2 (To Comparators) 2 FVREN + FVRRDY _ Any peripheral requiring the Fixed Reference (See Table 13-1) TABLE 13-1: Peripheral PERIPHERALS REQUIRING THE FIXED VOLTAGE REFERENCE (FVR) Conditions Description HFINTOSC FOSC<2:0> = 010 and IRCF<3:0> = 000x BOREN<1:0> = 11 BOR always enabled. BOR BOREN<1:0> = 10 and BORFS = 1 BOR disabled in Sleep mode, BOR Fast Start enabled. BOREN<1:0> = 01 and BORFS = 1 BOR under software control, BOR Fast Start enabled. LDO All PIC16F1508/9 devices, when VREGPM = 1 and not in Sleep The device runs off of the Low-Power Regulator when in Sleep mode. 2011 Microchip Technology Inc. INTOSC is active and device is not in Sleep. Preliminary DS41609A-page 131 PIC16(L)F1508/9 13.3 FVR Control Registers REGISTER 13-1: FVRCON: FIXED VOLTAGE REFERENCE CONTROL REGISTER R/W-0/0 R-q/q R/W-0/0 R/W-0/0 FVREN FVRRDY(1) TSEN TSRNG R/W-0/0 R/W-0/0 R/W-0/0 CDAFVR<1:0> R/W-0/0 ADFVR<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7 FVREN: Fixed Voltage Reference Enable bit 1 = Fixed Voltage Reference is enabled 0 = Fixed Voltage Reference is disabled bit 6 FVRRDY: Fixed Voltage Reference Ready Flag bit(1) 1 = Fixed Voltage Reference output is ready for use 0 = Fixed Voltage Reference output is not ready or not enabled bit 5 TSEN: Temperature Indicator Enable bit(3) 1 = Temperature Indicator is enabled 0 = Temperature Indicator is disabled bit 4 TSRNG: Temperature Indicator Range Selection bit(3) 1 = VOUT = VDD - 4VT (High Range) 0 = VOUT = VDD - 2VT (Low Range) bit 3-2 CDAFVR<1:0>: Comparator Fixed Voltage Reference Selection bits 11 = Comparator Fixed Voltage Reference Peripheral output is 4x (4.096V)(2) 10 = Comparator Fixed Voltage Reference Peripheral output is 2x (2.048V)(2) 01 = Comparator Fixed Voltage Reference Peripheral output is 1x (1.024V) 00 = Comparator Fixed Voltage Reference Peripheral output is off bit 1-0 ADFVR<1:0>: ADC Fixed Voltage Reference Selection bit 11 = ADC Fixed Voltage Reference Peripheral output is 4x (4.096V)(2) 10 = ADC Fixed Voltage Reference Peripheral output is 2x (2.048V)(2) 01 = ADC Fixed Voltage Reference Peripheral output is 1x (1.024V) 00 = ADC Fixed Voltage Reference Peripheral output is off Note 1: 2: 3: FVRRDY is always `1' for the PIC16F1508/9 devices. Fixed Voltage Reference output cannot exceed VDD. See Section 14.0 "Temperature Indicator Module" for additional information. TABLE 13-2: Name FVRCON Legend: SUMMARY OF REGISTERS ASSOCIATED WITH THE FIXED VOLTAGE REFERENCE Bit 7 Bit 6 Bit 5 Bit 4 FVREN FVRRDY TSEN TSRNG Bit 3 Bit 2 CDAFVR>1:0> Bit 1 Bit 0 ADFVR<1:0> Register on page 132 Shaded cells are unused by the Fixed Voltage Reference module. DS41609A-page 132 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 14.0 TEMPERATURE INDICATOR MODULE FIGURE 14-1: This family of devices is equipped with a temperature circuit designed to measure the operating temperature of the silicon die. The circuit's range of operating temperature falls between -40C and +85C. The output is a voltage that is proportional to the device temperature. The output of the temperature indicator is internally connected to the device ADC. TEMPERATURE CIRCUIT DIAGRAM VDD TSEN TSRNG The circuit may be used as a temperature threshold detector or a more accurate temperature indicator, depending on the level of calibration performed. A onepoint calibration allows the circuit to indicate a temperature closely surrounding that point. A two-point calibration allows the circuit to sense the entire range of temperature more accurately. Reference Application Note AN1333, "Use and Calibration of the Internal Temperature Indicator" (DS01333) for more details regarding the calibration process. 14.1 Circuit Operation 14.2 Figure 14-1 shows a simplified block diagram of the temperature circuit. The proportional voltage output is achieved by measuring the forward voltage drop across multiple silicon junctions. Equation 14-1 describes the output characteristics of the temperature indicator. EQUATION 14-1: VOUT VOUT RANGES To ADC Minimum Operating VDD When the temperature circuit is operated in low range, the device may be operated at any operating voltage that is within specifications. When the temperature circuit is operated in high range, the device operating voltage, VDD, must be high enough to ensure that the temperature circuit is correctly biased. Table 14-1 shows the recommended minimum VDD vs. range setting. High Range: VOUT = VDD - 4VT TABLE 14-1: Low Range: VOUT = VDD - 2VT The temperature sense circuit is integrated with the Fixed Voltage Reference (FVR) module. See Section 13.0 "Fixed Voltage Reference (FVR)" for more information. The circuit is enabled by setting the TSEN bit of the FVRCON register. When disabled, the circuit draws no current. The circuit operates in either high or low range. The high range, selected by setting the TSRNG bit of the FVRCON register, provides a wider output voltage. This provides more resolution over the temperature range, but may be less consistent from part to part. This range requires a higher bias voltage to operate and thus, a higher VDD is needed. The low range is selected by clearing the TSRNG bit of the FVRCON register. The low range generates a lower voltage drop and thus, a lower bias voltage is needed to operate the circuit. The low range is provided for low voltage operation. 2011 Microchip Technology Inc. RECOMMENDED VDD VS. RANGE Min. VDD, TSRNG = 1 Min. VDD, TSRNG = 0 3.6V 1.8V 14.3 Temperature Output The output of the circuit is measured using the internal Analog-to-Digital Converter. A channel is reserved for the temperature circuit output. Refer to Section 15.0 "Analog-to-Digital Converter (ADC) Module" for detailed information. 14.4 ADC Acquisition Time To ensure accurate temperature measurements, the user must wait at least 200 s after the ADC input multiplexer is connected to the temperature indicator output before the conversion is performed. In addition, the user must wait 200 s between sequential conversions of the temperature indicator output. Preliminary DS41609A-page 133 PIC16(L)F1508/9 TABLE 14-2: Name FVRCON Legend: SUMMARY OF REGISTERS ASSOCIATED WITH THE TEMPERATURE INDICATOR Bit 7 Bit 6 Bit 5 Bit 4 FVREN FVRRDY TSEN TSRNG Bit 3 Bit 2 CDAFVR<1:0> Bit 1 Bit 0 ADFVR<1:0> Register on page 118 Shaded cells are unused by the temperature indicator module. DS41609A-page 134 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 15.0 ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE The ADC can generate an interrupt upon completion of a conversion. This interrupt can be used to wake-up the device from Sleep. The Analog-to-Digital Converter (ADC) allows conversion of an analog input signal to a 10-bit binary representation of that signal. This device uses analog inputs, which are multiplexed into a single sample and hold circuit. The output of the sample and hold is connected to the input of the converter. The converter generates a 10-bit binary result via successive approximation and stores the conversion result into the ADC result registers (ADRESH:ADRESL register pair). Figure 15-1 shows the block diagram of the ADC. The ADC voltage reference is software selectable to be either internally generated or externally supplied. FIGURE 15-1: ADC BLOCK DIAGRAM VDD ADPREF = 00 VREF+ AN0 00000 VREF+/AN1 00001 AN2 00010 AN3 00011 AN4 00100 AN5 00101 AN6 00110 AN7 AN8 00111 01000 AN9 01001 AN10 01010 AN11 Reserved 01011 01100 Reserved 11100 ADPREF = 10 VREF- = VSS VREF+ ADC 10 GO/DONE ADFM 0 = Left Justify 1 = Right Justify ADON Temp Indicator 11101 DAC FVR Buffer1 11110 16 VSS ADRESH ADRESL 11111 CHS<4:0> Note 1: When ADON = 0, all multiplexer inputs are disconnected. 2011 Microchip Technology Inc. Preliminary DS41609A-page 135 PIC16(L)F1508/9 15.1 ADC Configuration 15.1.4 When configuring and using the ADC the following functions must be considered: * * * * * * Port configuration Channel selection ADC voltage reference selection ADC conversion clock source Interrupt control Result formatting 15.1.1 The ADC can be used to convert both analog and digital signals. When converting analog signals, the I/O pin should be configured for analog by setting the associated TRIS and ANSEL bits. Refer to Section 11.0 "I/O Ports" for more information. Note: 15.1.2 The source of the conversion clock is software selectable via the ADCS bits of the ADCON1 register. There are seven possible clock options: * * * * * * * PORT CONFIGURATION Analog voltages on any pin that is defined as a digital input may cause the input buffer to conduct excess current. FOSC/2 FOSC/4 FOSC/8 FOSC/16 FOSC/32 FOSC/64 FRC (dedicated internal oscillator) The time to complete one bit conversion is defined as TAD. One full 10-bit conversion requires 11.5 TAD periods as shown in Figure 15-2. For correct conversion, the appropriate TAD specification must be met. Refer to the A/D conversion requirements in Section 29.0 "Electrical Specifications" for more information. Table 15-1 gives examples of appropriate ADC clock selections. Note: CHANNEL SELECTION There are 15 channel selections available: * * * * CONVERSION CLOCK AN<11:0> pins Temperature Indicator DAC FVR (Fixed Voltage Reference) Output Unless using the FRC, any changes in the system clock frequency will change the ADC clock frequency, which may adversely affect the ADC result. Refer to Section 13.0 "Fixed Voltage Reference (FVR)" and Section 14.0 "Temperature Indicator Module" for more information on these channel selections. The CHS bits of the ADCON0 register determine which channel is connected to the sample and hold circuit. When changing channels, a delay is required before starting the next conversion. Refer to Section 15.2 "ADC Operation" for more information. 15.1.3 ADC VOLTAGE REFERENCE The ADPREF bits of the ADCON1 register provides control of the positive voltage reference. The positive voltage reference can be: * VREF+ pin * VDD See Section 13.0 "Fixed Voltage Reference (FVR)" for more details on the Fixed Voltage Reference. DS41609A-page 136 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 TABLE 15-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES ADC Clock Period (TAD) Device Frequency (FOSC) ADC Clock Source ADCS<2:0> 20 MHz 16 MHz 8 MHz 4 MHz 1 MHz Fosc/2 000 100 ns(2) 125 ns(2) 250 ns(2) 500 ns(2) 2.0 s Fosc/4 100 (2) 200 ns (2) 250 ns (2) Fosc/8 001 400 ns(2) 0.5 s(2) Fosc/16 101 800 ns 1.0 s Fosc/32 1.6 s 010 2.0 s Fosc/64 110 3.2 s 4.0 s FRC x11 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) Legend: Note 1: 2: 3: 4: 1.0 s 4.0 s 1.0 s 2.0 s 8.0 s(3) 2.0 s 4.0 s 16.0 s(3) 500 ns 4.0 s (3) 8.0 s 1.0-6.0 s(1,4) (3) 8.0 s (3) 16.0 s 1.0-6.0 s(1,4) 32.0 s(3) 64.0 s(3) 1.0-6.0 s(1,4) Shaded cells are outside of recommended range. The FRC source has a typical TAD time of 1.6 s for VDD. These values violate the minimum required TAD time. For faster conversion times, the selection of another clock source is recommended. The ADC clock period (TAD) and total ADC conversion time can be minimized when the ADC clock is derived from the system clock FOSC. However, the FRC clock source must be used when conversions are to be performed with the device in Sleep mode. FIGURE 15-2: ANALOG-TO-DIGITAL CONVERSION TAD CYCLES TCY - TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11 b4 b1 b0 b6 b7 b2 b8 b3 b9 b5 Conversion starts Holding capacitor is disconnected from analog input (typically 100 ns) Set GO bit On the following cycle: ADRESH:ADRESL is loaded, GO bit is cleared, ADIF bit is set, holding capacitor is connected to analog input. 2011 Microchip Technology Inc. Preliminary DS41609A-page 137 PIC16(L)F1508/9 15.1.5 INTERRUPTS 15.1.6 The ADC module allows for the ability to generate an interrupt upon completion of an Analog-to-Digital conversion. The ADC Interrupt Flag is the ADIF bit in the PIR1 register. The ADC Interrupt Enable is the ADIE bit in the PIE1 register. The ADIF bit must be cleared in software. RESULT FORMATTING The 10-bit A/D conversion result can be supplied in two formats, left justified or right justified. The ADFM bit of the ADCON1 register controls the output format. Figure 15-3 shows the two output formats. Note 1: The ADIF bit is set at the completion of every conversion, regardless of whether or not the ADC interrupt is enabled. 2: The ADC operates during Sleep only when the FRC oscillator is selected. This interrupt can be generated while the device is operating or while in Sleep. If the device is in Sleep, the interrupt will wake-up the device. Upon waking from Sleep, the next instruction following the SLEEP instruction is always executed. If the user is attempting to wake-up from Sleep and resume in-line code execution, the GIE and PEIE bits of the INTCON register must be disabled. If the GIE and PEIE bits of the INTCON register are enabled, execution will switch to the Interrupt Service Routine. FIGURE 15-3: 10-BIT A/D CONVERSION RESULT FORMAT ADRESH (ADFM = 0) ADRESL MSB LSB bit 7 bit 0 bit 7 Unimplemented: Read as `0' 10-bit A/D Result (ADFM = 1) MSB bit 7 LSB bit 0 Unimplemented: Read as `0' DS41609A-page 138 bit 0 bit 7 bit 0 10-bit A/D Result Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 15.2 15.2.1 ADC Operation 15.2.4 STARTING A CONVERSION To enable the ADC module, the ADON bit of the ADCON0 register must be set to a `1'. Setting the GO/ DONE bit of the ADCON0 register to a `1' will start the Analog-to-Digital conversion. Note: 15.2.2 The GO/DONE bit should not be set in the same instruction that turns on the ADC. Refer to Section 15.2.6 "A/D Conversion Procedure". COMPLETION OF A CONVERSION When the conversion is complete, the ADC module will: * Clear the GO/DONE bit * Set the ADIF Interrupt Flag bit * Update the ADRESH and ADRESL registers with new conversion result 15.2.3 TERMINATING A CONVERSION If a conversion must be terminated before completion, the GO/DONE bit can be cleared in software. The ADRESH and ADRESL registers will be updated with the partially complete Analog-to-Digital conversion sample. Incomplete bits will match the last bit converted. Note: A device Reset forces all registers to their Reset state. Thus, the ADC module is turned off and any pending conversion is terminated. 2011 Microchip Technology Inc. ADC OPERATION DURING SLEEP The ADC module can operate during Sleep. This requires the ADC clock source to be set to the FRC option. When the FRC clock source is selected, the ADC waits one additional instruction before starting the conversion. This allows the SLEEP instruction to be executed, which can reduce system noise during the conversion. If the ADC interrupt is enabled, the device will wake-up from Sleep when the conversion completes. If the ADC interrupt is disabled, the ADC module is turned off after the conversion completes, although the ADON bit remains set. When the ADC clock source is something other than FRC, a SLEEP instruction causes the present conversion to be aborted and the ADC module is turned off, although the ADON bit remains set. 15.2.5 AUTO-CONVERSION TRIGGER The auto-conversion trigger allows periodic ADC measurements without software intervention. When a rising edge of the selected source occurs, the GO/DONE bit is set by hardware. The auto-conversion trigger source is selected with the TRIGSEL<3:0> bits of the ADCON2 register. Using the auto-conversion trigger does not assure proper ADC timing. It is the user's responsibility to ensure that the ADC timing requirements are met. Auto-Conversion sources are: * * * * * * * * * TMR0 TMR1 TMR2 C1 C2 CLC1 CLC2 CLC3 CLC4 Preliminary DS41609A-page 139 PIC16(L)F1508/9 15.2.6 A/D CONVERSION PROCEDURE EXAMPLE 15-1: This is an example procedure for using the ADC to perform an Analog-to-Digital conversion: 1. 2. 3. 4. 5. 6. 7. 8. Configure Port: * Disable pin output driver (Refer to the TRIS register) * Configure pin as analog (Refer to the ANSEL register) Configure the ADC module: * Select ADC conversion clock * Configure voltage reference * Select ADC input channel * Turn on ADC module Configure ADC interrupt (optional): * Clear ADC interrupt flag * Enable ADC interrupt * Enable peripheral interrupt * Enable global interrupt(1) Wait the required acquisition time(2). Start conversion by setting the GO/DONE bit. Wait for ADC conversion to complete by one of the following: * Polling the GO/DONE bit * Waiting for the ADC interrupt (interrupts enabled) Read ADC Result. Clear the ADC interrupt flag (required if interrupt is enabled). A/D CONVERSION ;This code block configures the ADC ;for polling, Vdd and Vss references, Frc ;clock and AN0 input. ; ;Conversion start & polling for completion ; are included. ; BANKSEL ADCON1 ; MOVLW B'11110000' ;Right justify, Frc ;clock MOVWF ADCON1 ;Vdd and Vss Vref+ BANKSEL TRISA ; BSF TRISA,0 ;Set RA0 to input BANKSEL ANSEL ; BSF ANSEL,0 ;Set RA0 to analog BANKSEL ADCON0 ; MOVLW B'00000001' ;Select channel AN0 MOVWF ADCON0 ;Turn ADC On CALL SampleTime ;Acquisiton delay BSF ADCON0,ADGO ;Start conversion BTFSC ADCON0,ADGO ;Is conversion done? GOTO $-1 ;No, test again BANKSEL ADRESH ; MOVF ADRESH,W ;Read upper 2 bits MOVWF RESULTHI ;store in GPR space BANKSEL ADRESL ; MOVF ADRESL,W ;Read lower 8 bits MOVWF RESULTLO ;Store in GPR space Note 1: The global interrupt can be disabled if the user is attempting to wake-up from Sleep and resume in-line code execution. 2: Refer to Section 15.3 "A/D Acquisition Requirements". DS41609A-page 140 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 15.2.7 ADC REGISTER DEFINITIONS The following registers are used to control the operation of the ADC. REGISTER 15-1: U-0 ADCON0: A/D CONTROL REGISTER 0 R/W-0/0 R/W-0/0 -- R/W-0/0 R/W-0/0 CHS<4:0> R/W-0/0 R/W-0/0 R/W-0/0 GO/DONE ADON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 Unimplemented: Read as `0' bit 6-2 CHS<4:0>: Analog Channel Select bits 00000 = AN0 00001 = AN1 00010 = AN2 00011 = AN3 00100 = AN4 00101 = AN5 00110 = AN6 00111 = AN7 01000 = AN8 01001 = AN9 01010 = AN10 01011 = AN11 01100 = Reserved. No channel connected. * * * 11100 = Reserved. No channel connected. 11101 = Temperature Indicator(1) 11110 = DAC (Digital-to-Analog Converter)(2) 11111 = FVR (Fixed Voltage Reference) Buffer 1 Output(3) bit 1 GO/DONE: A/D Conversion Status bit 1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle. This bit is automatically cleared by hardware when the A/D conversion has completed. 0 = A/D conversion completed/not in progress bit 0 ADON: ADC Enable bit 1 = ADC is enabled 0 = ADC is disabled and consumes no operating current Note 1: 2: 3: See Section 14.0 "Temperature Indicator Module" for more information. See Section 16.0 "Digital-to-Analog Converter (DAC) Module" for more information. See Section 13.0 "Fixed Voltage Reference (FVR)" for more information. 2011 Microchip Technology Inc. Preliminary DS41609A-page 141 PIC16(L)F1508/9 REGISTER 15-2: R/W-0/0 ADCON1: A/D CONTROL REGISTER 1 R/W-0/0 ADFM R/W-0/0 R/W-0/0 ADCS<2:0> U-0 U-0 -- -- R/W-0/0 R/W-0/0 ADPREF<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 ADFM: A/D Result Format Select bit 1 = Right justified. Six Most Significant bits of ADRESH are set to `0' when the conversion result is loaded. 0 = Left justified. Six Least Significant bits of ADRESL are set to `0' when the conversion result is loaded. bit 6-4 ADCS<2:0>: A/D Conversion Clock Select bits 000 = FOSC/2 001 = FOSC/8 010 = FOSC/32 011 = FRC (clock supplied from a dedicated RC oscillator) 100 = FOSC/4 101 = FOSC/16 110 = FOSC/64 111 = FRC (clock supplied from a dedicated RC oscillator) bit 3-2 Unimplemented: Read as `0' bit 1-0 ADPREF<1:0>: A/D Positive Voltage Reference Configuration bits 00 = VREF+ is connected to VDD 01 = Reserved 10 = VREF+ is connected to external VREF+ pin(1) 11 = Reserved Note 1: When selecting the VREF+ pin as the source of the positive reference, be aware that a minimum voltage specification exists. See Section 29.0 "Electrical Specifications" for details. DS41609A-page 142 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 REGISTER 15-3: R/W-0/0 ADCON2: A/D CONTROL REGISTER 2 R/W-0/0 R/W-0/0 R/W-0/0 TRIGSEL<3:0> U-0 U-0 U-0 U-0 -- -- -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-4 TRIGSEL<3:0>: Auto-Conversion Trigger Selection bits(1) 0000 = No auto-conversion trigger selected 0001 = Reserved 0010 = Reserved 0011 = TMR0 Overflow(2) 0100 = TMR1 Overflow(2) 0101 = TMR2 Match to PR2(2) 0110 = SYNCC1OUT 0111 = SYNCC2OUT 1000 = CLC1 1001 = CLC2 1010 = CLC3 1011 = CLC4 1100 = Reserved 1101 = Reserved 1110 = Reserved 1111 = Reserved bit 3-0 Unimplemented: Read as `0' Note 1: 2: This is a rising edge sensitive input for all sources. Signal also sets its corresponding interrupt flag. 2011 Microchip Technology Inc. Preliminary DS41609A-page 143 PIC16(L)F1508/9 REGISTER 15-4: R/W-x/u ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u ADRES<9:2> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 ADRES<9:2>: ADC Result Register bits Upper 8 bits of 10-bit conversion result REGISTER 15-5: R/W-x/u ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0 R/W-x/u ADRES<1:0> R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u -- -- -- -- -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-6 ADRES<1:0>: ADC Result Register bits Lower 2 bits of 10-bit conversion result bit 5-0 Reserved: Do not use. DS41609A-page 144 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 REGISTER 15-6: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u -- -- -- -- -- -- R/W-x/u R/W-x/u ADRES<9:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-2 Reserved: Do not use. bit 1-0 ADRES<9:8>: ADC Result Register bits Upper 2 bits of 10-bit conversion result REGISTER 15-7: R/W-x/u ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u ADRES<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 ADRES<7:0>: ADC Result Register bits Lower 8 bits of 10-bit conversion result 2011 Microchip Technology Inc. Preliminary DS41609A-page 145 PIC16(L)F1508/9 15.3 A/D Acquisition Requirements For the ADC to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The Analog Input model is shown in Figure 15-4. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), refer to Figure 15-4. The maximum recommended impedance for analog sources is 10 k. As the EQUATION 15-1: Assumptions: source impedance is decreased, the acquisition time may be decreased. After the analog input channel is selected (or changed), an A/D acquisition must be done before the conversion can be started. To calculate the minimum acquisition time, Equation 15-1 may be used. This equation assumes that 1/2 LSb error is used (1,024 steps for the ADC). The 1/2 LSb error is the maximum error allowed for the ADC to meet its specified resolution. ACQUISITION TIME EXAMPLE Temperature = 50C and external impedance of 10k 5.0V V DD T ACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient = T AMP + T C + T COFF = 2s + T C + Temperature - 25C 0.05s/C The value for TC can be approximated with the following equations: 1 = V CHOLD V AP P LI ED 1 - -------------------------n+1 2 -1 ;[1] VCHOLD charged to within 1/2 lsb -TC ---------- RC V AP P LI ED 1 - e = V CHOLD ;[2] VCHOLD charge response to VAPPLIED - Tc --------- 1 RC ;combining [1] and [2] V AP P LI ED 1 - e = V A PP LIE D 1 - -------------------------n+1 2 -1 Note: Where n = number of bits of the ADC. Solving for TC: T C = - C HOLD R IC + R SS + R S ln(1/2047) = - 12.5pF 1k + 7k + 10k ln(0.0004885) = 1.12 s Therefore: T A CQ = 5s + 1.12 s + 50C- 25C 0.05 s/C = 7.37s Note 1: The reference voltage (VREF+) has no effect on the equation, since it cancels itself out. 2: The charge holding capacitor (CHOLD) is not discharged after each conversion. 3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin leakage specification. DS41609A-page 146 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 FIGURE 15-4: ANALOG INPUT MODEL VDD Analog Input pin Rs VT 0.6V CPIN 5 pF VA RIC 1k Sampling Switch SS Rss I LEAKAGE(1) VT 0.6V CHOLD = 10 pF VREF- Legend: CHOLD CPIN 6V 5V VDD 4V 3V 2V = Sample/Hold Capacitance = Input Capacitance RSS I LEAKAGE = Leakage current at the pin due to various junctions RIC = Interconnect Resistance RSS = Resistance of Sampling Switch SS = Sampling Switch VT = Threshold Voltage Note 1: FIGURE 15-5: 5 6 7 8 9 10 11 Sampling Switch (k) Refer to Section 29.0 "Electrical Specifications". ADC TRANSFER FUNCTION Full-Scale Range 3FFh 3FEh ADC Output Code 3FDh 3FCh 3FBh 03h 02h 01h 00h Analog Input Voltage 0.5 LSB VREF- 2011 Microchip Technology Inc. 1.5 LSB Zero-Scale Transition Full-Scale Transition Preliminary VREF+ DS41609A-page 147 PIC16(L)F1508/9 TABLE 15-2: Name SUMMARY OF REGISTERS ASSOCIATED WITH ADC Bit 7 ADCON0 -- ADCON1 ADFM ADCON2 Bit 6 Bit 5 Bit 4 TRIGSEL<3:0> A/D Result Register High ADRESL A/D Result Register Low -- Bit 2 -- -- ADPREF<1:0> -- -- -- CHS<4:0> ADCS<2:0> ADRESH ANSELA Bit 3 Bit 1 Bit 0 GO/DONE ADON -- Register on Page 141 142 143 144, 145 144, 145 -- -- ANSA4 -- ANSA2 ANSA1 ANSA0 115 ANSELB -- -- ANSB5 ANSB4 -- -- -- -- 119 ANSELC ANSC7 ANSC6 -- -- ANSC3 ANSC2 ANSC1 ANSC0 123 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 78 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE -- TMR2IE TMR1IE 79 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF -- TMR2IF TMR1IF 82 -- -- TRISA5 TRISA4 --(1) TRISA2 TRISA1 TRISA0 114 INTCON TRISA TRISB TRISB7 TRISB6 TRISB5 TRISB4 -- -- -- -- 118 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 122 FVREN FVRRDY TSEN TSRNG FVRCON Legend: Note 1: CDAFVR<1:0> ADFVR<1:0> 132 x = unknown, u = unchanged, -- = unimplemented read as `0', q = value depends on condition. Shaded cells are not used for ADC module. Unimplemented, read as `1'. DS41609A-page 148 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 16.0 DIGITAL-TO-ANALOG CONVERTER (DAC) MODULE The Digital-to-Analog Converter supplies a variable voltage reference, ratiometric with the input source, with 32 selectable output levels. The input of the DAC can be connected to: 16.1 Output Voltage Selection The DAC has 32 voltage level ranges. The 32 levels are set with the DACR<4:0> bits of the DACCON1 register. The DAC output voltage is determined by the following equations: * External VREF+ pin * VDD supply voltage The output of the DAC can be configured to supply a reference voltage to the following: * * * * Comparator positive input ADC input channel DACOUT1 pin DACOUT2 pin The Digital-to-Analog Converter (DAC) can be enabled by setting the DACEN bit of the DACCON0 register. EQUATION 16-1: DAC OUTPUT VOLTAGE IF DACEN = 1 DACR 4:0 VOUT = VSOURCE+ - VSOURCE- ----------------------------+ VSOURCE5 2 IF DACEN = 0 and DACLPS = 1 and DACR[4:0] = 11111 V OUT = V SOURCE + IF DACEN = 0 and DACLPS = 0 and DACR[4:0] = 00000 V OUT = V SOURCE - VSOURCE+ = VDD, VREF, or FVR BUFFER 2 VSOURCE- = VSS 16.2 Ratiometric Output Level 16.3 The DAC output value is derived using a resistor ladder with each end of the ladder tied to a positive and negative voltage reference input source. If the voltage of either input source fluctuates, a similar fluctuation will result in the DAC output value. The value of the individual resistors within the ladder can be found in Section 29.0 "Electrical Specifications". DAC Voltage Reference Output The DAC voltage can be output to the DACOUT1 and DACOUT2 pins by setting the respective DACOE1 and DACOE2 pins of the DACCON0 register. Selecting the DAC reference voltage for output on either DACOUTx pin automatically overrides the digital output buffer and digital input threshold detector functions of that pin. Reading the DACOUTx pin when it has been configured for DAC reference voltage output will always return a `0'. Due to the limited current drive capability, a buffer must be used on the DAC voltage reference output for external connections to either DACOUTx pin. Figure 16-2 shows an example buffering technique. 2011 Microchip Technology Inc. Preliminary DS41609A-page 149 PIC16(L)F1508/9 FIGURE 16-1: DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM Digital-to-Analog Converter (DAC) VSOURCE+ VDD DACR<4:0> 5 VREF+ R R DACPSS R DACEN R 32 Steps R 32-to-1 MUX R DAC (To Comparator and ADC Module) R DACOUT1 R DACOE1 VSOURCE- DACOUT2 DACOE2 FIGURE 16-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE PIC(R) MCU DAC Module R Voltage Reference Output Impedance DS41609A-page 150 DACOUTX Preliminary + - Buffered DAC Output 2011 Microchip Technology Inc. PIC16(L)F1508/9 16.4 Operation During Sleep When the device wakes up from Sleep through an interrupt or a Watchdog Timer time-out, the contents of the DACCON0 register are not affected. To minimize current consumption in Sleep mode, the voltage reference should be disabled. 16.5 Effects of a Reset A device Reset affects the following: * DAC is disabled. * DAC output voltage is removed from the DACOUT pin. * The DACR<4:0> range select bits are cleared. 2011 Microchip Technology Inc. Preliminary DS41609A-page 151 PIC16(L)F1508/9 16.6 DAC Control Registers REGISTER 16-1: DACCON0: VOLTAGE REFERENCE CONTROL REGISTER 0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 U-0 U-0 DACEN -- DACOE1 DACOE2 -- DACPSS -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 DACEN: DAC Enable bit 1 = DAC is enabled 0 = DAC is disabled bit 6 Unimplemented: Read as `0' bit 5 DACOE1: DAC Voltage Output Enable bit 1 = DAC voltage level is also an output on the DACOUT1 pin 0 = DAC voltage level is disconnected from the DACOUT1 pin bit 4 DACOE2: DAC Voltage Output Enable bit 1 = DAC voltage level is also an output on the DACOUT2 pin 0 = DAC voltage level is disconnected from the DACOUT2 pin bit 3 Unimplemented: Read as `0' bit 2 DACPSS: DAC Positive Source Select bit 1= VREF+ pin 0= VDD bit 1-0 Unimplemented: Read as `0' REGISTER 16-2: DACCON1: VOLTAGE REFERENCE CONTROL REGISTER 1 U-0 U-0 U-0 -- -- -- R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 DACR<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-5 Unimplemented: Read as `0' bit 4-0 DACR<4:0>: DAC Voltage Output Select bits TABLE 16-1: Name SUMMARY OF REGISTERS ASSOCIATED WITH THE DAC MODULE Bit 7 Bit 6 FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> DACCON0 DACEN -- DACOE1 DACOE2 -- -- -- -- DACCON1 Legend: Bit 5 Bit 4 Bit 3 Bit 2 DACPSS Bit 1 Bit 0 ADFVR<1:0> -- DACR<4:0> -- Register on page 161 152 152 -- = Unimplemented location, read as `0'. Shaded cells are not used with the DAC module. DS41609A-page 152 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 17.0 COMPARATOR MODULE FIGURE 17-1: Comparators are used to interface analog circuits to a digital circuit by comparing two analog voltages and providing a digital indication of their relative magnitudes. Comparators are very useful mixed signal building blocks because they provide analog functionality independent of program execution. The analog comparator module includes the following features: * * * * * * * * * Independent comparator control Programmable input selection Comparator output is available internally/externally Programmable output polarity Interrupt-on-change Wake-up from Sleep Programmable Speed/Power optimization PWM shutdown Programmable and Fixed Voltage Reference 17.1 SINGLE COMPARATOR VIN+ + VIN- - Output VINVIN+ Output Note: Comparator Overview The black areas of the output of the comparator represents the uncertainty due to input offsets and response time. A single comparator is shown in Figure 17-1 along with the relationship between the analog input levels and the digital output. When the analog voltage at VIN+ is less than the analog voltage at VIN-, the output of the comparator is a digital low level. When the analog voltage at VIN+ is greater than the analog voltage at VIN-, the output of the comparator is a digital high level. 2011 Microchip Technology Inc. Preliminary DS41609A-page 153 PIC16(L)F1508/9 FIGURE 17-2: COMPARATOR MODULES SIMPLIFIED BLOCK DIAGRAM CxNCH<2:0> CxON(1) 3 C12IN0- 0 C12IN1C12IN2- 1 MUX 2 (2) C12IN3- 3 FVR Buffer2 4 det Set CxIF 0 MUX 1 (2) DAC FVR Buffer2 CxINTN Interrupt det CXPOL CxVN D Cx CxVP CXIN+ CxINTP Interrupt CXOUT MCXOUT Q + EN Q1 CxHYS CxSP async_CxOUT 2 3 CXSYNC CxON CXPCH<1:0> To CWG CXOE TRIS bit CXOUT 0 2 D Q 1 (from Timer1) T1CLK SYNCCXOUT Note 1: 2: When CxON = 0, the Comparator will produce a `0' at the output When CxON = 0, all multiplexer inputs are disconnected. DS41609A-page 154 Preliminary To Timer1, CLCx, ADC 2011 Microchip Technology Inc. PIC16(L)F1508/9 17.2 Comparator Control 17.2.3 Each comparator has 2 control registers: CMxCON0 and CMxCON1. The CMxCON0 registers (see Register 17-1) contain Control and Status bits for the following: * * * * * * Enable Output selection Output polarity Speed/Power selection Hysteresis enable Output synchronization Inverting the output of the comparator is functionally equivalent to swapping the comparator inputs. The polarity of the comparator output can be inverted by setting the CxPOL bit of the CMxCON0 register. Clearing the CxPOL bit results in a non-inverted output. Table 17-1 shows the output state versus input conditions, including polarity control. TABLE 17-1: Interrupt enable Interrupt edge polarity Positive input channel selection Negative input channel selection 17.2.1 CxPOL CxOUT CxVN > CxVP 0 0 CxVN < CxVP 0 1 CxVN > CxVP 1 1 CxVN < CxVP 1 0 17.2.4 COMPARATOR ENABLE Setting the CxON bit of the CMxCON0 register enables the comparator for operation. Clearing the CxON bit disables the comparator resulting in minimum current consumption. 17.2.2 COMPARATOR OUTPUT SELECTION COMPARATOR OUTPUT STATE VS. INPUT CONDITIONS Input Condition The CMxCON1 registers (see Register 17-2) contain Control bits for the following: * * * * COMPARATOR OUTPUT POLARITY COMPARATOR SPEED/POWER SELECTION The trade-off between speed or power can be optimized during program execution with the CxSP control bit. The default state for this bit is `1' which selects the normal speed mode. Device power consumption can be optimized at the cost of slower comparator propagation delay by clearing the CxSP bit to `0'. The output of the comparator can be monitored by reading either the CxOUT bit of the CMxCON0 register or the MCxOUT bit of the CMOUT register. In order to make the output available for an external connection, the following conditions must be true: * CxOE bit of the CMxCON0 register must be set * Corresponding TRIS bit must be cleared * CxON bit of the CMxCON0 register must be set Note 1: The CxOE bit of the CMxCON0 register overrides the PORT data latch. Setting the CxON bit of the CMxCON0 register has no impact on the port override. 2: The internal output of the comparator is latched with each instruction cycle. Unless otherwise specified, external outputs are not latched. 2011 Microchip Technology Inc. Preliminary DS41609A-page 155 PIC16(L)F1508/9 17.3 Comparator Hysteresis 17.5 A selectable amount of separation voltage can be added to the input pins of each comparator to provide a hysteresis function to the overall operation. Hysteresis is enabled by setting the CxHYS bit of the CMxCON0 register. Comparator Interrupt An interrupt can be generated upon a change in the output value of the comparator for each comparator, a rising edge detector and a falling edge detector are present. See Section 29.0 "Electrical Specifications" for more information. When either edge detector is triggered and its associated enable bit is set (CxINTP and/or CxINTN bits of the CMxCON1 register), the Corresponding Interrupt Flag bit (CxIF bit of the PIR2 register) will be set. 17.4 To enable the interrupt, you must set the following bits: Timer1 Gate Operation The output resulting from a comparator operation can be used as a source for gate control of Timer1. See Section 19.5 "Timer1 Gate" for more information. This feature is useful for timing the duration or interval of an analog event. It is recommended that the comparator output be synchronized to Timer1. This ensures that Timer1 does not increment while a change in the comparator is occurring. 17.4.1 COMPARATOR OUTPUT SYNCHRONIZATION The output from either comparator, C1 or C2, can be synchronized with Timer1 by setting the CxSYNC bit of the CMxCON0 register. Once enabled, the comparator output is latched on the falling edge of the Timer1 source clock. If a prescaler is used with Timer1, the comparator output is latched after the prescaling function. To prevent a race condition, the comparator output is latched on the falling edge of the Timer1 clock source and Timer1 increments on the rising edge of its clock source. See the Comparator Block Diagram (Figure 17-2) and the Timer1 Block Diagram (Figure 19-1) for more information. * CxON, CxPOL and CxSP bits of the CMxCON0 register * CxIE bit of the PIE2 register * CxINTP bit of the CMxCON1 register (for a rising edge detection) * CxINTN bit of the CMxCON1 register (for a falling edge detection) * PEIE and GIE bits of the INTCON register The associated interrupt flag bit, CxIF bit of the PIR2 register, must be cleared in software. If another edge is detected while this flag is being cleared, the flag will still be set at the end of the sequence. Note: 17.6 Although a comparator is disabled, an interrupt can be generated by changing the output polarity with the CxPOL bit of the CMxCON0 register, or by switching the comparator on or off with the CxON bit of the CMxCON0 register. Comparator Positive Input Selection Configuring the CxPCH<1:0> bits of the CMxCON1 register directs an internal voltage reference or an analog pin to the non-inverting input of the comparator: * * * * CxIN+ analog pin DAC FVR (Fixed Voltage Reference) VSS (Ground) See Section 13.0 "Fixed Voltage Reference (FVR)" for more information on the Fixed Voltage Reference module. See Section 16.0 "Digital-to-Analog Converter (DAC) Module" for more information on the DAC input signal. Any time the comparator is disabled (CxON = 0), all comparator inputs are disabled. DS41609A-page 156 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 17.7 Comparator Negative Input Selection 17.10 Analog Input Connection Considerations The CxNCH<2:0> bits of the CMxCON0 register direct one of the input sources to the comparator inverting input. Note: 17.8 To use CxIN+ and CxINx- pins as analog input, the appropriate bits must be set in the ANSEL register and the corresponding TRIS bits must also be set to disable the output drivers. Comparator Response Time The comparator output is indeterminate for a period of time after the change of an input source or the selection of a new reference voltage. This period is referred to as the response time. The response time of the comparator differs from the settling time of the voltage reference. Therefore, both of these times must be considered when determining the total response time to a comparator input change. See the Comparator and Voltage Reference Specifications in Section 29.0 "Electrical Specifications" for more details. 17.9 A simplified circuit for an analog input is shown in Figure 17-3. Since the analog input pins share their connection with a digital input, they have reverse biased ESD protection diodes to VDD and VSS. The analog input, therefore, must be between VSS and VDD. If the input voltage deviates from this range by more than 0.6V in either direction, one of the diodes is forward biased and a latch-up may occur. A maximum source impedance of 10 k is recommended for the analog sources. Also, any external component connected to an analog input pin, such as a capacitor or a Zener diode, should have very little leakage current to minimize inaccuracies introduced. Note 1: When reading a PORT register, all pins configured as analog inputs will read as a `0'. Pins configured as digital inputs will convert as an analog input, according to the input specification. Interaction with ECCP Logic 2: Analog levels on any pin defined as a digital input, may cause the input buffer to consume more current than is specified. The C1 and C2 comparators can be used as general purpose comparators. Their outputs can be brought out to the C1OUT and C2OUT pins. When the ECCP Auto-Shutdown is active it can use one or both comparator signals. If auto-restart is also enabled, the comparators can be configured as a closed loop analog feedback to the ECCP, thereby, creating an analog controlled PWM. Note: When the comparator module is first initialized the output state is unknown. Upon initialization, the user should verify the output state of the comparator prior to relying on the result, primarily when using the result in connection with other peripheral features, such as the ECCP Auto-Shutdown mode. 2011 Microchip Technology Inc. Preliminary DS41609A-page 157 PIC16(L)F1508/9 FIGURE 17-3: ANALOG INPUT MODEL VDD Rs < 10K Analog Input pin VT 0.6V RIC To Comparator VA CPIN 5 pF VT 0.6V ILEAKAGE(1) Vss Legend: CPIN = Input Capacitance ILEAKAGE = Leakage Current at the pin due to various junctions = Interconnect Resistance RIC = Source Impedance RS = Analog Voltage VA = Threshold Voltage VT Note 1: DS41609A-page 158 See Section 29.0 "Electrical Specifications". Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 REGISTER 17-1: CMxCON0: COMPARATOR Cx CONTROL REGISTER 0 R/W-0/0 R-0/0 R/W-0/0 R/W-0/0 U-0 R/W-1/1 R/W-0/0 R/W-0/0 CxON CxOUT CxOE CxPOL -- CxSP CxHYS CxSYNC bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 CxON: Comparator Enable bit 1 = Comparator is enabled and consumes no active power 0 = Comparator is disabled bit 6 CxOUT: Comparator Output bit If CxPOL = 1 (inverted polarity): 1 = CxVP < CxVN 0 = CxVP > CxVN If CxPOL = 0 (non-inverted polarity): 1 = CxVP > CxVN 0 = CxVP < CxVN bit 5 CxOE: Comparator Output Enable bit 1 = CxOUT is present on the CxOUT pin. Requires that the associated TRIS bit be cleared to actually drive the pin. Not affected by CxON. 0 = CxOUT is internal only bit 4 CxPOL: Comparator Output Polarity Select bit 1 = Comparator output is inverted 0 = Comparator output is not inverted bit 3 Unimplemented: Read as `0' bit 2 CxSP: Comparator Speed/Power Select bit 1 = Comparator operates in normal power, higher speed mode 0 = Comparator operates in low-power, low-speed mode bit 1 CxHYS: Comparator Hysteresis Enable bit 1 = Comparator hysteresis enabled 0 = Comparator hysteresis disabled bit 0 CxSYNC: Comparator Output Synchronous Mode bit 1 = Comparator output to Timer1 and I/O pin is synchronous to changes on Timer1 clock source. Output updated on the falling edge of Timer1 clock source. 0 = Comparator output to Timer1 and I/O pin is asynchronous 2011 Microchip Technology Inc. Preliminary DS41609A-page 159 PIC16(L)F1508/9 REGISTER 17-2: CMxCON1: COMPARATOR Cx CONTROL REGISTER 1 R/W-0/0 R/W-0/0 CxINTP CxINTN R/W-0/0 R/W-0/0 CxPCH<1:0> U-0 R/W-0/0 R/W-0/0 R/W-0/0 CxNCH<2:0> -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 CxINTP: Comparator Interrupt on Positive Going Edge Enable bits 1 = The CxIF interrupt flag will be set upon a positive going edge of the CxOUT bit 0 = No interrupt flag will be set on a positive going edge of the CxOUT bit bit 6 CxINTN: Comparator Interrupt on Negative Going Edge Enable bits 1 = The CxIF interrupt flag will be set upon a negative going edge of the CxOUT bit 0 = No interrupt flag will be set on a negative going edge of the CxOUT bit bit 5-4 CxPCH<1:0>: Comparator Positive Input Channel Select bits 11 = CxVP connects to VSS 10 = CxVP connects to FVR Voltage Reference 01 = CxVP connects to DAC Voltage Reference 00 = CxVP connects to CxIN+ pin bit 3 Unimplemented: Read as `0' bit 2-0 CxNCH<2:0>: Comparator Negative Input Channel Select bits 111 = Reserved 110 = Reserved 101 = Reserved 100 = CxVN connects to FVR Voltage reference 011 = CxVN connects to C12IN3- pin 010 = CxVN connects to C12IN2- pin 001 = CxVN connects to C12IN1- pin 000 = CxVN connects to C12IN0- pin REGISTER 17-3: U-0 CMOUT: COMPARATOR OUTPUT REGISTER U-0 -- -- U-0 -- U-0 -- U-0 -- U-0 R-0/0 R-0/0 -- MC2OUT MC1OUT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-2 Unimplemented: Read as `0' bit 1 MC2OUT: Mirror Copy of C2OUT bit bit 0 MC1OUT: Mirror Copy of C1OUT bit DS41609A-page 160 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 TABLE 17-2: SUMMARY OF REGISTERS ASSOCIATED WITH COMPARATOR MODULE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSELA -- -- -- ANSA4 -- ANSA2 ANSA1 ANSA0 115 ANSELC ANSC7 ANSC6 -- -- ANSC3 ANSC2 ANSC1 ANSC0 123 CM1CON0 C1ON C1OUT C1OE C1POL -- C1SP C1HYS C1SYNC 159 C2OE C2POL -- C2SP C2HYS C2SYNC 159 Name CM2CON0 C2ON C2OUT CM1CON1 C1NTP C1INTN CM2CON1 C2NTP C2INTN -- -- -- -- -- -- MC2OUT MC1OUT 160 DACCON0 DACEN -- DACOE1 DACOE2 -- DACPSS -- -- 152 DACCON1 -- -- -- FVRCON FVREN FVRRDY TSEN TSRNG INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 78 PIE2 OSFIE C2IE C1IE -- BCL1IE NCO1IE -- -- 80 PIR2 CMOUT C1PCH<1:0> -- C2PCH<1:0> -- C1NCH<2:0> 160 C2NCH<2:0> 160 DACR<4:0> CDAFVR<1:0> 152 ADFVR<1:0> 132 OSFIF C2IF C1IF -- BCL1IF NCO1IF -- -- 83 PORTA -- -- RA5 RA4 RA3 RA2 RA1 RA0 114 PORTC 122 RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 LATA -- -- LATA5 LATA4 -- LATA2 LATA1 LATA0 115 LATC LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 122 TRISA -- -- TRISA5 TRISA4 --(1) TRISA2 TRISA1 TRISA0 114 TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 122 TRISC Legend: Note 1: -- = unimplemented location, read as `0'. Shaded cells are unused by the comparator module. Unimplemented, read as `1'. 2011 Microchip Technology Inc. Preliminary DS41609A-page 161 PIC16(L)F1508/9 NOTES: DS41609A-page 162 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 18.0 TIMER0 MODULE 18.1.2 8-BIT COUNTER MODE The Timer0 module is an 8-bit timer/counter with the following features: In 8-Bit Counter mode, the Timer0 module will increment on every rising or falling edge of the T0CKI pin. * * * * * * 8-Bit Counter mode using the T0CKI pin is selected by setting the TMR0CS bit in the OPTION_REG register to `1'. 8-bit timer/counter register (TMR0) 8-bit prescaler (independent of Watchdog Timer) Programmable internal or external clock source Programmable external clock edge selection Interrupt on overflow TMR0 can be used to gate Timer1 The rising or falling transition of the incrementing edge for either input source is determined by the TMR0SE bit in the OPTION_REG register. Figure 18-1 is a block diagram of the Timer0 module. 18.1 Timer0 Operation The Timer0 module can be used as either an 8-bit timer or an 8-bit counter. 18.1.1 8-BIT TIMER MODE The Timer0 module will increment every instruction cycle, if used without a prescaler. 8-Bit Timer mode is selected by clearing the TMR0CS bit of the OPTION_REG register. When TMR0 is written, the increment is inhibited for two instruction cycles immediately following the write. Note: The value written to the TMR0 register can be adjusted, in order to account for the two instruction cycle delay when TMR0 is written. FIGURE 18-1: BLOCK DIAGRAM OF THE TIMER0 FOSC/4 Data Bus 0 T0CKI 1 1 8 Sync 2 TCY TMR0 0 TMR0SE TMR0CS 8-bit Prescaler PSA Set Flag bit TMR0IF on Overflow Overflow to Timer1 8 PS<2:0> 2011 Microchip Technology Inc. Preliminary DS41609A-page 163 PIC16(L)F1508/9 18.1.3 SOFTWARE PROGRAMMABLE PRESCALER A software programmable prescaler is available for exclusive use with Timer0. The prescaler is enabled by clearing the PSA bit of the OPTION_REG register. Note: The Watchdog Timer (WDT) uses its own independent prescaler. There are 8 prescaler options for the Timer0 module ranging from 1:2 to 1:256. The prescale values are selectable via the PS<2:0> bits of the OPTION_REG register. In order to have a 1:1 prescaler value for the Timer0 module, the prescaler must be disabled by setting the PSA bit of the OPTION_REG register. The prescaler is not readable or writable. All instructions writing to the TMR0 register will clear the prescaler. 18.1.4 TIMER0 INTERRUPT Timer0 will generate an interrupt when the TMR0 register overflows from FFh to 00h. The TMR0IF interrupt flag bit of the INTCON register is set every time the TMR0 register overflows, regardless of whether or not the Timer0 interrupt is enabled. The TMR0IF bit can only be cleared in software. The Timer0 interrupt enable is the TMR0IE bit of the INTCON register. Note: 18.1.5 The Timer0 interrupt cannot wake the processor from Sleep since the timer is frozen during Sleep. 8-BIT COUNTER MODE SYNCHRONIZATION When in 8-Bit Counter mode, the incrementing edge on the T0CKI pin must be synchronized to the instruction clock. Synchronization can be accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the instruction clock. The high and low periods of the external clocking source must meet the timing requirements as shown in Section 29.0 "Electrical Specifications". 18.1.6 OPERATION DURING SLEEP Timer0 cannot operate while the processor is in Sleep mode. The contents of the TMR0 register will remain unchanged while the processor is in Sleep mode. DS41609A-page 164 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 18.2 Option and Timer0 Control Register REGISTER 18-1: OPTION_REG: OPTION REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 WPUEN INTEDG TMR0CS TMR0SE PSA R/W-1/1 R/W-1/1 R/W-1/1 PS<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 WPUEN: Weak Pull-Up Enable bit 1 = All weak pull-ups are disabled (except MCLR, if it is enabled) 0 = Weak pull-ups are enabled by individual WPUx latch values bit 6 INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of INT pin 0 = Interrupt on falling edge of INT pin bit 5 TMR0CS: Timer0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (FOSC/4) bit 4 TMR0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin bit 3 PSA: Prescaler Assignment bit 1 = Prescaler is not assigned to the Timer0 module 0 = Prescaler is assigned to the Timer0 module bit 2-0 PS<2:0>: Prescaler Rate Select bits TABLE 18-1: Name Bit Value Timer0 Rate 000 001 010 011 100 101 110 111 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0 Bit 7 Bit 6 ADCON2 INTCON TMR0 Legend: * Note 1: Bit 4 TRIGSEL<3:0> OPTION_REG TRISA Bit 5 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page -- -- -- -- 143 TMR0IF INTF IOCIF GIE PEIE TMR0IE INTE IOCIE WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0> Holding Register for the 8-bit Timer0 Count -- -- TRISA5 TRISA4 78 165 163* --(1) TRISA2 TRISA1 TRISA0 114 -- = Unimplemented location, read as `0'. Shaded cells are not used by the Timer0 module. Page provides register information. Unimplemented, read as `1'. 2011 Microchip Technology Inc. Preliminary DS41609A-page 165 PIC16(L)F1508/9 NOTES: DS41609A-page 166 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 19.0 TIMER1 MODULE WITH GATE CONTROL * Gate Single-Pulse mode * Gate Value Status * Gate Event Interrupt The Timer1 module is a 16-bit timer/counter with the following features: Figure 19-1 is a block diagram of the Timer1 module. * * * * * * * 16-bit timer/counter register pair (TMR1H:TMR1L) Programmable internal or external clock source 2-bit prescaler Optionally synchronized comparator out Multiple Timer1 gate (count enable) sources Interrupt on overflow Wake-up on overflow (external clock, Asynchronous mode only) * Special Event Trigger * Selectable Gate Source Polarity * Gate Toggle mode FIGURE 19-1: TIMER1 BLOCK DIAGRAM T1GSS<1:0> T1GSPM 00 T1G From Timer0 Overflow 01 SYNCC1OUT 10 SYNCC2OUT 11 0 t1g_in Single Pulse TMR1ON T1GTM T1GPOL T1GVAL 0 D Q CK R Q 1 Acq. Control 1 Q1 Data Bus D Q RD T1GCON EN Interrupt T1GGO/DONE Set TMR1GIF det TMR1GE Set flag bit TMR1IF on Overflow TMR1ON TMR1(2) To ADC Auto-Conversion TMR1H TMR1L EN Q D T1CLK Synchronized Clock Input 0 1 TMR1CS<1:0> SOSCO/T1CKI Secondary Oscillator SOSCI T1SYNC OUT LFINTOSC 11 1 Synchronize(3) Prescaler 1, 2, 4, 8 det 10 EN 0 T1OSCEN (1) FOSC Internal Clock 01 FOSC/4 Internal Clock 00 2 T1CKPS<1:0> FOSC/2 Internal Clock Sleep input To Clock Switching Modules Note 1: ST Buffer is high speed type when using T1CKI. 2: Timer1 register increments on rising edge. 3: Synchronize does not operate while in Sleep. 2011 Microchip Technology Inc. Preliminary DS41609A-page 167 PIC16(L)F1508/9 19.1 Timer1 Operation 19.2 The Timer1 module is a 16-bit incrementing counter which is accessed through the TMR1H:TMR1L register pair. Writes to TMR1H or TMR1L directly update the counter. When used with an internal clock source, the module is a timer and increments on every instruction cycle. When used with an external clock source, the module can be used as either a timer or counter and increments on every selected edge of the external source. Timer1 is enabled by configuring the TMR1ON and TMR1GE bits in the T1CON and T1GCON registers, respectively. Table 19-1 displays the Timer1 enable selections. TABLE 19-1: TIMER1 ENABLE SELECTIONS Clock Source Selection The TMR1CS<1:0> bits of the T1CON register are used to select the clock source for Timer1. Table 19-2 displays the clock source selections. 19.2.1 INTERNAL CLOCK SOURCE When the internal clock source is selected the TMR1H:TMR1L register pair will increment on multiples of FOSC as determined by the Timer1 prescaler. When the FOSC internal clock source is selected, the Timer1 register value will increment by four counts every instruction clock cycle. Due to this condition, a 2 LSB error in resolution will occur when reading the Timer1 value. To utilize the full resolution of Timer1, an asynchronous input signal must be used to gate the Timer1 clock input. The following asynchronous sources may be used: * Asynchronous event on the T1G pin to Timer1 gate Timer1 Operation TMR1ON TMR1GE 0 0 Off 19.2.2 0 1 Off 1 0 Always On When the external clock source is selected, the Timer1 module may work as a timer or a counter. 1 1 Count Enabled EXTERNAL CLOCK SOURCE When enabled to count, Timer1 is incremented on the rising edge of the external clock input T1CKI. The external clock source can be synchronized to the microcontroller system clock or it can run asynchronously. Note: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge after any one or more of the following conditions: * * * * TABLE 19-2: Timer1 enabled after POR Write to TMR1H or TMR1L Timer1 is disabled Timer1 is disabled (TMR1ON = 0) when T1CKI is high then Timer1 is enabled (TMR1ON=1) when T1CKI is low. CLOCK SOURCE SELECTIONS TMR1CS<1:0> T1OSCEN 11 x LFINTOSC 1 Secondary Oscillator Circuit on SOSCI/SOSCO Pins 10 Clock Source 0 External Clocking on T1CKI Pin 01 x System Clock (FOSC) or Oscillator. Circuit on SOSCI/SOSCO 00 x Instruction Clock (FOSC/4) DS41609A-page 168 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 19.3 Timer1 Prescaler Timer1 has four prescaler options allowing 1, 2, 4 or 8 divisions of the clock input. The T1CKPS bits of the T1CON register control the prescale counter. The prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to TMR1H or TMR1L. 19.4 Timer1 Operation in Asynchronous Counter Mode If control bit T1SYNC of the T1CON register is set, the external clock input is not synchronized. The timer increments asynchronously to the internal phase clocks. If the external clock source is selected then the timer will continue to run during Sleep and can generate an interrupt on overflow, which will wake-up the processor. However, special precautions in software are needed to read/write the timer (see Section 19.4.1 "Reading and Writing Timer1 in Asynchronous Counter Mode"). Note: 19.4.1 When switching from synchronous to asynchronous operation, it is possible to skip an increment. When switching from asynchronous to synchronous operation, it is possible to produce an additional increment. When Timer1 Gate Enable mode is enabled, Timer1 will increment on the rising edge of the Timer1 clock source. When Timer1 Gate Enable mode is disabled, no incrementing will occur and Timer1 will hold the current count. See Figure 19-3 for timing details. TABLE 19-3: TIMER1 GATE ENABLE SELECTIONS T1CLK T1GPOL T1G 0 0 Counts 0 1 Holds Count 1 0 Holds Count 1 1 Counts 19.5.2 Timer1 Operation TIMER1 GATE SOURCE SELECTION Timer1 gate source selections are shown in Table 19-4. Source selection is controlled by the T1GSS<1:0> bits of the T1GCON register. The polarity for each available source is also selectable. Polarity selection is controlled by the T1GPOL bit of the T1GCON register. TABLE 19-4: T1GSS READING AND WRITING TIMER1 IN ASYNCHRONOUS COUNTER MODE Reading TMR1H or TMR1L while the timer is running from an external asynchronous clock will ensure a valid read (taken care of in hardware). However, the user should keep in mind that reading the 16-bit timer in two 8-bit values itself, poses certain problems, since the timer may overflow between the reads. TIMER1 GATE SOURCES Timer1 Gate Source 00 Timer1 Gate Pin 01 Overflow of Timer0 (TMR0 increments from FFh to 00h) 10 Comparator 1 Output SYNCC1OUT (optionally synchronized comparator output) 11 Comparator 2 Output SYNCC2OUT (optionally synchronized comparator output) For writes, it is recommended that the user simply stop the timer and write the desired values. A write contention may occur by writing to the timer registers, while the register is incrementing. This may produce an unpredictable value in the TMR1H:TMR1L register pair. 19.5 Timer1 Gate Timer1 can be configured to count freely or the count can be enabled and disabled using Timer1 gate circuitry. This is also referred to as Timer1 Gate Enable. Timer1 gate can also be driven by multiple selectable sources. 19.5.1 TIMER1 GATE ENABLE The Timer1 Gate Enable mode is enabled by setting the TMR1GE bit of the T1GCON register. The polarity of the Timer1 Gate Enable mode is configured using the T1GPOL bit of the T1GCON register. 2011 Microchip Technology Inc. Preliminary DS41609A-page 169 PIC16(L)F1508/9 19.5.2.1 T1G Pin Gate Operation 19.5.5 The T1G pin is one source for Timer1 Gate Control. It can be used to supply an external source to the Timer1 gate circuitry. 19.5.2.2 Timer0 Overflow Gate Operation When Timer0 increments from FFh to 00h, a low-tohigh pulse will automatically be generated and internally supplied to the Timer1 gate circuitry. 19.5.3 TIMER1 GATE TOGGLE MODE When Timer1 Gate Toggle mode is enabled, it is possible to measure the full-cycle length of a Timer1 gate signal, as opposed to the duration of a single level pulse. The Timer1 gate source is routed through a flip-flop that changes state on every incrementing edge of the signal. See Figure 19-4 for timing details. TIMER1 GATE VALUE STATUS When Timer1 Gate Value Status is utilized, it is possible to read the most current level of the gate control value. The value is stored in the T1GVAL bit in the T1GCON register. The T1GVAL bit is valid even when the Timer1 gate is not enabled (TMR1GE bit is cleared). 19.5.6 TIMER1 GATE EVENT INTERRUPT When Timer1 Gate Event Interrupt is enabled, it is possible to generate an interrupt upon the completion of a gate event. When the falling edge of T1GVAL occurs, the TMR1GIF flag bit in the PIR1 register will be set. If the TMR1GIE bit in the PIE1 register is set, then an interrupt will be recognized. The TMR1GIF flag bit operates even when the Timer1 gate is not enabled (TMR1GE bit is cleared). Timer1 Gate Toggle mode is enabled by setting the T1GTM bit of the T1GCON register. When the T1GTM bit is cleared, the flip-flop is cleared and held clear. This is necessary in order to control which edge is measured. Note: 19.5.4 Enabling Toggle mode at the same time as changing the gate polarity may result in indeterminate operation. TIMER1 GATE SINGLE-PULSE MODE When Timer1 Gate Single-Pulse mode is enabled, it is possible to capture a single pulse gate event. Timer1 Gate Single-Pulse mode is first enabled by setting the T1GSPM bit in the T1GCON register. Next, the T1GGO/ DONE bit in the T1GCON register must be set. The Timer1 will be fully enabled on the next incrementing edge. On the next trailing edge of the pulse, the T1GGO/ DONE bit will automatically be cleared. No other gate events will be allowed to increment Timer1 until the T1GGO/DONE bit is once again set in software. See Figure 19-5 for timing details. If the Single Pulse Gate mode is disabled by clearing the T1GSPM bit in the T1GCON register, the T1GGO/DONE bit should also be cleared. Enabling the Toggle mode and the Single-Pulse mode simultaneously will permit both sections to work together. This allows the cycle times on the Timer1 gate source to be measured. See Figure 19-6 for timing details. DS41609A-page 170 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 19.6 Timer1 Interrupt 19.7.1 The Timer1 register pair (TMR1H:TMR1L) increments to FFFFh and rolls over to 0000h. When Timer1 rolls over, the Timer1 interrupt flag bit of the PIR1 register is set. To enable the interrupt on rollover, you must set these bits: * * * * TMR1ON bit of the T1CON register TMR1IE bit of the PIE1 register PEIE bit of the INTCON register GIE bit of the INTCON register ALTERNATE PIN LOCATIONS This module incorporates I/O pins that can be moved to other locations with the use of the alternate pin function register, APFCON. To determine which pins can be moved and what their default locations are upon a Reset, see Section 11.1 "Alternate Pin Function" for more information. The interrupt is cleared by clearing the TMR1IF bit in the Interrupt Service Routine. The TMR1H:TMR1L register pair and the TMR1IF bit should be cleared before enabling interrupts. Note: 19.7 Timer1 Operation During Sleep Timer1 can only operate during Sleep when setup in Asynchronous Counter mode. In this mode, an external crystal or clock source can be used to increment the counter. To set up the timer to wake the device: * * * * * TMR1ON bit of the T1CON register must be set TMR1IE bit of the PIE1 register must be set PEIE bit of the INTCON register must be set T1SYNC bit of the T1CON register must be set TMR1CS bits of the T1CON register must be configured The device will wake-up on an overflow and execute the next instructions. If the GIE bit of the INTCON register is set, the device will call the Interrupt Service Routine. Timer1 oscillator will continue to operate in Sleep regardless of the T1SYNC bit setting. FIGURE 19-2: TIMER1 INCREMENTING EDGE T1CKI = 1 when TMR1 Enabled T1CKI = 0 when TMR1 Enabled Note 1: 2: Arrows indicate counter increments. In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock. 2011 Microchip Technology Inc. Preliminary DS41609A-page 171 PIC16(L)F1508/9 FIGURE 19-3: TIMER1 GATE ENABLE MODE TMR1GE T1GPOL t1g_in T1CKI T1GVAL Timer1 N FIGURE 19-4: N+1 N+2 N+3 N+4 TIMER1 GATE TOGGLE MODE TMR1GE T1GPOL T1GTM t1g_in T1CKI T1GVAL Timer1 DS41609A-page 172 N N+1 N+2 N+3 N+4 Preliminary N+5 N+6 N+7 N+8 2011 Microchip Technology Inc. PIC16(L)F1508/9 FIGURE 19-5: TIMER1 GATE SINGLE-PULSE MODE TMR1GE T1GPOL T1GSPM T1GGO/ Cleared by hardware on falling edge of T1GVAL Set by software DONE Counting enabled on rising edge of T1G t1g_in T1CKI T1GVAL Timer1 TMR1GIF N N+1 Set by hardware on falling edge of T1GVAL Cleared by software 2011 Microchip Technology Inc. N+2 Preliminary Cleared by software DS41609A-page 173 PIC16(L)F1508/9 FIGURE 19-6: TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE TMR1GE T1GPOL T1GSPM T1GTM T1GGO/ Cleared by hardware on falling edge of T1GVAL Set by software DONE Counting enabled on rising edge of T1G t1g_in T1CKI T1GVAL Timer1 TMR1GIF DS41609A-page 174 N Cleared by software N+1 N+2 N+3 Set by hardware on falling edge of T1GVAL Preliminary N+4 Cleared by software 2011 Microchip Technology Inc. PIC16(L)F1508/9 19.8 Timer1 Control Registers REGISTER 19-1: R/W-0/u T1CON: TIMER1 CONTROL REGISTER R/W-0/u TMR1CS<1:0> R/W-0/u R/W-0/u T1CKPS<1:0> R/W-0/u R/W-0/u U-0 R/W-0/u T1OSCEN T1SYNC -- TMR1ON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-6 TMR1CS<1:0>: Timer1 Clock Source Select bits 11 = Timer1 clock source is Capacitive Sensing Oscillator (CAPOSC) 10 = Timer1 clock source is pin or oscillator: If T1OSCEN = 0: External clock from T1CKI pin (on the rising edge) If T1OSCEN = 1: Crystal oscillator on SOSCI/SOSCO pins 01 = Timer1 clock source is system clock (FOSC) 00 = Timer1 clock source is instruction clock (FOSC/4) bit 5-4 T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 3 T1OSCEN: LP Oscillator Enable Control bit 1 = Dedicated Timer1 oscillator circuit enabled 0 = Dedicated Timer1 oscillator circuit disabled bit 2 T1SYNC: Timer1 Synchronization Control bit 1 = Do not synchronize asynchronous clock input 0 = Synchronize asynchronous clock input with system clock (FOSC) bit 1 Unimplemented: Read as `0' bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 and clears Timer1 gate flip-flop 2011 Microchip Technology Inc. Preliminary DS41609A-page 175 PIC16(L)F1508/9 REGISTER 19-2: T1GCON: TIMER1 GATE CONTROL REGISTER R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W/HC-0/u R-x/x TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ DONE T1GVAL R/W-0/u R/W-0/u T1GSS<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared HC = Bit is cleared by hardware bit 7 TMR1GE: Timer1 Gate Enable bit If TMR1ON = 0: This bit is ignored If TMR1ON = 1: 1 = Timer1 counting is controlled by the Timer1 gate function 0 = Timer1 counts regardless of Timer1 gate function bit 6 T1GPOL: Timer1 Gate Polarity bit 1 = Timer1 gate is active-high (Timer1 counts when gate is high) 0 = Timer1 gate is active-low (Timer1 counts when gate is low) bit 5 T1GTM: Timer1 Gate Toggle Mode bit 1 = Timer1 Gate Toggle mode is enabled 0 = Timer1 Gate Toggle mode is disabled and toggle flip-flop is cleared Timer1 gate flip-flop toggles on every rising edge. bit 4 T1GSPM: Timer1 Gate Single-Pulse Mode bit 1 = Timer1 gate Single-Pulse mode is enabled and is controlling Timer1 gate 0 = Timer1 gate Single-Pulse mode is disabled bit 3 T1GGO/DONE: Timer1 Gate Single-Pulse Acquisition Status bit 1 = Timer1 gate single-pulse acquisition is ready, waiting for an edge 0 = Timer1 gate single-pulse acquisition has completed or has not been started bit 2 T1GVAL: Timer1 Gate Current State bit Indicates the current state of the Timer1 gate that could be provided to TMR1H:TMR1L. Unaffected by Timer1 Gate Enable (TMR1GE). bit 0 T1GSS<1:0>: Timer1 Gate Source Select bits 11 = Comparator 2 optionally synchronized output (SYNCC2OUT) 10 = Comparator 1 optionally synchronized output (SYNCC1OUT) 01 = Timer0 overflow output 00 = Timer1 gate pin DS41609A-page 176 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 TABLE 19-5: Name SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1 Bit 7 Bit 6 Bit 5 Bit 4 ANSELA -- -- -- APFCON -- -- -- INTCON PIE1 PIR1 Bit 2 ANSA4 -- ANSA2 ANSA1 ANSA0 115 SSSEL T1GSEL -- CLC1SEL NCO1SEL 112 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 78 ADIE RCIE TXIE SSP1IE -- TMR2IE TMR1IE 79 TMR1GIF ADIF RCIF TXIF SSP1IF -- TMR2IF TMR1IF Holding Register for the Most Significant Byte of the 16-bit TMR1 Count TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Count T1CON T1GCON Legend: * Note 1: Bit 0 TMR1GIE TMR1H TRISA Bit 1 Register on Page Bit 3 -- -- TMR1CS<1:0> TMR1GE T1GPOL TRISA5 TRISA4 T1CKPS<1:0> T1GTM T1GSPM 82 171* 171* --(1) TRISA2 TRISA1 TRISA0 114 T1OSCEN T1SYNC -- TMR1ON 175 T1GGO/ DONE T1GVAL T1GSS<1:0> 176 -- = unimplemented location, read as `0'. Shaded cells are not used by the Timer1 module. Page provides register information. Unimplemented, read as `1'. 2011 Microchip Technology Inc. Preliminary DS41609A-page 177 PIC16(L)F1508/9 NOTES: DS41609A-page 178 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 20.0 TIMER2 MODULE The Timer2 module incorporates the following features: * 8-bit Timer and Period registers (TMR2 and PR2, respectively) * Readable and writable (both registers) * Software programmable prescaler (1:1, 1:4, 1:16, and 1:64) * Software programmable postscaler (1:1 to 1:16) * Interrupt on TMR2 match with PR2, respectively See Figure 20-1 for a block diagram of Timer2. FIGURE 20-1: TIMER2 BLOCK DIAGRAM TMR2 Output FOSC/4 Prescaler 1:1, 1:4, 1:16, 1:64 2 TMR2 Comparator Sets Flag bit TMR2IF Reset Postscaler 1:1 to 1:16 EQ T2CKPS<1:0> 4 PR2 T2OUTPS<3:0> 2011 Microchip Technology Inc. Preliminary DS41609A-page 179 PIC16(L)F1508/9 20.1 Timer2 Operation 20.3 The clock input to the Timer2 module is the system instruction clock (FOSC/4). TMR2 increments from 00h on each clock edge. A 4-bit counter/prescaler on the clock input allows direct input, divide-by-4 and divide-by-16 prescale options. These options are selected by the prescaler control bits, T2CKPS<1:0> of the T2CON register. The value of TMR2 is compared to that of the Period register, PR2, on each clock cycle. When the two values match, the comparator generates a match signal as the timer output. This signal also resets the value of TMR2 to 00h on the next cycle and drives the output counter/ postscaler (see Section 20.2 "Timer2 Interrupt"). Timer2 Output The unscaled output of TMR2 is available primarily to the PWMx module, where it is used as a time base for operation. 20.4 Timer2 Operation During Sleep Timer2 cannot be operated while the processor is in Sleep mode. The contents of the TMR2 and PR2 registers will remain unchanged while the processor is in Sleep mode. The TMR2 and PR2 registers are both directly readable and writable. The TMR2 register is cleared on any device Reset, whereas the PR2 register initializes to FFh. Both the prescaler and postscaler counters are cleared on the following events: * * * * * * * * * a write to the TMR2 register a write to the T2CON register Power-on Reset (POR) Brown-out Reset (BOR) MCLR Reset Watchdog Timer (WDT) Reset Stack Overflow Reset Stack Underflow Reset RESET Instruction Note: 20.2 TMR2 is not cleared when T2CON is written. Timer2 Interrupt Timer2 can also generate an optional device interrupt. The Timer2 output signal (TMR2-to-PR2 match) provides the input for the 4-bit counter/postscaler. This counter generates the TMR2 match interrupt flag which is latched in TMR2IF of the PIR1 register. The interrupt is enabled by setting the TMR2 Match Interrupt Enable bit, TMR2IE of the PIE1 register. A range of 16 postscale options (from 1:1 through 1:16 inclusive) can be selected with the postscaler control bits, T2OUTPS<3:0>, of the T2CON register. DS41609A-page 180 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 REGISTER 20-1: U-0 T2CON: TIMER2 CONTROL REGISTER R/W-0/0 -- R/W-0/0 R/W-0/0 R/W-0/0 T2OUTPS<3:0> R/W-0/0 R/W-0/0 TMR2ON bit 7 R/W-0/0 T2CKPS<1:0> bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 Unimplemented: Read as `0' bit 6-3 T2OUTPS<3:0>: Timer2 Output Postscaler Select bits 0000 = 1:1 Postscaler 0001 = 1:2 Postscaler 0010 = 1:3 Postscaler 0011 = 1:4 Postscaler 0100 = 1:5 Postscaler 0101 = 1:6 Postscaler 0110 = 1:7 Postscaler 0111 = 1:8 Postscaler 1000 = 1:9 Postscaler 1001 = 1:10 Postscaler 1010 = 1:11 Postscaler 1011 = 1:12 Postscaler 1100 = 1:13 Postscaler 1101 = 1:14 Postscaler 1110 = 1:15 Postscaler 1111 = 1:16 Postscaler bit 2 TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 10 = Prescaler is 16 11 = Prescaler is 64 2011 Microchip Technology Inc. Preliminary DS41609A-page 181 PIC16(L)F1508/9 TABLE 20-1: Name INTCON SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 78 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE -- TMR2IE TMR1IE 79 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF -- TMR2IF TMR1IF PR2 Timer2 Module Period Register 82 179* PWM1CON PWM1EN PWM1OE PWM1OUT PWM1POL -- -- -- -- 269 PWM2CON PWM2EN PWM2OE PWM2OUT PWM2POL -- -- -- -- 269 PWM3CON PWM3EN PWM3OE PWM3OUT PWM3POL -- -- -- -- 269 PWM4CON PWM4EN PWM4OE PWM4OUT PWM4POL -- -- -- -- 269 T2CON TMR2 Legend: * -- T2OUTPS<3:0> TMR2ON T2CKPS<1:0> Holding Register for the 8-bit TMR2 Count 181 179* -- = unimplemented location, read as `0'. Shaded cells are not used for Timer2 module. Page provides register information. DS41609A-page 182 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 21.0 MASTER SYNCHRONOUS SERIAL PORT MODULE 21.1 Master SSP (MSSP) Module Overview The Master Synchronous Serial Port (MSSPx) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc. The MSSPx module can operate in one of two modes: * Serial Peripheral Interface (SPI) * Inter-Integrated Circuit (I2CTM) The SPI interface supports the following modes and features: * * * * * Master mode Slave mode Clock Parity Slave Select Synchronization (Slave mode only) Daisy-chain connection of slave devices Figure 21-1 is a block diagram of the SPI interface module. FIGURE 21-1: MSSPX BLOCK DIAGRAM (SPI MODE) Data Bus Read Write SSPBUF Reg SDI SSPSR Reg SDO bit 0 SS SSx Control Enable Shift Clock 2 (CKP, CKE) Clock Select Edge Select SSPM<3:0> 4 SCK Edge Select TRIS bit 2011 Microchip Technology Inc. Preliminary ( TMR22Output ) Prescaler TOSC 4, 16, 64 Baud Rate Generator (SSPxADD) DS41609A-page 183 PIC16(L)F1508/9 The I2C interface supports the following modes and features: Master mode Slave mode Byte NACKing (Slave mode) Limited Multi-master support 7-bit and 10-bit addressing Start and Stop interrupts Interrupt masking Clock stretching Bus collision detection General call address matching Address masking Address Hold and Data Hold modes Selectable SDAx hold times Note 1: In devices with more than one MSSP module, it is very important to pay close attention to SSPxCONx register names. SSPxCON1 and SSPxCON2 registers control different operational aspects of the same module, while SSPxCON1 and SSP2CON1 control the same features for two different modules. 2: Throughout this section, generic references to an MSSPx module in any of its operating modes may be interpreted as being equally applicable to MSSPx or MSSP2. Register names, module I/O signals, and bit names may use the generic designator `x' to indicate the use of a numeral to distinguish a particular module when required. Figure 21-2 is a block diagram of the I2C interface module in Master mode. Figure 21-3 is a diagram of the I2C interface module in Slave mode. MSSPX BLOCK DIAGRAM (I2CTM MASTER MODE) Internal data bus Read [SSPM<3:0>] Write SSPxBUF Baud Rate Generator (SSPxADD) Shift Clock SDAx SDAx in Receive Enable (RCEN) SCLx SCLx in Bus Collision DS41609A-page 184 LSb Start bit, Stop bit, Acknowledge Generate (SSPxCON2) Start bit detect, Stop bit detect Write collision detect Clock arbitration State counter for end of XMIT/RCV Address Match detect Preliminary Clock Cntl SSPxSR MSb (Hold off clock source) FIGURE 21-2: Clock arbitrate/BCOL detect * * * * * * * * * * * * * The PIC16F1508/9 has one MSSP module. Set/Reset: S, P, SSPxSTAT, WCOL, SSPOV Reset SEN, PEN (SSPxCON2) Set SSPxIF, BCLxIF 2011 Microchip Technology Inc. PIC16(L)F1508/9 FIGURE 21-3: MSSP BLOCK DIAGRAM (I2CTM SLAVE MODE) Internal Data Bus Read Write SSPxBUF Reg SCLx Shift Clock SSPxSR Reg SDAx MSb LSb SSPxMSK Reg Match Detect Addr Match SSPxADD Reg Start and Stop bit Detect 2011 Microchip Technology Inc. Preliminary Set, Reset S, P bits (SSPxSTAT Reg) DS41609A-page 185 PIC16(L)F1508/9 21.2 SPI Mode Overview The Serial Peripheral Interface (SPI) bus is a synchronous serial data communication bus that operates in Full-Duplex mode. Devices communicate in a master/slave environment where the master device initiates the communication. A slave device is controlled through a Chip Select known as Slave Select. The SPI bus specifies four signal connections: * * * * During each SPI clock cycle, a full-duplex data transmission occurs. This means that while the master device is sending out the MSb from its shift register (on its SDOx pin) and the slave device is reading this bit and saving it as the LSb of its shift register, that the slave device is also sending out the MSb from its shift register (on its SDOx pin) and the master device is reading this bit and saving it as the LSb of its shift register. After 8 bits have been shifted out, the master and slave have exchanged register values. Serial Clock (SCKx) Serial Data Out (SDOx) Serial Data In (SDIx) Slave Select (SSx) If there is more data to exchange, the shift registers are loaded with new data and the process repeats itself. Figure 21-1 shows the block diagram of the MSSP module when operating in SPI mode. The SPI bus operates with a single master device and one or more slave devices. When multiple slave devices are used, an independent Slave Select connection is required from the master device to each slave device. Figure 21-4 shows a typical connection between a master device and multiple slave devices. The master selects only one slave at a time. Most slave devices have tri-state outputs so their output signal appears disconnected from the bus when they are not selected. Transmissions involve two shift registers, eight bits in size, one in the master and one in the slave. With either the master or the slave device, data is always shifted out one bit at a time, with the Most Significant bit (MSb) shifted out first. At the same time, a new Least Significant bit (LSb) is shifted into the same register. Whether the data is meaningful or not (dummy data), depends on the application software. This leads to three scenarios for data transmission: * Master sends useful data and slave sends dummy data. * Master sends useful data and slave sends useful data. * Master sends dummy data and slave sends useful data. Transmissions may involve any number of clock cycles. When there is no more data to be transmitted, the master stops sending the clock signal and it deselects the slave. Every slave device connected to the bus that has not been selected through its slave select line must disregard the clock and transmission signals and must not transmit out any data of its own. Figure 21-5 shows a typical connection between two processors configured as master and slave devices. Data is shifted out of both shift registers on the programmed clock edge and latched on the opposite edge of the clock. The master device transmits information out on its SDOx output pin which is connected to, and received by, the slave's SDIx input pin. The slave device transmits information out on its SDOx output pin, which is connected to, and received by, the master's SDIx input pin. To begin communication, the master device first sends out the clock signal. Both the master and the slave devices should be configured for the same clock polarity. The master device starts a transmission by sending out the MSb from its shift register. The slave device reads this bit from that same line and saves it into the LSb position of its shift register. DS41609A-page 186 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 FIGURE 21-4: SPI MASTER AND MULTIPLE SLAVE CONNECTION SPI Master SCKx SCKx SDOx SDIx SDIx SDOx General I/O General I/O SSx General I/O SCKx SDIx SDOx SPI Slave #1 SPI Slave #2 SSx SCKx SDIx SDOx SPI Slave #3 SSx 21.2.1 SPI MODE REGISTERS The MSSP module has five registers for SPI mode operation. These are: * * * * * * MSSP STATUS register (SSPxSTAT) MSSP Control Register 1 (SSPxCON1) MSSP Control Register 3 (SSPxCON3) MSSP Data Buffer register (SSPxBUF) MSSP Address register (SSPxADD) MSSP Shift register (SSPxSR) (Not directly accessible) SSPxCON1 and SSPxSTAT are the control STATUS registers in SPI mode operation. SSPxCON1 register is readable and writable. lower 6 bits of the SSPxSTAT are read-only. upper two bits of the SSPxSTAT are read/write. and The The The In SPI master mode, SSPxADD can be loaded with a value used in the Baud Rate Generator. More information on the Baud Rate Generator is available in Section 21.7 "Baud Rate Generator". SSPxSR is the shift register used for shifting data in and out. SSPxBUF provides indirect access to the SSPxSR register. SSPxBUF is the buffer register to which data bytes are written, and from which data bytes are read. In receive operations, SSPxSR and SSPxBUF together create a buffered receiver. When SSPxSR receives a complete byte, it is transferred to SSPxBUF and the SSPxIF interrupt is set. During transmission, the SSPxBUF is not buffered. A write to SSPxBUF will write to both SSPxBUF and SSPxSR. 2011 Microchip Technology Inc. Preliminary DS41609A-page 187 PIC16(L)F1508/9 21.2.2 SPI MODE OPERATION When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPxCON1<5:0> and SSPxSTAT<7:6>). These control bits allow the following to be specified: * * * * Master mode (SCKx is the clock output) Slave mode (SCKx is the clock input) Clock Polarity (Idle state of SCKx) Data Input Sample Phase (middle or end of data output time) * Clock Edge (output data on rising/falling edge of SCKx) * Clock Rate (Master mode only) * Slave Select mode (Slave mode only) To enable the serial port, SSP Enable bit, SSPEN of the SSPxCON1 register, must be set. To reset or reconfigure SPI mode, clear the SSPEN bit, re-initialize the SSPxCONx registers and then set the SSPEN bit. This configures the SDI, SDO, SCK and SS pins as serial port pins. For the pins to behave as the serial port function, some must have their data direction bits (in the TRIS register) appropriately programmed as follows: * SDIx must have corresponding TRIS bit set * SDOx must have corresponding TRIS bit cleared * SCKx (Master mode) must have corresponding TRIS bit cleared * SCKx (Slave mode) must have corresponding TRIS bit set * SSx must have corresponding TRIS bit set Any serial port function that is not desired may be overridden by programming the corresponding data direction (TRIS) register to the opposite value. FIGURE 21-5: The MSSP consists of a transmit/receive shift register (SSPxSR) and a buffer register (SSPxBUF). The SSPxSR shifts the data in and out of the device, MSb first. The SSPxBUF holds the data that was written to the SSPxSR until the received data is ready. Once the 8 bits of data have been received, that byte is moved to the SSPxBUF register. Then, the Buffer Full Detect bit, BF of the SSPxSTAT register, and the interrupt flag bit, SSPxIF, are set. This double-buffering of the received data (SSPxBUF) allows the next byte to start reception before reading the data that was just received. Any write to the SSPxBUF register during transmission/reception of data will be ignored and the write collision detect bit, WCOL of the SSPxCON1 register, will be set. User software must clear the WCOL bit to allow the following write(s) to the SSPxBUF register to complete successfully. When the application software is expecting to receive valid data, the SSPxBUF should be read before the next byte of data to transfer is written to the SSPxBUF. The Buffer Full bit, BF of the SSPxSTAT register, indicates when SSPxBUF has been loaded with the received data (transmission is complete). When the SSPxBUF is read, the BF bit is cleared. This data may be irrelevant if the SPI is only a transmitter. Generally, the MSSP interrupt is used to determine when the transmission/reception has completed. If the interrupt method is not going to be used, then software polling can be done to ensure that a write collision does not occur. The SSPxSR is not directly readable or writable and can only be accessed by addressing the SSPxBUF register. Additionally, the SSPxSTAT register indicates the various Status conditions. SPI MASTER/SLAVE CONNECTION SPI Master SSPM<3:0> = 00xx = 1010 SPI Slave SSPM<3:0> = 010x SDOx SDIx Serial Input Buffer (BUF) SDIx Shift Register (SSPxSR) MSb Serial Input Buffer (SSPxBUF) LSb SCKx General I/O Processor 1 DS41609A-page 188 SDOx Serial Clock Slave Select (optional) Preliminary Shift Register (SSPxSR) MSb LSb SCKx SSx Processor 2 2011 Microchip Technology Inc. PIC16(L)F1508/9 21.2.3 SPI MASTER MODE The master can initiate the data transfer at any time because it controls the SCKx line. The master determines when the slave (Processor 2, Figure 21-5) is to broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPxBUF register is written to. If the SPI is only going to receive, the SDOx output could be disabled (programmed as an input). The SSPxSR register will continue to shift in the signal present on the SDIx pin at the programmed clock rate. As each byte is received, it will be loaded into the SSPxBUF register as if a normal received byte (interrupts and Status bits appropriately set). The clock polarity is selected by appropriately programming the CKP bit of the SSPxCON1 register and the CKE bit of the SSPxSTAT register. This then, would give waveforms for SPI communication as shown in Figure 21-6, Figure 21-9 and Figure 21-10, where the MSb is transmitted first. In Master mode, the SPI clock rate (bit rate) is user programmable to be one of the following: * * * * * FOSC/4 (or TCY) FOSC/16 (or 4 * TCY) FOSC/64 (or 16 * TCY) Timer2 output/2 Fosc/(4 * (SSPxADD + 1)) Figure 21-6 shows the waveforms for Master mode. When the CKE bit is set, the SDOx data is valid before there is a clock edge on SCKx. The change of the input sample is shown based on the state of the SMP bit. The time when the SSPxBUF is loaded with the received data is shown. FIGURE 21-6: SPI MODE WAVEFORM (MASTER MODE) Write to SSPxBUF SCKx (CKP = 0 CKE = 0) SCKx (CKP = 1 CKE = 0) 4 Clock Modes SCKx (CKP = 0 CKE = 1) SCKx (CKP = 1 CKE = 1) SDOx (CKE = 0) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDOx (CKE = 1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDIx (SMP = 0) bit 0 bit 7 Input Sample (SMP = 0) SDIx (SMP = 1) bit 0 bit 7 Input Sample (SMP = 1) SSPxIF SSPxSR to SSPxBUF 2011 Microchip Technology Inc. Preliminary DS41609A-page 189 PIC16(L)F1508/9 21.2.4 21.2.5 SPI SLAVE MODE In Slave mode, the data is transmitted and received as external clock pulses appear on SCKx. When the last bit is latched, the SSPxIF interrupt flag bit is set. Before enabling the module in SPI Slave mode, the clock line must match the proper Idle state. The clock line can be observed by reading the SCKx pin. The Idle state is determined by the CKP bit of the SSPxCON1 register. While in Slave mode, the external clock is supplied by the external clock source on the SCKx pin. This external clock must meet the minimum high and low times as specified in the electrical specifications. While in Sleep mode, the slave can transmit/receive data. The shift register is clocked from the SCKx pin input and when a byte is received, the device will generate an interrupt. If enabled, the device will wake-up from Sleep. 21.2.4.1 Daisy-Chain Configuration The SPI bus can sometimes be connected in a daisy-chain configuration. The first slave output is connected to the second slave input, the second slave output is connected to the third slave input, and so on. The final slave output is connected to the master input. Each slave sends out, during a second group of clock pulses, an exact copy of what was received during the first group of clock pulses. The whole chain acts as one large communication shift register. The daisy-chain feature only requires a single Slave Select line from the master device. Figure 21-7 shows the block diagram of a typical daisy-chain connection when operating in SPI mode. In a daisy-chain configuration, only the most recent byte on the bus is required by the slave. Setting the BOEN bit of the SSPxCON3 register will enable writes to the SSPxBUF register, even if the previous byte has not been read. This allows the software to ignore data that may not apply to it. SLAVE SELECT SYNCHRONIZATION The Slave Select can also be used to synchronize communication. The Slave Select line is held high until the master device is ready to communicate. When the Slave Select line is pulled low, the slave knows that a new transmission is starting. If the slave fails to receive the communication properly, it will be reset at the end of the transmission, when the Slave Select line returns to a high state. The slave is then ready to receive a new transmission when the Slave Select line is pulled low again. If the Slave Select line is not used, there is a risk that the slave will eventually become out of sync with the master. If the slave misses a bit, it will always be one bit off in future transmissions. Use of the Slave Select line allows the slave and master to align themselves at the beginning of each transmission. The SSx pin allows a Synchronous Slave mode. The SPI must be in Slave mode with SSx pin control enabled (SSPxCON1<3:0> = 0100). When the SSx pin is low, transmission and reception are enabled and the SDOx pin is driven. When the SSx pin goes high, the SDOx pin is no longer driven, even if in the middle of a transmitted byte and becomes a floating output. External pull-up/pull-down resistors may be desirable depending on the application. Note 1: When the SPI is in Slave mode with SSx pin control enabled (SSPxCON1<3:0> = 0100), the SPI module will reset if the SSx pin is set to VDD. 2: When the SPI is used in Slave mode with CKE set; the user must enable SSx pin control. 3: While operated in SPI Slave mode the SMP bit of the SSPxSTAT register must remain clear. When the SPI module resets, the bit counter is forced to `0'. This can be done by either forcing the SSx pin to a high level or clearing the SSPEN bit. DS41609A-page 190 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 FIGURE 21-7: SPI DAISY-CHAIN CONNECTION SPI Master SCK SCK SDOx SDIx SDIx SDOx General I/O SPI Slave #1 SSx SCK SDIx SDOx SPI Slave #2 SSx SCK SDIx SDOx SPI Slave #3 SSx FIGURE 21-8: SLAVE SELECT SYNCHRONOUS WAVEFORM SSx SCKx (CKP = 0 CKE = 0) SCKx (CKP = 1 CKE = 0) Write to SSPxBUF Shift register SSPxSR and bit count are reset SSPxBUF to SSPxSR SDOx bit 7 bit 6 bit 7 SDIx bit 6 bit 0 bit 0 bit 7 bit 7 Input Sample SSPxIF Interrupt Flag SSPxSR to SSPxBUF 2011 Microchip Technology Inc. Preliminary DS41609A-page 191 PIC16(L)F1508/9 FIGURE 21-9: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SSx Optional SCKx (CKP = 0 CKE = 0) SCKx (CKP = 1 CKE = 0) Write to SSPxBUF Valid SDOx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDIx bit 0 bit 7 Input Sample SSPxIF Interrupt Flag SSPxSR to SSPxBUF Write Collision detection active FIGURE 21-10: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SSx Not Optional SCKx (CKP = 0 CKE = 1) SCKx (CKP = 1 CKE = 1) Write to SSPxBUF Valid SDOx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDIx bit 0 bit 7 Input Sample SSPxIF Interrupt Flag SSPxSR to SSPxBUF Write Collision detection active DS41609A-page 192 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 21.2.6 SPI OPERATION IN SLEEP MODE In SPI Master mode, module clocks may be operating at a different speed than when in Full-Power mode; in the case of the Sleep mode, all clocks are halted. Special care must be taken by the user when the MSSP clock is much faster than the system clock. In Slave mode, when MSSP interrupts are enabled, after the master completes sending data, an MSSP interrupt will wake the controller from Sleep. If an exit from Sleep mode is not desired, MSSP interrupts should be disabled. In SPI Master mode, when the Sleep mode is selected, all module clocks are halted and the transmission/reception will remain in that state until the device wakes. After the device returns to Run mode, the module will resume transmitting and receiving data. In SPI Slave mode, the SPI Transmit/Receive Shift register operates asynchronously to the device. This allows the device to be placed in Sleep mode and data to be shifted into the SPI Transmit/Receive Shift register. When all 8 bits have been received, the MSSP interrupt flag bit will be set and if enabled, will wake the device. TABLE 21-1: Name ANSELA INTCON PIE1 PIR1 SSP1BUF SUMMARY OF REGISTERS ASSOCIATED WITH SPI OPERATION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page -- -- -- ANSA4 -- ANSA2 ANSA1 ANSA0 115 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 78 TMR1GIE ADIE RCIE TXIE SSP1IE -- TMR2IE TMR1IE 79 TMR1GIF ADIF RCIF TXIF SSP1IF -- TMR2IF TMR1IF Synchronous Serial Port Receive Buffer/Transmit Register SSP1CON1 WCOL SSPOV SSPEN CKP SSP1CON3 ACKTIM PCIE SCIE BOEN SSP1STAT SMP CKE D/A P S R/W -- -- TRISA5 TRISA4 --(1) TRISA2 TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISA TRISC Legend: * Note 1: 82 187* SSPM<3:0> SDAHT SBCDE AHEN 232 DHEN 234 UA BF 231 TRISA1 TRISA0 114 TRISC0 122 -- = Unimplemented location, read as `0'. Shaded cells are not used by the MSSP in SPI mode. Page provides register information. Unimplemented, read as `1'. 2011 Microchip Technology Inc. Preliminary DS41609A-page 193 PIC16(L)F1508/9 21.3 I2C MODE OVERVIEW FIGURE 21-11: The Inter-Integrated Circuit Bus (I2C) is a multi-master serial data communication bus. Devices communicate in a master/slave environment where the master devices initiate the communication. A Slave device is controlled through addressing. VDD SCLx The I2C bus specifies two signal connections: * Serial Clock (SCLx) * Serial Data (SDAx) Figure 21-11 shows a typical connection between two processors configured as master and slave devices. The I2C bus can operate with one or more master devices and one or more slave devices. There are four potential modes of operation for a given device: * Master Transmit mode (master is transmitting data to a slave) * Master Receive mode (master is receiving data from a slave) * Slave Transmit mode (slave is transmitting data to a master) * Slave Receive mode (slave is receiving data from the master) SDAx The Acknowledge bit (ACK) is an active-low signal, which holds the SDAx line low to indicate to the transmitter that the slave device has received the transmitted data and is ready to receive more. The transition of a data bits is always performed while the SCLx line is held low. Transitions that occur while the SCLx line is held high are used to indicate Start and Stop bits. If the master intends to write to the slave, then it repeatedly sends out a byte of data, with the slave responding after each byte with an ACK bit. In this example, the master device is in Master Transmit mode and the slave is in Slave Receive mode. If the master intends to read from the slave, then it repeatedly receives a byte of data from the slave, and responds after each byte with an ACK bit. In this example, the master device is in Master Receive mode and the slave is Slave Transmit mode. To begin communication, a master device starts out in Master Transmit mode. The master device sends out a Start bit followed by the address byte of the slave it intends to communicate with. This is followed by a single Read/Write bit, which determines whether the master intends to transmit to or receive data from the slave device. If the requested slave exists on the bus, it will respond with an Acknowledge bit, otherwise known as an ACK. The master then continues in either Transmit mode or Receive mode and the slave continues in the complement, either in Receive mode or Transmit mode, respectively. A Start bit is indicated by a high-to-low transition of the SDAx line while the SCLx line is held high. Address and data bytes are sent out, Most Significant bit (MSb) first. The Read/Write bit is sent out as a logical one when the master intends to read data from the slave, and is sent out as a logical zero when it intends to write data to the slave. DS41609A-page 194 Slave SDAx Figure 21-2 and Figure 21-3 show the block diagrams of the MSSP module when operating in I2C mode. SCLx VDD Master Both the SCLx and SDAx connections are bidirectional open-drain lines, each requiring pull-up resistors for the supply voltage. Pulling the line to ground is considered a logical zero and letting the line float is considered a logical one. I2C MASTER/ SLAVE CONNECTION On the last byte of data communicated, the master device may end the transmission by sending a Stop bit. If the master device is in Receive mode, it sends the Stop bit in place of the last ACK bit. A Stop bit is indicated by a low-to-high transition of the SDAx line while the SCLx line is held high. In some cases, the master may want to maintain control of the bus and re-initiate another transmission. If so, the master device may send another Start bit in place of the Stop bit or last ACK bit when it is in receive mode. The I2C bus specifies three message protocols; * Single message where a master writes data to a slave. * Single message where a master reads data from a slave. * Combined message where a master initiates a minimum of two writes, or two reads, or a combination of writes and reads, to one or more slaves. Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 When one device is transmitting a logical one, or letting the line float, and a second device is transmitting a logical zero, or holding the line low, the first device can detect that the line is not a logical one. This detection, when used on the SCLx line, is called clock stretching. Clock stretching gives slave devices a mechanism to control the flow of data. When this detection is used on the SDAx line, it is called arbitration. Arbitration ensures that there is only one master device communicating at any single time. 21.3.1 CLOCK STRETCHING When a slave device has not completed processing data, it can delay the transfer of more data through the process of clock stretching. An addressed slave device may hold the SCLx clock line low after receiving or sending a bit, indicating that it is not yet ready to continue. The master that is communicating with the slave will attempt to raise the SCLx line in order to transfer the next bit, but will detect that the clock line has not yet been released. Because the SCLx connection is open-drain, the slave has the ability to hold that line low until it is ready to continue communicating. Clock stretching allows receivers that cannot keep up with a transmitter to control the flow of incoming data. 21.3.2 ARBITRATION Each master device must monitor the bus for Start and Stop bits. If the device detects that the bus is busy, it cannot begin a new message until the bus returns to an Idle state. However, two master devices may try to initiate a transmission on or about the same time. When this occurs, the process of arbitration begins. Each transmitter checks the level of the SDAx data line and compares it to the level that it expects to find. The first transmitter to observe that the two levels do not match, loses arbitration, and must stop transmitting on the SDAx line. For example, if one transmitter holds the SDAx line to a logical one (lets it float) and a second transmitter holds it to a logical zero (pulls it low), the result is that the SDAx line will be low. The first transmitter then observes that the level of the line is different than expected and concludes that another transmitter is communicating. The first transmitter to notice this difference is the one that loses arbitration and must stop driving the SDAx line. If this transmitter is also a master device, it also must stop driving the SCLx line. It then can monitor the lines for a Stop condition before trying to reissue its transmission. In the meantime, the other device that has not noticed any difference between the expected and actual levels on the SDAx line continues with its original transmission. It can do so without any complications, because so far, the transmission appears exactly as expected with no other transmitter disturbing the message. Slave Transmit mode can also be arbitrated, when a master addresses multiple slaves, but this is less common. If two master devices are sending a message to two different slave devices at the address stage, the master sending the lower slave address always wins arbitration. When two master devices send messages to the same slave address, and addresses can sometimes refer to multiple slaves, the arbitration process must continue into the data stage. Arbitration usually occurs very rarely, but it is a necessary process for proper multi-master support. 2011 Microchip Technology Inc. Preliminary DS41609A-page 195 PIC16(L)F1508/9 21.4 I2C MODE OPERATION TABLE 21-2: All MSSP I2C communication is byte oriented and shifted out MSb first. Six SFR registers and 2 interrupt flags interface the module with the PIC(R) microcontroller and user software. Two pins, SDAx and SCLx, are exercised by the module to communicate with other external I2C devices. 21.4.1 BYTE FORMAT All communication in I2C is done in 9-bit segments. A byte is sent from a master to a slave or vice-versa, followed by an Acknowledge bit sent back. After the 8th falling edge of the SCLx line, the device outputting data on the SDAx changes that pin to an input and reads in an acknowledge value on the next clock pulse. The clock signal, SCLx, is provided by the master. Data is valid to change while the SCLx signal is low, and sampled on the rising edge of the clock. Changes on the SDAx line while the SCLx line is high define special conditions on the bus, explained below. 21.4.2 DEFINITION OF I2C TERMINOLOGY There is language and terminology in the description of I2C communication that have definitions specific to I2C. That word usage is defined below and may be used in the rest of this document without explanation. This table was adapted from the Philips I2C specification. 21.4.3 SDAX AND SCLX PINS Selection of any I2C mode with the SSPEN bit set, forces the SCLx and SDAx pins to be open-drain. These pins should be set by the user to inputs by setting the appropriate TRIS bits. Note: Data is tied to output zero when an I2C mode is enabled. 21.4.4 SDAX HOLD TIME The hold time of the SDAx pin is selected by the SDAHT bit of the SSPxCON3 register. Hold time is the time SDAx is held valid after the falling edge of SCLx. Setting the SDAHT bit selects a longer 300 ns minimum hold time and may help on buses with large capacitance. DS41609A-page 196 TERM I2C BUS TERMS Description Transmitter The device which shifts data out onto the bus. Receiver The device which shifts data in from the bus. Master The device that initiates a transfer, generates clock signals and terminates a transfer. Slave The device addressed by the master. Multi-master A bus with more than one device that can initiate data transfers. Arbitration Procedure to ensure that only one master at a time controls the bus. Winning arbitration ensures that the message is not corrupted. Synchronization Procedure to synchronize the clocks of two or more devices on the bus. Idle No master is controlling the bus, and both SDAx and SCLx lines are high. Active Any time one or more master devices are controlling the bus. Addressed Slave device that has received a Slave matching address and is actively being clocked by a master. Matching Address byte that is clocked into a Address slave that matches the value stored in SSPxADD. Write Request Slave receives a matching address with R/W bit clear, and is ready to clock in data. Read Request Master sends an address byte with the R/W bit set, indicating that it wishes to clock data out of the Slave. This data is the next and all following bytes until a Restart or Stop. Clock Stretching When a device on the bus hold SCLx low to stall communication. Bus Collision Any time the SDAx line is sampled low by the module while it is outputting and expected high state. Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 21.4.5 START CONDITION 21.4.7 The I2C specification defines a Start condition as a transition of SDAx from a high to a low state while SCLx line is high. A Start condition is always generated by the master and signifies the transition of the bus from an Idle to an Active state. Figure 21-12 shows wave forms for Start and Stop conditions. A Restart is valid any time that a Stop would be valid. A master can issue a Restart if it wishes to hold the bus after terminating the current transfer. A Restart has the same effect on the slave that a Start would, resetting all slave logic and preparing it to clock in an address. The master may want to address the same or another slave. A bus collision can occur on a Start condition if the module samples the SDAx line low before asserting it low. This does not conform to the I2C Specification that states no bus collision can occur on a Start. 21.4.6 RESTART CONDITION In 10-bit Addressing Slave mode a Restart is required for the master to clock data out of the addressed slave. Once a slave has been fully addressed, matching both high and low address bytes, the master can issue a Restart and the high address byte with the R/W bit set. The slave logic will then hold the clock and prepare to clock out data. STOP CONDITION A Stop condition is a transition of the SDAx line from low-to-high state while the SCLx line is high. After a full match with R/W clear in 10-bit mode, a prior match flag is set and maintained. Until a Stop condition, a high address with R/W clear, or high address match fails. Note: At least one SCLx low time must appear before a Stop is valid, therefore, if the SDAx line goes low then high again while the SCLx line stays high, only the Start condition is detected. 21.4.8 START/STOP CONDITION INTERRUPT MASKING The SCIE and PCIE bits of the SSPxCON3 register can enable the generation of an interrupt in Slave modes that do not typically support this function. Slave modes where interrupt on Start and Stop detect are already enabled, these bits will have no effect. FIGURE 21-12: I2C START AND STOP CONDITIONS SDAx SCLx S Start P Change of Change of Data Allowed Data Allowed Condition FIGURE 21-13: Stop Condition I2C RESTART CONDITION Sr Change of Change of Data Allowed Restart Data Allowed Condition 2011 Microchip Technology Inc. Preliminary DS41609A-page 197 PIC16(L)F1508/9 21.4.9 21.5.1.1 ACKNOWLEDGE SEQUENCE I2C Slave 7-bit Addressing Mode The 9th SCLx pulse for any transferred byte in I2C is dedicated as an Acknowledge. It allows receiving devices to respond back to the transmitter by pulling the SDAx line low. The transmitter must release control of the line during this time to shift in the response. The Acknowledge (ACK) is an active-low signal, pulling the SDAx line low indicated to the transmitter that the device has received the transmitted data and is ready to receive more. In 7-bit Addressing mode, the LSb of the received data byte is ignored when determining if there is an address match. The result of an ACK is placed in the ACKSTAT bit of the SSPxCON2 register. After the acknowledge of the high byte the UA bit is set and SCLx is held low until the user updates SSPxADD with the low address. The low address byte is clocked in and all 8 bits are compared to the low address value in SSPxADD. Even if there is not an address match; SSPxIF and UA are set, and SCLx is held low until SSPxADD is updated to receive a high byte again. When SSPxADD is updated the UA bit is cleared. This ensures the module is ready to receive the high address byte on the next communication. Slave software, when the AHEN and DHEN bits are set, allow the user to set the ACK value sent back to the transmitter. The ACKDT bit of the SSPxCON2 register is set/cleared to determine the response. Slave hardware will generate an ACK response if the AHEN and DHEN bits of the SSPxCON3 register are clear. There are certain conditions where an ACK will not be sent by the slave. If the BF bit of the SSPxSTAT register or the SSPOV bit of the SSPxCON1 register are set when a byte is received. When the module is addressed, after the 8th falling edge of SCLx on the bus, the ACKTIM bit of the SSPxCON3 register is set. The ACKTIM bit indicates the acknowledge time of the active bus. The ACKTIM Status bit is only active when the AHEN bit or DHEN bit is enabled. 21.5 I2C Slave Mode Operation The MSSP Slave mode operates in one of four modes selected in the SSPM bits of SSPxCON1 register. The modes can be divided into 7-bit and 10-bit Addressing mode. 10-bit Addressing modes operate the same as 7-bit with some additional overhead for handling the larger addresses. Modes with Start and Stop bit interrupts operate the same as the other modes with SSPxIF additionally getting set upon detection of a Start, Restart, or Stop condition. 21.5.1 SLAVE MODE ADDRESSES The SSPxADD register (Register 21-6) contains the Slave mode address. The first byte received after a Start or Restart condition is compared against the value stored in this register. If the byte matches the value is loaded into the SSPxBUF register and an interrupt is generated. If the value does not match, the module goes idle and no indication is given to the software that anything happened. 21.5.1.2 I2C Slave 10-bit Addressing Mode In 10-bit Addressing mode, the first received byte is compared to the binary value of `1 1 1 1 0 A9 A8 0'. A9 and A8 are the two MSb of the 10-bit address and stored in bits 2 and 1 of the SSPxADD register. A high and low address match as a write request is required at the start of all 10-bit addressing communication. A transmission can be initiated by issuing a Restart once the slave is addressed, and clocking in the high address with the R/W bit set. The slave hardware will then acknowledge the read request and prepare to clock out data. This is only valid for a slave after it has received a complete high and low address byte match. 21.5.2 SLAVE RECEPTION When the R/W bit of a matching received address byte is clear, the R/W bit of the SSPxSTAT register is cleared. The received address is loaded into the SSPxBUF register and acknowledged. When the overflow condition exists for a received address, then not Acknowledge is given. An overflow condition is defined as either bit BF of the SSPxSTAT register is set, or bit SSPOV of the SSPxCON1 register is set. The BOEN bit of the SSPxCON3 register modifies this operation. For more information see Register 21-4. An MSSP interrupt is generated for each transferred data byte. Flag bit, SSPxIF, must be cleared by software. When the SEN bit of the SSPxCON2 register is set, SCLx will be held low (clock stretch) following each received byte. The clock must be released by setting the CKP bit of the SSPxCON1 register, except sometimes in 10-bit mode. See Section 21.2.3 "SPI Master Mode" for more detail. The SSP Mask register (Register 21-5) affects the address matching process. See Section 21.5.9 "SSPx Mask Register" for more information. DS41609A-page 198 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 21.5.2.1 7-bit Addressing Reception 21.5.2.2 This section describes a standard sequence of events for the MSSP module configured as an I2C Slave in 7-bit Addressing mode. Figure 21-14 and Figure 21-15 are used as visual references for this description. This is a step by step process of what typically must be done to accomplish I2C communication. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. Start bit detected. S bit of SSPxSTAT is set; SSPxIF is set if interrupt on Start detect is enabled. Matching address with R/W bit clear is received. The slave pulls SDAx low sending an ACK to the master, and sets SSPxIF bit. Software clears the SSPxIF bit. Software reads received address from SSPxBUF clearing the BF flag. If SEN = 1; Slave software sets CKP bit to release the SCLx line. The master clocks out a data byte. Slave drives SDAx low sending an ACK to the master, and sets SSPxIF bit. Software clears SSPxIF. Software reads the received byte from SSPxBUF clearing BF. Steps 8-12 are repeated for all received bytes from the Master. Master sends Stop condition, setting P bit of SSPxSTAT, and the bus goes idle. 7-bit Reception with AHEN and DHEN Slave device reception with AHEN and DHEN set operate the same as without these options with extra interrupts and clock stretching added after the 8th falling edge of SCLx. These additional interrupts allow the slave software to decide whether it wants to ACK the receive address or data byte, rather than the hardware. This functionality adds support for PMBusTM that was not present on previous versions of this module. This list describes the steps that need to be taken by slave software to use these options for I2C communcation. Figure 21-16 displays a module using both address and data holding. Figure 21-17 includes the operation with the SEN bit of the SSPxCON2 register set. 1. S bit of SSPxSTAT is set; SSPxIF is set if interrupt on Start detect is enabled. 2. Matching address with R/W bit clear is clocked in. SSPxIF is set and CKP cleared after the 8th falling edge of SCLx. 3. Slave clears the SSPxIF. 4. Slave can look at the ACKTIM bit of the SSPxCON3 register to determine if the SSPxIF was after or before the ACK. 5. Slave reads the address value from SSPxBUF, clearing the BF flag. 6. Slave sets ACK value clocked out to the master by setting ACKDT. 7. Slave releases the clock by setting CKP. 8. SSPxIF is set after an ACK, not after a NACK. 9. If SEN = 1 the slave hardware will stretch the clock after the ACK. 10. Slave clears SSPxIF. Note: SSPxIF is still set after the 9th falling edge of SCLx even if there is no clock stretching and BF has been cleared. Only if NACK is sent to master is SSPxIF not set 11. SSPxIF set and CKP cleared after 8th falling edge of SCLx for a received data byte. 12. Slave looks at ACKTIM bit of SSPxCON3 to determine the source of the interrupt. 13. Slave reads the received data from SSPxBUF clearing BF. 14. Steps 7-14 are the same for each received data byte. 15. Communication is ended by either the slave sending an ACK = 1, or the master sending a Stop condition. If a Stop is sent and Interrupt on Stop Detect is disabled, the slave will only know by polling the P bit of the SSPSTAT register. 2011 Microchip Technology Inc. Preliminary DS41609A-page 199 SDAx SCLx S Receiving Data A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 ACK 8 9 Receiving Data D7 D6 D5 D4 D3 D2 D1 1 2 3 4 5 6 7 D0 ACK D7 8 9 1 ACK = 1 D6 D5 D4 D3 D2 D1 D0 2 3 4 5 6 7 8 9 P Preliminary SSPxIF Cleared by software Cleared by software BF SSPxBUF is read First byte of data is available in SSPxBUF SSPOV 2011 Microchip Technology Inc. SSPOV set because SSPxBUF is still full. ACK is not sent. SSPxIF set on 9th falling edge of SCLx I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 0, DHEN = 0) From Slave to Master Receiving Address PIC16(L)F1508/9 FIGURE 21-14: DS41609A-page 200 Bus Master sends Stop condition SDAx SCLx S Receive Data A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 R/W=0 ACK 8 9 SEN Receive Data D7 D6 D5 D4 D3 D2 D1 D0 ACK 1 2 3 4 5 6 7 8 9 SEN ACK D7 D6 D5 D4 D3 D2 D1 D0 1 2 3 4 5 6 7 8 9 P Clock is held low until CKP is set to `1' Preliminary SSPxIF Cleared by software BF SSPxBUF is read Cleared by software SSPxIF set on 9th falling edge of SCLx First byte of data is available in SSPxBUF SSPOV set because SSPxBUF is still full. ACK is not sent. CKP CKP is written to `1' in software, releasing SCLx CKP is written to `1' in software, releasing SCLx DS41609A-page 201 SCLx is not held low because ACK= 1 PIC16(L)F1508/9 SSPOV I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 0, DHEN = 0) Receive Address FIGURE 21-15: 2011 Microchip Technology Inc. Bus Master sends Stop condition Receiving Data ACK D7 D6 D5 D4 D3 D2 D1 D0 A7 A6 A5 A4 A3 A2 A1 Received Data ACK ACK=1 D7 D6 D5 D4 D3 D2 D1 D0 S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P SSPxIF If AHEN = 1: SSPxIF is set BF Preliminary ACKDT SSPxIF is set on 9th falling edge of SCLx, after ACK Address is read from SSBUF Data is read from SSPxBUF Slave software clears ACKDT to CKP Slave software sets ACKDT to not ACK ACK the received byte When AHEN=1: CKP is cleared by hardware and SCLx is stretched No interrupt after not ACK from Slave Cleared by software When DHEN=1: CKP is cleared by hardware on 8th falling edge of SCLx CKP set by software, SCLx is released ACKTIM ACKTIM set by hardware on 8th falling edge of SCLx 2011 Microchip Technology Inc. S P ACKTIM cleared by hardware in 9th rising edge of SCLx ACKTIM set by hardware on 8th falling edge of SCLx I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 1) SCLx PIC16(L)F1508/9 Receiving Address SDAx FIGURE 21-16: DS41609A-page 202 Master sends Stop condition Master Releases SDAx to slave for ACK sequence ACK SCLx S 1 2 3 4 5 6 7 8 9 Receive Data 1 2 3 4 5 6 7 ACK Receive Data D7 D6 D5 D4 D3 D2 D1 D0 8 ACK 9 D7 D6 D5 D4 D3 D2 D1 D0 1 2 3 4 5 6 7 8 9 P SSPxIF No interrupt after if not ACK from Slave Cleared by software Preliminary BF Received address is loaded into SSPxBUF Received data is available on SSPxBUF ACKDT Slave software clears ACKDT to ACK the received byte SSPxBUF can be read any time before next byte is loaded Slave sends not ACK CKP When DHEN = 1; on the 8th falling edge of SCLx of a received data byte, CKP is cleared ACKTIM ACKTIM is set by hardware on 8th falling edge of SCLx S DS41609A-page 203 P ACKTIM is cleared by hardware on 9th rising edge of SCLx Set by software, release SCLx CKP is not cleared if not ACK PIC16(L)F1508/9 When AHEN = 1; on the 8th falling edge of SCLx of an address byte, CKP is cleared I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 1, DHEN = 1) Receiving Address A7 A6 A5 A4 A3 A2 A1 FIGURE 21-17: 2011 Microchip Technology Inc. R/W = 0 SDAx Master sends Stop condition Master releases SDAx to slave for ACK sequence PIC16(L)F1508/9 21.5.3 SLAVE TRANSMISSION 21.5.3.2 7-bit Transmission When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPxSTAT register is set. The received address is loaded into the SSPxBUF register, and an ACK pulse is sent by the slave on the ninth bit. A master device can transmit a read request to a slave, and then clock data out of the slave. The list below outlines what software for a slave will need to do to accomplish a standard transmission. Figure 21-17 can be used as a reference to this list. Following the ACK, slave hardware clears the CKP bit and the SCLx pin is held low (see Section 21.5.6 "Clock Stretching" for more detail). By stretching the clock, the master will be unable to assert another clock pulse until the slave is done preparing the transmit data. 1. The transmit data must be loaded into the SSPxBUF register which also loads the SSPxSR register. Then the SCLx pin should be released by setting the CKP bit of the SSPxCON1 register. The eight data bits are shifted out on the falling edge of the SCLx input. This ensures that the SDAx signal is valid during the SCLx high time. The ACK pulse from the master-receiver is latched on the rising edge of the ninth SCLx input pulse. This ACK value is copied to the ACKSTAT bit of the SSPxCON2 register. If ACKSTAT is set (not ACK), then the data transfer is complete. In this case, when the not ACK is latched by the slave, the slave goes idle and waits for another occurrence of the Start bit. If the SDAx line was low (ACK), the next transmit data must be loaded into the SSPxBUF register. Again, the SCLx pin must be released by setting bit CKP. An MSSP interrupt is generated for each data transfer byte. The SSPxIF bit must be cleared by software and the SSPxSTAT register is used to determine the status of the byte. The SSPxIF bit is set on the falling edge of the ninth clock pulse. 21.5.3.1 Slave Mode Bus Collision A slave receives a Read request and begins shifting data out on the SDAx line. If a bus collision is detected and the SBCDE bit of the SSPxCON3 register is set, the BCLxIF bit of the PIRx register is set. Once a bus collision is detected, the slave goes idle and waits to be addressed again. User software can use the BCLxIF bit to handle a slave bus collision. DS41609A-page 204 Master sends a Start condition on SDAx and SCLx. 2. S bit of SSPxSTAT is set; SSPxIF is set if interrupt on Start detect is enabled. 3. Matching address with R/W bit set is received by the Slave setting SSPxIF bit. 4. Slave hardware generates an ACK and sets SSPxIF. 5. SSPxIF bit is cleared by user. 6. Software reads the received address from SSPxBUF, clearing BF. 7. R/W is set so CKP was automatically cleared after the ACK. 8. The slave software loads the transmit data into SSPxBUF. 9. CKP bit is set releasing SCLx, allowing the master to clock the data out of the slave. 10. SSPxIF is set after the ACK response from the master is loaded into the ACKSTAT register. 11. SSPxIF bit is cleared. 12. The slave software checks the ACKSTAT bit to see if the master wants to clock out more data. Note 1: If the master ACKs the clock will be stretched. 2: ACKSTAT is the only bit updated on the rising edge of SCLx (9th) rather than the falling. 13. Steps 9-13 are repeated for each transmitted byte. 14. If the master sends a not ACK; the clock is not held, but SSPxIF is still set. 15. The master sends a Restart condition or a Stop. 16. The slave is no longer addressed. Preliminary 2011 Microchip Technology Inc. Receiving Address SDAx S R/W = 1 Automatic ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 1 8 1 1 2 3 4 5 6 7 9 2 3 4 5 6 Automatic 7 8 9 Transmitting Data 2 3 4 5 6 7 8 SSPxIF Cleared by software BF Received address is read from SSPxBUF Data to transmit is loaded into SSPxBUF BF is automatically cleared after 8th falling edge of SCLx Preliminary CKP When R/W is set SCLx is always held low after 9th SCLx falling edge Set by software CKP is not held for not ACK ACKSTAT R/W R/W is copied from the matching address byte D/A Indicates an address has been received S DS41609A-page 205 P P PIC16(L)F1508/9 Masters not ACK is copied to ACKSTAT 9 I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 0) SCLx Transmitting Data ACK A7 A6 A5 A4 A3 A2 A1 FIGURE 21-18: 2011 Microchip Technology Inc. Master sends Stop condition PIC16(L)F1508/9 21.5.3.3 7-bit Transmission with Address Hold Enabled Setting the AHEN bit of the SSPxCON3 register enables additional clock stretching and interrupt generation after the 8th falling edge of a received matching address. Once a matching address has been clocked in, CKP is cleared and the SSPxIF interrupt is set. Figure 21-18 displays a standard waveform of a 7-bit Address Slave Transmission with AHEN enabled. 1. 2. Bus starts idle. Master sends Start condition; the S bit of SSPxSTAT is set; SSPxIF is set if interrupt on Start detect is enabled. 3. Master sends matching address with R/W bit set. After the 8th falling edge of the SCLx line the CKP bit is cleared and SSPxIF interrupt is generated. 4. Slave software clears SSPxIF. 5. Slave software reads ACKTIM bit of SSPxCON3 register, and R/W and D/A of the SSPxSTAT register to determine the source of the interrupt. 6. Slave reads the address value from the SSPxBUF register clearing the BF bit. 7. Slave software decides from this information if it wishes to ACK or not ACK and sets the ACKDT bit of the SSPxCON2 register accordingly. 8. Slave sets the CKP bit releasing SCLx. 9. Master clocks in the ACK value from the slave. 10. Slave hardware automatically clears the CKP bit and sets SSPxIF after the ACK if the R/W bit is set. 11. Slave software clears SSPxIF. 12. Slave loads value to transmit to the master into SSPxBUF setting the BF bit. Note: SSPxBUF cannot be loaded until after the ACK. 13. Slave sets CKP bit releasing the clock. 14. Master clocks out the data from the slave and sends an ACK value on the 9th SCLx pulse. 15. Slave hardware copies the ACK value into the ACKSTAT bit of the SSPxCON2 register. 16. Steps 10-15 are repeated for each byte transmitted to the master from the slave. 17. If the master sends a not ACK the slave releases the bus allowing the master to send a Stop and end the communication. Note: Master must send a not ACK on the last byte to ensure that the slave releases the SCLx line to receive a Stop. DS41609A-page 206 Preliminary 2011 Microchip Technology Inc. Receiving Address SCLx S 1 2 3 4 5 6 Automatic R/W = 1 ACK A7 A6 A5 A4 A3 A2 A1 7 8 9 Transmitting Data Automatic D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 1 1 2 3 4 5 6 7 8 9 Transmitting Data 2 3 4 5 6 7 SSPxIF Cleared by software BF Received address is read from SSPxBUF Data to transmit is loaded into SSPxBUF BF is automatically cleared after 8th falling edge of SCLx Preliminary ACKDT Slave clears ACKDT to ACK address ACKSTAT Master's ACK response is copied to SSPxSTAT When AHEN = 1; CKP is cleared by hardware after receiving matching address. ACKTIM DS41609A-page 207 R/W D/A ACKTIM is set on 8th falling edge of SCLx CKP not cleared When R/W = 1; CKP is always cleared after ACK Set by software, releases SCLx ACKTIM is cleared on 9th rising edge of SCLx after not ACK 8 9 P PIC16(L)F1508/9 CKP ACK I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 1) SDAx FIGURE 21-19: 2011 Microchip Technology Inc. Master sends Stop condition Master releases SDAx to slave for ACK sequence PIC16(L)F1508/9 21.5.4 SLAVE MODE 10-BIT ADDRESS RECEPTION 21.5.5 This section describes a standard sequence of events for the MSSP module configured as an I2C slave in 10-bit Addressing mode. Figure 21-19 and is used as a visual reference for this description. This is a step by step process of what must be done by slave software to accomplish I2C communication. 1. 2. 3. 4. 5. 6. 7. 8. Bus starts idle. Master sends Start condition; S bit of SSPxSTAT is set; SSPxIF is set if interrupt on Start detect is enabled. Master sends matching high address with R/W bit clear; UA bit of the SSPxSTAT register is set. Slave sends ACK and SSPxIF is set. Software clears the SSPxIF bit. Software reads received address from SSPxBUF clearing the BF flag. Slave loads low address into SSPxADD, releasing SCLx. Master sends matching low address byte to the Slave; UA bit is set. 10-BIT ADDRESSING WITH ADDRESS OR DATA HOLD Reception using 10-bit addressing with AHEN or DHEN set is the same as with 7-bit modes. The only difference is the need to update the SSPxADD register using the UA bit. All functionality, specifically when the CKP bit is cleared and SCLx line is held low are the same. Figure 21-20 can be used as a reference of a slave in 10-bit addressing with AHEN set. Figure 21-21 shows a standard waveform for a slave transmitter in 10-bit Addressing mode. Note: Updates to the SSPxADD register are not allowed until after the ACK sequence. 9. Slave sends ACK and SSPxIF is set. Note: If the low address does not match, SSPxIF and UA are still set so that the slave software can set SSPxADD back to the high address. BF is not set because there is no match. CKP is unaffected. 10. Slave clears SSPxIF. 11. Slave reads the received matching address from SSPxBUF clearing BF. 12. Slave loads high address into SSPxADD. 13. Master clocks a data byte to the slave and clocks out the slaves ACK on the 9th SCLx pulse; SSPxIF is set. 14. If SEN bit of SSPxCON2 is set, CKP is cleared by hardware and the clock is stretched. 15. Slave clears SSPxIF. 16. Slave reads the received byte from SSPxBUF clearing BF. 17. If SEN is set the slave sets CKP to release the SCLx. 18. Steps 13-17 repeat for each received byte. 19. Master sends Stop to end the transmission. DS41609A-page 208 Preliminary 2011 Microchip Technology Inc. SCLx S 1 1 1 1 0 A9 A8 1 2 3 4 5 6 7 ACK 8 9 A7 A6 A5 A4 A3 A2 A1 A0 ACK 1 2 3 4 5 6 7 8 9 Receive Data Receive Data D7 D6 D5 D4 D3 D2 D1 D0 ACK 1 2 3 4 5 6 7 8 9 D7 D6 D5 D4 D3 D2 D1 D0 ACK 1 2 3 4 5 6 7 SCLx is held low while CKP = 0 Preliminary SSPxIF Set by hardware on 9th falling edge Cleared by software BF Receive address is read from SSPxBUF If address matches SSPxADD it is loaded into SSPxBUF Data is read from SSPxBUF When UA = 1; SCLx is held low Software updates SSPxADD and releases SCLx CKP DS41609A-page 209 Set by software, When SEN = 1; releasing SCLx CKP is cleared after 9th falling edge of received byte 9 P PIC16(L)F1508/9 UA 8 I2C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 0, DHEN = 0) Receive Second Address Byte Receive First Address Byte SDAx FIGURE 21-20: 2011 Microchip Technology Inc. Master sends Stop condition S 1 1 1 0 A9 A8 1 2 3 4 5 6 7 ACK 8 9 UA Receive Data A7 A6 A5 A4 A3 A2 A1 A0 ACK 1 2 3 4 5 6 7 8 9 UA Receive Data D7 D6 D5 D4 D3 D2 D1 1 2 3 4 5 6 7 D0 ACK D7 8 9 1 D6 D5 2 SSPxIF Set by hardware on 9th falling edge Cleared by software Cleared by software Preliminary BF SSPxBUF can be read anytime before the next received byte Received data is read from SSPxBUF ACKDT Slave software clears ACKDT to ACK the received byte UA Update to SSPxADD is not allowed until 9th falling edge of SCLx 2011 Microchip Technology Inc. CKP If when AHEN = 1; on the 8th falling edge of SCLx of an address byte, CKP is cleared ACKTIM ACKTIM is set by hardware on 8th falling edge of SCLx Update of SSPxADD, clears UA and releases SCLx Set CKP with software releases SCLx I2C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 0) SCLx 1 PIC16(L)F1508/9 SDAx Receive Second Address Byte R/W = 0 FIGURE 21-21: DS41609A-page 210 Receive First Address Byte FIGURE 21-22: Receiving Address R/W = 0 1 1 1 1 0 A9 A8 ACK SDAx SCLx S 1 2 3 4 5 6 7 8 9 Master sends not ACK Receiving Second Address Byte Receive First Address Byte A7 A6 A5 A4 A3 A2 A1 A0 ACK 1 1 1 1 0 A9 A8 1 2 3 4 5 6 7 8 1 9 2 3 4 5 6 7 8 Transmitting Data Byte ACK 9 ACK = 1 D7 D6 D5 D4 D3 D2 D1 D0 1 2 3 4 5 6 7 8 Sr Preliminary SSPxIF Set by hardware Cleared by software Set by hardware BF SSPxBUF loaded with received address Received address is read from SSPxBUF Data to transmit is loaded into SSPxBUF UA CKP After SSPxADD is updated, UA is cleared and SCLx is released High address is loaded back into SSPxADD When R/W = 1; CKP is cleared on 9th falling edge of SCLx ACKSTAT Set by software releases SCLx Masters not ACK is copied R/W DS41609A-page 211 R/W is copied from the matching address byte D/A Indicates an address has been received 9 P PIC16(L)F1508/9 UA indicates SSPxADD must be updated Master sends Stop condition I2C SLAVE, 10-BIT ADDRESS, TRANSMISSION (SEN = 0, AHEN = 0, DHEN = 0) 2011 Microchip Technology Inc. Master sends Restart event PIC16(L)F1508/9 21.5.6 21.5.6.2 CLOCK STRETCHING Clock stretching occurs when a device on the bus holds the SCLx line low, effectively pausing communication. The slave may stretch the clock to allow more time to handle data or prepare a response for the master device. A master device is not concerned with stretching as anytime it is active on the bus and not transferring data it is stretching. Any stretching done by a slave is invisible to the master software and handled by the hardware that generates SCLx. The CKP bit of the SSPxCON1 register is used to control stretching in software. Any time the CKP bit is cleared, the module will wait for the SCLx line to go low and then hold it. Setting CKP will release SCLx and allow more communication. 21.5.6.1 Normal Clock Stretching Following an ACK if the R/W bit of SSPxSTAT is set, a read request, the slave hardware will clear CKP. This allows the slave time to update SSPxBUF with data to transfer to the master. If the SEN bit of SSPxCON2 is set, the slave hardware will always stretch the clock after the ACK sequence. Once the slave is ready, CKP is set by software and communication resumes. Note 1: The BF bit has no effect on if the clock will be stretched or not. This is different than previous versions of the module that would not stretch the clock, clear CKP, if SSPxBUF was read before the 9th falling edge of SCLx. 2: Previous versions of the module did not stretch the clock for a transmission if SSPxBUF was loaded before the 9th falling edge of SCLx. It is now always cleared for read requests. FIGURE 21-23: 10-bit Addressing Mode In 10-bit Addressing mode, when the UA bit is set, the clock is always stretched. This is the only time the SCLx is stretched without CKP being cleared. SCLx is released immediately after a write to SSPxADD. Note: Previous versions of the module did not stretch the clock if the second address byte did not match. 21.5.6.3 Byte NACKing When the AHEN bit of SSPxCON3 is set; CKP is cleared by hardware after the 8th falling edge of SCLx for a received matching address byte. When the DHEN bit of SSPxCON3 is set, CKP is cleared after the 8th falling edge of SCLx for received data. Stretching after the 8th falling edge of SCLx allows the slave to look at the received address or data and decide if it wants to ACK the received data. 21.5.7 CLOCK SYNCHRONIZATION AND THE CKP BIT Any time the CKP bit is cleared, the module will wait for the SCLx line to go low and then hold it. However, clearing the CKP bit will not assert the SCLx output low until the SCLx output is already sampled low. Therefore, the CKP bit will not assert the SCLx line until an external I2C master device has already asserted the SCLx line. The SCLx output will remain low until the CKP bit is set and all other devices on the I2C bus have released SCLx. This ensures that a write to the CKP bit will not violate the minimum high time requirement for SCLx (see Figure 21-22). CLOCK SYNCHRONIZATION TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 SDAx DX - 1 DX SCLx CKP Master device asserts clock Master device releases clock WR SSPxCON1 DS41609A-page 212 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 21.5.8 In 10-bit Address mode, the UA bit will not be set on the reception of the general call address. The slave will prepare to receive the second byte as data, just as it would in 7-bit mode. GENERAL CALL ADDRESS SUPPORT The addressing procedure for the I2C bus is such that the first byte after the Start condition usually determines which device will be the slave addressed by the master device. The exception is the general call address which can address all devices. When this address is used, all devices should, in theory, respond with an acknowledge. If the AHEN bit of the SSPxCON3 register is set, just as with any other address reception, the slave hardware will stretch the clock after the 8th falling edge of SCLx. The slave must then set its ACKDT value and release the clock with communication progressing as it would normally. The general call address is a reserved address in the I2C protocol, defined as address 0x00. When the GCEN bit of the SSPxCON2 register is set, the slave module will automatically ACK the reception of this address regardless of the value stored in SSPxADD. After the slave clocks in an address of all zeros with the R/W bit clear, an interrupt is generated and slave software can read SSPxBUF and respond. Figure 21-23 shows a General Call reception sequence. FIGURE 21-24: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE Address is compared to General Call Address after ACK, set interrupt R/W = 0 ACK D7 General Call Address SDAx SCLx S 1 2 3 4 5 6 7 8 9 1 Receiving Data ACK D6 D5 D4 D3 D2 D1 D0 2 3 4 5 6 7 8 9 SSPxIF BF (SSPxSTAT<0>) Cleared by software SSPxBUF is read GCEN (SSPxCON2<7>) '1' 21.5.9 SSPx MASK REGISTER An SSPx Mask (SSPxMSK) register (Register 21-5) is available in I2C Slave mode as a mask for the value held in the SSPxSR register during an address comparison operation. A zero (`0') bit in the SSPxMSK register has the effect of making the corresponding bit of the received address a "don't care". This register is reset to all `1's upon any Reset condition and, therefore, has no effect on standard SSPx operation until written with a mask value. The SSPx Mask register is active during: * 7-bit Address mode: address compare of A<7:1>. * 10-bit Address mode: address compare of A<7:0> only. The SSPx mask has no effect during the reception of the first (high) byte of the address. 2011 Microchip Technology Inc. Preliminary DS41609A-page 213 PIC16(L)F1508/9 21.6 I2C MASTER MODE 21.6.1 Master mode is enabled by setting and clearing the appropriate SSPM bits in the SSPxCON1 register and by setting the SSPEN bit. In Master mode, the SDAx and SCKx pins must be configured as inputs. The MSSP peripheral hardware will override the output driver TRIS controls when necessary to drive the pins low. Master mode of operation is supported by interrupt generation on the detection of the Start and Stop conditions. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSPx module is disabled. Control of the I 2C bus may be taken when the P bit is set, or the bus is idle. In Firmware Controlled Master mode, user code conducts all I 2C bus operations based on Start and Stop bit condition detection. Start and Stop condition detection is the only active circuitry in this mode. All other communication is done by the user software directly manipulating the SDAx and SCLx lines. The following events will cause the SSPx Interrupt Flag bit, SSPxIF, to be set (SSPx interrupt, if enabled): * * * * * Start condition detected Stop condition detected Data transfer byte transmitted/received Acknowledge transmitted/received Repeated Start generated I2C MASTER MODE OPERATION The master device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is ended with a Stop condition or with a Repeated Start condition. Since the Repeated Start condition is also the beginning of the next serial transfer, the I2C bus will not be released. In Master Transmitter mode, serial data is output through SDAx, while SCLx outputs the serial clock. The first byte transmitted contains the slave address of the receiving device (7 bits) and the Read/Write (R/W) bit. In this case, the R/W bit will be logic `0'. Serial data is transmitted 8 bits at a time. After each byte is transmitted, an Acknowledge bit is received. Start and Stop conditions are output to indicate the beginning and the end of a serial transfer. In Master Receive mode, the first byte transmitted contains the slave address of the transmitting device (7 bits) and the R/W bit. In this case, the R/W bit will be logic `1'. Thus, the first byte transmitted is a 7-bit slave address followed by a `1' to indicate the receive bit. Serial data is received via SDAx, while SCLx outputs the serial clock. Serial data is received 8 bits at a time. After each byte is received, an Acknowledge bit is transmitted. Start and Stop conditions indicate the beginning and end of transmission. A Baud Rate Generator is used to set the clock frequency output on SCLx. See Section 21.7 "Baud Rate Generator" for more detail. Note 1: The MSSPx module, when configured in I2C Master mode, does not allow queueing of events. For instance, the user is not allowed to initiate a Start condition and immediately write the SSPxBUF register to initiate transmission before the Start condition is complete. In this case, the SSPxBUF will not be written to and the WCOL bit will be set, indicating that a write to the SSPxBUF did not occur 2: When in Master mode, Start/Stop detection is masked and an interrupt is generated when the SEN/PEN bit is cleared and the generation is complete. DS41609A-page 214 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 21.6.2 CLOCK ARBITRATION Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, releases the SCLx pin (SCLx allowed to float high). When the SCLx pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCLx pin is actually sampled high. When the SCLx pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPxADD<7:0> and begins counting. This ensures that the SCLx high time will always be at least one BRG rollover count in the event that the clock is held low by an external device (Figure 21-25). FIGURE 21-25: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION SDAx DX - 1 DX SCLx deasserted but slave holds SCLx low (clock arbitration) SCLx allowed to transition high SCLx BRG decrements on Q2 and Q4 cycles BRG Value 03h 02h 01h 00h (hold off) 03h 02h SCLx is sampled high, reload takes place and BRG starts its count BRG Reload 21.6.3 WCOL STATUS FLAG If the user writes the SSPxBUF when a Start, Restart, Stop, Receive or Transmit sequence is in progress, the WCOL bit is set and the contents of the buffer are unchanged (the write does not occur). Any time the WCOL bit is set it indicates that an action on SSPxBUF was attempted while the module was not idle. Note: Because queueing of events is not allowed, writing to the lower 5 bits of SSPxCON2 is disabled until the Start condition is complete. 2011 Microchip Technology Inc. Preliminary DS41609A-page 215 PIC16(L)F1508/9 21.6.4 I2C MASTER MODE START by hardware; the Baud Rate Generator is suspended, leaving the SDAx line held low and the Start condition is complete. CONDITION TIMING To initiate a Start condition, the user sets the Start Enable bit, SEN bit of the SSPxCON2 register. If the SDAx and SCLx pins are sampled high, the Baud Rate Generator is reloaded with the contents of SSPxADD<7:0> and starts its count. If SCLx and SDAx are both sampled high when the Baud Rate Generator times out (TBRG), the SDAx pin is driven low. The action of the SDAx being driven low while SCLx is high is the Start condition and causes the S bit of the SSPxSTAT1 register to be set. Following this, the Baud Rate Generator is reloaded with the contents of SSPxADD<7:0> and resumes its count. When the Baud Rate Generator times out (TBRG), the SEN bit of the SSPxCON2 register will be automatically cleared FIGURE 21-26: Note 1: If at the beginning of the Start condition, the SDAx and SCLx pins are already sampled low, or if during the Start condition, the SCLx line is sampled low before the SDAx line is driven low, a bus collision occurs, the Bus Collision Interrupt Flag, BCLxIF, is set, the Start condition is aborted and the I2C module is reset into its Idle state. 2: The Philips I2C Specification states that a bus collision cannot occur on a Start. FIRST START BIT TIMING Set S bit (SSPxSTAT<3>) Write to SEN bit occurs here At completion of Start bit, hardware clears SEN bit and sets SSPxIF bit SDAx = 1, SCLx = 1 TBRG TBRG Write to SSPxBUF occurs here SDAx 1st bit 2nd bit TBRG SCLx S DS41609A-page 216 Preliminary TBRG 2011 Microchip Technology Inc. PIC16(L)F1508/9 21.6.5 I2C MASTER MODE REPEATED SSPxCON2 register will be automatically cleared and the Baud Rate Generator will not be reloaded, leaving the SDAx pin held low. As soon as a Start condition is detected on the SDAx and SCLx pins, the S bit of the SSPxSTAT register will be set. The SSPxIF bit will not be set until the Baud Rate Generator has timed out. START CONDITION TIMING A Repeated Start condition occurs when the RSEN bit of the SSPxCON2 register is programmed high and the master state machine is no longer active. When the RSEN bit is set, the SCLx pin is asserted low. When the SCLx pin is sampled low, the Baud Rate Generator is loaded and begins counting. The SDAx pin is released (brought high) for one Baud Rate Generator count (TBRG). When the Baud Rate Generator times out, if SDAx is sampled high, the SCLx pin will be deasserted (brought high). When SCLx is sampled high, the Baud Rate Generator is reloaded and begins counting. SDAx and SCLx must be sampled high for one TBRG. This action is then followed by assertion of the SDAx pin (SDAx = 0) for one TBRG while SCLx is high. SCLx is asserted low. Following this, the RSEN bit of the FIGURE 21-27: Note 1: If RSEN is programmed while any other event is in progress, it will not take effect. 2: A bus collision during the Repeated Start condition occurs if: * SDAx is sampled low when SCLx goes from low-to-high. * SCLx goes low before SDAx is asserted low. This may indicate that another master is attempting to transmit a data `1'. REPEAT START CONDITION WAVEFORM S bit set by hardware Write to SSPxCON2 occurs here SDAx = 1, SCLx (no change) At completion of Start bit, hardware clears RSEN bit and sets SSPxIF SDAx = 1, SCLx = 1 TBRG TBRG TBRG 1st bit SDAx Write to SSPxBUF occurs here TBRG SCLx Sr TBRG Repeated Start 2011 Microchip Technology Inc. Preliminary DS41609A-page 217 PIC16(L)F1508/9 21.6.6 I2C MASTER MODE TRANSMISSION 21.6.6.3 Transmission of a data byte, a 7-bit address or the other half of a 10-bit address is accomplished by simply writing a value to the SSPxBUF register. This action will set the Buffer Full flag bit, BF, and allow the Baud Rate Generator to begin counting and start the next transmission. Each bit of address/data will be shifted out onto the SDAx pin after the falling edge of SCLx is asserted. SCLx is held low for one Baud Rate Generator rollover count (TBRG). Data should be valid before SCLx is released high. When the SCLx pin is released high, it is held that way for TBRG. The data on the SDAx pin must remain stable for that duration and some hold time after the next falling edge of SCLx. After the eighth bit is shifted out (the falling edge of the eighth clock), the BF flag is cleared and the master releases SDAx. This allows the slave device being addressed to respond with an ACK bit during the ninth bit time if an address match occurred, or if data was received properly. The status of ACK is written into the ACKSTAT bit on the rising edge of the ninth clock. If the master receives an Acknowledge, the Acknowledge Status bit, ACKSTAT, is cleared. If not, the bit is set. After the ninth clock, the SSPxIF bit is set and the master clock (Baud Rate Generator) is suspended until the next data byte is loaded into the SSPxBUF, leaving SCLx low and SDAx unchanged (Figure 21-27). After the write to the SSPxBUF, each bit of the address will be shifted out on the falling edge of SCLx until all seven address bits and the R/W bit are completed. On the falling edge of the eighth clock, the master will release the SDAx pin, allowing the slave to respond with an Acknowledge. On the falling edge of the ninth clock, the master will sample the SDAx pin to see if the address was recognized by a slave. The status of the ACK bit is loaded into the ACKSTAT Status bit of the SSPxCON2 register. Following the falling edge of the ninth clock transmission of the address, the SSPxIF is set, the BF flag is cleared and the Baud Rate Generator is turned off until another write to the SSPxBUF takes place, holding SCLx low and allowing SDAx to float. 21.6.6.1 ACKSTAT Status Flag In Transmit mode, the ACKSTAT bit of the SSPxCON2 register is cleared when the slave has sent an Acknowledge (ACK = 0) and is set when the slave does not Acknowledge (ACK = 1). A slave sends an Acknowledge when it has recognized its address (including a general call), or when the slave has properly received its data. 21.6.6.4 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. BF Status Flag Typical transmit sequence: The user generates a Start condition by setting the SEN bit of the SSPxCON2 register. SSPxIF is set by hardware on completion of the Start. SSPxIF is cleared by software. The MSSPx module will wait the required start time before any other operation takes place. The user loads the SSPxBUF with the slave address to transmit. Address is shifted out the SDAx pin until all 8 bits are transmitted. Transmission begins as soon as SSPxBUF is written to. The MSSPx module shifts in the ACK bit from the slave device and writes its value into the ACKSTAT bit of the SSPxCON2 register. The MSSPx module generates an interrupt at the end of the ninth clock cycle by setting the SSPxIF bit. The user loads the SSPxBUF with eight bits of data. Data is shifted out the SDAx pin until all 8 bits are transmitted. The MSSPx module shifts in the ACK bit from the slave device and writes its value into the ACKSTAT bit of the SSPxCON2 register. Steps 8-11 are repeated for all transmitted data bytes. The user generates a Stop or Restart condition by setting the PEN or RSEN bits of the SSPxCON2 register. Interrupt is generated once the Stop/Restart condition is complete. In Transmit mode, the BF bit of the SSPxSTAT register is set when the CPU writes to SSPxBUF and is cleared when all 8 bits are shifted out. 21.6.6.2 WCOL Status Flag If the user writes the SSPxBUF when a transmit is already in progress (i.e., SSPxSR is still shifting out a data byte), the WCOL bit is set and the contents of the buffer are unchanged (the write does not occur). WCOL must be cleared by software before the next transmission. DS41609A-page 218 Preliminary 2011 Microchip Technology Inc. FIGURE 21-28: SEN = 0 Transmit Address to Slave SDAx A7 A6 A5 A4 ACKSTAT in SSPxCON2 = 1 From slave, clear ACKSTAT bit SSPxCON2<6> A3 A2 Transmitting Data or Second Half of 10-bit Address R/W = 0 ACK = 0 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 1 SCLx held low while CPU responds to SSPxIF 2 3 4 5 6 7 8 SSPxBUF written with 7-bit address and R/W start transmit SCLx S 1 2 3 4 5 6 7 8 9 9 P Preliminary SSPxIF Cleared by software Cleared by software service routine from SSP interrupt BF (SSPxSTAT<0>) SSPxBUF written SEN PEN R/W DS41609A-page 219 PIC16(L)F1508/9 After Start condition, SEN cleared by hardware SSPxBUF is written by software Cleared by software I2C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS) 2011 Microchip Technology Inc. Write SSPxCON2<0> SEN = 1 Start condition begins PIC16(L)F1508/9 21.6.7 I2C MASTER MODE RECEPTION 21.6.7.4 Master mode reception is enabled by programming the Receive Enable bit, RCEN bit of the SSPxCON2 register. Note: The MSSPx module must be in an Idle state before the RCEN bit is set or the RCEN bit will be disregarded. The Baud Rate Generator begins counting and on each rollover, the state of the SCLx pin changes (high-to-low/low-to-high) and data is shifted into the SSPxSR. After the falling edge of the eighth clock, the receive enable flag is automatically cleared, the contents of the SSPxSR are loaded into the SSPxBUF, the BF flag bit is set, the SSPxIF flag bit is set and the Baud Rate Generator is suspended from counting, holding SCLx low. The MSSP is now in Idle state awaiting the next command. When the buffer is read by the CPU, the BF flag bit is automatically cleared. The user can then send an Acknowledge bit at the end of reception by setting the Acknowledge Sequence Enable, ACKEN bit of the SSPxCON2 register. 21.6.7.1 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. BF Status Flag In receive operation, the BF bit is set when an address or data byte is loaded into SSPxBUF from SSPxSR. It is cleared when the SSPxBUF register is read. 11. 21.6.7.2 12. SSPOV Status Flag In receive operation, the SSPOV bit is set when 8 bits are received into the SSPxSR and the BF flag bit is already set from a previous reception. 13. 14. 21.6.7.3 15. WCOL Status Flag If the user writes the SSPxBUF when a receive is already in progress (i.e., SSPxSR is still shifting in a data byte), the WCOL bit is set and the contents of the buffer are unchanged (the write does not occur). DS41609A-page 220 Preliminary Typical Receive Sequence: The user generates a Start condition by setting the SEN bit of the SSPxCON2 register. SSPxIF is set by hardware on completion of the Start. SSPxIF is cleared by software. User writes SSPxBUF with the slave address to transmit and the R/W bit set. Address is shifted out the SDAx pin until all 8 bits are transmitted. Transmission begins as soon as SSPxBUF is written to. The MSSP module shifts in the ACK bit from the slave device and writes its value into the ACKSTAT bit of the SSPxCON2 register. The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPxIF bit. User sets the RCEN bit of the SSPxCON2 register and the Master clocks in a byte from the slave. After the 8th falling edge of SCLx, SSPxIF and BF are set. Master clears SSPxIF and reads the received byte from SSPxBUF, clears BF. Master sets ACK value sent to slave in ACKDT bit of the SSPxCON2 register and initiates the ACK by setting the ACKEN bit. Masters ACK is clocked out to the Slave and SSPxIF is set. User clears SSPxIF. Steps 8-13 are repeated for each received byte from the slave. Master sends a not ACK or Stop to end communication. 2011 Microchip Technology Inc. Write to SSPxCON2<0>(SEN = 1), begin Start condition Receiving Data from Slave Receiving Data from Slave A1 R/W ACK PEN bit = 1 written here RCEN cleared automatically D7 D6 D5 D4 D3 D2 D1 ACK D0 D7 D6 D5 D4 D3 D2 D1 D0 ACK Bus master terminates transfer ACK is not sent SCLx S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 Data shifted in on falling edge of CLK Preliminary Set SSPxIF interrupt at end of receive Cleared by software Cleared by software Cleared by software BF (SSPxSTAT<0>) P Set SSPxIF at end of receive Set SSPxIF interrupt at end of Acknowledge sequence SSPxIF SDAx = 0, SCLx = 1 while CPU responds to SSPxIF 9 8 Cleared by software Cleared in software Last bit is shifted into SSPxSR and contents are unloaded into SSPxBUF SSPOV is set because SSPxBUF is still full ACKEN DS41609A-page 221 RCEN Master configured as a receiver by programming SSPxCON2<3> (RCEN = 1) RCEN cleared automatically ACK from Master SDAx = ACKDT = 0 RCEN cleared automatically Set P bit (SSPxSTAT<4>) and SSPxIF PIC16(L)F1508/9 SSPOV Set SSPxIF interrupt at end of Acknowledge sequence I2C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS) A6 A5 A4 A3 A2 RCEN = 1, start next receive RCEN cleared automatically Transmit Address to Slave A7 Set ACKEN, start Acknowledge sequence SDAx = ACKDT = 1 ACK from Master SDAx = ACKDT = 0 Master configured as a receiver by programming SSPxCON2<3> (RCEN = 1) SEN = 0 Write to SSPxBUF occurs here, ACK from Slave start XMIT SDAx FIGURE 21-29: 2011 Microchip Technology Inc. Write to SSPxCON2<4> to start Acknowledge sequence SDAx = ACKDT (SSPxCON2<5>) = 0 PIC16(L)F1508/9 21.6.8 ACKNOWLEDGE SEQUENCE TIMING 21.6.9 A Stop bit is asserted on the SDAx pin at the end of a receive/transmit by setting the Stop Sequence Enable bit, PEN bit of the SSPxCON2 register. At the end of a receive/transmit, the SCLx line is held low after the falling edge of the ninth clock. When the PEN bit is set, the master will assert the SDAx line low. When the SDAx line is sampled low, the Baud Rate Generator is reloaded and counts down to `0'. When the Baud Rate Generator times out, the SCLx pin will be brought high and one TBRG (Baud Rate Generator rollover count) later, the SDAx pin will be deasserted. When the SDAx pin is sampled high while SCLx is high, the P bit of the SSPxSTAT register is set. A TBRG later, the PEN bit is cleared and the SSPxIF bit is set (Figure 21-30). An Acknowledge sequence is enabled by setting the Acknowledge Sequence Enable bit, ACKEN bit of the SSPxCON2 register. When this bit is set, the SCLx pin is pulled low and the contents of the Acknowledge data bit are presented on the SDAx pin. If the user wishes to generate an Acknowledge, then the ACKDT bit should be cleared. If not, the user should set the ACKDT bit before starting an Acknowledge sequence. The Baud Rate Generator then counts for one rollover period (TBRG) and the SCLx pin is deasserted (pulled high). When the SCLx pin is sampled high (clock arbitration), the Baud Rate Generator counts for TBRG. The SCLx pin is then pulled low. Following this, the ACKEN bit is automatically cleared, the Baud Rate Generator is turned off and the MSSP module then goes into Idle mode (Figure 21-29). 21.6.8.1 21.6.9.1 WCOL Status Flag If the user writes the SSPxBUF when a Stop sequence is in progress, then the WCOL bit is set and the contents of the buffer are unchanged (the write does not occur). WCOL Status Flag If the user writes the SSPxBUF when an Acknowledge sequence is in progress, then the WCOL bit is set and the contents of the buffer are unchanged (the write does not occur). FIGURE 21-30: STOP CONDITION TIMING ACKNOWLEDGE SEQUENCE WAVEFORM Acknowledge sequence starts here, write to SSPxCON2 ACKEN = 1, ACKDT = 0 ACKEN automatically cleared TBRG TBRG SDAx SCLx ACK D0 8 9 SSPxIF SSPxIF set at the end of receive Cleared in software Cleared in software SSPxIF set at the end of Acknowledge sequence Note: TBRG = one Baud Rate Generator period. DS41609A-page 222 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 FIGURE 21-31: STOP CONDITION RECEIVE OR TRANSMIT MODE SCLx = 1 for TBRG, followed by SDAx = 1 for TBRG after SDAx sampled high. P bit (SSPxSTAT<4>) is set. Write to SSPxCON2, set PEN PEN bit (SSPxCON2<2>) is cleared by hardware and the SSPxIF bit is set Falling edge of 9th clock TBRG SCLx SDAx ACK P TBRG TBRG TBRG SCLx brought high after TBRG SDAx asserted low before rising edge of clock to setup Stop condition Note: TBRG = one Baud Rate Generator period. 21.6.10 SLEEP OPERATION 21.6.13 the I2C slave While in Sleep mode, module can receive addresses or data and when an address match or complete byte transfer occurs, wake the processor from Sleep (if the MSSP interrupt is enabled). 21.6.11 EFFECTS OF A RESET A Reset disables the MSSP module and terminates the current transfer. 21.6.12 MULTI-MASTER MODE In Multi-Master mode, the interrupt generation on the detection of the Start and Stop conditions allows the determination of when the bus is free. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSP module is disabled. Control of the I 2C bus may be taken when the P bit of the SSPxSTAT register is set, or the bus is idle, with both the S and P bits clear. When the bus is busy, enabling the SSP interrupt will generate the interrupt when the Stop condition occurs. In multi-master operation, the SDAx line must be monitored for arbitration to see if the signal level is the expected output level. This check is performed by hardware with the result placed in the BCLxIF bit. The states where arbitration can be lost are: * * * * * Address Transfer Data Transfer A Start Condition A Repeated Start Condition An Acknowledge Condition MULTI -MASTER COMMUNICATION, BUS COLLISION AND BUS ARBITRATION Multi-Master mode support is achieved by bus arbitration. When the master outputs address/data bits onto the SDAx pin, arbitration takes place when the master outputs a `1' on SDAx, by letting SDAx float high and another master asserts a `0'. When the SCLx pin floats high, data should be stable. If the expected data on SDAx is a `1' and the data sampled on the SDAx pin is `0', then a bus collision has taken place. The master will set the Bus Collision Interrupt Flag, BCLxIF and reset the I2C port to its Idle state (Figure 21-31). If a transmit was in progress when the bus collision occurred, the transmission is halted, the BF flag is cleared, the SDAx and SCLx lines are deasserted and the SSPxBUF can be written to. When the user services the bus collision Interrupt Service Routine and if the I2C bus is free, the user can resume communication by asserting a Start condition. If a Start, Repeated Start, Stop or Acknowledge condition was in progress when the bus collision occurred, the condition is aborted, the SDAx and SCLx lines are deasserted and the respective control bits in the SSPxCON2 register are cleared. When the user services the bus collision Interrupt Service Routine and if the I2C bus is free, the user can resume communication by asserting a Start condition. The master will continue to monitor the SDAx and SCLx pins. If a Stop condition occurs, the SSPxIF bit will be set. A write to the SSPxBUF will start the transmission of data at the first data bit, regardless of where the transmitter left off when the bus collision occurred. In Multi-Master mode, the interrupt generation on the detection of Start and Stop conditions allows the determination of when the bus is free. Control of the I2C bus can be taken when the P bit is set in the SSPxSTAT register, or the bus is idle and the S and P bits are cleared. 2011 Microchip Technology Inc. Preliminary DS41609A-page 223 PIC16(L)F1508/9 FIGURE 21-32: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE Data changes while SCLx = 0 SDAx line pulled low by another source SDAx released by master Sample SDAx. While SCLx is high, data does not match what is driven by the master. Bus collision has occurred. SDAx SCLx Set bus collision interrupt (BCLxIF) BCLxIF DS41609A-page 224 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 21.6.13.1 Bus Collision During a Start Condition During a Start condition, a bus collision occurs if: a) b) SDA or SCL are sampled low at the beginning of the Start condition (Figure 21-32). SCL is sampled low before SDAx is asserted low (Figure 21-33). During a Start condition, both the SDAx and the SCL pins are monitored. If the SDAx pin is sampled low during this count, the BRG is reset and the SDAx line is asserted early (Figure 21-34). If, however, a `1' is sampled on the SDA pin, the SDA pin is asserted low at the end of the BRG count. The Baud Rate Generator is then reloaded and counts down to zero; if the SCL pin is sampled as `0' during this time, a bus collision does not occur. At the end of the BRG count, the SCL pin is asserted low. Note: If the SDA pin is already low, or the SCL pin is already low, then all of the following occur: * the Start condition is aborted, * the BCL1IF flag is set and * the MSSP module is reset to its Idle state (Figure 21-32). The Start condition begins with the SDAx and SCLx pins deasserted. When the SDAx pin is sampled high, the Baud Rate Generator is loaded and counts down. If the SCLx pin is sampled low while SDAx is high, a bus collision occurs because it is assumed that another master is attempting to drive a data `1' during the Start condition. FIGURE 21-33: The reason that bus collision is not a factor during a Start condition is that no two bus masters can assert a Start condition at the exact same time. Therefore, one master will always assert SDAx before the other. This condition does not cause a bus collision because the two masters must be allowed to arbitrate the first address following the Start condition. If the address is the same, arbitration must be allowed to continue into the data portion, Repeated Start or Stop conditions. BUS COLLISION DURING START CONDITION (SDAX ONLY) SDAx goes low before the SEN bit is set. Set BCLxIF, S bit and SSPxIF set because SDAx = 0, SCLx = 1. SDAx SCLx Set SEN, enable Start condition if SDAx = 1, SCLx = 1 SEN cleared automatically because of bus collision. SSP module reset into Idle state. SEN BCLxIF SDAx sampled low before Start condition. Set BCLxIF. S bit and SSPxIF set because SDAx = 0, SCLx = 1. SSPxIF and BCLxIF are cleared by software S SSPxIF SSPxIF and BCLxIF are cleared by software 2011 Microchip Technology Inc. Preliminary DS41609A-page 225 PIC16(L)F1508/9 FIGURE 21-34: BUS COLLISION DURING START CONDITION (SCLX = 0) SDAx = 0, SCLx = 1 TBRG TBRG SDAx Set SEN, enable Start sequence if SDAx = 1, SCLx = 1 SCLx SCLx = 0 before SDAx = 0, bus collision occurs. Set BCLxIF. SEN SCLx = 0 before BRG time-out, bus collision occurs. Set BCLxIF. BCLxIF Interrupt cleared by software S '0' '0' SSPxIF '0' '0' FIGURE 21-35: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION SDAx = 0, SCLx = 1 Set S Less than TBRG SDAx SCLx TBRG SDAx pulled low by other master. Reset BRG and assert SDAx. S SCLx pulled low after BRG time-out SEN BCLxIF Set SSPxIF Set SEN, enable Start sequence if SDAx = 1, SCLx = 1 '0' S SSPxIF SDAx = 0, SCLx = 1, set SSPxIF DS41609A-page 226 Preliminary Interrupts cleared by software 2011 Microchip Technology Inc. PIC16(L)F1508/9 21.6.13.2 Bus Collision During a Repeated Start Condition If SDAx is low, a bus collision has occurred (i.e., another master is attempting to transmit a data `0', Figure 21-35). If SDAx is sampled high, the BRG is reloaded and begins counting. If SDAx goes from high-to-low before the BRG times out, no bus collision occurs because no two masters can assert SDAx at exactly the same time. During a Repeated Start condition, a bus collision occurs if: a) b) A low level is sampled on SDAx when SCLx goes from low level to high level. SCLx goes low before SDAx is asserted low, indicating that another master is attempting to transmit a data `1'. If SCLx goes from high-to-low before the BRG times out and SDAx has not already been asserted, a bus collision occurs. In this case, another master is attempting to transmit a data `1' during the Repeated Start condition, see Figure 21-36. When the user releases SDAx and the pin is allowed to float high, the BRG is loaded with SSPxADD and counts down to zero. The SCLx pin is then deasserted and when sampled high, the SDAx pin is sampled. FIGURE 21-36: If, at the end of the BRG time-out, both SCLx and SDAx are still high, the SDAx pin is driven low and the BRG is reloaded and begins counting. At the end of the count, regardless of the status of the SCLx pin, the SCLx pin is driven low and the Repeated Start condition is complete. BUS COLLISION DURING A REPEATED START CONDITION (CASE 1) SDAx SCLx Sample SDAx when SCLx goes high. If SDAx = 0, set BCLxIF and release SDAx and SCLx. RSEN BCLxIF Cleared by software S '0' SSPxIF '0' FIGURE 21-37: BUS COLLISION DURING REPEATED START CONDITION (CASE 2) TBRG TBRG SDAx SCLx BCLxIF SCLx goes low before SDAx, set BCLxIF. Release SDAx and SCLx. Interrupt cleared by software RSEN '0' S SSPxIF 2011 Microchip Technology Inc. Preliminary DS41609A-page 227 PIC16(L)F1508/9 21.6.13.3 Bus Collision During a Stop Condition The Stop condition begins with SDAx asserted low. When SDAx is sampled low, the SCLx pin is allowed to float. When the pin is sampled high (clock arbitration), the Baud Rate Generator is loaded with SSPxADD and counts down to 0. After the BRG times out, SDAx is sampled. If SDAx is sampled low, a bus collision has occurred. This is due to another master attempting to drive a data `0' (Figure 21-37). If the SCLx pin is sampled low before SDAx is allowed to float high, a bus collision occurs. This is another case of another master attempting to drive a data `0' (Figure 21-38). Bus collision occurs during a Stop condition if: a) b) After the SDAx pin has been deasserted and allowed to float high, SDAx is sampled low after the BRG has timed out. After the SCLx pin is deasserted, SCLx is sampled low before SDAx goes high. FIGURE 21-38: BUS COLLISION DURING A STOP CONDITION (CASE 1) TBRG TBRG SDAx sampled low after TBRG, set BCLxIF TBRG SDAx SDAx asserted low SCLx PEN BCLxIF P '0' SSPxIF '0' FIGURE 21-39: BUS COLLISION DURING A STOP CONDITION (CASE 2) TBRG TBRG TBRG SDAx SCLx goes low before SDAx goes high, set BCLxIF Assert SDAx SCLx PEN BCLxIF P '0' SSPxIF '0' DS41609A-page 228 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 TABLE 21-3: Name INTCON SUMMARY OF REGISTERS ASSOCIATED WITH I2CTM OPERATION Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: INTE IOCIE TMR0IF INTF IOCIF 78 Bit 7 Bit 6 Bit 5 Bit 4 GIE PEIE TMR0IE PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE -- TMR2IE TMR1IE 79 PIE2 OSFIE C2IE C1IE -- BCL1IE NCO1IE -- -- 80 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF -- TMR2IF TMR1IF 82 PIR2 OSFIF C2IF C1IF -- BCL1IF NCO1IF -- -- 83 -- -- TRISA5 TRISA4 --(1) TRISA2 TRISA1 TRISA0 114 TRISA SSP1ADD SSP1BUF SSP1CON1 ADD<7:0> 235 MSSP Receive Buffer/Transmit Register 187* WCOL SSPOV SSPEN CKP SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 233 SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 234 SSP1MSK SSP1STAT Legend: * Note 1: SSPM<3:0> 232 MSK<7:0> SMP CKE D/A P 235 S R/W UA BF 231 -- = unimplemented location, read as `0'. Shaded cells are not used by the MSSP module in I2CTM mode. Page provides register information. Unimplemented, read as `1'. 2011 Microchip Technology Inc. Preliminary DS41609A-page 229 PIC16(L)F1508/9 21.7 BAUD RATE GENERATOR The MSSP module has a Baud Rate Generator available for clock generation in both I2C and SPI Master modes. The Baud Rate Generator (BRG) reload value is placed in the SSPxADD register (Register 21-6). When a write occurs to SSPxBUF, the Baud Rate Generator will automatically begin counting down. Once the given operation is complete, the internal clock will automatically stop counting and the clock pin will remain in its last state. module clock line. The logic dictating when the reload signal is asserted depends on the mode the MSSP is being operated in. Table 21-4 demonstrates clock rates based on instruction cycles and the BRG value loaded into SSPxADD. EQUATION 21-1: FOSC FCLOCK = ------------------------------------------------ SSPxADD + 1 4 An internal signal "Reload" in Figure 21-39 triggers the value from SSPxADD to be loaded into the BRG counter. This occurs twice for each oscillation of the FIGURE 21-40: BAUD RATE GENERATOR BLOCK DIAGRAM SSPM<3:0> SSPM<3:0> Reload SSPxADD<7:0> Reload Control SCLx SSPxCLK BRG Down Counter FOSC/2 Note: Values of 0x00, 0x01 and 0x02 are not valid for SSPxADD when used as a Baud Rate Generator for I2C. This is an implementation limitation. TABLE 21-4: Note 1: MSSP CLOCK RATE W/BRG FOSC FCY BRG Value FCLOCK (2 Rollovers of BRG) 16 MHz 4 MHz 09h 400 kHz(1) 16 MHz 4 MHz 0Ch 308 kHz 16 MHz 4 MHz 27h 100 kHz 4 MHz 1 MHz 09h 100 kHz The I2C interface does not conform to the 400 kHz I2C specification (which applies to rates greater than 100 kHz) in all details, but may be used with care where higher rates are required by the application. DS41609A-page 230 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 REGISTER 21-1: SSPSTAT: SSP STATUS REGISTER R/W-0/0 R/W-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 SMP: SPI Data Input Sample bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave mode: SMP must be cleared when SPI is used in Slave mode In I2 C Master or Slave mode: 1 = Slew rate control disabled for standard speed mode (100 kHz and 1 MHz) 0 = Slew rate control enabled for high speed mode (400 kHz) bit 6 CKE: SPI Clock Edge Select bit (SPI mode only) In SPI Master or Slave mode: 1 = Transmit occurs on transition from active to Idle clock state 0 = Transmit occurs on transition from Idle to active clock state In I2 CTM mode only: 1 = Enable input logic so that thresholds are compliant with SMBus specification 0 = Disable SMBus specific inputs bit 5 bit 4 D/A: Data/Address bit (I2C mode only) 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address P: Stop bit (I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.) 1 = Indicates that a Stop bit has been detected last (this bit is `0' on Reset) 0 = Stop bit was not detected last bit 3 S: Start bit (I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.) 1 = Indicates that a Start bit has been detected last (this bit is `0' on Reset) 0 = Start bit was not detected last bit 2 R/W: Read/Write bit information (I2C mode only) This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit, or not ACK bit. In I2 C Slave mode: 1 = Read 0 = Write In I2 C Master mode: 1 = Transmit is in progress 0 = Transmit is not in progress OR-ing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Idle mode. bit 1 UA: Update Address bit (10-bit I2C mode only) 1 = Indicates that the user needs to update the address in the SSPxADD register 0 = Address does not need to be updated bit 0 BF: Buffer Full Status bit Receive (SPI and I2 C modes): 1 = Receive complete, SSPxBUF is full 0 = Receive not complete, SSPxBUF is empty Transmit (I2 C mode only): 1 = Data transmit in progress (does not include the ACK and Stop bits), SSPxBUF is full 0 = Data transmit complete (does not include the ACK and Stop bits), SSPxBUF is empty 2011 Microchip Technology Inc. Preliminary DS41609A-page 231 PIC16(L)F1508/9 REGISTER 21-2: SSPXCON1: SSP CONTROL REGISTER 1 R/C/HS-0/0 R/C/HS-0/0 R/W-0/0 R/W-0/0 WCOL SSPOV SSPEN CKP R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 SSPM<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared HS = Bit is set by hardware C = User cleared bit 7 WCOL: Write Collision Detect bit Master mode: 1 = A write to the SSPxBUF register was attempted while the I2C conditions were not valid for a transmission to be started 0 = No collision Slave mode: 1 = The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision bit 6 SSPOV: Receive Overflow Indicator bit(1) In SPI mode: 1 = A new byte is received while the SSPxBUF register is still holding the previous data. In case of overflow, the data in SSPxSR is lost. Overflow can only occur in Slave mode. In Slave mode, the user must read the SSPxBUF, even if only transmitting data, to avoid setting overflow. In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPxBUF register (must be cleared in software). 0 = No overflow 2 In I C mode: 1 = A byte is received while the SSPxBUF register is still holding the previous byte. SSPOV is a "don't care" in Transmit mode (must be cleared in software). 0 = No overflow bit 5 SSPEN: Synchronous Serial Port Enable bit In both modes, when enabled, these pins must be properly configured as input or output In SPI mode: 1 = Enables serial port and configures SCKx, SDOx, SDIx and SSx as the source of the serial port pins(2) 0 = Disables serial port and configures these pins as I/O port pins In I2C mode: 1 = Enables the serial port and configures the SDAx and SCLx pins as the source of the serial port pins(3) 0 = Disables serial port and configures these pins as I/O port pins bit 4 CKP: Clock Polarity Select bit In SPI mode: 1 = Idle state for clock is a high level 0 = Idle state for clock is a low level In I2C Slave mode: SCLx release control 1 = Enable clock 0 = Holds clock low (clock stretch). (Used to ensure data setup time.) In I2C Master mode: Unused in this mode bit 3-0 SSPM<3:0>: Synchronous Serial Port Mode Select bits 0000 = SPI Master mode, clock = FOSC/4 0001 = SPI Master mode, clock = FOSC/16 0010 = SPI Master mode, clock = FOSC/64 0011 = SPI Master mode, clock = TMR2 output/2 0100 = SPI Slave mode, clock = SCKx pin, SS pin control enabled 0101 = SPI Slave mode, clock = SCKx pin, SS pin control disabled, SSx can be used as I/O pin 0110 = I2C Slave mode, 7-bit address 0111 = I2C Slave mode, 10-bit address 1000 = I2C Master mode, clock = FOSC/(4 * (SSPxADD+1))(4) 1001 = Reserved 1010 = SPI Master mode, clock = FOSC/(4 * (SSPxADD+1))(5) 1011 = I2C firmware controlled Master mode (Slave idle) 1100 = Reserved 1101 = Reserved 1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled 1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled Note 1: 2: 3: 4: 5: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPxBUF register. When enabled, these pins must be properly configured as input or output. When enabled, the SDAx and SCLx pins must be configured as inputs. SSPxADD values of 0, 1 or 2 are not supported for I2C mode. SSPxADD value of `0' is not supported. Use SSPM = 0000 instead. DS41609A-page 232 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 REGISTER 21-3: SSPXCON2: SSP CONTROL REGISTER 2 R/W-0/0 R-0/0 R/W-0/0 R/S/HS-0/0 R/S/HS-0/0 R/S/HS-0/0 R/S/HS-0/0 R/W/HS-0/0 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared HC = Cleared by hardware S = User set bit 7 GCEN: General Call Enable bit (in I2C Slave mode only) 1 = Enable interrupt when a general call address (0x00 or 00h) is received in the SSPxSR 0 = General call address disabled bit 6 ACKSTAT: Acknowledge Status bit (in I2C mode only) 1 = Acknowledge was not received 0 = Acknowledge was received bit 5 ACKDT: Acknowledge Data bit (in I2C mode only) In Receive mode: Value transmitted when the user initiates an Acknowledge sequence at the end of a receive 1 = Not Acknowledge 0 = Acknowledge bit 4 ACKEN: Acknowledge Sequence Enable bit (in I2C Master mode only) In Master Receive mode: 1 = Initiate Acknowledge sequence on SDAx and SCLx pins, and transmit ACKDT data bit. Automatically cleared by hardware. 0 = Acknowledge sequence idle bit 3 RCEN: Receive Enable bit (in I2C Master mode only) 1 = Enables Receive mode for I2C 0 = Receive idle bit 2 PEN: Stop Condition Enable bit (in I2C Master mode only) SCKx Release Control: 1 = Initiate Stop condition on SDAx and SCLx pins. Automatically cleared by hardware. 0 = Stop condition Idle bit 1 RSEN: Repeated Start Condition Enabled bit (in I2C Master mode only) 1 = Initiate Repeated Start condition on SDAx and SCLx pins. Automatically cleared by hardware. 0 = Repeated Start condition Idle bit 0 SEN: Start Condition Enabled bit (in I2C Master mode only) In Master mode: 1 = Initiate Start condition on SDAx and SCLx pins. Automatically cleared by hardware. 0 = Start condition Idle In Slave mode: 1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled) 0 = Clock stretching is disabled Note 1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode, this bit may not be set (no spooling) and the SSPxBUF may not be written (or writes to the SSPxBUF are disabled). 2011 Microchip Technology Inc. Preliminary DS41609A-page 233 PIC16(L)F1508/9 REGISTER 21-4: SSPXCON3: SSP CONTROL REGISTER 3 R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 ACKTIM: Acknowledge Time Status bit (I2C mode only)(3) 1 = Indicates the I2C bus is in an Acknowledge sequence, set on 8TH falling edge of SCLx clock 0 = Not an Acknowledge sequence, cleared on 9TH rising edge of SCLx clock bit 6 PCIE: Stop Condition Interrupt Enable bit (I2C mode only) 1 = Enable interrupt on detection of Stop condition 0 = Stop detection interrupts are disabled(2) bit 5 SCIE: Start Condition Interrupt Enable bit (I2C mode only) 1 = Enable interrupt on detection of Start or Restart conditions 0 = Start detection interrupts are disabled(2) bit 4 BOEN: Buffer Overwrite Enable bit In SPI Slave mode:(1) 1 = SSPxBUF updates every time that a new data byte is shifted in ignoring the BF bit 0 = If new byte is received with BF bit of the SSPxSTAT register already set, SSPOV bit of the SSPxCON1 register is set, and the buffer is not updated In I2C Master mode: This bit is ignored. In I2C Slave mode: 1 = SSPxBUF is updated and ACK is generated for a received address/data byte, ignoring the state of the SSPOV bit only if the BF bit = 0. 0 = SSPxBUF is only updated when SSPOV is clear bit 3 SDAHT: SDAx Hold Time Selection bit (I2C mode only) 1 = Minimum of 300 ns hold time on SDAx after the falling edge of SCLx 0 = Minimum of 100 ns hold time on SDAx after the falling edge of SCLx bit 2 SBCDE: Slave Mode Bus Collision Detect Enable bit (I2C Slave mode only) If on the rising edge of SCLx, SDAx is sampled low when the module is outputting a high state, the BCLxIF bit of the PIR2 register is set, and bus goes idle 1 = Enable slave bus collision interrupts 0 = Slave bus collision interrupts are disabled bit 1 AHEN: Address Hold Enable bit (I2C Slave mode only) 1 = Following the 8th falling edge of SCLx for a matching received address byte, CKP bit of the SSPxCON1 register will be cleared and the SCLx will be held low. 0 = Address holding is disabled bit 0 DHEN: Data Hold Enable bit (I2C Slave mode only) 1 = Following the 8th falling edge of SCLx for a received data byte, slave hardware clears the CKP bit of the SSPxCON1 register and SCLx is held low. 0 = Data holding is disabled Note 1: 2: 3: For daisy-chained SPI operation, allows the user to ignore all but the last received byte. SSPOV is still set when a new byte is received and BF = 1, but hardware continues to write the most recent byte to SSPxBUF. This bit has no effect in Slave modes that Start and Stop condition detection is explicitly listed as enabled. The ACKTIM Status bit is only active when the AHEN bit or DHEN bit is set. DS41609A-page 234 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 REGISTER 21-5: R/W-1/1 SSPXMSK: SSP MASK REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 MSK<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-1 MSK<7:1>: Mask bits 1 = The received address bit n is compared to SSPxADD<n> to detect I2C address match 0 = The received address bit n is not used to detect I2C address match bit 0 MSK<0>: Mask bit for I2C Slave mode, 10-bit Address I2C Slave mode, 10-bit address (SSPM<3:0> = 0111 or 1111): 1 = The received address bit 0 is compared to SSPxADD<0> to detect I2C address match 0 = The received address bit 0 is not used to detect I2C address match I2C Slave mode, 7-bit address, the bit is ignored REGISTER 21-6: R/W-0/0 SSPXADD: MSSP ADDRESS AND BAUD RATE REGISTER (I2C MODE) R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 ADD<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared Master mode: bit 7-0 ADD<7:0>: Baud Rate Clock Divider bits SCLx pin clock period = ((ADD<7:0> + 1) *4)/FOSC 10-Bit Slave mode -- Most Significant Address Byte: bit 7-3 Not used: Unused for Most Significant Address Byte. Bit state of this register is a "don't care". Bit pattern sent by master is fixed by I2C specification and must be equal to `11110'. However, those bits are compared by hardware and are not affected by the value in this register. bit 2-1 ADD<2:1>: Two Most Significant bits of 10-bit address bit 0 Not used: Unused in this mode. Bit state is a "don't care". 10-Bit Slave mode -- Least Significant Address Byte: bit 7-0 ADD<7:0>: Eight Least Significant bits of 10-bit address 7-Bit Slave mode: bit 7-1 ADD<7:1>: 7-bit address bit 0 Not used: Unused in this mode. Bit state is a "don't care". 2011 Microchip Technology Inc. Preliminary DS41609A-page 235 PIC16(L)F1508/9 NOTES: DS41609A-page 236 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 22.0 ENHANCED UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (EUSART) The EUSART module includes the following capabilities: * * * * * * * * * * Full-duplex asynchronous transmit and receive Two-character input buffer One-character output buffer Programmable 8-bit or 9-bit character length Address detection in 9-bit mode Input buffer overrun error detection Received character framing error detection Half-duplex synchronous master Half-duplex synchronous slave Programmable clock polarity in synchronous modes * Sleep operation The Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) module is a serial I/O communications peripheral. It contains all the clock generators, shift registers and data buffers necessary to perform an input or output serial data transfer independent of device program execution. The EUSART, also known as a Serial Communications Interface (SCI), can be configured as a full-duplex asynchronous system or half-duplex synchronous system. Full-Duplex mode is useful for communications with peripheral systems, such as CRT terminals and personal computers. Half-Duplex Synchronous mode is intended for communications with peripheral devices, such as A/D or D/A integrated circuits, serial EEPROMs or other microcontrollers. These devices typically do not have internal clocks for baud rate generation and require the external clock signal provided by a master synchronous device. FIGURE 22-1: The EUSART module implements the following additional features, making it ideally suited for use in Local Interconnect Network (LIN) bus systems: * Automatic detection and calibration of the baud rate * Wake-up on Break reception * 13-bit Break character transmit Block diagrams of the EUSART transmitter and receiver are shown in Figure 22-1 and Figure 22-2. EUSART TRANSMIT BLOCK DIAGRAM Data Bus TXIE Interrupt TXIF TXREG Register 8 MSb TX/CK pin LSb (8) * * * 0 Pin Buffer and Control TRMT SPEN Transmit Shift Register (TSR) TXEN Baud Rate Generator FOSC TX9 n BRG16 +1 SPBRGH /n SPBRGL Multiplier x4 x16 x64 SYNC 1 X 0 0 0 BRGH X 1 1 0 0 BRG16 X 1 0 1 0 2011 Microchip Technology Inc. TX9D Preliminary DS41609A-page 237 PIC16(L)F1508/9 FIGURE 22-2: EUSART RECEIVE BLOCK DIAGRAM SPEN CREN RX/DT pin Baud Rate Generator Data Recovery FOSC SPBRGH SPBRGL x4 x16 x64 SYNC 1 X 0 0 0 BRGH X 1 1 0 0 BRG16 X 1 0 1 0 (8) *** 7 1 LSb 0 START RX9 /n BRG16 Multiplier Stop RCIDL RSR Register MSb Pin Buffer and Control +1 OERR n FERR RX9D RCREG Register 8 FIFO Data Bus RCIF RCIE Interrupt The operation of the EUSART module is controlled through three registers: * Transmit Status and Control (TXSTA) * Receive Status and Control (RCSTA) * Baud Rate Control (BAUDCON) These registers are detailed in Register 22-1, Register 22-2 and Register 22-3, respectively. When the receiver or transmitter section is not enabled then the corresponding RX or TX pin may be used for general purpose input and output. DS41609A-page 238 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 22.1 EUSART Asynchronous Mode 22.1.1.2 The EUSART transmits and receives data using the standard non-return-to-zero (NRZ) format. NRZ is implemented with two levels: a VOH mark state which represents a `1' data bit, and a VOL space state which represents a `0' data bit. NRZ refers to the fact that consecutively transmitted data bits of the same value stay at the output level of that bit without returning to a neutral level between each bit transmission. An NRZ transmission port idles in the mark state. Each character transmission consists of one Start bit followed by eight or nine data bits and is always terminated by one or more Stop bits. The Start bit is always a space and the Stop bits are always marks. The most common data format is 8 bits. Each transmitted bit persists for a period of 1/(Baud Rate). An on-chip dedicated 8-bit/16-bit Baud Rate Generator is used to derive standard baud rate frequencies from the system oscillator. See Table 22-5 for examples of baud rate configurations. The EUSART transmits and receives the LSb first. The EUSART's transmitter and receiver are functionally independent, but share the same data format and baud rate. Parity is not supported by the hardware, but can be implemented in software and stored as the ninth data bit. 22.1.1 EUSART ASYNCHRONOUS TRANSMITTER 22.1.1.1 Enabling the Transmitter The EUSART transmitter is enabled for asynchronous operations by configuring the following three control bits: * TXEN = 1 * SYNC = 0 * SPEN = 1 All other EUSART control bits are assumed to be in their default state. Setting the TXEN bit of the TXSTA register enables the transmitter circuitry of the EUSART. Clearing the SYNC bit of the TXSTA register configures the EUSART for asynchronous operation. Setting the SPEN bit of the RCSTA register enables the EUSART and automatically configures the TX/CK I/O pin as an output. If the TX/CK pin is shared with an analog peripheral, the analog I/O function must be disabled by clearing the corresponding ANSEL bit. Note: A transmission is initiated by writing a character to the TXREG register. If this is the first character, or the previous character has been completely flushed from the TSR, the data in the TXREG is immediately transferred to the TSR register. If the TSR still contains all or part of a previous character, the new character data is held in the TXREG until the Stop bit of the previous character has been transmitted. The pending character in the TXREG is then transferred to the TSR in one TCY immediately following the Stop bit transmission. The transmission of the Start bit, data bits and Stop bit sequence commences immediately following the transfer of the data to the TSR from the TXREG. 22.1.1.3 Transmit Data Polarity The polarity of the transmit data can be controlled with the SCKP bit of the BAUDCON register. The default state of this bit is `0' which selects high true transmit idle and data bits. Setting the SCKP bit to `1' will invert the transmit data resulting in low true idle and data bits. The SCKP bit controls transmit data polarity in Asynchronous mode only. In Synchronous mode, the SCKP bit has a different function. See Section 22.4.1.2 "Clock Polarity". 22.1.1.4 The EUSART transmitter block diagram is shown in Figure 22-1. The heart of the transmitter is the serial Transmit Shift Register (TSR), which is not directly accessible by software. The TSR obtains its data from the transmit buffer, which is the TXREG register. Transmitting Data Transmit Interrupt Flag The TXIF interrupt flag bit of the PIR1 register is set whenever the EUSART transmitter is enabled and no character is being held for transmission in the TXREG. In other words, the TXIF bit is only clear when the TSR is busy with a character and a new character has been queued for transmission in the TXREG. The TXIF flag bit is not cleared immediately upon writing TXREG. TXIF becomes valid in the second instruction cycle following the write execution. Polling TXIF immediately following the TXREG write will return invalid results. The TXIF bit is read-only, it cannot be set or cleared by software. The TXIF interrupt can be enabled by setting the TXIE interrupt enable bit of the PIE1 register. However, the TXIF flag bit will be set whenever the TXREG is empty, regardless of the state of TXIE enable bit. To use interrupts when transmitting data, set the TXIE bit only when there is more data to send. Clear the TXIE interrupt enable bit upon writing the last character of the transmission to the TXREG. The TXIF Transmitter Interrupt flag is set when the TXEN enable bit is set. 2011 Microchip Technology Inc. Preliminary DS41609A-page 239 PIC16(L)F1508/9 22.1.1.5 TSR Status 22.1.1.7 The TRMT bit of the TXSTA register indicates the status of the TSR register. This is a read-only bit. The TRMT bit is set when the TSR register is empty and is cleared when a character is transferred to the TSR register from the TXREG. The TRMT bit remains clear until all bits have been shifted out of the TSR register. No interrupt logic is tied to this bit, so the user has to poll this bit to determine the TSR status. Note: 22.1.1.6 1. 2. 3. The TSR register is not mapped in data memory, so it is not available to the user. 4. 5. Transmitting 9-Bit Characters The EUSART supports 9-bit character transmissions. When the TX9 bit of the TXSTA register is set, the EUSART will shift 9 bits out for each character transmitted. The TX9D bit of the TXSTA register is the ninth, and Most Significant, data bit. When transmitting 9-bit data, the TX9D data bit must be written before writing the 8 Least Significant bits into the TXREG. All nine bits of data will be transferred to the TSR shift register immediately after the TXREG is written. A special 9-bit Address mode is available for use with multiple receivers. See Section 22.1.2.7 "Address Detection" for more information on the address mode. FIGURE 22-3: Write to TXREG BRG Output (Shift Clock) 8. Word 1 Start bit bit 0 bit 1 bit 7/8 Stop bit Word 1 TXIF bit (Transmit Buffer Reg. Empty Flag) FIGURE 22-4: 7. Initialize the SPBRGH, SPBRGL register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 22.3 "EUSART Baud Rate Generator (BRG)"). Enable the asynchronous serial port by clearing the SYNC bit and setting the SPEN bit. If 9-bit transmission is desired, set the TX9 control bit. A set ninth data bit will indicate that the 8 Least Significant data bits are an address when the receiver is set for address detection. Set SCKP bit if inverted transmit is desired. Enable the transmission by setting the TXEN control bit. This will cause the TXIF interrupt bit to be set. If interrupts are desired, set the TXIE interrupt enable bit of the PIE1 register. An interrupt will occur immediately provided that the GIE and PEIE bits of the INTCON register are also set. If 9-bit transmission is selected, the ninth bit should be loaded into the TX9D data bit. Load 8-bit data into the TXREG register. This will start the transmission. ASYNCHRONOUS TRANSMISSION TX/CK pin TRMT bit (Transmit Shift Reg. Empty Flag) 6. Asynchronous Transmission Set-up: 1 TCY Word 1 Transmit Shift Reg. ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK) Write to TXREG BRG Output (Shift Clock) Word 1 TX/CK pin TXIF bit (Transmit Buffer Reg. Empty Flag) TRMT bit (Transmit Shift Reg. Empty Flag) Note: Word 2 Start bit bit 0 1 TCY bit 1 Word 1 bit 7/8 Stop bit Start bit bit 0 Word 2 1 TCY Word 1 Transmit Shift Reg. Word 2 Transmit Shift Reg. This timing diagram shows two consecutive transmissions. DS41609A-page 240 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 TABLE 22-1: SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ABDOVF RCIDL -- SCKP BRG16 -- WUE ABDEN 248 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 78 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE -- TMR2IE TMR1IE 79 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF -- TMR2IF TMR1IF 82 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 247* Name BAUDCON INTCON RCSTA SPBRGL BRG<7:0> 249* SPBRGH BRG<15:8> 249* TRISC TXREG TXSTA TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 EUSART Transmit Data Register CSRC TX9 TXEN 122 239 SYNC SENDB BRGH TRMT TX9D 246 Legend: -- = unimplemented location, read as `0'. Shaded cells are not used for asynchronous transmission. * Page provides register information. 2011 Microchip Technology Inc. Preliminary DS41609A-page 241 PIC16(L)F1508/9 22.1.2 EUSART ASYNCHRONOUS RECEIVER 22.1.2.2 The Asynchronous mode is typically used in RS-232 systems. The receiver block diagram is shown in Figure 22-2. The data is received on the RX/DT pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at 16 times the baud rate, whereas the serial Receive Shift Register (RSR) operates at the bit rate. When all 8 or 9 bits of the character have been shifted in, they are immediately transferred to a two character First-In-First-Out (FIFO) memory. The FIFO buffering allows reception of two complete characters and the start of a third character before software must start servicing the EUSART receiver. The FIFO and RSR registers are not directly accessible by software. Access to the received data is via the RCREG register. 22.1.2.1 Enabling the Receiver The EUSART receiver is enabled for asynchronous operation by configuring the following three control bits: * CREN = 1 * SYNC = 0 * SPEN = 1 All other EUSART control bits are assumed to be in their default state. Setting the CREN bit of the RCSTA register enables the receiver circuitry of the EUSART. Clearing the SYNC bit of the TXSTA register configures the EUSART for asynchronous operation. Setting the SPEN bit of the RCSTA register enables the EUSART. The programmer must set the corresponding TRIS bit to configure the RX/DT I/O pin as an input. Note: If the RX/DT function is on an analog pin, the corresponding ANSEL bit must be cleared for the receiver to function. Receiving Data The receiver data recovery circuit initiates character reception on the falling edge of the first bit. The first bit, also known as the Start bit, is always a zero. The data recovery circuit counts one-half bit time to the center of the Start bit and verifies that the bit is still a zero. If it is not a zero then the data recovery circuit aborts character reception, without generating an error, and resumes looking for the falling edge of the Start bit. If the Start bit zero verification succeeds then the data recovery circuit counts a full bit time to the center of the next bit. The bit is then sampled by a majority detect circuit and the resulting `0' or `1' is shifted into the RSR. This repeats until all data bits have been sampled and shifted into the RSR. One final bit time is measured and the level sampled. This is the Stop bit, which is always a `1'. If the data recovery circuit samples a `0' in the Stop bit position then a framing error is set for this character, otherwise the framing error is cleared for this character. See Section 22.1.2.4 "Receive Framing Error" for more information on framing errors. Immediately after all data bits and the Stop bit have been received, the character in the RSR is transferred to the EUSART receive FIFO and the RCIF interrupt flag bit of the PIR1 register is set. The top character in the FIFO is transferred out of the FIFO by reading the RCREG register. Note: 22.1.2.3 If the receive FIFO is overrun, no additional characters will be received until the overrun condition is cleared. See Section 22.1.2.5 "Receive Overrun Error" for more information on overrun errors. Receive Interrupts The RCIF interrupt flag bit of the PIR1 register is set whenever the EUSART receiver is enabled and there is an unread character in the receive FIFO. The RCIF interrupt flag bit is read-only, it cannot be set or cleared by software. RCIF interrupts are enabled by setting all of the following bits: * RCIE interrupt enable bit of the PIE1 register * PEIE peripheral interrupt enable bit of the INTCON register * GIE Global Interrupt Enable bit of the INTCON register The RCIF interrupt flag bit will be set when there is an unread character in the FIFO, regardless of the state of interrupt enable bits. DS41609A-page 242 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 22.1.2.4 Receive Framing Error 22.1.2.7 Each character in the receive FIFO buffer has a corresponding framing error Status bit. A framing error indicates that a Stop bit was not seen at the expected time. The framing error status is accessed via the FERR bit of the RCSTA register. The FERR bit represents the status of the top unread character in the receive FIFO. Therefore, the FERR bit must be read before reading the RCREG. The FERR bit is read-only and only applies to the top unread character in the receive FIFO. A framing error (FERR = 1) does not preclude reception of additional characters. It is not necessary to clear the FERR bit. Reading the next character from the FIFO buffer will advance the FIFO to the next character and the next corresponding framing error. The FERR bit can be forced clear by clearing the SPEN bit of the RCSTA register which resets the EUSART. Clearing the CREN bit of the RCSTA register does not affect the FERR bit. A framing error by itself does not generate an interrupt. Note: 22.1.2.5 Address Detection A special Address Detection mode is available for use when multiple receivers share the same transmission line, such as in RS-485 systems. Address detection is enabled by setting the ADDEN bit of the RCSTA register. Address detection requires 9-bit character reception. When address detection is enabled, only characters with the ninth data bit set will be transferred to the receive FIFO buffer, thereby setting the RCIF interrupt bit. All other characters will be ignored. Upon receiving an address character, user software determines if the address matches its own. Upon address match, user software must disable address detection by clearing the ADDEN bit before the next Stop bit occurs. When user software detects the end of the message, determined by the message protocol used, software places the receiver back into the Address Detection mode by setting the ADDEN bit. If all receive characters in the receive FIFO have framing errors, repeated reads of the RCREG will not clear the FERR bit. Receive Overrun Error The receive FIFO buffer can hold two characters. An overrun error will be generated if a third character, in its entirety, is received before the FIFO is accessed. When this happens the OERR bit of the RCSTA register is set. The characters already in the FIFO buffer can be read but no additional characters will be received until the error is cleared. The error must be cleared by either clearing the CREN bit of the RCSTA register or by resetting the EUSART by clearing the SPEN bit of the RCSTA register. 22.1.2.6 Receiving 9-bit Characters The EUSART supports 9-bit character reception. When the RX9 bit of the RCSTA register is set the EUSART will shift 9 bits into the RSR for each character received. The RX9D bit of the RCSTA register is the ninth and Most Significant data bit of the top unread character in the receive FIFO. When reading 9-bit data from the receive FIFO buffer, the RX9D data bit must be read before reading the 8 Least Significant bits from the RCREG. 2011 Microchip Technology Inc. Preliminary DS41609A-page 243 PIC16(L)F1508/9 22.1.2.8 Asynchronous Reception Set-up: 22.1.2.9 1. Initialize the SPBRGH, SPBRGL register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 22.3 "EUSART Baud Rate Generator (BRG)"). 2. Clear the ANSEL bit for the RX pin (if applicable). 3. Enable the serial port by setting the SPEN bit. The SYNC bit must be clear for asynchronous operation. 4. If interrupts are desired, set the RCIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. 5. If 9-bit reception is desired, set the RX9 bit. 6. Enable reception by setting the CREN bit. 7. The RCIF interrupt flag bit will be set when a character is transferred from the RSR to the receive buffer. An interrupt will be generated if the RCIE interrupt enable bit was also set. 8. Read the RCSTA register to get the error flags and, if 9-bit data reception is enabled, the ninth data bit. 9. Get the received 8 Least Significant data bits from the receive buffer by reading the RCREG register. 10. If an overrun occurred, clear the OERR flag by clearing the CREN receiver enable bit. FIGURE 22-5: Rcv Shift Reg Rcv Buffer Reg. RCIDL This mode would typically be used in RS-485 systems. To set up an Asynchronous Reception with Address Detect Enable: 1. Initialize the SPBRGH, SPBRGL register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 22.3 "EUSART Baud Rate Generator (BRG)"). 2. Clear the ANSEL bit for the RX pin (if applicable). 3. Enable the serial port by setting the SPEN bit. The SYNC bit must be clear for asynchronous operation. 4. If interrupts are desired, set the RCIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. 5. Enable 9-bit reception by setting the RX9 bit. 6. Enable address detection by setting the ADDEN bit. 7. Enable reception by setting the CREN bit. 8. The RCIF interrupt flag bit will be set when a character with the ninth bit set is transferred from the RSR to the receive buffer. An interrupt will be generated if the RCIE interrupt enable bit was also set. 9. Read the RCSTA register to get the error flags. The ninth data bit will always be set. 10. Get the received 8 Least Significant data bits from the receive buffer by reading the RCREG register. Software determines if this is the device's address. 11. If an overrun occurred, clear the OERR flag by clearing the CREN receiver enable bit. 12. If the device has been addressed, clear the ADDEN bit to allow all received data into the receive buffer and generate interrupts. ASYNCHRONOUS RECEPTION Start bit bit 0 RX/DT pin 9-bit Address Detection Mode Set-up bit 1 bit 7/8 Stop bit Start bit bit 0 Word 1 RCREG bit 7/8 Stop bit Start bit bit 7/8 Stop bit Word 2 RCREG Read Rcv Buffer Reg. RCREG RCIF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set. DS41609A-page 244 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 TABLE 22-2: SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ABDOVF RCIDL -- SCKP BRG16 -- WUE ABDEN 248 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 78 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE -- TMR2IE TMR1IE 79 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF -- TMR2IF TMR1IF Name BAUDCON INTCON RCREG RCSTA EUSART Receive Data Register SPEN RX9 SREN SPBRGL CREN ADDEN FERR OERR RX9D BRG<7:0> SPBRGH TRISC TRISC7 TRISC6 TXSTA CSRC TX9 TXEN 247* 249* BRG<15:8> TRISC5 82 242* 249* TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 122 SYNC SENDB BRGH TRMT TX9D 246 Legend: -- = unimplemented location, read as `0'. Shaded cells are not used for asynchronous reception. * Page provides register information. 2011 Microchip Technology Inc. Preliminary DS41609A-page 245 PIC16(L)F1508/9 22.2 Clock Accuracy with Asynchronous Operation The factory calibrates the internal oscillator block output (INTOSC). However, the INTOSC frequency may drift as VDD or temperature changes, and this directly affects the asynchronous baud rate. Two methods may be used to adjust the baud rate clock, but both require a reference clock source of some kind. REGISTER 22-1: The first (preferred) method uses the OSCTUNE register to adjust the INTOSC output. Adjusting the value in the OSCTUNE register allows for fine resolution changes to the system clock source. See Section 5.2.2 "Internal Clock Sources" for more information. The other method adjusts the value in the Baud Rate Generator. This can be done automatically with the Auto-Baud Detect feature (see Section 22.3.1 "Auto-Baud Detect"). There may not be fine enough resolution when adjusting the Baud Rate Generator to compensate for a gradual change in the peripheral clock frequency. TXSTA: TRANSMIT STATUS AND CONTROL REGISTER R/W-/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-1/1 R/W-0/0 CSRC TX9 TXEN(1) SYNC SENDB BRGH TRMT TX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don't care Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external source) bit 6 TX9: 9-bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission bit 5 TXEN: Transmit Enable bit(1) 1 = Transmit enabled 0 = Transmit disabled bit 4 SYNC: EUSART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode bit 3 SENDB: Send Break Character bit Asynchronous mode: 1 = Send Sync Break on next transmission (cleared by hardware upon completion) 0 = Sync Break transmission completed Synchronous mode: Don't care bit 2 BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speed Synchronous mode: Unused in this mode bit 1 TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full bit 0 TX9D: Ninth bit of Transmit Data Can be address/data bit or a parity bit. Note 1: SREN/CREN overrides TXEN in Sync mode. DS41609A-page 246 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 RCSTA: RECEIVE STATUS AND CONTROL REGISTER(1) REGISTER 22-2: R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-0/0 R-0/0 R-0/0 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins) 0 = Serial port disabled (held in Reset) bit 6 RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5 SREN: Single Receive Enable bit Asynchronous mode: Don't care Synchronous mode - Master: 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode - Slave Don't care bit 4 CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables receiver 0 = Disables receiver Synchronous mode: 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) 0 = Disables continuous receive bit 3 ADDEN: Address Detect Enable bit Asynchronous mode 9-bit (RX9 = 1): 1 = Enables address detection, enable interrupt and load the receive buffer when RSR<8> is set 0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit Asynchronous mode 8-bit (RX9 = 0): Don't care bit 2 FERR: Framing Error bit 1 = Framing error (can be updated by reading RCREG register and receive next valid byte) 0 = No framing error bit 1 OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN) 0 = No overrun error bit 0 RX9D: Ninth bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware. 2011 Microchip Technology Inc. Preliminary DS41609A-page 247 PIC16(L)F1508/9 REGISTER 22-3: BAUDCON: BAUD RATE CONTROL REGISTER R-0/0 R-1/1 U-0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 ABDOVF RCIDL -- SCKP BRG16 -- WUE ABDEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 ABDOVF: Auto-Baud Detect Overflow bit Asynchronous mode: 1 = Auto-baud timer overflowed 0 = Auto-baud timer did not overflow Synchronous mode: Don't care bit 6 RCIDL: Receive Idle Flag bit Asynchronous mode: 1 = Receiver is idle 0 = Start bit has been received and the receiver is receiving Synchronous mode: Don't care bit 5 Unimplemented: Read as `0' bit 4 SCKP: Synchronous Clock Polarity Select bit Asynchronous mode: 1 = Transmit inverted data to the TX/CK pin 0 = Transmit non-inverted data to the TX/CK pin Synchronous mode: 1 = Data is clocked on rising edge of the clock 0 = Data is clocked on falling edge of the clock bit 3 BRG16: 16-bit Baud Rate Generator bit 1 = 16-bit Baud Rate Generator is used 0 = 8-bit Baud Rate Generator is used bit 2 Unimplemented: Read as `0' bit 1 WUE: Wake-up Enable bit Asynchronous mode: 1 = Receiver is waiting for a falling edge. No character will be received, byte RCIF will be set. WUE will automatically clear after RCIF is set. 0 = Receiver is operating normally Synchronous mode: Don't care bit 0 ABDEN: Auto-Baud Detect Enable bit Asynchronous mode: 1 = Auto-Baud Detect mode is enabled (clears when auto-baud is complete) 0 = Auto-Baud Detect mode is disabled Synchronous mode: Don't care DS41609A-page 248 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 22.3 EUSART Baud Rate Generator (BRG) EXAMPLE 22-1: The Baud Rate Generator (BRG) is an 8-bit or 16-bit timer that is dedicated to the support of both the asynchronous and synchronous EUSART operation. By default, the BRG operates in 8-bit mode. Setting the BRG16 bit of the BAUDCON register selects 16-bit mode. For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG: F OS C Desired Baud Rate = -----------------------------------------------------------------------64 [SPBRGH:SPBRGL] + 1 Solving for SPBRGH:SPBRGL: FOSC --------------------------------------------Desired Baud Rate X = --------------------------------------------- - 1 64 The SPBRGH, SPBRGL register pair determines the period of the free running baud rate timer. In Asynchronous mode the multiplier of the baud rate period is determined by both the BRGH bit of the TXSTA register and the BRG16 bit of the BAUDCON register. In Synchronous mode, the BRGH bit is ignored. Table 22-3 contains the formulas for determining the baud rate. Example 22-1 provides a sample calculation for determining the baud rate and baud rate error. CALCULATING BAUD RATE ERROR 16000000 -----------------------9600 = ------------------------ - 1 64 = 25.042 = 25 16000000 Calculated Baud Rate = --------------------------64 25 + 1 Typical baud rates and error values for various Asynchronous modes have been computed for your convenience and are shown in Table 22-3. It may be advantageous to use the high baud rate (BRGH = 1), or the 16-bit BRG (BRG16 = 1) to reduce the baud rate error. The 16-bit BRG mode is used to achieve slow baud rates for fast oscillator frequencies. = 9615 Calc. Baud Rate - Desired Baud Rate Error = -------------------------------------------------------------------------------------------Desired Baud Rate 9615 - 9600 = ---------------------------------- = 0.16% 9600 Writing a new value to the SPBRGH, SPBRGL register pair causes the BRG timer to be reset (or cleared). This ensures that the BRG does not wait for a timer overflow before outputting the new baud rate. If the system clock is changed during an active receive operation, a receive error or data loss may result. To avoid this problem, check the status of the RCIDL bit to make sure that the receive operation is idle before changing the system clock. 2011 Microchip Technology Inc. Preliminary DS41609A-page 249 PIC16(L)F1508/9 TABLE 22-3: BAUD RATE FORMULAS Configuration Bits BRG/EUSART Mode Baud Rate Formula 0 8-bit/Asynchronous FOSC/[64 (n+1)] 0 1 8-bit/Asynchronous 0 1 0 16-bit/Asynchronous 0 1 1 16-bit/Asynchronous 1 0 x 8-bit/Synchronous 1 x 16-bit/Synchronous SYNC BRG16 BRGH 0 0 0 1 Legend: Name BAUDCON SUMMARY OF REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ABDOVF RCIDL -- SCKP BRG16 -- WUE ABDEN 248 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D SPBRGL BRG<7:0> SPBRGH BRG<15:8> TXSTA FOSC/[4 (n+1)] x = Don't care, n = value of SPBRGH, SPBRGL register pair. TABLE 22-4: RCSTA FOSC/[16 (n+1)] CSRC TX9 TXEN SYNC SENDB 247 249* 249* BRGH TRMT TX9D 246 Legend: -- = unimplemented location, read as `0'. Shaded cells are not used for the Baud Rate Generator. * Page provides register information. DS41609A-page 250 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 TABLE 22-5: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0, BRG16 = 0 BAUD RATE FOSC = 20.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 18.432 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 16.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 11.0592 MHz Actual Rate % Error SPBRG value (decimal) 300 -- -- -- -- -- -- -- -- -- -- -- -- 1200 1221 1.73 255 1200 0.00 239 1202 0.16 207 1200 0.00 143 2400 2404 0.16 129 2400 0.00 119 2404 0.16 103 2400 0.00 71 9600 9470 -1.36 32 9600 0.00 29 9615 0.16 25 9600 0.00 17 10417 10417 0.00 29 10286 -1.26 27 10417 0.00 23 10165 -2.42 16 19.2k 19.53k 1.73 15 19.20k 0.00 14 19.23k 0.16 12 19.20k 0.00 8 57.6k -- -- -- 57.60k 0.00 7 -- -- -- 57.60k 0.00 2 115.2k -- -- -- -- -- -- -- -- -- -- -- -- SYNC = 0, BRGH = 0, BRG16 = 0 BAUD RATE FOSC = 8.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 4.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 3.6864 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 1.000 MHz Actual Rate % Error SPBRG value (decimal) 300 -- -- -- 300 0.16 207 300 0.00 191 300 0.16 51 1200 1202 0.16 103 1202 0.16 51 1200 0.00 47 1202 0.16 12 2400 2404 0.16 51 2404 0.16 25 2400 0.00 23 -- -- -- 9600 9615 0.16 12 -- -- -- 9600 0.00 5 -- -- -- 10417 10417 0.00 11 10417 0.00 5 -- -- -- -- -- -- 19.2k -- -- -- -- -- -- 19.20k 0.00 2 -- -- -- 57.6k -- -- -- -- -- -- 57.60k 0.00 0 -- -- -- 115.2k -- -- -- -- -- -- -- -- -- -- -- -- SYNC = 0, BRGH = 1, BRG16 = 0 BAUD RATE FOSC = 20.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 18.432 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 16.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 11.0592 MHz Actual Rate % Error SPBRG value (decimal) 300 -- -- -- -- -- -- -- -- -- -- -- -- 1200 -- -- -- -- -- -- -- -- -- -- -- -- 2400 -- -- -- -- -- -- -- -- -- -- -- -- 9600 9615 0.16 129 9600 0.00 119 9615 0.16 103 9600 0.00 71 10417 10417 0.00 119 10378 -0.37 110 10417 0.00 95 10473 0.53 65 19.2k 19.23k 0.16 64 19.20k 0.00 59 19.23k 0.16 51 19.20k 0.00 35 57.6k 56.82k -1.36 21 57.60k 0.00 19 58.82k 2.12 16 57.60k 0.00 11 115.2k 113.64k -1.36 10 115.2k 0.00 9 111.1k -3.55 8 115.2k 0.00 5 2011 Microchip Technology Inc. Preliminary DS41609A-page 251 PIC16(L)F1508/9 TABLE 22-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 0 BAUD RATE FOSC = 8.000 MHz SPBRG Actual % value Rate Error (decimal) FOSC = 4.000 MHz SPBRG Actual % value Rate Error (decimal) FOSC = 3.6864 MHz SPBRG Actual % value Rate Error (decimal) FOSC = 1.000 MHz SPBRG Actual % value Rate Error (decimal) 300 1200 -- -- -- -- -- -- -- 1202 -- 0.16 -- 207 -- 1200 -- 0.00 -- 191 300 1202 0.16 0.16 207 51 2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25 -- 9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 -- -- 10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5 19.2k 19231 0.16 25 19.23k 0.16 12 19.2k 0.00 11 -- -- -- 57.6k 55556 -3.55 8 -- -- -- 57.60k 0.00 3 -- -- -- 115.2k -- -- -- -- -- -- 115.2k 0.00 1 -- -- -- SYNC = 0, BRGH = 0, BRG16 = 1 BAUD RATE FOSC = 20.000 MHz Actual Rate FOSC = 18.432 MHz % Error SPBRG value (decimal) Actual Rate FOSC = 16.000 MHz % Error SPBRG value (decimal) Actual Rate FOSC = 11.0592 MHz % Error SPBRG value (decimal) Actual Rate % Error SPBRG value (decimal) 300 300.0 -0.01 4166 300.0 0.00 3839 300.03 0.01 3332 300.0 0.00 2303 1200 1200 -0.03 1041 1200 0.00 959 1200.5 0.04 832 1200 0.00 575 2400 2399 -0.03 520 2400 0.00 479 2398 -0.08 416 2400 0.00 287 9600 9615 0.16 129 9600 0.00 119 9615 0.16 103 9600 0.00 71 10417 10417 0.00 119 10378 -0.37 110 10417 0.00 95 10473 0.53 65 19.2k 19.23k 0.16 64 19.20k 0.00 59 19.23k 0.16 51 19.20k 0.00 35 57.6k 56.818 -1.36 21 57.60k 0.00 19 58.82k 2.12 16 57.60k 0.00 11 115.2k 113.636 -1.36 10 115.2k 0.00 9 111.11k -3.55 8 115.2k 0.00 5 SYNC = 0, BRGH = 0, BRG16 = 1 BAUD RATE FOSC = 8.000 MHz Actual Rate FOSC = 4.000 MHz % Error SPBRG value (decimal) Actual Rate FOSC = 3.6864 MHz % Error SPBRG value (decimal) Actual Rate FOSC = 1.000 MHz % Error SPBRG value (decimal) Actual Rate % Error SPBRG value (decimal) 300 299.9 -0.02 1666 300.1 0.04 832 300.0 0.00 767 300.5 0.16 207 1200 1199 -0.08 416 1202 0.16 207 1200 0.00 191 1202 0.16 51 2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25 9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 -- -- -- 10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5 19.2k 19.23k 0.16 25 19.23k 0.16 12 19.20k 0.00 11 -- -- -- 57.6k 55556 -3.55 8 -- -- -- 57.60k 0.00 3 -- -- -- 115.2k -- -- -- -- -- -- 115.2k 0.00 1 -- -- -- DS41609A-page 252 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 TABLE 22-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 FOSC = 20.000 MHz SPBRG Actual % value Rate Error (decimal) FOSC = 18.432 MHz SPBRG Actual % value Rate Error (decimal) FOSC = 16.000 MHz SPBRG Actual % value Rate Error (decimal) FOSC = 11.0592 MHz SPBRG Actual % value Rate Error (decimal) 300 1200 300.0 1200 0.00 -0.01 16665 4166 300.0 1200 0.00 0.00 15359 3839 300.0 1200.1 0.00 0.01 13332 3332 300.0 1200 0.00 0.00 9215 2303 2400 2400 0.02 2082 2400 0.00 1919 2399.5 -0.02 1666 2400 0.00 1151 9600 9597 -0.03 520 9600 0.00 479 9592 -0.08 416 9600 0.00 287 10417 10417 0.00 479 10425 0.08 441 10417 0.00 383 10433 0.16 264 BAUD RATE 19.2k 19.23k 0.16 259 19.20k 0.00 239 19.23k 0.16 207 19.20k 0.00 143 57.6k 57.47k -0.22 86 57.60k 0.00 79 57.97k 0.64 68 57.60k 0.00 47 115.2k 116.3k 0.94 42 115.2k 0.00 39 114.29k -0.79 34 115.2k 0.00 23 SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD RATE FOSC = 8.000 MHz Actual Rate FOSC = 4.000 MHz % Error SPBRG value (decimal) Actual Rate FOSC = 3.6864 MHz % Error SPBRG value (decimal) Actual Rate FOSC = 1.000 MHz % Error SPBRG value (decimal) Actual Rate % Error SPBRG value (decimal) 300 300.0 0.00 6666 300.0 0.01 3332 300.0 0.00 3071 300.1 0.04 832 1200 1200 -0.02 1666 1200 0.04 832 1200 0.00 767 1202 0.16 207 2400 2401 0.04 832 2398 0.08 416 2400 0.00 383 2404 0.16 103 9600 9615 0.16 207 9615 0.16 103 9600 0.00 95 9615 0.16 25 10417 10417 0 191 10417 0.00 95 10473 0.53 87 10417 0.00 23 19.2k 19.23k 0.16 103 19.23k 0.16 51 19.20k 0.00 47 19.23k 0.16 12 57.6k 57.14k -0.79 34 58.82k 2.12 16 57.60k 0.00 15 -- -- -- 115.2k 117.6k 2.12 16 111.1k -3.55 8 115.2k 0.00 7 -- -- -- 2011 Microchip Technology Inc. Preliminary DS41609A-page 253 PIC16(L)F1508/9 22.3.1 AUTO-BAUD DETECT The EUSART module supports automatic detection and calibration of the baud rate. In the Auto-Baud Detect (ABD) mode, the clock to the BRG is reversed. Rather than the BRG clocking the incoming RX signal, the RX signal is timing the BRG. The Baud Rate Generator is used to time the period of a received 55h (ASCII "U") which is the Sync character for the LIN bus. The unique feature of this character is that it has five rising edges including the Stop bit edge. Setting the ABDEN bit of the BAUDCON register starts the auto-baud calibration sequence (Figure 22-6). While the ABD sequence takes place, the EUSART state machine is held in Idle. On the first rising edge of the receive line, after the Start bit, the SPBRG begins counting up using the BRG counter clock as shown in Table 22-6. The fifth rising edge will occur on the RX pin at the end of the eighth bit period. At that time, an accumulated value totaling the proper BRG period is left in the SPBRGH, SPBRGL register pair, the ABDEN bit is automatically cleared and the RCIF interrupt flag is set. The value in the RCREG needs to be read to clear the RCIF interrupt. RCREG content should be discarded. When calibrating for modes that do not use the SPBRGH register the user can verify that the SPBRGL register did not overflow by checking for 00h in the SPBRGH register. The BRG auto-baud clock is determined by the BRG16 and BRGH bits as shown in Table 22-6. During ABD, both the SPBRGH and SPBRGL registers are used as a 16-bit counter, independent of the BRG16 bit setting. While calibrating the baud rate period, the SPBRGH FIGURE 22-6: Note 1: If the WUE bit is set with the ABDEN bit, auto-baud detection will occur on the byte following the Break character (see Section 22.3.3 "Auto-Wake-up on Break"). 2: It is up to the user to determine that the incoming character baud rate is within the range of the selected BRG clock source. Some combinations of oscillator frequency and EUSART baud rates are not possible. 3: During the auto-baud process, the auto-baud counter starts counting at 1. Upon completion of the auto-baud sequence, to achieve maximum accuracy, subtract 1 from the SPBRGH:SPBRGL register pair. TABLE 22-6: BRG COUNTER CLOCK RATES BRG16 BRGH BRG Base Clock BRG ABD Clock 0 0 FOSC/64 FOSC/512 0 1 FOSC/16 FOSC/128 1 0 FOSC/16 FOSC/128 1 FOSC/4 FOSC/32 1 Note: During the ABD sequence, SPBRGL and SPBRGH registers are both used as a 16-bit counter, independent of BRG16 setting. AUTOMATIC BAUD RATE CALIBRATION XXXXh BRG Value and SPBRGL registers are clocked at 1/8th the BRG base clock rate. The resulting byte measurement is the average bit time when clocked at full speed. RX pin 0000h 001Ch Start Edge #1 bit 1 bit 0 Edge #2 bit 3 bit 2 Edge #3 bit 5 bit 4 Edge #4 bit 7 bit 6 Edge #5 Stop bit BRG Clock Auto Cleared Set by User ABDEN bit RCIDL RCIF bit (Interrupt) Read RCREG SPBRGL XXh 1Ch SPBRGH XXh 00h Note 1: The ABD sequence requires the EUSART module to be configured in Asynchronous mode. DS41609A-page 254 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 22.3.2 AUTO-BAUD OVERFLOW 22.3.3.1 During the course of automatic baud detection, the ABDOVF bit of the BAUDCON register will be set if the baud rate counter overflows before the fifth rising edge is detected on the RX pin. The ABDOVF bit indicates that the counter has exceeded the maximum count that can fit in the 16 bits of the SPBRGH:SPBRGL register pair. After the ABDOVF bit has been set, the counter continues to count until the fifth rising edge is detected on the RX pin. Upon detecting the fifth RX edge, the hardware will set the RCIF interrupt flag and clear the ABDEN bit of the BAUDCON register. The RCIF flag can be subsequently cleared by reading the RCREG register. The ABDOVF flag of the BAUDCON register can be cleared by software directly. To terminate the auto-baud process before the RCIF flag is set, clear the ABDEN bit then clear the ABDOVF bit of the BAUDCON register. The ABDOVF bit will remain set if the ABDEN bit is not cleared first. 22.3.3 AUTO-WAKE-UP ON BREAK During Sleep mode, all clocks to the EUSART are suspended. Because of this, the Baud Rate Generator is inactive and a proper character reception cannot be performed. The Auto-Wake-up feature allows the controller to wake-up due to activity on the RX/DT line. This feature is available only in Asynchronous mode. The Auto-Wake-up feature is enabled by setting the WUE bit of the BAUDCON register. Once set, the normal receive sequence on RX/DT is disabled, and the EUSART remains in an Idle state, monitoring for a wake-up event independent of the CPU mode. A wake-up event consists of a high-to-low transition on the RX/DT line. (This coincides with the start of a Sync Break or a wake-up signal character for the LIN protocol.) The EUSART module generates an RCIF interrupt coincident with the wake-up event. The interrupt is generated synchronously to the Q clocks in normal CPU operating modes (Figure 22-7), and asynchronously if the device is in Sleep mode (Figure 22-8). The interrupt condition is cleared by reading the RCREG register. Special Considerations Break Character To avoid character errors or character fragments during a wake-up event, the wake-up character must be all zeros. When the wake-up is enabled the function works independent of the low time on the data stream. If the WUE bit is set and a valid non-zero character is received, the low time from the Start bit to the first rising edge will be interpreted as the wake-up event. The remaining bits in the character will be received as a fragmented character and subsequent characters can result in framing or overrun errors. Therefore, the initial character in the transmission must be all `0's. This must be 10 or more bit times, 13-bit times recommended for LIN bus, or any number of bit times for standard RS-232 devices. Oscillator Start-up Time Oscillator start-up time must be considered, especially in applications using oscillators with longer start-up intervals (i.e., LP, XT or HS/PLL mode). The Sync Break (or wake-up signal) character must be of sufficient length, and be followed by a sufficient interval, to allow enough time for the selected oscillator to start and provide proper initialization of the EUSART. WUE Bit The wake-up event causes a receive interrupt by setting the RCIF bit. The WUE bit is cleared in hardware by a rising edge on RX/DT. The interrupt condition is then cleared in software by reading the RCREG register and discarding its contents. To ensure that no actual data is lost, check the RCIDL bit to verify that a receive operation is not in process before setting the WUE bit. If a receive operation is not occurring, the WUE bit may then be set just prior to entering the Sleep mode. The WUE bit is automatically cleared by the low-to-high transition on the RX line at the end of the Break. This signals to the user that the Break event is over. At this point, the EUSART module is in Idle mode waiting to receive the next character. 2011 Microchip Technology Inc. Preliminary DS41609A-page 255 PIC16(L)F1508/9 FIGURE 22-7: AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Auto Cleared Bit set by user WUE bit RX/DT Line RCIF Note 1: Cleared due to User Read of RCREG The EUSART remains in Idle while the WUE bit is set. FIGURE 22-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 OSC1 Auto Cleared Bit Set by User WUE bit RX/DT Line Note 1 RCIF Sleep Command Executed Note 1: 2: Sleep Ends Cleared due to User Read of RCREG If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposc signal is still active. This sequence should not depend on the presence of Q clocks. The EUSART remains in Idle while the WUE bit is set. DS41609A-page 256 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 22.3.4 BREAK CHARACTER SEQUENCE The EUSART module has the capability of sending the special Break character sequences that are required by the LIN bus standard. A Break character consists of a Start bit, followed by 12 `0' bits and a Stop bit. To send a Break character, set the SENDB and TXEN bits of the TXSTA register. The Break character transmission is then initiated by a write to the TXREG. The value of data written to TXREG will be ignored and all `0's will be transmitted. The SENDB bit is automatically reset by hardware after the corresponding Stop bit is sent. This allows the user to preload the transmit FIFO with the next transmit byte following the Break character (typically, the Sync character in the LIN specification). The TRMT bit of the TXSTA register indicates when the transmit operation is active or idle, just as it does during normal transmission. See Figure 22-9 for the timing of the Break character sequence. 22.3.4.1 Break and Sync Transmit Sequence The following sequence will start a message frame header made up of a Break, followed by an auto-baud Sync byte. This sequence is typical of a LIN bus master. 1. 2. 3. 4. 5. 22.3.5 RECEIVING A BREAK CHARACTER The Enhanced EUSART module can receive a Break character in two ways. The first method to detect a Break character uses the FERR bit of the RCSTA register and the Received data as indicated by RCREG. The Baud Rate Generator is assumed to have been initialized to the expected baud rate. A Break character has been received when; * RCIF bit is set * FERR bit is set * RCREG = 00h The second method uses the Auto-Wake-up feature described in Section 22.3.3 "Auto-Wake-up on Break". By enabling this feature, the EUSART will sample the next two transitions on RX/DT, cause an RCIF interrupt, and receive the next data byte followed by another interrupt. Note that following a Break character, the user will typically want to enable the Auto-Baud Detect feature. For both methods, the user can set the ABDEN bit of the BAUDCON register before placing the EUSART in Sleep mode. Configure the EUSART for the desired mode. Set the TXEN and SENDB bits to enable the Break sequence. Load the TXREG with a dummy character to initiate transmission (the value is ignored). Write `55h' to TXREG to load the Sync character into the transmit FIFO buffer. After the Break has been sent, the SENDB bit is reset by hardware and the Sync character is then transmitted. When the TXREG becomes empty, as indicated by the TXIF, the next data byte can be written to TXREG. FIGURE 22-9: Write to TXREG SEND BREAK CHARACTER SEQUENCE Dummy Write BRG Output (Shift Clock) TX (pin) Start bit bit 0 bit 1 bit 11 Stop bit Break TXIF bit (Transmit Interrupt Flag) TRMT bit (Transmit Shift Empty Flag) SENDB (send Break control bit) 2011 Microchip Technology Inc. SENDB Sampled Here Preliminary Auto Cleared DS41609A-page 257 PIC16(L)F1508/9 22.4 EUSART Synchronous Mode Synchronous serial communications are typically used in systems with a single master and one or more slaves. The master device contains the necessary circuitry for baud rate generation and supplies the clock for all devices in the system. Slave devices can take advantage of the master clock by eliminating the internal clock generation circuitry. There are two signal lines in Synchronous mode: a bidirectional data line and a clock line. Slaves use the external clock supplied by the master to shift the serial data into and out of their respective receive and transmit shift registers. Since the data line is bidirectional, synchronous operation is half-duplex only. Half-duplex refers to the fact that master and slave devices can receive and transmit data but not both simultaneously. The EUSART can operate as either a master or slave device. Start and Stop bits are not used in synchronous transmissions. 22.4.1 SYNCHRONOUS MASTER MODE Clearing the SCKP bit sets the Idle state as low. When the SCKP bit is cleared, the data changes on the rising edge of each clock. 22.4.1.3 Data is transferred out of the device on the RX/DT pin. The RX/DT and TX/CK pin output drivers are automatically enabled when the EUSART is configured for synchronous master transmit operation. A transmission is initiated by writing a character to the TXREG register. If the TSR still contains all or part of a previous character the new character data is held in the TXREG until the last bit of the previous character has been transmitted. If this is the first character, or the previous character has been completely flushed from the TSR, the data in the TXREG is immediately transferred to the TSR. The transmission of the character commences immediately following the transfer of the data to the TSR from the TXREG. Each data bit changes on the leading edge of the master clock and remains valid until the subsequent leading clock edge. Note: The TSR register is not mapped in data memory, so it is not available to the user. 22.4.1.4 Synchronous Master Transmission Set-up: The following bits are used to configure the EUSART for synchronous master operation: * * * * * SYNC = 1 CSRC = 1 SREN = 0 (for transmit); SREN = 1 (for receive) CREN = 0 (for transmit); CREN = 1 (for receive) SPEN = 1 1. Setting the SYNC bit of the TXSTA register configures the device for synchronous operation. Setting the CSRC bit of the TXSTA register configures the device as a master. Clearing the SREN and CREN bits of the RCSTA register ensures that the device is in the Transmit mode, otherwise the device will be configured to receive. Setting the SPEN bit of the RCSTA register enables the EUSART. 22.4.1.1 22.4.1.2 2. 3. 4. 5. 6. Master Clock Synchronous data transfers use a separate clock line, which is synchronous with the data. A device configured as a master transmits the clock on the TX/CK line. The TX/CK pin output driver is automatically enabled when the EUSART is configured for synchronous transmit or receive operation. Serial data bits change on the leading edge to ensure they are valid at the trailing edge of each clock. One clock cycle is generated for each data bit. Only as many clock cycles are generated as there are data bits. Synchronous Master Transmission 7. 8. Initialize the SPBRGH, SPBRGL register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 22.3 "EUSART Baud Rate Generator (BRG)"). Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. Disable Receive mode by clearing bits SREN and CREN. Enable Transmit mode by setting the TXEN bit. If 9-bit transmission is desired, set the TX9 bit. If interrupts are desired, set the TXIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. If 9-bit transmission is selected, the ninth bit should be loaded in the TX9D bit. Start transmission by loading data to the TXREG register. Clock Polarity A clock polarity option is provided for Microwire compatibility. Clock polarity is selected with the SCKP bit of the BAUDCON register. Setting the SCKP bit sets the clock Idle state as high. When the SCKP bit is set, the data changes on the falling edge of each clock. DS41609A-page 258 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 FIGURE 22-10: SYNCHRONOUS TRANSMISSION RX/DT pin bit 0 bit 1 Word 1 bit 2 bit 7 bit 0 bit 1 Word 2 bit 7 TX/CK pin (SCKP = 0) TX/CK pin (SCKP = 1) Write to TXREG Reg Write Word 1 Write Word 2 TXIF bit (Interrupt Flag) TRMT bit TXEN bit `1' Note: `1' Sync Master mode, SPBRGL = 0, continuous transmission of two 8-bit words. FIGURE 22-11: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RX/DT pin bit 0 bit 2 bit 1 bit 6 bit 7 TX/CK pin Write to TXREG reg TXIF bit TRMT bit TXEN bit TABLE 22-7: Name SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Bit 7 Bit 6 ABDOVF GIE PIE1 PIR1 BAUDCON INTCON RCSTA Bit 2 Bit 1 Bit 0 Register on Page BRG16 -- WUE ABDEN 248 IOCIE TMR0IF INTF IOCIF 78 TXIE SSP1IE -- TMR2IE TMR1IE 79 TXIF SSP1IF -- TMR2IF TMR1IF 82 CREN ADDEN FERR OERR RX9D 247 Bit 5 Bit 4 Bit 3 RCIDL -- SCKP PEIE TMR0IE INTE TMR1GIE ADIE RCIE TMR1GIF ADIF RCIF SPEN RX9 SREN SPBRGL BRG<7:0> 249* SPBRGH BRG<15:8> 249* TRISC TRISC7 TRISC6 TXSTA Legend: * TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 EUSART Transmit Data Register TXREG CSRC TX9 TXEN SYNC SENDB BRGH 122 239* TRMT TX9D 246 -- = unimplemented location, read as `0'. Shaded cells are not used for synchronous master transmission. Page provides register information. 2011 Microchip Technology Inc. Preliminary DS41609A-page 259 PIC16(L)F1508/9 22.4.1.5 Synchronous Master Reception Data is received at the RX/DT pin. The RX/DT pin output driver is automatically disabled when the EUSART is configured for synchronous master receive operation. In Synchronous mode, reception is enabled by setting either the Single Receive Enable bit (SREN of the RCSTA register) or the Continuous Receive Enable bit (CREN of the RCSTA register). When SREN is set and CREN is clear, only as many clock cycles are generated as there are data bits in a single character. The SREN bit is automatically cleared at the completion of one character. When CREN is set, clocks are continuously generated until CREN is cleared. If CREN is cleared in the middle of a character the CK clock stops immediately and the partial character is discarded. If SREN and CREN are both set, then SREN is cleared at the completion of the first character and CREN takes precedence. To initiate reception, set either SREN or CREN. Data is sampled at the RX/DT pin on the trailing edge of the TX/CK clock pin and is shifted into the Receive Shift Register (RSR). When a complete character is received into the RSR, the RCIF bit is set and the character is automatically transferred to the two character receive FIFO. The Least Significant eight bits of the top character in the receive FIFO are available in RCREG. The RCIF bit remains set as long as there are unread characters in the receive FIFO. Note: 22.4.1.6 If the RX/DT function is on an analog pin, the corresponding ANSEL bit must be cleared for the receiver to function. Slave Clock Synchronous data transfers use a separate clock line, which is synchronous with the data. A device configured as a slave receives the clock on the TX/CK line. The TX/CK pin output driver is automatically disabled when the device is configured for synchronous slave transmit or receive operation. Serial data bits change on the leading edge to ensure they are valid at the trailing edge of each clock. One data bit is transferred for each clock cycle. Only as many clock cycles should be received as there are data bits. Note: 22.4.1.7 If the device is configured as a slave and the TX/CK function is on an analog pin, the corresponding ANSEL bit must be cleared. buffer can be read, however, no additional characters will be received until the error is cleared. The OERR bit can only be cleared by clearing the overrun condition. If the overrun error occurred when the SREN bit is set and CREN is clear then the error is cleared by reading RCREG. If the overrun occurred when the CREN bit is set then the error condition is cleared by either clearing the CREN bit of the RCSTA register or by clearing the SPEN bit which resets the EUSART. 22.4.1.8 Receiving 9-bit Characters The EUSART supports 9-bit character reception. When the RX9 bit of the RCSTA register is set the EUSART will shift 9-bits into the RSR for each character received. The RX9D bit of the RCSTA register is the ninth, and Most Significant, data bit of the top unread character in the receive FIFO. When reading 9-bit data from the receive FIFO buffer, the RX9D data bit must be read before reading the 8 Least Significant bits from the RCREG. 22.4.1.9 Synchronous Master Reception Set-up: 1. Initialize the SPBRGH, SPBRGL register pair for the appropriate baud rate. Set or clear the BRGH and BRG16 bits, as required, to achieve the desired baud rate. 2. Clear the ANSEL bit for the RX pin (if applicable). 3. Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. 4. Ensure bits CREN and SREN are clear. 5. If interrupts are desired, set the RCIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. 6. If 9-bit reception is desired, set bit RX9. 7. Start reception by setting the SREN bit or for continuous reception, set the CREN bit. 8. Interrupt flag bit RCIF will be set when reception of a character is complete. An interrupt will be generated if the enable bit RCIE was set. 9. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. 10. Read the 8-bit received data by reading the RCREG register. 11. If an overrun error occurs, clear the error by either clearing the CREN bit of the RCSTA register or by clearing the SPEN bit which resets the EUSART. Receive Overrun Error The receive FIFO buffer can hold two characters. An overrun error will be generated if a third character, in its entirety, is received before RCREG is read to access the FIFO. When this happens the OERR bit of the RCSTA register is set. Previous data in the FIFO will not be overwritten. The two characters in the FIFO DS41609A-page 260 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 FIGURE 22-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) RX/DT pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 TX/CK pin (SCKP = 0) TX/CK pin (SCKP = 1) Write to bit SREN SREN bit CREN bit `0' `0' RCIF bit (Interrupt) Read RCREG Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0. TABLE 22-8: Name SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Bit 7 Bit 6 ABDOVF GIE PIE1 PIR1 BAUDCON INTCON Bit 1 Bit 0 Register on Page BRG16 -- WUE ABDEN 248 IOCIE TMR0IF INTF IOCIF 78 TXIE SSP1IE -- TMR2IE TMR1IE 79 TXIF SSP1IF -- TMR2IF TMR1IF 82 OERR RX9D Bit 4 Bit 3 RCIDL -- SCKP PEIE TMR0IE INTE TMR1GIE ADIE RCIE TMR1GIF ADIF RCIF SPEN RX9 SREN RCREG RCSTA Bit 2 Bit 5 EUSART Receive Data Register CREN ADDEN FERR 242* 247 SPBRGL BRG<7:0> 249* SPBRGH BRG<15:8> 249* TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 122 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 246 Legend: -- = unimplemented location, read as `0'. Shaded cells are not used for synchronous master reception. * Page provides register information. 2011 Microchip Technology Inc. Preliminary DS41609A-page 261 PIC16(L)F1508/9 22.4.2 SYNCHRONOUS SLAVE MODE The following bits are used to configure the EUSART for synchronous slave operation: * * * * * SYNC = 1 CSRC = 0 SREN = 0 (for transmit); SREN = 1 (for receive) CREN = 0 (for transmit); CREN = 1 (for receive) SPEN = 1 1. 2. 3. 4. Setting the SYNC bit of the TXSTA register configures the device for synchronous operation. Clearing the CSRC bit of the TXSTA register configures the device as a slave. Clearing the SREN and CREN bits of the RCSTA register ensures that the device is in the Transmit mode, otherwise the device will be configured to receive. Setting the SPEN bit of the RCSTA register enables the EUSART. 22.4.2.1 If two words are written to the TXREG and then the SLEEP instruction is executed, the following will occur: EUSART Synchronous Slave Transmit 5. 22.4.2.2 1. The operation of the Synchronous Master and Slave Section 22.4.1.3 modes are identical (see "Synchronous Master Transmission"), except in the case of the Sleep mode. 2. 3. 4. 5. 6. 7. 8. TABLE 22-9: Name BAUDCON The first character will immediately transfer to the TSR register and transmit. The second word will remain in the TXREG register. The TXIF bit will not be set. After the first character has been shifted out of TSR, the TXREG register will transfer the second character to the TSR and the TXIF bit will now be set. If the PEIE and TXIE bits are set, the interrupt will wake the device from Sleep and execute the next instruction. If the GIE bit is also set, the program will call the Interrupt Service Routine. Synchronous Slave Transmission Set-up: Set the SYNC and SPEN bits and clear the CSRC bit. Clear the ANSEL bit for the CK pin (if applicable). Clear the CREN and SREN bits. If interrupts are desired, set the TXIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. If 9-bit transmission is desired, set the TX9 bit. Enable transmission by setting the TXEN bit. If 9-bit transmission is selected, insert the Most Significant bit into the TX9D bit. Start transmission by writing the Least Significant 8 bits to the TXREG register. SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Bit 7 Bit 6 ABDOVF Bit 2 Bit 1 Bit 0 Register on Page BRG16 -- WUE ABDEN 248 IOCIE TMR0IF INTF IOCIF 78 79 Bit 5 Bit 4 Bit 3 RCIDL -- SCKP INTE GIE PEIE TMR0IE PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE -- TMR2IE TMR1IE PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF -- TMR2IF TMR1IF 82 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 247 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 122 INTCON TXREG TXSTA EUSART Transmit Data Register CSRC TX9 TXEN SYNC SENDB BRGH 239* TRMT TX9D 246 Legend: -- = unimplemented location, read as `0'. Shaded cells are not used for synchronous slave transmission. * Page provides register information. DS41609A-page 262 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 22.4.2.3 EUSART Synchronous Slave Reception 22.4.2.4 The operation of the Synchronous Master and Slave modes is identical (Section 22.4.1.5 "Synchronous Master Reception"), with the following exceptions: * Sleep * CREN bit is always set, therefore the receiver is never idle * SREN bit, which is a "don't care" in Slave mode 1. 2. 3. A character may be received while in Sleep mode by setting the CREN bit prior to entering Sleep. Once the word is received, the RSR register will transfer the data to the RCREG register. If the RCIE enable bit is set, the interrupt generated will wake the device from Sleep and execute the next instruction. If the GIE bit is also set, the program will branch to the interrupt vector. 4. 5. 6. 7. 8. 9. Synchronous Slave Reception Set-up: Set the SYNC and SPEN bits and clear the CSRC bit. Clear the ANSEL bit for both the CK and DT pins (if applicable). If interrupts are desired, set the RCIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. If 9-bit reception is desired, set the RX9 bit. Set the CREN bit to enable reception. The RCIF bit will be set when reception is complete. An interrupt will be generated if the RCIE bit was set. If 9-bit mode is enabled, retrieve the Most Significant bit from the RX9D bit of the RCSTA register. Retrieve the 8 Least Significant bits from the receive FIFO by reading the RCREG register. If an overrun error occurs, clear the error by either clearing the CREN bit of the RCSTA register or by clearing the SPEN bit which resets the EUSART. TABLE 22-10: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Name BAUDCON Bit 7 Bit 6 ABDOVF Bit 2 Bit 1 Bit 0 Register on Page BRG16 -- WUE ABDEN 248 IOCIE TMR0IF INTF IOCIF 78 79 Bit 5 Bit 4 Bit 3 RCIDL -- SCKP INTE GIE PEIE TMR0IE PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE -- TMR2IE TMR1IE PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF -- TMR2IF TMR1IF INTCON RCREG EUSART Receive Data Register 82 242* RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 247 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 122 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 246 Legend: -- = unimplemented location, read as `0'. Shaded cells are not used for synchronous slave reception. * Page provides register information. 2011 Microchip Technology Inc. Preliminary DS41609A-page 263 PIC16(L)F1508/9 22.5 EUSART Operation During Sleep The EUSART will remain active during Sleep only in the Synchronous Slave mode. All other modes require the system clock and therefore cannot generate the necessary signals to run the Transmit or Receive Shift registers during Sleep. Synchronous Slave mode uses an externally generated clock to run the Transmit and Receive Shift registers. 22.5.1 SYNCHRONOUS RECEIVE DURING SLEEP To receive during Sleep, all the following conditions must be met before entering Sleep mode: * RCSTA and TXSTA Control registers must be configured for Synchronous Slave Reception (see Section 22.4.2.4 "Synchronous Slave Reception Set-up:"). * If interrupts are desired, set the RCIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. * The RCIF interrupt flag must be cleared by reading RCREG to unload any pending characters in the receive buffer. Upon entering Sleep mode, the device will be ready to accept data and clocks on the RX/DT and TX/CK pins, respectively. When the data word has been completely clocked in by the external device, the RCIF interrupt flag bit of the PIR1 register will be set. Thereby, waking the processor from Sleep. Upon waking from Sleep, the instruction following the SLEEP instruction will be executed. If the Global Interrupt Enable (GIE) bit of the INTCON register is also set, then the Interrupt Service Routine at address 004h will be called. DS41609A-page 264 22.5.2 SYNCHRONOUS TRANSMIT DURING SLEEP To transmit during Sleep, all the following conditions must be met before entering Sleep mode: * RCSTA and TXSTA Control registers must be configured for synchronous slave transmission (see Section 22.4.2.2 "Synchronous Slave Transmission Set-up:"). * The TXIF interrupt flag must be cleared by writing the output data to the TXREG, thereby filling the TSR and transmit buffer. * If interrupts are desired, set the TXIE bit of the PIE1 register and the PEIE bit of the INTCON register. * Interrupt enable bits TXIE of the PIE1 register and PEIE of the INTCON register must set. Upon entering Sleep mode, the device will be ready to accept clocks on TX/CK pin and transmit data on the RX/DT pin. When the data word in the TSR has been completely clocked out by the external device, the pending byte in the TXREG will transfer to the TSR and the TXIF flag will be set. Thereby, waking the processor from Sleep. At this point, the TXREG is available to accept another character for transmission, which will clear the TXIF flag. Upon waking from Sleep, the instruction following the SLEEP instruction will be executed. If the Global Interrupt Enable (GIE) bit is also set then the Interrupt Service Routine at address 0004h will be called. 22.5.3 ALTERNATE PIN LOCATIONS This module incorporates I/O pins that can be moved to other locations with the use of the alternate pin function register, APFCON. To determine which pins can be moved and what their default locations are upon a Reset, see Section 11.1 "Alternate Pin Function" for more information. Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 23.0 PULSE WIDTH MODULATION (PWM) MODULE For a step-by-step procedure on how to set up this module for PWM operation, refer to Section 23.1.9 "Setup for PWM Operation using PWMx Pins". The PWM module generates a Pulse-Width Modulated signal determined by the duty cycle, period, and resolution that are configured by the following registers: * * * * * FIGURE 23-1: PWM OUTPUT Period PR2 T2CON PWMxDCH PWMxDCL PWMxCON Pulse Width TMR2 = 0 TMR2 = PR2 TMR2 = PWMxDCH<7:0>:PWMxDCL<7:6> Figure 23-2 shows a simplified block diagram of PWM operation. Figure 23-1 shows a typical waveform of the PWM signal. FIGURE 23-2: SIMPLIFIED PWM BLOCK DIAGRAM Duty Cycle registers PWMxDCL<7:6> PWMxDCH PWMxOUT to other peripherals: CLC and CWG Latched (Not visible to user) Output Enable (PWMxOE) TRIS Control Comparator R Q 0 PWMx S Q 1 TMR2 Module TMR2 Output Polarity (PWMxPOL) (1) Comparator PR2 Note 1: Clear Timer, PWMx pin and latch Duty Cycle 8-bit timer is concatenated with the two Least Significant bits of 1/FOSC adjusted by the Timer2 prescaler to create a 10-bit time base. 2011 Microchip Technology Inc. Preliminary DS41609A-page 265 PIC16(L)F1508/9 23.1 PWMx Pin Configuration All PWM outputs are multiplexed with the PORT data latch. The user must configure the pins as outputs by clearing the associated TRIS bits. Note: 23.1.1 Clearing the PWMxOE bit will relinquish control of the PWMx pin. FUNDAMENTAL OPERATION The PWM module produces a 10-bit resolution output. Timer2 and PR2 set the period of the PWM. The PWMxDCL and PWMxDCH registers configure the duty cycle. The period is common to all PWM modules, whereas the duty cycle is independently controlled. Note: The Timer2 postscaler is not used in the determination of the PWM frequency. The postscaler could be used to have a servo update rate at a different frequency than the PWM output. All PWM outputs associated with Timer2 are set when TMR2 is cleared. Each PWMx is cleared when TMR2 is equal to the value specified in the corresponding PWMxDCH (8 MSb) and PWMxDCL<7:6> (2 LSb) registers. When the value is greater than or equal to PR2, the PWM output is never cleared (100% duty cycle). Note: 23.1.2 When TMR2 is equal to PR2, the following three events occur on the next increment cycle: * TMR2 is cleared * The PWM output is active. (Exception: When the PWM duty cycle = 0%, the PWM output will remain inactive.) * The PWMxDCH and PWMxDCL register values are latched into the buffers. Note: 23.1.4 Equation 23-2 is used to calculate the PWM pulse width. Equation 23-3 is used to calculate the PWM duty cycle ratio. EQUATION 23-2: T OS C (TMR2 Prescale Value) Note: TOSC = 1/FOSC EQUATION 23-3: EQUATION 23-1: PWM PERIOD DUTY CYCLE RATIO PWMxDCH:PWMxDCL<7:6> Duty Cycle Ratio = ----------------------------------------------------------------------------------4 PR2 + 1 PWM PERIOD The PWM period is specified by the PR2 register of Timer2. The PWM period can be calculated using the formula of Equation 23-1. PULSE WIDTH Pulse Width = PWMxDCH:PWMxDCL<7:6> The output polarity is inverted by setting the PWMxPOL bit of the PWMxCON register. 23.1.3 PWM DUTY CYCLE The PWM duty cycle is specified by writing a 10-bit value to the PWMxDCH and PWMxDCL register pair. The PWMxDCH register contains the eight MSbs and the PWMxDCL<7:6>, the two LSbs. The PWMxDCH and PWMxDCL registers can be written to at any time. The PWMxDCH and PWMxDCL registers are double buffered. The buffers are updated when Timer2 matches PR2. Care should be taken to update both registers before the timer match occurs. PWM OUTPUT POLARITY The Timer2 postscaler has no effect on the PWM operation. The 8-bit timer TMR2 register is concatenated with the two Least Significant bits of 1/FOSC, adjusted by the Timer2 prescaler to create the 10-bit time base. The system clock is used if the Timer2 prescaler is set to 1:1. PWM Period = PR2 + 1 4 T OSC (TMR2 Prescale Value) Note: TOSC = 1/FOSC DS41609A-page 266 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 23.1.5 PWM RESOLUTION The resolution determines the number of available duty cycles for a given period. For example, a 10-bit resolution will result in 1024 discrete duty cycles, whereas an 8-bit resolution will result in 256 discrete duty cycles. The maximum PWM resolution is 10 bits when PR2 is 255. The resolution is a function of the PR2 register value as shown by Equation 23-4. EQUATION 23-4: PWM RESOLUTION log 4 PR2 + 1 Resolution = ------------------------------------------ bits log 2 Note: If the pulse width value is greater than the period the assigned PWM pin(s) will remain unchanged. TABLE 23-1: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz) PWM Frequency 0.31 kHz Timer Prescale (1, 4, 64) PR2 Value 78.12 kHz 156.3 kHz 208.3 kHz 64 4 1 1 1 1 0xFF 0xFF 0x3F 0x1F 0x17 10 10 10 8 7 6.6 EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz) PWM Frequency 0.31 kHz Timer Prescale (1, 4, 64) PR2 Value 4.90 kHz 19.61 kHz 76.92 kHz 153.85 kHz 200.0 kHz 64 4 1 1 1 1 0x65 0x65 0x65 0x19 0x0C 0x09 8 8 8 6 5 5 Maximum Resolution (bits) 23.1.6 19.53 kHz 0xFF Maximum Resolution (bits) TABLE 23-2: 4.88 kHz OPERATION IN SLEEP MODE In Sleep mode, the TMR2 register will not increment and the state of the module will not change. If the PWMx pin is driving a value, it will continue to drive that value. When the device wakes up, TMR2 will continue from its previous state. 23.1.7 CHANGES IN SYSTEM CLOCK FREQUENCY The PWM frequency is derived from the system clock frequency (FOSC). Any changes in the system clock frequency will result in changes to the PWM frequency. Refer to Section 5.0 "Oscillator Module (With Fail-Safe Clock Monitor)" for additional details. 23.1.8 EFFECTS OF RESET Any Reset will force all ports to Input mode and the PWM registers to their Reset states. 2011 Microchip Technology Inc. Preliminary DS41609A-page 267 PIC16(L)F1508/9 23.1.9 SETUP FOR PWM OPERATION USING PWMx PINS The following steps should be taken when configuring the module for PWM operation using the PWMx pins: 1. 2. 3. 4. 5. 6. 7. 8. Disable the PWMx pin output driver(s) by setting the associated TRIS bit(s). Clear the PWMxCON register. Load the PR2 register with the PWM period value. Clear the PWMxDCH register and bits <7:6> of the PWMxDCL register. Configure and start Timer2: * Clear the TMR2IF interrupt flag bit of the PIR1 register. See Note below. * Configure the T2CKPS bits of the T2CON register with the Timer2 prescale value. * Enable Timer2 by setting the TMR2ON bit of the T2CON register. Enable PWM output pin and wait until Timer2 overflows, TMR2IF bit of the PIR1 register is set. See note below. Enable the PWMx pin output driver(s) by clearing the associated TRIS bit(s) and setting the PWMxOE bit of the PWMxCON register. Configure the PWM module by loading the PWMxCON register with the appropriate values. Note 1: In order to send a complete duty cycle and period on the first PWM output, the above steps must be followed in the order given. If it is not critical to start with a complete PWM signal, then move Step 8 to replace Step 4. 2: For operation with other peripherals only, disable PWMx pin outputs. DS41609A-page 268 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 23.2 PWM Register Definitions REGISTER 23-1: PWMxCON: PWM CONTROL REGISTER R/W-0/0 R/W-0/0 R-0/0 R/W-0/0 U-0 U-0 U-0 U-0 PWMxEN PWMxOE PWMxOUT PWMxPOL -- -- -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 PWMxEN: PWM Module Enable bit 1 = PWM module is enabled 0 = PWM module is disabled bit 6 PWMxOE: PWM Module Output Enable bit 1 = Output to PWMx pin is enabled 0 = Output to PWMx pin is disabled bit 5 PWMxOUT: PWM Module Output Value bit bit 4 PWMxPOL: PWMx Output Polarity Select bit 1 = PWM output is active low 0 = PWM output is active high bit 3-0 Unimplemented: Read as `0' 2011 Microchip Technology Inc. Preliminary DS41609A-page 269 PIC16(L)F1508/9 REGISTER 23-2: R/W-x/u PWMxDCH: PWM DUTY CYCLE HIGH BITS R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u PWMxDCH<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 PWMxDCH<7:0>: PWM Duty Cycle Most Significant bits These bits are the MSbs of the PWM duty cycle. The two LSbs are found in the PWMxDCL register. REGISTER 23-3: R/W-x/u PWMxDCL: PWM DUTY CYCLE LOW BITS R/W-x/u PWMxDCL<7:6> U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-6 PWMxDCL<7:6>: PWM Duty Cycle Least Significant bits These bits are the LSbs of the PWM duty cycle. The MSbs are found in the PWMxDCH register. bit 5-0 Unimplemented: Read as `0' TABLE 23-3: Name SUMMARY OF REGISTERS ASSOCIATED WITH PWM Bit 7 Bit 6 Bit 5 PWM1EN PWM1OE PWM1OUT PR2 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 -- -- -- Timer2 module Period Register PWM1CON PWM1DCH PWM1DCL PWM2CON PWM3CON PWM1DCL<7:6> PWM2EN PWM2OE PWM4CON 179* -- -- -- -- -- -- PWM2POL -- -- -- -- PWM2DCH<7:0> PWM2DCL<7:6> PWM3EN PWM3OE PWM3DCL<7:6> PWM4OE -- -- -- -- -- -- PWM3OUT PWM3POL -- -- -- -- -- -- -- -- -- -- PWM4POL -- -- -- -- PWM4DCH<7:0> PWM4DCL PWM4DCL<7:6> T2CON -- -- -- -- T2OUTPS<3:0> TMR2 270 270 269 270 PWM4OUT PWM4DCH 270 270 PWM3DCH<7:0> PWM4EN 269 270 PWM2OUT PWM3DCH PWM3DCL -- PWM1DCH<7:0> PWM2DCH PWM2DCL PWM1POL Register on Page 270 269 270 -- TMR2ON -- -- T2CKPS<1:0> Timer2 module Register 270 181 179* TRISA -- -- TRISA5 TRISA4 --(1) TRISA2 TRISA1 TRISA0 114 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 122 Legend: Note * 1: - = Unimplemented locations, read as `0', u = unchanged, x = unknown. Shaded cells are not used by the PWM. Page provides register information. Unimplemented, read as `1'. DS41609A-page 270 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 24.0 CONFIGURABLE LOGIC CELL (CLC) The Configurable Logic Cell (CLCx) provides programmable logic that operates outside the speed limitations of software execution. The logic cell takes up to 16 input signals and through the use of configurable gates reduces the 16 inputs to four logic lines that drive one of eight selectable single-output logic functions. Input sources are a combination of the following: * * * * I/O pins Internal clocks Peripherals Register bits The output can be directed internally to peripherals and to an output pin. CLCxIN[0] CLCxIN[1] CLCxIN[2] CLCxIN[3] CLCxIN[4] CLCxIN[5] CLCxIN[6] CLCxIN[7] CLCxIN[8] CLCxIN[9] CLCxIN[10] CLCxIN[11] CLCxIN[12] CLCxIN[13] CLCxIN[14] CLCxIN[15] Possible configurations include: * Combinatorial Logic - AND - NAND - AND-OR - AND-OR-INVERT - OR-XOR - OR-XNOR * Latches - S-R - Clocked D with Set and Reset - Transparent D with Set and Reset - Clocked J-K with Reset CLCx SIMPLIFIED BLOCK DIAGRAM D Q1 See Figure 24-3 Input Data Selection Gates FIGURE 24-1: Refer to Figure 24-1 for a simplified diagram showing signal flow through the CLCx. MLCxOUT LE LCxOE LCxEN lcxg1 LCxOUT Q TRIS Control lcxg2 Logic lcxg3 Function lcxq lcx_out CLCx lcxg4 LCxPOL LCxMODE<2:0> det LCxINTP LCxINTN sets CLCxIF flag Interrupt See Figure 24-2 2011 Microchip Technology Inc. Interrupt det Preliminary DS41609A-page 271 PIC16(L)F1508/9 24.1 CLCx Setup 24.1.1 Programming the CLCx module is performed by configuring the 4 stages in the logic signal flow. The 4 stages are: * * * * Data selection Data gating Logic function selection Output polarity Each stage is setup at run time by writing to the corresponding CLCx Special Function Registers. This has the added advantage of permitting logic reconfiguration on-the-fly during program execution. DATA SELECTION There are 16 signals available as inputs to the configurable logic. Four 8-input multiplexers are used to select the inputs to pass on to the next stage. The 16 inputs to the multiplexers are arranged in groups of four. Each group is available to two of the four multiplexers, in each case, paired with a different group. This arrangement makes possible selection of up to two from a group without precluding a selection from another group. Data inputs are selected with the CLCxSEL0 and CLCxSEL1 registers (Register 24-3 and Register 24-4, respectively). Data inputs are selected with CLCxSEL0 and CLCxSEL1 registers (Register 24-3 and Register 24-4, respectively). Data selection is through four multiplexers as indicated on the left side of Figure 24-2. Data inputs in the figure are identified by a generic numbered input name. Table 24-1 correlates the generic input name to the actual signal for each CLC module. The columns labeled lcxd1 through lcxd4 indicate the MUX output for the selected data input. D1S through D4S are abbreviations for the MUX select input codes: LCxD1S<2:0> through LCxD4S<2:0>, respectively. Selecting a data input in a column excludes all other inputs in that column. Note: TABLE 24-1: Data Input Data selections are undefined at power-up. CLCx DATA INPUT SELECTION lcxd1 D1S lcxd2 D2S lcxd3 D3S lcxd4 D4S CLC 1 CLC 2 CLC 3 CLC 4 CLCxIN[0] 000 -- -- 100 CLC1IN0 CLC2IN0 CLC3IN0 CLC4IN0 CLCxIN[1] 001 -- -- 101 CLC1IN1 CLC2IN1 CLC3IN1 CLC4IN1 CLCxIN[2] 010 -- -- 110 SYNCC1OUT SYNCC1OUT SYNCC1OUT SYNCC1OUT CLCxIN[3] 011 -- -- 111 SYNCC2OUT SYNCC2OUT SYNCC2OUT SYNCC2OUT CLCxIN[4] 100 000 -- -- FOSC FOSC FOSC FOSC CLCxIN[5] 101 001 -- -- TMR0IF TMR0IF TMR0IF TMR0IF CLCxIN[6] 110 010 -- -- TMR1IF TMR1IF TMR1IF TMR1IF CLCxIN[7] 111 011 -- -- TMR2 = PR2 TMR2 = PR2 TMR2 = PR2 TMR2 = PR2 CLCxIN[8] -- 100 000 -- lc1_out lc1_out lc1_out lc1_out CLCxIN[9] -- 101 001 -- lc2_out lc2_out lc2_out lc2_out CLCxIN[10] -- 110 010 -- lc3_out lc3_out lc3_out lc3_out CLCxIN[11] -- 111 011 -- lc4_out lc4_out lc4_out lc4_out CLCxIN[12] -- -- 100 000 NCO1OUT LFINTOSC TX (EUSART) SCK (MSSP) CLCxIN[13] -- -- 101 001 HFINTOSC ADFRC LFINTOSC SDO (MSSP) CLCxIN[14] -- -- 110 010 PWM3OUT PWM1OUT PWM2OUT PWM1OUT CLCxIN[15] -- -- 111 011 PWM4OUT PWM2OUT PWM3OUT PWM4OUT DS41609A-page 272 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 24.1.2 DATA GATING Outputs from the input multiplexers are directed to the desired logic function input through the data gating stage. Each data gate can direct any combination of the four selected inputs. Note: 24.1.3 Data gating is undefined at power-up. The gate stage is more than just signal direction. The gate can be configured to direct each input signal as inverted or non-inverted data. Directed signals are ANDed together in each gate. The output of each gate can be inverted before going on to the logic function stage. The gating is in essence a 1-to-4 input AND/NAND/OR/NOR gate. When every input is inverted and the output is inverted, the gate is an OR of all enabled data inputs. When the inputs and output are not inverted, the gate is an AND or all enabled inputs. Table 24-2 summarizes the basic logic that can be obtained in gate 1 by using the gate logic select bits. The table shows the logic of four input variables, but each gate can be configured to use less than four. If no inputs are selected, the output will be zero or one, depending on the gate output polarity bit. TABLE 24-2: LCxG1POL Gate Logic 0x55 1 AND 0x55 0 NAND 0xAA 1 NOR 0xAA 0 OR 0x00 0 Logic 0 0x00 1 Logic 1 LOGIC FUNCTION There are 8 available logic functions including: * * * * * * * * AND-OR OR-XOR AND S-R Latch D Flip-Flop with Set and Reset D Flip-Flop with Reset J-K Flip-Flop with Reset Transparent Latch with Set and Reset Logic functions are shown in Figure 24-3. Each logic function has four inputs and one output. The four inputs are the four data gate outputs of the previous stage. The output is fed to the inversion stage and from there to other peripherals, an output pin, and back to the CLCx itself. 24.1.4 OUTPUT POLARITY The last stage in the configurable logic cell is the output polarity. Setting the LCxPOL bit of the CLCxCON register inverts the output signal from the logic stage. Changing the polarity while the interrupts are enabled will cause an interrupt for the resulting output transition. DATA GATING LOGIC CLCxGLS0 Data gating is indicated in the right side of Figure 24-2. Only one gate is shown in detail. The remaining three gates are configured identically with the exception that the data enables correspond to the enables for that gate. It is possible (but not recommended) to select both the true and negated values of an input. When this is done, the gate output is zero, regardless of the other inputs, but may emit logic glitches (transient-induced pulses). If the output of the channel must be zero or one, the recommended method is to set all gate bits to zero and use the gate polarity bit to set the desired level. Data gating is configured with the logic gate select registers as follows: * * * * Gate 1: CLCxGLS0 (Register 24-5) Gate 2: CLCxGLS1 (Register 24-6) Gate 3: CLCxGLS2 (Register 24-7) Gate 4: CLCxGLS3 (Register 24-8) Register number suffixes are different than the gate numbers because other variations of this module have multiple gate selections in the same register. 2011 Microchip Technology Inc. Preliminary DS41609A-page 273 PIC16(L)F1508/9 24.1.5 24.2 CLCx SETUP STEPS The following steps should be followed when setting up the CLCx: * Disable CLCx by clearing the LCxEN bit. * Select desired inputs using CLCxSEL0 and CLCxSEL1 registers (See Table 24-1). * Clear any associated ANSEL bits. * Set all TRIS bits associated with inputs. * Clear all TRIS bits associated with outputs. * Enable the chosen inputs through the four gates using CLCxGLS0, CLCxGLS1, CLCxGLS2, and CLCxGLS3 registers. * Select the gate output polarities with the LCxPOLy bits of the CLCxPOL register. * Select the desired logic function with the LCxMODE<2:0> bits of the CLCxCON register. * Select the desired polarity of the logic output with the LCxPOL bit of the CLCxPOL register. (This step may be combined with the previous gate output polarity step). * If driving the CLCx pin, set the LCxOE bit of the CLCxCON register and also clear the TRIS bit corresponding to that output. * If interrupts are desired, configure the following bits: - Set the LCxINTP bit in the CLCxCON register for rising event. - Set the LCxINTN bit in the CLCxCON register or falling event. - Set the CLCxIE bit of the associated PIE registers. - Set the GIE and PEIE bits of the INTCON register. * Enable the CLCx by setting the LCxEN bit of the CLCxCON register. CLCx Interrupts An interrupt will be generated upon a change in the output value of the CLCx when the appropriate interrupt enables are set. A rising edge detector and a falling edge detector are present in each CLC for this purpose. The CLCxIF bit of the associated PIR registers will be set when either edge detector is triggered and its associated enable bit is set. The LCxINTP enables rising edge interrupts and the LCxINTN bit enables falling edge interrupts. Both are located in the CLCxCON register. To fully enable the interrupt, set the following bits: * LCxON bit of the CLCxCON register * CLCxIE bit of the associated PIE registers * LCxINTP bit of the CLCxCON register (for a rising edge detection) * LCxINTN bit of the CLCxCON register (for a falling edge detection) * PEIE and GIE bits of the INTCON register The CLCxIF bit of the associated PIR registers, must be cleared in software as part of the interrupt service. If another edge is detected while this flag is being cleared, the flag will still be set at the end of the sequence. 24.3 Output Mirror Copies Mirror copies of all LCxCON output bits are contained in the CLCxDATA register. Reading this register reads the outputs of all CLCs simultaneously. This prevents any reading skew introduced by testing or reading the CLCxOUT bits in the individual CLCxCON registers. 24.4 Effects of a Reset The CLCxCON register is cleared to zero as the result of a Reset. All other selection and gating values remain unchanged. 24.5 Operation During Sleep The CLC module operates independently from the system clock and will continue to run during Sleep, provided that the input sources selected remain active. The HFINTOSC remains active during Sleep when the CLC module is enabled and the HFINTOSC is selected as an input source, regardless of the system clock source selected. In other words, if the HFINTOSC is simultaneously selected as the system clock and as a CLC input source, when the CLC is enabled, the CPU will go idle during Sleep, but the CLC will continue to operate and the HFINTOSC will remain active. This will have a direct effect on the Sleep mode current. DS41609A-page 274 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 FIGURE 24-2: CLCxIN[0] CLCxIN[1] CLCxIN[2] CLCxIN[3] CLCxIN[4] CLCxIN[5] CLCxIN[6] CLCxIN[7] INPUT DATA SELECTION AND GATING Data Selection 000 Data GATE 1 lcxd1T LCxD1G1T lcxd1N LCxD1G1N 111 LCxD2G1T LCxD1S<2:0> LCxD2G1N CLCxIN[4] CLCxIN[5] CLCxIN[6] CLCxIN[7] CLCxIN[8] CLCxIN[9] CLCxIN[10] CLCxIN[11] lcxg1 000 LCxD3G1T lcxd2T LCxG1POL LCxD3G1N lcxd2N LCxD4G1T 111 LCxD2S<2:0> CLCxIN[8] CLCxIN[9] CLCxIN[10] CLCxIN[11] CLCxIN[12] CLCxIN[13] CLCxIN[14] CLCxIN[15] LCxD4G1N 000 Data GATE 2 lcxg2 lcxd3T (Same as Data GATE 1) lcxd3N Data GATE 3 111 lcxg3 LCxD3S<2:0> CLCxIN[12] CLCxIN[13] CLCxIN[14] CLCxIN[15] CLCxIN[0] CLCxIN[1] CLCxIN[2] CLCxIN[3] (Same as Data GATE 1) Data GATE 4 000 lcxg4 (Same as Data GATE 1) lcxd4T lcxd4N 111 LCxD4S<2:0> Note: All controls are undefined at power-up. 2011 Microchip Technology Inc. Preliminary DS41609A-page 275 PIC16(L)F1508/9 FIGURE 24-3: PROGRAMMABLE LOGIC FUNCTIONS AND - OR OR - XOR lcxg1 lcxg1 lcxg2 lcxg2 lcxq lcxg3 lcxq lcxg3 lcxg4 lcxg4 LCxMODE<2:0>= 000 LCxMODE<2:0>= 001 4-Input AND S-R Latch lcxg1 lcxg1 lcxg2 lcxg2 lcxq lcxg3 S lcxg3 lcxg4 R lcxg4 LCxMODE<2:0>= 010 lcxq Q LCxMODE<2:0>= 011 1-Input D Flip-Flop with S and R 2-Input D Flip-Flop with R lcxg4 lcxg2 D S lcxg4 Q lcxq D lcxg2 lcxg1 lcxg1 Q lcxq R R lcxg3 lcxg3 LCxMODE<2:0>= 100 LCxMODE<2:0>= 101 J-K Flip-Flop with R 1-Input Transparent Latch with S and R lcxg4 lcxg2 J Q lcxq lcxg1 lcxg4 K R lcxg2 D lcxg1 LE lcxg3 S Q lcxq R lcxg3 LCxMODE<2:0>= 110 DS41609A-page 276 LCxMODE<2:0>= 111 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 24.6 CLCx Control Registers REGISTER 24-1: CLCxCON: CONFIGURABLE LOGIC CELL CONTROL REGISTER R/W-0/0 R/W-0/0 R-0/0 R/W-0/0 R/W-0/0 LCxEN LCxOE LCxOUT LCxINTP LCxINTN R/W-0/0 R/W-0/0 R/W-0/0 LCxMODE<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 LCxEN: Configurable Logic Cell Enable bit 1 = Configurable logic cell is enabled and mixing input signals 0 = Configurable logic cell is disabled and has logic zero output bit 6 LCxOE: Configurable Logic Cell Output Enable bit 1 = Configurable logic cell port pin output enabled 0 = Configurable logic cell port pin output disabled bit 5 LCxOUT: Configurable Logic Cell Data Output bit Read-only: logic cell output data, after LCxPOL; sampled from lcx_out wire. bit 4 LCxINTP: Configurable Logic Cell Positive Edge Going Interrupt Enable bit 1 = CLCxIF will be set when a rising edge occurs on lcx_out 0 = CLCxIF will not be set bit 3 LCxINTN: Configurable Logic Cell Negative Edge Going Interrupt Enable bit 1 = CLCxIF will be set when a falling edge occurs on lcx_out 0 = CLCxIF will not be set bit 2-0 LCxMODE<2:0>: Configurable Logic Cell Functional Mode bits 111 = Cell is 1-input transparent latch with S and R 110 = Cell is J-K flip-flop with R 101 = Cell is 2-input D flip-flop with R 100 = Cell is 1-input D flip-flop with S and R 011 = Cell is S-R latch 010 = Cell is 4-input AND 001 = Cell is OR-XOR 000 = Cell is AND-OR 2011 Microchip Technology Inc. Preliminary DS41609A-page 277 PIC16(L)F1508/9 REGISTER 24-2: CLCxPOL: SIGNAL POLARITY CONTROL REGISTER R/W-0/0 U-0 U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u LCxPOL -- -- -- LCxG4POL LCxG3POL LCxG2POL LCxG1POL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 LCxPOL: LCOUT Polarity Control bit 1 = The output of the logic cell is inverted 0 = The output of the logic cell is not inverted bit 6-4 Unimplemented: Read as `0' bit 3 LCxG4POL: Gate 4 Output Polarity Control bit 1 = The output of gate 4 is inverted when applied to the logic cell 0 = The output of gate 4 is not inverted bit 2 LCxG3POL: Gate 3 Output Polarity Control bit 1 = The output of gate 3 is inverted when applied to the logic cell 0 = The output of gate 3 is not inverted bit 1 LCxG2POL: Gate 2 Output Polarity Control bit 1 = The output of gate 2 is inverted when applied to the logic cell 0 = The output of gate 2 is not inverted bit 0 LCxG1POL: Gate 1 Output Polarity Control bit 1 = The output of gate 1 is inverted when applied to the logic cell 0 = The output of gate 1 is not inverted DS41609A-page 278 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 REGISTER 24-3: U-0 CLCxSEL0: MULTIPLEXER DATA 1 AND 2 SELECT REGISTER R/W-x/u -- R/W-x/u R/W-x/u LCxD2S<2:0> U-0 -- R/W-x/u R/W-x/u R/W-x/u LCxD1S<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 Unimplemented: Read as `0' bit 6-4 LCxD2S<2:0>: Input Data 2 Selection Control bits(1) 111 = CLCxIN[11] is selected for lcxd2 110 = CLCxIN[10] is selected for lcxd2 101 = CLCxIN[9] is selected for lcxd2 100 = CLCxIN[8] is selected for lcxd2 011 = CLCxIN[7] is selected for lcxd2 010 = CLCxIN[6] is selected for lcxd2 001 = CLCxIN[5] is selected for lcxd2 000 = CLCxIN[4] is selected for lcxd2 bit 3 Unimplemented: Read as `0' bit 2-0 LCxD1S<2:0>: Input Data 1 Selection Control bits(1) 111 = CLCxIN[7] is selected for lcxd1 110 = CLCxIN[6] is selected for lcxd1 101 = CLCxIN[5] is selected for lcxd1 100 = CLCxIN[4] is selected for lcxd1 011 = CLCxIN[3] is selected for lcxd1 010 = CLCxIN[2] is selected for lcxd1 001 = CLCxIN[1] is selected for lcxd1 000 = CLCxIN[0] is selected for lcxd1 Note 1: See Table 24-1 for signal names associated with inputs. 2011 Microchip Technology Inc. Preliminary DS41609A-page 279 PIC16(L)F1508/9 REGISTER 24-4: U-0 CLCxSEL1: MULTIPLEXER DATA 3 AND 4 SELECT REGISTER R/W-x/u -- R/W-x/u R/W-x/u LCxD4S<2:0> U-0 -- R/W-x/u R/W-x/u R/W-x/u LCxD3S<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 Unimplemented: Read as `0' bit 6-4 LCxD4S<2:0>: Input Data 4 Selection Control bits(1) 111 = CLCxIN[3] is selected for lcxd4 110 = CLCxIN[2] is selected for lcxd4 101 = CLCxIN[1] is selected for lcxd4 100 = CLCxIN[0] is selected for lcxd4 011 = CLCxIN[15] is selected for lcxd4 010 = CLCxIN[14] is selected for lcxd4 001 = CLCxIN[13] is selected for lcxd4 000 = CLCxIN[12] is selected for lcxd4 bit 3 Unimplemented: Read as `0' bit 2-0 LCxD3S<2:0>: Input Data 3 Selection Control bits(1) 111 = CLCxIN[15] is selected for lcxd3 110 = CLCxIN[14] is selected for lcxd3 101 = CLCxIN[13] is selected for lcxd3 100 = CLCxIN[12] is selected for lcxd3 011 = CLCxIN[11] is selected for lcxd3 010 = CLCxIN[10] is selected for lcxd3 001 = CLCxIN[9] is selected for lcxd3 000 = CLCxIN[8] is selected for lcxd3 Note 1: See Table 24-1 for signal names associated with inputs. DS41609A-page 280 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 REGISTER 24-5: CLCxGLS0: GATE 1 LOGIC SELECT REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LCxG1D4T LCxG1D4N LCxG1D3T LCxG1D3N LCxG1D2T LCxG1D2N LCxG1D1T LCxG1D1N bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 LCxG1D4T: Gate 1 Data 4 True (non-inverted) bit 1 = lcxd4T is gated into lcxg1 0 = lcxd4T is not gated into lcxg1 bit 6 LCxG1D4N: Gate 1 Data 4 Negated (inverted) bit 1 = lcxd4N is gated into lcxg1 0 = lcxd4N is not gated into lcxg1 bit 5 LCxG1D3T: Gate 1 Data 3 True (non-inverted) bit 1 = lcxd3T is gated into lcxg1 0 = lcxd3T is not gated into lcxg1 bit 4 LCxG1D3N: Gate 1 Data 3 Negated (inverted) bit 1 = lcxd3N is gated into lcxg1 0 = lcxd3N is not gated into lcxg1 bit 3 LCxG1D2T: Gate 1 Data 2 True (non-inverted) bit 1 = lcxd2T is gated into lcxg1 0 = lcxd2T is not gated into lcxg1 bit 2 LCxG1D2N: Gate 1 Data 2 Negated (inverted) bit 1 = lcxd2N is gated into lcxg1 0 = lcxd2N is not gated into lcxg1 bit 1 LCxG1D1T: Gate 1 Data 1 True (non-inverted) bit 1 = lcxd1T is gated into lcxg1 0 = lcxd1T is not gated into lcxg1 bit 0 LCxG1D1N: Gate 1 Data 1 Negated (inverted) bit 1 = lcxd1N is gated into lcxg1 0 = lcxd1N is not gated into lcxg1 2011 Microchip Technology Inc. Preliminary DS41609A-page 281 PIC16(L)F1508/9 REGISTER 24-6: CLCxGLS1: GATE 2 LOGIC SELECT REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LCxG2D4T LCxG2D4N LCxG2D3T LCxG2D3N LCxG2D2T LCxG2D2N LCxG2D1T LCxG2D1N bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 LCxG2D4T: Gate 2 Data 4 True (non-inverted) bit 1 = lcxd4T is gated into lcxg2 0 = lcxd4T is not gated into lcxg2 bit 6 LCxG2D4N: Gate 2 Data 4 Negated (inverted) bit 1 = lcxd4N is gated into lcxg2 0 = lcxd4N is not gated into lcxg2 bit 5 LCxG2D3T: Gate 2 Data 3 True (non-inverted) bit 1 = lcxd3T is gated into lcxg2 0 = lcxd3T is not gated into lcxg2 bit 4 LCxG2D3N: Gate 2 Data 3 Negated (inverted) bit 1 = lcxd3N is gated into lcxg2 0 = lcxd3N is not gated into lcxg2 bit 3 LCxG2D2T: Gate 2 Data 2 True (non-inverted) bit 1 = lcxd2T is gated into lcxg2 0 = lcxd2T is not gated into lcxg2 bit 2 LCxG2D2N: Gate 2 Data 2 Negated (inverted) bit 1 = lcxd2N is gated into lcxg2 0 = lcxd2N is not gated into lcxg2 bit 1 LCxG2D1T: Gate 2 Data 1 True (non-inverted) bit 1 = lcxd1T is gated into lcxg2 0 = lcxd1T is not gated into lcxg2 bit 0 LCxG2D1N: Gate 2 Data 1 Negated (inverted) bit 1 = lcxd1N is gated into lcxg2 0 = lcxd1N is not gated into lcxg2 DS41609A-page 282 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 REGISTER 24-7: CLCxGLS2: GATE 3 LOGIC SELECT REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LCxG3D4T LCxG3D4N LCxG3D3T LCxG3D3N LCxG3D2T LCxG3D2N LCxG3D1T LCxG3D1N bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 LCxG3D4T: Gate 3 Data 4 True (non-inverted) bit 1 = lcxd4T is gated into lcxg3 0 = lcxd4T is not gated into lcxg3 bit 6 LCxG3D4N: Gate 3 Data 4 Negated (inverted) bit 1 = lcxd4N is gated into lcxg3 0 = lcxd4N is not gated into lcxg3 bit 5 LCxG3D3T: Gate 3 Data 3 True (non-inverted) bit 1 = lcxd3T is gated into lcxg3 0 = lcxd3T is not gated into lcxg3 bit 4 LCxG3D3N: Gate 3 Data 3 Negated (inverted) bit 1 = lcxd3N is gated into lcxg3 0 = lcxd3N is not gated into lcxg3 bit 3 LCxG3D2T: Gate 3 Data 2 True (non-inverted) bit 1 = lcxd2T is gated into lcxg3 0 = lcxd2T is not gated into lcxg3 bit 2 LCxG3D2N: Gate 3 Data 2 Negated (inverted) bit 1 = lcxd2N is gated into lcxg3 0 = lcxd2N is not gated into lcxg3 bit 1 LCxG3D1T: Gate 3 Data 1 True (non-inverted) bit 1 = lcxd1T is gated into lcxg3 0 = lcxd1T is not gated into lcxg3 bit 0 LCxG3D1N: Gate 3 Data 1 Negated (inverted) bit 1 = lcxd1N is gated into lcxg3 0 = lcxd1N is not gated into lcxg3 2011 Microchip Technology Inc. Preliminary DS41609A-page 283 PIC16(L)F1508/9 REGISTER 24-8: CLCxGLS3: GATE 4 LOGIC SELECT REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LCxG4D4T LCxG4D4N LCxG4D3T LCxG4D3N LCxG4D2T LCxG4D2N LCxG4D1T LCxG4D1N bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 LCxG4D4T: Gate 4 Data 4 True (non-inverted) bit 1 = lcxd4T is gated into lcxg4 0 = lcxd4T is not gated into lcxg4 bit 6 LCxG4D4N: Gate 4 Data 4 Negated (inverted) bit 1 = lcxd4N is gated into lcxg4 0 = lcxd4N is not gated into lcxg4 bit 5 LCxG4D3T: Gate 4 Data 3 True (non-inverted) bit 1 = lcxd3T is gated into lcxg4 0 = lcxd3T is not gated into lcxg4 bit 4 LCxG4D3N: Gate 4 Data 3 Negated (inverted) bit 1 = lcxd3N is gated into lcxg4 0 = lcxd3N is not gated into lcxg4 bit 3 LCxG4D2T: Gate 4 Data 2 True (non-inverted) bit 1 = lcxd2T is gated into lcxg4 0 = lcxd2T is not gated into lcxg4 bit 2 LCxG4D2N: Gate 4 Data 2 Negated (inverted) bit 1 = lcxd2N is gated into lcxg4 0 = lcxd2N is not gated into lcxg4 bit 1 LCxG4D1T: Gate 4 Data 1 True (non-inverted) bit 1 = lcxd1T is gated into lcxg4 0 = lcxd1T is not gated into lcxg4 bit 0 LCxG4D1N: Gate 4 Data 1 Negated (inverted) bit 1 = lcxd1N is gated into lcxg4 0 = lcxd1N is not gated into lcxg4 DS41609A-page 284 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 REGISTER 24-9: CLCDATA: CLC DATA OUTPUT U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0 -- -- -- -- MLC4OUT MLC3OUT MLC2OUT MLC1OUT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-4 Unimplemented: Read as `0' bit 3 MLC4OUT: Mirror copy of LC4OUT bit bit 2 MLC3OUT: Mirror copy of LC3OUT bit bit 1 MLC2OUT: Mirror copy of LC2OUT bit bit 0 MLC1OUT: Mirror copy of LC1OUT bit 2011 Microchip Technology Inc. Preliminary DS41609A-page 285 PIC16(L)F1508/9 TABLE 24-3: Name SUMMARY OF REGISTERS ASSOCIATED WITH CLCx Bit4 BIt3 Bit2 -- ANSC3 ANSC2 SSSEL T1GSEL -- Bit0 Register on Page ANSC1 ANSC0 123 CLC1SEL NCO1SEL 112 Bit7 Bit6 Bit5 Bit1 ANSELC ANSC7 ANSC6 -- APFCON -- -- -- CLC1CON LC1EN LC1OE LC1OUT LC1INTP LC1INTN LC1MODE<2:0> 277 CLC2CON LC2EN LC2OE LC2OUT LC2INTP LC2INTN LC2MODE<2:0> 277 CLCDATA -- -- -- -- MLC4OUT MLC3OUT MLC2OUT MLC1OUT 281 CLC1GLS0 LC1G1D4T LC1G1D4N LC1G1D3T LC1G1D3N LC1G1D2T LC1G1D2N LC1G1D1T LC1G1D1N 281 CLC1GLS1 LC1G2D4T LC1G2D4N LC1G2D3T LC1G2D3N LC1G2D2T LC1G2D2N LC1G2D1T LC1G2D1N 282 CLC1GLS2 LC1G3D4T LC1G3D4N LC1G3D3T LC1G3D3N LC1G3D2T LC1G3D2N LC1G3D1T LC1G3D1N 283 CLC1GLS3 LC1G4D4T LC1G4D4N LC1G4D3T LC1G4D3N LC1G4D2T LC1G4D2N LC1G4D1T LC1G4D1N 284 CLC1POL LC1POL -- -- -- LC1G4POL LC1G3POL LC1G2POL LC1G1POL 278 CLC1SEL0 -- LC1D2S<2:0> -- LC1D1S<2:0> 279 CLC1SEL1 -- LC1D4S<2:0> -- LC1D3S<2:0> 280 CLC2GLS0 LC2G1D4T LC2G1D4N LC2G1D3T LC2G1D3N LC2G1D2T LC2G1D2N LC2G1D1T LC2G1D1N 281 CLC2GLS1 LC2G2D4T LC2G2D4N LC2G2D3T LC2G2D3N LC2G2D2T LC2G2D2N LC2G2D1T LC2G2D1N 282 CLC2GLS2 LC2G3D4T LC2G3D4N LC2G3D3T LC2G3D3N LC2G3D2T LC2G3D2N LC2G3D1T LC2G3D1N 283 CLC2GLS3 LC2G4D4T LC2G4D4N LC2G4D3T LC2G4D3N LC2G4D2T LC2G4D2N LC2G4D1T LC2G4D1N 284 CLC2POL LC2POL -- -- -- LC2G4POL LC2G3POL LC2G2POL LC2G1POL 278 CLC2SEL0 -- LC2D2S<2:0> -- LC2D4S<2:0> LC2D1S<2:0> -- 279 CLC2SEL1 -- CLC3GLS0 LC3G1D4T LC3G1D4N LC3G1D3T LC3G1D3N LC3G1D2T LC3G1D2N LC2D3S<2:0> LC3G1D1T LC3G1D1N 280 281 CLC3GLS1 LC3G2D4T LC3G2D4N LC3G2D3T LC3G2D3N LC3G2D2T LC3G2D2N LC3G2D1T LC3G2D1N 282 CLC3GLS2 LC3G3D4T LC3G3D4N LC3G3D3T LC3G3D3N LC3G3D2T LC3G3D2N LC3G3D1T LC3G3D1N 283 CLC3GLS3 LC3G4D4T LC3G4D4N LC3G4D3T LC3G4D3N LC3G4D2T LC3G4D2N LC3G4D1T LC3G4D1N 284 -- -- -- LC3G4POL LC3G3POL LC3G2POL LC3G1POL 278 CLC3POL LC3POL CLC3SEL0 -- LC3D2S<2:0> -- LC3D1S<2:0> 279 CLC3SEL1 -- LC3D4S<2:0> -- LC3D3S<2:0> 280 CLC4GLS0 LC4G1D4T LC4G1D4N LC4G1D3T LC4G1D3N LC4G1D2T LC4G1D2N LC4G1D1T LC4G1D1N 281 CLC4GLS1 LC4G2D4T LC4G2D4N LC4G2D3T LC4G2D3N LC4G2D2T LC4G2D2N LC4G2D1T LC4G2D1N 282 CLC4GLS2 LC4G3D4T LC4G3D4N LC4G3D3T LC4G3D3N LC4G3D2T LC4G3D2N LC4G3D1T LC4G3D1N 283 CLC4GLS3 LC4G4D4T LC4G4D4N LC4G4D3T LC4G4D3N LC4G4D2T LC4G4D2N LC4G4D1T LC4G4D1N 284 CLC4POL LC4POL -- -- -- LC4G4POL LC4G3POL LC4G2POL LC4G1POL 278 CLC4SEL0 -- LC4D2S<2:0> -- LC4D1S<2:0> CLC4SEL1 -- LC4D4S<2:0> -- LC4D3S<2:0> 279 280 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 78 PIE3 -- -- -- -- CLC4IE CLC3IE CLC2IE CLC1IE 81 PIR3 -- -- -- -- CLC4IF CLC3IF CLC2IF CLC1IF 84 TRISA2 TRISA1 TRISA0 114 TRISC2 TRISC1 TRISC0 122 INTCON TRISA -- -- TRISA5 TRISA4 --(1) TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 Legend: Note 1: -- = unimplemented read as `0',. Shaded cells are not used for CLC module. Unimplemented, read as `1'. DS41609A-page 286 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 25.0 NUMERICALLY CONTROLLED OSCILLATOR (NCO) MODULE The Numerically Controlled Oscillator (NCOx) module is a timer that uses the overflow from the addition of an increment value to divide the input frequency. The advantage of the addition method over simple counter driven timer is that the resolution of division does not vary with the divider value. The NCOx is most useful for applications that require frequency accuracy and fine resolution at a fixed duty cycle. Features of the NCOx include: * * * * * * * 16-bit increment function Fixed Duty Cycle (FDC) mode Pulse Frequency (PF) mode Output pulse width control Multiple clock input sources Output polarity control Interrupt capability Figure 25-1 is a simplified block diagram of the NCOx module. 2011 Microchip Technology Inc. Preliminary DS41609A-page 287 NUMERICALLY CONTROLLED OSCILLATOR (NCOx) MODULE SIMPLIFIED BLOCK DIAGRAM Increment 16 (1) Buffer 16 Interrupt event Set NCOxIF flag NCO1CLK 20 11 LC1OUT FOSC Preliminary HFINTOSC 10 Accumulator 01 20 00 D NCOxOUT Q NxOE Overflow Q NCOx Clock TRIS Control 0 NxEN NCOx 1 2 NxCKS<2:0> Overflow S Q NxPFM NxPOL R 3 2011 Microchip Technology Inc. NCOx Clock Ripple Counter Note 1: To CLC, CWG Q NxPWS<2:0> Reset The increment registers are double-buffered to allow for value changes to be made without first disabling the NCOx module. They are shown here for reference. The buffers are not user-accessible. PIC16(L)F1508/9 DS41609A-page 288 FIGURE 25-1: PIC16(L)F1508/9 25.1 NCOx OPERATION 25.1.3 ADDER The NCOx operates by repeatedly adding a fixed value to an accumulator. Additions occur at the input clock rate. The accumulator will overflow with a carry periodically, which is the raw NCOx output. This effectively reduces the input clock by the ratio of the addition value to the maximum accumulator value. See Equation 25-1. The NCOx Adder is a full adder, which operates independently from the system clock. The addition of the previous result and the increment value replaces the accumulator value on the rising edge of each input clock. The NCOx output can be further modified by stretching the pulse or toggling a flip-flop. The modified NCOx output is then distributed internally to other peripherals and optionally output to a pin. The accumulator overflow also generates an interrupt. The Increment value is stored in two 8-bit registers making up a 16-bit increment. In order of LSB to MSB they are: The NCOx period changes in discrete steps to create an average frequency. This output depends on the ability of the receiving circuit (i.e., CWG or external resonant converter circuitry) to average the NCOx output to reduce uncertainty. Both of the registers are readable and writeable. The Increment registers are double-buffered to allow for value changes to be made without first disabling the NCOx module. 25.1.1 NCOx CLOCK SOURCES Clock sources available to the NCOx include: * * * * HFINTOSC FOSC LC1OUT CLKIN pin 25.1.4 INCREMENT REGISTERS * NCOxINCL * NCOxINCH The buffer loads are immediate when the module is disabled. Writing to the NCOxINCH register first is necessary because then the buffer is loaded synchronously with the NCOx operation after the write is executed on the NCOxINCL register. Note: The increment buffer registers are not user-accessible. The NCOx clock source is selected by configuring the NxCKS<2:0> bits in the NCOxCLK register. 25.1.2 ACCUMULATOR The accumulator is a 20-bit register. Read and write access to the accumulator is available through three registers: * NCOxACCL * NCOxACCH * NCOxACCU EQUATION 25-1: NCO Clock Frequency Increment Value F OVERFLOW = --------------------------------------------------------------------------------------------------------------n 2 n = Accumulator width in bits 2011 Microchip Technology Inc. Preliminary DS41609A-page 289 PIC16(L)F1508/9 25.2 FIXED DUTY CYCLE (FDC) MODE In Fixed Duty Cycle (FDC) mode, every time the accumulator overflows, the output is toggled. This provides a 50% duty cycle, provided that the increment value remains constant. For more information, see Figure 25-2. The FDC mode is selected by clearing the NxPFM bit in the NCOxCON register. 25.3 PULSE FREQUENCY (PF) MODE In Pulse Frequency (PF) mode, every time the accumulator overflows, the output becomes active for one or more clock periods. Once the clock period expires, the output returns to an inactive state. This provides a pulsed output. The output becomes active on the rising clock edge immediately following the overflow event. For more information, see Figure 25-2. The value of the active and inactive states depends on the polarity bit, NxPOL in the NCOxCON register. The PF mode is selected by setting the NxPFM bit in the NCOxCON register. 25.3.1 OUTPUT PULSE WIDTH CONTROL When operating in PF mode, the active state of the output can vary in width by multiple clock periods. Various pulse widths are selected with the NxPWS<2:0> bits in the NCOxCLK register. When the selected pulse width is greater than the accumulator overflow time frame, the output of the NCOx operation is indeterminate. 25.4 OUTPUT POLARITY CONTROL The last stage in the NCOx module is the output polarity. The NxPOL bit in the NCOxCON register selects the output polarity. Changing the polarity while the interrupts are enabled will cause an interrupt for the resulting output transition. The NCOx output can be used internally by source code or other peripherals. Accomplish this by reading the NxOUT (read-only) bit of the NCOxCON register. DS41609A-page 290 Preliminary 2011 Microchip Technology Inc. FDC OUTPUT MODE OPERATION DIAGRAM Clock Source NCOx Increment Value NCOx Accumulator Input 2000h 02000h 04000h 06000h 08000h 0A000h 0C000h 0E000h 10000h 02000h 04000h 06000h 08000h 0A000h 0C000h 0E000h 10000h 02000h 2000h 4000h 6000h 8000h A000h C000h E000h 0000h 04000h Tadder Overflow is the MSB of the accumulator Accumulator Input Overflow Preliminary Tadder_ NCOx Accumulator Value 0000h 2000h 4000h 6000h 8000h A000h C000h E000h 0000h Tadder Overflow PWS = 000 Interrupt Event 2011 Microchip Technology Inc. NCOx Output FDC mode NCOx Output PF mode NCOX PWS = 000 NCOx Output PF mode NCOx PWS = 010 Tadder 2000h PIC16(L)F1508/9 DS41609A-page 291 FIGURE 25-2: PIC16(L)F1508/9 25.5 Interrupts When the accumulator overflows, the NCOx Interrupt Flag bit, NCOxIF, of the PIRx register is set. To enable the interrupt event, the following bits must be set: * * * * NxEN bit of the NCOxCON register NCOxIE bit of the PIEx register PEIE bit of the INTCON register GIE bit of the INTCON register The interrupt must be cleared by software by clearing the NCOxIF bit in the Interrupt Service Routine. 25.6 Effects of a Reset All of the NCOx registers are cleared to zero as the result of a Reset. 25.7 Operation In Sleep The NCO module operates independently from the system clock and will continue to run during Sleep, provided that the clock source selected remains active. The HFINTOSC remains active during Sleep when the NCO module is enabled and the HFINTOSC is selected as the clock source, regardless of the system clock source selected. In other words, if the HFINTOSC is simultaneously selected as the system clock and the NCO clock source, when the NCO is enabled, the CPU will go idle during Sleep, but the NCO will continue to operate and the HFINTOSC will remain active. This will have a direct effect on the Sleep mode current. 25.8 Alternate Pin Locations This module incorporates I/O pins that can be moved to other locations with the use of the alternate pin function register, APFCON. To determine which pins can be moved and what their default locations are upon a Reset, see Section 11.1 "Alternate Pin Function" for more information. DS41609A-page 292 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 25.9 NCOx Control Registers REGISTER 25-1: NCOxCON: NCOx CONTROL REGISTER R/W-0/0 R/W-0/0 R-0/0 R/W-0/0 U-0 U-0 U-0 R/W-0/0 NxEN NxOE NxOUT NxPOL -- -- -- NxPFM bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 NxEN: NCOx Enable bit 1 = NCOx module is enabled 0 = NCOx module is disabled bit 6 NxOE: NCOx Output Enable bit 1 = NCOx output pin is enabled 0 = NCOx output pin is disabled bit 5 NxOUT: NCOx Output bit 1 = NCOx output is high 0 = NCOx output is low bit 4 NxPOL: NCOx Polarity bit 1 = NCOx output signal is active-high 0 = NCOx output signal is active-low bit 3-1 Unimplemented: Read as `0'. bit 0 NxPFM: NCOx Pulse Frequency Mode bit 1 = NCOx operates in Pulse Frequency mode 0 = NCOx operates in Fixed Duty Cycle mode REGISTER 25-2: R/W-0/0 NCOxCLK: NCOx INPUT CLOCK CONTROL REGISTER R/W-0/0 R/W-0/0 NxPWS<2:0> U-0 U-0 U-0 -- -- -- R/W-0/0 R/W-0/0 NxCKS<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-5 NxPWS<2:0>: NCOx Output Pulse Width Select bits(1, 2) 111 = 128 NCOx clock periods 110 = 64 NCOx clock periods 101 = 32 NCOx clock periods 100 = 16 NCOx clock periods 011 = 8 NCOx clock periods 010 = 4 NCOx clock periods 001 = 2 NCOx clock periods 000 = 1 NCOx clock periods bit 4-2 Unimplemented: Read as `0' bit 1-0 NxCKS<1:0>: NCOx Clock Source Select bits 11 = NCO1CLK 10 = LC1OUT 01 = FOSC 00 = HFINTOSC (16 MHz) Note 1: NxPWS applies only when operating in Pulse Frequency mode. 2: If NCOx pulse width is greater than NCOx overflow period, operation is undeterminate. 2011 Microchip Technology Inc. Preliminary DS41609A-page 293 PIC16(L)F1508/9 REGISTER 25-3: R/W-0/0 NCOxACCL: NCOx ACCUMULATOR REGISTER - LOW BYTE R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 NCOxACC<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 NCOxACC<7:0>: NCOx Accumulator, low byte REGISTER 25-4: R/W-0/0 NCOxACCH: NCOx ACCUMULATOR REGISTER - HIGH BYTE R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 NCOxACC<15:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 NCOxACC<15:8>: NCOx Accumulator, high byte REGISTER 25-5: NCOxACCU: NCOx ACCUMULATOR REGISTER - UPPER BYTE U-0 U-0 U-0 U-0 -- -- -- -- R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 NCOxACC<19:16> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-4 Unimplemented: Read as `0' bit 3-0 NCOxACC<19:16>: NCOx Accumulator, upper byte DS41609A-page 294 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 REGISTER 25-6: R/W-0/0 NCOxINCL: NCOx INCREMENT REGISTER - LOW BYTE R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-1/1 NCOxINC<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 NCOxINC<7:0>: NCOx Increment, low byte REGISTER 25-7: R/W-0/0 NCOxINCH: NCOx INCREMENT REGISTER - HIGH BYTE R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 NCOxINC<15:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 NCOxINC<15:8>: NCOx Increment, high byte 2011 Microchip Technology Inc. Preliminary DS41609A-page 295 PIC16(L)F1508/9 TABLE 25-1: Name SUMMARY OF REGISTERS ASSOCIATED WITH NCOx Bit 2 Bit 1 Bit 0 Register on Page T1GSEL -- CLC1SEL NCO1SEL 112 IOCIE TMR0IF INTF IOCIF 78 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 APFCON -- -- -- SSSEL INTCON GIE PEIE TMR0IE INTE NCO1ACCH NCO1ACC<15:8> 294 NCO1ACCL NCO1ACC<7:0> 294 -- NCO1ACCU NCO1CLK NCO1CON NCO1ACC<19:16> N1PWS<2:0> N1EN N1OE N1OUT NCO1INCH -- -- -- N1POL -- -- 294 N1CKS<1:0> -- N1PFM NCO1INC<15:8> NCO1INCL 293 293 295 NCO1INC<7:0> 295 PIE2 OSFIE C2IE C1IE -- BCL1IE NCO1IE -- -- PIR2 OSFIF C2IF C1IF -- BCL1IF NCO1IF -- -- 83 -- -- TRISA5 TRISA4 --(1) TRISA2 TRISA1 TRISA0 114 TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 122 TRISA TRISC Legend: Note 1: 80 x = unknown, u = unchanged, -- = unimplemented read as `0', q = value depends on condition. Shaded cells are not used for NCOx module. Unimplemented, read as `1'. DS41609A-page 296 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 26.0 COMPLEMENTARY WAVEFORM GENERATOR (CWG) MODULE The Complementary Waveform Generator (CWG) produces a complementary waveform with dead-band delay from a selection of input sources. The CWG module has the following features: * * * * * Selectable dead-band clock source control Selectable input sources Output enable control Output polarity control Dead-band control with independent 6-bit rising and falling edge dead-band counters * Auto-shutdown control with: - Selectable shutdown sources - Auto-restart enable - Auto-shutdown pin override control 2011 Microchip Technology Inc. Preliminary DS41609A-page 297 2011 Microchip Technology Inc. FIGURE 26-1: SIMPLIFIED CWG BLOCK DIAGRAM GxASDLA GxCS 00 1 FOSC 2 `0' 10 `1' 11 1 cwg_clock GxASDLA = 01 GxOEA CWGxDBR HFINTOSC 6 GxIS 1 3 Preliminary async_C1OUT async_C2OUT PWM1OUT PWM2OUT PWM3OUT PWM4OUT NCO1OUT LC1OUT EN R S Q R Q = 0 TRISx GxPOLA Input Source CWGxA CWGxDBF 6 EN GxOEB R TRISx = 0 GxPOLB 1 CWGxB GxASDLB = 01 CWG1FLT (INT pin) `0' 10 GxASDFLT async_C1OUT GxASDC1 async_C2OUT GxASDC2 LC2OUT GxASCLC `1' 11 DS41609A-page 298 GxASE Data Bit WRITE x = CWG module number GxASE Auto-Shutdown Source GxARSEN S Q R Q set dominate D S Q shutdown GxASDLB 2 PIC16(L)F1508/9 00 PIC16(L)F1508/9 FIGURE 26-2: TYPICAL CWG OPERATION WITH PWM1 (NO AUTO-SHUTDOWN) cwg_clock PWM1 CWGxA Rising Edge Dead Band Falling Edge Dead Band Rising Edge Dead Band Rising Edge D Falling Edge Dead Band CWGxB 2011 Microchip Technology Inc. Preliminary DS41609A-page 299 PIC16(L)F1508/9 26.1 Fundamental Operation The CWG generates a two output complementary waveform from one of four selectable input sources. The off-to-on transition of each output can be delayed from the on-to-off transition of the other output, thereby, creating a time delay immediately where neither output is driven. This is referred to as dead time and is covered in Section 26.5 "Dead-Band Control". A typical operating waveform, with dead band, generated from a single input signal is shown in Figure 26-2. It may be necessary to guard against the possibility of circuit faults or a feedback event arriving too late or not at all. In this case, the active drive must be terminated before the Fault condition causes damage. This is referred to as auto-shutdown and is covered in Section 26.9 "Auto-shutdown Control". 26.2 Clock Source The CWG module allows the following clock sources to be selected: * Fosc (system clock) * HFINTOSC (16 MHz only) The clock sources are selected using the G1CS0 bit of the CWGxCON0 register (Register 26-1). 26.3 async_C1OUT async_C2OUT PWM1OUT PWM2OUT PWM3OUT PWM4OUT NCO1OUT LC1OUT Output Control Immediately after the CWG module is enabled, the complementary drive is configured with both CWGxA and CWGxB drives cleared. 26.4.1 POLARITY CONTROL The polarity of each CWG output can be selected independently. When the output polarity bit is set, the corresponding output is active high. Clearing the output polarity bit configures the corresponding output as active low. However, polarity does not affect the override levels. Output polarity is selected with the GxPOLA and GxPOLB bits of the CWGxCON0 register. 26.5 Dead-Band Control Dead-band control provides for non-overlapping output signals to prevent shoot-through current in power switches. The CWG contains two 6-bit dead-band counters. One dead-band counter is used for the rising edge of the input source control. The other is used for the falling edge of the input source control. Dead band is timed by counting CWG clock periods from zero up to the value in the rising or falling deadband counter registers. See CWGxDBR and CWGxDBF registers (Register 26-4 and Register 26-5, respectively). Rising Edge Dead Band The rising edge dead-band delays the turn-on of the CWGxA output from when the CWGxB output is turned off. The rising edge dead-band time starts when the rising edge of the input source signal goes true. When this happens, the CWGxB output is immediately turned off and the rising edge dead-band delay time starts. When the rising edge dead-band delay time is reached, the CWGxA output is turned on. The CWGxDBR register sets the duration of the deadband interval on the rising edge of the input source signal. This duration is from 0 to 64 counts of dead band. The input sources are selected using the GxIS<2:0> bits in the CWGxCON1 register (Register 26-2). 26.4 26.4.2 26.6 Selectable Input Sources The CWG can generate the complementary waveform for the following input sources: * * * * * * * * enables are dependent on the module enable bit, GxEN. When GxEN is cleared, CWG output enables and CWG drive levels have no effect. Dead band is always counted off the edge on the input source signal. A count of 0 (zero), indicates that no dead band is present. If the input source signal is not present for enough time for the count to be completed, no output will be seen on the respective output. OUTPUT ENABLES Each CWG output pin has individual output enable control. Output enables are selected with the GxOEA and GxOEB bits of the CWGxCON0 register. When an output enable control is cleared, the module asserts no control over the pin. When an output enable is set, the override value or active PWM waveform is applied to the pin per the port priority selection. The output pin DS41609A-page 300 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 26.7 Falling Edge Dead Band The falling edge dead band delays the turn-on of the CWGxB output from when the CWGxA output is turned off. The falling edge dead-band time starts when the falling edge of the input source goes true. When this happens, the CWGxA output is immediately turned off and the falling edge dead-band delay time starts. When the falling edge dead-band delay time is reached, the CWGxB output is turned on. The CWGxDBF register sets the duration of the deadband interval on the falling edge of the input source signal. This duration is from 0 to 64 counts of dead band. Dead band is always counted off the edge on the input source signal. A count of 0 (zero), indicates that no dead band is present. If the input source signal is not present for enough time for the count to be completed, no output will be seen on the respective output. Refer to Figure 26-3 and Figure 26-4 for examples. 26.8 Dead-Band Uncertainty When the rising and falling edges of the input source triggers the dead-band counters, the input may be asynchronous. This will create some uncertainty in the deadband time delay. The maximum uncertainty is equal to one CWG clock period. Refer to Equation 26-1 for more detail. 2011 Microchip Technology Inc. Preliminary DS41609A-page 301 2011 Microchip Technology Inc. FIGURE 26-3: DEAD-BAND OPERATION, CWGxDBR = 01H, CWGxDBF = 02H cwg_clock Input Source CWGxA CWGxB FIGURE 26-4: DEAD-BAND OPERATION, CWGxDBR = 03H, CWGxDBF = 04H, SOURCE SHORTER THAN DEAD BAND Preliminary cwg_clock Input Source CWGxA DS41609A-page 302 PIC16(L)F1508/9 source shorter than dead band CWGxB PIC16(L)F1508/9 EQUATION 26-1: DEAD-BAND UNCERTAINTY 1 TDEADBAND_UNCERTAINTY = ----------------------------Fcwg_clock Example: Fcwg_clock = 16 MHz Therefore: 1 TDEADBAND_UNCERTAINTY = ----------------------------Fcwg_clock 1 = ------------------16 MHz = 62.5ns 2011 Microchip Technology Inc. Preliminary DS41609A-page 303 PIC16(L)F1508/9 26.9 Auto-shutdown Control 26.10 Operation During Sleep Auto-shutdown is a method to immediately override the CWG output levels with specific overrides that allow for safe shutdown of the circuit. The shutdown state can be either cleared automatically or held until cleared by software. 26.9.1 SHUTDOWN The shutdown state can be entered by either of the following two methods: * Software generated * External Input 26.9.1.1 Software Generated Shutdown Setting the GxASE bit of the CWGxCON2 register will force the CWG into the shutdown state. When auto-restart is disabled, the shutdown state will persist as long as the GxASE bit is set. The CWG module operates independently from the system clock and will continue to run during Sleep, provided that the clock and input sources selected remain active. The HFINTOSC remains active during Sleep, provided that the CWG module is enabled, the input source is active, and the HFINTOSC is selected as the clock source, regardless of the system clock source selected. In other words, if the HFINTOSC is simultaneously selected as the system clock and the CWG clock source, when the CWG is enabled and the input source is active, the CPU will go idle during Sleep, but the CWG will continue to operate and the HFINTOSC will remain active. This will have a direct effect on the Sleep mode current. When auto-restart is enabled, the GxASE bit will clear automatically and resume operation on the next rising edge event. See Figure 26-6. 26.9.1.2 External Input Source External shutdown inputs provide the fastest way to safely suspend CWG operation in the event of a Fault condition. When any of the selected shutdown inputs goes active, the CWG outputs will immediately go to the selected override levels without software delay. Any combination of two input sources can be selected to cause a shutdown condition. The sources are: * * * * async_C1OUT async_C2OUT LC2OUT CWG1FLT Shutdown inputs are selected using the GxASDS0 and GxASDS1 bits of the CWGxCON2 register. (Register 26-3). Note: Shutdown inputs are level sensitive, not edge sensitive. The shutdown state cannot be cleared, except by disabling autoshutdown, as long as the shutdown input level persists. DS41609A-page 304 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 26.11 Configuring the CWG 26.11.1 The following steps illustrate how to properly configure the CWG to ensure a synchronous start: The levels driven to the output pins, while the shutdown input is true, are controlled by the GxASDLA and GxASDLB bits of the CWGxCON2 register (Register 26-3). GxASDLA controls the CWG1A override level and GxASDLB controls the CWG1B override level. The control bit logic level corresponds to the output logic drive level while in the shutdown state. The polarity control does not apply to the override level. 1. 2. 3. 4. 5. 6. 7. 8. 9. Ensure that the TRIS control bits corresponding to CWGxA and CWGxB are set so that both are configured as inputs. Clear the GxEN bit, if not already cleared. Set desired dead-band times with the CWGxDBR and CWGxDBF registers. Setup the following controls in CWGxCON2 auto-shutdown register: * Select desired shutdown source. * Select both output overrides to the desired levels (this is necessary even if not using auto-shutdown because start-up will be from a shutdown state). * Set the GxASE bit and clear the GxARSEN bit. Select the desired input source using the CWGxCON1 register. Configure the following controls in CWGxCON0 register: * Select desired clock source. * Select the desired output polarities. * Set the output enables for the outputs to be used. Set the GxEN bit. Clear TRIS control bits corresponding to CWGxA and CWGxB to be used to configure those pins as outputs. If auto-restart is to be used, set the GxARSEN bit and the GxASE bit will be cleared automatically. Otherwise, clear the GxASE bit to start the CWG. 2011 Microchip Technology Inc. 26.11.2 PIN OVERRIDE LEVELS AUTO-SHUTDOWN RESTART After an auto-shutdown event has occurred, there are two ways to have resume operation: * Software controlled * Auto-restart The restart method is selected with the GxARSEN bit of the CWGxCON2 register. Waveforms of software controlled and automatic restarts are shown in Figure 26-5 and Figure 26-6. 26.11.2.1 Software controlled restart When the GxARSEN bit of the CWGxCON2 register is cleared, the CWG must be restarted after an auto-shutdown event by software. Clearing the shutdown state requires all selected shutdown inputs to be low, otherwise the GxASE bit will remain set. The overrides will remain in effect until the first rising edge event after the GxASE bit is cleared. The CWG will then resume operation. 26.11.2.2 Auto-Restart When the GxARSEN bit of the CWGxCON2 register is set, the CWG will restart from the auto-shutdown state automatically. The GxASE bit will clear automatically when all shutdown sources go low. The overrides will remain in effect until the first rising edge event after the GxASE bit is cleared. The CWG will then resume operation. Preliminary DS41609A-page 305 2011 Microchip Technology Inc. FIGURE 26-5: SHUTDOWN FUNCTIONALITY, AUTO-RESTART DISABLED (GxARSEN = 0,GxASDLA = 01, GxASDLB = 01) Shutdown Event Ceases GxASE Cleared by Software CWG Input Source Shutdown Source GxASE CWG1A Tri-State (No Pulse) CWG1B Tri-State (No Pulse) No Shutdown Preliminary Output Resumes Shutdown FIGURE 26-6: SHUTDOWN FUNCTIONALITY, AUTO-RESTART ENABLED (GxARSEN = 1,GxASDLA = 01, GxASDLB = 01) Shutdown Event Ceases GxASE auto-cleared by hardware Shutdown Source GxASE DS41609A-page 306 CWG1A Tri-State (No Pulse) CWG1B Tri-State (No Pulse) No Shutdown Shutdown Output Resumes PIC16(L)F1508/9 CWG Input Source PIC16(L)F1508/9 26.12 CWG Control Registers REGISTER 26-1: CWGxCON0: CWG CONTROL REGISTER 0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0 GxEN GxOEB GxOEA GxPOLB GxPOLA -- -- GxCS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7 GxEN: CWGx Enable bit 1 = Module is enabled 0 = Module is disabled bit 6 GxOEB: CWGxB Output Enable bit 1 = CWGxB is available on appropriate I/O pin 0 = CWGxB is not available on appropriate I/O pin bit 5 GxOEA: CWGxA Output Enable bit 1 = CWGxA is available on appropriate I/O pin 0 = CWGxA is not available on appropriate I/O pin bit 4 GxPOLB: CWGxB Output Polarity bit 1 = Output is inverted polarity 0 = Output is normal polarity bit 3 GxPOLA: CWGxA Output Polarity bit 1 = Output is inverted polarity 0 = Output is normal polarity bit 2-1 Unimplemented: Read as `0' bit 0 GxCS0: CWGx Clock Source Select bit 1 = HFINTOSC 0 = FOSC 2011 Microchip Technology Inc. Preliminary DS41609A-page 307 PIC16(L)F1508/9 REGISTER 26-2: R/W-x/u CWGxCON1: CWG CONTROL REGISTER 1 R/W-x/u GxASDLB<1:0> R/W-x/u R/W-x/u U-0 GxASDLA<1:0> -- R/W-0/0 R/W-0/0 R/W-0/0 GxIS<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-6 GxASDLB<1:0>: CWGx Shutdown State for CWGxB When an auto shutdown event is present (GxASE = 1): 11 = CWGxB pin is driven to `1', regardless of the setting of the GxPOLB bit. 10 = CWGxB pin is driven to `0', regardless of the setting of the GxPOLB bit. 01 = CWGxB pin is tri-stated 00 = CWGxB pin is driven to it's inactive state after the selected dead-band interval. GxPOLB still will control the polarity of the output. bit 5-4 GxASDLA<1:0>: CWGx Shutdown State for CWGxA When an auto shutdown event is present (GxASE = 1): 11 = CWGxA pin is driven to `1', regardless of the setting of the GxPOLA bit. 10 = CWGxA pin is driven to `0', regardless of the setting of the GxPOLA bit. 01 = CWGxA pin is tri-stated 00 = CWGxA pin is driven to it's inactive state after the selected dead-band interval. GxPOLA still will control the polarity of the output. bit 3 Unimplemented: Read as `0' bit 2-0 GxIS<2:0>: CWGx Input Source Select bits 111 = LC1OUT 110 = NCO1OUT 101 = PWM4OUT 100 = PWM3OUT 011 = PWM2OUT 010 = PWM1OUT 001 = async_C1OUT 000 = async_C2OUT DS41609A-page 308 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 REGISTER 26-3: CWGxCON2: CWG CONTROL REGISTER 2 R/W-0/0 R/W-0/0 GxASE GxARSEN U-0 -- U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 -- GxASDC2 GxASDC1 GxASDFLT GxASDCLC2 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7 GxASE: Auto-Shutdown Event Status bit 1 = An auto-shutdown event has occurred 0 = No auto-shutdown event has occurred bit 6 GxARSEN: Auto-Restart Enable bit 1 = Auto-restart is enabled 0 = Auto-restart is disabled bit 5-4 Unimplemented: Read as `0' bit 3 GxASDC2: CWG Auto-shutdown on Comparator 2 Enable 1 = Shutdown when Comparator 2 output is high 0 = Comparator 2 output has no effect on shutdown bit 2 GxASDC1: CWG Auto-shutdown on Comparator 1 Enable 1 = Shutdown when Comparator 1 output is high 0 = Comparator 1 output has no effect on shutdown bit 1 GxASDFLT: CWG Auto-shutdown on FLT Enable bit 1 = Shutdown when CWG1FLT input is low 0 = CWG1FLT input has no effect on shutdown bit 0 GxASDCLC2: CWG Auto-shutdown on CLC2 Enable bit 1 = Shutdown when LC2OUT is high 0 = LC2OUT has no effect on shutdown 2011 Microchip Technology Inc. Preliminary DS41609A-page 309 PIC16(L)F1508/9 REGISTER 26-4: U-0 CWGxDBR: COMPLEMENTARY WAVEFORM GENERATOR (CWGx) RISING DEAD-BAND COUNT REGISTER U-0 -- R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u CWGxDBR<5:0> -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-6 Unimplemented: Read as `0' bit 5-0 CWGxDBR<5:0>: Complementary Waveform Generator (CWGx) Rising counts 11 1111 = 63-64 counts of dead band 11 1110 = 62-63 counts of dead band 00 0010 = 2-3 counts of dead band 00 0001 = 1-2 counts of dead band 00 0000 = 0 counts of dead band REGISTER 26-5: CWGxDBF: COMPLEMENTARY WAVEFORM GENERATOR (CWGx) FALLING DEAD-BAND COUNT REGISTER U-0 U-0 -- -- R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u CWGxDBF<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-6 Unimplemented: Read as `0' bit 5-0 CWGxDBF<5:0>: Complementary Waveform Generator (CWGx) Falling counts 11 1111 = 63-64 counts of dead band 11 1110 = 62-63 counts of dead band 00 0010 = 2-3 counts of dead band 00 0001 = 1-2 counts of dead band 00 0000 = 0 counts of dead band. Dead-band generation is bypassed. DS41609A-page 310 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 TABLE 26-1: Name ANSELA CWG1CON0 CWG1CON1 CWG1CON2 CWG1DBF CWG1DBR SUMMARY OF REGISTERS ASSOCIATED WITH CWG Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page -- -- -- ANSA4 -- ANSA2 ANSA1 ANSA0 115 G1EN G1OEB G1OEA G1POLB G1POLA -- -- G1CS0 307 -- -- G1ASDC2 G1ASDC1 G1ASDLB<1:0> G1ASDLA<1:0> G1ASDSFLT G1ASDSCLC2 308 309 G1ASE G1ARSEN -- -- CWG1DBF<5:0> 310 -- CWG1DBR<5:0> 310 -- -- -- TRISA -- -- TRISA5 TRISA4 TRISC TRISC7 TRISC6 TRISC5 TRISC4 Legend: Note 1: G1IS<1:0> (1) -- TRISC3 TRISA2 TRISA1 TRISA0 114 TRISC2 TRISC1 TRISC0 122 x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by CWG. Unimplemented, read as `1'. 2011 Microchip Technology Inc. Preliminary DS41609A-page 311 PIC16(L)F1508/9 NOTES: DS41609A-page 312 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 27.0 IN-CIRCUIT SERIAL PROGRAMMINGTM (ICSPTM) 27.3 ICSPTM programming allows customers to manufacture circuit boards with unprogrammed devices. Programming can be done after the assembly process allowing the device to be programmed with the most recent firmware or a custom firmware. Five pins are needed for ICSPTM programming: * ICSPCLK * ICSPDAT * MCLR/VPP * VDD * VSS Connection to a target device is typically done through an ICSPTM header. A commonly found connector on development tools is the RJ-11 in the 6P6C (6 pin, 6 connector) configuration. See Figure 27-1. FIGURE 27-1: VDD In Program/Verify mode the Program Memory, User IDs and the Configuration Words are programmed through serial communications. The ICSPDAT pin is a bidirectional I/O used for transferring the serial data and the ICSPCLK pin is the clock input. For more information on ICSPTM refer to the "PIC12(L)F1501/PIC16(L)F150X Memory Programming Specification" (DS41573). 27.1 The Low-Voltage Programming Entry mode allows the PIC Flash MCUs devices to be programmed using VDD only, without high voltage. When the LVP bit of Configuration Words is set to `1', the low-voltage ICSP programming entry is enabled. To disable the Low-Voltage ICSP mode, the LVP bit must be programmed to `0'. ICSPDAT NC 2 4 6 ICSPCLK 1 3 5 Target VSS PC Board Bottom Side Pin Description* 1 = VPP/MCLR High-Voltage Programming Entry Mode Low-Voltage Programming Entry Mode ICD RJ-11 STYLE CONNECTOR INTERFACE VPP/MCLR 2 = VDD Target 3 = VSS (ground) 4 = ICSPDAT The device is placed into High-Voltage Programming Entry mode by holding the ICSPCLK and ICSPDAT pins low then raising the voltage on MCLR/VPP to VIHH. 27.2 Common Programming Interfaces 5 = ICSPCLK 6 = No Connect Another connector often found in use with the PICkitTM programmers is a standard 6-pin header with 0.1 inch spacing. Refer to Figure 27-2. Entry into the Low-Voltage Programming Entry mode requires the following steps: 1. 2. MCLR is brought to VIL. A 32-bit key sequence is presented on ICSPDAT, while clocking ICSPCLK. Once the key sequence is complete, MCLR must be held at VIL for as long as Program/Verify mode is to be maintained. If low-voltage programming is enabled (LVP = 1), the MCLR Reset function is automatically enabled and cannot be disabled. See Section 6.4 "MCLR" for more information. The LVP bit can only be reprogrammed to `0' by using the High-Voltage Programming mode. 2011 Microchip Technology Inc. Preliminary DS41609A-page 313 PIC16(L)F1508/9 FIGURE 27-2: PICkitTM PROGRAMMER STYLE CONNECTOR INTERFACE Pin 1 Indicator Pin Description* 1 = VPP/MCLR 1 2 3 4 5 6 2 = VDD Target 3 = VSS (ground) 4 = ICSPDAT 5 = ICSPCLK 6 = No Connect * The 6-pin header (0.100" spacing) accepts 0.025" square pins. For additional interface recommendations, refer to your specific device programmer manual prior to PCB design. It is recommended that isolation devices be used to separate the programming pins from other circuitry. The type of isolation is highly dependent on the specific application and may include devices such as resistors, diodes, or even jumpers. See Figure 27-3 for more information. FIGURE 27-3: TYPICAL CONNECTION FOR ICSPTM PROGRAMMING External Programming Signals Device to be Programmed VDD VDD VDD VPP MCLR/VPP VSS VSS Data ICSPDAT Clock ICSPCLK * * * To Normal Connections * Isolation devices (as required). DS41609A-page 314 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 28.0 INSTRUCTION SET SUMMARY 28.1 Read-Modify-Write Operations * Byte Oriented * Bit Oriented * Literal and Control Any instruction that specifies a file register as part of the instruction performs a Read-Modify-Write (R-M-W) operation. The register is read, the data is modified, and the result is stored according to either the instruction, or the destination designator `d'. A read operation is performed on a register even if the instruction writes to that register. The literal and control category contains the most varied instruction word format. TABLE 28-1: Each PIC16 instruction is a 14-bit word containing the operation code (opcode) and all required operands. The op codes are broken into three broad categories. Table 28-3 lists the instructions recognized by the MPASMTM assembler. All instructions are executed within a single instruction cycle, with the following exceptions, which may take two or three cycles: * Subroutine takes two cycles (CALL, CALLW) * Returns from interrupts or subroutines take two cycles (RETURN, RETLW, RETFIE) * Program branching takes two cycles (GOTO, BRA, BRW, BTFSS, BTFSC, DECFSZ, INCSFZ) * One additional instruction cycle will be used when any instruction references an indirect file register and the file select register is pointing to program memory. One instruction cycle consists of 4 oscillator cycles; for an oscillator frequency of 4 MHz, this gives a nominal instruction execution rate of 1 MHz. All instruction examples use the format `0xhh' to represent a hexadecimal number, where `h' signifies a hexadecimal digit. OPCODE FIELD DESCRIPTIONS Field f Description Register file address (0x00 to 0x7F) W Working register (accumulator) b Bit address within an 8-bit file register k Literal field, constant data or label x Don't care location (= 0 or 1). The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. d Destination select; d = 0: store result in W, d = 1: store result in file register f. Default is d = 1. n FSR or INDF number. (0-1) mm Pre-post increment-decrement mode selection TABLE 28-2: ABBREVIATION DESCRIPTIONS Field PC Program Counter TO Time-out bit C DC Z PD 2011 Microchip Technology Inc. Description Preliminary Carry bit Digit carry bit Zero bit Power-down bit DS41609A-page 315 PIC16(L)F1508/9 FIGURE 28-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 13 8 7 6 OPCODE d f (FILE #) 0 d = 0 for destination W d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 7 6 OPCODE b (BIT #) f (FILE #) 0 b = 3-bit bit address f = 7-bit file register address Literal and control operations General 13 OPCODE 8 7 0 k (literal) k = 8-bit immediate value CALL and GOTO instructions only 13 11 10 OPCODE 0 k (literal) k = 11-bit immediate value MOVLP instruction only 13 OPCODE 7 6 0 k (literal) k = 7-bit immediate value MOVLB instruction only 13 OPCODE 5 4 0 k (literal) k = 5-bit immediate value BRA instruction only 13 OPCODE 9 8 0 k (literal) k = 9-bit immediate value FSR Offset instructions 13 OPCODE 7 6 n 5 0 k (literal) n = appropriate FSR k = 6-bit immediate value FSR Increment instructions 13 OPCODE 3 2 1 0 n m (mode) n = appropriate FSR m = 2-bit mode value OPCODE only 13 0 OPCODE DS41609A-page 316 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 TABLE 28-3: PIC16(L)F1508/9 ENHANCED INSTRUCTION SET Mnemonic, Operands Description Cycles 14-Bit Opcode MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ADDWFC ANDWF ASRF LSLF LSRF CLRF CLRW COMF DECF INCF IORWF MOVF MOVWF RLF RRF SUBWF SUBWFB SWAPF XORWF f, d f, d f, d f, d f, d f, d f - f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d f, d Add W and f Add with Carry W and f AND W with f Arithmetic Right Shift Logical Left Shift Logical Right Shift Clear f Clear W Complement f Decrement f Increment f Inclusive OR W with f Move f Move W to f Rotate Left f through Carry Rotate Right f through Carry Subtract W from f Subtract with Borrow W from f Swap nibbles in f Exclusive OR W with f 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 00 11 00 11 11 11 00 00 00 00 00 00 00 00 00 00 00 11 00 00 0111 1101 0101 0111 0101 0110 0001 0001 1001 0011 1010 0100 1000 0000 1101 1100 0010 1011 1110 0110 dfff dfff dfff dfff dfff dfff lfff 0000 dfff dfff dfff dfff dfff 1fff dfff dfff dfff dfff dfff dfff ffff ffff ffff ffff ffff ffff ffff 00xx ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff C, DC, Z C, DC, Z Z C, Z C, Z C, Z Z Z Z Z Z Z Z C C C, DC, Z C, DC, Z Z 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 BYTE ORIENTED SKIP OPERATIONS DECFSZ INCFSZ f, d f, d Decrement f, Skip if 0 Increment f, Skip if 0 BCF BSF f, b f, b Bit Clear f Bit Set f 1(2) 1(2) 00 00 1, 2 1, 2 1011 dfff ffff 1111 dfff ffff BIT-ORIENTED FILE REGISTER OPERATIONS 1 1 00bb bfff ffff 01bb bfff ffff 2 2 01 01 10bb bfff ffff 11bb bfff ffff 1, 2 1, 2 11 11 11 00 11 11 11 11 1110 1001 1000 0000 0001 0000 1100 1010 01 01 BIT-ORIENTED SKIP OPERATIONS BTFSC BTFSS f, b f, b Bit Test f, Skip if Clear Bit Test f, Skip if Set ADDLW ANDLW IORLW MOVLB MOVLP MOVLW SUBLW XORLW k k k k k k k k Add literal and W AND literal with W Inclusive OR literal with W Move literal to BSR Move literal to PCLATH Move literal to W Subtract W from literal Exclusive OR literal with W 1 (2) 1 (2) LITERAL OPERATIONS 1 1 1 1 1 1 1 1 kkkk kkkk kkkk 001k 1kkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk C, DC, Z Z Z C, DC, Z Z Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require one additional instruction cycle. 2011 Microchip Technology Inc. Preliminary DS41609A-page 317 PIC16(L)F1508/9 TABLE 28-3: PIC16(L)F1508/9 ENHANCED INSTRUCTION SET (CONTINUED) Mnemonic, Operands Description Cycles 14-Bit Opcode MSb LSb Status Affected Notes CONTROL OPERATIONS 2 2 2 2 2 2 2 2 BRA BRW CALL CALLW GOTO RETFIE RETLW RETURN k - k - k k k - Relative Branch Relative Branch with W Call Subroutine Call Subroutine with W Go to address Return from interrupt Return with literal in W Return from Subroutine CLRWDT NOP OPTION RESET SLEEP TRIS - - - - - f Clear Watchdog Timer No Operation Load OPTION_REG register with W Software device Reset Go into Standby mode Load TRIS register with W ADDFSR MOVIW n, k n mm MOVWI k[n] n mm Add Literal k to FSRn Move Indirect FSRn to W with pre/post inc/dec modifier, mm Move INDFn to W, Indexed Indirect. Move W to Indirect FSRn with pre/post inc/dec modifier, mm Move W to INDFn, Indexed Indirect. 11 00 10 00 10 00 11 00 001k 0000 0kkk 0000 1kkk 0000 0100 0000 kkkk 0000 kkkk 0000 kkkk 0000 kkkk 0000 kkkk 1011 kkkk 1010 kkkk 1001 kkkk 1000 00 00 00 00 00 00 0000 0000 0000 0000 0000 0000 0110 0000 0110 0000 0110 0110 0100 TO, PD 0000 0010 0001 0011 TO, PD 0fff INHERENT OPERATIONS 1 1 1 1 1 1 C-COMPILER OPTIMIZED k[n] 1 1 11 00 1 1 11 00 0001 0nkk kkkk 0000 0001 0nmm Z kkkk 1111 0nkk 1nmm Z 0000 0001 kkkk 1 11 1111 1nkk 2, 3 2 2, 3 2 Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require one additional instruction cycle. 3: See Table in the MOVIW and MOVWI instruction descriptions. DS41609A-page 318 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 28.2 Instruction Descriptions ADDFSR Add Literal to FSRn ANDLW AND literal with W Syntax: [ label ] ADDFSR FSRn, k Syntax: [ label ] ANDLW Operands: -32 k 31 n [ 0, 1] Operands: 0 k 255 Operation: FSR(n) + k FSR(n) Status Affected: None Description: The signed 6-bit literal `k' is added to the contents of the FSRnH:FSRnL register pair. k Operation: (W) .AND. (k) (W) Status Affected: Z Description: The contents of W register are AND'ed with the eight-bit literal `k'. The result is placed in the W register. FSRn is limited to the range 0000h FFFFh. Moving beyond these bounds will cause the FSR to wrap around. ADDLW Add literal and W ANDWF AND W with f Syntax: [ label ] ADDLW Syntax: [ label ] ANDWF Operands: 0 f 127 d 0,1 Operation: (W) .AND. (f) (destination) Status Affected: Z Description: AND the W register with register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'. ASRF Arithmetic Right Shift k Operands: 0 k 255 Operation: (W) + k (W) Status Affected: C, DC, Z Description: The contents of the W register are added to the eight-bit literal `k' and the result is placed in the W register. f,d ADDWF Add W and f Syntax: [ label ] ADDWF Syntax: [ label ] ASRF Operands: 0 f 127 d 0,1 Operands: 0 f 127 d [0,1] Operation: (W) + (f) (destination) Operation: (f<7>) dest<7> (f<7:1>) dest<6:0>, (f<0>) C, f,d Status Affected: C, DC, Z Description: Add the contents of the W register with register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'. ADDWFC ADD W and CARRY bit to f Syntax: [ label ] ADDWFC Operands: 0 f 127 d [0,1] Status Affected: C, Z Description: The contents of register `f' are shifted one bit to the right through the Carry flag. The MSb remains unchanged. If `d' is `0', the result is placed in W. If `d' is `1', the result is stored back in register `f'. register f C f {,d} Operation: (W) + (f) + (C) dest Status Affected: C, DC, Z Description: Add W, the Carry flag and data memory location `f'. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed in data memory location `f'. 2011 Microchip Technology Inc. f {,d} Preliminary DS41609A-page 319 PIC16(L)F1508/9 BCF Bit Clear f Syntax: [ label ] BCF f,b BTFSC Bit Test f, Skip if Clear Syntax: [ label ] BTFSC f,b 0 f 127 0b7 Operands: 0 f 127 0b7 Operands: Operation: 0 (f<b>) Operation: skip if (f<b>) = 0 Status Affected: None Status Affected: None Description: Bit `b' in register `f' is cleared. Description: If bit `b' in register `f' is `1', the next instruction is executed. If bit `b', in register `f', is `0', the next instruction is discarded, and a NOP is executed instead, making this a 2-cycle instruction. BRA Relative Branch BTFSS Bit Test f, Skip if Set Syntax: [ label ] BRA label [ label ] BRA $+k Syntax: [ label ] BTFSS f,b Operands: Operands: -256 label - PC + 1 255 -256 k 255 0 f 127 0b<7 Operation: skip if (f<b>) = 1 Operation: (PC) + 1 + k PC Status Affected: None Status Affected: None Description: Description: Add the signed 9-bit literal `k' to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 1 + k. This instruction is a two-cycle instruction. This branch has a limited range. If bit `b' in register `f' is `0', the next instruction is executed. If bit `b' is `1', then the next instruction is discarded and a NOP is executed instead, making this a 2-cycle instruction. BRW Relative Branch with W Syntax: [ label ] BRW Operands: None Operation: (PC) + (W) PC Status Affected: None Description: Add the contents of W (unsigned) to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 1 + (W). This instruction is a two-cycle instruction. BSF Bit Set f Syntax: [ label ] BSF Operands: 0 f 127 0b7 Operation: 1 (f<b>) Status Affected: None Description: Bit `b' in register `f' is set. DS41609A-page 320 f,b Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 CALL Call Subroutine CLRWDT Clear Watchdog Timer Syntax: [ label ] CALL k Syntax: [ label ] CLRWDT Operands: 0 k 2047 Operands: None Operation: (PC)+ 1 TOS, k PC<10:0>, (PCLATH<4:3>) PC<12:11> Operation: Status Affected: None 00h WDT 0 WDT prescaler, 1 TO 1 PD Description: Call Subroutine. First, return address (PC + 1) is pushed onto the stack. The eleven-bit immediate address is loaded into PC bits <10:0>. The upper bits of the PC are loaded from PCLATH. CALL is a two-cycle instruction. Status Affected: TO, PD Description: CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler of the WDT. Status bits TO and PD are set. CALLW Subroutine Call With W COMF Complement f Syntax: [ label ] CALLW Syntax: [ label ] COMF Operands: None Operands: Operation: (PC) +1 TOS, (W) PC<7:0>, (PCLATH<6:0>) PC<14:8> 0 f 127 d [0,1] Operation: (f) (destination) Status Affected: Z Description: The contents of register `f' are complemented. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f'. DECF Decrement f Syntax: [ label ] DECF f,d Status Affected: None Description: Subroutine call with W. First, the return address (PC + 1) is pushed onto the return stack. Then, the contents of W is loaded into PC<7:0>, and the contents of PCLATH into PC<14:8>. CALLW is a two-cycle instruction. CLRF Clear f Syntax: [ label ] CLRF f f,d Operands: 0 f 127 Operands: Operation: 00h (f) 1Z 0 f 127 d [0,1] Operation: (f) - 1 (destination) Status Affected: Z Status Affected: Z Description: The contents of register `f' are cleared and the Z bit is set. Description: Decrement register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'. CLRW Clear W Syntax: [ label ] CLRW Operands: None Operation: 00h (W) 1Z Status Affected: Z Description: W register is cleared. Zero bit (Z) is set. 2011 Microchip Technology Inc. Preliminary DS41609A-page 321 PIC16(L)F1508/9 DECFSZ Decrement f, Skip if 0 INCFSZ Increment f, Skip if 0 Syntax: [ label ] DECFSZ f,d Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 f 127 d [0,1] Operation: (f) - 1 (destination); skip if result = 0 Operation: (f) + 1 (destination), skip if result = 0 Status Affected: None Status Affected: None Description: The contents of register `f' are decremented. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'. If the result is `1', the next instruction is executed. If the result is `0', then a NOP is executed instead, making it a 2-cycle instruction. Description: The contents of register `f' are incremented. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'. If the result is `1', the next instruction is executed. If the result is `0', a NOP is executed instead, making it a 2-cycle instruction. GOTO Unconditional Branch IORLW Inclusive OR literal with W Syntax: [ label ] Syntax: [ label ] GOTO k INCFSZ f,d IORLW k Operands: 0 k 2047 Operands: 0 k 255 Operation: k PC<10:0> PCLATH<4:3> PC<12:11> Operation: (W) .OR. k (W) Status Affected: Z Status Affected: None Description: Description: GOTO is an unconditional branch. The eleven-bit immediate value is loaded into PC bits <10:0>. The upper bits of PC are loaded from PCLATH<4:3>. GOTO is a two-cycle instruction. The contents of the W register are OR'ed with the eight-bit literal `k'. The result is placed in the W register. INCF Increment f IORWF Inclusive OR W with f Syntax: [ label ] Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 f 127 d [0,1] Operation: (f) + 1 (destination) Operation: (W) .OR. (f) (destination) Status Affected: Z Status Affected: Z Description: The contents of register `f' are incremented. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'. Description: Inclusive OR the W register with register `f'. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'. DS41609A-page 322 INCF f,d Preliminary IORWF f,d 2011 Microchip Technology Inc. PIC16(L)F1508/9 LSLF Logical Left Shift f {,d} MOVF Move f Syntax: [ label ] LSLF Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 f 127 d [0,1] Operation: (f<7>) C (f<6:0>) dest<7:1> 0 dest<0> Operation: (f) (dest) Status Affected: C, Z Description: The contents of register `f' are shifted one bit to the left through the Carry flag. A `0' is shifted into the LSb. If `d' is `0', the result is placed in W. If `d' is `1', the result is stored back in register `f'. C register f 0 Status Affected: Z Description: The contents of register f is moved to a destination dependent upon the status of d. If d = 0, destination is W register. If d = 1, the destination is file register f itself. d = 1 is useful to test a file register since status flag Z is affected. Words: 1 Cycles: 1 Example: Logical Right Shift Syntax: [ label ] LSRF Operands: 0 f 127 d [0,1] Operation: 0 dest<7> (f<7:1>) dest<6:0>, (f<0>) C, Status Affected: C, Z Description: The contents of register `f' are shifted one bit to the right through the Carry flag. A `0' is shifted into the MSb. If `d' is `0', the result is placed in W. If `d' is `1', the result is stored back in register `f'. 2011 Microchip Technology Inc. f {,d} register f MOVF FSR, 0 After Instruction W = value in FSR register Z = 1 LSRF 0 MOVF f,d C Preliminary DS41609A-page 323 PIC16(L)F1508/9 MOVIW Move INDFn to W Syntax: [ label ] MOVIW ++FSRn [ label ] MOVIW --FSRn [ label ] MOVIW FSRn++ [ label ] MOVIW FSRn-[ label ] MOVIW k[FSRn] Operands: n [0,1] mm [00,01, 10, 11] -32 k 31 Operation: INDFn W Effective address is determined by * FSR + 1 (preincrement) * FSR - 1 (predecrement) * FSR + k (relative offset) After the Move, the FSR value will be either: * FSR + 1 (all increments) * FSR - 1 (all decrements) * Unchanged Status Affected: MOVLP Move literal to PCLATH Syntax: [ label ] MOVLP k Operands: 0 k 127 Operation: k PCLATH Status Affected: None Description: The seven-bit literal `k' is loaded into the PCLATH register. MOVLW Move literal to W Syntax: [ label ] Operands: 0 k 255 Operation: k (W) Status Affected: None Description: The eight-bit literal `k' is loaded into W register. The "don't cares" will assemble as `0's. Words: 1 1 Z Mode Syntax mm Cycles: Preincrement ++FSRn 00 Example: Predecrement --FSRn 01 Postincrement FSRn++ 10 Postdecrement FSRn-- 11 Description: Note: The INDFn registers are not physical registers. Any instruction that accesses an INDFn register actually accesses the register at the address specified by the FSRn. Syntax: [ label ] MOVLB k Operands: 0 k 15 Operation: k BSR Status Affected: None Description: The five-bit literal `k' is loaded into the Bank Select Register (BSR). DS41609A-page 324 0x5A MOVWF Move W to f Syntax: [ label ] MOVWF Operands: 0 f 127 Operation: (W) (f) 0x5A f Status Affected: None Description: Move data from W register to register `f'. Words: 1 Cycles: 1 Example: FSRn is limited to the range 0000h FFFFh. Incrementing/decrementing it beyond these bounds will cause it to wrap-around. Move literal to BSR MOVLW After Instruction W = This instruction is used to move data between W and one of the indirect registers (INDFn). Before/after this move, the pointer (FSRn) is updated by pre/post incrementing/decrementing it. MOVLB MOVLW k Preliminary MOVWF OPTION_REG Before Instruction OPTION_REG = W = After Instruction OPTION_REG = W = 0xFF 0x4F 0x4F 0x4F 2011 Microchip Technology Inc. PIC16(L)F1508/9 MOVWI Move W to INDFn Syntax: [ label ] MOVWI ++FSRn [ label ] MOVWI --FSRn [ label ] MOVWI FSRn++ [ label ] MOVWI FSRn-[ label ] MOVWI k[FSRn] Operands: Operation: Status Affected: n [0,1] mm [00,01, 10, 11] -32 k 31 W INDFn Effective address is determined by * FSR + 1 (preincrement) * FSR - 1 (predecrement) * FSR + k (relative offset) After the Move, the FSR value will be either: * FSR + 1 (all increments) * FSR - 1 (all decrements) Unchanged None Mode Syntax mm Preincrement ++FSRn 00 Predecrement --FSRn 01 Postincrement FSRn++ 10 Postdecrement FSRn-- 11 Description: This instruction is used to move data between W and one of the indirect registers (INDFn). Before/after this move, the pointer (FSRn) is updated by pre/post incrementing/decrementing it. Note: The INDFn registers are not physical registers. Any instruction that accesses an INDFn register actually accesses the register at the address specified by the FSRn. NOP No Operation Syntax: [ label ] Operands: None Operation: No operation Status Affected: None Description: No operation. Words: 1 Cycles: 1 Example: NOP NOP OPTION Load OPTION_REG Register with W Syntax: [ label ] OPTION Operands: None Operation: (W) OPTION_REG Status Affected: None Description: Move data from W register to OPTION_REG register. RESET Software Reset Syntax: [ label ] RESET Operands: None Operation: Execute a device Reset. Resets the nRI flag of the PCON register. Status Affected: None Description: This instruction provides a way to execute a hardware Reset by software. FSRn is limited to the range 0000h FFFFh. Incrementing/decrementing it beyond these bounds will cause it to wrap-around. The increment/decrement operation on FSRn WILL NOT affect any Status bits. 2011 Microchip Technology Inc. Preliminary DS41609A-page 325 PIC16(L)F1508/9 RETFIE Return from Interrupt Syntax: [ label ] RETURN RETFIE Return from Subroutine Syntax: [ label ] None RETURN Operands: None Operands: Operation: TOS PC, 1 GIE Operation: TOS PC Status Affected: None Status Affected: None Description: Description: Return from Interrupt. Stack is POPed and Top-of-Stack (TOS) is loaded in the PC. Interrupts are enabled by setting Global Interrupt Enable bit, GIE (INTCON<7>). This is a two-cycle instruction. Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a two-cycle instruction. Words: 1 Cycles: 2 Example: RETFIE After Interrupt PC = GIE = TOS 1 RETLW Return with literal in W Syntax: [ label ] Operands: 0 k 255 Operation: k (W); TOS PC Status Affected: None Description: The W register is loaded with the eight bit literal `k'. The program counter is loaded from the top of the stack (the return address). This is a two-cycle instruction. Words: 1 Cycles: 2 Example: TABLE RETLW k Rotate Left f through Carry Syntax: [ label ] Operands: 0 f 127 d [ 0, 1] Operation: See description below Status Affected: C Description: The contents of register `f' are rotated one bit to the left through the Carry flag. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is stored back in register `f'. RLF C CALL TABLE;W contains table ;offset value * ;W now has table value * * ADDWF PC ;W = offset RETLW k1 ;Begin table RETLW k2 ; * * * RETLW kn ; End of table Before Instruction W = After Instruction W = DS41609A-page 326 RLF Words: 1 Cycles: 1 Example: RLF f,d Register f REG1,0 Before Instruction REG1 C After Instruction REG1 W C = = 1110 0110 0 = = = 1110 0110 1100 1100 1 0x07 value of k8 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 SUBLW Subtract W from literal Syntax: [ label ] RRF Rotate Right f through Carry Syntax: [ label ] Operands: 0 f 127 d [0,1] Operation: See description below Status Affected: C, DC, Z Status Affected: C Description: Description: The contents of register `f' are rotated one bit to the right through the Carry flag. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'. The W register is subtracted (2's complement method) from the eight-bit literal `k'. The result is placed in the W register. RRF f,d C SUBLW k Operands: 0 k 255 Operation: k - (W) W) Register f C=0 Wk C=1 Wk DC = 0 W<3:0> k<3:0> DC = 1 W<3:0> k<3:0> SLEEP Enter Sleep mode SUBWF Subtract W from f Syntax: [ label ] Syntax: [ label ] Operands: 0 f 127 d [0,1] Operation: (f) - (W) destination) Status Affected: C, DC, Z Description: Subtract (2's complement method) W register from register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f. SLEEP Operands: None Operation: 00h WDT, 0 WDT prescaler, 1 TO, 0 PD Status Affected: TO, PD Description: The power-down Status bit, PD is cleared. Time-out Status bit, TO is set. Watchdog Timer and its prescaler are cleared. The processor is put into Sleep mode with the oscillator stopped. 2011 Microchip Technology Inc. SUBWF f,d C=0 Wf C=1 Wf DC = 0 W<3:0> f<3:0> DC = 1 W<3:0> f<3:0> SUBWFB Subtract W from f with Borrow Syntax: SUBWFB Operands: 0 f 127 d [0,1] Operation: (f) - (W) - (B) dest f {,d} Status Affected: C, DC, Z Description: Subtract W and the BORROW flag (CARRY) from register `f' (2's complement method). If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f'. Preliminary DS41609A-page 327 PIC16(L)F1508/9 SWAPF Swap Nibbles in f XORLW Exclusive OR literal with W Syntax: [ label ] Syntax: [ label ] Operands: 0 f 127 d [0,1] Operation: SWAPF f,d (f<3:0>) (destination<7:4>), (f<7:4>) (destination<3:0>) XORLW k Operands: 0 k 255 Operation: (W) .XOR. k W) Status Affected: Z Description: The contents of the W register are XOR'ed with the eight-bit literal `k'. The result is placed in the W register. Status Affected: None Description: The upper and lower nibbles of register `f' are exchanged. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed in register `f'. TRIS Load TRIS Register with W XORWF Exclusive OR W with f Syntax: [ label ] TRIS f Syntax: [ label ] Operands: 5f7 Operands: Operation: (W) TRIS register `f' 0 f 127 d [0,1] Status Affected: None Operation: (W) .XOR. (f) destination) Status Affected: Z Description: Exclusive OR the contents of the W register with register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'. Description: DS41609A-page 328 Move data from W register to TRIS register. When `f' = 5, TRISA is loaded. When `f' = 6, TRISB is loaded. When `f' = 7, TRISC is loaded. Preliminary XORWF f,d 2011 Microchip Technology Inc. PIC16(L)F1508/9 29.0 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings() Ambient temperature under bias....................................................................................................... -40C to +125C Storage temperature ........................................................................................................................ -65C to +150C Voltage on VDD with respect to VSS, PIC16F1508/9 .......................................................................... -0.3V to +6.5V Voltage on VDD with respect to VSS, PIC16LF1508/9 ........................................................................ -0.3V to +4.0V Voltage on MCLR with respect to Vss ................................................................................................. -0.3V to +9.0V Voltage on all other pins with respect to VSS ........................................................................... -0.3V to (VDD + 0.3V) Total power dissipation(1) ............................................................................................................................... 800 mW Maximum current out of VSS pin, -40C TA +85C for industrial............................................................... 396 mA Maximum current out of VSS pin, -40C TA +125C for extended ............................................................ 114 mA Maximum current into VDD pin, -40C TA +85C for industrial.................................................................. 292 mA Maximum current into VDD pin, -40C TA +125C for extended ............................................................... 107 mA Clamp current, IK (VPIN < 0 or VPIN > VDD) 20 mA Maximum output current sunk by any I/O pin.................................................................................................... 25 mA Maximum output current sourced by any I/O pin .............................................................................................. 25 mA Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD - IOH} + {(VDD - VOH) x IOH} + (VOl x IOL). NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for extended periods may affect device reliability. 2011 Microchip Technology Inc. Preliminary DS41609A-page 329 PIC16(L)F1508/9 PIC16F1508/9 VOLTAGE FREQUENCY GRAPH, -40C TA +125C FIGURE 29-1: VDD (V) 5.5 2.5 2.3 4 0 10 16 20 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Refer to Table 29-1 for each Oscillator mode's supported frequencies. PIC16LF1508/9 VOLTAGE FREQUENCY GRAPH, -40C TA +125C VDD (V) FIGURE 29-2: 3.6 2.5 1.8 0 4 10 16 20 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Refer to Table 29-1 for each Oscillator mode's supported frequencies. DS41609A-page 330 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 29.1 DC Characteristics: PIC16(L)F1508/9-I/E (Industrial, Extended) PIC16LF1508/9 Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended PIC16F1508/9 Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Param. No. D001 Sym. VDD Characteristic VDR VPOR* VPORR* Units PIC16LF1508/9 1.8 2.5 -- -- 3.6 3.6 V V FOSC 16 MHz FOSC 20 MHz PIC16F1508/9 2.3 2.5 -- -- 5.5 5.5 V V FOSC 16 MHz FOSC 20 MHz PIC16LF1508/9 1.5 -- -- V Device in Sleep mode PIC16F1508/9 1.7 -- -- V Device in Sleep mode PIC16LF1508/9 -- 1.6 -- V PIC16F1508/9 -- 1.7 -- V V Power-on Reset Rearm Voltage PIC16LF1508/9 -- 0.8 -- PIC16F1508/9 -- 1.65 -- V Fixed Voltage Reference Voltage for ADC, Initial Accuracy -- -- -- -- -- -- 1 1 1 1 1 1 -- -- -- -- -- -- % D003C* TCVFVR Temperature Coefficient, Fixed Voltage Reference -- -130 -- ppm/C D003D* VFVR/ VIN Line Regulation, Fixed Voltage Reference -- 0.270 -- %/V D004* VDD Rise Rate to ensure internal Power-on Reset signal 0.05 -- -- V/ms D002B D003 VADFVR SVDD Conditions Power-on Reset Release Voltage D002A D002B Max. RAM Data Retention Voltage(1) D002* D002A Typ Supply Voltage D001 D002* Min. 1.024V, VDD 2.5V, 85C (NOTE 2) 1.024V, VDD 2.5V, 125C (NOTE 2) 2.048V, VDD 2.5V, 85C 2.048V, VDD 2.5V, 125C 4.096V, VDD 4.75V, 85C 4.096V, VDD 4.75V, 125C See Section 6.1 "Power-on Reset (POR)" for details. * Note These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data. 2: For proper operation, the minimum value of the ADC positive voltage reference must be 1.8V or greater. When selecting the FVR or the VREF+ pin as the source of the ADC positive voltage reference, be aware that the voltage must be 1.8V or greater. 2011 Microchip Technology Inc. Preliminary DS41609A-page 331 PIC16(L)F1508/9 FIGURE 29-3: POR AND POR REARM WITH SLOW RISING VDD VDD VPOR VPORR VSS NPOR POR REARM VSS TVLOW(2) Note 1: 2: 3: DS41609A-page 332 TPOR(3) When NPOR is low, the device is held in Reset. TPOR 1 s typical. TVLOW 2.7 s typical. Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 29.2 DC Characteristics: PIC16(L)F1508/9-I/E (Industrial, Extended) PIC16LF1508/9 Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended PIC16F1508/9 Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Param No. Device Characteristics Conditions Min. Typ Max. Units -- 2 10 A 1.8 -- 4 12 A 3.0 -- 16 50 A 2.3 -- 16 55 A 3.0 -- 19 60 A 5.0 -- 40 110 A 1.8 -- 80 170 A 3.0 -- 110 200 A 2.3 -- 130 250 A 3.0 VDD Note Supply Current (IDD)(1, 2) D010 D010 D011 D011 D012 D012 D013 D013 D014 D014 D015 D015 -- 160 340 A 5.0 -- 120 290 A 1.8 -- 220 480 A 3.0 -- 230 300 A 2.3 -- 300 500 A 3.0 -- 350 700 A 5.0 -- 30 140 A 1.8 -- 50 230 A 3.0 -- 70 180 A 2.3 -- 85 240 A 3.0 -- 115 320 A 5.0 -- 100 250 A 2.3 -- 180 430 A 3.0 -- 160 275 A 2.3 -- 210 450 A 3.0 -- 240 500 A 5.0 -- 2.3 58 A 1.8 -- 4.0 300 A 3.0 -- 14 100 A 2.3 -- 15 280 A 3.0 -- 17 400 A 5.0 FOSC = 32 kHz LP Oscillator mode FOSC = 32 kHz LP Oscillator mode FOSC = 1 MHz XT Oscillator mode FOSC = 1 MHz XT Oscillator mode FOSC = 4 MHz XT Oscillator mode FOSC = 4 MHz XT Oscillator mode FOSC = 1 MHz EC Oscillator mode, Medium-power mode FOSC = 1 MHz EC Oscillator mode Medium-power mode FOSC = 4 MHz EC Oscillator mode, Medium-power mode FOSC = 4 MHz EC Oscillator mode Medium-power mode FOSC = 31 kHz LFINTOSC mode FOSC = 31 kHz LFINTOSC mode * These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The test conditions for all IDD measurements in active operation mode are: CLKIN = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended by the formula IR = VDD/2REXT (mA) with REXT in k. 2011 Microchip Technology Inc. Preliminary DS41609A-page 333 PIC16(L)F1508/9 29.2 DC Characteristics: PIC16(L)F1508/9-I/E (Industrial, Extended) (Continued) PIC16LF1508/9 Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended PIC16F1508/9 Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Param No. Device Characteristics D016 D016 D017* D017* Conditions Min. Typ Max. Units -- 220 400 A 1.8 -- 280 600 A 3.0 -- 280 400 A 2.3 -- 310 550 A 3.0 -- 360 750 A 5.0 -- 380 700 A 1.8 -- 560 1100 A 3.0 -- 490 850 A 2.3 -- 600 1150 A 3.0 VDD Note FOSC = 500 kHz HFINTOSC mode FOSC = 500 kHz HFINTOSC mode FOSC = 8 MHz HFINTOSC mode FOSC = 8 MHz HFINTOSC mode -- 690 1350 A 5.0 -- 520 1200 A 1.8 -- 810 1750 A 3.0 -- 680 1200 A 2.3 -- 850 1800 A 3.0 -- 960 2000 A 5.0 D019A -- 750 2100 A 3.0 FOSC = 20 MHz ECH mode D019A -- 790 2100 A 3.0 -- 810 2400 A 5.0 FOSC = 20 MHz ECH mode D019B -- 6 15 A 1.8 FOSC = 32 kHz ECL mode -- 8 20 A 3.0 -- 14 43 A 2.3 -- 16 55 A 3.0 -- 18 57 A 5.0 -- 15 40 A 1.8 -- 20 60 A 3.0 -- 32 60 A 2.3 -- 41 90 A 3.0 D018 D018 D019B D019C D019C D020 D020 -- 47 100 A 5.0 -- 150 350 A 1.8 -- 280 680 A 3.0 -- 230 350 A 2.3 -- 310 680 A 3.0 -- 370 830 A 5.0 FOSC = 16 MHz HFINTOSC mode FOSC = 16 MHz HFINTOSC mode FOSC = 32 kHz ECL mode FOSC = 500 kHz ECL mode FOSC = 500 kHz ECL mode FOSC = 4 MHz EXTRC mode (Note 3) FOSC = 4 MHz EXTRC mode (Note 3) * These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The test conditions for all IDD measurements in active operation mode are: CLKIN = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended by the formula IR = VDD/2REXT (mA) with REXT in k. DS41609A-page 334 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 29.2 DC Characteristics: PIC16(L)F1508/9-I/E (Industrial, Extended) (Continued) PIC16LF1508/9 Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended PIC16F1508/9 Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Param No. Device Characteristics Conditions Min. Typ Max. Units D021 -- 1000 2100 A 3.0 FOSC = 20 MHz HS Oscillator mode D021 -- 1350 2100 A 3.0 FOSC = 20 MHz HS Oscillator mode -- 1700 2400 A 5.0 VDD Note * These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The test conditions for all IDD measurements in active operation mode are: CLKIN = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended by the formula IR = VDD/2REXT (mA) with REXT in k. 2011 Microchip Technology Inc. Preliminary DS41609A-page 335 PIC16(L)F1508/9 29.3 DC Characteristics: PIC16(L)F1508/9-I/E (Power-Down) PIC16LF1508/9 Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended PIC16F1508/9 Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Param No. Device Characteristics Power-down Current D022 D022 D022A D023 D023 D023A D023A Min. Typ Max. +85C Max. +125C Units -- 0.025 1.0 7.0 -- 0.035 2.0 -- 0.20 -- 0.25 -- -- Conditions VDD Note A 1.8 9.0 A 3.0 Base Current: WDT, BOR, FVR, and SOSC disabled, all Peripherals inactive 2.0 10 A 2.3 4.0 12 A 3.0 0.30 12 15 A 5.0 10 17 18 A 2.3 -- 11 22 24 A 3.0 -- 12 25 30 A 5.0 -- 0.29 1.5 7 A 1.8 -- 0.39 2.0 9 A 3.0 -- 10.5 38 44 A 2.3 -- 11.3 43 48 A 3.0 -- 12.5 46 50 A 5.0 -- 14 44 50 A 1.8 -- 23 48 54 A 3.0 -- 23 62 65 A 2.3 -- 30 72 75 A 3.0 5.0 (IPD)(2) WDT, BOR, FVR, and SOSC disabled, all Peripherals inactive (VREGPM = 1; Low-Power mode) Base Current: WDT, BOR, FVR and SOSC disabled, all peripheral inactive (VREGPM = 0; Normal Power mode) LPWDT Current (Note 1) LPWDT Current (Note 1) FVR current (Note 1) FVR current (Note 1) -- 34 115 120 A D024 -- 7 14 16 A 3.0 BOR Current (Note 1) D024 -- 15 47 50 A 3.0 BOR Current (Note 1) -- 17 55 66 A 5.0 D24A -- 0.1 4 14 A 3.0 LPBOR Current (Note 1) D24A -- 11 47 50 A 3.0 LPBOR Current (Note 1) -- 12 52 60 A 5.0 * Note 1: 2: 3: These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD. A/D oscillator source is FRC. DS41609A-page 336 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 29.3 DC Characteristics: PIC16(L)F1508/9-I/E (Power-Down) (Continued) PIC16LF1508/9 Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended PIC16F1508/9 Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Param No. Device Characteristics D025 D025 D026 D026 D026A* D026A* D027 D027 * Note 1: 2: 3: Min. Typ Max. +85C -- 0.6 -- 1.8 -- Conditions Max. +125C Units 3.5 8 A 1.8 4.0 10 A 3.0 11 39 45 A 2.3 -- 13 43 49 A 3.0 -- 19 46 65 A 5.0 -- .025 -- -- A 1.8 -- .035 -- -- A 3.0 -- 10 -- -- A 2.3 -- 11 -- -- A 3.0 VDD -- 12 -- -- A 5.0 -- 250 -- -- A 1.8 -- 250 -- -- A 3.0 -- 280 -- -- A 2.3 -- 280 -- -- A 3.0 -- 280 -- -- A 5.0 -- 7 25 55 A 1.8 -- 8 40 65 A 3.0 -- 17 50 65 A 2.3 -- 18 55 70 A 3.0 -- 19 60 75 A 5.0 Note SOSC Current (Note 1) SOSC Current (Note 1) A/D Current (Note 1, Note 3), no conversion in progress A/D Current (Note 1, Note 3), no conversion in progress A/D Current (Note 1, Note 3), conversion in progress A/D Current (Note 1, Note 3), conversion in progress Comparator, Low-Power mode (Note 1) Comparator, Low-Power mode (Note 1) These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD. A/D oscillator source is FRC. 2011 Microchip Technology Inc. Preliminary DS41609A-page 337 PIC16(L)F1508/9 29.4 DC Characteristics: PIC16(L)F1508/9-I/E DC CHARACTERISTICS Param No. Sym. VIL Characteristic Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Min. Typ Max. Units Conditions Input Low Voltage I/O PORT: D030 with TTL buffer D030A D031 with Schmitt Trigger buffer D032 MCLR VIH -- -- 0.8 V 4.5V VDD 5.5V -- -- 0.15 VDD V 1.8V VDD 4.5V -- -- 0.2 VDD V 2.0V VDD 5.5V -- -- 0.2 VDD V Input High Voltage I/O ports: D040 with TTL buffer D040A D041 with Schmitt Trigger buffer D042 MCLR IIL 2.0 -- -- V 4.5V VDD 5.5V 0.25 VDD + 0.8 -- -- V 1.8V VDD 4.5V 2.0V VDD 5.5V 0.8 VDD -- -- V 0.8 VDD -- -- V nA Input Leakage Current(1) D060 I/O ports -- 5 125 5 1000 nA VSS VPIN VDD, Pin at highimpedance at 85C 125C D061 MCLR(2) -- 50 200 nA VSS VPIN VDD at 85C 25 25 100 140 200 300 A VDD = 3.3V, VPIN = VSS VDD = 5.0V, VPIN = VSS -- -- 0.6 V IOL = 8mA, VDD = 5V IOL = 6mA, VDD = 3.3V IOL = 1.8mA, VDD = 1.8V VDD - 0.7 -- -- V IOH = 3.5mA, VDD = 5V IOH = 3mA, VDD = 3.3V IOH = 1mA, VDD = 1.8V -- 50 pF IPUR Weak Pull-up Current D070* VOL D080 Output Low Voltage(3) I/O ports VOH D090 Output High Voltage(3) I/O ports Capacitive Loading Specs on Output Pins D101A* CIO All I/O pins -- * These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Negative current is defined as current sourced by the pin. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Including OSC2 in CLKOUT mode. DS41609A-page 338 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 29.5 Memory Programming Requirements Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C DC CHARACTERISTICS Param No. Sym. Characteristic Min. Typ Max. Units Conditions Program Memory Programming Specifications D110 VIHH Voltage on MCLR/VPP pin 8.0 -- 9.0 V D111 IDDP Supply Current during Programming -- -- 10 mA (Note 2) D112 VBE VDD for Bulk Erase 2.7 -- VDD max. V D113 VPEW VDD for Write or Row Erase VDD min. -- VDD max. V D114 IPPPGM Current on MCLR/VPP during Erase/ Write -- 1.0 -- mA D115 IDDPGM Current on VDD during Erase/Write -- 5.0 -- mA D121 EP Cell Endurance 10K -- -- E/W VDD min. -- VDD max. V -- 2 2.5 ms -- 40 -- Year Provided no other specifications are violated 100K -- -- E/W 0C to +60C lower byte, last 128 addresses Program Flash Memory D122 VPR VDD for Read D123 TIW Self-timed Write Cycle Time D124 TRETD Characteristic Retention D125 EHEFC High-Endurance Flash Cell -40C to +85C (Note 1) Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Self-write and Block Erase. 2: Required only if single-supply programming is disabled. 2011 Microchip Technology Inc. Preliminary DS41609A-page 339 PIC16(L)F1508/9 29.6 Thermal Considerations Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C Param No. TH01 TH02 Sym. Characteristic JA Thermal Resistance Junction to Ambient JC TH03 TJMAX TH04 PD TH05 Thermal Resistance Junction to Case Maximum Junction Temperature Power Dissipation PINTERNAL Internal Power Dissipation Typ. Units Conditions 62.2 C/W 20-pin PDIP package 75.0 C/W 20-pin SOIC package 89.3 C/W 20-pin SSOP package 43.0 C/W 20-pin QFN 4X4mm package 27.5 C/W 20-pin PDIP package 23.1 C/W 20-pin SOIC package 31.1 C/W 20-pin SSOP package 5.3 C/W 20-pin QFN 4X4mm package 150 C -- W PD = PINTERNAL + PI/O -- W PINTERNAL = IDD x VDD(1) TH06 PI/O I/O Power Dissipation -- W PI/O = (IOL * VOL) + (IOH * (VDD - VOH)) TH07 PDER Derated Power -- W PDER = PDMAX (TJ - TA)/JA(2) Note 1: IDD is current to run the chip alone without driving any load on the output pins. 2: TA = Ambient Temperature 3: TJ = Junction Temperature DS41609A-page 340 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 29.7 Timing Parameter Symbology The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings: pp cc CCP1 ck CLKOUT cs CS di SDIx do SDO dt Data in io I/O PORT mc MCLR Uppercase letters and their meanings: S F Fall H High I Invalid (High-impedance) L Low FIGURE 29-4: T Time osc rd rw sc ss t0 t1 wr CLKIN RD RD or WR SCKx SS T0CKI T1CKI WR P R V Z Period Rise Valid High-impedance LOAD CONDITIONS Load Condition Pin CL VSS Legend: CL = 50 pF for all pins 2011 Microchip Technology Inc. Preliminary DS41609A-page 341 PIC16(L)F1508/9 29.8 AC Characteristics: PIC16(L)F1508/9-I/E FIGURE 29-5: CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 CLKIN OS12 OS02 OS11 OS03 CLKOUT (CLKOUT Mode) Note 1: See Table 29-3. TABLE 29-1: CLOCK OSCILLATOR TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C Param No. OS01 Sym. FOSC Characteristic External CLKIN Frequency(1) Min. Typ Max. Units Conditions DC -- 0.5 MHz EC Oscillator mode (low) DC -- 4 MHz EC Oscillator mode (medium) EC Oscillator mode (high) DC -- 20 MHz OS02 TOSC External CLKIN Period(1) 31.25 -- ns EC mode OS03 TCY Instruction Cycle Time(1) 125 -- DC ns TCY = FOSC/4 * These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min" values with an external clock applied to CLKIN pin. When an external clock input is used, the "max" cycle time limit is "DC" (no clock) for all devices. TABLE 29-2: OSCILLATOR PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param No. Sym. Characteristic Freq. Tolerance Min. Typ Max. Units Conditions OS08 HFOSC Internal Calibrated HFINTOSC Frequency(1) 10% -- 16.0 -- MHz 0C TA +85C OS09 LFOSC Internal LFINTOSC Frequency -- -- 31 -- kHz -40C TA +125C OS10* TIOSC ST HFINTOSC Wake-up from Sleep Start-up Time -- -- 5 8 s * These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 F and 0.01 F values in parallel are recommended. DS41609A-page 342 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 FIGURE 29-6: CLKOUT AND I/O TIMING Cycle Write Fetch Read Execute Q4 Q1 Q2 Q3 FOSC OS12 OS11 OS20 OS21 CLKOUT OS19 OS18 OS16 OS13 OS17 I/O pin (Input) OS14 OS15 I/O pin (Output) New Value Old Value OS18, OS19 TABLE 29-3: CLKOUT AND I/O TIMING PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param No. OS11 OS12 Sym. TosH2ckL Characteristic Min. Typ Max. Units Conditions FOSC to CLKOUT (1) -- -- 70 ns VDD = 3.3-5.0V (1) -- -- 72 ns VDD = 3.3-5.0V TosH2ckH FOSC to CLKOUT valid(1) OS13 TckL2ioV CLKOUT to Port out OS14 OS15 OS16 TioV2ckH TosH2ioV TosH2ioI OS17 TioV2osH OS18* TioR Port input valid before CLKOUT(1) Fosc (Q1 cycle) to Port out valid Fosc (Q2 cycle) to Port input invalid (I/O in hold time) Port input valid to Fosc(Q2 cycle) (I/O in setup time) Port output rise time(2) OS19* TioF Port output fall time(2) -- -- 20 ns TOSC + 200 ns -- 50 -- 50 -- -- 70* -- ns ns ns 20 -- -- ns -- -- -- -- 25 25 15 40 28 15 -- -- 32 72 55 30 -- -- ns OS20* Tinp OS21* Tioc INT pin input high or low time Interrupt-on-change new input level time * These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. Note 1: Measurements are taken in EC mode where CLKOUT output is 4 x TOSC. 2011 Microchip Technology Inc. Preliminary ns VDD = 3.3-5.0V VDD = 3.3-5.0V VDD = 2.0V VDD = 5.0V VDD = 2.0V VDD = 5.0V ns ns DS41609A-page 343 PIC16(L)F1508/9 FIGURE 29-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out Internal Reset(1) Watchdog Timer Reset(1) 31 34 34 I/O pins Note 1: Asserted low. FIGURE 29-8: BROWN-OUT RESET TIMING AND CHARACTERISTICS VDD VBOR and VHYST VBOR (Device in Brown-out Reset) (Device not in Brown-out Reset) 37 Reset 33(1) (due to BOR) Note 1: 64 ms delay only if PWRTE bit in the Configuration Words is programmed to `0'. 2 ms delay if PWRTE = 0 and VREGEN = 1. DS41609A-page 344 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 TABLE 29-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param No. Sym. Characteristic Min. Typ Max. Units Conditions 2 5 -- -- -- -- s s VDD = 3.3-5V, -40C to +85C VDD = 3.3-5V 10 16 27 ms VDD = 3.3V-5V, 1:16 Prescaler used 30 TMCL MCLR Pulse Width (low) 31 TWDTLP Low-Power Watchdog Timer Time-out Period 33* TPWRT Power-up Timer Period, PWRTE = 0 40 65 140 ms 34* TIOZ I/O high-impedance from MCLR Low or Watchdog Timer Reset -- -- 2.0 s 35 VBOR Brown-out Reset Voltage 2.50 2.70 2.80 V 2.30 1.8 2.40 1.90 2.50 2.00 V V 0 25 50 mV -40C to +85C 1 3 5 s VDD VBOR Brown-out Reset Hysteresis 36* VHYST 37* TBORDC Brown-out Reset DC Response Time BORV = 0, high trip point BORV = 1, low trip point (PIC16F1508/9) (PIC16LF1508/9) * These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 F and 0.01 F values in parallel are recommended. FIGURE 29-9: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 40 41 42 T1CKI 45 46 47 49 TMR0 or TMR1 2011 Microchip Technology Inc. Preliminary DS41609A-page 345 PIC16(L)F1508/9 TABLE 29-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param No. 40* Sym. Characteristic TT0H T0CKI High Pulse Width Min. No Prescaler TT0L T0CKI Low Pulse Width No Prescaler TT0P T0CKI Period 45* TT1H T1CKI High Synchronous, No Prescaler Time Synchronous, with Prescaler -- -- ns -- -- ns 0.5 TCY + 20 -- -- ns 10 -- -- ns Greater of: 20 or TCY + 40 N -- -- ns 0.5 TCY + 20 -- -- ns 15 -- -- ns Asynchronous 46* TT1L T1CKI Low Time Units 10 With Prescaler 42* Max. 0.5 TCY + 20 With Prescaler 41* Typ 30 -- -- ns Synchronous, No Prescaler 0.5 TCY + 20 -- -- ns Synchronous, with Prescaler 15 -- -- ns Asynchronous 30 -- -- ns Greater of: 30 or TCY + 40 N -- -- ns 47* TT1P 49* TCKEZTMR1 Delay from External Clock Edge to Timer Increment T1CKI Input Synchronous Period Asynchronous 60 -- -- ns 2 TOSC -- 7 TOSC -- Conditions N = prescale value (2, 4, ..., 256) N = prescale value (1, 2, 4, 8) Timers in Sync mode * These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: For proper operation, the minimum value of the ADC positive voltage reference must be 1.8V or greater. When selecting the FVR or the VREF+ pin as the source of the ADC positive voltage reference, be aware that the voltage must be 1.8V or greater. TABLE 29-6: PIC16(L)F1508/9 A/D CONVERTER (ADC) CHARACTERISTICS: Standard Operating Conditions (unless otherwise stated) Operating temperature Tested at 25C Param Sym. No. Characteristic Min. Typ Max. Units Conditions AD01 NR Resolution -- -- 10 AD02 EIL Integral Error -- -- 1.7 AD03 EDL Differential Error -- -- 1 AD04 EOFF Offset Error -- -- 2.5 LSb VREF = 3.0V AD05 EGN -- -- 2.0 LSb VREF = 3.0V AD06 VREF Reference Voltage(3) 1.8 -- VDD V AD07 VAIN Full-Scale Range VSS -- VREF V AD08 ZAIN Recommended Impedance of Analog Voltage Source -- -- 10 k * Note 1: 2: 3: 4: 5: Gain Error bit LSb VREF = 3.0V LSb No missing codes VREF = 3.0V VREF = (VREF+ minus VREF-) (NOTE 5) Can go higher if external 0.01F capacitor is present on input pin. These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Total Absolute Error includes integral, differential, offset and gain errors. The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. ADC VREF is from external VREF+ pin, VDD pin, whichever is selected as reference input. When ADC is off, it will not consume any current other than leakage current. The power-down current specification includes any such leakage from the ADC module. FVR voltage selected must be 2.048V or 4.096V. DS41609A-page 346 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 TABLE 29-7: PIC16(L)F1508/9 A/D CONVERSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C Param No. Sym. Characteristic AD130* TAD AD131 TCNV AD132* TACQ Min. Typ Max. Units Conditions A/D Clock Period 1.0 -- 9.0 s TOSC-based A/D Internal FRC Oscillator Period 1.0 1.6 6.0 s ADCS<1:0> = 11 (ADFRC mode) Conversion Time (not including Acquisition Time)(1) -- 11 -- TAD Set GO/DONE bit to conversion complete Acquisition Time -- 5.0 -- s * These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The ADRES register may be read on the following TCY cycle. FIGURE 29-10: PIC16(L)F1508/9 A/D CONVERSION TIMING (NORMAL MODE) BSF ADCON0, GO AD134 1 TCY (TOSC/2(1)) AD131 Q4 AD130 A/D CLK 9 A/D Data 8 7 6 3 OLD_DATA ADRES 1 0 NEW_DATA 1 TCY ADIF GO Sample 2 DONE AD132 Sampling Stopped Note 1: If the A/D clock source is selected as FRC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 2011 Microchip Technology Inc. Preliminary DS41609A-page 347 PIC16(L)F1508/9 FIGURE 29-11: PIC16(L)F1508/9 A/D CONVERSION TIMING (SLEEP MODE) BSF ADCON0, GO AD134 (TOSC/2 + TCY(1)) 1 TCY AD131 Q4 AD130 A/D CLK 9 A/D Data 8 7 6 OLD_DATA ADRES 3 2 1 0 NEW_DATA ADIF 1 TCY GO DONE Sample AD132 Sampling Stopped Note 1: If the A/D clock source is selected as FRC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. DS41609A-page 348 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 TABLE 29-8: COMPARATOR SPECIFICATIONS Operating Conditions: 1.8V < VDD < 5.5V, -40C < TA < +125C (unless otherwise stated). Param No. Sym. Characteristics Min. Typ. Max. Units Comments CM01 VIOFF Input Offset Voltage -- 7.5 60 mV CM02 VICM Input Common Mode Voltage 0 -- VDD V CM04A Response Time Rising Edge -- 400 800 ns High-Power mode (Note 1) CM04B Response Time Falling Edge -- 200 400 ns High-Power mode (Note 1) Response Time Rising Edge -- 1200 -- ns Low-Power mode (Note 1) Response Time Falling Edge -- 550 -- ns Low-Power mode (Note 1) Comparator Mode Change to Output Valid* -- -- 10 s -- 65 -- mV CM04C TRESP CM04D TMC2OV CM05 CHYSTER Comparator Hysteresis CM06 * Note 1: 2: Note 2 These parameters are characterized but not tested. Response time measured with one comparator input at VDD/2, while the other input transitions from VSS to VDD. Comparator Hysteresis is available when the CxHYS bit of the CMxCON0 register is enabled. TABLE 29-9: DIGITAL-TO-ANALOG CONVERTER (DAC) SPECIFICATIONS Operating Conditions: 1.8V < VDD < 5.5V, -40C < TA < +125C (unless otherwise stated). Param No. Sym. Characteristics Min. Typ. Max. Units DAC01* CLSB Step Size(2) -- VDD/32 -- V DAC02* CACC Absolute Accuracy -- -- 1/2 LSb DAC03* CR Unit Resistor Value (R) -- 5K -- CST Time(1) -- -- 10 s DAC04* Settling Comments * These parameters are characterized but not tested. Legend: TBD = To Be Determined Note 1: Settling time measured while DACR<4:0> transitions from `0000' to `1111'. 2011 Microchip Technology Inc. Preliminary DS41609A-page 349 PIC16(L)F1508/9 FIGURE 29-12: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING CK US121 US121 DT US122 US120 Note: Refer to Figure 29-4 for load conditions. TABLE 29-10: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param. No. Symbol Characteristic Min. Max. Units US120 TCKH2DTV SYNC XMIT (Master and Slave) Clock high to data-out valid 3.0-5.5V -- 80 ns 1.8-5.5V -- 100 ns US121 TCKRF Clock out rise time and fall time (Master mode) 3.0-5.5V -- 45 ns 1.8-5.5V -- 50 ns Data-out rise time and fall time 3.0-5.5V -- 45 ns 1.8-5.5V -- 50 ns US122 TDTRF FIGURE 29-13: Conditions USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING CK US125 DT US126 Note: Refer to Figure 29-4 for load conditions. TABLE 29-11: USART SYNCHRONOUS RECEIVE REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param. No. Symbol Characteristic US125 TDTV2CKL SYNC RCV (Master and Slave) Data-hold before CK (DT hold time) US126 TCKL2DTL DS41609A-page 350 Data-hold after CK (DT hold time) Preliminary Min. Max. Units 10 -- ns 15 -- ns Conditions 2011 Microchip Technology Inc. PIC16(L)F1508/9 FIGURE 29-14: SPI MASTER MODE TIMING (CKE = 0, SMP = 0) SS SP70 SCK (CKP = 0) SP71 SP72 SP78 SP79 SP79 SP78 SCK (CKP = 1) SP80 bit 6 - - - - - -1 MSb SDO LSb SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 SP73 Note: Refer to Figure 29-4 for load conditions. FIGURE 29-15: SPI MASTER MODE TIMING (CKE = 1, SMP = 1) SS SP81 SCK (CKP = 0) SP71 SP72 SP79 SP73 SCK (CKP = 1) SP80 SDO MSb SP78 bit 6 - - - - - -1 LSb SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 Note: Refer to Figure 29-4 for load conditions. 2011 Microchip Technology Inc. Preliminary DS41609A-page 351 PIC16(L)F1508/9 FIGURE 29-16: SPI SLAVE MODE TIMING (CKE = 0) SS SP70 SCK (CKP = 0) SP83 SP71 SP72 SP78 SP79 SP79 SP78 SCK (CKP = 1) SP80 MSb SDO LSb bit 6 - - - - - -1 SP77 SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 SP73 Note: Refer to Figure 29-4 for load conditions. FIGURE 29-17: SS SPI SLAVE MODE TIMING (CKE = 1) SP82 SP70 SP83 SCK (CKP = 0) SP71 SP72 SCK (CKP = 1) SP80 SDO MSb bit 6 - - - - - -1 LSb SP77 SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 Note: Refer to Figure 29-4 for load conditions. DS41609A-page 352 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 TABLE 29-12: SPI MODE REQUIREMENTS Param No. Symbol Characteristic SP70* TSSL2SCH, SS to SCK or SCK input TSSL2SCL Min. Typ Max. Units Conditions TCY -- -- ns SP71* TSCH SCK input high time (Slave mode) TCY + 20 -- -- ns SP72* TSCL SCK input low time (Slave mode) TCY + 20 -- -- ns 100 -- -- ns 100 -- -- ns 3.0-5.5V -- 10 25 ns 1.8-5.5V -- 25 50 ns -- 10 25 ns SP73* TDIV2SCH, Setup time of SDI data input to SCK edge TDIV2SCL SP74* TSCH2DIL, TSCL2DIL Hold time of SDI data input to SCK edge SP75* TDOR SDO data output rise time SP76* TDOF SDO data output fall time SP77* TSSH2DOZ SS to SDO output high-impedance 10 -- 50 ns SP78* TSCR SCK output rise time (Master mode) 3.0-5.5V -- 10 25 ns 1.8-5.5V -- 25 50 ns SP79* TSCF SCK output fall time (Master mode) -- 10 25 ns 3.0-5.5V -- -- 50 ns 1.8-5.5V -- -- 145 ns Tcy -- -- ns -- -- 50 ns 1.5TCY + 40 -- -- ns SP80* TSCH2DOV, SDO data output valid after TSCL2DOV SCK edge SP81* TDOV2SCH, SDO data output setup to SCK edge TDOV2SCL SP82* TSSL2DOV SDO data output valid after SS edge SP83* TSCH2SSH, SS after SCK edge TSCL2SSH * These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. 2011 Microchip Technology Inc. Preliminary DS41609A-page 353 PIC16(L)F1508/9 FIGURE 29-18: I2CTM BUS START/STOP BITS TIMING SCL SP93 SP91 SP90 SP92 SDA Stop Condition Start Condition Note: Refer to Figure 29-4 for load conditions. TABLE 29-13: I2CTM BUS START/STOP BITS REQUIREMENTS Param No. Symbol SP90* TSU:STA SP91* THD:STA SP92* TSU:STO SP93 Characteristic Typ Max. Units Start condition 100 kHz mode 4700 -- -- Setup time 400 kHz mode 600 -- -- Start condition 100 kHz mode 4000 -- -- Hold time 400 kHz mode 600 -- -- Stop condition 100 kHz mode 4700 -- -- Setup time 400 kHz mode 600 -- -- 100 kHz mode 4000 -- -- 400 kHz mode 600 -- -- THD:STO Stop condition Hold time * Min. Conditions ns Only relevant for Repeated Start condition ns After this period, the first clock pulse is generated ns ns These parameters are characterized but not tested. FIGURE 29-19: I2CTM BUS DATA TIMING SP103 SCL SP100 SP90 SP102 SP101 SP106 SP107 SP91 SDA In SP92 SP110 SP109 SP109 SDA Out Note: Refer to Figure 29-4 for load conditions. DS41609A-page 354 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 TABLE 29-14: I2CTM BUS DATA REQUIREMENTS Param. No. Symbol SP100* THIGH Characteristic Clock high time Min. Max. Units 100 kHz mode 4.0 -- s Device must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 -- s Device must operate at a minimum of 10 MHz 1.5TCY -- 100 kHz mode 4.7 -- s Device must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 -- s Device must operate at a minimum of 10 MHz SSP module SP101* TLOW Clock low time 1.5TCY -- SDA and SCL rise time 100 kHz mode -- 1000 ns 400 kHz mode 20 + 0.1CB 300 ns SDA and SCL fall time 100 kHz mode -- 250 ns 400 kHz mode 20 + 0.1CB 250 ns SSP module SP102* TR SP103* TF SP106* THD:DAT SP107* TSU:DAT SP109* TAA SP110* SP111 * Note 1: 2: TBUF CB Data input hold time 100 kHz mode 0 -- ns 400 kHz mode 0 0.9 s Data input setup time Output valid from clock Bus free time Conditions 100 kHz mode 250 -- ns 400 kHz mode 100 -- ns 100 kHz mode -- 3500 ns 400 kHz mode -- -- ns 100 kHz mode 4.7 -- s 400 kHz mode 1.3 -- s -- 400 pF Bus capacitive loading CB is specified to be from 10-400 pF CB is specified to be from 10-400 pF (Note 2) (Note 1) Time the bus must be free before a new transmission can start These parameters are characterized but not tested. As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. A Fast mode (400 kHz) I2CTM bus device can be used in a Standard mode (100 kHz) I2C bus system, but the requirement TSU:DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit to the SDA line TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification), before the SCL line is released. 2011 Microchip Technology Inc. Preliminary DS41609A-page 355 PIC16(L)F1508/9 NOTES: DS41609A-page 356 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 30.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS Graphs and charts are not available at this time. 2011 Microchip Technology Inc. Preliminary DS41609A-page 357 PIC16(L)F1508/9 NOTES: DS41609A-page 358 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 31.0 DEVELOPMENT SUPPORT 31.1 The PIC(R) microcontrollers and dsPIC(R) digital signal controllers are supported with a full range of software and hardware development tools: * Integrated Development Environment - MPLAB(R) IDE Software * Compilers/Assemblers/Linkers - MPLAB C Compiler for Various Device Families - HI-TECH C(R) for Various Device Families - MPASMTM Assembler - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB Assembler/Linker/Librarian for Various Device Families * Simulators - MPLAB SIM Software Simulator * Emulators - MPLAB REAL ICETM In-Circuit Emulator * In-Circuit Debuggers - MPLAB ICD 3 - PICkitTM 3 Debug Express * Device Programmers - PICkitTM 2 Programmer - MPLAB PM3 Device Programmer * Low-Cost Demonstration/Development Boards, Evaluation Kits, and Starter Kits MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16/32-bit microcontroller market. The MPLAB IDE is a Windows(R) operating system-based application that contains: * A single graphical interface to all debugging tools - Simulator - Programmer (sold separately) - In-Circuit Emulator (sold separately) - In-Circuit Debugger (sold separately) * A full-featured editor with color-coded context * A multiple project manager * Customizable data windows with direct edit of contents * High-level source code debugging * Mouse over variable inspection * Drag and drop variables from source to watch windows * Extensive on-line help * Integration of select third party tools, such as IAR C Compilers The MPLAB IDE allows you to: * Edit your source files (either C or assembly) * One-touch compile or assemble, and download to emulator and simulator tools (automatically updates all project information) * Debug using: - Source files (C or assembly) - Mixed C and assembly - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power. 2011 Microchip Technology Inc. Preliminary DS41609A-page 359 PIC16(L)F1508/9 31.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip's PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. 31.3 HI-TECH C for Various Device Families For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. The compilers include a macro assembler, linker, preprocessor, and one-step driver, and can run on multiple platforms. MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for PIC10/12/16/18 MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel(R) standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging. The MPASM Assembler features include: MPLINK Object Linker/ MPLIB Object Librarian The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the MPLAB C18 C Compiler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: The HI-TECH C Compiler code development systems are complete ANSI C compilers for Microchip's PIC family of microcontrollers and the dsPIC family of digital signal controllers. These compilers provide powerful integration capabilities, omniscient code generation and ease of use. 31.4 31.5 * Efficient linking of single libraries instead of many smaller files * Enhanced code maintainability by grouping related modules together * Flexible creation of libraries with easy module listing, replacement, deletion and extraction 31.6 MPLAB Assembler, Linker and Librarian for Various Device Families MPLAB Assembler produces relocatable machine code from symbolic assembly language for PIC24, PIC32 and dsPIC devices. MPLAB C Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: * * * * * * Support for the entire device instruction set Support for fixed-point and floating-point data Command line interface Rich directive set Flexible macro language MPLAB IDE compatibility * Integration into MPLAB IDE projects * User-defined macros to streamline assembly code * Conditional assembly for multi-purpose source files * Directives that allow complete control over the assembly process DS41609A-page 360 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 31.7 MPLAB SIM Software Simulator 31.9 The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC(R) DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on I/O, most peripherals and internal registers. The MPLAB SIM Software Simulator fully supports symbolic debugging using the MPLAB C Compilers, and the MPASM and MPLAB Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool. 31.8 MPLAB REAL ICE In-Circuit Emulator System MPLAB REAL ICE In-Circuit Emulator System is Microchip's next generation high-speed emulator for Microchip Flash DSC and MCU devices. It debugs and programs PIC(R) Flash MCUs and dsPIC(R) Flash DSCs with the easy-to-use, powerful graphical user interface of the MPLAB Integrated Development Environment (IDE), included with each kit. The emulator is connected to the design engineer's PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with incircuit debugger systems (RJ11) or with the new highspeed, noise tolerant, Low-Voltage Differential Signal (LVDS) interconnection (CAT5). The emulator is field upgradable through future firmware downloads in MPLAB IDE. In upcoming releases of MPLAB IDE, new devices will be supported, and new features will be added. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables. 2011 Microchip Technology Inc. MPLAB ICD 3 In-Circuit Debugger System MPLAB ICD 3 In-Circuit Debugger System is Microchip's most cost effective high-speed hardware debugger/programmer for Microchip Flash Digital Signal Controller (DSC) and microcontroller (MCU) devices. It debugs and programs PIC(R) Flash microcontrollers and dsPIC(R) DSCs with the powerful, yet easyto-use graphical user interface of MPLAB Integrated Development Environment (IDE). The MPLAB ICD 3 In-Circuit Debugger probe is connected to the design engineer's PC using a high-speed USB 2.0 interface and is connected to the target with a connector compatible with the MPLAB ICD 2 or MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3 supports all MPLAB ICD 2 headers. 31.10 PICkit 3 In-Circuit Debugger/ Programmer and PICkit 3 Debug Express The MPLAB PICkit 3 allows debugging and programming of PIC(R) and dsPIC(R) Flash microcontrollers at a most affordable price point using the powerful graphical user interface of the MPLAB Integrated Development Environment (IDE). The MPLAB PICkit 3 is connected to the design engineer's PC using a full speed USB interface and can be connected to the target via an Microchip debug (RJ-11) connector (compatible with MPLAB ICD 3 and MPLAB REAL ICE). The connector uses two device I/O pins and the reset line to implement in-circuit debugging and In-Circuit Serial ProgrammingTM. The PICkit 3 Debug Express include the PICkit 3, demo board and microcontroller, hookup cables and CDROM with user's guide, lessons, tutorial, compiler and MPLAB IDE software. Preliminary DS41609A-page 361 PIC16(L)F1508/9 31.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express 31.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits The PICkitTM 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip's Flash families of microcontrollers. The full featured Windows(R) programming interface supports baseline (PIC10F, PIC12F5xx, PIC16F5xx), midrange (PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30, dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit microcontrollers, and many Microchip Serial EEPROM products. With Microchip's powerful MPLAB Integrated Development Environment (IDE) the PICkitTM 2 enables in-circuit debugging on most PIC(R) microcontrollers. In-Circuit-Debugging runs, halts and single steps the program while the PIC microcontroller is embedded in the application. When halted at a breakpoint, the file registers can be examined and modified. A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. The PICkit 2 Debug Express include the PICkit 2, demo board and microcontroller, hookup cables and CDROM with user's guide, lessons, tutorial, compiler and MPLAB IDE software. 31.12 MPLAB PM3 Device Programmer The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages and a modular, detachable socket assembly to support various package types. The ICSPTM cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an MMC card for file storage and data applications. DS41609A-page 362 The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory. The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEMTM and dsPICDEMTM demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ(R) security ICs, CAN, IrDA(R), PowerSmart battery management, SEEVAL(R) evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Also available are starter kits that contain everything needed to experience the specified device. This usually includes a single application and debug capability, all on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 32.0 PACKAGING INFORMATION 32.1 Package Marking Information 20-Lead PDIP (300 mil) Example PIC16F1508 -E/P e3 1120123 XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN 20-Lead SOIC (7.50 mm) Example PIC16F1508 -E/SO e3 1120123 Legend: XX...X Y YY WW NNN e3 * Note: * Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. Standard PICmicro(R) device marking consists of Microchip part number, year code, week code and traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. 2011 Microchip Technology Inc. Preliminary DS41609A-page 363 PIC16(L)F1508/9 32.2 Package Marking Information 20-Lead SSOP (5.30 mm) Example PIC16F1508 -E/SS e3 1120123 20-Lead QFN (4x4x0.9 mm) Example PIN 1 DS41609A-page 364 PIN 1 Preliminary PIC16 F1508 -E/ML e3 120123 2011 Microchip Technology Inc. PIC16(L)F1508/9 32.3 Package Details The following sections give the technical details of the packages. /HDG3ODVWLF'XDO,Q/LQH 3 PLO%RG\>3',3@ 1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWSZZZPLFURFKLSFRPSDFNDJLQJ N E1 NOTE 1 1 2 3 D E A2 A L c A1 b1 b eB e 8QLWV 'LPHQVLRQ/LPLWV 1XPEHURI3LQV ,1&+(6 0,1 1 120 0$; 3LWFK H 7RSWR6HDWLQJ3ODQH $ 0ROGHG3DFNDJH7KLFNQHVV $ %DVHWR6HDWLQJ3ODQH $ 6KRXOGHUWR6KRXOGHU:LGWK ( 0ROGHG3DFNDJH:LGWK ( 2YHUDOO/HQJWK ' 7LSWR6HDWLQJ3ODQH / /HDG7KLFNQHVV F E E H% 8SSHU/HDG:LGWK /RZHU/HDG:LGWK 2YHUDOO5RZ6SDFLQJ %6& 1RWHV 3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD 6LJQLILFDQW&KDUDFWHULVWLF 'LPHQVLRQV'DQG(GRQRWLQFOXGHPROGIODVKRUSURWUXVLRQV0ROGIODVKRUSURWUXVLRQVVKDOOQRWH[FHHGSHUVLGH 'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0 %6& %DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &% 2011 Microchip Technology Inc. Preliminary DS41609A-page 365 PIC16(L)F1508/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS41609A-page 366 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2011 Microchip Technology Inc. Preliminary DS41609A-page 367 PIC16(L)F1508/9 /HDG3ODVWLF6KULQN6PDOO2XWOLQH 66 PP%RG\>6623@ 1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWSZZZPLFURFKLSFRPSDFNDJLQJ D N E E1 NOTE 1 1 2 e b c A2 A A1 L1 8QLWV 'LPHQVLRQ/LPLWV 1XPEHURI3LQV L 0,//,0(7(56 0,1 1 120 0$; 3LWFK H 2YHUDOO+HLJKW $ %6& 0ROGHG3DFNDJH7KLFNQHVV $ 6WDQGRII $ 2YHUDOO:LGWK ( 0ROGHG3DFNDJH:LGWK ( 2YHUDOO/HQJWK ' )RRW/HQJWK / )RRWSULQW / 5() /HDG7KLFNQHVV F )RRW$QJOH /HDG:LGWK E 1RWHV 3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD 'LPHQVLRQV'DQG(GRQRWLQFOXGHPROGIODVKRUSURWUXVLRQV0ROGIODVKRUSURWUXVLRQVVKDOOQRWH[FHHGPPSHUVLGH 'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0 %6& %DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV 5() 5HIHUHQFH'LPHQVLRQXVXDOO\ZLWKRXWWROHUDQFHIRULQIRUPDWLRQSXUSRVHVRQO\ 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &% DS41609A-page 368 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2011 Microchip Technology Inc. Preliminary DS41609A-page 369 PIC16(L)F1508/9 /HDG3ODVWLF4XDG)ODW1R/HDG3DFNDJH 0/ [[PP%RG\>4)1@ 1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWSZZZPLFURFKLSFRPSDFNDJLQJ D D2 EXPOSED PAD e E2 2 E b 2 1 1 K N N NOTE 1 TOP VIEW L BOTTOM VIEW A A1 A3 8QLWV 'LPHQVLRQ/LPLWV 1XPEHURI3LQV 0,//,0(7(56 0,1 1 120 0$; 3LWFK H 2YHUDOO+HLJKW $ 6WDQGRII $ &RQWDFW7KLFNQHVV $ 2YHUDOO:LGWK ( ([SRVHG3DG:LGWK ( 2YHUDOO/HQJWK ' ([SRVHG3DG/HQJWK %6& 5() %6& %6& ' &RQWDFW:LGWK E &RQWDFW/HQJWK / &RQWDFWWR([SRVHG3DG . 1RWHV 3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD 3DFNDJHLVVDZVLQJXODWHG 'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0 %6& %DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV 5() 5HIHUHQFH'LPHQVLRQXVXDOO\ZLWKRXWWROHUDQFHIRULQIRUPDWLRQSXUSRVHVRQO\ 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &% DS41609A-page 370 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWSZZZPLFURFKLSFRPSDFNDJLQJ 2011 Microchip Technology Inc. Preliminary DS41609A-page 371 PIC16(L)F1508/9 NOTES: DS41609A-page 372 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 APPENDIX A: DATA SHEET REVISION HISTORY Revision A Original release (10/2011). 2011 Microchip Technology Inc. Preliminary DS41609A-page 373 PIC16(L)F1508/9 NOTES: DS41609A-page 374 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 INDEX A A/D Specifications.................................................... 346, 347 Absolute Maximum Ratings .............................................. 329 AC Characteristics Industrial and Extended ............................................ 342 Load Conditions ........................................................ 341 ACKSTAT ......................................................................... 218 ACKSTAT Status Flag ...................................................... 218 ADC .................................................................................. 135 Acquisition Requirements ......................................... 146 Associated registers.................................................. 148 Block Diagram........................................................... 135 Calculating Acquisition Time..................................... 146 Channel Selection..................................................... 136 Configuration............................................................. 136 Configuring Interrupt ................................................. 140 Conversion Clock...................................................... 136 Conversion Procedure .............................................. 140 Internal Sampling Switch (RSS) Impedance.............. 146 Interrupts................................................................... 138 Operation .................................................................. 139 Operation During Sleep ............................................ 139 Port Configuration ..................................................... 136 Reference Voltage (VREF)......................................... 136 Source Impedance.................................................... 146 Starting an A/D Conversion ...................................... 138 ADCON0 Register....................................................... 29, 141 ADCON1 Register....................................................... 29, 142 ADCON2 Register............................................................. 143 ADDFSR ........................................................................... 319 ADDWFC .......................................................................... 319 ADRESH Register............................................................... 29 ADRESH Register (ADFM = 0) ......................................... 144 ADRESH Register (ADFM = 1) ......................................... 145 ADRESL Register (ADFM = 0).......................................... 144 ADRESL Register (ADFM = 1).......................................... 145 Alternate Pin Function....................................................... 112 Analog-to-Digital Converter. See ADC ANSELA Register ............................................................. 115 ANSELB Register ............................................................. 119 ANSELC Register ............................................................. 123 APFCON Register............................................................. 112 Assembler MPASM Assembler................................................... 360 Automatic Context Saving................................................... 77 B Bank 10 ............................................................................... 32 Bank 11 ............................................................................... 32 Bank 12 ............................................................................... 32 Bank 13 ............................................................................... 32 Bank 2 ................................................................................. 30 Bank 3 ................................................................................. 30 Bank 30 ............................................................................... 33 Bank 4 ................................................................................. 31 Bank 5 ................................................................................. 31 Bank 6 ................................................................................. 31 Bank 7 ................................................................................. 31 Bank 8 ................................................................................. 31 Bank 9 ................................................................................. 31 BAUDCON Register.......................................................... 248 BF ............................................................................. 218, 220 2011 Microchip Technology Inc. BF Status Flag .......................................................... 218, 220 Block Diagrams ADC .......................................................................... 135 ADC Transfer Function............................................. 147 Analog Input Model........................................... 147, 158 Block Diagrams PIC16(L)1508/9 .................................................... 5 Clock Source .............................................................. 50 Comparator............................................................... 154 Crystal Operation.................................................. 52, 53 Digital-to-Analog Converter (DAC) ........................... 150 EUSART Receive ..................................................... 238 EUSART Transmit .................................................... 237 External RC Mode ...................................................... 53 Fail-Safe Clock Monitor (FSCM)................................. 60 Generic I/O Port........................................................ 111 Interrupt Logic............................................................. 73 NCO.......................................................................... 288 On-Chip Reset Circuit................................................. 65 PIC16(L)F1508/9 ........................................................ 10 PWM......................................................................... 265 Resonator Operation .................................................. 52 Timer0 ...................................................................... 163 Timer1 ...................................................................... 167 Timer1 Gate.............................................. 172, 173, 174 Timer2 ...................................................................... 179 Voltage Reference.................................................... 131 Voltage Reference Output Buffer Example .............. 150 BORCON Register.............................................................. 67 BRA .................................................................................. 320 Break Character (12-bit) Transmit and Receive ............... 257 Brown-out Reset (BOR)...................................................... 67 Specifications ........................................................... 345 Timing and Characteristics ....................................... 344 C C Compilers MPLAB C18.............................................................. 360 CALL................................................................................. 321 CALLW ............................................................................. 321 CLCDATA Register........................................................... 285 CLCxCON Register .......................................................... 277 CLCxGLS0 Register ......................................................... 281 CLCxGLS1 Register ......................................................... 282 CLCxGLS2 Register ......................................................... 283 CLCxGLS3 Register ......................................................... 284 CLCxPOL Register ........................................................... 278 CLCxSEL0 Register.......................................................... 279 Clock Accuracy with Asynchronous Operation ................. 246 Clock Sources External Modes........................................................... 51 EC ...................................................................... 51 HS ...................................................................... 51 LP ....................................................................... 51 OST .................................................................... 52 RC ...................................................................... 53 XT ....................................................................... 51 Internal Modes............................................................ 54 HFINTOSC ......................................................... 54 Internal Oscillator Clock Switch Timing .............. 55 LFINTOSC.......................................................... 54 Clock Switching .................................................................. 57 CMOUT Register .............................................................. 160 CMxCON0 Register .......................................................... 159 Preliminary DS41609A-page 375 PIC16(L)F1508/9 CMxCON1 Register .......................................................... 160 Code Examples A/D Conversion ......................................................... 140 Initializing PORTA ..................................................... 113 Writing to Flash Program Memory ............................ 104 Comparator Associated Registers ................................................ 161 Operation .................................................................. 153 Comparator Module .......................................................... 153 Cx Output State Versus Input Conditions ................. 155 Comparator Specifications ................................................ 349 Comparators C2OUT as T1 Gate ................................................... 169 Complementary Waveform Generator (CWG) .......... 297, 298 CONFIG1 Register.............................................................. 44 CONFIG2 Register.............................................................. 45 Core Function Register ....................................................... 28 Customer Change Notification Service ............................. 381 Customer Notification Service........................................... 381 Customer Support ............................................................. 381 CWG Auto-shutdown Control ............................................. 304 Clock Source............................................................. 300 Output Control........................................................... 300 Selectable Input Sources .......................................... 300 CWGxCON0 Register ....................................................... 307 CWGxCON1 Register ....................................................... 308 CWGxCON2 Register ....................................................... 309 CWGxDBF Register .......................................................... 310 CWGxDBR Register.......................................................... 310 D DACCON0 (Digital-to-Analog Converter Control 0) Register..................................................................... 152 DACCON1 (Digital-to-Analog Converter Control 1) Register..................................................................... 152 Data Memory....................................................................... 20 DC and AC Characteristics ............................................... 357 DC Characteristics Extended and Industrial ............................................ 338 Industrial and Extended ............................................ 331 Development Support ....................................................... 359 Device Configuration........................................................... 43 Code Protection .......................................................... 46 Configuration Word ..................................................... 43 User ID .................................................................. 46, 47 Device ID Register .............................................................. 47 Device Overview ............................................................. 9, 91 Digital-to-Analog Converter (DAC).................................... 149 Associated Registers ................................................ 152 Effects of a Reset...................................................... 150 Specifications ............................................................ 349 E Effects of Reset PWM mode ............................................................... 267 Electrical Specifications .................................................... 329 Enhanced Mid-Range CPU................................................. 15 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)............................... 237 Errata .................................................................................... 8 EUSART............................................................................ 237 Associated Registers Baud Rate Generator........................................ 250 Asynchronous Mode ................................................. 239 12-bit Break Transmit and Receive................... 257 DS41609A-page 376 Associated Registers Receive .................................................... 245 Transmit.................................................... 241 Auto-Wake-up on Break ................................... 255 Baud Rate Generator (BRG) ............................ 249 Clock Accuracy................................................. 246 Receiver ........................................................... 242 Setting up 9-bit Mode with Address Detect ...... 244 Transmitter ....................................................... 239 Baud Rate Generator (BRG) Auto Baud Rate Detect..................................... 254 Baud Rate Error, Calculating............................ 249 Baud Rates, Asynchronous Modes .................. 251 Formulas........................................................... 250 High Baud Rate Select (BRGH Bit) .................. 249 Synchronous Master Mode............................... 258, 262 Associated Registers Receive .................................................... 261 Transmit.................................................... 259 Reception ......................................................... 260 Transmission .................................................... 258 Synchronous Slave Mode Associated Registers Receive .................................................... 263 Transmit.................................................... 262 Reception ......................................................... 263 Transmission .................................................... 262 Extended Instruction Set ADDFSR ................................................................... 319 F Fail-Safe Clock Monitor ...................................................... 60 Fail-Safe Condition Clearing....................................... 60 Fail-Safe Detection ..................................................... 60 Fail-Safe Operation..................................................... 60 Reset or Wake-up from Sleep .................................... 60 Firmware Instructions ....................................................... 315 Fixed Voltage Reference (FVR)........................................ 131 Associated Registers ................................................ 132 Flash Program Memory ...................................................... 95 Associated Registers ................................................ 110 Configuration Word w/ Flash Program Memory........ 110 Erasing ....................................................................... 99 Modifying .................................................................. 105 Write Verify ............................................................... 107 Writing ...................................................................... 101 FSR Register ...................................................................... 28 FVRCON (Fixed Voltage Reference Control) Register..... 132 I I2C Mode (MSSPx) Acknowledge Sequence Timing ............................... 222 Bus Collision During a Repeated Start Condition................... 227 During a Stop Condition ................................... 228 Effects of a Reset ..................................................... 223 I2C Clock Rate w/BRG.............................................. 230 Master Mode Operation.......................................................... 214 Reception ......................................................... 220 Start Condition Timing .............................. 216, 217 Transmission .................................................... 218 Multi-Master Communication, Bus Collision and Arbitration ......................................................... 223 Multi-Master Mode .................................................... 223 Read/Write Bit Information (R/W Bit) ........................ 198 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 Slave Mode Transmission .................................................... 204 Sleep Operation ........................................................ 223 Stop Condition Timing............................................... 222 INDF Register ..................................................................... 28 Indirect Addressing ............................................................. 38 Instruction Format ............................................................. 316 Instruction Set ................................................................... 315 ADDLW ..................................................................... 319 ADDWF..................................................................... 319 ADDWFC .................................................................. 319 ANDLW ..................................................................... 319 ANDWF..................................................................... 319 BRA........................................................................... 320 CALL ......................................................................... 321 CALLW...................................................................... 321 LSLF ......................................................................... 323 LSRF......................................................................... 323 MOVF........................................................................ 323 MOVIW ..................................................................... 324 MOVLB ..................................................................... 324 MOVWI ..................................................................... 325 OPTION .................................................................... 325 RESET ...................................................................... 325 SUBWFB................................................................... 327 TRIS.......................................................................... 328 BCF........................................................................... 320 BSF ........................................................................... 320 BTFSC ...................................................................... 320 BTFSS ...................................................................... 320 CALL ......................................................................... 321 CLRF......................................................................... 321 CLRW ....................................................................... 321 CLRWDT................................................................... 321 COMF ....................................................................... 321 DECF ........................................................................ 321 DECFSZ.................................................................... 322 GOTO ....................................................................... 322 INCF.......................................................................... 322 INCFSZ ..................................................................... 322 IORLW ...................................................................... 322 IORWF ...................................................................... 322 MOVLW .................................................................... 324 MOVWF .................................................................... 324 NOP .......................................................................... 325 RETFIE ..................................................................... 326 RETLW ..................................................................... 326 RETURN ................................................................... 326 RLF ........................................................................... 326 RRF........................................................................... 327 SLEEP ...................................................................... 327 SUBLW ..................................................................... 327 SUBWF ..................................................................... 327 SWAPF ..................................................................... 328 XORLW..................................................................... 328 XORWF..................................................................... 328 INTCON Register ................................................................ 78 Internal Oscillator Block INTOSC Specifications.................................................... 342 Internal Sampling Switch (RSS) Impedance ...................... 146 Internet Address................................................................ 381 Interrupt-On-Change ......................................................... 125 Associated Registers ................................................ 129 Interrupts ............................................................................. 73 2011 Microchip Technology Inc. ADC .......................................................................... 140 Associated registers w/ Interrupts .............................. 85 Configuration Word w/ Clock Sources........................ 63 TMR1........................................................................ 171 INTOSC Specifications ..................................................... 342 IOCAF Register ................................................................ 127 IOCAN Register ................................................................ 127 IOCAP Register ................................................................ 127 IOCBF Register ................................................................ 128 IOCBN Register ................................................................ 128 IOCBP Register ................................................................ 128 L LATA Register .......................................................... 115, 122 LATB Register .................................................................. 119 Load Conditions................................................................ 341 LSLF ................................................................................. 323 LSRF ................................................................................ 323 M Master Synchronous Serial Port. See MSSPx MCLR ................................................................................. 68 Internal........................................................................ 68 Memory Organization ......................................................... 17 Data ............................................................................ 20 Program...................................................................... 17 Microchip Internet Web Site.............................................. 381 MOVIW ............................................................................. 324 MOVLB ............................................................................. 324 MOVWI ............................................................................. 325 MPLAB ASM30 Assembler, Linker, Librarian ................... 360 MPLAB Integrated Development Environment Software.. 359 MPLAB PM3 Device Programmer .................................... 362 MPLAB REAL ICE In-Circuit Emulator System ................ 361 MPLINK Object Linker/MPLIB Object Librarian ................ 360 MSSPx.............................................................................. 183 SPI Mode.................................................................. 186 SSPxBUF Register ................................................... 189 SSPxSR Register ..................................................... 189 N NCO Associated registers ................................................. 296 NCOxACCH Register ....................................................... 294 NCOxACCL Register ........................................................ 294 NCOxACCU Register ....................................................... 294 NCOxCLK Register........................................................... 293 NCOxCON Register.......................................................... 293 NCOxINCH Register......................................................... 295 NCOxINCL Register ......................................................... 295 Numerically Controlled Oscillator (NCO) .......................... 287 O OPCODE Field Descriptions............................................. 315 OPTION ............................................................................ 325 OPTION Register.............................................................. 165 OSCCON Register.............................................................. 62 Oscillator Associated Registers.................................................. 63 Associated registers ................................................. 311 Oscillator Module ................................................................ 49 ECH ............................................................................ 49 ECL............................................................................. 49 ECM............................................................................ 49 HS............................................................................... 49 INTOSC ...................................................................... 49 Preliminary DS41609A-page 377 PIC16(L)F1508/9 LP................................................................................ 49 RC ............................................................................... 49 XT ............................................................................... 49 Oscillator Parameters........................................................ 342 Oscillator Specifications .................................................... 342 Oscillator Start-up Timer (OST) Specifications ............................................................ 345 Oscillator Switching Fail-Safe Clock Monitor............................................... 60 Two-Speed Clock Start-up .......................................... 58 OSCSTAT Register............................................................. 63 P Packaging ......................................................................... 363 Marking ............................................................. 363, 364 PDIP Details.............................................................. 365 PCL and PCLATH ............................................................... 16 PCL Register....................................................................... 28 PCLATH Register................................................................ 28 PCON Register ............................................................. 29, 71 PIE1 Register ................................................................ 29, 79 PIE2 Register ................................................................ 29, 80 PIE3 Register ................................................................ 29, 81 Pinout Descriptions PIC16(L)F1508/9 ........................................................ 11 PIR1 Register................................................................ 29, 82 PIR2 Register................................................................ 29, 83 PIR3 Register................................................................ 29, 84 PMADR Registers ............................................................... 95 PMADRH Registers ............................................................ 95 PMADRL Register............................................................. 108 PMADRL Registers ............................................................. 95 PMCON1 Register ...................................................... 95, 109 PMCON2 Register ...................................................... 95, 110 PMDATH Register............................................................. 108 PMDATL Register ............................................................. 108 PMDRH Register............................................................... 108 PORTA.............................................................................. 113 ANSELA Register ..................................................... 113 Associated Registers ................................................ 116 LATA Register............................................................. 30 PORTA Register ......................................................... 29 Specifications ............................................................ 343 PORTA Register ............................................................... 114 PORTB.............................................................................. 117 ANSELB Register ..................................................... 117 Associated Registers ................................................ 120 LATB Register............................................................. 30 PORTB Register ......................................................... 29 PORTB Register ............................................................... 118 PORTC ANSELC Register ..................................................... 121 Associated Registers ................................................ 123 LATC Register ............................................................ 30 Pin Descriptions and Diagrams................................. 121 PORTC Register ......................................................... 29 PORTC Register ............................................................... 122 Power-Down Mode (Sleep) ................................................. 87 Associated Registers .................................................. 90 Power-on Reset .................................................................. 66 Power-up Time-out Sequence ............................................ 68 Power-up Timer (PWRT)..................................................... 66 Specifications ............................................................ 345 PR2 Register....................................................................... 29 Program Memory ................................................................ 17 Map and Stack (PIC16(L)F1508 ................................. 18 DS41609A-page 378 Map and Stack (PIC16(L)F1509 ................................. 18 Programming, Device Instructions .................................... 315 Pulse Width Modulation (PWM)........................................ 265 Associated registers w/ PWM ................................... 270 PWM Mode Duty Cycle ........................................................ 266 Effects of Reset ................................................ 267 Example PWM Frequencies and Resolutions, 20 MHZ ................................ 267 Example PWM Frequencies and Resolutions, 8 MHz .................................. 267 Operation in Sleep Mode.................................. 267 Setup for Operation using PWMx pins ............. 268 System Clock Frequency Changes .................. 267 PWM Period.............................................................. 266 Setup for PWM Operation using PWMx Pins ........... 268 PWMxCON Register ......................................................... 269 PWMxDCH Register ......................................................... 270 PWMxDCL Register.......................................................... 270 R RCREG............................................................................. 244 RCREG Register ................................................................ 30 RCSTA Register ......................................................... 30, 247 Reader Response............................................................. 382 Read-Modify-Write Operations ......................................... 315 Registers ADCON0 (ADC Control 0) ........................................ 141 ADCON1 (ADC Control 1) ........................................ 142 ADCON2 (ADC Control 2) ........................................ 143 ADRESH (ADC Result High) with ADFM = 0) .......... 144 ADRESH (ADC Result High) with ADFM = 1) .......... 145 ADRESL (ADC Result Low) with ADFM = 0)............ 144 ADRESL (ADC Result Low) with ADFM = 1)............ 145 ANSELA (PORTA Analog Select)............................. 115 ANSELB (PORTB Analog Select)............................. 119 ANSELC (PORTC Analog Select) ............................ 123 APFCON (Alternate Pin Function Control) ............... 112 BAUDCON (Baud Rate Control)............................... 248 BORCON Brown-out Reset Control) .......................... 67 CLCDATA (Data Output) .......................................... 285 CLCxCON (CLCx Control)........................................ 277 CLCxGLS0 (Gate 1 Logic Select)............................. 281 CLCxGLS1 (Gate 2 Logic Select)............................. 282 CLCxGLS2 (Gate 3 Logic Select)............................. 283 CLCxGLS3 (Gate 4 Logic Select)............................. 284 CLCxPOL (Signal Polarity Control)........................... 278 CLCxSEL0 (Multiplexer Data 1 and 2 Select)........... 279 CMOUT (Comparator Output) .................................. 160 CMxCON0 (Cx Control) ............................................ 159 CMxCON1 (Cx Control 1) ......................................... 160 Configuration Word 1.................................................. 44 Configuration Word 2.................................................. 45 Core Function, Summary............................................ 28 CWGxCON0 (CWG Control 0) ................................. 307 CWGxCON1 (CWG Control 1) ................................. 308 CWGxCON2 (CWG Control 1) ................................. 309 CWGxDBF (CWGx Dead Band Falling Count)......... 310 CWGxDBR (CWGx Dead Band Rising Count) ......... 310 DACCON0 ................................................................ 152 DACCON1 ................................................................ 152 Device ID .................................................................... 47 FVRCON................................................................... 132 INTCON (Interrupt Control)......................................... 78 IOCAF (Interrupt-on-Change PORTA Flag).............. 127 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 IOCAN (Interrupt-on-Change PORTA Negative Edge) ................................................. 127 IOCAP (Interrupt-on-Change PORTA Positive Edge)................................................... 127 IOCBF (Interrupt-on-Change PORTB Flag).............. 128 IOCBN (Interrupt-on-Change PORTB Negative Edge) ................................................. 128 IOCBP (Interrupt-on-Change PORTB Positive Edge)................................................... 128 LATA (Data Latch PORTA)....................................... 115 LATB (Data Latch PORTB)....................................... 119 LATC (Data Latch PORTC) ...................................... 122 NCOxACCH (NCOx Accumulator High Byte) ........... 294 NCOxACCL (NCOx Accumulator Low Byte)............. 294 NCOxACCU (NCOx Accumulator Upper Byte)......... 294 NCOxCLK (NCOx Clock Control) ............................. 293 NCOxCON (NCOx Control) ...................................... 293 NCOxINCH (NCOx Increment High Byte)................. 295 NCOxINCL (NCOx Increment Low Byte) .................. 295 OPTION_REG (OPTION) ......................................... 165 OSCCON (Oscillator Control) ..................................... 62 OSCSTAT (Oscillator Status) ..................................... 63 PCON (Power Control Register) ................................. 71 PCON (Power Control) ............................................... 71 PIE1 (Peripheral Interrupt Enable 1)........................... 79 PIE2 (Peripheral Interrupt Enable 2)........................... 80 PIE3 (Peripheral Interrupt Enable 3)........................... 81 PIR1 (Peripheral Interrupt Register 1) ........................ 82 PIR2 (Peripheral Interrupt Request 2) ........................ 83 PIR3 (Peripheral Interrupt Request 3) ........................ 84 PMADRL (Program Memory Address)...................... 108 PMCON1 (Program Memory Control 1).................... 109 PMCON2 (Program Memory Control 2).................... 110 PMDATH (Program Memory Data) ........................... 108 PMDATL (Program Memory Data)............................ 108 PMDRH (Program Memory Address) ....................... 108 PORTA...................................................................... 114 PORTB...................................................................... 118 PORTC ..................................................................... 122 PWMxCON (PWM Control)....................................... 269 PWMxDCH (PWM Control)....................................... 270 PWMxDCL (PWM Control) ....................................... 270 RCREG ..................................................................... 254 RCSTA (Receive Status and Control)....................... 247 SPBRGH................................................................... 249 SPBRGL ................................................................... 249 Special Function, Summary ........................................ 29 SSPxADD (MSSPx Address and Baud Rate, I2C Mode) ......................................................... 235 SSPxCON1 (MSSPx Control 1) ................................ 232 SSPxCON2 (SSPx Control 2) ................................... 233 SSPxCON3 (SSPx Control 3) ................................... 234 SSPxMSK (SSPx Mask) ........................................... 235 SSPxSTAT (SSPx Status) ........................................ 231 STATUS...................................................................... 21 T1CON (Timer1 Control)........................................... 175 T1GCON (Timer1 Gate Control) ............................... 176 T2CON...................................................................... 181 TRISA (Tri-State PORTA)......................................... 114 TRISB (Tri-State PORTB)......................................... 118 TRISC (Tri-State PORTC) ........................................ 122 TXSTA (Transmit Status and Control) ...................... 246 VREGCON (Voltage Regulator Control) ..................... 90 WDTCON (Watchdog Timer Control) ......................... 93 WPUA (Weak Pull-up PORTA) ................................. 116 2011 Microchip Technology Inc. WPUB (Weak Pull-up PORTB)................................. 120 RESET.............................................................................. 325 Reset .................................................................................. 65 Reset Instruction................................................................. 68 Resets ................................................................................ 65 Associated Registers.................................................. 72 Revision History................................................................ 373 S Software Simulator (MPLAB SIM) .................................... 361 SPBRG Register................................................................. 30 SPBRGH Register ............................................................ 249 SPBRGL Register............................................................. 249 Special Function Registers (SFRs)..................................... 29 SPI Mode (MSSPx) Associated Registers................................................ 193 SPI Clock.................................................................. 189 SSPOV ............................................................................. 220 SSPOV Status Flag .......................................................... 220 SSPxADD Register........................................................... 235 SSPxCON1 Register ........................................................ 232 SSPxCON2 Register ........................................................ 233 SSPxCON3 Register ........................................................ 234 SSPxMSK Register........................................................... 235 SSPxSTAT Register ......................................................... 231 R/W Bit ..................................................................... 198 Stack................................................................................... 36 Accessing ................................................................... 36 Reset .......................................................................... 38 Stack Overflow/Underflow .................................................. 68 STATUS Register ............................................................... 21 SUBWFB .......................................................................... 327 T T1CON Register ......................................................... 29, 175 T1GCON Register ............................................................ 176 T2CON (Timer2) Register................................................. 181 T2CON Register ................................................................. 29 Temperature Indicator Associated Registers................................................ 134 Temperature Indicator Module.......................................... 133 Thermal Considerations.................................................... 340 Timer0 .............................................................................. 163 Associated Registers................................................ 165 Operation.................................................................. 163 Specifications ........................................................... 346 Timer1 .............................................................................. 167 Associated registers ................................................. 177 Asynchronous Counter Mode ................................... 169 Reading and Writing ......................................... 169 Clock Source Selection ............................................ 168 Interrupt .................................................................... 171 Operation.................................................................. 168 Operation During Sleep ............................................ 171 Prescaler .................................................................. 169 Specifications ........................................................... 346 Timer1 Gate Selecting Source .............................................. 169 TMR1H Register....................................................... 167 TMR1L Register ....................................................... 167 Timer2 .............................................................................. 179 Associated registers ................................................. 182 Timers Timer1 T1CON ............................................................. 175 T1GCON........................................................... 176 Preliminary DS41609A-page 379 PIC16(L)F1508/9 Timer2 T2CON.............................................................. 181 Timing Diagrams A/D Conversion ......................................................... 347 A/D Conversion (Sleep Mode) .................................. 348 Acknowledge Sequence ........................................... 222 Asynchronous Reception .......................................... 244 Asynchronous Transmission ..................................... 240 Asynchronous Transmission (Back to Back) ............ 240 Auto Wake-up Bit (WUE) During Normal Operation . 256 Auto Wake-up Bit (WUE) During Sleep .................... 256 Automatic Baud Rate Calibration .............................. 254 Baud Rate Generator with Clock Arbitration ............. 215 BRG Reset Due to SDA Arbitration During Start Condition........................................................... 226 Brown-out Reset (BOR) ............................................ 344 Brown-out Reset Situations ........................................ 67 Bus Collision During a Repeated Start Condition (Case 1) ............................................................ 227 Bus Collision During a Repeated Start Condition (Case 2) ............................................................ 227 Bus Collision During a Start Condition (SCL = 0) ..... 226 Bus Collision During a Stop Condition (Case 1) ....... 228 Bus Collision During a Stop Condition (Case 2) ....... 228 Bus Collision During Start Condition (SDA only) ...... 225 Bus Collision for Transmit and Acknowledge............ 224 CLKOUT and I/O....................................................... 343 Clock Synchronization .............................................. 212 Clock Timing ............................................................. 342 Comparator Output ................................................... 153 Fail-Safe Clock Monitor (FSCM) ................................. 61 First Start Bit Timing ................................................. 216 I2C Bus Data ............................................................. 354 I2C Bus Start/Stop Bits.............................................. 354 I2C Master Mode (7 or 10-Bit Transmission) ............ 219 I2C Master Mode (7-Bit Reception) ........................... 221 I2C Stop Condition Receive or Transmit Mode ......... 223 INT Pin Interrupt.......................................................... 76 Internal Oscillator Switch Timing................................. 56 Repeat Start Condition.............................................. 217 Reset Start-up Sequence............................................ 69 Reset, WDT, OST and Power-up Timer ................... 344 Send Break Character Sequence ............................. 257 SPI Master Mode (CKE = 1, SMP = 1) ..................... 351 SPI Mode (Master Mode) .......................................... 189 SPI Slave Mode (CKE = 0) ....................................... 352 SPI Slave Mode (CKE = 1) ....................................... 352 Synchronous Reception (Master Mode, SREN) ....... 261 Synchronous Transmission....................................... 259 Synchronous Transmission (Through TXEN) ........... 259 Timer0 and Timer1 External Clock ........................... 345 Timer1 Incrementing Edge........................................ 171 Two Speed Start-up .................................................... 59 USART Synchronous Receive (Master/Slave) ......... 350 USART Synchronous Transmission (Master/Slave)................................................... 350 Wake-up from Interrupt ............................................... 88 Timing Parameter Symbology........................................... 341 Timing Requirements I2C Bus Data ............................................................. 355 I2C Bus Start/Stop Bits ............................................. 354 SPI Mode .................................................................. 353 TMR0 Register .................................................................... 29 TMR1H Register ................................................................. 29 TMR1L Register .................................................................. 29 DS41609A-page 380 TMR2 Register.................................................................... 29 TRIS.................................................................................. 328 TRISA Register........................................................... 29, 114 TRISB Register........................................................... 29, 118 TRISC ............................................................................... 121 TRISC Register........................................................... 29, 122 Two-Speed Clock Start-up Mode........................................ 58 TXREG ............................................................................. 239 TXREG Register ................................................................. 30 TXSTA Register.......................................................... 30, 246 BRGH Bit .................................................................. 249 U USART Synchronous Master Mode Requirements, Synchronous Receive .............. 350 Requirements, Synchronous Transmission...... 350 Timing Diagram, Synchronous Receive ........... 350 Timing Diagram, Synchronous Transmission... 350 V VREF. SEE ADC Reference Voltage VREGCON Register ........................................................... 90 W Wake-up on Break ............................................................ 255 Wake-up Using Interrupts ................................................... 87 Watchdog Timer (WDT)...................................................... 68 Associated Registers .................................................. 94 Modes ......................................................................... 92 Specifications ........................................................... 345 WCOL ....................................................... 215, 218, 220, 222 WCOL Status Flag.................................... 215, 218, 220, 222 WDTCON Register ............................................................. 93 WPUA Register................................................................. 116 WPUB Register................................................................. 120 Write Protection .................................................................. 46 WWW Address ................................................................. 381 WWW, On-Line Support ....................................................... 8 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: Users of Microchip products can receive assistance through several channels: * Product Support - Data sheets and errata, application notes and sample programs, design resources, user's guides and hardware support documents, latest software releases and archived software * General Technical Support - Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing * Business of Microchip - Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives * * * * * Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Development Systems Information Line Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://microchip.com/support CUSTOMER CHANGE NOTIFICATION SERVICE Microchip's customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under "Support", click on "Customer Change Notification" and follow the registration instructions. 2011 Microchip Technology Inc. Preliminary DS41609A-page 381 PIC16(L)F1508/9 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. TO: Technical Publications Manager RE: Reader Response Total Pages Sent ________ From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: PIC16(L)F1508/9 Literature Number: DS41609A Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS41609A-page 382 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1508/9 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. [X](1) PART NO. Device - X Tape and Reel Temperature Option Range /XX XXX Package Pattern Examples: a) b) Device: PIC16F1508, PIC16LF1508, PIC16F1509, PIC16LF1509 Tape and Reel Option: Blank T = Standard packaging (tube or tray) = Tape and Reel(1) Temperature Range: I E = -40C to +85C = -40C to +125C Package: ML P SO SS c) Pattern: = = = = (Industrial) (Extended) Micro Lead Frame (QFN) 4x4 Plastic DIP SOIC SSOP QTP, SQTP, Code or Special Requirements (blank otherwise) 2011 Microchip Technology Inc. PIC16LF1508T - I/SO Tape and Reel, Industrial temperature, SOIC package PIC16F1509 - I/P Industrial temperature PDIP package PIC16F1508 - E/ML Extended temperature, QFN package QTP pattern #298 Preliminary Note 1: Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option. DS41609A-page 383 Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://www.microchip.com/ support Web Address: www.microchip.com Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 India - Bangalore Tel: 91-80-3090-4444 Fax: 91-80-3090-4123 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Korea - Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Cleveland Independence, OH Tel: 216-447-0464 Fax: 216-447-0643 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Indianapolis Noblesville, IN Tel: 317-773-8323 Fax: 317-773-5453 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8569-7000 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 China - Chongqing Tel: 86-23-8980-9588 Fax: 86-23-8980-9500 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 China - Hangzhou Tel: 86-571-2819-3187 Fax: 86-571-2819-3189 Malaysia - Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 Malaysia - Penang Tel: 60-4-227-8870 Fax: 60-4-227-4068 China - Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 Taiwan - Hsin Chu Tel: 886-3-5778-366 Fax: 886-3-5770-955 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-330-9305 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820 China - Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 China - Xiamen Tel: 86-592-2388138 Fax: 86-592-2388130 China - Zhuhai Tel: 86-756-3210040 Fax: 86-756-3210049 DS41609A-page 384 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 08/02/11 Preliminary 2011 Microchip Technology Inc. Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Microchip: PIC16F1508-I/ML PIC16F1508-I/P PIC16F1508-I/SO PIC16F1508-I/SS PIC16F1509-I/ML PIC16F1509-I/P PIC16F1509-I/SO PIC16F1509-I/SS PIC16F1508-E/ML PIC16F1508-E/P PIC16F1508-E/SO PIC16F1508-E/SS PIC16F1508T-I/ML PIC16F1508T-I/SO PIC16F1508T-I/SS PIC16F1509-E/ML PIC16F1509-E/P PIC16F1509-E/SO PIC16F1509-E/SS PIC16F1509T-I/ML PIC16F1509T-I/SO PIC16F1509T-I/SS PIC16LF1508-E/ML PIC16LF1508E/P PIC16LF1508-E/SO PIC16LF1508-E/SS PIC16LF1508-I/ML PIC16LF1508-I/P PIC16LF1508-I/SO PIC16LF1508T-I/ML PIC16LF1508T-I/SO PIC16LF1508T-I/SS PIC16LF1509-E/ML PIC16LF1509-E/P PIC16LF1509E/SO PIC16LF1509-E/SS PIC16LF1509-I/ML PIC16LF1509-I/P PIC16LF1509-I/SO PIC16LF1509-I/SS PIC16LF1509T-I/ML PIC16LF1509T-I/SO PIC16LF1509T-I/SS