STM32L071x8 STM32L071xB STM32L071xZ Access line ultra-low-power 32-bit MCU Arm(R)-based Cortex(R)-M0+, up to 192KB Flash, 20KB SRAM, 6KB EEPROM, ADC Datasheet - production data Features FBGA * * * * * * * * Ultra-low-power platform - 1.65 V to 3.6 V power supply - -40 to 125 C temperature range - 0.29 A Standby mode (3 wakeup pins) - 0.43 A Stop mode (16 wakeup lines) - 0.86 A Stop mode + RTC + 20-Kbyte RAM retention - Down to 93 A/MHz in Run mode - 5 s wakeup time (from Flash memory) - 41 A 12-bit ADC conversion at 10 ksps Core: Arm(R) 32-bit Cortex(R)-M0+ with MPU - From 32 kHz up to 32 MHz max. - 0.95 DMIPS/MHz Memories - Up to 192-Kbyte Flash memory with ECC(2 banks with read-while-write capability) - 20 -Kbyte RAM - 6 Kbytes of data EEPROM with ECC - 20-byte backup register - Sector protection against R/W operation Up to 84 fast I/Os (78 I/Os 5V tolerant) Reset and supply management - Ultra-safe, low-power BOR (brownout reset) with 5 selectable thresholds - Ultra-low-power POR/PDR - Programmable voltage detector (PVD) Clock sources - 1 to 25 MHz crystal oscillator - 32 kHz oscillator for RTC with calibration - High speed internal 16 MHz factory-trimmed RC (+/- 1%) - Internal low-power 37 kHz RC - Internal multispeed low-power 65 kHz to 4.2 MHz RC - PLL for CPU clock Pre-programmed bootloader - USART, I2C, SPI supported Development support - Serial wire debug supported November 2019 This is information on a product in full production. LQFP32 (7x7 mm) LQFP48 (7x7 mm) LQFP64 (10x10 mm) LQFP100 (14x14 mm) UFQFxPN32 (5x5 mm) UFQFPN48 (7x7 mm) UFBGA64 TFBGA64 (5x5mm) FBGA UFBGA100 (7x7 mm) WLCSP49 (3.294x3.258 mm) * * * * * * Rich Analog peripherals - 12-bit ADC 1.14 Msps up to 16 channels (down to 1.65 V) - 2x ultra-low-power comparators (window mode and wake up capability, down to 1.65 V) 7-channel DMA controller, supporting ADC, SPI, I2C, USART, Timers Up to 10x peripheral communication interfaces - 4x USART (2 with ISO 7816, IrDA), 1x UART (low power) - Up to 6x SPI 16 Mbits/s - 3x I2C (2 with SMBus/PMBus) 11x timers: 2x 16-bit with up to 4 channels, 2x 16-bit with up to 2 channels, 1x 16-bit ultra-low-power timer, 1x SysTick, 1x RTC, 2x 16-bit basic, and 2x watchdogs (independent/window) CRC calculation unit, 96-bit unique ID All packages are ECOPACK2 Table 1. Device summary Reference Part number STM32L071x8 STM32L071V8, STM32L071K8, STM32L071C8 STM32L071xB STM32L071VB, STM32L071RB, STM32L071CB, STM32L071KB STM32L071xZ STM32L071VZ, STM32L071RZ, STM32L071CZ, STM32L071KZ DS10690 Rev 7 1/148 www.st.com Contents STM32L071xx Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2 Ultra-low-power device continuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2 Interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.3 Arm(R) Cortex(R)-M0+ core with MPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.4 Reset and supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.4.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.4.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.4.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.5 Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.6 Low-power real-time clock and backup registers . . . . . . . . . . . . . . . . . . . 25 3.7 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.8 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.9 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.10 Direct memory access (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.11 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.12 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.12.1 3.13 Ultra-low-power comparators and reference voltage . . . . . . . . . . . . . . . . 28 3.14 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.15 2/148 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.14.1 General-purpose timers (TIM2, TIM3, TIM21 and TIM22) . . . . . . . . . . . 29 3.14.2 Low-power Timer (LPTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.14.3 Basic timer (TIM6, TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.14.4 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.14.5 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.14.6 Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 DS10690 Rev 7 STM32L071xx Contents 3.15.1 I2C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.15.2 Universal synchronous/asynchronous receiver transmitter (USART) . . 32 3.15.3 Low-power universal asynchronous receiver transmitter (LPUART) . . . 32 3.15.4 Serial peripheral interface (SPI)/Inter-integrated sound (I2S) . . . . . . . . 33 3.16 Cyclic redundancy check (CRC) calculation unit . . . . . . . . . . . . . . . . . . . 33 3.17 Serial wire debug port (SW-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 6.3.2 Embedded reset and power control block characteristics . . . . . . . . . . . 62 6.3.3 Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6.3.4 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 6.3.5 Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.3.6 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6.3.7 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 6.3.8 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6.3.9 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.3.10 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.3.11 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 6.3.12 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 6.3.13 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 6.3.14 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 6.3.15 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 DS10690 Rev 7 3/148 4 Contents 7 STM32L071xx 6.3.16 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 6.3.17 Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 6.3.18 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 6.3.19 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 7.1 LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 7.2 UFBGA100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 7.3 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 7.4 UFBGA64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 7.5 TFBGA64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 7.6 WLCSP49 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 7.7 LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 7.8 UFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 7.9 LQFP32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 7.10 UFQFPN32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 7.11 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 7.11.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 4/148 DS10690 Rev 7 STM32L071xx List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ultra-low-power STM32L071xx device features and peripheral counts . . . . . . . . . . . . . . . 12 Functionalities depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . 16 CPU frequency range depending on dynamic voltage scaling . . . . . . . . . . . . . . . . . . . . . . 17 Functionalities depending on the working mode (from Run/active down to standby) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 STM32L0xx peripherals interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Internal voltage reference measured values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Comparison of I2C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 STM32L071xx I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 SPI/I2S implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 STM32L071xxx pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Alternate functions port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Alternate functions port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Alternate functions port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Alternate functions port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Alternate functions port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Alternate functions port H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 62 Embedded internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Current consumption in Run mode, code with data processing running from Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Current consumption in Run mode vs code type, code with data processing running from Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Current consumption in Run mode, code with data processing running from RAM . . . . . . 67 Current consumption in Run mode vs code type, code with data processing running from RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Current consumption in Low-power run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Current consumption in Low-power sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Typical and maximum current consumptions in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . 72 Typical and maximum current consumptions in Standby mode . . . . . . . . . . . . . . . . . . . . . 73 Average current consumption during Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Peripheral current consumption in Run or Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Peripheral current consumption in Stop and Standby mode . . . . . . . . . . . . . . . . . . . . . . . 77 Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 DS10690 Rev 7 5/148 7 List of tables Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. 6/148 STM32L071xx LSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 16 MHz HSI16 oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 MSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Flash memory and data EEPROM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Flash memory and data EEPROM endurance and retention . . . . . . . . . . . . . . . . . . . . . . . 87 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 RAIN max for fADC = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Comparator 1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Comparator 2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 SPI characteristics in voltage Range 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 SPI characteristics in voltage Range 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 SPI characteristics in voltage Range 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 I2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 UFBGA100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 UFBGA100 recommended PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . 117 LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 UFBGA64 - 64-ball, 5 x 5 mm, 0.5 mm pitch ultra profile fine pitch ball grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 UFBGA64 recommended PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . . 122 TFBGA64 - 64-ball, 5 x 5 mm, 0.5 mm pitch thin profile fine pitch ball grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 TFBGA64 recommended PCB design rules (0.5 mm pitch BGA). . . . . . . . . . . . . . . . . . . 124 WLCSP49 - 49-pin, 3.294 x 3.258 mm, 0.4 mm pitch wafer level chip scale package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 WLCSP49 recommended PCB design rules (0.4 mm pitch) . . . . . . . . . . . . . . . . . . . . . . 128 LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package mechanical data. . . . . . . . . . . 130 UFQFPN48 - 48 leads, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package mechanical data. . . . . . . . . . . 136 UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 DS10690 Rev 7 STM32L071xx Table 89. Table 90. List of tables Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 DS10690 Rev 7 7/148 7 List of figures STM32L071xx List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. 8/148 STM32L071xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 STM32L071xx LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 STM32L071xx UFBGA100 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 STM32L071xx LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 STM32L071xx UFBGA64/TFBGA64 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 STM32L071xx WLCSP49 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 STM32L071xx LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 STM32L071xx UFQFPN48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 STM32L071xx LQFP32 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 STM32L071xx UFQFPN32 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 IDD vs VDD, at TA= 25/55/85/105 C, Run mode, code running from Flash memory, Range 2, HSE, 1WS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 IDD vs VDD, at TA= 25/55/85/105 C, Run mode, code running from Flash memory, Range 2, HSI16, 1WS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 IDD vs VDD, at TA= 25 C, Low-power run mode, code running from RAM, Range 3, MSI (Range 0) at 64 KHz, 0 WS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 IDD vs VDD, at TA= 25/55/ 85/105/125 C, Stop mode with RTC enabled and running on LSE Low drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 IDD vs VDD, at TA= 25/55/85/105/125 C, Stop mode with RTC disabled, all clocks OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 HSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 HSI16 minimum and maximum value versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . 84 VIH/VIL versus VDD (CMOS I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 VIH/VIL versus VDD (TTL I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Power supply and reference decoupling (VREF+ not connected to VDDA) . . . . . . . . . . . . 101 Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 102 SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat package outline . . . . . . . . . . . . . . 113 LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 LQFP100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 UFBGA100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball DS10690 Rev 7 STM32L071xx Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. List of figures grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 UFBGA100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . 118 LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat recommended footprint . . . . . . . . . . 119 LQFP64 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 UFBGA64 - 64-ball, 5 x 5 mm, 0.5 mm pitch ultra profile fine pitch ball grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 UFBGA64 - 64-ball, 5 x 5 mm, 0.5 mm pitch ultra profile fine pitch ball grid array package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 TFBGA64 - 64-ball, 5 x 5 mm, 0.5 mm pitch thin profile fine pitch ball grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 TFBGA64 - 64-ball, 5 x 5 mm, 0.5 mm pitch, thin profile fine pitch ball ,grid array recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 TFBGA64 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 WLCSP49 - 49-pin, 3.294 x 3.258 mm, 0.4 mm pitch wafer level chip scale package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 WLCSP49 - 49-pin, 3.294 x 3.258 mm, 0.4 mm pitch wafer level chip scale recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 WLCSP49 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . . 129 LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat recommended footprint . . . . . . . . . . . . 130 LQFP48 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 UFQFPN48 - 48 leads, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 UFQFPN48 - 48 leads, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 UFQFPN48 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . . 135 LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat recommended footprint . . . . . . . . . . . . 136 LQFP32 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 UFQFPN32 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 DS10690 Rev 7 9/148 9 Introduction 1 STM32L071xx Introduction The ultra-low-power STM32L071xx are offered in 10 different package types from 32 pins to 100 pins. Depending on the device chosen, different sets of peripherals are included, the description below gives an overview of the complete range of peripherals proposed in this family. These features make the ultra-low-power STM32L071xx microcontrollers suitable for a wide range of applications: * Gas/water meters and industrial sensors * Healthcare and fitness equipment * Remote control and user interface * PC peripherals, gaming, GPS equipment * Alarm system, wired and wireless sensors, video intercom This STM32L071xx datasheet should be read in conjunction with the STM32L0x1xx reference manual (RM0377). For information on the Arm(R)(a) Cortex(R)-M0+ core please refer to the Cortex(R)-M0+ Technical Reference Manual, available from the www.arm.com website. Figure 1 shows the general block diagram of the device family. a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere. 10/148 DS10690 Rev 7 STM32L071xx 2 Description Description The access line ultra-low-power STM32L071xx microcontrollers incorporate the highperformance Arm Cortex-M0+ 32-bit RISC core operating at a 32 MHz frequency, a memory protection unit (MPU), high-speed embedded memories (up to 192 Kbytes of Flash program memory, 6 Kbytes of data EEPROM and 20 Kbytes of RAM) plus an extensive range of enhanced I/Os and peripherals. The STM32L071xx devices provide high power efficiency for a wide range of performance. It is achieved with a large choice of internal and external clock sources, an internal voltage adaptation and several low-power modes. The STM32L071xx devices offer several analog features, one 12-bit ADC with hardware oversampling, two ultra-low-power comparators, several timers, one low-power timer (LPTIM), four general-purpose 16-bit timers and two basic timer, one RTC and one SysTick which can be used as timebases. They also feature two watchdogs, one watchdog with independent clock and window capability and one window watchdog based on bus clock. Moreover, the STM32L071xx devices embed standard and advanced communication interfaces: up to three I2Cs, two SPIs, one I2S, four USARTs, a low-power UART (LPUART), . The STM32L071xx also include a real-time clock and a set of backup registers that remain powered in Standby mode. The ultra-low-power STM32L071xx devices operate from a 1.8 to 3.6 V power supply (down to 1.65 V at power down) with BOR and from a 1.65 to 3.6 V power supply without BOR option. They are available in the -40 to +125 C temperature range. A comprehensive set of power-saving modes allows the design of low-power applications. DS10690 Rev 7 11/148 33 Description 2.1 STM32L071xx Device overview Table 2. Ultra-low-power STM32L071xx device features and peripheral counts Peripheral STM32L 071K8 STM32L 071C8 Flash (Kbytes) 64 Kbytes Data EEPROM (Kbytes) 3 Kbytes STM32L 071V8 STM32L 071KB STM32L 071CB 4 Basic 2 LPTIME R 1 1/1/1/1 4(3)(1)/0 6(4)(2)/1 4(3)(1)/0 6(4)(2)/1 4(3)(1)/0 6(4)(2)/1 I 2C 2 3 2 3 2 3 USART 3 4 4(3) 4 4(3) 4 GPIOs 1 23 37 84 25(3) 40(4) Clocks: HSE/LSE/HSI/MSI/LS I 12-bit synchronized ADC Number of channels 84 51(5) 25(3) 40(4) 84 51(5) 1 16(5) 1 10 1 13(4) 1 16 1 16(5) 1/1/1/1/1 1 10 1 13 1 16 1 10 1 16 1 13(4) Comparators 2 Max. CPU frequency Operating voltage STM32 L 071RZ 20 Kbytes LPUART 32 MHz 1.8 V to 3.6 V (down to 1.65 V at power-down) with BOR option 1.65 to 3.6 V without BOR option Operating temperatures Ambient temperature: -40 to +125 C Junction temperature: -40 to +130 C LQFP/ UFQFPN UFQFPN 32 48 LQFP/ UFBGA 100 LQFP/ UFQFPN/ UFQFPN48 LQFP32 WLCSP49 LQFP/ UFBGA 100 1. 3 SPI interfaces are USARTs operating in SPI master mode. 2. 4 SPI interfaces are USARTs operating in SPI master mode. 3. UFQFPN32 has 2 GPIOs and 1 UART less than LQFP32. 4. LQFP48 and UFQFPN48 have three GPIOs less than WLCSP49. 5. TFBGA64 has one GPIO, one ADC input less than LQFP64. 12/148 STM32L 071VZ 192 Kbytes Generalpurpose SPI/I2S Packages STM32L 071CZ 6 Kbytes RTC/SYSTICK/IWDG /WWDG Com. interfaces STM32L 071KZ 128 Kbytes RAM (Kbytes) Timers STM32L STM32L 071VB 071RB DS10690 Rev 7 LQFP/ TFBGA 64 LQFP/ UFQFPN/ UFQFPN48 LQFP32 WLCSP49 LQFP/ UFBGA 100 LQFP/ TFBGA 64 STM32L071xx Description Figure 1. STM32L071xx block diagram Temp sensor SWD SWD FLASH EEPROM BOOT FIREWALL CORTEX M0+ CPU Fmax:32MHz ADC1 AINx SPI1 MISO, MOSI, SCK, NSS USART1 RX, TX, RTS, CTS, CK RAM MPU DBG DMA1 NVIC EXTI A P B 2 TIM21 2ch TIM22 2ch BRIDGE PA[0:15] GPIO PORT A PB[0:8] GPIO PORT B COMP1 INP, INM, OUT COMP2 INP, INM, OUT LPTIM1 IN1, IN2, ETR, OUT CRC BRIDGE RAM 1K AHB: Fmax 32MHz TIM6 TIM7 A P B 1 OSC_IN, OSC_OUT HSE HSI 16M LSI SCL, SDA, SMBA I2C2 SCL, SDA I2C3 SCL, SDA, SMBA USART2 RX, TX, RTS, CTS, CK USART4 RX, TX, RTS, CTS, CK IWDG TIM2 RX, TX, RTS, CTS, CK RX, TX, RTS, CTS MISO/MCK, MOSI/SD, SCK/CK, NSS/ WS 4ch TIM3 4ch USART5 PLL MSI RTC LPUART1 BCKP REG SPI2/I2S RESET & CLK WKUPx OSC32_IN, OSC32_OUT I2C1 WWDG LSE PVD_IN VREF_OUT PMU NRST VDDA VDD REGULATOR MSv35454V1 DS10690 Rev 7 13/148 33 Description 2.2 STM32L071xx Ultra-low-power device continuum The ultra-low-power family offers a large choice of core and features, from 8-bit proprietary core up to Arm(R) Cortex(R)-M4, including Arm(R) Cortex(R)-M3 and Arm(R) Cortex(R)-M0+. The STM32Lx series are the best choice to answer your needs in terms of ultra-low-power features. The STM32 ultra-low-power series are the best solution for applications such as gaz/water meter, keyboard/mouse or fitness and healthcare application. Several built-in features like LCD drivers, dual-bank memory, low-power run mode, operational amplifiers, 128-bit AES, DAC, crystal-less USB and many other definitely help you building a highly cost optimized application by reducing BOM cost. STMicroelectronics, as a reliable and long-term manufacturer, ensures as much as possible pin-to-pin compatibility between all STM8Lx and STM32Lx on one hand, and between all STM32Lx and STM32Fx on the other hand. Thanks to this unprecedented scalability, your legacy application can be upgraded to respond to the latest market feature and efficiency requirements. 14/148 DS10690 Rev 7 STM32L071xx Functional overview 3 Functional overview 3.1 Low-power modes The ultra-low-power STM32L071xx support dynamic voltage scaling to optimize its power consumption in Run mode. The voltage from the internal low-drop regulator that supplies the logic can be adjusted according to the system's maximum operating frequency and the external voltage supply. There are three power consumption ranges: * Range 1 (VDD range limited to 1.71-3.6 V), with the CPU running at up to 32 MHz * Range 2 (full VDD range), with a maximum CPU frequency of 16 MHz * Range 3 (full VDD range), with a maximum CPU frequency limited to 4.2 MHz Seven low-power modes are provided to achieve the best compromise between low-power consumption, short startup time and available wakeup sources: * Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. Sleep mode power consumption at 16 MHz is about 1 mA with all peripherals off. * Low-power run mode This mode is achieved with the multispeed internal (MSI) RC oscillator set to the lowspeed clock (max 131 kHz), execution from SRAM or Flash memory, and internal regulator in low-power mode to minimize the regulator's operating current. In Lowpower run mode, the clock frequency and the number of enabled peripherals are both limited. * Low-power sleep mode This mode is achieved by entering Sleep mode with the internal voltage regulator in low-power mode to minimize the regulator's operating current. In Low-power sleep mode, both the clock frequency and the number of enabled peripherals are limited; a typical example would be to have a timer running at 32 kHz. When wakeup is triggered by an event or an interrupt, the system reverts to the Run mode with the regulator on. Stop mode with RTC The Stop mode achieves the lowest power consumption while retaining the RAM and register contents and real time clock. All clocks in the VCORE domain are stopped, the PLL, MSI RC, HSE crystal and HSI RC oscillators are disabled. The LSE or LSI is still running. The voltage regulator is in the low-power mode. Some peripherals featuring wakeup capability can enable the HSI RC during Stop mode to detect their wakeup condition. The device can be woken up from Stop mode by any of the EXTI line, in 3.5 s, the processor can serve the interrupt or resume the code. The EXTI line source can be any GPIO. It can be the PVD output, the comparator 1 event or comparator 2 event (if internal reference voltage is on), it can be the RTC alarm/tamper/timestamp/wakeup events, the USART/I2C/LPUART/LPTIMER wakeup events. DS10690 Rev 7 15/148 33 Functional overview * STM32L071xx Stop mode without RTC The Stop mode achieves the lowest power consumption while retaining the RAM and register contents. All clocks are stopped, the PLL, MSI RC, HSI and LSI RC, HSE and LSE crystal oscillators are disabled. Some peripherals featuring wakeup capability can enable the HSI RC during Stop mode to detect their wakeup condition. The voltage regulator is in the low-power mode. The device can be woken up from Stop mode by any of the EXTI line, in 3.5 s, the processor can serve the interrupt or resume the code. The EXTI line source can be any GPIO. It can be the PVD output, the comparator 1 event or comparator 2 event (if internal reference voltage is on). It can also be wakened by the USART/I2C/LPUART/LPTIMER wakeup events. * Standby mode with RTC The Standby mode is used to achieve the lowest power consumption and real time clock. The internal voltage regulator is switched off so that the entire VCORE domain is powered off. The PLL, MSI RC, HSE crystal and HSI RC oscillators are also switched off. The LSE or LSI is still running. After entering Standby mode, the RAM and register contents are lost except for registers in the Standby circuitry (wakeup logic, IWDG, RTC, LSI, LSE Crystal 32 KHz oscillator, RCC_CSR register). The device exits Standby mode in 60 s when an external reset (NRST pin), an IWDG reset, a rising edge on one of the three WKUP pins, RTC alarm (Alarm A or Alarm B), RTC tamper event, RTC timestamp event or RTC Wakeup event occurs. * Standby mode without RTC The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire VCORE domain is powered off. The PLL, MSI RC, HSI and LSI RC, HSE and LSE crystal oscillators are also switched off. After entering Standby mode, the RAM and register contents are lost except for registers in the Standby circuitry (wakeup logic, IWDG, RTC, LSI, LSE Crystal 32 KHz oscillator, RCC_CSR register). The device exits Standby mode in 60 s when an external reset (NRST pin) or a rising edge on one of the three WKUP pin occurs. Note: The RTC, the IWDG, and the corresponding clock sources are not stopped automatically by entering Stop or Standby mode. Table 3. Functionalities depending on the operating power supply range Operating power supply range(1) 16/148 Functionalities depending on the operating power supply range ADC operation Dynamic voltage scaling range VDD = 1.65 to 1.71 V ADC only, conversion time up to 570 ksps Range 2 or range 3 VDD = 1.71 to 1.8 V(2) ADC only, conversion time up to 1.14 Msps Range 1, range 2 or range 3 VDD = 1.8 to 2.0 V(2) Conversion time up to 1.14 Msps Range1, range 2 or range 3 DS10690 Rev 7 STM32L071xx Functional overview Table 3. Functionalities depending on the operating power supply range (continued) Operating power supply range(1) Functionalities depending on the operating power supply range ADC operation Dynamic voltage scaling range VDD = 2.0 to 2.4 V Conversion time up to 1.14 Msps Range 1, range 2 or range 3 VDD = 2.4 to 3.6 V Conversion time up to 1.14 Msps Range 1, range 2 or range 3 1. GPIO speed depends on VDD voltage. Refer to Table 60: I/O AC characteristics for more information about I/O speed. 2. CPU frequency changes from initial to final must respect "fcpu initial <4*fcpu final". It must also respect 5 s delay between two changes. For example to switch from 4.2 MHz to 32 MHz, you can switch from 4.2 MHz to 16 MHz, wait 5 s, then switch from 16 MHz to 32 MHz. Table 4. CPU frequency range depending on dynamic voltage scaling CPU frequency range Dynamic voltage scaling range 16 MHz to 32 MHz (1ws) 32 kHz to 16 MHz (0ws) Range 1 8 MHz to 16 MHz (1ws) 32 kHz to 8 MHz (0ws) Range 2 32 kHz to 4.2 MHz (0ws) Range 3 Table 5. Functionalities depending on the working mode (from Run/active down to standby) (1)(2) Standby Run/Active Sleep CPU Y -- Y -- -- -- Flash memory O O O O -- -- RAM Y Y Y Y Y -- Backup registers Y Y Y Y Y Y EEPROM O O O O -- -- Brown-out reset (BOR) O O O O O DMA O O O O -- Programmable Voltage Detector (PVD) O O O O O O - Power-on/down reset (POR/PDR) Y Y Y Y Y Y Y IPs DS10690 Rev 7 Lowpower sleep Stop Lowpower run Wakeup capability O Wakeup capability O O -- Y 17/148 33 Functional overview STM32L071xx Table 5. Functionalities depending on the working mode (from Run/active down to standby) (continued)(1)(2) Standby Run/Active Sleep High Speed Internal (HSI) O O -- -- (3) -- High Speed External (HSE) O O O O -- -- Low Speed Internal (LSI) O O O O O O Low Speed External (LSE) O O O O O O Multi-Speed Internal (MSI) O O Y Y -- -- Inter-Connect Controller Y Y Y Y Y -- RTC O O O O O O O RTC Tamper O O O O O O O O Auto WakeUp (AWU) O O O O O O O O USART O O O O O(4) O -- O -- IPs Lowpower sleep Stop Lowpower run Wakeup capability Wakeup capability LPUART O O O O O(4) SPI O O O O -- I2C O O -- -- O(5) ADC O O -- -- -- -- Temperature sensor O O O O O -- Comparators O O O O O 16-bit timers O O O O -- LPTIMER O O O O O O IWDG O O O O O O WWDG O O O O -- SysTick Timer O O O O GPIOs O O O O 0 s 0.36 s 3 s 32 s Wakeup time to Run mode 18/148 DS10690 Rev 7 -O O -- --- O O --- O O 3.5 s 2 pins 50 s STM32L071xx Functional overview Table 5. Functionalities depending on the working mode (from Run/active down to standby) (continued)(1)(2) IPs Run/Active Sleep Lowpower run Stop Lowpower sleep Standby Wakeup capability Wakeup capability 0.28 A (No 0.4 A (No RTC) VDD=1.8 V RTC) VDD=1.8 V Consumption VDD=1.8 to 3.6 V (Typ) Down to 140 A/MHz (from Flash memory) Down to 37 A/MHz (from Flash memory) Down to 8 A 0.65 A (with 0.8 A (with =1.8 V RTC) VDD=1.8 V RTC) V DD Down to 4.5 A 0.29 A (No 0.4 A (No RTC) VDD=3.0 V RTC) VDD=3.0 V 1 A (with RTC) 0.85 A (with VDD=3.0 V RTC) VDD=3.0 V 1. Legend: "Y" = Yes (enable). "O" = Optional can be enabled/disabled by software) "-" = Not available 2. The consumption values given in this table are preliminary data given for indication. They are subject to slight changes. 3. Some peripherals with wakeup from Stop capability can request HSI to be enabled. In this case, HSI is woken up by the peripheral, and only feeds the peripheral which requested it. HSI is automatically put off when the peripheral does not need it anymore. 4. UART and LPUART reception is functional in Stop mode. It generates a wakeup interrupt on Start. To generate a wakeup on address match or received frame event, the LPUART can run on LSE clock while the UART has to wake up or keep running the HSI clock. 5. I2C address detection is functional in Stop mode. It generates a wakeup interrupt in case of address match. It will wake up the HSI during reception. 3.2 Interconnect matrix Several peripherals are directly interconnected. This allows autonomous communication between peripherals, thus saving CPU resources and power consumption. In addition, these hardware connections allow fast and predictable latency. Depending on peripherals, these interconnections can operate in Run, Sleep, Low-power run, Low-power sleep and Stop modes. Table 6. STM32L0xx peripherals interconnect matrix Interconnect source Lowpower sleep Stop Y Y - Y Y Y Y Y Y Y - Interconnect action Run TIM2,TIM21, TIM22 Timer input channel, trigger from analog signals comparison Y Y LPTIM Timer input channel, trigger from analog signals comparison Y TIMx Timer triggered by other timer Y COMPx TIMx LowSleep power run Interconnect destination DS10690 Rev 7 19/148 33 Functional overview STM32L071xx Table 6. STM32L0xx peripherals interconnect matrix (continued) Interconnect source Lowpower sleep Stop Y Y - Y Y Y Y Y Y Y Y - Timer input channel and trigger Y Y Y Y - LPTIM Timer input channel and trigger Y Y Y Y Y ADC Conversion trigger Y Y Y Y - Interconnect action Run TIM21 Timer triggered by Auto wake-up Y Y LPTIM Timer triggered by RTC event Y TIMx Clock source used as input channel for RC measurement and trimming TIMx RTC All clock source GPIO 3.3 LowSleep power run Interconnect destination Arm(R) Cortex(R)-M0+ core with MPU The Cortex-M0+ processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including: * a simple architecture that is easy to learn and program * ultra-low power, energy-efficient operation * excellent code density * deterministic, high-performance interrupt handling * upward compatibility with Cortex-M processor family * platform security robustness, with integrated Memory Protection Unit (MPU). The Cortex-M0+ processor is built on a highly area and power optimized 32-bit processor core, with a 2-stage pipeline Von Neumann architecture. The processor delivers exceptional energy efficiency through a small but powerful instruction set and extensively optimized design, providing high-end processing hardware including a single-cycle multiplier. The Cortex-M0+ processor provides the exceptional performance expected of a modern 32bit architecture, with a higher code density than other 8-bit and 16-bit microcontrollers. Owing to its embedded Arm core, the STM32L071xx are compatible with all Arm tools and software. 20/148 DS10690 Rev 7 STM32L071xx Functional overview Nested vectored interrupt controller (NVIC) The ultra-low-power STM32L071xx embed a nested vectored interrupt controller able to handle up to 32 maskable interrupt channels and 4 priority levels. The Cortex-M0+ processor closely integrates a configurable Nested Vectored Interrupt Controller (NVIC), to deliver industry-leading interrupt performance. The NVIC: * includes a Non-Maskable Interrupt (NMI) * provides zero jitter interrupt option * provides four interrupt priority levels The tight integration of the processor core and NVIC provides fast execution of Interrupt Service Routines (ISRs), dramatically reducing the interrupt latency. This is achieved through the hardware stacking of registers, and the ability to abandon and restart loadmultiple and store-multiple operations. Interrupt handlers do not require any assembler wrapper code, removing any code overhead from the ISRs. Tail-chaining optimization also significantly reduces the overhead when switching from one ISR to another. To optimize low-power designs, the NVIC integrates with the sleep modes, that include a deep sleep function that enables the entire device to enter rapidly stop or standby mode. This hardware block provides flexible interrupt management features with minimal interrupt latency. 3.4 Reset and supply management 3.4.1 Power supply schemes 3.4.2 * VDD = 1.65 to 3.6 V: external power supply for I/Os and the internal regulator. Provided externally through VDD pins. * VSSA, VDDA = 1.65 to 3.6 V: external analog power supplies for ADC reset blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively. Power supply supervisor The devices have an integrated ZEROPOWER power-on reset (POR)/power-down reset (PDR) that can be coupled with a brownout reset (BOR) circuitry. Two versions are available: * The version with BOR activated at power-on operates between 1.8 V and 3.6 V. * The other version without BOR operates between 1.65 V and 3.6 V. After the VDD threshold is reached (1.65 V or 1.8 V depending on the BOR which is active or not at power-on), the option byte loading process starts, either to confirm or modify default thresholds, or to disable the BOR permanently: in this case, the VDD min value becomes 1.65 V (whatever the version, BOR active or not, at power-on). When BOR is active at power-on, it ensures proper operation starting from 1.8 V whatever the power ramp-up phase before it reaches 1.8 V. When BOR is not active at power-up, the power ramp-up should guarantee that 1.65 V is reached on VDD at least 1 ms after it exits the POR area. Five BOR thresholds are available through option bytes, starting from 1.8 V to 3 V. To reduce the power consumption in Stop mode, it is possible to automatically switch off the DS10690 Rev 7 21/148 33 Functional overview STM32L071xx internal reference voltage (VREFINT) in Stop mode. The device remains in reset mode when VDD is below a specified threshold, VPOR/PDR or VBOR, without the need for any external reset circuit. Note: The start-up time at power-on is typically 3.3 ms when BOR is active at power-up, the startup time at power-on can be decreased down to 1 ms typically for devices with BOR inactive at power-up. The devices feature an embedded programmable voltage detector (PVD) that monitors the VDD/VDDA power supply and compares it to the VPVD threshold. This PVD offers 7 different levels between 1.85 V and 3.05 V, chosen by software, with a step around 200 mV. An interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. 3.4.3 Voltage regulator The regulator has three operation modes: main (MR), low power (LPR) and power down. 3.5 * MR is used in Run mode (nominal regulation) * LPR is used in the Low-power run, Low-power sleep and Stop modes * Power down is used in Standby mode. The regulator output is high impedance, the kernel circuitry is powered down, inducing zero consumption but the contents of the registers and RAM are lost except for the standby circuitry (wakeup logic, IWDG, RTC, LSI, LSE crystal 32 KHz oscillator, RCC_CSR). Clock management The clock controller distributes the clocks coming from different oscillators to the core and the peripherals. It also manages clock gating for low-power modes and ensures clock robustness. It features: * Clock prescaler To get the best trade-off between speed and current consumption, the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler. * Safe clock switching Clock sources can be changed safely on the fly in Run mode through a configuration register. * Clock management To reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory. * System clock source Three different clock sources can be used to drive the master clock SYSCLK: * - 1-25 MHz high-speed external crystal (HSE), that can supply a PLL - 16 MHz high-speed internal RC oscillator (HSI), trimmable by software, that can supply a PLLMultispeed internal RC oscillator (MSI), trimmable by software, able to generate 7 frequencies (65 kHz, 131 kHz, 262 kHz, 524 kHz, 1.05 MHz, 2.1 MHz, 4.2 MHz). When a 32.768 kHz clock source is available in the system (LSE), the MSI frequency can be trimmed by software down to a 0.5% accuracy. Auxiliary clock source Two ultra-low-power clock sources that can be used to drive the real-time clock: 22/148 DS10690 Rev 7 STM32L071xx * Functional overview - 32.768 kHz low-speed external crystal (LSE) - 37 kHz low-speed internal RC (LSI), also used to drive the independent watchdog. The LSI clock can be measured using the high-speed internal RC oscillator for greater precision. RTC clock source The LSI, LSE or HSE sources can be chosen to clock the RTC, whatever the system clock. * Startup clock After reset, the microcontroller restarts by default with an internal 2.1 MHz clock (MSI). The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts. * Clock security system (CSS) This feature can be enabled by software. If an HSE clock failure occurs, the master clock is automatically switched to HSI and a software interrupt is generated if enabled. Another clock security system can be enabled, in case of failure of the LSE it provides an interrupt or wakeup event which is generated if enabled. * Clock-out capability (MCO: microcontroller clock output) It outputs one of the internal clocks for external use by the application. Several prescalers allow the configuration of the AHB frequency, each APB (APB1 and APB2) domains. The maximum frequency of the AHB and the APB domains is 32 MHz. See Figure 2 for details on the clock tree. DS10690 Rev 7 23/148 33 Functional overview STM32L071xx Figure 2. Clock tree @V33 LSI RC Enable Watchdog Legend: HSE = High-speed external clock signal HSI = High-speed internal clock signal LSI = Low-speed internal clock signal LSE = Low-speed external clock signal MSI = Multispeed internal clock signal Watchdog LS LSI tempo RTCSEL RTC2 enable LSE OSC RTC LSE tempo LSU LSD @V18 @V33 MSI RC LSD 1 MHz LSI LSE MSI Level shifters @V18 MCOSEL ADC enable ADCCLK MCO / 1,2,4,8,16 not deepsleep / 2,4,8,16 @V33 HSI16 RC CK_PWR not deepsleep ck_rchs Level shifters @V18 / 1,4 HSI16 System Clock HSE OSC Level shifters @V18 PLLSRC PLLCLK @V33 ck_pllin PLL LSU @V33 1 MHz Clock Detector HCLK / 1,2,..., 512 APB1 PRESC / 1,2,4,8,16 SysTick Timer 32 MHz max. PCLK1 to APB1 peripherals Peripheral clock enable to TIMx If (APB1 presc=1) x1 else x2) / 2,3,4 LSD not (sleep or deepsleep) AHB PRESC X 3,4,6,8,12,16, 24,32,48 Level shifters @VDDCORE HSE present or not FCLK /8 MSI HSI16 HSE @V33 not (sleep or deepsleep) Clock Source Control APB2 PRESC / 1,2,4,8,16 Peripheral clock enable PCLK2 to APB2 32 MHz peripherals max. Peripheral clock enable If (APB2 presc=1) x1 else x2) LSI SYSCLK to TIMx Peripheral clock enable LSE HSI16 Peripheral clock enable PCLK Peripheral clock enable LPTIMCLK LPUART/ UARTCLK I2CCLK MSv35455V1 24/148 DS10690 Rev 7 STM32L071xx 3.6 Functional overview Low-power real-time clock and backup registers The real time clock (RTC) and the 5 backup registers are supplied in all modes including standby mode. The backup registers are five 32-bit registers used to store 20 bytes of user application data. They are not reset by a system reset, or when the device wakes up from Standby mode. The RTC is an independent BCD timer/counter. Its main features are the following: * * * * * * * * * Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in BCD (binary-coded decimal) format Automatically correction for 28, 29 (leap year), 30, and 31 day of the month Two programmable alarms with wake up from Stop and Standby mode capability Periodic wakeup from Stop and Standby with programmable resolution and period On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to synchronize it with a master clock. Reference clock detection: a more precise second source clock (50 or 60 Hz) can be used to enhance the calendar precision. Digital calibration circuit with 1 ppm resolution, to compensate for quartz crystal inaccuracy 2 anti-tamper detection pins with programmable filter. The MCU can be woken up from Stop and Standby modes on tamper event detection. Timestamp feature which can be used to save the calendar content. This function can be triggered by an event on the timestamp pin, or by a tamper event. The MCU can be woken up from Stop and Standby modes on timestamp event detection. The RTC clock sources can be: * * * * 3.7 A 32.768 kHz external crystal A resonator or oscillator The internal low-power RC oscillator (typical frequency of 37 kHz) The high-speed external clock General-purpose inputs/outputs (GPIOs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions, and can be individually remapped using dedicated alternate function registers. All GPIOs are high current capable. Each GPIO output, speed can be slowed (40 MHz, 10 MHz, 2 MHz, 400 kHz). The alternate function configuration of I/Os can be locked if needed following a specific sequence in order to avoid spurious writing to the I/O registers. The I/O controller is connected to a dedicated IO bus with a toggling speed of up to 32 MHz. Extended interrupt/event controller (EXTI) The extended interrupt/event controller consists of 29 edge detector lines used to generate interrupt/event requests. Each line can be individually configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 84 GPIOs can be connected to the 16 configurable interrupt/event lines. The 13 other lines are connected to PVD, RTC, USARTs, I2C, LPUART, LPTIMER or comparator events. DS10690 Rev 7 25/148 33 Functional overview 3.8 STM32L071xx Memories The STM32L071xx devices have the following features: * 20 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states. With the enhanced bus matrix, operating the RAM does not lead to any performance penalty during accesses to the system bus (AHB and APB buses). * The non-volatile memory is divided into three arrays: - 64, 128 or 192 Kbytes of embedded Flash program memory - 6 Kbytes of data EEPROM - Information block containing 32 user and factory options bytes plus 8 Kbytes of system memory Flash program and data EEPROM are divided into two banks. This allows writing in one bank while running code or reading data from the other bank. The user options bytes are used to write-protect or read-out protect the memory (with 4 Kbyte granularity) and/or readout-protect the whole memory with the following options: * Level 0: no protection * Level 1: memory readout protected. The Flash memory cannot be read from or written to if either debug features are connected or boot in RAM is selected * Level 2: chip readout protected, debug features (Cortex-M0+ serial wire) and boot in RAM selection disabled (debugline fuse) The firewall protects parts of code/data from access by the rest of the code that is executed outside of the protected area. The granularity of the protected code segment or the nonvolatile data segment is 256 bytes (Flash memory or EEPROM) against 64 bytes for the volatile data segment (RAM). The whole non-volatile memory embeds the error correction code (ECC) feature. 3.9 Boot modes At startup, BOOT0 pin and nBOOT1 option bit are used to select one of three boot options: * Boot from Flash memory * Boot from System memory * Boot from embedded RAM The boot loader is located in System memory. It is used to reprogram the Flash memory by using SPI1(PA4, PA5, PA6, PA7) or SPI2 (PB12, PB13, PB14, PB15), I2C1 (PB6, PB7) or I2C2 (PB10, PB11), USART1(PA9, PA10) or USART2(PA2, PA3). See STM32TM microcontroller system memory boot mode AN2606 for details. 26/148 DS10690 Rev 7 STM32L071xx 3.10 Functional overview Direct memory access (DMA) The flexible 7-channel, general-purpose DMA is able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports circular buffer management, avoiding the generation of interrupts when the controller reaches the end of the buffer. Each channel is connected to dedicated hardware DMA requests, with software trigger support for each channel. Configuration is done by software and transfer sizes between source and destination are independent. The DMA can be used with the main peripherals: SPI, I2C, USART, LPUART, general-purpose timers, and ADC. 3.11 Analog-to-digital converter (ADC) A native 12-bit, extended to 16-bit through hardware oversampling, analog-to-digital converter is embedded into STM32L071xx device. It has up to 16 external channels and 3 internal channels (temperature sensor, voltage reference). Three channels, PA0, PA4 and PA5, are fast channels, while the others are standard channels. The ADC performs conversions in single-shot or scan mode. In scan mode, automatic conversion is performed on a selected group of analog inputs. The ADC frequency is independent from the CPU frequency, allowing maximum sampling rate of 1.14 MSPS even with a low CPU speed. The ADC consumption is low at all frequencies (~25 A at 10 kSPS, ~240 A at 1MSPS). An auto-shutdown function guarantees that the ADC is powered off except during the active conversion phase. The ADC can be served by the DMA controller. It can operate from a supply voltage down to 1.65 V. The ADC features a hardware oversampler up to 256 samples, this improves the resolution to 16 bits (see AN2668). An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all scanned channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. The events generated by the general-purpose timers (TIMx) can be internally connected to the ADC start triggers, to allow the application to synchronize A/D conversions and timers. 3.12 Temperature sensor The temperature sensor (TSENSE) generates a voltage VSENSE that varies linearly with temperature. The temperature sensor is internally connected to the ADC_IN18 input channel which is used to convert the sensor output voltage into a digital value. The sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. As the offset of the temperature sensor varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only. DS10690 Rev 7 27/148 33 Functional overview STM32L071xx To improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by ST. The temperature sensor factory calibration data are stored by ST in the system memory area, accessible in read-only mode. Table 7. Temperature sensor calibration values Calibration value name 3.12.1 Description Memory address TSENSE_CAL1 TS ADC raw data acquired at temperature of 30 C, VDDA= 3 V 0x1FF8 007A - 0x1FF8 007B TSENSE_CAL2 TS ADC raw data acquired at temperature of 130 C VDDA= 3 V 0x1FF8 007E - 0x1FF8 007F Internal voltage reference (VREFINT) The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the ADC and Comparators. VREFINT is internally connected to the ADC_IN17 input channel. It enables accurate monitoring of the VDD value (when no external voltage, VREF+, is available for ADC). The precise voltage of VREFINT is individually measured for each part by ST during production test and stored in the system memory area. It is accessible in read-only mode. Table 8. Internal voltage reference measured values Calibration value name VREFINT_CAL 3.13 Description Raw data acquired at temperature of 25 C VDDA = 3 V Memory address 0x1FF8 0078 - 0x1FF8 0079 Ultra-low-power comparators and reference voltage The STM32L071xx embed two comparators sharing the same current bias and reference voltage. The reference voltage can be internal or external (coming from an I/O). * One comparator with ultra low consumption * One comparator with rail-to-rail inputs, fast or slow mode. * The threshold can be one of the following: - External I/O pins - Internal reference voltage (VREFINT) - submultiple of Internal reference voltage(1/4, 1/2, 3/4) for the rail to rail comparator. Both comparators can wake up the devices from Stop mode, and be combined into a window comparator. The internal reference voltage is available externally via a low-power / low-current output buffer (driving current capability of 1 A typical). 28/148 DS10690 Rev 7 STM32L071xx 3.14 Functional overview Timers and watchdogs The ultra-low-power STM32L071xx devices include three general-purpose timers, one lowpower timer (LPTIM), one basic timer, two watchdog timers and the SysTick timer. Table 9 compares the features of the general-purpose and basic timers. Table 9. Timer feature comparison Timer Counter resolution Counter type Prescaler factor DMA request generation TIM2, TIM3 16-bit Up, down, up/down Any integer between 1 and 65536 Yes 4 No TIM21, TIM22 16-bit Up, down, up/down Any integer between 1 and 65536 No 2 No TIM6, TIM7 16-bit Up Any integer between 1 and 65536 Yes 0 No 3.14.1 Capture/compare Complementary channels outputs General-purpose timers (TIM2, TIM3, TIM21 and TIM22) There are four synchronizable general-purpose timers embedded in the STM32L071xx device (see Table 9 for differences). TIM2, TIM3 TIM2 and TIM3 are based on 16-bit auto-reload up/down counter. It includes a 16-bit prescaler. It features four independent channels each for input capture/output compare, PWM or one-pulse mode output. The TIM2/TIM3 general-purpose timers can work together or with the TIM21 and TIM22 general-purpose timers via the Timer Link feature for synchronization or event chaining. Their counter can be frozen in debug mode. Any of the general-purpose timers can be used to generate PWM outputs. TIM2/TIM3 have independent DMA request generation. These timers are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors. TIM21 and TIM22 TIM21 and TIM22 are based on a 16-bit auto-reload up/down counter. They include a 16-bit prescaler. They have two independent channels for input capture/output compare, PWM or one-pulse mode output. They can work together and be synchronized with the TIM2/TIM3, full-featured general-purpose timers. They can also be used as simple time bases and be clocked by the LSE clock source (32.768 kHz) to provide time bases independent from the main CPU clock. DS10690 Rev 7 29/148 33 Functional overview 3.14.2 STM32L071xx Low-power Timer (LPTIM) The low-power timer has an independent clock and is running also in Stop mode if it is clocked by LSE, LSI or an external clock. It is able to wakeup the devices from Stop mode. This low-power timer supports the following features: 3.14.3 * 16-bit up counter with 16-bit autoreload register * 16-bit compare register * Configurable output: pulse, PWM * Continuous / one shot mode * Selectable software / hardware input trigger * Selectable clock source - Internal clock source: LSE, LSI, HSI or APB clock - External clock source over LPTIM input (working even with no internal clock source running, used by the Pulse Counter Application) * Programmable digital glitch filter * Encoder mode Basic timer (TIM6, TIM7) These timers can be used as a generic 16-bit timebase. 3.14.4 SysTick timer This timer is dedicated to the OS, but could also be used as a standard downcounter. It is based on a 24-bit downcounter with autoreload capability and a programmable clock source. It features a maskable system interrupt generation when the counter reaches `0'. 3.14.5 Independent watchdog (IWDG) The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 37 kHz internal RC and, as it operates independently of the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. It is hardware- or software-configurable through the option bytes. The counter can be frozen in debug mode. 3.14.6 Window watchdog (WWDG) The window watchdog is based on a 7-bit downcounter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. 30/148 DS10690 Rev 7 STM32L071xx Functional overview 3.15 Communication interfaces 3.15.1 I2C bus Up to three I2C interfaces (I2C1 and I2C3) can operate in multimaster or slave modes. Each I2C interface can support Standard mode (Sm, up to 100 kbit/s), Fast mode (Fm, up to 400 kbit/s) and Fast Mode Plus (Fm+, up to 1 Mbit/s) with 20 mA output drive on some I/Os. 7-bit and 10-bit addressing modes, multiple 7-bit slave addresses (2 addresses, 1 with configurable mask) are also supported as well as programmable analog and digital noise filters. Table 10. Comparison of I2C analog and digital filters Analog filter Digital filter Pulse width of suppressed spikes 50 ns Programmable length from 1 to 15 I2C peripheral clocks Benefits Available in Stop mode 1. Extra filtering capability vs. standard requirements. 2. Stable length Drawbacks Variations depending on temperature, voltage, process Wakeup from Stop on address match is not available when digital filter is enabled. In addition, I2C1 and I2C3 provide hardware support for SMBus 2.0 and PMBus 1.1: ARP capability, Host notify protocol, hardware CRC (PEC) generation/verification, timeouts verifications and ALERT protocol management. I2C1/I2C3 also have a clock domain independent from the CPU clock, allowing the I2C1/I2C3 to wake up the MCU from Stop mode on address match. Each I2C interface can be served by the DMA controller. Refer to Table 11 for an overview of I2C interface features. Table 11. STM32L071xx I2C implementation I2C features(1) I2C1 I2C2 I2C3 7-bit addressing mode X X X 10-bit addressing mode X X X Standard mode (up to 100 kbit/s) X X X Fast mode (up to 400 kbit/s) X X X Fast Mode Plus with 20 mA output drive I/Os (up to 1 Mbit/s) X X(2) X Independent clock X - X SMBus X - X Wakeup from STOP X - X 1. X = supported. 2. See Table 15: STM32L071xxx pin definition on page 40 for the list of I/Os that feature Fast Mode Plus capability DS10690 Rev 7 31/148 33 Functional overview 3.15.2 STM32L071xx Universal synchronous/asynchronous receiver transmitter (USART) The four USART interfaces (USART1, USART2, USART4 and USART5) are able to communicate at speeds of up to 4 Mbit/s. They provide hardware management of the CTS, RTS and RS485 driver enable (DE) signals, multiprocessor communication mode, master synchronous communication and single-wire half-duplex communication mode. USART1 and USART2 also support SmartCard communication (ISO 7816), IrDA SIR ENDEC, LIN Master/Slave capability, auto baud rate feature and has a clock domain independent from the CPU clock, allowing to wake up the MCU from Stop mode using baudrates up to 42 Kbaud. All USART interfaces can be served by the DMA controller. Table 12 for the supported modes and features of USART interfaces. Table 12. USART implementation USART modes/features(1) USART1 and USART2 USART4 and USART5 Hardware flow control for modem X X Continuous communication using DMA X X Multiprocessor communication X X X X Smartcard mode X - Single-wire half-duplex communication X X IrDA SIR ENDEC block X - LIN mode X - Dual clock domain and wakeup from Stop mode X - Receiver timeout interrupt X - Modbus communication X - Auto baud rate detection (4 modes) X - Driver Enable X X Synchronous mode(2) 1. X = supported. 2. This mode allows using the USART as an SPI master. 3.15.3 Low-power universal asynchronous receiver transmitter (LPUART) The devices embed one Low-power UART. The LPUART supports asynchronous serial communication with minimum power consumption. It supports half duplex single wire communication and modem operations (CTS/RTS). It allows multiprocessor communication. The LPUART has a clock domain independent from the CPU clock. It can wake up the system from Stop mode using baudrates up to 46 Kbaud. The Wakeup events from Stop mode are programmable and can be: 32/148 * Start bit detection * Or any received data frame * Or a specific programmed data frame DS10690 Rev 7 STM32L071xx Functional overview Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to 9600 baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame while having an extremely low energy consumption. Higher speed clock can be used to reach higher baudrates. LPUART interface can be served by the DMA controller. 3.15.4 Serial peripheral interface (SPI)/Inter-integrated sound (I2S) Up to two SPIs are able to communicate at up to 16 Mbits/s in slave and master modes in full-duplex and half-duplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC modes. The USARTs with synchronous capability can also be used as SPI master. One standard I2S interfaces (multiplexed with SPI2) is available. It can operate in master or slave mode, and can be configured to operate with a 16-/32-bit resolution as input or output channels. Audio sampling frequencies from 8 kHz up to 192 kHz are supported. When the I2S interfaces is configured in master mode, the master clock can be output to the external DAC/CODEC at 256 times the sampling frequency. The SPIs can be served by the DMA controller. Refer to Table 13 for the differences between SPI1 and SPI2. Table 13. SPI/I2S implementation SPI features(1) SPI1 SPI2 Hardware CRC calculation X X I2S mode - X TI mode X X 1. X = supported. 3.16 Cyclic redundancy check (CRC) calculation unit The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a configurable generator polynomial value and size. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location. 3.17 Serial wire debug port (SW-DP) An Arm SW-DP interface is provided to allow a serial wire debugging tool to be connected to the MCU. DS10690 Rev 7 33/148 33 Pin descriptions 4 STM32L071xx Pin descriptions 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 VDD VSS PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 Figure 3. STM32L071xx LQFP100 pinout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 LQFP100 75 74 73 72 71 70 VDD69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VDDIO2 VSS VDD PA13 PA12 PA 11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 PB13 PB12 PA3 VSS VDD PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VSS VDD 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 PE2 PE3 PE4 PE5 PE6 VDD PC13 PC14-OSC32_IN PC15-OSC32_OUT PH9 PH10 PH0-OSC_IN PH1-OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VREFVREF+ VDDA PA0 PA1 PA2 MSv35459V2 1. The above figure shows the package top view. 2. PA11 and PA12 input/outputs (greyed out pins) are supplied by VDDIO2. 34/148 DS10690 Rev 7 STM32L071xx Pin descriptions Figure 4. STM32L071xx UFBGA100 ballout 5 2 A PE3 PE1 B PE4 PE2 PB9 PB7 PB6 PC13 PE5 PE0 VDD PB5 C D E F G PC14OSC32 PE6 _IN PC15OSC32 VDD _OUT 3 4 1 PB8 BOOT0 PD7 6 7 8 9 10 PD5 PB4 PB3 PA15 PA14 PA13 PA12 PD6 PD4 PD3 PD1 PC12 PC10 PA11 PD2 PD0 PC11 VDD PA10 PA9 PA8 PC9 PC8 PC7 PC6 VSS VSS VDD IO2 VDD VSS VSS PH0PH9 OSC_IN PH1OSC_ PH10 OUT 11 12 NRST VDD PD15 PD14 PD13 PC1 PC2 PD12 PD11 PD10 VREF - PC3 PA2 PA5 PC4 PB15 PB14 PB13 L VREF + PA0 PA3 PA6 PC5 PB2 PE8 PE10 PE12 PB10 PB11 M VDDA PA1 PA4 PB0 PB1 PE7 PE9 PE11 PE13 PE14 H PC0 J VSSA K PA7 PD9 PD8 PB12 PE15 MSv35460V2 1. The above figure shows the package top view. 2. PA11 and PA12 input/outputs (greyed out pins) are supplied by VDDIO2. VDD VSS PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD2 PC12 PC11 PC10 PA15 PA14 Figure 5. STM32L071xx LQFP64 pinout 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 47 2 46 3 45 4 44 5 43 6 42 7 41 8 LQFP64 40 9 39 10 38 11 37 12 36 13 35 14 34 15 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VDDIO2 VSS PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 PB15 PB14 PB13 PB12 PA3 VSS VDD PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PB10 PB11 VSS VDD VDD PC13 PC14-OSC32_IN PC15-OSC32_OUT PH0-OSC_IN PH1-OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VDDA PA0 PA1 PA2 MSv35457V3 1. The above figure shows the package top view. 2. PA11 and PA12 input/outputs (greyed out pins) are supplied by VDDIO2. DS10690 Rev 7 35/148 54 Pin descriptions STM32L071xx Figure 6. STM32L071xx UFBGA64/TFBGA64 ballout 1 2 3 4 5 A PC14OSC32 _IN PC13 PB9 PB4 PB3 B PC15OSC32 _OUT VDD PB8 BOOT 0 PH0OSC_IN VSS PB7 D PH1OSC_ OUT VDD E NRST F VSSA C 6 7 8 PA15 PA14 PA13 PD2 PC11 PC10 PA12 PB5 PC12 PA10 PA9 PA11 PB6 VSS VSS VSS PA8 PC9 PC1 PC0 VDD VDD VDD IO2 PC7 PC8 PC2 PA2 PA5 PB0 PC6 PB15 PB14 G VREF + PA0 PA3 PA6 PB1 PB2 PB10 PB13 H VDDA PA1 PA4 PA7 PC4 PC5 PB11 PB12 MSv35458V2 1. The above figure shows the package top view. 2. PA11 and PA12 input/outputs (greyed out pins) are supplied by VDDIO2. 36/148 DS10690 Rev 7 STM32L071xx Pin descriptions Figure 7. STM32L071xx WLCSP49 ballout 1 2 3 4 5 6 7 A VDD IO2 PA15 PB3 PB5 BOOT0 PB9 VDD B PA12 PA14 PB4 PB6 PB8 VDD PC13 C PA10 PA13 PB7 PC1 PC0 D PA8 PA11 PB1 VSS E PB15 PA9 PB2 F PB14 PB13 G PB12 VDD PC14OSC32 _IN PC15OSC32 _OUT NRST PH0OSC_IN PH1OSC_ OUT PA1 PA0 VREF+ PC2 PB11 PA7 PA4 PA2 VDDA PB10 PB0 PA6 PA5 PA3 MSv36157V3 1. The above figure shows the package top view. 2. PA11 and PA12 input/outputs (greyed out pins) are supplied by VDDIO2. DS10690 Rev 7 37/148 54 Pin descriptions STM32L071xx VDD VSS PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PA15 PA14 Figure 8. STM32L071xx LQFP48 pinout 48 47 46 45 44 43 42 41 40 39 38 37 36 1 2 35 34 3 33 4 32 5 31 6 LQFP48 30 7 29 8 28 9 27 10 26 11 25 12 13 14 15 16 17 18 19 20 21 22 23 24 VDDIO2 VSS PA13 PA12 PA11 PA10 PA9 PA8 PB15 PB14 PB13 PB12 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB10 PB11 VSS VDD VDD PC13 PC14-OSC32_IN PC15-OSC32_OUT PH0-OSC_IN PH1-OSC_OUT NRST VSSA VDDA PA0 PA1 PA2 MS34745V2 1. The above figure shows the package top view. 2. PA11 and PA12 input/outputs (greyed out pins) are supplied by VDDIO2. VDD VSS PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PA15 PA14 48 47 46 45 44 43 42 41 40 39 38 37 Figure 9. STM32L071xx UFQFPN48 VDD 1 36 VDDIO2 PC13 2 35 VSS PC14-OSC32_IN 3 34 PA13 PC15-OSC32_OUT 4 33 PA12 PH0-OSC_IN 5 32 PA11 PH1-OSC_OUT 6 31 PA10 NRST 7 30 PA9 VSSA 8 29 PA8 VDDA 9 28 PB15 PA0 10 27 PB14 PA1 11 26 PB13 PA2 12 25 PB12 13 14 15 16 17 18 19 20 21 22 23 24 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB10 PB11 VSS VDD UFQFPN48 MSv62416V1 1. The above figure shows the package top view. 2. PA11 and PA12 input/outputs (greyed out pins) are supplied by VDDIO2. 38/148 DS10690 Rev 7 STM32L071xx Pin descriptions VDD PC14-OSC32_IN PC15-OSC32_OUT 32 31 30 29 28 27 26 25 1 24 2 23 22 3 21 4 LQFP32 20 5 19 6 18 7 8 9 10 11 12 1 3 14 15 1617 PA14 PA13 PA12 PA11 PA10 PA9 PA8 VDD PA3 PA4 PA5 PA6 PA7 PB0 PB1 VSS NRST VDDA PA0 PA1 PA2 PB7 PB6 PB5 PB4 PB3 PA15 VSS BOOT0 Figure 10. STM32L071xx LQFP32 pinout MSv35429V3 1. The above figure shows the package top view. 32 31 30 29 28 27 26 25 24 1 23 2 22 3 4 VSS 21 5 20 6 19 18 7 8 9 10 11 12 13 14 15 1617 VDDIO2 PA13 PA12 PA11 PA10 PA9 PA8 VDD PA3 PA4 PA5 PA6 PA7 PB0 PB1 VSS PC14-OSC32_IN PC15-OSC32_OUT NRST VSSA VDDA PA0 PA1 PA2 BOOT0 PB7 PB6 PB5 PB4 PA14 VDD VSS Figure 11. STM32L071xx UFQFPN32 pinout MSv35461V3 1. The above figure shows the package top view. 2. PA11 and PA12 input/outputs (greyed out pins) are supplied by VDDIO2. DS10690 Rev 7 39/148 54 Pin descriptions STM32L071xx Table 14. Legend/abbreviations used in the pinout table Name Abbreviation Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name Pin name Pin type I/O structure S Supply pin I Input only pin I/O Input / output pin FT 5 V tolerant I/O FTf 5 V tolerant I/O, FM+ capable TC Standard 3.3V I/O B Dedicated BOOT0 pin RST Bidirectional reset pin with embedded weak pull-up resistor Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset. Notes Pin functions Definition Alternate functions Functions selected through GPIOx_AFR registers Additional functions Functions directly selected/enabled through peripheral registers Table 15. STM32L071xxx pin definition LQFP32 UFQFPN32(1) LQFP48 UFQFPN48 LQFP64 UFBGA/TFBGA64 WLCSP49 LQFP100 UFBG100 Pin type I/O structure Note Pin number Alternate functions - - - - - - - 1 B2 PE2 I/O FT - TIM3_ETR - - - - - - - - 2 A1 PE3 I/O FT - TIM22_CH1, TIM3_CH1 - - - - - - - - 3 B1 PE4 I/O FT - TIM22_CH2, TIM3_CH2 - - - - - - - - 4 C2 PE5 I/O FT - TIM21_CH1, TIM3_CH3 - - - - - - - - 5 D2 PE6 I/O FT - TIM21_CH2, TIM3_CH4 RTC_TAMP3/ WKUP3 1 - 1 1 1 6 E2 VDD S - - - - 40/148 B2 B6 Pin name (function after reset) DS10690 Rev 7 Additional functions STM32L071xx Pin descriptions Table 15. STM32L071xxx pin definition (continued) Note I/O structure Pin name (function after reset) Pin type UFBG100 LQFP100 WLCSP49 UFBGA/TFBGA64 LQFP64 UFQFPN48 LQFP48 UFQFPN32(1) LQFP32 Pin number Alternate functions Additional functions - - 2 2 2 A2 B7 7 C1 PC13 I/O FT - - RTC_TAMP1/ RTC_TS/ RTC_OUT/ WKUP2 2 1 3 3 3 A1 C6 8 D1 PC14OSC32_IN (PC14) I/O FT - - OSC32_IN 3 2 4 4 4 B1 C7 9 E1 PC15OSC32_OUT I/O TC (PC15) - - OSC32_OUT - - - - - - - 10 F2 PH9 I/O FT - - - - - - - - - - 11 G2 PH10 I/O FT - - - - - 5 5 5 C1 D6 12 F1 PH0-OSC_IN I/O TC (PH0) - - OSC_IN - - 6 6 6 D1 D7 13 G1 PH1OSC_OUT (PH1) I/O TC - - OSC_OUT 4 3 7 7 7 E1 D5 14 H2 NRST I/O - - - - LPTIM1_IN1, EVENTOUT, LPUART1_RX, I2C3_SCL ADC_IN10 ADC_IN11 - - - - 8 E3 C5 15 H1 PC0 - I/O FTf - - - - 9 E2 C4 16 J2 PC1 I/O FTf - LPTIM1_OUT, EVENTOUT, LPUART1_TX, I2C3_SDA - - - - 10 F2 E7 17 J3 PC2 I/O FTf - LPTIM1_IN2, SPI2_MISO/I2S2_ MCK ADC_IN12 - - - - 11 - - 18 K2 PC3 I/O FT - LPTIM1_ETR, SPI2_MOSI/I2S2_ SD ADC_IN13 - 4 8 8 12 F1 - 19 J1 VSSA S - - - - - - - - - - - 20 K1 VREF- S - - - - DS10690 Rev 7 41/148 54 Pin descriptions STM32L071xx Table 15. STM32L071xxx pin definition (continued) LQFP32 UFQFPN32(1) LQFP48 UFQFPN48 LQFP64 WLCSP49 LQFP100 UFBG100 Pin type I/O structure Note UFBGA/TFBGA64 Pin number Alternate functions - - - - - G1 E6 21 L1 VREF+ S - - - - 5 5 9 9 13 H1 F7 22 M1 VDDA S - - - - - TIM2_CH1, USART2_CTS, TIM2_ETR, USART4_TX, COMP1_OUT COMP1_INM, ADC_IN0, RTC_TAMP2/ WKUP1 - EVENTOUT, TIM2_CH2, USART2_RTS/ USART2_DE, TIM21_ETR, USART4_RX COMP1_INP, ADC_IN1 - TIM21_CH1, TIM2_CH3, USART2_TX, LPUART1_TX, COMP2_OUT COMP2_INM, ADC_IN2 COMP2_INP, ADC_IN3 6 7 8 6 7 8 10 10 14 11 11 15 12 12 16 9 9 - - - - - - - - G2 E5 H2 E4 F3 F6 23 24 25 L2 M2 K3 Pin name (function after reset) PA0 PA1 PA2 I/O I/O I/O TT a FT FT Additional functions G3 G7 26 L3 PA3 I/O FT - TIM21_CH2, TIM2_CH4, USART2_RX, LPUART1_RX 18 C2 - 27 D3 VSS S - - - - 19 D2 - 28 H3 VDD S - - - - 13 13 17 10 10 14 14 20 H3 F5 29 M3 PA4 I/O TC - SPI1_NSS, USART2_CK, TIM22_ETR COMP1_INM, COMP2_INM, ADC_IN4 11 11 F4 G6 30 K4 PA5 I/O TC - SPI1_SCK, TIM2_ETR, TIM2_CH1 COMP1_INM, COMP2_INM, ADC_IN5 42/148 15 15 21 DS10690 Rev 7 STM32L071xx Pin descriptions Table 15. STM32L071xxx pin definition (continued) 13 13 17 17 23 31 L4 PA6 I/O I/O structure Pin type UFBG100 LQFP100 WLCSP49 G4 G5 Pin name (function after reset) FT Note 12 12 16 16 22 UFBGA/TFBGA64 LQFP64 UFQFPN48 LQFP48 UFQFPN32(1) LQFP32 Pin number Alternate functions Additional functions - SPI1_MISO, TIM3_CH1, LPUART1_CTS, TIM22_CH1, EVENTOUT, COMP1_OUT ADC_IN6 ADC_IN7 H4 F4 32 M4 PA7 I/O FT - SPI1_MOSI, TIM3_CH2, TIM22_CH2, EVENTOUT, COMP2_OUT - - - - 24 H5 - 33 K5 PC4 I/O FT - EVENTOUT, LPUART1_TX ADC_IN14 - - - - 25 H6 - 34 L5 PC5 I/O FT - LPUART1_RX ADC_IN15 14 14 18 18 26 F5 G4 35 M5 PB0 I/O FT - EVENTOUT, TIM3_CH3 ADC_IN8, VREF_OUT 15 15 19 19 27 G5 D3 36 M6 PB1 I/O FT - TIM3_CH4, LPUART1_RTS/ LPUART1_DE ADC_IN9, VREF_OUT G6 E3 37 L6 PB2 I/O FT - LPTIM1_OUT, I2C3_SMBA - - - 20 20 28 - - - - - - - 38 M7 PE7 I/O FT - USART5_CK, USART5_RTS/ USART5_DE - - - - - - - - 39 L7 PE8 I/O FT - USART4_TX - - - - - - - - 40 M8 PE9 I/O FT - TIM2_CH1, TIM2_ETR, USART4_RX - - - - - - - - 41 L8 PE10 I/O FT - TIM2_CH2, USART5_TX - - - - - - - - 42 M9 PE11 I/O FT - TIM2_CH3, USART5_RX - - - - - - - - 43 L9 PE12 I/O FT - TIM2_CH4, SPI1_NSS - DS10690 Rev 7 43/148 54 Pin descriptions STM32L071xx Table 15. STM32L071xxx pin definition (continued) LQFP32 UFQFPN32(1) LQFP48 UFQFPN48 LQFP64 UFBGA/TFBGA64 WLCSP49 LQFP100 UFBG100 Pin type I/O structure Note Pin number Alternate functions - - - - - - - 44 M10 PE13 I/O FT - SPI1_SCK - - - - - - - - 45 M11 PE14 I/O FT - SPI1_MISO - - - - - - - - 46 M12 PE15 I/O FT - SPI1_MOSI - - TIM2_CH3, LPUART1_TX, SPI2_SCK, I2C2_SCL, LPUART1_RX - - - - 21 21 29 G7 G3 47 L10 Pin name (function after reset) PB10 I/O FT Additional functions 22 22 30 H7 F3 48 L11 PB11 I/O FT - EVENTOUT, TIM2_CH4, LPUART1_RX, I2C2_SDA, LPUART1_TX 16 16 23 23 31 D6 D4 49 F12 VSS S - - - - 17 17 24 24 32 E5 G2 50 G12 VDD S - - - - - SPI2_NSS/I2S2_ WS, LPUART1_RTS/ LPUART1_DE, I2C2_SMBA, EVENTOUT - - SPI2_SCK/I2S2_ CK, MCO, LPUART1_CTS, I2C2_SCL, TIM21_CH1 - - - - - - - - 25 25 33 26 26 34 H8 G1 G8 F2 51 52 L12 K12 PB12 PB13 I/O FT I/O FTf - - 27 27 35 F8 F1 53 K11 PB14 I/O FTf - SPI2_MISO/I2S2_ MCK, RTC_OUT, LPUART1_RTS/ LPUART1_DE, I2C2_SDA, TIM21_CH2 - - 28 28 36 F7 E1 54 K10 PB15 I/O FT - SPI2_MOSI/I2S2_ SD, RTC_REFIN - - - 55 K9 PD8 I/O FT - LPUART1_TX - 44/148 - - - - - DS10690 Rev 7 STM32L071xx Pin descriptions Table 15. STM32L071xxx pin definition (continued) LQFP32 UFQFPN32(1) LQFP48 UFQFPN48 LQFP64 UFBGA/TFBGA64 WLCSP49 LQFP100 UFBG100 Pin type I/O structure Note Pin number Alternate functions - - - - - - - 56 K8 PD9 I/O FT - LPUART1_RX - - - - - - - - 57 J12 PD10 I/O FT - - - - - - - - - - 58 J11 PD11 I/O FT - LPUART1_CTS - - - - - - - - 59 J10 PD12 I/O FT - LPUART1_RTS/ LPUART1_DE - - - - - - - - 60 H12 PD13 I/O FT - - - - - - - - - - 61 H11 PD14 I/O FT - - - - - - - - - - 62 H10 PD15 I/O FT - - - - - - - 37 F6 - 63 E12 PC6 I/O FT - TIM22_CH1, TIM3_CH1 - - - - - 38 E7 - 64 E11 PC7 I/O FT - TIM22_CH2, TIM3_CH2 - - - - - 39 E8 - 65 E10 PC8 I/O FT - TIM22_ETR, TIM3_CH3 - - - - - 40 D8 - 66 D12 PC9 I/O FTf - TIM21_ETR, TIM3_CH4, I2C3_SDA - 67 D11 PA8 I/O FTf - MCO, EVENTOUT, USART1_CK, I2C3_SCL - - 18 18 29 29 41 D7 D1 Pin name (function after reset) Additional functions 19 19 30 30 42 C7 E2 68 D10 PA9 I/O FTf - MCO, USART1_TX, I2C1_SCL, I2C3_SMBA 20 20 31 31 43 C6 C1 69 C12 PA10 I/O FTf - USART1_RX, I2C1_SDA - - SPI1_MISO, EVENTOUT, USART1_CTS, COMP1_OUT - 21 21 32 32 44 C8 D2 70 B12 PA11 I/O DS10690 Rev 7 FT 45/148 54 Pin descriptions STM32L071xx Table 15. STM32L071xxx pin definition (continued) PA12 I/O FT - 23 23 34 34 46 A8 C2 72 A11 PA13 I/O FT - SWDIO, LPUART1_RX - - - - - - - - - 35 35 47 UFBG100 A12 LQFP100 71 WLCSP49 B8 B1 LQFP64 22 22 33 33 45 SPI1_MOSI, EVENTOUT, USART1_RTS/ USART1_DE, COMP2_OUT LQFP48 Alternate functions LQFP32 Note I/O structure Pin name (function after reset) Pin type UFBGA/TFBGA64 UFQFPN48 UFQFPN32(1) Pin number Additional functions - - - 73 C11 VDD S - - - - D5 - 74 F11 VSS S - - - - 24 36 36 48 E6 A1 75 G11 VDDIO2 S - - - - 24 25 37 37 49 A7 B2 76 A10 PA14 I/O FT - SWCLK, USART2_TX, LPUART1_TX - - A6 A2 77 A9 PA15 I/O FT - SPI1_NSS, TIM2_ETR, EVENTOUT, USART2_RX, TIM2_CH1, USART4_RTS/ USART4_DE 51 B7 - 78 B11 PC10 I/O FT - LPUART1_TX, USART4_TX - - 52 B6 - 79 C10 PC11 I/O FT - LPUART1_RX, USART4_RX - - - 53 C5 - 80 B10 PC12 I/O FT - USART5_TX, USART4_CK - - - - - - - 81 C9 PD0 I/O FT - TIM21_CH1, SPI2_NSS/I2S2_W S - - - - - - - 82 B9 PD1 I/O FT - SPI2_SCK/I2S2_C K - 25 - - - - - - - - - - - - 46/148 38 38 50 DS10690 Rev 7 STM32L071xx Pin descriptions Table 15. STM32L071xxx pin definition (continued) 54 B5 - 83 C8 PD2 I/O FT - - - - - - - - 84 B8 PD3 I/O FT - USART2_CTS, SPI2_MISO/I2S2_ MCK - - UFBG100 - LQFP100 - WLCSP49 - LQFP64 - LPUART1_RTS/ LPUART1_DE, TIM3_ETR, USART5_RX LQFP48 Alternate functions LQFP32 Note I/O structure Pin name (function after reset) Pin type UFBGA/TFBGA64 UFQFPN48 UFQFPN32(1) Pin number Additional functions - - - - - - - - 85 B7 PD4 I/O FT - USART2_RTS/ USART2_DE, SPI2_MOSI/I2S2_S D - - - - - - - 86 A6 PD5 I/O FT - USART2_TX - - - - - - - - 87 B6 PD6 I/O FT - USART2_RX - - - - - - - - 88 A5 PD7 I/O FT - USART2_CK, TIM21_CH2 - - SPI1_SCK, TIM2_CH2, EVENTOUT, USART1_RTS/ USART1_DE, USART5_TX COMP2_INM - SPI1_MISO, TIM3_CH1, TIM22_CH1, USART1_CTS, USART5_RX, I2C3_SDA COMP2_INP - SPI1_MOSI, LPTIM1_IN1, I2C1_SMBA, TIM3_CH2/TIM22_ CH2, USART1_CK, USART5_CK, USART5_RTS/ USART5_DE COMP2_INP 26 - 39 39 55 27 26 40 40 56 28 27 41 41 57 A5 A3 A4 B3 C4 A4 89 90 91 A8 A7 C5 PB3 PB4 PB5 I/O FT I/O FTf I/O DS10690 Rev 7 FT 47/148 54 Pin descriptions STM32L071xx Table 15. STM32L071xxx pin definition (continued) B5 PB6 30 29 43 43 59 C3 C3 93 B4 PB7 31 30 44 44 60 B4 A5 94 A4 BOOT0 B3 B5 95 A3 PB8 - - 45 45 61 46 46 62 - I/O FTf - USART1_TX, I2C1_SCL, LPTIM1_ETR, COMP2_INP - USART1_RX, I2C1_SDA, LPTIM1_IN2, USART4_CTS COMP2_INP, VREF_PVD_IN - - - - I2C1_SCL - - B3 PB9 I/O FTf - - 97 C3 PE0 I/O FT - EVENTOUT - - - 98 A2 PE1 I/O FT - EVENTOUT - D4 - 99 D3 VSS S - - - - E4 A7 100 C4 VDD S - - - - - - - - - - - - - - - 32 48 48 64 I Additional functions 96 - - I/O FTf Alternate functions EVENTOUT, I2C1_SDA, SPI2_NSS/I2S2_W S - 32 31 47 47 63 I/O FTf Note UFBG100 92 I/O structure LQFP100 D3 B4 Pin name (function after reset) Pin type WLCSP49 29 28 42 42 58 UFBGA/TFBGA64 LQFP64 UFQFPN48 LQFP48 UFQFPN32(1) LQFP32 Pin number A3 A6 1. UFQFPN32 pinout differs from other STM32 devices except STM32L07xxx and STM32L8xxx. 48/148 DS10690 Rev 7 AF0 Port DS10690 Rev 7 Port A AF1 AF2 SPI1/SPI2/I2S2/ SPI1/SPI2/I2S2/ USART1/2/ LPUART1/ LPUART1/LPTI SPI1/SPI2/I2S2/ USART5/LPTIM M1/ I2C1/TIM2/21 1/TIM2/3/EVEN TIM2/21/22/ TOUT/ EVENTOUT/ SYS_AF SYS_AF PA0 - PA1 - AF3 I2C1/ EVENTOUT AF4 AF5 AF6 AF7 I2C1/2/ I2C1/USART1/2 LPUART1/ SPI2/I2S2/I2C2/ I2C3/LPUART1/ /LPUART1/ USART4/ USART1/ COMP1/2/ TIM3/22/ UASRT5/TIM21 TIM2/21/22 TIM3 EVENTOUT / EVENTOUT USART2_CTS TIM2_ETR USART4_TX COMP1_OUT EVENTOUT TIM2_CH2 USART2_RTS/ USART2_DE TIM21_ETR USART4_RX - PA2 TIM21_CH1 TIM2_CH3 USART2_TX - LPUART1_TX COMP2_OUT PA3 TIM21_CH2 TIM2_CH4 USART2_RX - LPUART1_RX - PA4 SPI1_NSS - - USART2_CK TIM22_ETR - - PA5 SPI1_SCK - TIM2_ETR TIM2_CH1 - - PA6 SPI1_MISO TIM3_CH1 LPUART1_CTS TIM22_CH1 EVENTOUT COMP1_OUT PA7 SPI1_MOSI TIM3_CH2 - TIM22_CH2 EVENTOUT COMP2_OUT PA8 MCO USART1_CK - - I2C3_SCL PA9 MCO - USART1_TX - I2C1_SCL I2C3_SMBA PA10 - - USART1_RX - I2C1_SDA - PA11 SPI1_MISO - EVENTOUT USART1_CTS - - COMP1_OUT PA12 SPI1_MOSI - EVENTOUT USART1_RTS/ USART1_DE - - COMP2_OUT PA13 SWDIO - - - - LPUART1_RX - PA14 SWCLK - - - USART2_TX - LPUART1_TX - PA15 SPI1_NSS TIM2_ETR EVENTOUT USART2_RX TIM2_CH1 USART4_RTS/ USART4_DE - EVENTOUT 49/148 Pin descriptions TIM2_CH1 STM32L071xx Table 16. Alternate functions port A AF0 Port DS10690 Rev 7 Port B SPI1/SPI2/I2S2/ USART1/2/ LPUART1/ LPTIM1/ TIM2/21/22/ EVENTOUT/ SYS_AF AF1 AF2 SPI1/SPI2/I2S2/ LPUART1/ SPI1/SPI2/I2S2/I USART5/LPTIM 1/TIM2/3/EVENT 2C1/TIM2/21 OUT/ SYS_AF AF3 AF4 AF5 AF6 AF7 I2C1/ EVENTOUT I2C1/USART1/2/ LPUART1/ TIM3/22/ EVENTOUT SPI2/I2S2/I2C2/ USART1/ TIM2/21/22 I2C1/2/ LPUART1/ USART4/ UASRT5/TIM21/ EVENTOUT I2C3/LPUART1/ COMP1/2/ TIM3 EVENTOUT TIM3_CH3 - - - - PB1 - TIM3_CH4 LPUART1_RTS/ LPUART1_DE - - - PB2 - LPTIM1_OUT - - - I2C3_SMBA PB3 SPI1_SCK TIM2_CH2 EVENTOUT USART1_RTS/ USART1_DE USART5_TX - PB4 SPI1_MISO TIM3_CH1 TIM22_CH1 USART1_CTS USART5_RX I2C3_SDA PB5 SPI1_MOSI LPTIM1_IN1 TIM3_CH2/ TIM22_CH2 USART1_CK USART5_CK, USART5_RTS/ USART5_DE - PB6 USART1_TX I2C1_SCL LPTIM1_ETR - - - - PB7 USART1_RX I2C1_SDA LPTIM1_IN2 - - USART4_CTS - PB8 - - I2C1_SCL - - - PB9 - EVENTOUT I2C1_SDA SPI2_NSS/ I2S2_WS - - PB10 - TIM2_CH3 LPUART1_TX SPI2_SCK I2C2_SCL LPUART1_RX PB11 EVENTOUT TIM2_CH4 LPUART1_RX - I2C2_SDA LPUART1_TX PB12 SPI2_NSS/I2S2_WS LPUART1_RTS/ LPUART1_DE I2C2_SMBA EVENTOUT - PB13 SPI2_SCK/I2S2_CK MCO LPUART1_CTS I2C2_SCL TIM21_CH1 - PB14 SPI2_MISO/ I2S2_MCK RTC_OUT LPUART1_RTS/ LPUART1_DE I2C2_SDA TIM21_CH2 - PB15 SPI2_MOSI/ I2S2_SD RTC_REFIN - - - - - I2C1_SMBA - - STM32L071xx PB0 Pin descriptions 50/148 Table 17. Alternate functions port B AF0 Port SPI1/SPI2/I2S2/ USART1/2/ LPUART1/ LPTIM1/ TIM2/21/22/ EVENTOUT/ SYS_AF AF2 SPI1/SPI2/I2S2/I2C1/ TIM2/21 SPI1/SPI2/I2S2/ LPUART1/ USART5/ LPTIM1/TIM2/3 /EVENTOUT/SYS_AF AF3 AF4 AF5 AF6 AF7 I2C1/ EVENTOUT I2C1/USART1/2/ LPUART1/ TIM3/22/ EVENTOUT SPI2/I2S2 /I2C2/ USART1/ TIM2/21/22 I2C1/2/ LPUART1/ USART4/ UASRT5/TIM21/E VENTOUT I2C3/LPUART1/ COMP1/2/ TIM3 DS10690 Rev 7 PC0 LPTIM1_IN1 EVENTOUT LPUART1_RX I2C3_SCL PC1 LPTIM1_OUT EVENTOUT LPUART1_TX I2C3_SDA PC2 LPTIM1_IN2 SPI2_MISO/ I2S2_MCK PC3 LPTIM1_ETR SPI2_MOSI/ I2S2_SD PC4 EVENTOUT LPUART1_TX PC5 Port C AF1 LPUART1_RX PC6 TIM22_CH1 TIM3_CH1 PC7 TIM22_CH2 TIM3_CH2 PC8 TIM22_ETR TIM3_CH3 PC9 TIM21_ETR TIM3_CH4 PC10 LPUART1_TX USART4_TX PC11 LPUART1_RX USART4_RX PC12 STM32L071xx Table 18. Alternate functions port C USART5_TX I2C3_SDA USART4_CK PC13 PC14 51/148 Pin descriptions PC15 AF0 AF1 AF2 AF4 AF5 AF6 AF7 SPI1/SPI2/I2S2/ USART1/2/ LPUART1/ LPTIM1/ TIM2/21/22/ EVENTOUT/ SYS_AF SPI1/SPI2/I2S2/I2C1/ TIM2/21 SPI1/SPI2/I2S2/ LPUART1/ USART5/ LPTIM1/TIM2/3 /EVENTOUT/ SYS_AF I2C1/ EVENTOUT I2C1/USART1/2/ LPUART1/ TIM3/22/ EVENTOUT SPI2/I2S2 /I2C2/ USART1/ TIM2/21/22 I2C1/2/ LPUART1/ USART4/ UASRT5/TIM21/E VENTOUT I2C3/LPUART1/ COMP1/2/TIM3 PD0 TIM21_CH1 SPI2_NSS/I2S2_WS - - - - - - PD1 - SPI2_SCK/I2S2_CK - - - - - - PD2 LPUART1_RTS/ LPUART1_DE TIM3_ETR - - - USART5_RX - PD3 USART2_CTS SPI2_MISO/ I2S2_MCK - - - - - PD4 USART2_RTS/ USART2_DE SPI2_MOSI/I2S2_SD - - - - - - PD5 USART2_TX - - - - - - - PD6 USART2_RX - - - - - - - PD7 USART2_CK TIM21_CH2 - - - - - - PD8 LPUART1_TX - - - - - - PD9 LPUART1_RX - - - - - - PD10 - - - - - - - PD11 LPUART1_CTS - - - - - - PD12 LPUART1_RTS/ LPUART1_DE - - - - - - PD13 - - - - - - - PD14 - - - - - - - - - - - - - DS10690 Rev 7 Port D Port PD15 STM32L071xx AF3 Pin descriptions 52/148 Table 19. Alternate functions port D AF0 DS10690 Rev 7 Port E Port SPI1/SPI2/I2S2/ USART1/2/ LPUART1/LPTI M1/ TIM2/21/22/ EVENTOUT/ SYS_AF AF1 AF2 AF3 AF4 AF5 AF6 AF7 SPI1/SPI2/I2S2/ LPUART1/ USART5/ LPTIM1/TIM2/3 /EVENTOUT/ SYS_AF I2C1/ EVENTOUT I2C1/USART1/2/ LPUART1/ TIM3/22/ EVENTOUT SPI2/I2S2 /I2C2/ USART1/ TIM2/21/22 I2C1/2/ LPUART1/ USART4/ UASRT5/TIM21/ EVENTOUT SPI1/SPI2/I2S2/I2C1 /TIM2/21 I2C3/LPUART1/ COMP1/2/TIM3 - EVENTOUT - - - - - PE1 - EVENTOUT - - - - - PE2 - TIM3_ETR - - - - - PE3 TIM22_CH1 TIM3_CH1 - - - - - PE4 TIM22_CH2 - TIM3_CH2 - - - - - PE5 TIM21_CH1 - TIM3_CH3 - - - - - PE6 TIM21_CH2 - TIM3_CH4 - - - - - PE7 - - - - - USART5_CK, USART5_RTS/ USART5_DE - PE8 - - - - - USART4_TX - PE9 TIM2_CH1 TIM2_ETR - - - USART4_RX - PE10 TIM2_CH2 - - - - USART5_TX - PE11 TIM2_CH3 - - - - - USART5_RX - PE12 TIM2_CH4 - SPI1_NSS - - - - - PE13 - SPI1_SCK - - - - - PE14 - SPI1_MISO - - - - - PE15 - SPI1_MOSI - - - - - 53/148 Pin descriptions PE0 STM32L071xx Table 20. Alternate functions port E AF0 Port H Port SPI1/SPI2/ I2S2/USART1/2/ LPUART1/ LPTIM1/ TIM2/21/22/ EVENTOUT/ SYS_AF PH0 PH1 - AF1 AF2 AF3 AF4 AF5 AF6 AF7 SPI1/SPI2/I2S2 /I2C1/TIM2/21 SPI1/SPI2/I2S2/ LPUART1/ USART5/ LPTIM1/TIM2/3/ EVENTOUT/ SYS_AF I2C1/ EVENTOUT I2C1/USART1/2/ LPUART1/ TIM3/22/ EVENTOUT SPI2/I2S2/I2C2/ USART1/ TIM2/21/22 I2C1/2/ LPUART1/ USART4/ UASRT5/TIM21/ EVENTOUT I2C3/ LPUART1/ COMP1/2/ TIM3 - - - - - - - - - - - - - - Pin descriptions 54/148 Table 21. Alternate functions port H DS10690 Rev 7 STM32L071xx STM32L071xx 5 Memory mapping Memory mapping Refer to the product line reference manual for details on the memory mapping as well as the boundary addresses for all peripherals. DS10690 Rev 7 55/148 55 Electrical characteristics STM32L071xx 6 Electrical characteristics 6.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 6.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 C and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3). 6.1.2 Typical values Unless otherwise specified, typical data are based on TA = 25 C, VDD = 3.6 V (for the 1.65 V VDD 3.6 V voltage range). They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2). 6.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 6.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 12. 6.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 13. Figure 12. Pin loading conditions Figure 13. Pin input voltage MCU pin MCU pin C = 50 pF VIN ai17851c 56/148 DS10690 Rev 7 ai17852c STM32L071xx 6.1.6 Electrical characteristics Power supply scheme Figure 14. Power supply scheme OUT GP I/Os IN Level shifter Standby-power circuitry (OSC32,RTC,Wake-up logic, RTC backup registers) IO Logic Kernel logic (CPU, Digital & Memories) VDD VDD Regulator N x 100 nF + 1 x 10 F VSS VDDA VDDA VREF 100 nF + 1 F 100 nF + 1 F VREF+ VREF- ADC Analog: RC,PLL,COMP, .... VSSA MSv34740V1 6.1.7 Current consumption measurement Figure 15. Current consumption measurement scheme VDDA IDD NxVDD N x 100 nF + 1 x 10 F NxVSS MSv34711V1 DS10690 Rev 7 57/148 112 Electrical characteristics 6.2 STM32L071xx Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 22: Voltage characteristics, Table 23: Current characteristics, and Table 24: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Device mission profile (application conditions) is compliant with JEDEC JESD47 Qualification Standard. Extended mission profiles are available on demand. Table 22. Voltage characteristics Symbol VDD-VSS VIN(2) Definition Min Max External main supply voltage (including VDDA, VDDIO2 VDD)(1) -0.3 4.0 Input voltage on FT and FTf pins VSS -0.3 VDD+4.0 Input voltage on TC pins VSS -0.3 4.0 Input voltage on BOOT0 VSS VDD + 4.0 VSS - 0.3 4.0 Input voltage on any other pin |VDD| Variations between different VDDx power pins - 50 |VDDA-VDDx| Variations between any VDDx and VDDA power pins(3) - 300 Variations between all different ground pins including VREF- pin - 50 - 0.4 |VSS| VREF+ -VDDA Allowed voltage difference for VREF+ > VDDA VESD(HBM) Electrostatic discharge voltage (human body model) Unit V mV V see Section 6.3.11 1. All main power (VDD,, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. VIN maximum must always be respected. Refer to Table 23 for maximum allowed injected current values. 3. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV between VDD and VDDA can be tolerated during power-up and device operation. VDDIO2 is independent from VDD and VDDA: its value does not need to respect this rule. 58/148 DS10690 Rev 7 STM32L071xx Electrical characteristics Table 23. Current characteristics Symbol Ratings Max. IVDD(2) Total current into sum of all VDD power lines (source)(1) 105 IVSS(2) (1) Total current out of sum of all VSS ground lines (sink) 105 IVDDIO2 Total current into VDDIO2 power line (source) 25 IVDD(PIN) Maximum current into each VDD power pin (source)(1) IVSS(PIN) IIO IIO(PIN) IINJ(PIN) IINJ(PIN) 100 (1) Maximum current out of each VSS ground pin (sink) 100 Output current sunk by any I/O and control pin except FTf pins 16 Output current sunk by FTf pins 22 Output current sourced by any I/O and control pin -16 Total output current sunk by sum of all IOs and control pins except PA11 and PA12(2) 90 Total output current sunk by PA11 and PA12 25 Total output current sourced by sum of all IOs and control pins(2) -90 Injected current on FT, FTf, RST and B pins Unit mA -5/+0(3) Injected current on TC pin 5(4) Total injected current (sum of all I/O and control pins)(5) 25 1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count LQFP packages. 3. Positive current injection is not possible on these I/Os. A negative injection is induced by VIN<VSS. IINJ(PIN) must never be exceeded. Refer to Table 22 for maximum allowed input voltage values. 4. A positive injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS. IINJ(PIN) must never be exceeded. Refer to Table 22: Voltage characteristics for the maximum allowed input voltage values. 5. When several inputs are submitted to a current injection, the maximum IINJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values). Table 24. Thermal characteristics Symbol TSTG TJ Ratings Storage temperature range Maximum junction temperature DS10690 Rev 7 Value Unit -65 to +150 C 150 C 59/148 112 Electrical characteristics STM32L071xx 6.3 Operating conditions 6.3.1 General operating conditions Table 25. General operating conditions Symbol Parameter Conditions Min Max Unit fHCLK Internal AHB clock frequency - 0 32 fPCLK1 Internal APB1 clock frequency - 0 32 fPCLK2 Internal APB2 clock frequency - 0 32 BOR detector disabled 1.65 3.6 BOR detector enabled, at power-on 1.8 3.6 BOR detector disabled, after power-on 1.65 3.6 Must be the same voltage as VDD(1) 1.65 3.6 V 1.65 3.6 V 2.0 V VDD 3.6 V -0.3 5.5 1.65 V VDD 2.0 V -0.3 5.2 VDD VDDA VDDIO2 Standard operating voltage Analog operating voltage (all features) Standard operating voltage Input voltage on FT, FTf and RST pins(2) VIN 60/148 - Input voltage on BOOT0 pin - 0 5.5 Input voltage on TC pin - -0.3 VDD+0.3 DS10690 Rev 7 MHz V V STM32L071xx Electrical characteristics Table 25. General operating conditions (continued) Symbol Parameter Min Max UFBGA100 package - 351 LQFP100 package - 488 UFBGA64 package - 308 TFBGA64 package - 313 LQFP64 package - 435 WLCSP49 package - 417 LQFP48 package - 370 UFQFPN48 package - 714 UFQFPN32 package - 556 LQFP32 package - 333 UFBGA100 package - 88 LQFP100 package - 122 UFBGA64 package - 77 TFBGA64 package - 78 LQFP64 package - 109 WLCSP49 package - 104 LQFP48 package - 93 UFQFPN48 package - 179 UFQFPN32 package - 139 LQFP32 package - 83 Maximum power dissipation (range 6) -40 85 Maximum power dissipation (range 7) -40 105 Maximum power dissipation (range 3) -40 125 Junction temperature range (range 6) -40 C TA 85 -40 105 Junction temperature range (range 7) -40 C TA 105 C -40 125 Junction temperature range (range 3) -40 C TA 125 C -40 130 Power dissipation at TA = 85 C (range 6) or TA =105 C (rage 7) (3) PD Power dissipation at TA = 125 C (range 3) (3) TA TJ Temperature range Conditions Unit mW C 1. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV between VDD and VDDA can be tolerated during power-up and normal operation. 2. To sustain a voltage higher than VDD+0.3V, the internal pull-up/pull-down resistors must be disabled. 3. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJ max (see Table 24: Thermal characteristics on page 59). DS10690 Rev 7 61/148 112 Electrical characteristics 6.3.2 STM32L071xx Embedded reset and power control block characteristics The parameters given in the following table are derived from the tests performed under the ambient temperature condition summarized in Table 25. Table 26. Embedded reset and power control block characteristics Symbol Parameter VDD rise time rate tVDD(1) VDD fall time rate TRSTTEMPO(1) Reset temporization VPOR/PDR Power-on/power down reset threshold VBOR0 Brown-out reset threshold 0 VBOR1 Brown-out reset threshold 1 VBOR2 Brown-out reset threshold 2 VBOR3 Brown-out reset threshold 3 VBOR4 Brown-out reset threshold 4 VPVD0 Programmable voltage detector threshold 0 VPVD1 PVD threshold 1 VPVD2 PVD threshold 2 VPVD3 PVD threshold 3 VPVD4 PVD threshold 4 VPVD5 PVD threshold 5 62/148 Conditions Min Typ Max BOR detector enabled 0 - BOR detector disabled 0 - 1000 BOR detector enabled 20 - BOR detector disabled 0 - 1000 VDD rising, BOR enabled - 2 3.3 0.4 0.7 1.6 Falling edge 1 1.5 1.65 Rising edge 1.3 1.5 1.65 Falling edge 1.67 1.7 1.74 Rising edge 1.69 1.76 1.8 Falling edge 1.87 1.93 1.97 Rising edge 1.96 2.03 2.07 Falling edge 2.22 2.30 2.35 Rising edge 2.31 2.41 2.44 Falling edge 2.45 2.55 2.6 Rising edge 2.54 2.66 2.7 Falling edge 2.68 2.8 2.85 Rising edge 2.78 2.9 2.95 Falling edge 1.8 1.85 1.88 Rising edge 1.88 1.94 1.99 Falling edge 1.98 2.04 2.09 Rising edge 2.08 2.14 2.18 Falling edge 2.20 2.24 2.28 Rising edge 2.28 2.34 2.38 Falling edge 2.39 2.44 2.48 Rising edge 2.47 2.54 2.58 Falling edge 2.57 2.64 2.69 Rising edge 2.68 2.74 2.79 Falling edge 2.77 2.83 2.88 Rising edge 2.87 2.94 2.99 VDD rising, BOR DS10690 Rev 7 disabled(2) Unit s/V ms V STM32L071xx Electrical characteristics Table 26. Embedded reset and power control block characteristics (continued) Symbol Parameter VPVD6 Conditions PVD threshold 6 Hysteresis voltage Vhyst Min Typ Max Falling edge 2.97 3.05 3.09 Rising edge 3.08 3.15 3.20 BOR0 threshold - 40 - All BOR and PVD thresholds excepting BOR0 - 100 - Unit V mV 1. Guaranteed by characterization results. 2. Valid for device version without BOR at power up. Please see option "D" in Ordering information scheme for more details. 6.3.3 Embedded internal reference voltage The parameters given in Table 28 are based on characterization results, unless otherwise specified. Table 27. Embedded internal reference voltage calibration values Calibration value name VREFINT_CAL Description Memory address Raw data acquired at temperature of 25 C VDDA= 3 V 0x1FF8 0078 - 0x1FF8 0079 Table 28. Embedded internal reference voltage(1) Symbol VREFINT out(2) Parameter Internal reference voltage Conditions Min Typ Max Unit - 40 C < TJ < +125 C 1.202 1.224 1.242 V TVREFINT Internal reference startup time - - 2 3 ms VVREF_MEAS VDDA and VREF+ voltage during VREFINT factory measure - 2.99 3 3.01 V AVREF_MEAS Accuracy of factory-measured VREFINT value(3) Including uncertainties due to ADC and VDDA/VREF+ values - - 5 mV TCoeff(4) Temperature coefficient -40 C < TJ < +125 C - 25 100 ppm/C ACoeff(4) Long-term stability 1000 hours, T= 25 C - - 1000 ppm VDDCoeff(4) Voltage coefficient 3.0 V < VDDA < 3.6 V - - 2000 ppm/V TS_vrefint(4)(5) ADC sampling time when reading the internal reference voltage - 5 10 - s TADC_BUF(4) Startup time of reference voltage buffer for ADC - - - 10 s IBUF_ADC(4) Consumption of reference voltage buffer for ADC - - 13.5 25 A IVREF_OUT(4) VREF_OUT output current(6) - - - 1 A CVREF_OUT(4) VREF_OUT output load - - - 50 pF DS10690 Rev 7 63/148 112 Electrical characteristics STM32L071xx Table 28. Embedded internal reference voltage(1) (continued) Symbol Parameter Conditions Min Typ Max Unit Consumption of reference voltage buffer for VREF_OUT and COMP - - 730 1200 nA VREFINT_DIV1(4) 1/4 reference voltage - 24 25 26 VREFINT_DIV2(4) 1/2 reference voltage - 49 50 51 VREFINT_DIV3(4) 3/4 reference voltage - 74 75 76 ILPBUF(4) % VREFINT 1. Refer to Table 40: Peripheral current consumption in Stop and Standby mode for the value of the internal reference current consumption (IREFINT). 2. Guaranteed by test in production. 3. The internal VREF value is individually measured in production and stored in dedicated EEPROM bytes. 4. Guaranteed by design. 5. Shortest sampling time can be determined in the application by multiple iterations. 6. To guarantee less than 1% VREF_OUT deviation. 6.3.4 Supply current characteristics The current consumption is a function of several parameters and factors such as the operating voltage, temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code. The current consumption is measured as described in Figure 15: Current consumption measurement scheme. All Run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to Dhrystone 2.1 code if not specified otherwise. The current consumption values are derived from the tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 25: General operating conditions unless otherwise specified. The MCU is placed under the following conditions: * All I/O pins are configured in analog input mode * All peripherals are disabled except when explicitly mentioned * The Flash memory access time and prefetch is adjusted depending on fHCLK frequency and voltage range to provide the best CPU performance unless otherwise specified. * When the peripherals are enabled fAPB1 = fAPB2 = fAPB * When PLL is ON, the PLL inputs are equal to HSI = 16 MHz (if internal clock is used) or HSE = 16 MHz (if HSE bypass mode is used) * The HSE user clock applied to OSCI_IN input follows the characteristic specified in Table 42: High-speed external user clock characteristics * For maximum current consumption VDD = VDDA = 3.6 V is applied to all supply pins * For typical current consumption VDD = VDDA = 3.0 V is applied to all supply pins if not specified otherwise The parameters given in Table 49, Table 25 and Table 26 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 25. 64/148 DS10690 Rev 7 STM32L071xx Electrical characteristics Table 29. Current consumption in Run mode, code with data processing running from Flash memory Symbol Parameter fHCLK (MHz) Typ Max(1) 1 190 250 2 345 380 4 650 670 4 0,8 0,86 8 1,55 1,7 16 2,95 3,1 8 1,9 2,1 16 3,55 3,8 32 6,65 7,2 0,065 39 130 0,524 115 210 4,2 700 770 Range2, Vcore=1.5 V VOS[1:0]=10 16 2,9 3,2 Range1, Vcore=1.8 V VOS[1:0]=01 32 Condition Range3, Vcore=1.2 V VOS[1:0]=11 fHSE = fHCLK up to 16MHz included, fHSE = fHCLK/2 above 16 MHz (PLL ON)(2) IDD (Run from Flash memory) Range2, Vcore=1.5 V VOS[1:0]=10 Range1, Vcore=1.8 V VOS[1:0]=01 Supply current in Run mode code executed from Flash memory MSI clock source HSI clock source (16MHz) Range3, Vcore=1.2 V VOS[1:0]=11 Unit A mA A mA 7,15 7,4 1. Guaranteed by characterization results at 125 C, unless otherwise specified. 2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register). DS10690 Rev 7 65/148 112 Electrical characteristics STM32L071xx Table 30. Current consumption in Run mode vs code type, code with data processing running from Flash memory Symbol IDD (Run from Flash memory) Parameter Conditions fHCLK Range 3, VCORE=1.2 V, VOS[1:0]=11 Supply current in Run mode, code executed from Flash memory Dhrystone 650 CoreMark 655 Fibonacci fHSE = fHCLK up to 16 MHz included, fHSE = fHCLK/2 above 16 MHz (PLL ON)(1) Range 1, VCORE=1.8 V, VOS[1:0]=01 Typ Unit 485 4 MHz A while(1) 385 while(1), 1WS, prefetch OFF 375 Dhrystone 6,65 CoreMark 6,9 Fibonacci 6,75 32 MHz while(1) 5,8 while(1), prefetch OFF 5,5 mA 1. Oscillator bypassed (HSEBYP = 1 in RCC_CR register). Figure 16. IDD vs VDD, at TA= 25/55/85/105 C, Run mode, code running from Flash memory, Range 2, HSE, 1WS 3.50 3.00 IDD (mA) 2.50 2.00 1.50 1.00 0.50 VDD (V) 0 1.65 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 -40 C 25 C 55 C 85 C 105 C 125 C MSv37843V1 66/148 DS10690 Rev 7 STM32L071xx Electrical characteristics Figure 17. IDD vs VDD, at TA= 25/55/85/105 C, Run mode, code running from Flash memory, Range 2, HSI16, 1WS 3.50 3.00 IDD (mA) 2.50 2.00 1.50 1.00 0.50 VDD (V) 0 1.65 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 -40 C 25 C 55 C 85 C 105 C 125 C MSv37844V1 Table 31. Current consumption in Run mode, code with data processing running from RAM Symbol Parameter Condition Range3, Vcore=1.2 V VOS[1:0]=11 fHSE = fHCLK up to 16 MHz included, fHSE = fHCLK/2 above 16 MHz (PLL ON)(2) IDD (Run from RAM) Range2, Vcore=1.5 V VOS[1:0]=10 Range1, Vcore=1.8 V VOS[1:0]=01 Supply current in Run mode code executed from RAM, Flash memory switched off MSI clock HSI clock source (16 MHz) fHCLK (MHz) Typ Max(1) 1 175 230 2 315 360 4 570 630 4 0,71 0,78 8 1,35 1,6 16 2,7 3 8 1,7 1,9 16 3,2 3,7 32 6,65 7,1 Range3, Vcore=1.2 V VOS[1:0]=11 0,065 38 98 0,524 105 160 4,2 615 710 Range2, Vcore=1.5 V VOS[1:0]=10 16 2,85 3 Range1, Vcore=1.8 V VOS[1:0]=01 32 Unit A mA A mA 6,85 7,3 1. Guaranteed by characterization results at 125 C, unless otherwise specified. DS10690 Rev 7 67/148 112 Electrical characteristics STM32L071xx 2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register). Table 32. Current consumption in Run mode vs code type, code with data processing running from RAM(1) Symbol Parameter Conditions fHCLK Dhrystone IDD (Run from RAM) Supply current in Run mode, code executed from RAM, Flash memory switched off fHSE = fHCLK up to 16 MHz included, fHSE = fHCLK/2 above 16 MHz (PLL ON)(2) Range 3, VCORE=1.2 V, VOS[1:0]=11 Range 1, VCORE=1.8 V, VOS[1:0]=01 CoreMark Fibonacci 2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register). 68/148 DS10690 Rev 7 4 MHz 670 410 375 Dhrystone 6,65 CoreMark Fibonacci Unit 570 while(1) while(1) 1. Guaranteed by characterization results, unless otherwise specified. Typ 32 MHz 6,95 5,9 5,2 A mA STM32L071xx Electrical characteristics Table 33. Current consumption in Sleep mode Symbol Parameter fHCLK (MHz) Typ Max(1) 1 43,5 110 2 72 140 4 130 200 4 160 220 8 305 380 16 590 690 8 370 460 16 715 840 32 1650 2000 0,065 18 93 0,524 31,5 110 4,2 140 230 Range2, Vcore=1.5 V VOS[1:0]=10 16 665 850 Range1, Vcore=1.8 V VOS[1:0]=01 32 1750 2100 1 57,5 130 2 84 160 4 150 220 4 170 240 8 315 400 16 605 710 8 380 470 16 730 860 32 1650 2000 0,065 29,5 110 0,524 44,5 120 4,2 150 240 Range2, Vcore=1.5 V VOS[1:0]=10 16 680 930 Range1, Vcore=1.8 V VOS[1:0]=01 32 1750 2200 Condition Range3, Vcore=1.2 V VOS[1:0]=11 fHSE = fHCLK up to 16 MHz included, fHSE = fHCLK/2 above 16 MHz (PLL ON)(2) Range2, Vcore=1.5 V VOS[1:0]=10 Range1, Vcore=1.8 V VOS[1:0]=01 Supply current in Sleep mode, Flash memory switched OFF Range3, Vcore=1.2 V VOS[1:0]=11 MSI clock HSI clock source (16 MHz) IDD (Sleep) Range3, Vcore=1.2 V VOS[1:0]=11 fHSE = fHCLK up to 16MHz included, fHSE = fHCLK/2 above 16 MHz (PLL ON)(2) Range2, Vcore=1.5 V VOS[1:0]=10 Range1, Vcore=1.8 V VOS[1:0]=01 Supply current in Sleep mode, Flash memory switched ON Range3, Vcore=1.2 V VOS[1:0]=11 MSI clock HSI clock source (16MHz) Unit A 1. Guaranteed by characterization results at 125 C, unless otherwise specified. DS10690 Rev 7 69/148 112 Electrical characteristics STM32L071xx 2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register). Table 34. Current consumption in Low-power run mode Symbol Parameter fHCLK (MHz) Typ Max(1) 9,45 12 14 58 21 64 36,5 160 14,5 18 19,5 60 26 65 42 160 26,5 30 27,5 60 31 66 TA = 105C 37,5 77 TA = 125C 53,5 170 TA = - 40 to 25C 24,5 34 30 82 38,5 90 TA = 125C 58 120 TA = - 40 to 25C 30,5 40 36,5 88 45 96 TA = 125C 64,5 120 TA = - 40 to 25C 45 56 TA = 55C 48 96 51 110 TA = 105C 59,5 120 TA = 125C 79,5 150 Condition TA = - 40 to 25C MSI clock = 65 kHz, fHCLK= 32 kHz TA = 85C TA = 105C 0,032 TA = 125C TA = - 40 to 25C All peripherals OFF, code TA = 85C MSI clock = 65 kHz, executed from 0,065 f = 65kHz HCLK TA = 105C RAM, Flash memory switched TA = 125C OFF, VDD from 1.65 to 3.6 V TA = - 40 to 25C MSI clock=131 kHz, fHCLK= 131 kHz IDD (LP Run) Supply current in Low-power run mode MSI clock = 65 kHz, fHCLK= 32 kHz All peripherals OFF, code MSI clock = 65 kHz, executed from fHCLK= 65 kHz Flash memory, VDD from 1.65 V to 3.6 V MSI clock = 131 kHz, fHCLK= 131 kHz TA = 55C TA = 85C TA = 85C TA = 105C TA = 85C TA = 105C TA = 85C 1. Guaranteed by characterization results at 125 C, unless otherwise specified. 70/148 DS10690 Rev 7 0,131 0,032 0,065 0,131 Unit A STM32L071xx Electrical characteristics Figure 18. IDD vs VDD, at TA= 25 C, Low-power run mode, code running from RAM, Range 3, MSI (Range 0) at 64 KHz, 0 WS IDD (mA) 4,5E-02 4,0E-02 3,5E-02 3,0E-02 2,5E-02 2,0E-02 1,5E-02 1,0E-02 5,0E-03 0 VDD (V) 1,65 1,8 2 2,2 2,4 2,6 2,8 3 3,2 3,4 3,6 -40 25 55 85 105 125 MSv37845V2 Table 35. Current consumption in Low-power sleep mode Symbol Parameter Condition Max (1) MSI clock = 65 kHz, fHCLK= 32 kHz, TA = - 40 to 25C Flash memory OFF 4,7 - TA = - 40 to 25C 17 24 TA = 85C 19,5 30 TA= 105C 23 47 TA= 125C 32,5 70 TA= - 40 to 25C 17 24 TA= 85C 20 31 TA = 105C 23,5 47 TA = 125C 32,5 70 TA= - 40 to 25C 19,5 27 TA = 55C 20,5 28 TA = 85C 22,5 33 TA = 105C 26 50 TA= 125C 35 73 MSI clock = 65 kHz, fHCLK= 32 kHz All peripherals Supply current in OFF, code IDD Low-power sleep executed from (LP Sleep) mode Flash memory, VDD from 1.65 to 3.6 V Typ MSI clock = 65 kHz, fHCLK= 65 kHz MSI clock = 131kHz, fHCLK= 131 kHz Unit A 1. Guaranteed by characterization results at 125 C, unless otherwise specified. DS10690 Rev 7 71/148 112 Electrical characteristics STM32L071xx Table 36. Typical and maximum current consumptions in Stop mode Symbol Parameter Max(1) Unit Conditions Typ TA = - 40 to 25C 0,43 1,00 TA = 55C 0,735 2,50 TA= 85C 2,25 4,90 TA = 105C 5,3 13,00 TA = 125C 12,5 28,00 IDD (Stop) Supply current in Stop mode A 1. Guaranteed by characterization results at 125 C, unless otherwise specified. Figure 19. IDD vs VDD, at TA= 25/55/ 85/105/125 C, Stop mode with RTC enabled and running on LSE Low drive 1.6E-02 1.4E-02 1.2E-02 1.0E-02 IDD (mA) 8.0E-03 6.0E-03 4.0E-03 2.0E-03 VDD (V) 0 1.65 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 -40 C 25 C 55 C 85 C 105 C 125 C MSv37846V1 72/148 DS10690 Rev 7 STM32L071xx Electrical characteristics Figure 20. IDD vs VDD, at TA= 25/55/85/105/125 C, Stop mode with RTC disabled, all clocks OFF 1.4E-02 1.2E-02 1.0E-02 IDD (mA) 8.0E-03 6.0E-03 4.0E-03 2.0E-03 VDD (V) 0 1.65 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 -40 C 25 C 55 C 85 C 105 C 125 C MSv37847V1 Table 37. Typical and maximum current consumptions in Standby mode Symbol Parameter Typ Max(1) TA = - 40 to 25C 0,855 1,70 TA = 55 C - 2,90 TA= 85 C - 3,30 TA = 105 C - 4,10 TA = 125 C - 8,50 TA = - 40 to 25C 0,29 0,60 TA = 55 C 0,32 1,20 TA = 85 C 0,5 2,30 TA = 105 C 0,94 3,00 TA = 125 C 2,6 7,00 Conditions Independent watchdog and LSI enabled IDD Supply current in Standby (Standby) mode Independent watchdog and LSI OFF Unit A 1. Guaranteed by characterization results at 125 C, unless otherwise specified DS10690 Rev 7 73/148 112 Electrical characteristics STM32L071xx Table 38. Average current consumption during Wakeup System frequency Current consumption during wakeup HSI 1 HSI/4 0,7 MSI clock = 4,2 MHz 0,7 MSI clock = 1,05 MHz 0,4 MSI clock = 65 KHz 0,1 Reset pin pulled down - 0,21 BOR ON - 0,23 MSI clock = 2,1 MHz 0,5 MSI clock = 2,1 MHz 0,12 Symbol parameter IDD (Wakeup from Supply current during Wakeup from Stop) Stop mode IDD (Reset) IDD (Power-up) IDD (Wakeup from With Fast wakeup set StandBy) With Fast wakeup disabled 74/148 DS10690 Rev 7 Unit mA STM32L071xx Electrical characteristics On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in the following tables. The MCU is placed under the following conditions: * all I/O pins are in input mode with a static value at VDD or VSS (no load) * all peripherals are disabled unless otherwise mentioned * the given value is calculated by measuring the current consumption - with all peripherals clocked OFF - with only one peripheral clocked on Table 39. Peripheral current consumption in Run or Sleep mode(1) Typical consumption, VDD = 3.0 V, TA = 25 C Peripheral APB1 Low-power sleep and run CRS 2.5 2 2 2 I2C1 11 9.5 7.5 9 I2C3 11 9 7 9 LPTIM1 10 8.5 6.5 8 LPUART1 8 6.5 5.5 6 SPI2 9 4.5 3.5 4 USART2 14.5 12 9.5 11 USART4 5 4 3 5 USART5 5 4 3 5 TIM2 10.5 8.5 7 9 TIM3 12 10 8 11 TIM6 3.5 3 2.5 2 TIM7 3.5 3 2.5 2 3 2 2 2 5.5 5 3.5 4 4 3 3 2.5 USART1 14.5 11.5 9.5 12 TIM21 7.5 6 5 5.5 TIM22 7 6 5 6 FIREWALL 1.5 1 1 0.5 DBGMCU 1.5 1 1 0.5 SYSCFG 2.5 2 2 1.5 WWDG ADC1 (2) SPI1 APB2 Range 2, Range 3, Range 1, VCORE=1.8 V VCORE=1.5 V VCORE=1.2 V VOS[1:0] = 01 VOS[1:0] = 10 VOS[1:0] = 11 DS10690 Rev 7 Unit A/MHz (fHCLK) A/MHz (fHCLK) 75/148 112 Electrical characteristics STM32L071xx Table 39. Peripheral current consumption in Run or Sleep mode(1) (continued) Typical consumption, VDD = 3.0 V, TA = 25 C Peripheral Range 2, Range 3, Range 1, VCORE=1.8 V VCORE=1.5 V VCORE=1.2 V VOS[1:0] = 01 VOS[1:0] = 10 VOS[1:0] = 11 Low-power sleep and run GPIOA 3.5 3 2.5 2.5 GPIOB 3.5 2.5 2 2.5 Cortex- GPIOC M0+ core I/O port GPIOD 8.5 6.5 5.5 7 1 0.5 0.5 0.5 GPIOE 8 6 5 6 GPIOH 1.5 1 1 0.5 CRC 1.5 1 1 1 0(3) 0(3) 0(3) AHB (3) Unit A/MHz (fHCLK) A/MHz (fHCLK) FLASH 0 DMA1 10 8 6.5 8.5 All enabled 204 162 130 202 A/MHz (fHCLK) PWR 2.5 2 2 1 A/MHz (fHCLK) 1. Data based on differential IDD measurement between all peripherals OFF an one peripheral with clock enabled, in the following conditions: fHCLK = 32 MHz (range 1), fHCLK = 16 MHz (range 2), fHCLK = 4 MHz (range 3), fHCLK = 64kHz (Low-power run/sleep), fAPB1 = fHCLK, fAPB2 = fHCLK, default prescaler value for each peripheral. The CPU is in Sleep mode in both cases. No I/O pins toggling. Not tested in production. 2. HSI oscillator is OFF for this measure. 3. Current consumption is negligible and close to 0 A. 76/148 DS10690 Rev 7 STM32L071xx Electrical characteristics Table 40. Peripheral current consumption in Stop and Standby mode(1) Symbol IDD(PVD / BOR) - IREFINT - - Typical consumption, TA = 25 C Peripheral LSE Low drive(2) VDD=1.8 V VDD=3.0 V 0.7 1.2 - 1.7 0.11 0,13 - LSI 0.27 0.31 - IWDG 0.2 0.3 - LPTIM1, Input 100 Hz 0.01 0,01 - LPTIM1, Input 1 MHz 11 12 - LPUART1 - 0,5 - RTC 0.16 0,3 Unit A 1. LPTIM, LPUART peripherals can operate in Stop mode but not in Standby mode. 2. LSE Low drive consumption is the difference between an external clock on OSC32_IN and a quartz between OSC32_IN and OSC32_OUT.- 6.3.5 Wakeup time from low-power mode The wakeup times given in the following table are measured with the MSI or HSI16 RC oscillator. The clock source used to wake up the device depends on the current operating mode: * Sleep mode: the clock source is the clock that was set before entering Sleep mode * Stop mode: the clock source is either the MSI oscillator in the range configured before entering Stop mode, the HSI16 or HSI16/4. * Standby mode: the clock source is the MSI oscillator running at 2.1 MHz All timings are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 25. Table 41. Low-power mode wakeup timings Symbol tWUSLEEP Parameter Conditions Wakeup from Sleep mode tWUSLEEP_ Wakeup from Low-power sleep mode, fHCLK = 262 kHz LP Typ Max fHCLK = 32 MHz 7 8 fHCLK = 262 kHz Flash memory enabled 7 8 fHCLK = 262 kHz Flash memory switched OFF 9 10 DS10690 Rev 7 Unit Number of clock cycles 77/148 112 Electrical characteristics STM32L071xx Table 41. Low-power mode wakeup timings (continued) Symbol tWUSTOP tWUSTDBY 78/148 Parameter Conditions Typ Max fHCLK = fMSI = 4.2 MHz Wakeup from Stop mode, regulator in Run fHCLK = fHSI = 16 MHz mode fHCLK = fHSI/4 = 4 MHz 5.0 8 4.9 7 8.0 11 fHCLK = fMSI = 4.2 MHz Voltage range 1 5.0 8 fHCLK = fMSI = 4.2 MHz Voltage range 2 5.0 8 fHCLK = fMSI = 4.2 MHz Voltage range 3 5.0 8 7.3 13 13 23 28 38 fHCLK = fMSI = 262 kHz 51 65 fHCLK = fMSI = 131 kHz 100 120 fHCLK = MSI = 65 kHz 190 260 fHCLK = fHSI = 16 MHz 4.9 7 fHCLK = fHSI/4 = 4 MHz 8.0 11 fHCLK = fHSI = 16 MHz Wakeup from Stop mode, regulator in lowfHCLK = fHSI/4 = 4 MHz power mode, code running from RAM fHCLK = fMSI = 4.2 MHz 4.9 7 7.9 10 4.7 8 Wakeup from Standby mode FWU bit = 1 fHCLK = MSI = 2.1 MHz 65 130 Wakeup from Standby mode FWU bit = 0 fHCLK = MSI = 2.1 MHz 2.2 3 fHCLK = fMSI = 2.1 MHz Wakeup from Stop mode, regulator in lowfHCLK = fMSI = 1.05 MHz power mode fHCLK = fMSI = 524 kHz DS10690 Rev 7 Unit s ms STM32L071xx 6.3.6 Electrical characteristics External clock source characteristics High-speed external user clock generated from an external source In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.The external clock signal has to respect the I/O characteristics in Section 6.3.12. However, the recommended clock input waveform is shown in Figure 21. Table 42. High-speed external user clock characteristics(1) Symbol fHSE_ext Parameter User external clock source frequency Conditions Min Typ Max Unit CSS is ON or PLL is used 1 8 32 MHz CSS is OFF, PLL not used 0 8 32 MHz VHSEH OSC_IN input pin high level voltage 0.7VDD - VDD VHSEL OSC_IN input pin low level voltage VSS - 0.3VDD tw(HSE) tw(HSE) OSC_IN high or low time 12 - - tr(HSE) tf(HSE) OSC_IN rise or fall time - - 20 OSC_IN input capacitance - 2.6 - pF 45 - 55 % - - 1 A Cin(HSE) ns - DuCy(HSE) Duty cycle IL OSC_IN Input leakage current V VSS VIN VDD 1. Guaranteed by design. Figure 21. High-speed external clock source AC timing diagram VHSEH 90% VHSEL 10% tr(HSE) tf(HSE) tW(HSE) tW(HSE) t THSE EXTER NAL CLOCK SOURC E fHSE_ext OSC _IN IL STM32Lxx ai18232c DS10690 Rev 7 79/148 112 Electrical characteristics STM32L071xx Low-speed external user clock generated from an external source The characteristics given in the following table result from tests performed using a lowspeed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 25. Table 43. Low-speed external user clock characteristics(1) Symbol Parameter Conditions fLSE_ext User external clock source frequency VLSEH OSC32_IN input pin high level voltage VLSEL OSC32_IN input pin low level voltage tw(LSE) tw(LSE) OSC32_IN high or low time tr(LSE) tf(LSE) OSC32_IN rise or fall time CIN(LSE) Typ Max Unit 1 32.768 1000 kHz 0.7VDD - VDD V - VSS - 0.3VDD 465 - ns - - 10 - - 0.6 - pF - 45 - 55 % VSS VIN VDD - - 1 A OSC32_IN input capacitance DuCy(LSE) Duty cycle IL Min OSC32_IN Input leakage current 1. Guaranteed by design, not tested in production Figure 22. Low-speed external clock source AC timing diagram VLSEH 90% VLSEL 10% tr(LSE) tf(LSE) tW(LSE) tW(LSE) t TLSE EXTER NAL CLOCK SOURC E fLSE_ext OSC32_IN IL STM32Lxx ai18233c 80/148 DS10690 Rev 7 STM32L071xx Electrical characteristics High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 1 to 25 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 44. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 44. HSE oscillator characteristics(1) Symbol Parameter Conditions fOSC_IN Oscillator frequency RF Feedback resistor Gm Maximum critical crystal transconductance tSU(HSE) (2) Startup time Min Typ - 1 - - Startup VDD is stabilized Max Unit 25 MHz 200 - k - - 700 A /V - 2 - ms 1. Guaranteed by design. 2. Guaranteed by characterization results. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer. For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the 5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see Figure 23). CL1 and CL2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing CL1 and CL2. Refer to the application note AN2867 "Oscillator design guide for ST microcontrollers" available from the ST website www.st.com. Figure 23. HSE oscillator circuit diagram fHSE to core Rm Lm RF CO CL1 OSC_IN Cm gm Resonator Resonator Consumption control STM32 OSC_OUT CL2 ai18235b DS10690 Rev 7 81/148 112 Electrical characteristics STM32L071xx Low-speed external clock generated from a crystal/ceramic resonator The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 45. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 45. LSE oscillator characteristics(1) Symbol fLSE Gm Conditions(2) Min(2) Typ Max Unit - 32.768 - kHz LSEDRV[1:0]=00 lower driving capability - - 0.5 LSEDRV[1:0]= 01 medium low driving capability - - 0.75 LSEDRV[1:0] = 10 medium high driving capability - - 1.7 LSEDRV[1:0]=11 higher driving capability - - 2.7 VDD is stabilized - 2 - Parameter LSE oscillator frequency Maximum critical crystal transconductance tSU(LSE)(3) Startup time A/V s 1. Guaranteed by design. 2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 "Oscillator design guide for ST microcontrollers". 3. Guaranteed by characterization results. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer. To increase speed, address a lower-drive quartz with a high- driver mode. Note: For information on selecting the crystal, refer to the application note AN2867 "Oscillator design guide for ST microcontrollers" available from the ST website www.st.com. Figure 24. Typical application with a 32.768 kHz crystal Resonator with integrated capacitors CL1 OSC32_IN fLSE Drive programmable amplifier 32.768 kHz resonator OSC32_OUT CL2 MS30253V2 Note: 82/148 An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden to add one. DS10690 Rev 7 STM32L071xx 6.3.7 Electrical characteristics Internal clock source characteristics The parameters given in Table 46 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 25. High-speed internal 16 MHz (HSI16) RC oscillator Table 46. 16 MHz HSI16 oscillator characteristics Symbol fHSI16 TRIM (1)(2) ACCHSI16 (2) Parameter Conditions Min Typ Max Unit Frequency VDD = 3.0 V - 16 - MHz HSI16 usertrimmed resolution Trimming code is not a multiple of 16 - 0.4 0.7 % Trimming code is a multiple of 16 - Accuracy of the factory-calibrated HSI16 oscillator - 1.5 % VDDA = 3.0 V, TA = 25 C -1(3) - 1(3) % VDDA = 3.0 V, TA = 0 to 55 C -1.5 - 1.5 % VDDA = 3.0 V, TA = -10 to 70 C -2 - 2 % VDDA = 3.0 V, TA = -10 to 85 C -2.5 - 2 % VDDA = 3.0 V, TA = -10 to 105 C -4 - 2 % -5.45 - 3.25 % VDDA = 1.65 V to 3.6 V TA = - 40 to 125 C tSU(HSI16)(2) HSI16 oscillator startup time - - 3.7 6 s IDD(HSI16)(2) HSI16 oscillator power consumption - - 100 140 A 1. The trimming step differs depending on the trimming code. It is usually negative on the codes which are multiples of 16 (0x00, 0x10, 0x20, 0x30...0xE0). 2. Guaranteed by characterization results. 3. Guaranteed by test in production. Figure 25. HSI16 minimum and maximum value versus temperature 4.00% 3.00% 2.00% 1.00% 1.65V min -60 -40 0.00% -20 0 -1.00% 20 40 60 80 100 120 140 3V typ 3.6V max 1.65V max -2.00% 3.6V min -3.00% -4.00% -5.00% -6.00% MSv34791V1 DS10690 Rev 7 83/148 112 Electrical characteristics STM32L071xx Low-speed internal (LSI) RC oscillator Table 47. LSI oscillator characteristics Symbol Parameter Min Typ Max Unit fLSI(1) LSI frequency 26 38 56 kHz DLSI(2) LSI oscillator frequency drift 0C TA 85C -10 - 4 % LSI oscillator startup time - - 200 s LSI oscillator power consumption - 400 510 nA tsu(LSI)(3) IDD(LSI) (3) 1. Guaranteed by test in production. 2. This is a deviation for an individual part, once the initial frequency has been measured. 3. Guaranteed by design. Multi-speed internal (MSI) RC oscillator Table 48. MSI oscillator characteristics Symbol fMSI ACCMSI DTEMP(MSI)(1) DVOLT(MSI)(1) 84/148 Parameter Condition Typ MSI range 0 65.5 - MSI range 1 131 - MSI range 2 262 - MSI range 3 524 - MSI range 4 1.05 - MSI range 5 2.1 - MSI range 6 4.2 - Frequency error after factory calibration - 0.5 - MSI oscillator frequency drift 0 C TA 85 C - 3 - MSI range 0 - 8.9 +7.0 MSI range 1 - 7.1 +5.0 MSI range 2 - 6.4 +4.0 MSI range 3 - 6.2 +3.0 MSI range 4 - 5.2 +3.0 MSI range 5 - 4.8 +2.0 MSI range 6 - 4.7 +2.0 - - 2.5 Frequency after factory calibration, done at VDD= 3.3 V and TA = 25 C MSI oscillator frequency drift VDD = 3.3 V, - 40 C TA 110 C MSI oscillator frequency drift 1.65 V VDD 3.6 V, TA = 25 C DS10690 Rev 7 Max Unit kHz MHz % % %/V STM32L071xx Electrical characteristics Table 48. MSI oscillator characteristics (continued) Symbol IDD(MSI)(2) tSU(MSI) tSTAB(MSI)(2) fOVER(MSI) Parameter MSI oscillator power consumption MSI oscillator startup time MSI oscillator stabilization time MSI oscillator frequency overshoot Condition Typ Max Unit MSI range 0 0.75 - MSI range 1 1 - MSI range 2 1.5 - MSI range 3 2.5 - MSI range 4 4.5 - MSI range 5 8 - MSI range 6 15 - MSI range 0 30 - MSI range 1 20 - MSI range 2 15 - MSI range 3 10 - MSI range 4 6 - MSI range 5 5 - MSI range 6, Voltage range 1 and 2 3.5 - MSI range 6, Voltage range 3 5 - MSI range 0 - 40 MSI range 1 - 20 MSI range 2 - 10 MSI range 3 - 4 MSI range 4 - 2.5 MSI range 5 - 2 MSI range 6, Voltage range 1 and 2 - 2 MSI range 3, Voltage range 3 - 3 Any range to range 5 - 4 Any range to range 6 - A s s MHz 6 1. This is a deviation for an individual part, once the initial frequency has been measured. 2. Guaranteed by characterization results. DS10690 Rev 7 85/148 112 Electrical characteristics 6.3.8 STM32L071xx PLL characteristics The parameters given in Table 49 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 25. Table 49. PLL characteristics Value Symbol Parameter Unit Min Typ Max(1) PLL input clock(2) 2 - 24 MHz PLL input clock duty cycle 45 - 55 % fPLL_OUT PLL output clock 2 - 32 MHz tLOCK PLL input = 16 MHz PLL VCO = 96 MHz - 115 160 s Jitter Cycle-to-cycle jitter - 600 ps IDDA(PLL) Current consumption on VDDA - 220 450 IDD(PLL) Current consumption on VDD - 120 150 fPLL_IN A 1. Guaranteed by characterization results. 2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with the range defined by fPLL_OUT. 6.3.9 Memory characteristics RAM memory Table 50. RAM and hardware registers Symbol VRM Parameter Data retention mode(1) Conditions STOP mode (or RESET) Min Typ Max Unit 1.65 - - V 1. Minimum supply voltage without losing data stored in RAM (in Stop mode or under Reset) or in hardware registers (only in Stop mode). Flash memory and data EEPROM Table 51. Flash memory and data EEPROM characteristics Symbol 86/148 Conditions Min Typ Max(1) Unit - 1.65 - 3.6 V Erasing - 3.28 3.94 Programming - 3.28 3.94 Parameter VDD Operating voltage Read / Write / Erase tprog Programming time for word or half-page DS10690 Rev 7 ms STM32L071xx Electrical characteristics Table 51. Flash memory and data EEPROM characteristics Symbol IDD Min Typ Max(1) Unit Average current during the whole programming / erase operation - 500 700 A Maximum current (peak) TA = 25 C, VDD = 3.6 V during the whole programming / erase operation - 1.5 2.5 mA Parameter Conditions 1. Guaranteed by design. Table 52. Flash memory and data EEPROM endurance and retention Value Symbol Parameter Cycling (erase / write) Program memory NCYC(2) Min(1) Unit 10 TA = -40C to 105 C Cycling (erase / write) EEPROM data memory 100 kcycles Cycling (erase / write) Program memory 0.2 TA = -40C to 125 C Cycling (erase / write) EEPROM data memory 2 Data retention (program memory) after 10 kcycles at TA = 85 C Data retention (EEPROM data memory) after 100 kcycles at TA = 85 C tRET(2) Conditions Data retention (program memory) after 10 kcycles at TA = 105 C Data retention (EEPROM data memory) after 100 kcycles at TA = 105 C Data retention (program memory) after 200 cycles at TA = 125 C Data retention (EEPROM data memory) after 2 kcycles at TA = 125 C 30 TRET = +85 C 30 TRET = +105 C years 10 TRET = +125 C 1. Guaranteed by characterization results. 2. Characterization is done according to JEDEC JESD22-A117. DS10690 Rev 7 87/148 112 Electrical characteristics 6.3.10 STM32L071xx EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs: * Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard. * FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard. A device reset allows normal operations to be resumed. The test results are given in Table 53. They are based on the EMS levels and classes defined in application note AN1709. Table 53. EMS characteristics Symbol Parameter Conditions VFESD VDD = 3.3 V, LQFP100, TA = +25 C, Voltage limits to be applied on any I/O pin to fHCLK = 32 MHz induce a functional disturbance conforms to IEC 61000-4-2 VEFTB Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a functional disturbance Level/ Class VDD = 3.3 V, LQFP100, TA = +25 C, fHCLK = 32 MHz conforms to IEC 61000-4-4 3B 4A Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations The software flowchart must include the management of runaway conditions such as: * Corrupted program counter * Unexpected reset * Critical data corruption (control registers...) Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the oscillator pins for 1 second. 88/148 DS10690 Rev 7 STM32L071xx Electrical characteristics To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). Electromagnetic Interference (EMI) The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with IEC 61967-2 standard which specifies the test board and the pin loading. Table 54. EMI characteristics Symbol Parameter SEMI Conditions VDD = 3.6 V, Peak level TA = 25 C, LQFP100 package compliant with IEC 61967-2 DS10690 Rev 7 Monitored frequency band Max vs. frequency range at 32 MHz 0.1 to 30 MHz -7 30 to 130 MHz 14 130 MHz to 1 GHz 9 EMI Level 2 Unit dBV - 89/148 112 Electrical characteristics 6.3.11 STM32L071xx Electrical sensitivity characteristics Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts x (n+1) supply pins). This test conforms to the ANSI/JEDEC standard. Table 55. ESD absolute maximum ratings Symbol VESD(HBM) Ratings Conditions Class Maximum value(1) 2 2000 TA = +25 C, Electrostatic discharge conforming to voltage (human body model) ANSI/JEDEC JS-001 TA = +25 C, conforming to ANSI/ESD STM5.3.1. Electrostatic discharge VESD(CDM) voltage (charge device model) Unit V C4 500 1. Guaranteed by characterization results. Static latch-up Two complementary static tests are required on six parts to assess the latch-up performance: * A supply overvoltage is applied to each power supply pin * A current injection is applied to each input, output and configurable I/O pin These tests are compliant with EIA/JESD 78A IC latch-up standard. Table 56. Electrical sensitivities Symbol LU 90/148 Parameter Static latch-up class Conditions TA = +125 C conforming to JESD78A DS10690 Rev 7 Class II level A STM32L071xx 6.3.12 Electrical characteristics I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below VSS or above VDD (for standard pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization. Functional susceptibility to I/O current injection While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures. The failure is indicated by an out of range parameter: ADC error above a certain limit (higher than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of -5 A/+0 A range), or other functional failure (for example reset occurrence oscillator frequency deviation). The test results are given in the Table 57. Table 57. I/O current injection susceptibility Functional susceptibility Symbol IINJ Description Negative injection Positive injection Injected current on BOOT0 -0 NA(1) Injected current on PA0, PA4, PA5, PC15, PH0 and PH1 -5 0 Injected current on any other FT, FTf pins -5 (2) NA(1) Injected current on any other pins -5 (2) +5 Unit mA 1. Current injection is not possible. 2. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents. DS10690 Rev 7 91/148 112 Electrical characteristics 6.3.13 STM32L071xx I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 58 are derived from tests performed under the conditions summarized in Table 25. All I/Os are CMOS and TTL compliant. Table 58. I/O static characteristics Symbol VIL VIH Vhys Ilkg RPU Parameter Input low level voltage Input high level voltage I/O Schmitt trigger voltage hysteresis (2) Input leakage current (4) Weak pull-up equivalent resistor(5) RPD Weak pull-down equivalent resistor CIO I/O pin capacitance (5) Conditions Min Typ Max TC, FT, FTf, RST I/Os - - 0.3VDD BOOT0 pin - - 0.14VDD(1) All I/Os 0.7 VDD - - Standard I/Os - 10% VDD(3) - BOOT0 pin - 0.01 - VSS VIN VDD All I/Os except for PA11, PA12, BOOT0 and FTf I/Os - - 50 VSS VIN VDD, PA11 and PA12 I/Os - - -50/+250 VSS VIN VDD FTf I/Os - - 100 VDDVIN 5 V All I/Os except for PA11, PA12, BOOT0 and FTf I/Os - - 200 VDDVIN 5 V FTf I/Os - - 500 VDDVIN 5 V PA11, PA12 and BOOT0 - - 10 A VIN = VSS 25 45 65 k VIN = VDD 25 45 65 k - - 5 - pF nA 2. Hysteresis voltage between Schmitt trigger switching levels. Guaranteed by characterization results. 3. With a minimum of 200 mV. Guaranteed by characterization results. 4. The max. value may be exceeded if negative current is injected on adjacent pins. 5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This MOS/NMOS contribution to the series resistance is minimum (~10% order). DS10690 Rev 7 V nA 1. Guaranteed by characterization. 92/148 Unit STM32L071xx Electrical characteristics Figure 26. VIH/VIL versus VDD (CMOS I/Os) VIL/VIH (V) ins (all p /1 0.59 V DD+ 15, PH0 9 .3 =0 , PC V IHmin t BOOT0 0.38 for + p 5V DD H0/1 exce = 0.4 ,P V IHmin 0, PC15 T BOO V DD min ard tand Ss CMO VIHmin 2.0 ts V IH men = 0.7 ire requ V DD V ILmax 1.3 = 0.3 Input range not guaranteed CMOS standard requirements VILmax = 0.3VDD VILmax 0.7 0.6 VDD (V) 2.0 2.7 3.0 3.3 3.6 MSv34789V1 Figure 27. VIH/VIL versus VDD (TTL I/Os) VIL/VIH (V) pins 9 (all +0.5 , PH0/1 D D V 9 15 = 0.3 , PC V IHmin t BOOT0 0.38 for + p exce = 0.45V DD PH0/1 , V IHmin 0, PC15 T BOO TTL standard requirements VIHmin = 2 V VIHmin 2.0 V DD V ILmax 1.3 = 0.3 Input range not guaranteed VILmax 0.8 0.7 TTL standard requirements VILmax = 0.8 V VDD (V) 2.0 2.7 3.0 3.3 3.6 MSv34790V1 Output driving current The GPIOs (general purpose input/outputs) can sink or source up to 8 mA, and sink or source up to 15 mA with the non-standard VOL/VOH specifications given in Table 59. In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 6.2: * The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating IVDD() (see Table 23). * The sum of the currents sunk by all the I/Os on VSS plus the maximum Run consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating IVSS() (see Table 23). DS10690 Rev 7 93/148 112 Electrical characteristics STM32L071xx Output voltage levels Unless otherwise specified, the parameters given in Table 59 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 25. All I/Os are CMOS and TTL compliant. Table 59. Output voltage characteristics Symbol Parameter VOL(1) Output low level voltage for an I/O pin VOH(3) Output high level voltage for an I/O pin Conditions Min Max CMOS port(2), IIO = +8 mA 2.7 V VDD 3.6 V - 0.4 VDD-0.4 - (1) Output low level voltage for an I/O pin TTL port(2), IIO =+ 8 mA 2.7 V VDD 3.6 V - 0.4 (3)(4) Output high level voltage for an I/O pin TTL port(2), IIO = -6 mA 2.7 V VDD 3.6 V 2.4 - VOL(1)(4) Output low level voltage for an I/O pin IIO = +15 mA 2.7 V VDD 3.6 V - 1.3 VOH(3)(4) Output high level voltage for an I/O pin IIO = -15 mA 2.7 V VDD 3.6 V VDD-1.3 - VOL(1)(4) Output low level voltage for an I/O pin IIO = +4 mA 1.65 V VDD < 3.6 V - 0.45 VOH(3)(4) Output high level voltage for an I/O pin IIO = -4 mA VDD-0.45 1.65 V VDD 3.6 V VOL VOH Output low level voltage for an FTf VOLFM+(1)(4) I/O pin in Fm+ mode Unit V - IIO = 20 mA 2.7 V VDD 3.6 V - 0.4 IIO = 10 mA 1.65 V VDD 3.6 V - 0.4 1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 23. The sum of the currents sunk by all the I/Os (I/O ports and control pins) must always be respected and must not exceed IIO(PIN). 2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52. 3. The IIO current sourced by the device must always respect the absolute maximum rating specified in Table 23. The sum of the currents sourced by all the I/Os (I/O ports and control pins) must always be respected and must not exceed IIO(PIN). 4. Guaranteed by characterization results. 94/148 DS10690 Rev 7 STM32L071xx Electrical characteristics Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 28 and Table 60, respectively. Unless otherwise specified, the parameters given in Table 60 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 25. Table 60. I/O AC characteristics(1) OSPEEDRx[1:0] bit value(1) Symbol fmax(IO)out Maximum frequency(3) tf(IO)out tr(IO)out Output rise and fall time fmax(IO)out Maximum frequency(3) tf(IO)out tr(IO)out Output rise and fall time 00 01 Fmax(IO)out Maximum frequency(3) 10 tf(IO)out tr(IO)out Output rise and fall time Fmax(IO)out Maximum frequency(3) 11 Fm+ configuration(4) - Min Max(2) CL = 50 pF, VDD = 2.7 V to 3.6 V - 400 CL = 50 pF, VDD = 1.65 V to 2.7 V - 100 CL = 50 pF, VDD = 2.7 V to 3.6 V - 125 CL = 50 pF, VDD = 1.65 V to 2.7 V - 320 CL = 50 pF, VDD = 2.7 V to 3.6 V - 2 CL = 50 pF, VDD = 1.65 V to 2.7 V - 0.6 CL = 50 pF, VDD = 2.7 V to 3.6 V - 30 CL = 50 pF, VDD = 1.65 V to 2.7 V - 65 CL = 50 pF, VDD = 2.7 V to 3.6 V - 10 CL = 50 pF, VDD = 1.65 V to 2.7 V - 2 CL = 50 pF, VDD = 2.7 V to 3.6 V - 13 CL = 50 pF, VDD = 1.65 V to 2.7 V - 28 CL = 30 pF, VDD = 2.7 V to 3.6 V - 35 CL = 50 pF, VDD = 1.65 V to 2.7 V - 10 CL = 30 pF, VDD = 2.7 V to 3.6 V - 6 CL = 50 pF, VDD = 1.65 V to 2.7 V - 17 - 1 - 10 Parameter tf(IO)out tr(IO)out Output rise and fall time fmax(IO)out Maximum frequency(3) Conditions tf(IO)out Output fall time tr(IO)out Output rise time - 30 Maximum frequency(3) - 350 - 15 - 60 8 - fmax(IO)out CL = 50 pF, VDD = 2.5 V to 3.6 V tf(IO)out Output fall time CL = 50 pF, VDD = 1.65 V to 3.6 V tr(IO)out Output rise time tEXTIpw Pulse width of external signals detected by the EXTI controller - Unit kHz ns MHz ns MHz ns MHz ns MHz ns KHz ns ns 1. The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the line reference manual for a description of GPIO Port configuration register. 2. Guaranteed by design. 3. The maximum frequency is defined in Figure 28. 4. When Fm+ configuration is set, the I/O speed control is bypassed. Refer to the line reference manual for a detailed description of Fm+ I/O configuration. DS10690 Rev 7 95/148 112 Electrical characteristics STM32L071xx Figure 28. I/O AC characteristics definition 90% 10% 50% 50% 90% 10% EXTERNAL OUTPUT ON CL tr(IO)out tf(IO)out T Maximum frequency is achieved if (tr + tf) (2/3)T and if the duty cycle is (45-55%) when loaded by CL specified in the table " I/O AC characteristics". ai14131d 6.3.14 NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU , except when it is internally driven low (see Table 61). Unless otherwise specified, the parameters given in Table 61 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 25. Table 61. NRST pin characteristics Symbol VIL(NRST) (1) Parameter Conditions Min Typ NRST input low level voltage - VSS - 0.8 - 1.4 - VDD IOL = 2 mA 2.7 V < VDD < 3.6 V - - IOL = 1.5 mA 1.65 V < VDD < 2.7 V - - - - 10%VDD(2) - mV Weak pull-up equivalent resistor(3) VIN = VSS 25 45 65 k NRST input filtered pulse - - - 50 ns NRST input not filtered pulse - 350 - - ns VIH(NRST)(1) NRST input high level voltage NRST output low level VOL(NRST)(1) voltage Vhys(NRST)(1) RPU VF(NRST)(1) VNF(NRST) (1) NRST Schmitt trigger voltage hysteresis Max Unit V 0.4 1. Guaranteed by design. 2. 200 mV minimum value 3. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance is around 10%. 96/148 DS10690 Rev 7 STM32L071xx Electrical characteristics Figure 29. Recommended NRST pin protection ([WHUQDO UHVHWFLUFXLW 9'' 538 1567 ,QWHUQDOUHVHW )LOWHU ) 069 1. The reset network protects the device against parasitic resets. 2. The external capacitor must be placed as close as possible to the device. 3. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 61. Otherwise the reset will not be taken into account by the device. 6.3.15 12-bit ADC characteristics Unless otherwise specified, the parameters given in Table 62 are derived from tests performed under ambient temperature, fPCLK frequency and VDDA supply voltage conditions summarized in Table 25: General operating conditions. Note: It is recommended to perform a calibration after each power-up. Table 62. ADC characteristics Symbol Parameter Conditions Min Typ Max Unit VDDA Analog supply voltage for ADC ON Fast channel 1.65 - 3.6 Standard channel 1.75(1) - 3.6 VREF+ Positive reference voltage - 1.65 VREF- Negative reference voltage - - 0 - Current consumption of the ADC on VDDAand VREF+ 1.14 Msps - 200 - 10 ksps - 40 - Current consumption of the ADC on VDD(2) 1.14 Msps - 70 - 10 ksps - 1 - Voltage scaling Range 1 0.14 - 16 Voltage scaling Range 2 0.14 - 8 Voltage scaling Range 3 0.14 - 4 Sampling rate 12-bit resolution 0.01 - 1.14 MHz External trigger frequency fADC = 16 MHz, 12-bit resolution - - 941 kHz - - - 17 1/fADC - 0 - VREF+ V IDDA (ADC) fADC fS(3) fTRIG(3) VAIN ADC clock frequency Conversion voltage range DS10690 Rev 7 VDDA V V A MHz 97/148 112 Electrical characteristics STM32L071xx Table 62. ADC characteristics (continued) Symbol Conditions Min Typ Max Unit See Equation 1 and Table 63 for details - - 50 k Sampling switch resistance - - - 1 k CADC(3) Internal sample and hold capacitor - - - 8 pF tCAL(3)(5) Calibration time RAIN(3) RADC(3)(4) Parameter External input impedance fADC = 16 MHz 5.2 s - 83 1/fADC 1.5 ADC cycles + 2 fPCLK cycles - 1.5 ADC cycles + 3 fPCLK cycles - ADC clock = PCLK/2 - 4.5 - fPCLK cycle ADC clock = PCLK/4 - 8.5 - fPCLK cycle ADC clock = HSI16 WLATENCY(6) tlatr(3) JitterADC tS(3) tUP_LDO(3)(5) tSTAB(3)(5) tConV (3) ADC_DR register write latency Trigger conversion latency fADC = fPCLK/2 = 16 MHz 0.266 s fADC = fPCLK/2 8.5 1/fPCLK fADC = fPCLK/4 = 8 MHz 0.516 s fADC = fPCLK/4 16.5 1/fPCLK fADC = fHSI16 = 16 MHz 0.252 - 0.260 s fADC = fHSI16 - 1 - 1/fHSI16 fADC = 16 MHz 0.093 - 10.03 s - 1.5 - 160.5 1/fADC Internal LDO power-up time - - - 10 s ADC stabilization time - ADC jitter on trigger conversion Sampling time Total conversion time (including sampling time) fADC = 16 MHz, 12-bit resolution 12-bit resolution 14 0.875 - 1/fADC 10.81 14 to 173 (tS for sampling +12.5 for successive approximation) s 1/fADC 1. VDDA minimum value can be decreased in specific temperature conditions. Refer to Table 63: RAIN max for fADC = 16 MHz. 2. A current consumption proportional to the APB clock frequency has to be added (see Table 39: Peripheral current consumption in Run or Sleep mode). 3. Guaranteed by design. 4. Standard channels have an extra protection resistance which depends on supply voltage. Refer to Table 63: RAIN max for fADC = 16 MHz. 5. This parameter only includes the ADC timing. It does not take into account register access latency. 6. This parameter specifies the latency to transfer the conversion result into the ADC_DR register. EOC bit is set to indicate the conversion is complete and has the same latency. 98/148 DS10690 Rev 7 STM32L071xx Electrical characteristics Equation 1: RAIN max formula TS - - R ADC R AIN < --------------------------------------------------------------N+2 f ADC x C ADC x ln ( 2 ) The simplified formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution). Table 63. RAIN max for fADC = 16 MHz(1) Ts (cycles) tS (s) RAIN max for fast channels (k) 1.5 0.09 3.5 RAIN max for standard channels (k) VDD > 1.65 V VDD > 1.65 V and and TA > -10 C TA > 25 C VDD > 2.7 V VDD > 2.4 V VDD > 2.0 V VDD > 1.8 V VDD > 1.75 V 0.5 < 0.1 NA NA NA NA NA NA 0.22 1 0.2 < 0.1 NA NA NA NA NA 7.5 0.47 2.5 1.7 1.5 < 0.1 NA NA NA NA 12.5 0.78 4 3.2 3 1 NA NA NA NA 19.5 1.22 6.5 5.7 5.5 3.5 NA NA NA < 0.1 39.5 2.47 13 12.2 12 10 NA NA NA 5 79.5 4.97 27 26.2 26 24 < 0.1 NA NA 19 160.5 10.03 50 49.2 49 47 32 < 0.1 < 0.1 42 1. Guaranteed by design. Table 64. ADC accuracy(1)(2)(3) Symbol Parameter Conditions Min Typ Max ET Total unadjusted error - 2 4 EO Offset error - 1 2.5 EG Gain error - 1 2 EL Integral linearity error - 1.5 2.5 ED Differential linearity error - 1 1.5 10.2 11 11.3 12.1 - Effective number of bits 1.65 V < VDDA = VREF+< 3.6 V, range 1/2/3 ENOB Effective number of bits (16-bit mode oversampling with ratio =256)(4) SINAD Signal-to-noise distortion 63 69 - Signal-to-noise ratio 63 69 - SNR Signal-to-noise ratio (16-bit mode oversampling with ratio =256)(4) 70 76 - THD Total harmonic distortion - -85 -73 DS10690 Rev 7 Unit LSB bits dB 99/148 112 Electrical characteristics STM32L071xx Table 64. ADC accuracy(1)(2)(3) (continued) Symbol Parameter Conditions Min Typ Max ET Total unadjusted error - 2 5 EO Offset error - 1 2.5 EG Gain error - 1 2 EL Integral linearity error - 1.5 3 - 1 2 1.65 V < VREF+ <VDDA < 3.6 V, range 1/2/3 ED Differential linearity error ENOB Effective number of bits 10.0 11.0 - SINAD Signal-to-noise distortion 62 69 - SNR Signal-to-noise ratio 61 69 - THD Total harmonic distortion - -85 -65 Unit LSB bits dB 1. ADC DC accuracy values are measured after internal calibration. 2. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (non-robust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 6.3.12 does not affect the ADC accuracy. 3. Better performance may be achieved in restricted VDDA, frequency and temperature ranges. 4. This number is obtained by the test board without additional noise, resulting in non-optimized value for oversampling mode. Figure 30. ADC accuracy characteristics VSSA EG (1) Example of an actual transfer curve (2) The ideal transfer curve (3) End point correlation line 4095 4094 4093 (2) ET (3) 7 (1) 6 5 EO EL 4 3 ED 2 1 LSB IDEAL 1 0 1 2 3 4 5 6 7 ET = total unajusted error: maximum deviation between the actual and ideal transfer curves. EO = offset error: maximum deviation between the first actual transition and the first ideal one. EG = gain error: deviation between the last ideal transition and the last actual one. ED = differential linearity error: maximum deviation between actual steps and the ideal ones. EL = integral linearity error: maximum deviation between any actual transition and the end point correlation line. 4093 4094 4095 4096 VDDA MS19880V2 100/148 DS10690 Rev 7 STM32L071xx Electrical characteristics Figure 31. Typical connection diagram using the ADC VDDA VT RAIN(1) VAIN AINx Cparasitic VT Sample and hold ADC converter RADC 12-bit converter IL50nA CADC MSv34712V1 1. Refer to Table 62: ADC characteristics for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy this, fADC should be reduced. General PCB design guidelines Power supply decoupling should be performed as shown in Figure 32 or Figure 33, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed as close as possible to the chip. Figure 32. Power supply and reference decoupling (VREF+ not connected to VDDA) STM32Lxx VREF+ 1 F // 100 nF VDDA 1 F // 100 nF VSSA / VREF- MS39601V1 DS10690 Rev 7 101/148 112 Electrical characteristics STM32L071xx Figure 33. Power supply and reference decoupling (VREF+ connected to VDDA) STM32Lxx VREF+/VDDA 1 F // 100 nF VREF-/VSSA MS39602V1 6.3.16 Temperature sensor characteristics Table 65. Temperature sensor calibration values Calibration value name Description Memory address TS_CAL1 TS ADC raw data acquired at temperature of 30 C, VDDA= 3 V TS_CAL2 TS ADC raw data acquired at 0x1FF8 007E - 0x1FF8 007F temperature of 130 C, VDDA= 3 V 0x1FF8 007A - 0x1FF8 007B Table 66. Temperature sensor characteristics Symbol TL(1) Avg_Slope Parameter VSENSE linearity with temperature (1) Average slope 5C(2) Min Typ Max Unit - 1 2 C 1.48 1.61 1.75 mV/C 640 670 700 mV A V130 Voltage at 130C IDDA(TEMP)(3) Current consumption - 3.4 6 tSTART(3) Startup time - - 10 TS_temp(4)(3) ADC sampling time when reading the temperature 10 - - 1. Guaranteed by characterization results. 2. Measured at VDD = 3 V 10 mV. V130 ADC conversion result is stored in the TS_CAL2 byte. 3. Guaranteed by design. 4. Shortest sampling time can be determined in the application by multiple iterations. 102/148 DS10690 Rev 7 s STM32L071xx 6.3.17 Electrical characteristics Comparators Table 67. Comparator 1 characteristics Conditions Min(1) Analog supply voltage - 1.65 Comparator 1 input voltage range - 0.6 Comparator startup time - Symbol VDDA VIN tSTART Parameter (2) Max(1) Unit 3.6 V - VDDA V - 7 10 Typ s td Propagation delay - - 3 10 Voffset Comparator offset - - 3 10 mV Comparator offset variation in VDDA = 3.6 V, VIN+ = 0 V, worst voltage stress conditions VIN- = VREFINT, TA = 25 C 0 1.5 10 mV/1000 h Current consumption(3) - 160 260 nA dVoffset/dt ICOMP1 - 1. Guaranteed by characterization. 2. The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input, the non-inverting input set to the reference. 3. Comparator consumption only. Internal reference voltage not included. Table 68. Comparator 2 characteristics Symbol VDDA VIN Conditions Min Typ Max(1) Unit Analog supply voltage - 1.65 - 3.6 V Comparator 2 input voltage range - 0 - VDDA V Fast mode - 15 20 Slow mode - 20 25 1.65 V VDDA 2.7 V - 1.8 3.5 2.7 V VDDA 3.6 V - 2.5 6 1.65 V VDDA 2.7 V - 0.8 2 2.7 V VDDA 3.6 V - 1.2 4 - 4 20 mV VDDA = 3.3V, TA = 0 to 50 C, V- = VREFINT, 3/4 VREFINT, 1/2 VREFINT, 1/4 VREFINT. - 15 30 ppm /C Fast mode - 3.5 5 Slow mode - 0.5 2 Parameter tSTART Comparator startup time td slow Propagation delay(2) in slow mode td fast Propagation delay(2) in fast mode Voffset Comparator offset error dThreshold/ dt ICOMP2 Threshold voltage temperature coefficient Current consumption(3) s A 1. Guaranteed by characterization results. 2. The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input, the non-inverting input set to the reference. 3. Comparator consumption only. Internal reference voltage (required for comparator operation) is not included. DS10690 Rev 7 103/148 112 Electrical characteristics 6.3.18 STM32L071xx Timer characteristics TIM timer characteristics The parameters given in the Table 69 are guaranteed by design. Refer to Section 6.3.13: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 69. TIMx characteristics(1) Symbol Parameter tres(TIM) Conditions Timer resolution time fTIMxCLK = 32 MHz Timer external clock frequency on CH1 to CH4 fEXT ResTIM tCOUNTER fTIMxCLK = 32 MHz Timer resolution - 16-bit counter clock period when internal clock is selected (timer's prescaler disabled) - Min Max Unit 1 - tTIMxCLK 31.25 - ns 0 fTIMxCLK/2 MHz 0 16 MHz 16 bit 65536 tTIMxCLK 2048 s 1 fTIMxCLK = 32 MHz 0.0312 tMAX_COUNT Maximum possible count - - 65536 x 65536 tTIMxCLK fTIMxCLK = 32 MHz - 134.2 s 1. TIMx is used as a general term to refer to the TIM2, TIM6, TIM21, and TIM22 timers. 6.3.19 Communications interfaces I2C interface characteristics The I2C interface meets the timings requirements of the I2C-bus specification and user manual rev. 03 for: * Standard-mode (Sm) : with a bit rate up to 100 kbit/s * Fast-mode (Fm) : with a bit rate up to 400 kbit/s * Fast-mode Plus (Fm+) : with a bit rate up to 1 Mbit/s. The I2C timing requirements are guaranteed by design when the I2C peripheral is properly configured (refer to the reference manual for details). The SDA and SCL I/O requirements are met with the following restrictions: the SDA and SCL I/O pins are not "true" open-drain. When configured as open-drain, the PMOS connected between the I/O pin and VDDIOx is disabled, but is still present. Only FTf I/O pins support Fm+ low level output current maximum requirement (refer to Section 6.3.13: I/O port characteristics for the I2C I/Os characteristics). All I2C SDA and SCL I/Os embed an analog filter (see Table 70 for the analog filter characteristics). 104/148 DS10690 Rev 7 STM32L071xx Electrical characteristics The analog spike filter is compliant with I2C timings requirements only for the following voltage ranges: * Fast mode Plus: 2.7 V VDD 3.6 V and voltage scaling Range 1 * Fast mode: - 2 V VDD 3.6 V and voltage scaling Range 1 or Range 2. - VDD < 2 V, voltage scaling Range 1 or Range 2, Cload < 200 pF. In other ranges, the analog filter should be disabled. The digital filter can be used instead. Note: In Standard mode, no spike filter is required. Table 70. I2C analog filter characteristics(1) Symbol Parameter Conditions Min Max Range 1 tAF Maximum pulse width of spikes that are suppressed by the analog filter Unit 100(3) 50(2) Range 2 - Range 3 ns - 1. Guaranteed by characterization results. 2. Spikes with widths below tAF(min) are filtered. 3. Spikes with widths above tAF(max) are not filtered SPI characteristics Unless otherwise specified, the parameters given in the following tables are derived from tests performed under ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 25. Refer to Section 6.3.12: I/O current injection characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO). Table 71. SPI characteristics in voltage Range 1 (1) Symbol Parameter Conditions Min Typ Master mode Duty(SCK) SPI clock frequency Duty cycle of SPI clock frequency - Slave mode Transmitter 1.71<VDD<3.6V - - 12(2) Slave mode Transmitter 2.7<VDD<3.6V - - 16(2) Slave mode 30 50 70 DS10690 Rev 7 Unit 16 - Slave mode receiver fSCK 1/tc(SCK) Max 16 MHz % 105/148 112 Electrical characteristics STM32L071xx Table 71. SPI characteristics in voltage Range 1 (1) (continued) Symbol Parameter Conditions Min Typ Max tsu(NSS) NSS setup time Slave mode, SPI presc = 2 4*Tpclk - - th(NSS) NSS hold time Slave mode, SPI presc = 2 2*Tpclk - - tw(SCKH) tw(SCKL) SCK high and low time Master mode Tpclk-2 Tpclk Tpclk+ 2 Master mode 0 - - Slave mode 3 - - Master mode 7 - - Slave mode 3.5 - - tsu(MI) tsu(SI) th(MI) th(SI) Data input setup time Data input hold time ta(SO Data output access time Slave mode 15 - 36 tdis(SO) Data output disable time Slave mode 10 - 30 Slave mode 1.65 V<VDD<3.6 V - 18 41 Slave mode 2.7 V<VDD<3.6 V - 18 25 Master mode - 4 7 Slave mode 10 - - Master mode 0 - - tv(SO) Data output valid time tv(MO) th(SO) th(MO) Data output hold time Unit ns 1. Guaranteed by characterization results. 2. The maximum SPI clock frequency in slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit into SCK low or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master having tsu(MI) = 0 while Duty(SCK) = 50%. 106/148 DS10690 Rev 7 STM32L071xx Electrical characteristics Table 72. SPI characteristics in voltage Range 2 (1) Symbol Parameter Conditions Min Typ Master mode fSCK 1/tc(SCK) SPI clock frequency Slave mode Transmitter 1.65<VDD<3.6V Max Unit 8 - - Slave mode Transmitter 2.7<VDD<3.6V 8 MHz 8(2) Duty(SCK) Duty cycle of SPI clock frequency Slave mode 30 50 70 tsu(NSS) NSS setup time Slave mode, SPI presc = 2 4*Tpclk - - th(NSS) NSS hold time Slave mode, SPI presc = 2 2*Tpclk - - tw(SCKH) tw(SCKL) SCK high and low time Master mode Tpclk-2 Tpclk Tpclk+2 Master mode 0 - - Slave mode 3 - - Master mode 11 - - Slave mode 4.5 - - tsu(MI) tsu(SI) th(MI) th(SI) Data input setup time Data input hold time ta(SO Data output access time Slave mode 18 - 52 tdis(SO) Data output disable time Slave mode 12 - 42 Slave mode - 20 56.5 Master mode - 5 9 Slave mode 13 - - Master mode 3 - - tv(SO) Data output valid time tv(MO) th(SO) th(MO) Data output hold time % ns 1. Guaranteed by characterization results. 2. The maximum SPI clock frequency in slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit into SCK low or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master having tsu(MI) = 0 while Duty(SCK) = 50%. DS10690 Rev 7 107/148 112 Electrical characteristics STM32L071xx Table 73. SPI characteristics in voltage Range 3 (1) Symbol Parameter fSCK 1/tc(SCK) SPI clock frequency Duty(SCK) Duty cycle of SPI clock frequency tsu(NSS) Min Typ - - Slave mode 30 50 70 NSS setup time Slave mode, SPI presc = 2 4*Tpclk - - th(NSS) NSS hold time Slave mode, SPI presc = 2 2*Tpclk - - tw(SCKH) tw(SCKL) SCK high and low time Master mode Tpclk-2 Tpclk Tpclk+2 Master mode 1.5 - - Slave mode 6 - - Master mode 13.5 - - Slave mode 16 - - tsu(MI) tsu(SI) th(MI) th(SI) Data input setup time Data input hold time Conditions Master mode Slave mode Max 2 2(2) ta(SO Data output access time Slave mode 30 - 70 tdis(SO) Data output disable time Slave mode 40 - 80 Slave mode - 30 70 Master mode - 7 9 Slave mode 25 - - Master mode 8 - - tv(SO) Data output valid time tv(MO) th(SO) th(MO) Data output hold time Unit MHz % ns 1. Guaranteed by characterization results. 2. The maximum SPI clock frequency in slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit into SCK low or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master having tsu(MI) = 0 while Duty(SCK) = 50%. 108/148 DS10690 Rev 7 STM32L071xx Electrical characteristics Figure 34. SPI timing diagram - slave mode and CPHA = 0 NSS input tc(SCK) SCK input tsu(NSS) th(NSS) tw(SCKH) tr(SCK) CPHA=0 CPOL=0 CPHA=0 CPOL=1 ta(SO) tw(SCKL) tv(SO) th(SO) First bit OUT MISO output tf(SCK) Next bits OUT tdis(SO) Last bit OUT th(SI) tsu(SI) First bit IN MOSI input Next bits IN Last bit IN MSv41658V1 Figure 35. SPI timing diagram - slave mode and CPHA = 1(1) NSS input SCK input tc(SCK) tsu(NSS) tw(SCKH) ta(SO) tw(SCKL) tf(SCK) th(NSS) CPHA=1 CPOL=0 CPHA=1 CPOL=1 MISO output tv(SO) First bit OUT tsu(SI) MOSI input th(SO) Next bits OUT tr(SCK) tdis(SO) Last bit OUT th(SI) First bit IN Next bits IN Last bit IN MSv41659V1 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. DS10690 Rev 7 109/148 112 Electrical characteristics STM32L071xx Figure 36. SPI timing diagram - master mode(1) High NSS input SCK Output CPHA= 0 CPOL=0 SCK Output tc(SCK) CPHA=1 CPOL=0 CPHA= 0 CPOL=1 CPHA=1 CPOL=1 tsu(MI) MISO INP UT tw(SCKH) tw(SCKL) MSB IN tr(SCK) tf(SCK) BIT6 IN LSB IN th(MI) MOSI OUTPUT MSB OUT B I T1 OUT tv(MO) LSB OUT th(MO) ai14136d 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. 110/148 DS10690 Rev 7 STM32L071xx Electrical characteristics I2S characteristics Table 74. I2S characteristics(1) Symbol Parameter Conditions Min Max Unit fMCK I2S Main clock output - 256 x 8K 256xFs (2) MHz fCK I2S clock frequency Master data: 32 bits - 64xFs Slave data: 32 bits - 64xFs DCK I2S clock frequency duty cycle Slave receiver 30 70 tv(WS) WS valid time Master mode - 15 th(WS) WS hold time Master mode 11 - tsu(WS) WS setup time Slave mode 6 - th(WS) WS hold time Slave mode 2 - Master receiver 0 - Slave receiver 6.5 - Master receiver 18 - Slave receiver 15.5 - Slave transmitter (after enable edge) - 77 Master transmitter (after enable edge) - 8 Slave transmitter (after enable edge) 18 - Master transmitter (after enable edge) 1.5 - tsu(SD_MR) tsu(SD_SR) th(SD_MR) th(SD_SR) tv(SD_ST) tv(SD_MT) th(SD_ST) th(SD_MT) Data input setup time Data input hold time Data output valid time Data output hold time MHz % ns 1. Guaranteed by characterization results. 2. 256xFs maximum value is equal to the maximum clock frequency. Note: Refer to the I2S section of the product reference manual for more details about the sampling frequency (Fs), fMCK, fCK and DCK values. These values reflect only the digital peripheral behavior, source clock precision might slightly change them. DCK depends mainly on the ODD bit value, digital contribution leads to a min of (I2SDIV/(2*I2SDIV+ODD) and a max of (I2SDIV+ODD)/(2*I2SDIV+ODD). Fs max is supported for each mode/condition. DS10690 Rev 7 111/148 112 Electrical characteristics STM32L071xx Figure 37. I2S slave timing diagram (Philips protocol)(1) 1. Measurement points are done at CMOS levels: 0.3 x VDD and 0.7 x VDD. 2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. Figure 38. I2S master timing diagram (Philips protocol)(1) 1. Guaranteed by characterization results. 2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. 112/148 DS10690 Rev 7 STM32L071xx 7 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at www.st.com. ECOPACK is an ST trademark. LQFP100 package information Figure 39. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat package outline 0.25 mm c A1 A SEATING PLANE C A2 GAUGE PLANE D A1 K ccc C L D1 L1 D3 51 75 76 50 100 26 PIN 1 1 IDENTIFICATION E E3 E1 b 7.1 25 e 1L_ME_V5 1. Drawing is not to scale. Dimensions are in millimeters. Table 75. LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 DS10690 Rev 7 113/148 143 Package information STM32L071xx Table 75. LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 15.800 16.000 16.200 0.6220 0.6299 0.6378 D1 13.800 14.000 14.200 0.5433 0.5512 0.5591 D3 - 12.000 - - 0.4724 - E 15.800 16.000 16.200 0.6220 0.6299 0.6378 E1 13.800 14.000 14.200 0.5433 0.5512 0.5591 E3 - 12.000 - - 0.4724 - e - 0.500 - - 0.0197 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0.0 3.5 7.0 0.0 3.5 7.0 ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 40. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat recommended footprint 75 76 51 50 0.5 0.3 16.7 14.3 100 26 1.2 1 25 12.3 16.7 ai14906c 1. Dimensions are expressed in millimeters. 114/148 DS10690 Rev 7 STM32L071xx Package information Device marking for LQFP100 The following figure gives an example of topside marking versus pin 1 position identifier location. The printed markings may differ depending on the supply chain. Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below. Figure 41. LQFP100 marking example (package top view) Product identification(1) STM32L071 VZT6 R Revision code Date code Y WW Pin 1 indentifier MSv39395V1 1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. DS10690 Rev 7 115/148 143 Package information 7.2 STM32L071xx UFBGA100 package information Figure 42. UFBGA100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package outline Z Seating plane ddd Z A4 A3 A2 A1 A E1 A1 ball identifier Z e A1 ball index area X E A Z D1 D e Y M 12 1 BOTTOM VIEW Ob (100 balls) O eee M Z Y X O fff M Z TOP VIEW A0C2_ME_V5 1. Drawing is not to scale. Table 76. UFBGA100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package mechanical data inches(1) millimeters Symbol 116/148 Min. Typ. Max. Min. Typ. Max. A - - 0.600 - - 0.0236 A1 - - 0.110 - - 0.0043 A2 - 0.450 - - 0.0177 - A3 - 0.130 - - 0.0051 0.0094 A4 - 0.320 - - 0.0126 - b 0.240 0.290 0.340 0.0094 0.0114 0.0134 D 6.850 7.000 7.150 0.2697 0.2756 0.2815 D1 - 5.500 - - 0.2165 - E 6.850 7.000 7.150 0.2697 0.2756 0.2815 E1 - 5.500 - - 0.2165 - e - 0.500 - - 0.0197 - Z - 0.750 - - 0.0295 - DS10690 Rev 7 STM32L071xx Package information Table 76. UFBGA100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package mechanical data (continued) inches(1) millimeters Symbol Min. Typ. Max. Min. Typ. Max. ddd - - 0.080 - - 0.0031 eee - - 0.150 - - 0.0059 fff - - 0.050 - - 0.0020 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 43. UFBGA100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package recommended footprint Dpad Dsm A0C2_FP_V1 Table 77. UFBGA100 recommended PCB design rules (0.5 mm pitch BGA) Dimension Recommended values Pitch 0.5 Dpad 0.280 mm Dsm 0.370 mm typ. (depends on the soldermask registration tolerance) Stencil opening 0.280 mm Stencil thickness Between 0.100 mm and 0.125 mm DS10690 Rev 7 117/148 143 Package information 7.3 STM32L071xx LQFP64 package information Figure 44. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline 0.25 mm GAUGE PLANE c A1 A A2 SEATING PLANE C A1 ccc C D D1 D3 K L L1 33 48 32 49 64 PIN 1 IDENTIFICATION E E1 E3 b 17 16 1 e 5W_ME_V3 1. Drawing is not to scale. Table 78. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol 118/148 Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D - 12.000 - - 0.4724 - D1 - 10.000 - - 0.3937 - D3 - 7.500 - - 0.2953 - E - 12.000 - - 0.4724 - E1 - 10.000 - - 0.3937 - DS10690 Rev 7 STM32L071xx Package information Table 78. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max E3 - 7.500 - - 0.2953 - e - 0.500 - - 0.0197 - K 0 3.5 7 0 3.5 7 L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 45. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat recommended footprint 48 33 0.3 0.5 49 32 12.7 10.3 10.3 17 64 1.2 16 1 7.8 12.7 ai14909c 1. Dimensions are expressed in millimeters. DS10690 Rev 7 119/148 143 Package information STM32L071xx Device marking for LQFP64 The following figure gives an example of topside marking versus pin 1 position identifier location. The printed markings may differ depending on the supply chain. Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below. Figure 46. LQFP64 marking example (package top view) Revision code Product identification(1) R STM32L 071RBT6 Date code Y WW Pin 1 indentifier MSv39396V1 1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. 120/148 DS10690 Rev 7 STM32L071xx 7.4 Package information UFBGA64 package information Figure 47. UFBGA64 - 64-ball, 5 x 5 mm, 0.5 mm pitch ultra profile fine pitch ball grid array package outline Z Seating plane ddd Z A4 A3 A2 A1 A E1 e A1 ball A1 ball identifier index area F X E A F D1 D e Y H 8 1 BOTTOM VIEW Ob (64 balls) O eee M Z Y X O fff M Z TOP VIEW A019_ME_V1 1. Drawing is not to scale. Table 79. UFBGA64 - 64-ball, 5 x 5 mm, 0.5 mm pitch ultra profile fine pitch ball grid array package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.460 0.530 0.600 0.0181 0.0209 0.0236 A1 0.050 0.080 0.110 0.0020 0.0031 0.0043 A2 0.400 0.450 0.500 0.0157 0.0177 0.0197 A3 0.080 0.130 0.180 0.0031 0.0051 0.0071 A4 0.270 0.320 0.370 0.0106 0.0126 0.0146 b 0.170 0.280 0.330 0.0067 0.0110 0.0130 D 4.850 5.000 5.150 0.1909 0.1969 0.2028 D1 3.450 3.500 3.550 0.1358 0.1378 0.1398 E 4.850 5.000 5.150 0.1909 0.1969 0.2028 E1 3.450 3.500 3.550 0.1358 0.1378 0.1398 e - 0.500 - - 0.0197 - F 0.700 0.750 0.800 0.0276 0.0295 0.0315 DS10690 Rev 7 121/148 143 Package information STM32L071xx Table 79. UFBGA64 - 64-ball, 5 x 5 mm, 0.5 mm pitch ultra profile fine pitch ball grid array package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max ddd - - 0.080 - - 0.0031 eee - - 0.150 - - 0.0059 fff - - 0.050 - - 0.0020 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 48. UFBGA64 - 64-ball, 5 x 5 mm, 0.5 mm pitch ultra profile fine pitch ball grid array package recommended footprint Dpad Dsm A019_FP_V2 Table 80. UFBGA64 recommended PCB design rules (0.5 mm pitch BGA) Dimension 122/148 Recommended values Pitch 0.5 Dpad 0.280 mm Dsm 0.370 mm typ. (depends on the soldermask registration tolerance) Stencil opening 0.280 mm Stencil thickness Between 0.100 mm and 0.125 mm Pad trace width 0.100 mm DS10690 Rev 7 STM32L071xx 7.5 Package information TFBGA64 package information Figure 49. TFBGA64 - 64-ball, 5 x 5 mm, 0.5 mm pitch thin profile fine pitch ball grid array package outline E1 A E F e H F D D1 Ob (64 balls) O eee M C B A O fff M C A B e 1 A1 ball index area TOP VIEW A1 ball identifier 8 BOTTOM VIEW C Seating plane ddd C A4 A2 A1 A SIDE VIEW R8_ME_V4 1. Drawing is not to scale. Table 81. TFBGA64 - 64-ball, 5 x 5 mm, 0.5 mm pitch thin profile fine pitch ball grid array package outline inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.200 - - 0.0472 A1 0.150 - - 0.0059 - - A2 - 0.200 - - 0.0079 - A4 - - 0.600 - - 0.0236 b 0.250 0.300 0.350 0.0098 0.0118 0.0138 D 4.850 5.000 5.150 0.1909 0.1969 0.2028 D1 - 3.500 - - 0.1378 - E 4.850 5.000 5.150 0.1909 0.1969 0.2028 E1 - 3.500 - - 0.1378 - e - 0.500 - - 0.0197 - F - 0.750 - - 0.0295 - DS10690 Rev 7 123/148 143 Package information STM32L071xx Table 81. TFBGA64 - 64-ball, 5 x 5 mm, 0.5 mm pitch thin profile fine pitch ball grid array package outline (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max ddd - - 0.080 - - 0.0031 eee - - 0.150 - - 0.0059 fff - - 0.050 - - 0.0020 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 50. TFBGA64 - 64-ball, 5 x 5 mm, 0.5 mm pitch, thin profile fine pitch ball ,grid array recommended footprint Dpad Dsm R8_FP_V1 Table 82. TFBGA64 recommended PCB design rules (0.5 mm pitch BGA) Dimension 124/148 Recommended values Pitch 0.5 Dpad 0.280 mm Dsm 0.370 mm typ. (depends on the soldermask registration tolerance) Stencil opening 0.280 mm Stencil thickness Between 0.100 mm and 1.125 mm Pad trace width 0.100 mm DS10690 Rev 7 STM32L071xx Package information Device marking for TFBGA64 The following figure gives an example of topside marking versus ball A 1 position identifier location. The printed markings may differ depending on the supply chain. Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below. Figure 51. TFBGA64 marking example (package top view) Product identification(1) L071RZH6 Date code = Year + week Y WW Revision code R Ball A1 MSv39397V1 1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. DS10690 Rev 7 125/148 143 Package information 7.6 STM32L071xx WLCSP49 package information Figure 52. WLCSP49 - 49-pin, 3.294 x 3.258 mm, 0.4 mm pitch wafer level chip scale package outline e1 bbb Z F A1 ball location A1 G Detail A e2 E e e A D A2 Bottom view Bump side Side view A2 A3 b Bump Front view A1 eee Z Z b49x ccc ddd E ZXY Z Note 2 A1 Orientation reference Detail A (rotated 90 ) Seating plane Note 1 aaa D (4x) Top view Wafer back side A038_ME_V1 1. Drawing is not to scale. 126/148 DS10690 Rev 7 STM32L071xx Package information Table 83. WLCSP49 - 49-pin, 3.294 x 3.258 mm, 0.4 mm pitch wafer level chip scale package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.525 0.555 0.585 0.0207 0.0219 0.0230 A1 - 0.175 - - 0.0069 - A2 - 0.380 - - 0.0150 - - 0.025 - - 0.0010 - b(3) 0.220 0.250 0.280 0.0087 0.0098 0.0110 D 3.259 3.294 3.329 0.1283 0.1297 0.1311 E 3.223 3.258 3.293 0.1269 0.1283 0.1296 e - 0.400 - - 0.0157 - e1 - 2.400 - - 0.0945 - e2 - 2.400 - - 0.0945 - F - 0.447 - - 0.0176 - G - 0.429 - - 0.0169 - aaa - - 0.100 - - 0.0039 bbb - - 0.100 - - 0.0039 ccc - - 0.100 - - 0.0039 ddd - - 0.050 - - 0.0020 eee - - 0.050 - - 0.0020 A3 (2) 1. Values in inches are converted from mm and rounded to 4 decimal digits. 2. Back side coating 3. Dimension is measured at the maximum bump diameter parallel to primary datum Z. Figure 53. WLCSP49 - 49-pin, 3.294 x 3.258 mm, 0.4 mm pitch wafer level chip scale recommended footprint Dpad Dsm DS10690 Rev 7 MS18965V2 127/148 143 Package information STM32L071xx Table 84. WLCSP49 recommended PCB design rules (0.4 mm pitch) Dimension Recommended values Pitch 0.4 260 m max. (circular) Dpad 220 m recommended Dsm 300 m min. (for 260 m diameter pad) PCB pad design Non-solder mask defined via underbump allowed. Device marking for WLCSP49 The following figure gives an example of topside marking versus ball A 1 position identifier location. The printed markings may differ depending on the supply chain. Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below. Figure 54. WLCSP49 marking example (package top view) Ball 1 indentifier Product identification(1) L071CZ6 Date code Revision code Y WW R MSv39398V1 1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. 128/148 DS10690 Rev 7 STM32L071xx LQFP48 package information Figure 55. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline SEATING PLANE C c A1 A A2 0.25 mm GAUGE PLANE ccc C K D A1 L D1 L1 D3 36 25 37 24 48 PIN 1 IDENTIFICATION E E1 b E3 7.7 Package information 13 1 12 e 5B_ME_V2 1. Drawing is not to scale. DS10690 Rev 7 129/148 143 Package information STM32L071xx Table 85. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 8.800 9.000 9.200 0.3465 0.3543 0.3622 D1 6.800 7.000 7.200 0.2677 0.2756 0.2835 D3 - 5.500 - - 0.2165 - E 8.800 9.000 9.200 0.3465 0.3543 0.3622 E1 6.800 7.000 7.200 0.2677 0.2756 0.2835 E3 - 5.500 - - 0.2165 - e - 0.500 - - 0.0197 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0 3.5 7 0 3.5 7 ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 56. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat recommended footprint 0.50 1.20 36 9.70 0.30 25 37 24 0.20 7.30 5.80 7.30 48 13 12 1 1.20 5.80 9.70 ai14911d 1. Dimensions are expressed in millimeters. 130/148 DS10690 Rev 7 STM32L071xx Package information Device marking for LQFP48 The following figure gives an example of topside marking versus pin 1 position identifier location. The printed markings may differ depending on the supply chain. Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below. Figure 57. LQFP48 marking example (package top view) Product identification(1) STM32L 071CZT7 Date code Y WW Revision code Pin 1 indentifier R MSv36160V2 1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. DS10690 Rev 7 131/148 143 Package information 7.8 STM32L071xx UFQFPN48 package information Figure 58. UFQFPN48 - 48 leads, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package outline Pin 1 identifier laser marking area D A E E T ddd A1 Seating plane b e Detail Y D Exposed pad area Y D2 1 L 48 C 0.500x45 pin1 corner E2 R 0.125 typ. Detail Z 1 Z 48 A0B9_ME_V3 1. Drawing is not to scale. 2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life. 3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and solder this back-side pad to PCB ground. 132/148 DS10690 Rev 7 STM32L071xx Package information Table 86. UFQFPN48 - 48 leads, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.500 0.550 0.600 0.0197 0.0217 0.0236 A1 0.000 0.020 0.050 0.0000 0.0008 0.0020 D 6.900 7.000 7.100 0.2717 0.2756 0.2795 E 6.900 7.000 7.100 0.2717 0.2756 0.2795 D2 5.500 5.600 5.700 0.2165 0.2205 0.2244 E2 5.500 5.600 5.700 0.2165 0.2205 0.2244 L 0.300 0.400 0.500 0.0118 0.0157 0.0197 T - 0.152 - - 0.0060 - b 0.200 0.250 0.300 0.0079 0.0098 0.0118 e - 0.500 - - 0.0197 - ddd - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 59. UFQFPN48 - 48 leads, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package recommended footprint 7.30 6.20 48 37 1 36 5.60 0.20 7.30 5.80 6.20 5.60 0.30 12 25 13 24 0.50 0.55 5.80 0.75 A0B9_FP_V2 1. Dimensions are expressed in millimeters. DS10690 Rev 7 133/148 143 Package information STM32L071xx Device marking for UFQFPN48 The following figure gives an example of topside marking versus pin 1 position identifier location. The printed markings may differ depending on the supply chain. Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below. Figure 60. UFQFPN48 marking example (package top view) Product identification(1) STM32L071 CZU6 Date code Y WW Revision code Pin 1 indentifier R MSv62437V1 1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. 134/148 DS10690 Rev 7 STM32L071xx LQFP32 package information Figure 61. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package outline c A2 A1 A SEATING PLANE C 0.25 mm ccc GAUGE PLANE C K D A1 L D1 L1 D3 24 17 25 16 32 9 PIN 1 IDENTIFICATION 1 E E1 E3 b 7.9 Package information 8 e 5V_ME_V2 1. Drawing is not to scale. DS10690 Rev 7 135/148 143 Package information STM32L071xx Table 87. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.300 0.370 0.450 0.0118 0.0146 0.0177 c 0.090 - 0.200 0.0035 - 0.0079 D 8.800 9.000 9.200 0.3465 0.3543 0.3622 D1 6.800 7.000 7.200 0.2677 0.2756 0.2835 D3 - 5.600 - - 0.2205 - E 8.800 9.000 9.200 0.3465 0.3543 0.3622 E1 6.800 7.000 7.200 0.2677 0.2756 0.2835 E3 - 5.600 - - 0.2205 - e - 0.800 - - 0.0315 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0 3.5 7 0 3.5 7 ccc - - 0.100 - - 0.0039 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 62. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat recommended footprint 0.80 1.20 24 17 25 16 0.50 0.30 7.30 6.10 9.70 7.30 32 9 8 1 1.20 6.10 9.70 1. Dimensions are expressed in millimeters. 136/148 DS10690 Rev 7 5V_FP_V2 STM32L071xx Package information Device marking for LQFP32 The following figure gives an example of topside marking versus pin 1 position identifier location. The printed markings may differ depending on the supply chain. Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below. Figure 63. LQFP32 marking example (package top view) STM32L Product identification (1) 071KZT6 Date code Y WW Revision code Pin 1 indentifier R MSv37839V1 1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. DS10690 Rev 7 137/148 143 Package information 7.10 STM32L071xx UFQFPN32 package information Figure 64. UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat package outline D A e A1 A3 ddd C C SEATINGPLANE D1 b e E2 b E1 E 1 L 32 D2 PIN 1 Identifier L A0B8_ME_V3 1. Drawing is not to scale. 2. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and solder this backside pad to PCB ground. 138/148 DS10690 Rev 7 STM32L071xx Package information Table 88. UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.500 0.550 0.600 0.0197 0.0217 0.0236 A1 - - 0.050 - - 0.0020 A3 - 0.152 - - 0.0060 - b 0.180 0.230 0.280 0.0071 0.0091 0.0110 D 4.900 5.000 5.100 0.1929 0.1969 0.2008 D1 3.400 3.500 3.600 0.1339 0.1378 0.1417 D2 3.400 3.500 3.600 0.1339 0.1378 0.1417 E 4.900 5.000 5.100 0.1929 0.1969 0.2008 E1 3.400 3.500 3.600 0.1339 0.1378 0.1417 E2 3.400 3.500 3.600 0.1339 0.1378 0.1417 e - 0.500 - - 0.0197 - L 0.300 0.400 0.500 0.0118 0.0157 0.0197 ddd - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 65. UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat recommended footprint 5.30 3.80 25 32 1 0.60 24 3.45 3.80 5.30 3.45 0.50 0.30 8 17 16 9 3.80 0.75 A0B8_FP_V2 1. Dimensions are expressed in millimeters. DS10690 Rev 7 139/148 143 Package information STM32L071xx Device marking for UFQFPN32 The following figure gives an example of topside marking versus pin 1 position identifier location. The printed markings may differ depending on the supply chain. Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below. Figure 66. UFQFPN32 marking example (package top view) Product identification(1) L071KZ6 Date code Y WW Revision code R Pin 1 indentifier MSv36159V1 1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. 140/148 DS10690 Rev 7 STM32L071xx 7.11 Package information Thermal characteristics The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated using the following equation: TJ max = TA max + (PD max x JA) Where: * TA max is the maximum ambient temperature in C, * JA is the package junction-to-ambient thermal resistance, in C/W, * PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax), * PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power. PI/O max represents the maximum power dissipation on output pins where: PI/O max = (VOL x IOL) + ((VDD - VOH) x IOH), taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application. Table 89. Thermal characteristics Symbol JA Parameter Value Thermal resistance junction-ambient UFQFPN32 - 5 x 5 mm / 0.5 mm pitch 36 Thermal resistance junction-ambient LQFP32 - 7 x 7 mm / 0.8 mm pitch 60 Thermal resistance junction-ambient LQFP48 - 7 x 7 mm / 0.5 mm pitch 54 Thermal resistance junction-ambient UFQFPN48 - 7 x 7 mm / 0.5 mm pitch 28 Thermal resistance junction-ambient WLCSP49 - 0.4 mm pitch 48 Thermal resistance junction-ambient TFBGA64 - 5 x 5 mm / 0.5 mm pitch 64 Thermal resistance junction-ambient UFBGA64 - 5 x 5 mm / 0.5 mm pitch 65 Thermal resistance junction-ambient LQFP64 - 10 x 10 mm / 0.5 mm pitch 46 Thermal resistance junction-ambient28 LQFP100 - 14 x 14 mm / 0.5 mm pitch 41 Thermal resistance junction-ambient UFBGA100 - 7 x 7 mm / 0.5 mm pitch 57 DS10690 Rev 7 Unit C/W 141/148 143 Package information STM32L071xx Figure 67. Thermal resistance 4000 3500 LQFPN32 3000 UFQFPN48 UQFN32 LQFP48 2500 WLCSP49 2000 UFBGA64 1500 LQFP100 TFBGA64 PD (mW) LQFP64 UFBGA100 1000 500 0 125 100 75 50 25 0 Temperature (C) MSv37833V4 7.11.1 Reference document JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air). Available from www.jedec.org. 142/148 DS10690 Rev 7 STM32L071xx 8 Ordering information Ordering information Example: STM32 L 071 R 8 T 6 D TR Device family STM32 = Arm-based 32-bit microcontroller Product type L = Low power Device subfamily 071 = Access line Pin count K = 32 pins C = 48/49 pins R = 64 pins V = 100 pins Flash memory size 8 = 64 Kbytes B = 128 Kbytes Z = 192 Kbytes Package T = LQFP H = TFBGA I = UFBGA U = UFQFPN Y = Standard WLCSP pins Temperature range 6 = Industrial temperature range, -40 to 85 C 7 = Industrial temperature range, -40 to 105 C 3 = Industrial temperature range, -40 to 125 C Options No character = VDD range: 1.8 to 3.6 V and BOR enabled D = VDD range: 1.65 to 3.6 V and BOR disabled Packing TR = tape and reel No character = tray or tube For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST sales office. DS10690 Rev 7 143/148 143 Revision history 9 STM32L071xx Revision history Table 90. Document revision history Date Revision 02-Sep-2015 1 Initial release 2 Changed confidentiality level to public. Updated datasheet status to "production data". Modified ultra-low-power platform features on cover page. In Table 15: STM32L071xxx pin definition: - changed pin name to VDDIO2 for the following pins: UFQFPN32 pin 24, LQFP48 pin 36, LQFP64 pin 48, UFBGA64 pin E5, WLCSP49 pin A1, LQFP100 pin 75 and UFBGA100 pin G11. - Added note related to UFQFPN32. In Section 6: Electrical characteristics, updated notes related to values guaranteed by characterization. Updated |VSS| definition to include VREF- in Table 22: Voltage characteristics. Updated fTRIG and VAIN maximum value, added VREF+ and VREF- in Table 62: ADC characteristics. Added Section : Device marking for LQFP100. Updated Figure 42: UFBGA100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package outline and Table 75: LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat package mechanical data. Added Section : Device marking for LQFP100, Section : Device marking for LQFP64, Section : Device marking for TFBGA64 and Section : Device marking for WLCSP49. Updated Figure 60: UFQFPN48 marking example (package top view). 26-Oct-2015 144/148 Changes DS10690 Rev 7 STM32L071xx Revision history Table 90. Document revision history (continued) Date 22-Mar-2016 Revision Changes 3 Updated number of SPIs on cover page and in Table 2: Ultra-lowpower STM32L071xx device features and peripheral counts. Changed minimum comparator supply voltage to 1.65 V on cover page. Added number of fast and standard channels in Section 3.11: Analog-to-digital converter (ADC). Updated Section 3.15.2: Universal synchronous/asynchronous receiver transmitter (USART) and Section 3.15.4: Serial peripheral interface (SPI)/Inter-integrated sound (I2S) to mention the fact that USARTs with synchronous mode feature can be used as SPI master interfaces. Added baudrate allowing to wake up the MCU from Stop mode in Section 3.15.2: Universal synchronous/asynchronous receiver transmitter (USART) and Section 3.15.3: Low-power universal asynchronous receiver transmitter (LPUART). Changed VDDA minimum value to 1.65 V in Table 25: General operating conditions. Section 6.3.15: 12-bit ADC characteristics: - Table 62: ADC characteristics: Distinction made between VDDA for fast and standard channels; added note 1. Added note 4. related to RADC. Updated fTRIG. and VAIN maximum value. Updated tS and tCONV. Added VREF+. - Updated equation 1 description. - Updated Table 63: RAIN max for fADC = 16 MHz for fADC = 16 MHz and distinction made between fast and standard channels. Added Table 87: USART/LPUART characteristics. DS10690 Rev 7 145/148 147 Revision history STM32L071xx Table 90. Document revision history (continued) Date 14-Sep-2017 Revision 4 Changes Memories and I/Os moved after Core in Features. Table 2: Ultra-low-power STM32L071xx device features and peripheral counts: changed number of USART for LQFP32/UFQFPN32 and added note 3. Removed column "I/O operation" from Table 3: Functionalities depending on the operating power supply range and added note related to GPIO speed. In Section 5: Memory mapping, replaced memory mapping schematic by reference to the reference manual. Update note related to PA11/12 below Figure 3: STM32L071xx LQFP100 pinout, Figure 4: STM32L071xx UFBGA100 ballout, Figure 5: STM32L071xx LQFP64 pinout, Figure 6: STM32L071xx UFBGA64/TFBGA64 ballout, Figure 7: STM32L071xx WLCSP49 ballout, Figure 8: STM32L071xx LQFP48 pinout and Figure 11: STM32L071xx UFQFPN32 pinout. Updated Figure 7: STM32L071xx WLCSP49 ballout. Added mission profile compliance with JEDEC JESD47 in Section 6.2: Absolute maximum ratings. Removed CRS from Table 39: Peripheral current consumption in Run or Sleep mode. Updated minimum and maximum values of I/O weak pull-up equivalent resistor (RPU) and weak pull-down equivalent resistor (RPD) in Table 58: I/O static characteristics. Updated minimum and maximum values of NRST weak pull-up equivalent resistor (RPU) in Table 61: NRST pin characteristics. Added note 2. related to the position of the external capacitor below Figure 29: Recommended NRST pin protection. Updated RAIN in Table 62: ADC characteristics. Updated tAF maximum value for range 1 in Table 70: I2C analog filter characteristics. Removed Table 90: USART/LPUART characteristics. NSS timing waveforms updated in Figure 34: SPI timing diagram slave mode and CPHA = 0 and Figure 35: SPI timing diagram - slave mode and CPHA = 1(1). Updated Figure 49: TFBGA64 - 64-ball, 5 x 5 mm, 0.5 mm pitch thin profile fine pitch ball grid array package outline. Added reference to optional marking or inset/upset marks in all package device marking sections. Updated note below marking schematics. 146/148 DS10690 Rev 7 STM32L071xx Revision history Table 90. Document revision history (continued) Date Revision Changes 07-May-2018 5 Updated Arm logo and added Arm word mark notice in Section 1: Introduction. Removed Cortex logo. Updated Table 5: Functionalities depending on the working mode (from Run/active down to standby) to change I2C functionality to disabled in Low-power Run and Low-power Sleep modes. Section 4: Pin descriptions: - Changed PC14-OSC_IN into PC14-OSC32_IN in Figure 11: STM32L071xx UFQFPN32 pinout. - Extended Figure 6 to UFBGA64. - Added UFBGA64 in Table 15: STM32L071xxx pin definition (same pinout as TFBGA64 - Swapped E5 and E6 signals for UFBGA64/TFBGA64. - Changed USARTx_RTS, USARTx_RTS_DE into USARTx_RTS/USARTx_DE, and LPUART1_RTS, LPUART1_RTS_DE into LPUART1_RTS/LPUART1_DE in Table 15: STM32L071xxx pin definition and in all alternate function tables. Updated power dissipation (PD) in Table 25: General operating conditions to add UFBGA64 package. Updated tAF maximum value for range 1 in Table 70: I2C analog filter characteristics. Added Section 7.4: UFBGA64 package information. Added UFBGA64 in Table 89: Thermal characteristics and Figure 67: Thermal resistance Updated Figure 64: UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat package outline and added note related to exposed pad; updated Table 88: UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat package mechanical data. Updated Figure 49: TFBGA64 - 64-ball, 5 x 5 mm, 0.5 mm pitch thin profile fine pitch ball grid array package outline, Figure 50: TFBGA64 - 64-ball, 5 x 5 mm, 0.5 mm pitch, thin profile fine pitch ball ,grid array recommended footprint and Figure 82: TFBGA64 recommended PCB design rules (0.5 mm pitch BGA). 31-Aug-2018 6 Updated Table 15: STM32L071xxx pin definition. Added UFQFPN48 package. 14-Nov-2019 7 Removed R10K and R400K from Table 67: Comparator 1 characteristics. Updated paragraph introducing all package marking schematics to add the new sentence "The printed markings may differ depending on the supply chain." DS10690 Rev 7 147/148 147 STM32L071xx IMPORTANT NOTICE - PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST's terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers' products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. (c) 2019 STMicroelectronics - All rights reserved 148/148 DS10690 Rev 7