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FEATURES
DESCRIPTION/ORDERING INFORMATION
PCA9544A4-CHANNEL I
2
C AND SMBus MULTIPLEXER
WITH INTERRUPT LOGIC
SCPS146A OCTOBER 2005 REVISED OCTOBER 2005
1-of-4 Bidirectional Translating Switches No Glitch on Power UpI
2
C Bus and SMBus Compatible Supports Hot InsertionFour Active-Low Interrupt Inputs Low Standby CurrentActive-Low Interrupt Output Operating Power-Supply Voltage Range of2.3 V to 5.5 VThree Address Pins, Allowing up to EightDevices on the I
2
C Bus 5.5-V Tolerant InputsChannel Selection Via I
2
C Bus 0 to 400-kHz Clock FrequencyPower Up With All Switch Channels Latch-Up Performance Exceeds 100 mA PerDeselected JESD 78Low R
ON
Switches ESD Protection Exceeds JESD 22Allows Voltage-Level Translation Between 2000-V Human-Body Model (A114-A)1.8-V, 2.5-V, 3.3-V, and 5-V Buses
200-V Machine Model (A115-A) 1000-V Charged-Device Model (C101)
The PCA9544A is a quad bidirectional translating switch controlled via the I
2
C bus. The SCL/SDA upstream pairfans out to four downstream pairs, or channels. One SCL/SDA pair can be selected at a time, and this isdetermined by the contents of the programmable control register. Four interrupt inputs ( INT3– INT0), one for eachof the downstream pairs, are provided. One interrupt output ( INT) acts as an AND of the four interrupt inputs.
A power-on reset function puts the registers in their default state and initializes the I
2
C state machine, with nochannel selected.
The pass gates of the switches are constructed such that the V
CC
pin can be used to limit the maximum highvoltage, which will be passed by the PCA9544A. This allows the use of different bus voltages on each pair, sothat 1.8-V, 2.5-V, or 3.3-V parts can communicate with 5-V parts, without any additional protection. Externalpullup resistors pull the bus up to the desired voltage level for each channel. All I/O pins are 5-V tolerant.
ORDERING INFORMATION
T
A
PACKAGE
(1)
ORDERABLE PART NUMBER TOP-SIDE MARKING
QFN RGW Reel of 3000 PCA9544ARGWR PREVIEWQFN RGY Reel of 1000 PCA9544ARGYR PD544ATube of 25 PCA9544ADW
PCA9544ASOIC DW Reel of 2000 PCA9544ADWRReel of 250 PCA9544ADWT PREVIEWTube of 70 PCA9544APW–40 °C to 85 °C
TSSOP PW Reel of 2000 PCA9544APWR PD544AReel of 250 PCA9544APWTReel of 2000 PCA9544ADGVR PD544ATVSOP DGV
Reel of 250 PCA9544ADGVT PREVIEWVFBGA GQN Reel of 1000 PCA9544AGQNR PD544AVFBGA ZQN (Pb-free) Reel of 1000 PCA9544AZQNR PD544A
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available atwww.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2005, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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DGV, DW, OR PW PACKAGE
(TOP VIEW) RGY PACKAGE
(TOP VIEW)
1 20
10 11
2
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
SDA
SCL
INT
SC3
SD3
INT3
SC2
SD2
A1
A2
INT0
SD0
SC0
INT1
SD1
SC1
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
A0
A1
A2
INT0
SD0
SC0
INT1
SD1
SC1
GND
VCC
SDA
SCL
INT
SC3
SD3
INT3
SC2
SD2
INT2
A0
GND INT2
VCC
20
6 8 9 10
1
2
3
4
5
15
14
13
12
11
INT2
SD2
SD1
SC1
GND
19
A2
INT0
SD0
SC0
INT1
INT
SC3
SD3
INT3
SC2
RGW PACKAGE
(TOP VIEW)
18 17 16
7
SDA
SCL
A1
A0
VCC
GQN OR ZQN PACKAGE
(TOP VIEW)
1 2 3 4
A
B
C
D
E
PCA9544A
4-CHANNEL I
2
C AND SMBus MULTIPLEXERWITH INTERRUPT LOGIC
SCPS146A OCTOBER 2005 REVISED OCTOBER 2005
PIN DESCRIPTION
PIN NO.
NAME FUNCTIONDGV, DW, PW,
RGWAND RGY
1 19 A0 Address input 02 20 A1 Address input 13 1 A2 Address input 24 2 INT0 Active-low interrupt input 05 3 SD0 Serial data 06 4 SC0 Serial clock 07 5 INT1 Active-low interrupt input 18 6 SD1 Serial data 19 7 SC1 Serial clock 110 8 GND Ground11 9 INT2 Active-low interrupt input 212 10 SD2 Serial data 213 11 SC2 Serial clock 214 12 INT3 Active-low interrupt input 315 13 SD3 Serial data 316 14 SC3 Serial clock 317 15 INT Active-low interrupt output18 16 SCL Serial clock line19 17 SDA Serial data line20 18 V
CC
Supply power
TERMINAL ASSIGNMENTS
1 2 3 4
AA1 A0 V
CC
SDA
BINT0 INT A2 SCL
CSC0 SD0 SD3 SC3
DSD1 SC2 INT1 INT3
EGND SC1 INT2 SD2
2
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Switch Control Logic
I2C Bus Control
Interrupt Logic
Input Filter
Power-on Reset
PCA9544A
SC0
A1
A0
INT
INT0
SDA
SCL
GND
SD3
SD2
SD1
SD0
SC3
SC2
SC1
VCC
A2
6
9
13
16
5
8
12
15
10
20
18
19
1
2
3
17
INT1
INT2
INT3
4
7
11
14
Pin numbers shown are for DGV, DW, PW, and RGY packages.
Output
Filter
PCA9544A4-CHANNEL I
2
C AND SMBus MULTIPLEXER
WITH INTERRUPT LOGIC
SCPS146A OCTOBER 2005 REVISED OCTOBER 2005
BLOCK DIAGRAM
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Device Address
1 1 1 0A1A2 A0
Slave Address
R/W
Fixed Hardware
Selectable
Control Register
Interrupt Bits
(Read Only) Channel-Selection Bits
(Read/Write)
Enable Bit
INT3 INT2 INT1 INT0 B2 B1 B0
7 6 54 3 2 1 0
X
INT1
INT3
INT2
INT0
Control Register Definition
PCA9544A
4-CHANNEL I
2
C AND SMBus MULTIPLEXERWITH INTERRUPT LOGIC
SCPS146A OCTOBER 2005 REVISED OCTOBER 2005
Following a start condition, the bus master must output the address of the slave it is accessing. The address ofthe PCA9544A is shown in Figure 1 . To conserve power, no internal pullup resistors are incorporated on thehardware-selectable address pins, and they must be pulled high or low.
Figure 1. PCA9544A Address
The last bit of the slave address defines the operation to be performed. When set to a logic 1, a read is selected,while a logic 0 selects a write operation.
Following the successful acknowledgment of the slave address, the bus master sends a byte to the PCA9544A,which is stored in the control register. If multiple bytes are received by the PCA9544A, it saves the last bytereceived. This register can be written and read via the I
2
C bus.
Figure 2. Control Register
One or several SCn/SDn downstream pairs, or channels, are selected by the contents of the control register (seeTable 1 ). This register is written after the PCA9544A has been addressed. The three LSBs of the control byte areused to determine which channel (or channels) is to be selected. When a channel is selected, the channelbecomes active after a stop condition has been placed on the I
2
C bus. This ensures that all SCn/SDn lines are ina high state when the channel is made active, so that no false conditions are generated at the time ofconnection. A stop condition always must occur right after the acknowledge cycle.
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Interrupt Handling
PCA9544A4-CHANNEL I
2
C AND SMBus MULTIPLEXER
WITH INTERRUPT LOGIC
SCPS146A OCTOBER 2005 REVISED OCTOBER 2005
Table 1. Control Register Write (Channel Selection), Control Register Read (Channel Status)
(1)
INT3 INT2 INT1 INT0 D3 B2 B1 B0 COMMAND
X X X X X 0 X X No channel selectedX X X X X 1 0 0 Channel 0 enabledX X X X X 1 0 1 Channel 1 enabledX X X X X 1 1 0 Channel 2 enabledX X X X X 1 1 1 Channel 3 enabledNo channel selected,00000000
power-up default state
(1) Only one channel may be selected at a time.
The PCA9544A provides four interrupt inputs (one for each channel) and one open-drain interrupt output. Whenan interrupt is generated by any device, it is detected by the PCA9544A, and the interrupt output is driven low.The channel does not need to be active for detection of the interrupt. A bit also is set in the control register (seeTable 2 ).
Bits 4–7 of the control register correspond to channels 0–3 of the PCA9544A, respectively. Therefore, if aninterrupt is generated by any device connected to channel 1, the state of the interrupt inputs is loaded into thecontrol register when a read is accomplished. Likewise, an interrupt on any device connected to channel 0causes bit 4 of the control register to be set on the read. The master then can address the PCA9544A and readthe contents of the control register to determine which channel contains the device generating the interrupt. Themaster can reconfigure the PCA9544A to select this channel and locate the device generating the interrupt andclear it. Once the device responsible for the interrupt clears, the interrupt clears.
It should be noted that more than one device can provide an interrupt on a channel, so it is up to the master toensure that all devices on a channel are interrogated for an interrupt.
The interrupt inputs can be used as general-purpose inputs if the interrupt function is not required.
If unused, interrupt input(s) must be connected to V
CC
.
Table 2. Control Register Read (Interrupt)
(1)
INT3 INT2 INT1 INT0 D3 B2 B1 B0 COMMAND
0 No interrupt on channel 0XXX XXXX1 Interrupt on channel 00 No interrupt on channel 1XX XXXXX1 Interrupt on channel 10 No interrupt on channel 2X XXXXXX1 Interrupt on channel 20 No interrupt on channel 3XXXXXXX1 Interrupt on channel 3
(1) Several interrupts can be active at the same time. For example, INT3 = 0, INT2 = 1, INT1 = 1, INT0 = 0 means that there is no interrupton channels 0 and 3, and there is interrupt on channels 1 and 2.
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Power-On Reset
Voltage Translation
2
Maximum
Typical
Minimum
VCC (V)
4.543.532.5 5 5.5
1
5
4.5
4
3.5
3
2.5
2
1.5
Vpass (V)
I
2
C Interface
PCA9544A
4-CHANNEL I
2
C AND SMBus MULTIPLEXERWITH INTERRUPT LOGIC
SCPS146A OCTOBER 2005 REVISED OCTOBER 2005
When power is applied to V
CC
, an internal power-on reset holds the PCA9544A in a reset condition until V
CC
hasreached V
POR
. At this point, the reset condition is released, and the PCA9544A registers and I
2
C state machineare initialized to their default states, all zeroes, causing all the channels to be deselected. Thereafter, V
CC
mustbe lowered below 0.2 V to reset the device.
The pass-gate transistors of the PCA9544A are constructed such that the V
CC
voltage can be used to limit themaximum voltage that is passed from one I
2
C bus to another.
Figure 3 shows the voltage characteristics of the pass-gate transistors (note that the graph was generated usingdata specified in the electrical characteristics section of this data sheet). In order for the PCA9544A to act as avoltage translator, the V
pass
voltage must be equal to or lower than the lowest bus voltage. For example, if themain bus is running at 5 V and the downstream buses are 3.3 V and 2.7 V, V
pass
must be equal to or below 2.7 Vto effectively clamp the downstream bus voltages. As shown in Figure 3 , V
pass
(max) is at 2.7 V when thePCA9544A supply voltage is 3.5 V or lower, so the PCA9544A supply voltage could be set to 3.3 V. Pullupresistors then can be used to bring the bus voltages to their appropriate levels (see Figure 12 ).
Figure 3. V
pass
Voltage vs V
CC
The I
2
C bus is for two-way two-line communication between different ICs or modules. The two lines are a serialdata line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pullupresistor when connected to the output stages of a device. Data transfer can be initiated only when the bus is notbusy.
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the highperiod of the clock pulse, as changes in the data line at this time are interpreted as control signals (see Figure 4 ).
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SDA
SCL
Start Condition
S
Stop Condition
P
SDA
SCL
Master
Transmitter/
Receiver Slave
Receiver Slave
Transmitter/
Receiver Master
Transmitter
Master
Transmitter/
Receiver
I2C
Multiplexer
Slave
PCA9544A4-CHANNEL I
2
C AND SMBus MULTIPLEXER
WITH INTERRUPT LOGIC
SCPS146A OCTOBER 2005 REVISED OCTOBER 2005
Figure 4. Bit Transfer
Both data and clock lines remain high when the bus is not busy. A high-to-low transition of the data line while theclock is high is defined as the start condition (S). A low-to-high transition of the data line while the clock is high isdefined as the stop condition (P) (see Figure 5 ).
Figure 5. Definition of Start and Stop Conditions
A device generating a message is a transmitter; a device receiving a message is the receiver. The device thatcontrols the message is the master, and the devices that are controlled by the master are the slaves (seeFigure 6 ).
Figure 6. System Configuration
The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is notlimited. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before thereceiver can send an ACK bit.
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Data Output
by Transmitter
SCL From
Master
Start
Condition
S
1 2 8 9
Data Output
by Receiver
Clock Pulse for ACK
NACK
ACK
A AS 1 1 1 0 A2 A1 A0 0
Start Condition
SDA
R/W ACK From Slave ACK From Slave
P
B0B1B2XXXXX
Stop Condition
Slave Address Control Register
ANA
S 1 1 1 0 A2 A1 A0 1SDA INT0INT3 INT2 INT1 P
0B2 B1 B0
Start Condition R/W ACK From Slave NACK From Master Stop Condition
Slave Address Control Register
PCA9544A
4-CHANNEL I
2
C AND SMBus MULTIPLEXERWITH INTERRUPT LOGIC
SCPS146A OCTOBER 2005 REVISED OCTOBER 2005
When a slave receiver is addressed, it must generate an acknowledge (ACK) after the reception of each byte.Also, a master must generate an ACK after the reception of each byte that has been clocked out of the slavetransmitter. The device that acknowledges must pull down the SDA line during the ACK clock pulse so that theSDA line is stable low during the high pulse of the ACK-related clock period (see Figure 7 ). Setup and hold timesmust be taken into account.
Figure 7. Acknowledgment on the I
2
C Bus
A master receiver must signal an end of data to the transmitter by not generating an acknowledge (NACK) afterthe last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line high.In this event, the transmitter must release the data line to enable the master to generate a stop condition.
Data is transmitted to the PCA9544A control register using the write mode shown in Figure 8 .
Figure 8. Write Control Register
Data is read from the PCA9544A control register using the read mode shown in Figure 9 .
Figure 9. Read Control Register
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Absolute Maximum Ratings
(1)
Recommended Operating Conditions
(1)
PCA9544A4-CHANNEL I
2
C AND SMBus MULTIPLEXER
WITH INTERRUPT LOGIC
SCPS146A OCTOBER 2005 REVISED OCTOBER 2005
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
V
CC
Supply voltage range –0.5 7 VV
I
Input voltage range
(2)
–0.5 7 VI
I
Input current ±20 mAI
O
Output current ±25 mAContinuous current through V
CC
±100 mAContinuous current through GND ±100 mADGV package
(3)
92DW package
(3)
58GQN package
(3)
78θ
JA
Package thermal impedance °C/WPW package
(3)
83RGW package
(4)
TBDRGY package
(4)
37P
tot
Total power dissipation 400 mWT
stg
Storage temperature range –65 150 °CT
A
Operating free-air temperature range –40 85 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.(3) The package thermal impedance is calculated in accordance with JESD 51-7.(4) The package thermal impedance is calculated in accordance with JESD 51-5.
MIN MAX UNIT
V
CC
Supply voltage 2.3 5.5 VSCL, SDA 0.7 ×V
CC
6V
IH
High-level input voltage VA2–A0, INT3– INT0 0.7 ×V
CC
V
CC
+ 0.5SCL, SDA –0.5 0.3 ×V
CCV
IL
Low-level input voltage VA2–A0, INT3– INT0 –0.5 0.3 ×V
CC
T
A
Operating free-air temperature –40 85 °C
(1) All unused inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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Electrical Characteristics
PCA9544A
4-CHANNEL I
2
C AND SMBus MULTIPLEXERWITH INTERRUPT LOGIC
SCPS146A OCTOBER 2005 REVISED OCTOBER 2005
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS V
CC
MIN TYP
(1)
MAX UNIT
V
POR
Power-on reset voltage
(2)
No load, V
I
= V
CC
or GND V
POR
1.7 2.1 V5 V 3.64.5 V to 5.5 V 2.6 4.53.3 V 1.9V
pass
Switch output voltage V
SWin
= V
CC
, I
SWout
= –100 µA V3 V to 3.6 V 1.6 2.82.5 V 1.52.3 V to 2.7 V 1.1 2I
OH
INT V
O
= V
CC
2.3 V to 5.5 V 10 µAV
OL
= 0.4 V 3 7SCL, SDAI
OL
V
OL
= 0.6 V 2.3 V to 5.5 V 6 10 mAINT V
OL
= 0.4 V 3 7SCL, SDA ±1SC3–SC0, SD3–SD0 ±1I
I
V
I
= V
CC
or GND 2.3 V to 5.5 V µAA2–A0 ±1INT3– INT0 ±15.5 V 3 12Operating mode f
SCL
= 100 kHz V
I
= V
CC
or GND, I
O
= 0 3.6 V 3 112.7 V 3 105.5 V 0.3 1I
CC
Low inputs V
I
= GND, I
O
= 0 3.6 V 0.1 1 µA2.7 V 0.1 1Standby mode
5.5 V 0.3 1High inputs V
I
= V
CC
, I
O
= 0 3.6 V 0.1 12.7 V 0.1 1One INT3– INT0 input at 0.6 V,
8 15Other inputs at V
CC
or GNDINT3– INT0
One INT3– INT0 input at V
CC
0.6 V,
8 15Other inputs at V
CC
or GNDSupply-current
I
CC
2.3 V to 5.5 V µAchange
SCL or SDA input at 0.6 V,
8 15Other inputs at V
CC
or GNDSCL, SDA
SCL or SDA inputs at V
CC
0.6 V,
8 15Other inputs at V
CC
or GNDA2–A0 4.5 6C
i
V
I
= V
CC
or GND 2.3 V to 5.5 V pFINT3– INT0 4.5 6SCL, SDA 15 19C
io(OFF)
(3)
V
I
= V
CC
or GND, Switch OFF 2.3 V to 5.5 V pFSC3–SC0, SD3–SD0 6 84.5 V to 5.5 V 4 9 16V
O
= 0.4 V, I
O
= 15 mAR
ON
Switch-on resistance 3 V to 3.6 V 5 11 20 V
O
= 0.4 V, I
O
= 10 mA 2.3 V to 2.7 V 7 16 45
(1) All typical values are at nominal supply voltage (2.5-V, 3.3-V, or 5-V V
CC
), T
A
= 25 °C.(2) The power-on reset circuit resets the I
2
C bus logic with V
CC
< V
POR
. V
CC
must be lowered to 0.2 V to reset the device.(3) C
io(ON)
depends on internal capacitance and external capacitance added to the SCn lines when channels(s) are ON.
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I
2
C Interface Timing Requirements
Switching Characteristics
Interrupt Timing Requirements
PCA9544A4-CHANNEL I
2
C AND SMBus MULTIPLEXER
WITH INTERRUPT LOGIC
SCPS146A OCTOBER 2005 REVISED OCTOBER 2005
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 12 )
STANDARD-MODE FAST-MODEI
2
C BUS I
2
C BUS
UNITMIN MAX MIN MAX
f
scl
I
2
C clock frequency 0 100 0 400 kHzt
sch
I
2
C clock high time 4 0.6 µst
scl
I
2
C clock low time 4.7 1.3 µst
sp
I
2
C spike time 50 50 nst
sds
I
2
C serial-data setup time 250 100 nst
sdh
I
2
C serial-data hold time 0
(1)
0
(1)
µst
icr
I
2
C input rise time 1000 20 + 0.1C
b
(2)
300 nst
icf
I
2
C input fall time 300 20 + 0.1C
b
(2)
300 nst
ocf
I
2
C output fall time (10-pF to 400-pF bus) 300 20 + 0.1C
b
(2)
300 nst
buf
I
2
C bus free time between stop and start 4.7 1.3 µst
sts
I
2
C start or repeated start condition setup 4.7 0.6 µst
sth
I
2
C start or repeated start condition hold 4 0.6 µst
sps
I
2
C stop condition setup 4 0.6 µst
vdL(Data)
Valid-data time (high to low)
(3)
SCL low to SDA output low valid 1 1 µst
vdH(Data)
Valid-data time (low to high)
(3)
SCL low to SDA output high valid 0.6 0.6 µsACK signal from SCL lowt
vd(ack)
Valid-data time of ACK condition 1 1 µsto SDA output lowC
b
I
2
C bus capacitive load 400 400 pF
(1) A device internally must provide a hold time of at least 300 ns for the SDA signal (referred to as the V
IH
min of the SCL signal), in orderto bridge the undefined region of the falling edge of SCL.(2) C
b
= total bus capacitance of one bus line in pF(3) Data taken using a 1-k pullup resistor and 50-pF load (see Figure 10 ).
over recommended operating free-air temperature range, C
L
100 pF (unless otherwise noted) (see Figure 10 )
FROM TOPARAMETER MIN MAX UNIT(INPUT) (OUTPUT)
R
ON
= 20 , C
L
= 15 pF 0.3t
pd
(1)
Propagation delay time SDA or SCL SDn or SCn µsR
ON
= 20 , C
L
= 50 pF 1t
iv
Interrupt valid time
(2)
INTn INT 4 µst
ir
Interrupt reset delay time
(2)
INTn INT 2 µs
(1) The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified loadcapacitance, when driven by an ideal voltage source (zero output impedance).(2) Data taken using a 4.7-k pullup resistor and 100-pF load (see Figure 11 ).
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER MIN MAX UNIT
t
PWRL
Low-level pulse duration rejection of INTn inputs
(1)
1µst
PWRH
High-level pulse duration rejection of INTn inputs
(1)
0.5 µs
(1) Data taken using a 4.7-k pullup resistor and 100-pF load (see Figure 11 ).
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PARAMETER MEASUREMENT INFORMATION
RL = 1 k
VCC
CL = 50 pF
(See Note A)
tbuf
ticr
tsth tsds
tsdh
ticf
ticr
tscl tsch
tsts
tvd(ACK)
or tvdL
tvdH
0.3 × VCC
Stop
Condition
tsps
Repeat
Start
Condition
Start or Repeat
Start Condition
SCL
SDA
Start
Condition
(S)
Address
Bit 7
(MSB)
Data
Bit 0
(LSB)
Stop
Condition
(P)
Two Bytes for Complete
Device Programming
I2C-PORT LOAD CONFIGURATION
VOLTAGE WAVEFORMS
ticf
Stop
Condition
(P)
tsp
DUT SDn, SCn
0.7 × VCC
0.3 × VCC
0.7 × VCC
R/W
Bit 0
(LSB)
ACK
(A)
Data
Bit 7
(MSB)
Address
Bit 1
Address
Bit 6 ACK
(A)
BYTE DESCRIPTION
I2C address + R/W
Control register data
1
2
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr/tf 30 ns.
C. The outputs are measured one at a time, with one transition per measurement.
PCA9544A
4-CHANNEL I
2
C AND SMBus MULTIPLEXERWITH INTERRUPT LOGIC
SCPS146A OCTOBER 2005 REVISED OCTOBER 2005
Figure 10. I
2
C Interface Load Circuit, Byte Descriptions, and Voltage Waveforms
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RL = 4.7 k
VCC
CL = 100 pF
(See Note A)
INTERRUPT LOAD CONFIGURATION
DUT INT
0.5 × VCC
INTn
(input)
VOLTAGE WAVEFORMS (tiv)
tiv
VOLTAGE WAVEFORMS (tir)
INT
(output) 0.5 × VCC
INTn
(input)
INT
(output)
0.5 × VCC
0.5 × VCC
tir
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr/tf 30 ns.
PCA9544A4-CHANNEL I
2
C AND SMBus MULTIPLEXER
WITH INTERRUPT LOGIC
SCPS146A OCTOBER 2005 REVISED OCTOBER 2005
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 11. Interrupt Load Circuit and Voltage Waveforms
13
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APPLICATION INFORMATION
PCA9544A
SD1
SDA Channel 0
Channel 1
Channel 2
Channel 3
See Note A
I2C/SMBus
Master SCL INT
INT1
SC1
SD2
SC2
SD3
SC3
INT2
INT3
SD0
INT0
SC0
VCC = 2.7 V to 5.5 V VCC = 3.3 V VCC = 2.7 V to 5.5 V
VCC = 2.7 V to 5.5 V
VCC = 2.7 V to 5.5 V
VCC = 2.7 V to 5.5 V
See Note A
See Note A
See Note A
NOTES: A. If the device generating the interrupt has an open-drain output structure or can be 3-stated, a pullup resistor is required.
If the device generating the interrupt has a totem-pole output structure and cannot be 3-stated, a pullup resistor is not required.
The interrupt inputs should not be left floating.
B. Pin numbers shown are for DGV, DW, PW, and RGY packages.
SDA
SCL
GND
A0
A1
A2
5
6
4
8
9
7
12
13
11
15
16
14
19
18
17
2
3
1
10
20
PCA9544A
4-CHANNEL I
2
C AND SMBus MULTIPLEXERWITH INTERRUPT LOGIC
SCPS146A OCTOBER 2005 REVISED OCTOBER 2005
Figure 12. Typical Application
14
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
PCA9544ADGVR PREVIEW TVSOP DGV 20 2000 TBD Call TI Call TI
PCA9544ADGVT PREVIEW TVSOP DGV 20 250 TBD Call TI Call TI
PCA9544ADW PREVIEW SOIC DW 20 25 TBD Call TI Call TI
PCA9544ADWR PREVIEW SOIC DW 20 2000 TBD Call TI Call TI
PCA9544ADWT PREVIEW SOIC DW 20 250 TBD Call TI Call TI
PCA9544AGQNR PREVIEW VFBGA GQN 20 1000 TBD Call TI Call TI
PCA9544APW PREVIEW TSSOP PW 20 70 TBD Call TI Call TI
PCA9544APWR PREVIEW TSSOP PW 20 2000 TBD Call TI Call TI
PCA9544APWT PREVIEW TSSOP PW 20 250 TBD Call TI Call TI
PCA9544ARGWR PREVIEW QFN RGW 20 3000 TBD Call TI Call TI
PCA9544ARGYR PREVIEW QFN RGY 20 1000 TBD Call TI Call TI
PCA9544AZQNR PREVIEW VFBGA ZQN 20 1000 TBD Call TI Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
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incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 7-Oct-2005
Addendum-Page 1
MECHANICAL DATA
MPDS006C – FEBRUAR Y 1996 – REVISED AUGUST 2000
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE
24 PINS SHOWN
14
3,70
3,50 4,90
5,10
20
DIM
PINS **
4073251/E 08/00
1,20 MAX
Seating Plane
0,05
0,15
0,25
0,50
0,75
0,23
0,13
112
24 13
4,30
4,50
0,16 NOM
Gage Plane
A
7,90
7,70
382416
4,90
5,103,70
3,50
A MAX
A MIN
6,60
6,20
11,20
11,40
56
9,60
9,80
48
0,08
M
0,07
0,40
0°8°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,65 M
0,10
0,10
0,25
0,50
0,75
0,15 NOM
Gage Plane
28
9,80
9,60
24
7,90
7,70
2016
6,60
6,40
4040064/F 01/97
0,30
6,60
6,20
80,19
4,30
4,50
7
0,15
14
A
1
1,20 MAX
14
5,10
4,90
8
3,10
2,90
A MAX
A MIN
DIM PINS **
0,05
4,90
5,10
Seating Plane
0°–8°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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