High Common-Mode Voltage,
Difference Amplifier
AD629
Rev. C
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FEATURES
Improved replacement for: INA117P and INA117KU
±270 V common-mode voltage range
Input protection to
±500 V common mode
±500 V differential mode
Wide power supply range (±2.5 V to ±18 V)
±10 V output swing on ±12 V supply
1 mA maximum power supply current
HIGH ACCURACY DC PERFORMANCE
3 ppm maximum gain nonlinearity (AD629B)
20 μV/°C maximum offset drift (AD629A)
10 μV/°C maximum offset drift (AD629B)
10 ppm/°C maximum gain drift
EXCELLENT AC SPECIFICATIONS
77 dB minimum CMRR @ 500 Hz (AD629A)
86 dB minimum CMRR @ 500 Hz (AD629B)
500 kHz bandwidth
APPLICATIONS
High voltage current sensing
Battery cell voltage monitors
Power supply current monitors
Motor controls
Isolation
FUNCTIONAL BLOCK DIAGRAM
1
2
3
4
8
7
6
5
21.1kΩ
380kΩ
380kΩ
380kΩ
20kΩ
REF(–)
–IN
+IN
–V
S
NC
+V
S
OUTPUT
REF(+)
AD629
NC = NO CONNECT
0
0783-001
Figure 1.
GENERAL DESCRIPTION
The AD629 is a difference amplifier with a very high input,
common-mode voltage range. It is a precision device that allows
the user to accurately measure differential signals in the
presence of high common-mode voltages up to ±270 V.
The AD629 can replace costly isolation amplifiers in
applications that do not require galvanic isolation. The device
operates over a ±270 V common-mode voltage range and has
inputs that are protected from common-mode or differential
mode transients up to ±500 V.
The AD629 has low offset, low offset drift, low gain error drift,
low common-mode rejection drift, and excellent CMRR over a
wide frequency range.
The AD629 is available in die and packaged form featuring
8-lead PDIP and 8-lead SOIC packages. For all packages
(including die) and grades, performance is guaranteed over
the industrial temperature range of −40°C to +85°C.
FREQUENCY (Hz)
COMMON-MODE REJECTION
R
A
TIO (dB)
100
50
55
60
65
70
75
80
85
90
95
20 100 1k 10k 20k
00783-002
Figure 2. Common-Mode Rejection Ratio vs. Frequency
COMMON-MODE VOLTAGE (V)
OUTPUT ERROR (2mV/DIV)
–240 240120–120 0
00783-003
2mV/DIV
60V/DIV
Figure 3. Error Voltage vs. Input Common-Mode Voltage
AD629
Rev. C | Page 2 of 16
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
ESD Caution.................................................................................. 4
Pin Configuration and Function Descriptions............................. 5
Typical Performance Characteristics ............................................. 6
Theory of Operation ...................................................................... 10
Applications..................................................................................... 11
Basic Connections...................................................................... 11
Single-Supply Operation ........................................................... 11
System-Level Decoupling and Grounding.............................. 11
Using a Large Sense Resistor..................................................... 12
Output Filtering.......................................................................... 12
Output Current and Buffering.................................................. 13
A Gain of 19 Differential Amplifier......................................... 13
Error Budget Analysis Example 1 ............................................ 13
Error Budget Analysis Example 2 ............................................ 14
Outline Dimensions ....................................................................... 15
Ordering Guide .......................................................................... 16
REVISION HISTORY
4/11—Rev. B to Rev. C
Changes to General Description Section ...................................... 1
Added Endnote 1 in Table 1............................................................ 3
Added Figure 5; Renumbered Sequentially .................................. 4
Added Table 3; Renumbered Sequentially .................................... 4
Added Pin Configuration and Function Descriptions Section,
Figure 6, and Table 4 ........................................................................ 5
Changes to Ordering Guide .......................................................... 16
3/07—Rev. A to Rev. B
Updated Format and Layout .............................................Universal
Changes to Ordering Guide.......................................................... 15
3/00—Rev. 0 to Rev. A
10/99—Revision 0: Initial Version
AD629
Rev. C | Page 3 of 16
SPECIFICATIONS
TA = 25°C, VS = ±15 V, unless otherwise noted.
Table 1.
AD629A1 AD629B
Parameter Condition Min Typ Max Min Typ Max Unit
GAIN VOUT = ±10 V, RL = 2 kΩ
Nominal Gain 1 1 V/V
Gain Error 0.01 0.05 0.01 0.03 %
Gain Nonlinearity 4 10 4 10 ppm
R
L = 10 kΩ 1 1 3 ppm
Gain vs. Temperature TA = TMIN to TMAX 3 10 3 10 ppm/°C
OFFSET VOLTAGE
Offset Voltage 0.2 1 0.1 0.5 mV
V
S = ±5 V 1 mV
vs. Temperature TA = TMIN to TMAX 6 20 3 10 μV/°C
vs. Supply (PSRR) VS = ±5 V to ± 15 V 84 100 90 110 dB
INPUT
Common-Mode Rejection Ratio VCM = ±250 V dc 77 88 86 96 dB
T
A = TMIN to TMAX 73 82 dB
V
CM = 500 V p-p, dc to 500 Hz 77 86 dB
V
CM = 500 V p-p, dc to 1 kHz 88 90 dB
Operating Voltage Range Common mode ±270 ±270 V
Differential ±13 ±13 V
Input Operating Impedance Common mode 200 200 kΩ
Differential 800 800 kΩ
OUTPUT
Operating Voltage Range RL = 10 kΩ ±13 ±13 V
R
L = 2 kΩ ±12.5 ±12.5 V
V
S = ±12 V, RL = 2 kΩ ±10 ±10 V
Output Short-Circuit Current ±25 ±25 mA
Capacitive Load Stable operation 1000 1000 pF
DYNAMIC RESPONSE
Small Signal –3 dB Bandwidth 500 500 kHz
Slew Rate 1.7 2.1 1.7 2.1 V/μs
Full Power Bandwidth VOUT = 20 V p-p 28 28 kHz
Settling Time 0.01%, VOUT = 10 V step 15 15 μs
0.1%, VOUT = 10 V step 12 12 μs
0.01%, VCM = 10 V step, VDIFF = 0 V 5 5 μs
OUTPUT NOISE VOLTAGE
0.01 Hz to 10 Hz 15 15 μV p-p
Spectral Density, ≥100 Hz2 550 550 nV/√Hz
POWER SUPPLY
Operating Voltage Range ±2.5 ±18 ±2.5 ±18 V
Quiescent Current VOUT = 0 V 0.9 1 0.9 1 mA
T
MIN to TMAX 1.2 1.2 mA
TEMPERATURE RANGE
For Specified Performance TA = TMIN to TMAX −40 +85 −40 +85 °C
1 Specifications for the AD629 A grade are also valid for the die model (listed in the as AD629AC-WP). Ordering Guide
2 See . Figure 21
AD629
Rev. C | Page 4 of 16
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Supply Voltage, VS ±18 V
Internal Power Dissipation1
8-Lead PDIP (N) See Figure 4
8-Lead SOIC (R) See Figure 4
Input Voltage Range, Continuous ±300 V
Common-Mode and Differential, 10 sec ±500 V
Output Short-Circuit Duration Indefinite
Pin 1 and Pin 5 –VS − 0.3 V to +VS + 0.3 V
Maximum Junction Temperature 150°C
Operating Temperature Range −55°C to +125°C
Storage Temperature Range −65°C to +150°C
Lead Temperature (Soldering 60 sec) 300°C
1 Specification is for device in free air:
8-Lead PDIP, θJA = 100°C/W;
8-Lead SOIC, θJA = 155°C/W.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
AMBIENT TEMPERATURE (°C)
MAXIMUM POWER DISSIP
A
TION (W)
2.0
1.5
1.0
0.5
0
–50 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90
00783-004
8-LEAD SOIC
T
J
= 150°C
8-LEAD PDIP
Figure 4. Maximum Power Dissipation vs. Temperature for SOIC and PDIP
DIE SIZE: 1655µm (X) by 2465µm (Y)
X
Y
7
2
1a 1b
3
4
5a 5b
6b
6a
00783-041
Figure 5. Metallization Photograph
Table 3. Pin Pad Coordinates
Coordinates1
Pad Pin X Y Description
1a REF(−) −677 +1082
1b −534 +1084
For the die model, either
pad can be bonded because
1a and 1b are internally
shorted.
2 −IN −661 +939
3 +IN −661 −658
4 −VS +680 −800
5a REF(+) +396 −1084
5b +538 −1084
For the die model, either
pad can be bonded because
5a and 5b are internally
shorted.
6a OUTPUT +681 −950
6b +681 −807
For the die model, both
pads must be bonded
because 6a and 6b are not
internally shorted.
7 +VS +680 +612
1 All coordinates are with respect to the center of the die.
ESD CAUTION
AD629
Rev. C | Page 5 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
REF(–) 1
–IN 2
+IN 3
–VS4
NC
8
+VS
7
OUTPUT6
REF(+)5
NC = NO CONNECT
AD629
TOP VIEW
(Not to Scale)
00783-040
Figure 6. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 REF(−) Negative Reference Voltage Input.
2 −IN Inverting Input.
3 +IN Noninverting Input.
4 −VS Negative Supply Voltage.
5 REF(+) Positive Reference Voltage Input.
6 OUTPUT Output.
7 +VS Positive Supply Voltage.
8 NC No Connect. Do not connect to this pin.
AD629
Rev. C | Page 6 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VS = ±15 V, unless otherwise noted.
FREQUENCY (Hz)
COMMON-MODE REJECTION R
A
TIO (dB)
100
90
80
70
60
50
40
30
20
10
0
100 1k 10k 100k 1M 10M
00783-006
Figure 7. Common-Mode Rejection Ratio vs. Frequency
V
OUT
(V)
OUTPUT ERROR (2mV/DIV)
–20 –16 –8 –4 0 4 8 12 16–12 20
00783-007
R
L
= 10kΩ
V
S
= ±18V
V
S
= ±15V
V
S
= ±12V
V
S
= ±10V
2mV/DIV
4V/DIV
Figure 8. Typical Gain Error Normalized @ VOUT = 0 V and Output Voltage
Operating Range vs. Supply Voltage, RL = 10 kΩ (Curves Offset for Clarity)
V
OUT
(V)
OUTPUT ERROR (2mV/DIV)
–20 –16 –8 –4 0 4 8 12 16–12 20
00783-008
R
L
= 1kΩ
V
S
= ±18V
V
S
= ±15V
V
S
= ±12V
V
S
= ±10V 4V/DIV
Figure 9. Typical Gain Error Normalized @ VOUT = 0 V and Output Voltage
Operating Range vs. Supply Voltage, RL = 1 kΩ (Curves Offset for Clarity)
POWER SUPPLY VOLTAGE (±V)
COMMON-MODE VOLTAGE (±V)
400
360
320
280
240
200
160
120
80
40
0
02 6 104 8 12 14 1816 20
00783-009
T
A
= +25°C
T
A
= +85°C
T
A
= –40°C
Figure 10. Common-Mode Operating Range vs. Power Supply Voltage
V
OUT
(V)
OUTPUT ERROR (2mV/DIV)
–20 –16 –8 –4 0 4 8 12 16–12 20
00783-010
R
L
= 2kΩ
V
S
= ±18V
V
S
= ±15V
V
S
= ±12V
V
S
= ±10V 4V/DIV
Figure 11. Typical Gain Error Normalized @ VOUT = 0 V and Output Voltage
Operating Range vs. Supply Voltage, RL = 2 kΩ (Curves Offset for Clarity)
V
OUT
(V)
OUTPUT ERROR (2mV/DIV)
–20 –16 –8 –4 0 4 8 12 16–12 20
00783-011
V
S
= ±5V, R
L
= 2kΩ
V
S
= ±5V, R
L
= 1kΩ
V
S
= ±2.5V, R
L
= 1kΩ1V/DIV
V
S
= ±5V, R
L
= 10kΩ
Figure 12. Typical Gain Error Normalized @ VOUT = 0 V and Output Voltage
Operating Range vs. Supply Voltage (Curves Offset for Clarity)
AD629
Rev. C | Page 7 of 16
V
OUT
(V)
ERROR (0.8ppm/DIV)
–10 –5 0 5 10
00783-012
20µV/DIV
2.5V/DIV
V
S
= ±15V
R
L
= 10kΩ
Figure 13. Gain Nonlinearity; VS = ±15 V, RL = 10 kΩ
V
OUT
(V)
ERROR (1ppm/DIV)
–10 –2–4–6–8 0246810
00783-013
20µV/DIV
2V/DIV
V
S
= ±12V
R
L
= 10kΩ
Figure 14. Gain Nonlinearity; VS = ±12 V, RL =10 kΩ
V
OUT
(V)
ERROR (6.67ppm/DIV)
–3.0 –0.6–1.2–1.8–2.4 0 0.6 1.2 1.8 2.4 3.0
00783-014
40µV/DIV
0.6V/DIV
V
S
= ±5V
R
L
= 1kΩ
Figure 15. Gain Nonlinearity; VS = ±5 V, RL = 1 kΩ
V
OUT
(V)
ERROR (2ppm/DIV)
–10 –2–4–6–8 0246810
00783-015
40µV/DIV
2V/DIV
V
S
= ±15V
R
L
= 2kΩ
Figure 16. Gain Nonlinearity; VS = ±15 V, RL = 2kΩ
OUTPUT CURRENT (mA)
OUTPUT VOLTAGE (V)
14.0
13.0
12.0
11.0
10.0
9.0
–11.5
–12.0
–12.5
–13.0
–13.5
0 2 4 6 8 10 12 14 16 18 20
00783-016
–40°C
–40°C
–40°C
+85°C
+85°C
+25°C
+25°C
V
S
= ±15V
Figure 17. Output Voltage Operating Range vs. Output Current; VS = ±15 V
OUTPUT CURRENT (mA)
OUTPUT VOLTAGE (V)
11.5
10.5
9.5
8.5
7.5
6.5
–9.0
–9.5
–10.0
–10.5
–11.0
0 2 4 6 8 10 12 14 16 18 20
00783-017
V
S
= ±12V
–40°C
–40°C
+85°C
+25°C
–40°C
+85°C
+85°C
+25°C
Figure 18. Output Voltage Operating Range vs. Output Current; VS = ±12 V
AD629
Rev. C | Page 8 of 16
OUTPUT CURRENT (mA)
OUTPUT VOLTAGE (V)
4.5
3.5
2.5
1.5
0.5
–2.0
–2.5
–3.0
–3.5
–4.0
0 2 4 6 8 10 12 14 16 18 20
00783-018
V
S
= ±5V
–40°C
+85°C
+85°C
–40°C
+25°C
+25°C
–40°C
+25°C
+85°C
+85°C
Figure 19. Output Voltage Operating Range vs. Output Current; VS = ±5 V
FREQUENCY (Hz)
POWER SUPPLY REJECTION
R
A
TIO (dB)
120
110
100
90
80
70
60
50
40
30
0.1 101.0 100 1k 10k
00783-019
–V
S
+V
S
Figure 20. Power Supply Rejection Ratio vs. Frequency
FREQUENCY (Hz)
VOL
T
AGE NOISE SPECTRAL DENSI
T
Y (µV/ Hz)
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.01 1.00.1 10010 1k 100k10k
00783-020
Figure 21. Voltage Noise Spectral Density vs. Frequency
00783-021
25mV/DIV 4µs/DIV
G = +1
R
L
= 2kΩ
C
L
= 1000pF
Figure 22. Small Signal Pulse Response
00783-022
25mV/DIV 4µs/DIV
G = +1
R
L
= 2kΩ
C
L
= 1000pF
Figure 23. Small Signal Pulse Response
00783-023
5V/DIV 5µs/DIV
G = +1
RL = 2kΩ
CL = 1000pF
Figure 24. Large Signal Pulse Response
AD629
Rev. C | Page 9 of 16
00783-024
VOUT
5V/DIV
1mV/DIV
OUTPUT
ERROR
0V
+10V
10µs/DIV
1mV = 0.01%
Figure 25. Settling Time to 0.01%, for 0 V to 10 V Output Step; G = −1, RL = 2 kΩ
COMMON-MODE REJECTION RATIO (ppm)
NUMBER OF UNITS
350
300
250
200
150
100
50
0
–150 –50–100 500 150100
00783-025
N = 2180
n ≈ 200 PCS. FROM
10 ASSEMBLY LOTS
Figure 26. Typical Distribution of Common-Mode Rejection; Package Option N-8
–1 GAIN ERROR (ppm)
NUMBER OF UNITS
400
300
250
350
200
150
100
50
0
–600 –200–400 2000 600400
00783-026
N = 2180
n ≈ 200 PCS. FROM
10 ASSEMBLY LOTS
Figure 27. Typical Distribution of −1 Gain Error; Package Option N-8
00783-027
V
OUT
5V/DIV
1mV/DIV
OUTPUT
ERROR
0V
–10V
10µs/DIV
1mV = 0.01%
Figure 28. Settling Time to 0.01% for 0 V to −10 V Output Step; G = −1, RL = 2kΩ
OFFSET VOLTAGE (µV)
NUMBER OF UNITS
300
250
200
150
100
50
0
–900 –300–600 3000 900600
00783-028
N = 2180
n ≈ 200 PCS. FROM
10 ASSEMBLY LOTS
Figure 29. Typical Distribution of Offset Voltage; Package Option N-8
+1 GAIN ERROR (ppm)
NUMBER OF UNITS
400
300
250
350
200
150
100
50
0
–600 –200–400 2000 600400
00783-029
N = 2180
n ≈ 200 PCS. FROM
10 ASSEMBLY LOTS
Figure 30. Typical Distribution of +1 Gain Error; Package Option N-8
AD629
Rev. C | Page 10 of 16
THEORY OF OPERATION
The AD629 is a unity gain, differential-to-single-ended
amplifier (diff amp) that can reject extremely high common-
mode signals (in excess of 270 V with 15 V supplies). It consists
of an operational amplifier (op amp) and a resistor network.
To achieve high common-mode voltage range, an internal
resistor divider (Pin 3 or Pin 5) attenuates the noninverting
signal by a factor of 20. Other internal resistors (Pin 1, Pin 2,
and the feedback resistor) restore the gain to provide a differential
gain of unity. The complete transfer function equals
VOUT = V (+IN) − V (−IN)
Laser wafer trimming provides resistor matching so that
common-mode signals are rejected while differential input
signals are amplified.
To reduce output drift, the op amp uses super beta transistors
in its input stage. The input offset current and its associated
temperature coefficient contribute no appreciable output
voltage offset or drift, which has the added benefit of reducing
voltage noise because the corner where 1/f noise becomes
dominant is below 5 Hz. To reduce the dependence of gain
accuracy on the op amp, the open-loop voltage gain of the op
amp exceeds 20 million, and the PSRR exceeds 140 dB.
1
2
3
4
8
7
6
5
21.1kΩ
380kΩ
380kΩ
380kΩ
20kΩ
REF(–)
–IN
+IN
–V
S
NC
+V
S
OUTPUT
REF(+)
AD629
NC = NO CONNECT
0
0783-001
Figure 31. Functional Block Diagram
AD629
Rev. C | Page 11 of 16
APPLICATIONS
BASIC CONNECTIONS
Figure 32 shows the basic connections for operating the AD629
with a dual supply. A supply voltage of between ±3 V and ±18 V
is applied between Pin 7 and Pin 4. Both supplies should be
decoupled close to the pins using 0.1 µF capacitors. Electrolytic
capacitors of 10 µF, also located close to the supply pins, may be
required if low frequency noise is present on the power supply.
While multiple amplifiers can be decoupled by a single set of
10 µF capacitors, each in amp should have its own set of 0.1 µF
capacitors so that the decoupling point can be located right at
the IC’s power pins.
REF (–)
REF (+)
–V
S
–V
S
+
V
S
+V
S
V
OUT
= I
SHUNT
× R
SHUNT
NC
–IN
+IN
R
SHUNT
I
SHUNT
(SEE
TEXT)
(SEE
TEXT)
0.1µF
0.1µF
+3V TO +18V
–3V TO –18V
NC = NO CONNECT
21.1kΩ
380kΩ380kΩ
20kΩ
380kΩ
AD629
1
2
3
4
8
7
6
5
00783-030
Figure 32. Basic Connections
The differential input signal, which typically results from a load
current flowing through a small shunt resistor, is applied to
Pin 2 and Pin 3 with the polarity shown to obtain a positive
gain. The common-mode range on the differential input signal
can range from −270 V to +270 V, and the maximum differential
range is ±13 V. When configured as shown in Figure 32, the
device operates as a simple gain-of-1, differential-to-single-
ended amplifier; the output voltage being the shunt resistance
times the shunt current. The output is measured with respect to
Pin 1 and Pin 5.
Pin 1 and Pin 5 (REF(–) and REF(+)) should be grounded for a
gain of unity and should be connected to the same low impedance
ground plane. Failure to do this results in degraded common-
mode rejection. Pin 8 is a no connect pin and should be left open.
SINGLE-SUPPLY OPERATION
Figure 33 shows the connections for operating the AD629 with
a single supply. Because the output can swing to within only
about 2 V of either rail, it is necessary to apply an offset to the
output. This can be conveniently done by connecting REF(+)
and REF(–) to a low impedance reference voltage (some ADCs
provide this voltage as an output), which is capable of sinking
current. Therefore, for a single supply of 10 V, VREF may be set
to 5 V for a bipolar input signal. This allows the output to swing
±3 V around the central 5 V reference voltage. Alternatively, for
unipolar input signals, VREF can be set to about 2 V, allowing the
output to swing from 2 V (for a 0 V input) to within 2 V of the
positive rail.
REF (–)
REF (+)
–V
S
V
Y
V
X
+V
S
+V
S
NC
–IN
+IN
R
SHUNT
I
SHUNT
0.1µF
NC = NO CONNECT
21.1kΩ
380kΩ380kΩ
20kΩ
380kΩ
AD629
1
2
3
4
8
7
6
5
00783-031
OUTPUT = V
OUT
– V
REF
V
REF
Figure 33. Operation with a Single Supply
Applying a reference voltage to REF(+) and REF(–) and
operating on a single supply reduces the input common-mode
range of the AD629. The new input common-mode range
depends upon the voltage at the inverting and noninverting
inputs of the internal operational amplifier, labeled VX and VY
in Figure 33. These nodes can swing to within 1 V of either rail.
Therefore, for a (single) supply voltage of 10 V, VX and VY can
range between 1 V and 9 V. If VREF is set to 5 V, the permissible
common-mode range is +85 V to –75 V. The common-mode
voltage ranges can be calculated by
VCM (±) = 20 VX/VY(±) − 19 VREF
SYSTEM-LEVEL DECOUPLING AND GROUNDING
The use of ground planes is recommended to minimize the
impedance of ground returns (and therefore the size of dc
errors). Figure 34 shows how to work with grounding in a
mixed-signal environment, that is, with digital and analog
signals present. To isolate low level analog signals from a noisy
digital environment, many data acquisition components have
separate analog and digital ground returns. All ground pins
from mixed-signal components, such as ADCs, should return
through a low impedance analog ground plane. Digital ground
lines of mixed-signal converters should also be connected to the
analog ground plane. Typically, analog and digital grounds
should be separated; however, it is also a requirement to
minimize the voltage difference between digital and analog
grounds on a converter, to keep them as small as possible
(typically <0.3 V). The increased noise, caused by the
converter’s digital return currents flowing through the analog
ground plane, is typically negligible. Maximum isolation
between analog and digital is achieved by connecting the ground
planes back at the supplies. Note that Figure 34 suggests a “star”
ground system for the analog circuitry, with all ground lines
being connected, in this case, to the ADC’s analog ground.
However, when ground planes are used, it is sufficient to
connect ground pins to the nearest point on the low impedance
ground plane.
AD629
Rev. C | Page 12 of 16
ANALOG POWER
SUPPLY
DIGITAL
POWER SUPPLY
0.1µF
0.1µF
0.1µF0.1µF
+IN
–IN
–VS
VIN1
VIN2
VDD VDD
OUTPUT
AGND GND
MICROPROCESSOR
DGND
+VS
AD629 AD7892-2
REF(–) REF(+)
6
7
14
4
1
3
3
2
6 4
1 5
12
+5V GND +5VGND
–5V
00783-032
Figure 34. Optimal Grounding Practice for a Bipolar Supply Environment
with Separate Analog and Digital Supplies
POWER SUPPLY
V
IN1
V
IN2
V
DD
AGND DGND
ADC
0.1µF
0.1µF
+IN
–IN
+V
S
OUTPUT
–V
S
AD629
REF(–) REF(+)
47
3
2
6
1 5
V
DD
GND
MICROPROCESSOR
+5V GND
0.1µF
00783-033
Figure 35. Optimal Ground Practice in a Single-Supply Environment
If there is only a single power supply available, it must be shared
by both digital and analog circuitry. Figure 35 shows how to
minimize interference between the digital and analog circuitry.
In this example, the ADC’s reference is used to drive Pin REF(+)
and Pin REF(–). This means that the reference must be capable
of sourcing and sinking a current equal to VCM/200 k. As in
the previous case, separate analog and digital ground planes
should be used (reasonably thick traces can be used as an
alternative to a digital ground plane). These ground planes
should connect at the power supply’s ground pin. Separate
traces (or power planes) should run from the power supply to
the supply pins of the digital and analog circuits. Ideally, each
device should have its own power supply trace, but these can be
shared by a number of devices, as long as a single trace is not
used to route current to both digital and analog circuitry.
USING A LARGE SENSE RESISTOR
Insertion of a large value shunt resistance across the input pins,
Pin 2 and Pin 3, will imbalance the input resistor network,
introducing a common-mode error. The magnitude of the error
will depend on the common-mode voltage and the magnitude
of RSHUNT.
Tabl e 5 shows some sample error voltages generated by a
common-mode voltage of 200 V dc with shunt resistors from
20 to 2000 . Assuming that the shunt resistor is selected to
use the full ±10 V output swing of the AD629, the error voltage
becomes quite significant as RSHUNT increases.
Table 5. Error Resulting from Large Values of RSHUNT
(Uncompensated Circuit)
RS (Ω) Error VOUT (V) Error Indicated (mA)
20 0.01 0.5
1000 0.498 0.498
2000 1 0.5
To measure low current or current near zero in a high common-
mode environment, an external resistor equal to the shunt
resistor value can be added to the low impedance side of the
shunt resistor, as shown in Figure 36.
REF (–)
REF (+)
–V
S
–V
S
+V
S
+V
S
V
OUT
NC
–IN
+IN
R
SHUNT
R
COMP
I
SHUNT
0.1µF
0.1µF
NC = NO CONNECT
21.1kΩ
380kΩ380kΩ
20kΩ
380kΩ
AD629
1
2
3
4
8
7
6
5
00783-034
Figure 36. Compensating for Large Sense Resistors
OUTPUT FILTERING
A simple 2-pole, low-pass Butterworth filter can be implemented
using the OP177 after the AD629 to limit noise at the output, as
shown in Figure 37. Table 6 gives recommended component
values for various corner frequencies, along with the peak-to-
peak output noise for each case.
REF (–)
REF (+)
–
V
S
–V
S
+V
S
+V
S
+V
S
V
OUT
NC
–IN
+IN
0.1µF
0.1µF 0.1µF
0.1µF
NC = NO CONNECT
21.1kΩ
380kΩ380kΩ
20kΩ
380kΩ
AD629
1
2
3
4
8
7
6
5
00783-035
R1 R2
C1
C2
OP177
Figure 37. Filtering of Output Noise Using a 2-Pole Butterworth Filter
Table 6. Recommended Values for 2-Pole Butterworth Filter
Corner Frequency R1 R2 C1 C2 Output Noise (p-p)
No Filter
3.2 mV
50 kHz 2.94 kΩ ± 1% 1.58 kΩ ± 1% 2.2 nF ± 10% 1 nF ± 10% 1 mV
5 kHz 2.94 kΩ ± 1% 1.58 kΩ ± 1% 22 nF ± 10% 10 nF ± 10% 0.32 mV
500 Hz 2.94 kΩ ± 1% 1.58 kΩ ± 1% 220 nF ± 10% 0.1 μF ± 10% 100 μV
50 Hz 2.7 kΩ ± 10% 1.5 kΩ ± 10% 2.2 μF ± 20% 1 μF ± 20% 32 μV
AD629
Rev. C | Page 13 of 16
OUTPUT CURRENT AND BUFFERING
The AD629 is designed to drive loads of 2 kΩ to within 2 V of
the rails but can deliver higher output currents at lower output
voltages (see Figure 17). If higher output current is required, the
output of the AD629 should be buffered with a precision op amp,
such as the OP113, as shown in Figure 38. This op amp can swing
to within 1 V of either rail while driving a load as small as 600 Ω.
REF (–)
REF (+)
–
V
S
–V
S
+V
S
V
OU
T
NC
–IN
+IN
0.1µF
0.1µF
0.1µF
0.1µF
NC = NO CONNECT
21.1kΩ
380kΩ380kΩ
20kΩ
380kΩ
AD629
1
2
3
4
8
7
6
5
00783-036
OP113
Figure 38. Output Buffering Application
A GAIN OF 19 DIFFERENTIAL AMPLIFIER
While low level signals can be connected directly to the –IN and
+IN inputs of the AD629, differential input signals can also be
connected, as shown in Figure 39, to give a precise gain of 19.
However, large common-mode voltages are no longer permissible.
Cold junction compensation can be implemented using a
temperature sensor, such as the AD590.
REF (–)
REF (+)
+VS
+VS
NC
–IN
+IN
0.1µF
NC = NO CONNECT
21.1kΩ
380kΩ380kΩ
20kΩ
380kΩ
AD629
1
2
3
4
8
7
6
5
00783-037
VOU
T
VREF
THERMOCOUPLE
Figure 39. A Gain of 19 Thermocouple Amplifier
ERROR BUDGET ANALYSIS EXAMPLE 1
In the dc application that follows, the 10 A output current from
a device with a high common-mode voltage (such as a power
supply or current-mode amplifier) is sensed across a 1 Ω shunt
resistor (see Figure 40). The common-mode voltage is 200 V,
and the resistor terminals are connected through a long pair of
lead wires located in a high noise environment, for example,
50 Hz/60 Hz, 440 V ac power lines. The calculations in Table 7
assume an induced noise level of 1 V at 60 Hz on the leads, in
addition to a full-scale dc differential voltage of 10 V. The error
budget table quantifies the contribution of each error source.
Note that the dominant error source in this example is due to
the dc common-mode voltage.
REF (–)
OUTPUT
CURRENT
60Hz
POWER LINE
1Ω
SHUNT
REF (+)
–V
S
+V
S
V
OUT
NC
–IN
+IN
0.1µF
0.1µF
NC = NO CONNECT
21.1kΩ
380kΩ380kΩ
20kΩ
380kΩ
AD629
1
2
3
4
8
7
6
5
00783-038
10 AMPS
200V
CM
DC
TO GROUND
Figure 40. Error Budget Analysis Example 1: VIN = 10 V Full-Scale,
VCM = 200 V DC, RSHUNT = 1 Ω, 1 V p-p, 60 Hz Power-Line Interference
Table 7. AD629 vs. INA117 Error Budget Analysis Example 1 (VCM = 200 V dc)
Error, ppm of FS
Error Source AD629 INA117 AD629 INA117
ACCURACY, TA = 25°C
Initial Gain Error (0.0005 × 10)/10 V × 106 (0.0005 × 10)/10 V × 106 500 500
Offset Voltage (0.001 V/10 V) × 106 (0.002 V/10 V) × 106 100 200
DC CMR (Over Temperature) (224 × 10-6 × 200 V)/10 V × 106 (500 × 10-6 × 200 V)/10 V × 106 4480 10,000
Total Accuracy Error 5080 10,700
TEMPERATURE DRIFT (85°C)
Gain 10 ppm/°C × 60°C 10 ppm/°C × 60°C 600 600
Offset Voltage (20 μV/°C × 60°C) × 106/10 V (40 μV/°C × 60°C) × 106/10 V 120 240
Total Drift Error 720 840
RESOLUTION
Noise, Typical, 0.01 Hz to 10 Hz, μV p-p 15 μV/10 V × 106 25 μV/10 V × 106 2 3
CMR, 60 Hz (141 × 10-6 × 1 V)/10 V × 106 (500 × 10-6 × 1 V)/10 V × 106 14 50
Nonlinearity (10-5 × 10 V)/10 V × 106 (10-5 × 10 V)/10 V × 106 10 10
Total Resolution Error 26 63
Total Error 5826 11,603
AD629
Rev. C | Page 14 of 16
ERROR BUDGET ANALYSIS EXAMPLE 2
This application is similar to the previous example except
that the sensed load current is from an amplifier with an ac
common-mode component of ±100 V (frequency = 500 Hz)
present on the shunt (see Figure 41). All other conditions are
the same as before. Note that the same kind of power-line
interference can happen as detailed in Example 1. However,
the ac common-mode component of 200 V p-p coming from
the shunt is much larger than the interference of 1 V p-p;
therefore, this interference component can be neglected.
REF (–)
OUTPUT
CURRENT
60Hz
POWER LINE
1Ω
SHUNT
REF (+)
–V
S
+V
S
V
OUT
NC
–IN
+IN
0.1µF
0.1µF
NC = NO CONNECT
21.1kΩ
380kΩ380kΩ
20kΩ
380kΩ
AD629
1
2
3
4
8
7
6
5
00783-039
10 AMPS
±100V AC CM
TO GROUND
Figure 41. Error Budget Analysis Example 2: VIN = 10 V Full-Scale,
VCM = ±100 V at 500 Hz, RSHUNT =1 Ω
Table 8. AD629 vs. INA117 AC Error Budget Example 2 (VCM = ±100 V @ 500 Hz)
Error, ppm of FS
Error Source AD629 INA117 AD629 INA117
ACCURACY, TA = 25°C
Initial Gain Error (0.0005 × 10)/10 V × 106 (0.0005 × 10)/10 V × 106 500 500
Offset Voltage (0.001 V/10 V) × 106 (0.002 V/10 V) × 106 100 200
Total Accuracy Error 600 700
TEMPERATURE DRIFT (85°C)
Gain 10 ppm/°C × 60°C 10 ppm/°C × 60°C 600 600
Offset Voltage (20 μV/°C × 60°C) × 106/10 V (40 μV/°C × 60°C) × 106/10 V 120 240
Total Drift Error 720 840
RESOLUTION
Noise, Typical, 0.01 Hz to 10 Hz, μV p-p 15 μV/10 V × 106 25 μV/10 V × 106 2 3
CMR, 60 Hz (141 × 10-6 × 1 V)/10 V × 106 (500 × 10-6 × 1 V)/10 V × 106 14 50
Nonlinearity (10-5 × 10 V)/10 V × 106 (10-5 × 10 V)/10 V × 106 10 10
AC CMR @ 500 Hz (141 × 10-6 × 200 V)/10 V × 106 (500 × 10-6 × 200 V)/10 V × 106 2820 10,000
Total Resolution Error 2846 10,063
Total Error 4166 11,603
AD629
Rev. C | Page 15 of 16
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MS-001
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
070606-A
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
SEATING
PLANE
0.015
(0.38)
MIN
0.210 (5.33)
MAX
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
8
14
5
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.100 (2.54)
BSC
0.400 (10.16)
0.365 (9.27)
0.355 (9.02)
0.060 (1.52)
MAX
0.430 (10.92)
MAX
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
PLANE
0.005 (0.13)
MIN
Figure 42. 8-Lead Plastic Dual In-Line Package [PDIP]
(N-8)
Dimensions shown in inches and (millimeters)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-AA
012407-A
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099) 45°
8°
0°
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
4
1
85
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2441)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
Figure 43. 8-Lead Standard Small Outline Package [SOIC_N]
(R-8)
Dimensions shown in millimeters and (inches)
AD629
Rev. C | Page 16 of 16
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
AD629AN −40°C to +85°C 8-Lead PDIP N-8
AD629ANZ −40°C to +85°C 8-Lead PDIP N-8
AD629AR −40°C to +85°C 8-Lead SOIC_N R-8
AD629AR-REEL −40°C to +85°C 8-Lead SOIC_N R-8
AD629AR-REEL7 −40°C to +85°C 8-Lead SOIC_N R-8
AD629ARZ −40°C to +85°C 8-Lead SOIC_N R-8
AD629ARZ-RL −40°C to +85°C 8-Lead SOIC_N, 13-Inch Tape and Reel, 2,500 pieces R-8
AD629ARZ-R7 −40°C to +85°C 8-Lead SOIC_N, 7-Inch Tape and Reel, 1,000 pieces R-8
AD629BNZ −40°C to +85°C 8-Lead PDIP N-8
AD629BR −40°C to +85°C 8-Lead SOIC_N R-8
AD629BR-REEL −40°C to +85°C 8-Lead SOIC_N, 13-Inch Tape and Reel, 2,500 pieces R-8
AD629BR-REEL7 −40°C to +85°C 8-Lead SOIC_N, 7-Inch Tape and Reel, 1,000 pieces R-8
AD629BRZ −40°C to +85°C 8-Lead SOIC_N R-8
AD629BRZ-RL −40°C to +85°C 8-Lead SOIC_N, 13-Inch Tape and Reel, 2,500 pieces R-8
AD629BRZ-R7 −40°C to +85°C 8-Lead SOIC_N, 7-Inch Tape and Reel, 1,000 pieces R-8
AD629AC-WP −40°C to +85°C Die
1 Z = RoHS Compliant Part.
©1999-2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00783-0-4/11(C)
