SP7652ER-L/TR - EXAR - Datasheet.World

S

SP

P7

76

65

52

2

P

Po

ow

we

er

rb

bl

lo

ox

xT

TM

M

6

6A

A

2

28

8V

V

6

60

00

0K

KH

Hz

z

S

Sy

yn

nc

ch

hr

ro

on

no

ou

us

s

S

St

te

ep

p

D

Do

ow

wn

n

R

Re

eg

gu

ul

la

at

to

or

r

July 2012

Rev. 2.0.0

Exar Corporation www.exar.com

48720 Kato Road, Fremont CA 94538, USA Tel. +1 510 668-7000 – Fax. +1 510 668-7001

GENERAL DESCRIPTION

The SP7652 is a synchronous voltage mode

PWM step down (buck) regulator capable of a

constant output current up to 6Amps. A wide

2.5V to 28V power input voltage range, with

the required 5V biasing voltage, allows

conversions from industry standard 5V, 12V,

18V and 24V power rails.

With a 600kHz constant operating frequency

and integrated high and low side switch, the

SP7652 reduces the overall component count

and solution footprint. In addition to a 1%

output setpoint accuracy, this device provides

high efficiency, low ripple and excellent line

and load regulation. An enable function and

soft start feature allow for controlled power up

sequencing implementation.

Built-in Under voltage lockout (VLO) on both

VCC and VIN, outputs short-circuit and over

temperature protection insure safe operation

under abnormal operating conditions.

The SP7652 is offered in a RoHS compliant,

lead free 26-pin 7mmx4mm DFN package.

APPLICATIONS

 Distributed Power Architectures

 Point of Load Converters

 Power Supply Modules

 FPGAs, DSPs and Processors Supplies

FEATURES

 6A Continuous Current

 2.5V-28V Power Input Voltage Rail

 5V Biasing voltage

 0.8V Min. Output Voltage – 1% Accuracy

 PWM Voltage Mode Control

 600kHz Fixed Synchronous Operations

 Low RDSON Power Switches

 Greater than 92% Efficiency

 Type II & III Compensations Support

 Programmable Soft Start

 UVLO on both VIN and VCC

 Pre-biased Output Start-Up

 Over Temperature & Short Circuit

Protection/Auto-Restart

 RoHS Compliant Lead Free 26-Pin DFN

 US Patent #6,922,041

TYPICAL APPLICATION DIAGRAM

Fig. 1: SP7652 Application Diagram

S

SP

P7

76

65

52

2

P

Po

ow

we

er

rb

bl

lo

ox

xT

TM

M

6

6A

A

2

28

8V

V

6

60

00

0K

KH

Hz

z

S

Sy

yn

nc

ch

hr

ro

on

no

ou

us

s

S

St

te

ep

p

D

Do

ow

wn

n

R

Re

eg

gu

ul

la

at

to

or

r

ABSOLUTE MAXIMUM RATINGS

These are stress ratings only and functional operation of

the device at these ratings or any other above those

indicated in the operation sections of the specifications

below is not implied. Exposure to absolute maximum

rating conditions for extended periods of time may affect

reliability.

VIN ........................................................................ 30V

VCC ......................................................................... 7V

ILX ........................................................................ 10A

BST ...................................................................... 35V

LX-BST........................................................ -0.3V to 7V

LX ............................................................... -1V to 30V

All other pins ................................... -0.3V to (VCC+0.3)V

Storage Temperature .............................. -65°C to 150°C

Power Dissipation ................................ Internally Limited

Lead Temperature (Soldering, 10 sec).................... 300°C

ESD Rating (HBM - Human Body Model) ............. 2kV HBM

OPERATING RATINGS

Input Voltage Range VCC .............................. 4.5V to 5.5V

Input Voltage Range VIN .................................. 3V to 28V

Junction Temperature Range ................. -40°C to +125°C

Thermal Resistance θJC ........................................ 5°C/W

Thermal Resistance θJA ...................................... 36°C/W

ELECTRICAL SPECIFICATIONS

Specifications with standard type are for an Operating Junction Temperature of TJ = TA = 25°C only; limits applying over the

full Operating Junction Temperature range are denoted by a “•”. Minimum and Maximum limits are guaranteed through test,

design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = TA = 25°C, and are

provided for reference purposes only. Unless otherwise indicated, VCC = 4.5V to 5.5V, VIN = 3.0V to 28V, BST = LX + 5V,

LX = GND = 0V, UVIN = 3V, CVCC = 1µF, CCOMP = 0.1µF, CSS = 50nF, TA= –40°C to 85°C, TJ = –40°C to 125°C.

Parameter

Min.

Typ.

Max.

Units

Conditions

Quiescent Current

VCC Supply Current (No

Switching)

1.5

3

mA

VFB = 0.9V

VCC Supply Current (Switching)

11

15

mA

•

BST Supply Current (No

Switching)

0.2

0.4

mA

VFB = 0.9V

BST Supply Current (Switching)

8

12

mA

•

Protection: UVLO

VCC UVLO Start Threshold

4.00

4.25

4.5

v

VCC UVLO Hysteresis

100

200

300

mV

UVIN Start Threshold

2.3

2.5

2.65

V

•

UVIN Hysteresis

200

300

400

mV

UVIN Input Current

1

µA

UVIN = 3.0V

Error Amplifier Reference

0.792

0.800

0.808

V

2x Gain Config., Measure VFB; VCC=5V,

T=25°C

Error Amplifier Reference Over

Line and Temperature

0.788

0.800

0.812

V

•

Error Amplifier

Transconductance

6

mA/V

Error Amplifier Gain

60

dB

No Load

COMP Sink Current

150

µA

VFB = 0.9V, COMP = 0.9V

COMP Source Current

150

µA

VFB = 0.7V, COMP = 2.2V

VFB Input Bias Current

50

200

nA

VFB = 0.8V

Internal Pole

4

MHz

COMP Clamp

2.5

V

VFB = 0.7V, TA=25°C

COMP Clamp Temp. Coefficient

-2

mV/°C

S

SP

P7

76

65

52

2

P

Po

ow

we

er

rb

bl

lo

ox

xT

TM

M

6

6A

A

2

28

8V

V

6

60

00

0K

KH

Hz

z

S

Sy

yn

nc

ch

hr

ro

on

no

ou

us

s

S

St

te

ep

p

D

Do

ow

wn

n

R

Re

eg

gu

ul

la

at

to

or

r

Parameter

Min.

Typ.

Max.

Units

Conditions

Control Loop: PWM Comparator, Ramp & Loop Delay Path

Ramp Amplitude

0.92

1.1

1.28

V

Ramp Offset

1.1

V

•

TA=25°C, Ramp COMP

Ramp Offset Temp. Coefficient

-2

mV/°C

GH Minimum Pulse width

90

180

ns

•

Maximum Controllable Duty

Ratio

92

97

%

Maximum Duty Ratio measured just

before pulsing begins

Maximum Duty Ratio

100

%

Valid for 20 cycles

Internal Oscillator Ratio

420

600

720

kHz

•

Timers: Soft Start

SS Charge Current

10

µA

SS Discharge Current

1

mA

•

Fault Present, SS = 0.2V

Protection: Short Circuit & Thermal

Short Circuit Threshold Voltage

0.2

0.25

0.3

V

•

Measured (VREF(0.8V)-VFB)

Hiccup Timeout

200

ms

VFB = 0.5V

Number of Allowable Clock

Cycles at 100% Duty Cycle

20

Cycles

Minimum GL Pulse After 20

Cycles

0.5

Cycles

VFB = 0.7V

Thermal Shutdown Temperature

145

°C

VFB = 0.7V

Thermal Recovery Temperature

135

°C

Thermal Hysteresis

10

°C

Output: Power Stage

High Side RDSON

15

mΩ

VCC = 5V ; IOUT= 6A, TA = 25°C

Synchronous FET RDSON

15

mΩ

VCC = 5V ; IOUT= 6A, TA = 25°C

Maximum Output Current

6

A

PIN ASSIGNMENT

Fig. 2: SP7652 Pin Assignment

S

SP

P7

76

65

52

2

P

Po

ow

we

er

rb

bl

lo

ox

xT

TM

M

6

6A

A

2

28

8V

V

6

60

00

0K

KH

Hz

z

S

Sy

yn

nc

ch

hr

ro

on

no

ou

us

s

S

St

te

ep

p

D

Do

ow

wn

n

R

Re

eg

gu

ul

la

at

to

or

r

PIN DESCRIPTION

Name

Pin Number

Description

PGND

1, 2, 3

Ground connection for the synchronous rectifier.

GND

4, 8, 19, 20, 21

Ground Pin. The control circuitry of the IC and lower power driver are referenced to this

pin. Return separately from other ground traces to the (-) terminal of COUT.

VFB

5

Feedback Voltage and Short Circuit Detection pin. The inverting input of the Error

Amplifier and serves as the output voltage feedback point for the Buck Converter. The

output voltage is sensed and can be adjusted through an external resistor divider.

Whenever VFB drops 0.25V below the positive reference, a short circuit fault is detected

and the IC enters hiccup mode.

COMP

6

Output of the Error Amplifier. Internally connected to the inverting input of the PWM

comparator. An optimal filter combination is chosen and connected to this pin and

either ground or VFB to stabilize the voltage mode loop.

UVIN

7

UVLO input for VIN voltage. Connect a resistor divider between VIN and UVIN to set

minimum operating voltage.

SS

9

Soft Start. Connect an external capacitor between SS and GND to set the soft start rate

based on the 10μA source current. The SS pin is held low via a 1mA (min.) current

during all fault conditions.

VIN

10, 11, 12, 13

Input connection to the high-side N-channel MOSFET. Place a decoupling capacitor

between this pin and PGND.

LX

14, 15, 16,

23, 24, 25, 26

Connect an inductor between this pin and VOUT.

NC

17

No Connect.

BST

18

High-side driver supply pin. Connect BST to the external boost diode and capacitor as

shown in the Typical Application Circuit on page one. High-side driver is connected

between BST and SWN pin.

VCC

22

Input for external 5V bias supply

-

Exposed Pad 1

Connect to LX through PCB.

-

Exposed Pad 2

Exposed Pad 1

Connect to GND through PCB.

-

Exposed Pad 3

Exposed Pad 1

Connect to VIN through PCB.

ORDERING INFORMATION

Part Number

Junction

Temperature

Range

Marking

Package

Packing

Quantity

Note 1

Note 2

SP7652ER-L

-40°C≤TJ≤+125°C

SP7652ER

YYWWL

X

7mm x 4mm

26-pin DFN

Bulk

Lead Free

SP7652ER-L/TR

3K/Tape & Reel

Lead Free

SP7662EB

SP7652 Evaluation Board

“YY” = Year – “WW” = Work Week – “X” = Lot Number; when applicable.

S

SP

P7

76

65

52

2

P

Po

ow

we

er

rb

bl

lo

ox

xT

TM

M

6

6A

A

2

28

8V

V

6

60

00

0K

KH

Hz

z

S

Sy

yn

nc

ch

hr

ro

on

no

ou

us

s

S

St

te

ep

p

D

Do

ow

wn

n

R

Re

eg

gu

ul

la

at

to

or

r

TYPICAL PERFORMANCE CHARACTERISTICS

All data taken at VIN = 2.7V to 5.5V, TJ = TA = 25°C, unless otherwise specified - Schematic and BOM from Application

Information section of this datasheet.

Fig. 3: Efficiency versus Output Current

VIN=8V, 12V and 15V, VOUT=5V

Fig. 4: Output Voltage versus Output Current

VIN=8V, 12V and 15V

Fig. 5: Efficiency versus Output Current

VIN=5V, VOUT=3.3V

Fig. 6: Output Voltage versus Output Current

VIN=5V, VOUT=3.3V

Fig. 7: Efficiency versus Output Current

VIN=3.3V, VOUT=0.8V

Fig. 8: Output Voltage versus Output Current

VIN=3.3V, VOUT=0.8V

S

SP

P7

76

65

52

2

P

Po

ow

we

er

rb

bl

lo

ox

xT

TM

M

6

6A

A

2

28

8V

V

6

60

00

0K

KH

Hz

z

S

Sy

yn

nc

ch

hr

ro

on

no

ou

us

s

S

St

te

ep

p

D

Do

ow

wn

n

R

Re

eg

gu

ul

la

at

to

or

r

Fig. 9: Efficiency versus Output Current

VIN=12V

Fig. 10: Efficiency versus Output Current

VIN=5V

Fig. 11: Efficiency versus Output Current

VIN=3.3V

S

SP

P7

76

65

52

2

P

Po

ow

we

er

rb

bl

lo

ox

xT

TM

M

6

6A

A

2

28

8V

V

6

60

00

0K

KH

Hz

z

S

Sy

yn

nc

ch

hr

ro

on

no

ou

us

s

S

St

te

ep

p

D

Do

ow

wn

n

R

Re

eg

gu

ul

la

at

to

or

r

THEORY OF OPERATION

GENERAL OVERVIEW

The SP7652 is a fixed frequency, voltage

mode, synchronous PWM regulator optimized

for high efficiency. The part has been designed

to be especially attractive for split plane

applications utilizing 5V to power the controller

and 3V to 20V for step down conversion.

The heart of the SP7652 is a wide bandwidth

transconductance amplifier designed to

accommodate Type II and Type III

compensation schemes. A precision 0.8V

reference, present on the positive terminal of

the error amplifier, permits the programming

of the output voltage down to 0.8V via the VFB

pin. The output of the error amplifier, COMP,

which is compared to a 1.1V peak-to-peak

ramp, is responsible for trailing edge PWM

control. This voltage ramp and PWM control

logic are governed by the internal oscillator

that accurately sets the PWM frequency to

600kHz.

The SP7652 contains two unique control

features that are very powerful in distributed

applications. First, asynchronous driver control

is enabled during start up, to prohibit the low

side NFET from pulling down the output until

the high side NFET has attempted to turn on.

Second, a 100% duty cycle timeout ensures

that the low side NFET is periodically enhanced

during extended periods at 100% duty cycle.

This guarantees the synchronized refreshing of

the BST capacitor during very large duty cycle

ratios.

The SP7652 also contains a number of

valuable protection features. Programmable

UVLO allows the user to set the exact VIN

value at which the conversion voltage can

safely begin down conversion, and an internal

VCC UVLO ensures that the controller itself has

enough voltage to operate properly. Other

protection features include thermal shutdown

and short-circuit detection. In the event that

either a thermal, short-circuit, or UVLO fault is

detected, the SP7652 is forced into an idle

state where the output drivers are held off for

a finite period before a re-start is attempted.

SOFT START

Soft start is achieved when a power converter

ramps up the output voltage while controlling

the magnitude of the input supply source

current. In a modern step down converter,

ramping up the positive terminal of the error

amplifier controls soft start. As a result,

excess source current can be defined as the

current required to charge the output

capacitor.

IVIN = COUT * (ΔVOUT / ΔTSOFT-START)

The SP7652 provides the user with the option

to program the soft start rate by tying a

capacitor from the SS pin to GND. The

selection of this capacitor is based on the

10μA pull up current present at the SS pin and

the 0.8V reference voltage. Therefore, the

excess source can be redefined as:

IVIN = COUT * (ΔVOUT *10μA / (CSS * 0.8V)

UNDER VOLTAGE LOCK OUT (UVLO)

The SP7652 contains two separate UVLO

comparators to monitor the internal bias (VCC)

and conversion (VIN) voltages independently.

The VCC UVLO threshold is internally set to

4.25V, whereas the VIN UVLO threshold is

programmable through the UVIN pin. When

the UVIN pin is greater than 2.5V, the SP7652

is permitted to start up pending the removal of

all other faults. Both the VCC and VIN UVLO

comparators have been designed with

hysteresis to prevent noise from resetting a

fault.

THERMAL AND SHORT-CIRCUIT PROTECTION

Because the SP7652 is designed to drive large

output current, there is a chance that the

power converter will become too hot.

Therefore, an internal thermal shutdown

(145°C) has been included to prevent the IC

from malfunctioning at extreme temperatures.

A short-circuit detection comparator has also

been included in the SP7652 to protect against

an accidental short at the output of the power

converter. This comparator constantly

monitors the positive and negative terminals

of the error amplifier, and if the VFB pin falls

more than 250mV (typical) below the positive

S

SP

P7

76

65

52

2

P

Po

ow

we

er

rb

bl

lo

ox

xT

TM

M

6

6A

A

2

28

8V

V

6

60

00

0K

KH

Hz

z

S

Sy

yn

nc

ch

hr

ro

on

no

ou

us

s

S

St

te

ep

p

D

Do

ow

wn

n

R

Re

eg

gu

ul

la

at

to

or

r

reference, a short-circuit fault is set. Because

the SS pin overrides the internal 0.8V

reference during soft start, the SP7652 is

capable of detecting short-circuit faults

throughout the duration of soft start as well as

in regular operation.

HANDLING OF FAULTS

Upon the detection of power (UVLO), thermal,

or short-circuit faults, the SP7652 is forced

into an idle state where the SS and COMP pins

are pulled low and the NFETS are held off. In

the event of UVLO fault, the SP7652 remains

in this idle state until the UVLO fault is

removed. Upon the detection of a thermal or

short-circuit fault, an internal 200ms timer is

activated. In the event of a short-circuit fault,

a re-start is attempted immediately after the

200ms timeout expires. Whereas, when a

thermal fault is detected, the 200ms delay

continuously recycles and a re-start cannot be

attempted until the thermal fault is removed

and the timer expires.

ERROR AMPLIFIER AND VOLTAGE LOOP

Since the heart of the SP7652 voltage error

loop is a high performance, wide bandwidth

transconductance amplifier, great care should

be taken to select the optimal compensation

network. Because of the amplifier’s current

limited (±150μA) transconductance, there are

many ways to compensate the voltage loop or

to control the COMP pin externally. If a simple,

single-pole, single-zero response is desired,

then compensation can be as simple as an RC

circuit to Ground. If a more complex

compensation is required, then the amplifier

has enough bandwidth (45°C at 4MHz) and

enough gain (60dB) to run Type III

compensation schemes with adequate gain

and phase margins at cross over frequencies

greater than 50kHz.

The common mode output of the error

amplifier is 0.9V to 2.2V. Therefore, the PWM

voltage ramp has been set between 1.1V and

2.2V to ensure proper 0% to 100% duty cycle

capability. The voltage loop also includes two

other very important features. One is an

asynchronous startup mode. Basically, the

synchronous rectifier cannot turn on unless

the high-side NFET has attempted to turn on

or the SS pin has exceeded 1.7V. This feature

prevents the controller from “dragging down”

the output voltage during startup or in fault

modes. The second feature is a 100% duty

cycle timeout that ensures synchronized

refreshing of the BST capacitor at very high

duty ratios. In the event that the high-side

NFET is on for 20 continuous clock cycles, a

reset is given to the PWM flip-flop half way

through the 21st cycle. This forces GL to rise

for the cycle, in turn refreshing the BST

capacitor.

POWER MOSFETS

The SP7652 contains a pair of integrated low

resistance N-MOSFETs designed to drive up to

6A of output current. Maximum output current

could be limited by thermal limitations of a

particular application. The SP7652

incorporates a built-in over-temperature

protection to prevent internal overheating.

SETTING OUTPUT VOLTAGES

The SP7652 can be set to different output

voltages. The relationship in the following

formula is based on a voltage divider from the

output to the feedback pin VFB, which is set to

an internal reference voltage of 0.80V.

S

SP

P7

76

65

52

2

P

Po

ow

we

er

rb

bl

lo

ox

xT

TM

M

6

6A

A

2

28

8V

V

6

60

00

0K

KH

Hz

z

S

Sy

yn

nc

ch

hr

ro

on

no

ou

us

s

S

St

te

ep

p

D

Do

ow

wn

n

R

Re

eg

gu

ul

la

at

to

or

r

Standard 1% metal film resistors of surface

mount size 0603 are recommended.

Where R1 = 68.1kΩ and for VOUT = 0.80V

setting, simply remove R2 from the board.

Furthermore, one could select the value of the

R1 and R2 combination to meet the exact

output voltage setting by restricting R1

resistance range such that 50kΩ<R1<100kΩ

for overall system loop stability.

APPLICATION INFORMATION

INDUCTOR SELECTION

There are many factors to consider in selecting

the inductor including core material,

inductance vs. frequency, current handling

capability, efficiency, size and EMI. In a typical

SP7652 circuit, the inductor is chosen

primarily by operating frequency, saturation

current and DC resistance. Increasing the

inductor value will decrease output voltage

ripple, but degrade transient response. Low

inductor values provide the smallest size, but

cause large ripple currents, poor efficiency and

require more output capacitance to smooth

out the larger ripple current. The inductor

must be able to handle the peak current at the

switching frequency without saturating, and

the copper resistance in the winding should be

kept as low as possible to minimize resistive

power loss. A good compromise between size,

loss and cost is to set the inductor ripple

current to be within 20% to 40% of the

maximum output current.

The switching frequency and the inductor

operating point determine the inductor value

as follows:

where:

Fs = switching frequency

KrR = ratio of the AC inductor ripple current to

the maximum output current.

The peak to peak inductor ripple current is:

Once the required inductor value is selected,

the proper selection of core material is based

on peak inductor current and efficiency

requirements.

The core must be large enough not to saturate

at the peak inductor current

and provide low core loss at the high switching

frequency. Low cost powdered-iron cores are

inappropriate for 900kHz operation. Gapped

ferrite inductors are widely available for

consideration. Select devices that have

operating data shown up to 1 MHz. Ferrite

materials, on the other hand, are more

expensive and have an abrupt saturation

characteristic with the inductance dropping

sharply when the peak design current is

exceeded. Nevertheless, they are preferred at

high switching frequencies because they

present very low core loss and the design only

needs to prevent saturation. In general, ferrite

or molypermalloy materials are better choice

for all but the most cost sensitive applications.

OPTIMIZING EFFICIENCY

The power dissipated in the inductor is equal

to the sum of the core and copper losses. To

minimize copper losses, the winding resistance

needs to be minimized, but this usually comes

at the expense of a larger inductor. Core

losses have a more significant contribution at

low output current where the copper losses

are at a minimum, and can typically be

S

SP

P7

76

65

52

2

P

Po

ow

we

er

rb

bl

lo

ox

xT

TM

M

6

6A

A

2

28

8V

V

6

60

00

0K

KH

Hz

z

S

Sy

yn

nc

ch

hr

ro

on

no

ou

us

s

S

St

te

ep

p

D

Do

ow

wn

n

R

Re

eg

gu

ul

la

at

to

or

r

neglected at higher output currents where the

copper losses dominate. Core loss information

is usually available from the magnetics

vendor. Proper inductor selection can affect

the resulting power supply efficiency by more

than 15-20%!

The copper loss in the inductor can be

calculated

using the following equation:

PL(CU) = I2L(RMS) RWINDING

where IL(RMS) is the RMS inductor current that

can be calculated as follows:

OUTPUT CAPACITOR SELECTION

The required ESR (Equivalent Series

Resistance) and capacitance drive the

selection of the type and quantity of the

output capacitors. The ESR must be small

enough that both the resistive voltage

deviation due to a step change in the load

current and the output ripple voltage do not

exceed the tolerance limits expected on the

output voltage. During an output load

transient, the output capacitor must supply all

the additional current demanded by the load

until the SP7652 adjusts the inductor current

to the new value.

In order to maintain VOUT, the capacitance

must be large enough so that the output

voltage is held up while the inductor current

ramps up or down to the value corresponding

to the new load current. Additionally, the ESR

in the output capacitor causes a step in the

output voltage equal to the current. Because

of the fast transient response and inherent

100% to 0% duty cycle capability provided by

the SP7652 when exposed to output load

transient, the output capacitor is typically

chosen for ESR, not for capacitance value.

The ESR of the output capacitor, combined

with the inductor ripple current, is typically the

main contributor to output voltage ripple. The

maximum allowable ESR required to maintain

a specified output voltage ripple can be

calculated by:

where:

ΔVOUT = Peak-to-Peak Output Voltage Ripple

IPK-PK= Peak-to-Peak Inductor Current

The total output ripple is a combination of the

ESR and the output capacitance value and can

be calculated as follows:

FS = Switching Frequency

D = Duty Cycle

COUT = Output Capacitance Value

INPUT CAPACITOR SELECTION

The input capacitor should be selected for

ripple current rating, capacitance and voltage

rating. The input capacitor must meet the

ripple current requirement imposed by the

switching current. In continuous conduction

mode, the source current of the high-side

MOSFET is approximately a square wave of

duty cycle VOUT/VIN. Most of this current is

supplied by the input bypass capacitors. The

RMS value of input capacitor current is

determined at the maximum output current

and under the assumption that the peak to

peak inductor ripple current is low; it is given

by:

ICIN(RMS)= IOUT(MAX) √D(1-D)

The worse case occurs when the duty cycle D

is 50% and gives an RMS current value equal

to IOUT/2.

Select input capacitors with adequate ripple

current rating to ensure reliable operation.

The power dissipated in the input capacitor is:

PCIN=I2CIN(RMS) RESR(CIN)

This can become a significant part of power

losses in a converter and hurt the overall

energy transfer efficiency. The input voltage

ripple primarily depends on the input capacitor

ESR and capacitance. Ignoring the inductor

S

SP

P7

76

65

52

2

P

Po

ow

we

er

rb

bl

lo

ox

xT

TM

M

6

6A

A

2

28

8V

V

6

60

00

0K

KH

Hz

z

S

Sy

yn

nc

ch

hr

ro

on

no

ou

us

s

S

St

te

ep

p

D

Do

ow

wn

n

R

Re

eg

gu

ul

la

at

to

or

r

ripple current, the input voltage ripple can be

determined by:

The capacitor type suitable for the output

capacitors can also be used for the input

capacitors. However, exercise additional

caution when tantalum capacitors are used.

Tantalum capacitors are known for

catastrophic failure when exposed to surge

current, and input capacitors are prone to

such surge current when power supplies are

connected “live” to low impedance power

sources.

LOOP COMPENSATION DESIGN

The open loop gain of the whole system can

be divided into the gain of the error amplifier,

PWM modulator, buck converter output stage,

and feedback resistor divider. In order to cross

over at the selected frequency fcoFCO, the

gain of the error amplifier compensates for the

attenuation caused by the rest of the loop at

this frequency.

The goal of loop compensation is to

manipulate loop frequency response such that

its gain crosses over 0db at a slope of -

20db/dec. The first step of compensation

design is to pick the loop crossover frequency.

High crossover frequency is desirable for fast

transient response, but often jeopardizes the

system stability. Crossover frequency should

be higher than the ESR zero but less than 1/5

of the switching frequency. The ESR zero is

contributed by the ESR associated with the

output capacitors and can be determined by:

The next step is to calculate the complex

conjugate poles contributed by the LC output

filter,

When the output capacitors are of a Ceramic

Type, the SP7652 Evaluation Board requires a

Type III compensation circuit to give a phase

boost of 180° in order to counteract the

effects of an underdamped resonance of the

output filter at the double pole frequency

Fig. 12: SP7652 Voltage Mode Control Loop

S

SP

P7

76

65

52

2

P

Po

ow

we

er

rb

bl

lo

ox

xT

TM

M

6

6A

A

2

28

8V

V

6

60

00

0K

KH

Hz

z

S

Sy

yn

nc

ch

hr

ro

on

no

ou

us

s

S

St

te

ep

p

D

Do

ow

wn

n

R

Re

eg

gu

ul

la

at

to

or

r

Definitions:

RESR = Output Capacitor Equivalent Series Resistance

RDC = Output Inductor DC Resistance

RRAMP_PP = SP7652 internal Ramp Amplitude Peak to Peak Voltage

Conditions:

CZ2 >> Cp1 and R1 >> RZ3

Output Load Resistance >> RESR and RDC

Fig. 13: Bode Plot of Type III Error Amplifier Compensation

Fig. 14: Type III Error Amplifier Compensation Circuit

SP765X THERMAL RESISTANCE

The SP765X family has been tested with a

variety of footprint layouts along with

different copper area and thermal resistance

has been measured. The layouts were done

on 4 layer FR4 PCB with the top and bottom

layers using 3oz copper and the power and

ground layers using 1oz copper.

For the Minimum footprint, only about 0.1

square inch (of 3 ounces of) Copper was used

on the top or footprint layer, and this layer

had no vias to connect to the 3 other layers.

For the Medium footprint, about 0.7 square

inches (of 3 ounces of) Copper was used on

the top layer, but vias were used to connect

to the other 3 layers. For the Maximum

footprint, about .0 square inch (of 3 ounces

of) Copper was used on the top layer and

many vias were used to connect to the 3

other layers.

The results show that only about 0.7 square

inches (of 3 ounces of) Copper on the top

layer and vias connecting to the 3 other

layers are needed to get the best thermal

resistance of 36°C/W. Adding area on the top

beyond the 0.7 square inches did not reduce

thermal resistance.

Using a minimum of 0.1 square inches of (3

ounces of) Copper on the top layer with no

vias connecting to the 3 other layers

produced a thermal resistance of 44°C/W.

This thermal impedance is only 22% higher

than the medium and large footprint layouts,

indicating that space constrained designs can

still benefit thermally from the Powerblox

family of ICs. This indicates that a minimum

footprint of 0.1 square inch, if used on a 4

layer board, can produce 44°C/W thermal

resistance. This approach is still very

worthwhile if used in a space constrained

design.

S

SP

P7

76

65

52

2

P

Po

ow

we

er

rb

bl

lo

ox

xT

TM

M

6

6A

A

2

28

8V

V

6

60

00

0K

KH

Hz

z

S

Sy

yn

nc

ch

hr

ro

on

no

ou

us

s

S

St

te

ep

p

D

Do

ow

wn

n

R

Re

eg

gu

ul

la

at

to

or

r

The following figures show the footprint

layouts from an ORCAD file. The thermal data

was taken for still air, not with forced air. If

forced air is used, some improvement in

thermal resistance would be seen.

SP765X THERMAL RESISTANCE

4 Layer Board:

 Top Layer 3ounces Copper

 GND Layer 1ounce Copper

 Power Layer ounce Copper

 Bottom Layer 3ounces Copper

Minimum Footprint: 44°C/W

Top Layer: 0.1 square inch

No Vias to other 3 Layers

Fig. 15: Minimum Footprint = 0.10in2

Medium Footprint: 36°C/W

Top Layer: 0.7 square inch

Vias to other 3 Layers

Fig. 16: Medium Footprint = 0.70in2

Maximum Footprint: 36°C/W

Top Layer: .0 square inch

Vias to other 3 Layers

Fig. 17: Maximum Footprint = 1.0in2

S

SP

P7

76

65

52

2

P

Po

ow

we

er

rb

bl

lo

ox

xT

TM

M

6

6A

A

2

28

8V

V

6

60

00

0K

KH

Hz

z

S

Sy

yn

nc

ch

hr

ro

on

no

ou

us

s

S

St

te

ep

p

D

Do

ow

wn

n

R

Re

eg

gu

ul

la

at

to

or

r

PACKAGE SPECIFICATION

26 PIN DFN

S

SP

P7

76

65

52

2

P

Po

ow

we

er

rb

bl

lo

ox

xT

TM

M

6

6A

A

2

28

8V

V

6

60

00

0K

KH

Hz

z

S

Sy

yn

nc

ch

hr

ro

on

no

ou

us

s

S

St

te

ep

p

D

Do

ow

wn

n

R

Re

eg

gu

ul

la

at

to

or

r

REVISION HISTORY

Revision

Date

Description

2.0.0

07/15/16/2012

Reformat of Datasheet

FOR FURTHER ASSISTANCE

Email: customersupport@exar.com

Exar Technical Documentation: http://www.exar.com/TechDoc/default.aspx?

EXAR CORPORATION

HEADQUARTERS AND SALES OFFICES

48720 Kato Road

Fremont, CA 94538 – USA

Tel.: +1 (510) 668-7000

Fax: +1 (510) 668-7030

www.exar.com

NOTICE

EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve

design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein,

conveys no license under any patent or other right, and makes no representation that the circuits are free of patent

infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a

user’s specific application. While the information in this publication has been carefully checked; no responsibility, however,

is assumed for inaccuracies.

EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or

malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its

safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in

writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all

such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances.

Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.