1
LTC1871-1
18711fa
Wide Input Range, No R
SENSE
TM
Current Mode Boost,
Flyback and SEPIC Controller
The LTC
®
1871-1 is a wide input range, current mode,
boost, flyback or SEPIC controller that drives an N-
channel power MOSFET and requires very few external
components. It eliminates the need for a current sense
resistor by utilizing the power MOSFET’s on-resistance,
thereby maximizing efficiency. Higher output voltage
applications are possible with the LTC1871-1 by connect-
ing the SENSE pin to a resistor in the source of the power
MOSFET.
The IC’s operating frequency can be set with an external
resistor over a 50kHz to 1MHz range, and can be synchro-
nized to an external clock using the MODE/SYNC pin.
The LTC1871-1 differs from the LTC1871 by having a
lower pulse skip threshold, making it ideal for applica-
tions requiring constant frequency operation at light
loads. The lower pulse skip threshold also helps maintain
constant frequency operation in applications with a wide
input voltage range. For applications requiring primary-
to-secondary side isolation, please refer to the LTC1871
datasheet.
The LTC1871-1 is available in the 10-lead MSOP package.
High Efficiency (No Sense Resistor Required)
Wide Input Voltage Range: 2.5V to 36V
Current Mode Control Provides Excellent
Transient Response
High Maximum Duty Cycle (92% Typ)
±2% RUN Pin Threshold with 100mV Hysteresis
±1% Internal Voltage Reference
Ultra Low Pulse Skip Threshold for Wide Input
Range Applications
Micropower Shutdown: I
Q
= 10μA
Programmable Operating Frequency
(50kHz to 1MHz) with One External Resistor
Synchronizable to an External Clock Up to 1.3 × f
OSC
User-Controlled Pulse Skip or Burst Mode
®
Operation
Internal 5.2V Low Dropout Voltage Regulator
Output Overvoltage Protection
Capable of Operating with a Sense Resistor for High
Output Voltage Applications
Small 10-Lead MSOP Package
Telecom Power Supplies
Portable Electronic Equipment
Figure 1. High Efficiency 3.3V Input, 5V Output Boost Converter (Bootstrapped)
Efficiency of Figure 1
OUTPUT CURRENT (A)
30
EFFICIENCY (%)
90
100
80
50
70
60
40
0.001 0.1 1 10
1871 F01b
0.01
Burst Mode
OPERATION
PULSE-SKIP
MODE
DESCRIPTIO
U
FEATURES
APPLICATIO S
U
TYPICAL APPLICATIO
U
+
RUN
I
TH
FB
FREQ
MODE/SYNC
SENSE
V
IN
INTV
CC
GATE
GND
LTC1871-1
R
T
80.6k
1%
R2
37.4k
1%
R1
12.1k
1% C
VCC
4.7μF
X5R
C
IN
22μF
6.3V
×2
M1
D1
L1
1μH
R
C
22k
C
C1
6.8nF
C
C2
47pF
C
OUT1
150μF
6.3V
×4
V
IN
3.3V
V
OUT
5V
7A
(10A PEAK)
GND
1871 F01a
+
C
OUT2
22μF
6.3V
X5R
×2
C
IN
: TAIYO YUDEN JMK325BJ226MM
C
OUT1
: PANASONIC EEFUEOJ151R
C
OUT2
: TAIYO YUDEN JMK325BJ226MM
D1: MBRB2515L
L1: SUMIDA CEP125-H 1R0MH
M1: FAIRCHILD FDS7760A
, LT, LTC, LTM and Burst Mode are registered trademarks of Linear Technology
Corporation. No R
SENSE
is a trademark of Linear Technology Corporation. All other
trademarks are the property of their respective owners.
2
LTC1871-1
18711fa
ELECTRICAL CHARACTERISTICS
The denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VIN = 5V, VRUN = 1.5V, RFREQ = 80k, VMODE/SYNC = 0V, unless otherwise specified.
(Note 1)
V
IN
Voltage ...............................................0.3V to 36V
INTV
CC
Voltage ...........................................0.3V to 7V
INTV
CC
Output Current ........................................ 50mA
GATE Voltage ...........................0.3V to V
INTVCC
+ 0.3V
I
TH
, FB Voltages .......................................0.3V to 2.7V
RUN, MODE/SYNC Voltages .......................0.3V to 7V
FREQ Voltage ............................................0.3V to 1.5V
SENSE Pin Voltage ...................................0.3V to 36V
Operating Junction Temperature Range (Note 2)
LTC1871E-1 ....................................... 40°C to 85°C
LTC1871I-1 ...................................... 40°C to 125°C
Junction Temperature (Note 3)............................ 125°C
Storage Temperature Range ................. 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
ABSOLUTE AXI U RATI GS
WWWU
PACKAGE/ORDER I FOR ATIO
UU
W
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Main Control Loop
V
IN(MIN)
Minimum Input Voltage 2.5 V
I-Grade (Note 2) 2.5 V
I
Q
Input Voltage Supply Current (Note 4)
Continuous Mode V
MODE/SYNC
= 5V, V
FB
= 1.4V, V
ITH
= 0.75V 550 1000 μA
V
MODE/SYNC
= 5V, V
FB
= 1.4V, V
ITH
= 0.75V, 550 1000 μA
I-Grade (Note 2)
Burst Mode Operation, No Load V
MODE/SYNC
= 0V, V
ITH
= 0V (Note 5) 250 500 μA
V
MODE/SYNC
= 0V, V
ITH
= 0V (Note 5), 250 500 μA
I-Grade (Note 2)
Shutdown Mode V
RUN
= 0V 10 20 μA
V
RUN
= 0V, I-Grade (Note 2) 10 20 μA
V
RUN+
Rising RUN Input Threshold Voltage 1.348 V
V
RUN
Falling RUN Input Threshold Voltage 1.223 1.248 1.273 V
1.198 1.298 V
V
RUN(HYST)
RUN Pin Input Threshold Hysteresis 50 100 150 mV
I-Grade (Note 2) 35 100 175 mV
I
RUN
RUN Input Current 160 nA
V
FB
Feedback Voltage V
ITH
= 0.4V (Note 5) 1.218 1.230 1.242 V
1.212 1.248 V
V
ITH
= 0.4V (Note 5), I-Grade (Note 2) 1.205 1.255 V
I
FB
FB Pin Input Current V
ITH
= 0.4V (Note 5) 18 60 nA
ΔV
FB
Line Regulation 2.5V V
IN
30V 0.002 0.02 %/V
ΔV
IN
2.5V V
IN
30V, I-Grade (Note 2) 0.002 0.03 %/V
T
JMAX
= 125°C, θ
JA
= 120°C/ W
1
2
3
4
5
RUN
I
TH
FB
FREQ
MODE/
SYNC
10
9
8
7
6
SENSE
V
IN
INTV
CC
GATE
GND
TOP VIEW
MS PACKAGE
10-LEAD PLASTIC MSOP
ORDER PART NUMBER *MS PART MARKING
Consult LTC Marketing for parts specified with wider operating temperature ranges.
*The temperature grade is identified by a label on the shipping container.
LTC1871EMS-1
LTC1871IMS-1
LTCTV
LTCTV
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
3
LTC1871-1
18711fa
ELECTRICAL CHARACTERISTICS
The denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VIN = 5V, VRUN = 1.5V, RFREQ = 80k, VMODE/SYNC = 0V, unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
ΔV
FB
Load Regulation V
MODE/SYNC
= 0V, V
ITH
= 0.5V to 0.9V (Note 5) –1 –0.1 %
ΔV
ITH
V
MODE/SYNC
= 0V, V
ITH
= 0.5V to 0.9V (Note 5) –1 –0.1 %
I-Grade (Note 2)
ΔV
FB(OV)
ΔFB Pin, Overvoltage Lockout V
FB(OV)
– V
FB(NOM)
in Percent 2.5 6 10 %
g
m
Error Amplifier Transconductance I
TH
Pin Load = ±5μA (Note 5) 650 μmho
V
ITH(BURST)
Burst Mode Operation I
TH
Pin Voltage Falling I
TH
Voltage (Note 5) 195 mV
V
SENSE(MAX)
Maximum Current Sense Input Threshold Duty Cycle < 20% 120 150 180 mV
Duty Cycle < 20%, I-Grade (Note 2) 100 200 mV
I
SENSE(ON)
SENSE Pin Current (GATE High) V
SENSE
= 0V 35 50 μA
I
SENSE(OFF)
SENSE Pin Current (GATE Low) V
SENSE
= 30V 0.1 5 μA
Oscillator
f
OSC
Oscillator Frequency R
FREQ
= 80k 250 300 350 kHz
R
FREQ
= 80k, I-Grade (Note 2) 250 300 350 kHz
Oscillator Frequency Range 50 1000 kHz
I-Grade (Note 2) 50 1000 kHz
D
MAX
Maximum Duty Cycle 87 92 97 %
I-Grade (Note 2) 87 92 97 %
f
SYNC/
f
OSC
Recommended Maximum Synchronized f
OSC
= 300kHz (Note 6) 1.25 1.30
Frequency Ratio
f
OSC
= 300kHz (Note 6), I-Grade (Note 2) 1.25 1.30
t
SYNC(MIN)
MODE/SYNC Minimum Input Pulse Width V
SYNC
= 0V to 5V 25 ns
t
SYNC(MAX)
MODE/SYNC Maximum Input Pulse Width V
SYNC
= 0V to 5V 0.8/f
OSC
ns
V
IL(MODE)
Low Level MODE/SYNC Input Voltage 0.3 V
I-Grade (Note 2) 0.3 V
V
IH(MODE)
High Level MODE/SYNC Input Voltage 1.2 V
I-Grade (Note 2) 1.2 V
R
MODE/SYNC
MODE/SYNC Input Pull-Down Resistance 50 kΩ
V
FREQ
Nominal FREQ Pin Voltage 0.62 V
Low Dropout Regulator
V
INTVCC
INTV
CC
Regulator Output Voltage V
IN
= 7.5V 5.0 5.2 5.4 V
V
IN
= 7.5V, I-Grade (Note 2) 5.0 5.2 5.4 V
ΔV
INTVCC
INTV
CC
Regulator Line Regulation 7.5V V
IN
15V 8 25 mV
ΔV
IN1
ΔV
INTVCC
INTV
CC
Regulator Line Regulation 15V V
IN
30V 70 200 mV
ΔV
IN2
V
LDO(LOAD)
INTV
CC
Load Regulation 0 I
INTVCC
20mA, V
IN
= 7.5V 2 0.2 %
V
DROPOUT
INTV
CC
Regulator Dropout Voltage INTV
CC
Load = 20mA 280 mV
I
INTVCC
Bootstrap Mode INTV
CC
Supply RUN = 0V, SENSE = 5V 10 20 μA
Current in Shutdown
I-Grade (Note 2) 30 μA
GATE Driver
t
r
GATE Driver Output Rise Time C
L
= 3300pF (Note 7) 17 100 ns
t
f
GATE Driver Output Fall Time C
L
= 3300pF (Note 7) 8 100 ns
4
LTC1871-1
18711fa
TYPICAL PERFOR A CE CHARACTERISTICS
UW
FB Voltage vs Temp FB Voltage Line Regulation FB Pin Current vs Temperature
TEMPERATURE (°C)
–50
FB VOLTAGE (V)
1.23
1.24
150
1871 G01
1.22
1.21 050 100
–25 25 75 125
1.25
V
IN
(V)
0
1.229
FB VOLTAGE (V)
1.230
1.231
5101520
1871 G02
25 30 35
TEMPERATURE (°C)
–50
0
FB PIN CURRENT (nA)
10
20
30
40
60
–25 250 50 10075
1871 G03
125 150
50
Shutdown Mode IQ vs VIN Burst Mode IQ vs VIN
V
IN
(V)
0
0
SHUTDOWN MODE I
Q
(μA)
10
20
10 20 30 40
1871 G04
30
Shutdown Mode IQ vs Temperature
TEMPERATURE (°C)
–50
0
SHUTDOWN MODE I
Q
(μA)
5
10
15
20
25 0 25 50
1871 G05
75 100 125 150
V
IN
= 5V
VIN (V)
0
0
Burst Mode IQ (μA)
100
200
300
400
600
10 20
1871 G06
30 40
500
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC1871E-1 is guaranteed to meet performance specifications
from 0°C to 85°C junction temperature. Specifications over the –40°C to
85°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LTC1871I-1 is guaranteed over the full –40°C to 125°C operating junction
temperature range.
Note 3: T
J
is calculated from the ambient temperature T
A
and power
dissipation P
D
according to the following formula:
T
J
= T
A
+ (P
D
• 110°C/W)
Note 4: The dynamic input supply current is higher due to power MOSFET
gate charging (Q
G
• f
OSC
). See Applications Information.
Note 5: The LTC1871-1 is tested in a feedback loop which servos V
FB
to
the reference voltage with the I
TH
pin forced to the midpoint of its voltage
range (0.3V V
ITH
1.2V, midpoint = 0.75V).
Note 6: In a synchronized application, the internal slope compensation
gain is increased by 25%. Synchronizing to a significantly higher ratio will
reduce the effective amount of slope compensation, which could result in
subharmonic oscillation for duty cycles greater than 50%.
Note 7: Rise and fall times are measured at 10% and 90% levels.
ELECTRICAL CHARACTERISTICS
5
LTC1871-1
18711fa
TYPICAL PERFOR A CE CHARACTERISTICS
UW
RUN Thresholds vs VIN RT vs Frequency
Frequency vs Temperature SENSE Pin Current vs Temperature
Maximum Sense Threshold
vs Temperature
V
IN
(V)
0
1.2
RUN THRESHOLDS (V)
1.3
1.4
10 20 30 40
1871 G10
1.5
RUN Thresholds vs Temperature
TEMPERATURE (°C)
–50
RUN THRESHOLDS (V)
1.30
1.35
150
1871 G11
1.25
1.20 050 100
–25 25 75 125
1.40
FREQUENCY (kHz)
100
R
T
(kΩ)
300
1000
1871 G12
10
100
200 1000
900
800700600
500
400
0
TEMPERATURE (°C)
–50
275
GATE FREQUENCY (kHz)
280
290
295
300
325
310
050 75
1871 G13
285
315
320
305
–25 25 100 125 150
TEMPERATURE (°C)
–50
140
MAX SENSE THRESHOLD (mV)
145
150
155
160
25 0 25 50
1871 G14
75 100 125 150
TEMPERATURE (°C)
–50
25
SENSE PIN CURRENT (μA)
30
35
050 75
1871 G15
–25 25 100 125 150
GATE HIGH
VSENSE = 0V
Burst Mode IQ vs Temperature
Gate Drive Rise and Fall Time
vs CL
Dynamic IQ vs Frequency
TEMPERATURE (°C)
–50
0
Burst Mode IQ (μA)
200
500
050 75
1871 G07
100
400
300
–25 25 100 125 150
FREQUENCY (kHz)
0
0
IQ (mA)
2
6
8
10
800
18
1871 G08
4
400 1200
600
200 1000
12
14
16
CL = 3300pF
IQ(TOT) = 550μA + Qg • f
CL (pF)
0
0
TIME (ns)
10
20
30
40
60
2000 4000 6000 8000
1871 G09
10000 12000
50
RISE TIME
FALL TIME
6
LTC1871-1
18711fa
UU
U
PI FU CTIO S
RUN (Pin 1): The RUN pin provides the user with an
accurate means for sensing the input voltage and pro-
gramming the start-up threshold for the converter. The
falling RUN pin threshold is nominally 1.248V and the
comparator has 100mV of hysteresis for noise immunity.
When the RUN pin is below this input threshold, the IC is
shut down and the V
IN
supply current is kept to a low
value (typ 10μA). The Absolute Maximum Rating for the
voltage on this pin is 7V.
I
TH
(Pin 2): Error Amplifier Compensation Pin. The cur-
rent comparator input threshold increases with this
control voltage. Nominal voltage range for this pin is 0V
to 1.40V.
FB (Pin 3): Receives the feedback voltage from the
external resistor divider across the output. Nominal
voltage for this pin in regulation is 1.230V.
FREQ (Pin 4): A resistor from the FREQ pin to ground
programs the operating frequency of the chip. The nomi-
nal voltage at the FREQ pin is 0.6V.
MODE/SYNC (Pin 5): This input controls the operating
mode of the converter and allows for synchronizing the
operating frequency to an external clock. If the MODE/
SYNC pin is connected to ground, Burst Mode operation
is enabled. If the MODE/SYNC pin is connected to IN-
TV
CC
, or if an external logic-level synchronization signal
is applied to this input, Burst Mode operation is disabled
and the IC operates in a continuous mode.
GND (Pin 6): Ground Pin.
GATE (Pin 7): Gate Driver Output.
I
NTV
CC
(Pin 8): The Internal 5.20V Regulator Output. The
gate driver and control circuits are powered from this
voltage. Decouple this pin locally to the IC ground with a
minimum of 4.7μF low ESR tantalum or ceramic
capacitor.
V
IN
(Pin 9): Main Supply Pin. Must be closely decoupled
to ground.
SENSE (Pin 10): The Current Sense Input for the Control
Loop. Connect this pin to the drain of the power MOSFET
for V
DS
sensing and highest efficiency. Alternatively, the
SENSE pin may be connected to a resistor in the source
of the power MOSFET. Internal leading edge blanking is
provided for both sensing methods.
TYPICAL PERFOR A CE CHARACTERISTICS
UW
INTVCC Load Regulation
INTVCC Dropout Voltage
vs Current, Temperature
INTVCC Line Regulation
INTV
CC
LOAD (mA)
0
INTV
CC
VOLTAGE (V)
5.2
30 50 80
1871 G16
5.1
5.0
10 20 40 60 70
V
IN
= 7.5V
V
IN
(V)
0
5.1
INTV
CC
VOLTAGE (V)
5.2
5.3
10 20 30 40
1871 G17
5.4
51525 35
INTV
CC
LOAD (mA)
0
0
DROPOUT VOLTAGE (mV)
50
150
200
250
500
350
510
1871 G18
100
400
450
300
15 20
150°C
75°C
125°C
25°C
–50°C
0°C
7
LTC1871-1
18711fa
BLOCK DIAGRA
W
+
+
+
1.230V
85mV OV
50k
EA
UV
TO
START-UP
CONTROL
BURST
COMPARATOR
S
R
Q
LOGIC
PWM LATCH
CURRENT
COMPARATOR
0.175V
1.230V
5.2V
+
2.00V
1.230V
SLOPE
1.230V
ILOOP
FB
ITH
+
gm
3
MODE/SYNC
5
FREQ
4
2
INTVCC
8LDO
V-TO-I
OSCV-TO-I
SLOPE
COMPENSATION
BIAS AND
START-UP
CONTROL
VIN
BIAS VREF
IOSC
RLOOP
+
+
C1
SENSE
10
GND
1871 BD
6
GATE
INTVCC
GND
7
VIN
1.248V
9
RUN
C2
1
0.6V
8
LTC1871-1
18711fa
Main Control Loop
The LTC1871-1 is a constant frequency, current mode
controller for DC/DC boost, SEPIC and flyback converter
applications. The LTC1871-1 is distinguished from con-
ventional current mode controllers because the current
control loop can be closed by sensing the voltage drop
across the power MOSFET switch instead of across a
discrete sense resistor, as shown in Figure 2. This sensing
technique improves efficiency, increases power density,
and reduces the cost of the overall solution.
OPERATIO
U
to rise, which causes the current comparator C1 to trip at
a higher peak inductor current value. The average inductor
current will therefore rise until it equals the load current,
thereby maintaining output regulation.
The nominal operating frequency of the LTC1871-1 is
programmed using a resistor from the FREQ pin to ground
and can be controlled over a 50kHz to 1000kHz range. In
addition, the internal oscillator can be synchronized to an
external clock applied to the MODE/SYNC pin and can be
locked to a frequency between 100% and 130% of its
nominal value. When the MODE/SYNC pin is left open, it is
pulled low by an internal 50k resistor and Burst Mode
operation is enabled. If this pin is taken above 2V or an
external clock is applied, Burst Mode operation is disabled
and the IC operates in continuous mode. With no load (or
an extremely light load), the controller will skip pulses in
order to maintain regulation and prevent excessive output
ripple.
The RUN pin controls whether the IC is enabled or is in a
low current shutdown state. A micropower 1.248V refer-
ence and comparator C2 allow the user to program the
supply voltage at which the IC turns on and off (compara-
tor C2 has 100mV of hysteresis for noise immunity). With
the RUN pin below 1.248V, the chip is off and the input
supply current is typically only 10μA.
An overvoltage comparator OV senses when the FB pin
exceeds the reference voltage by 6.5% and provides a
reset pulse to the main RS latch. Because this RS latch is
reset-dominant, the power MOSFET is actively held off for
the duration of an output overvoltage condition.
The LTC1871-1 can be used either by sensing the voltage
drop across the power MOSFET or by connecting the
SENSE pin to a conventional shunt resistor in the source
of the power MOSFET, as shown in Figure 2. Sensing the
voltage across the power MOSFET maximizes converter
efficiency and minimizes the component count, but limits
the output voltage to the maximum rating for this pin
(36V). By connecting the SENSE pin to a resistor in the
source of the power MOSFET, the user is able to program
output voltages significantly greater than 36V.
COUT
VSW
VSW
2a. SENSE Pin Connection for
Maximum Efficiency (VSW < 36V)
VOUT
VIN
GND
LD
+
COUT
RS
1871 F02
2b. SENSE Pin Connection for Precise
Control of Peak Current or for VSW > 36V
VOUT
VIN
GND
LD
+
GATE
GND
VIN
SENSE
GATE
GND
VIN
SENSE
Figure 2. Using the SENSE Pin On the LTC1871-1
For circuit operation, please refer to the Block Diagram of
the IC and Figure 1. In normal operation, the power
MOSFET is turned on when the oscillator sets the PWM
latch and is turned off when the current comparator C1
resets the latch. The divided-down output voltage is com-
pared to an internal 1.230V reference by the error amplifier
EA, which outputs an error signal at the I
TH
pin. The voltage
on the I
TH
pin sets the current comparator C1 input
threshold. When the load current increases, a fall in the FB
voltage relative to the reference voltage causes the I
TH
pin
9
LTC1871-1
18711fa
OPERATIO
U
Programming the Operating Mode
For applications where maximizing the efficiency at very
light loads (e.g., <100μA) is a high priority, the current in
the output divider could be decreased to a few micro-
amps and Burst Mode operation should be applied (i.e.,
the MODE/SYNC pin should be connected to ground). In
applications where fixed frequency operation is more
critical than low current efficiency, or where the lowest
output ripple is desired, pulse-skip mode operation should
be used and the MODE/SYNC pin should be connected to
the INTV
CC
pin. This allows discontinuous conduction
mode (DCM) operation down to near the limit defined by
the chip’s minimum on-time (about 175ns). Below this
output current level, the converter will begin to skip
cycles in order to maintain output regulation. Figures 3
and 4 show the light load switching waveforms for Burst
Mode and pulse-skip mode operation for the converter in
Figure 1.
Burst Mode Operation
Burst Mode operation is selected by leaving the MODE/
SYNC pin unconnected or by connecting it to ground. In
normal operation, the range on the I
TH
pin corresponding
to no load to full load is 0.30V to 1.2V. In Burst Mode
operation, if the error amplifier EA drives the I
TH
voltage
below 0.525V, the buffered I
TH
input to the current com-
parator C1 will be clamped at 0.525V (which corresponds
to 25% of maximum load current). The inductor current
peak is then held at approximately 30mV divided by the
power MOSFET R
DS(ON)
. If the I
TH
pin drops below 0.175V,
the Burst Mode comparator B1 will turn off the power
MOSFET and scale back the quiescent current of the IC to
250μA (sleep mode). In this condition, the load current will
be supplied by the output capacitor until the I
TH
voltage
rises above the 50mV hysteresis of the burst comparator.
At light loads, short bursts of switching (where the aver-
age inductor current is 20% of its maximum value) fol-
lowed by long periods of sleep will be observed, thereby
greatly improving converter efficiency. Oscilloscope wave-
forms illustrating Burst Mode operation are shown in
Figure 3.
Pulse-Skip Mode Operation
With the MODE/SYNC pin tied to a DC voltage above 2V,
Burst Mode operation is disabled. The internal, 0.525V
buffered I
TH
burst clamp is removed, allowing the I
TH
pin
to directly control the current comparator from no load to
full load. With no load, the I
TH
pin is driven below 0.175V,
the power MOSFET is turned off and sleep mode is
invoked. Oscilloscope waveforms illustrating this mode of
operation are shown in Figure 4.
When an external clock signal drives the MODE/SYNC pin
at a rate faster than the chip’s internal oscillator, the
oscillator will synchronize to it. In this synchronized mode,
Burst Mode operation is disabled. The constant frequency
associated with synchronized operation provides a more
controlled noise spectrum from the converter, at the
expense of overall system efficiency of light loads.
10μs/DIV 1871 F03
Figure 3. LTC1871-1 Burst Mode Operation
(MODE/SYNC = 0V) at Low Output Current
Figure 4. LTC1871-1 Low Output Current Operation with
Burst Mode Operation Disabled (MODE/SYNC = INTVCC)
V
OUT
50mV/DIV
I
L
5A/DIV
V
IN
= 3.3V
V
OUT
= 5V
I
OUT
= 500mA
MODE/SYNC = 0V
(Burst Mode OPERATION)
V
OUT
50mV/DIV
I
L
5A/DIV
V
IN
= 3.3V
V
OUT
= 5V
I
OUT
= 500mA
MODE/SYNC = INTV
CC
(PULSE-SKIP MODE)
2μs/DIV 1871 F04
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When the oscillator’s internal logic circuitry detects a
synchronizing signal on the MODE/SYNC pin, the internal
oscillator ramp is terminated early and the slope compen-
sation is increased by approximately 30%. As a result, in
applications requiring synchronization, it is recommended
that the nominal operating frequency of the IC be pro-
grammed to be about 75% of the external clock frequency.
Attempting to synchronize to too high an external fre-
quency (above 1.3f
O
) can result in inadequate slope com-
pensation and possible subharmonic oscillation (or jitter).
The external clock signal must exceed 2V for at least 25ns,
and should have a maximum duty cycle of 80%, as shown
in Figure 5. The MOSFET turn on will synchronize to the
rising edge of the external clock signal.
pin is used to charge and discharge an internal oscillator
capacitor. A graph for selecting the value of R
T
for a given
operating frequency is shown in Figure 6.
Figure 6. Timing Resistor (RT) Value
Figure 5. MODE/SYNC Clock Input and Switching
Waveforms for Synchronized Operation
1871 F05
2V TO 7V
MODE/
SYNC
GATE
I
L
t
MIN
= 25ns
0.8T
D = 40%
T T = 1/f
O
FREQUENCY (kHz)
100
RT (kΩ)
300
1000
1871 F06
10
100
200 1000
900
800700600
500
400
0
Programming the Operating Frequency
The choice of operating frequency and inductor value is a
tradeoff between efficiency and component size. Low
frequency operation improves efficiency by reducing
MOSFET and diode switching losses. However, lower
frequency operation requires more inductance for a given
amount of load current.
The LTC1871-1 uses a constant frequency architecture
that can be programmed over a 50kHz to 1000kHz range
with a single external resistor from the FREQ pin to
ground, as shown in Figure 1. The nominal voltage on the
FREQ pin is 0.6V, and the current that flows into the FREQ
INTV
CC
Regulator Bypassing and Operation
An internal, P-channel low dropout voltage regulator pro-
duces the 5.2V supply which powers the gate driver and
logic circuitry within the LTC1871-1, as shown in Figure 7.
The INTV
CC
regulator can supply up to 50mA and must be
bypassed to ground immediately adjacent to the IC pins
with a minimum of 4.7μF tantalum or ceramic capacitor.
Good bypassing is necessary to supply the high transient
currents required by the MOSFET gate driver.
For input voltages that don’t exceed 7V (the absolute
maximum rating for this pin), the internal low dropout
regulator in the LTC1871-1 is redundant and the INTV
CC
pin can be shorted directly to the V
IN
pin. With the INTV
CC
pin shorted to V
IN
, however, the divider that programs the
regulated INTV
CC
voltage will draw 10μA of current from
the input supply, even in shutdown mode. For applications
that require the lowest shutdown mode input supply
current, do not connect the INTV
CC
pin to V
IN
. Regardless
of whether the INTV
CC
pin is shorted to V
IN
or not, it is
always necessary to have the driver circuitry bypassed
with a 4.7μF tantalum or low ESR ceramic capacitor to
ground immediately adjacent to the INTV
CC
and GND
pins.
In an actual application, most of the IC supply current is
used to drive the gate capacitance of the power MOSFET.
11
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As a result, high input voltage applications in which a large
power MOSFET is being driven at high frequencies can
cause the LTC1871-1 to exceed its maximum junction
temperature rating. The junction temperature can be
estimated using the following equations:
I
Q(TOT)
I
Q
+ f • Q
G
P
IC
= V
IN
• (I
Q
+ f • Q
G
)
T
J
= T
A
+ P
IC
• R
TH(JA)
The total quiescent current I
Q(TOT)
consists of the static
supply current (I
Q
) and the current required to charge and
discharge the gate of the power MOSFET. The 10-pin
MSOP package has a thermal resistance of R
TH(JA)
=
120°C/W.
As an example, consider a power supply with V
IN
= 5V and
V
O
= 12V at I
O
= 1A. The switching frequency is 500kHz,
and the maximum ambient temperature is 70°C. The
power MOSFET chosen is the IRF7805, which has a
maximum R
DS(ON)
of 11mΩ (at room temperature) and a
maximum total gate charge of 37nC (the temperature
coefficient of the gate charge is low).
I
Q(TOT)
= 600μA + 37nC • 500kHz = 19.1mA
P
IC
= 5V • 19.1mA = 95mW
T
J
= 70°C + 120°C/W • 95mW = 81.4°C
This demonstrates how significant the gate charge current
can be when compared to the static quiescent current in
the IC.
To prevent the maximum junction temperature from being
exceeded, the input supply current must be checked when
operating in a continuous mode at high V
IN
. A tradeoff
between the operating frequency and the size of the power
MOSFET may need to be made in order to maintain a
reliable IC junction temperature. Prior to lowering the
operating frequency, however, be sure to check with
power MOSFET manufacturers for their latest-and-great-
est low Q
G
, low R
DS(ON)
devices. Power MOSFET manu-
facturing technologies are continually improving, with
newer and better performance devices being introduced
almost yearly.
Output Voltage Programming
The output voltage is set by a resistor divider according to
the following formula:
VV
R
R
O=+
1 230 1 2
1
.•
The external resistor divider is connected to the output as
shown in Figure 1, allowing remote voltage sensing. The
resistors R1 and R2 are typically chosen so that the error
Figure 7. Bypassing the LDO Regulator and Gate Driver Supply
+
+
1.230V
R2 R1
P-CH
5.2V
DRIVER GATE
C
VCC
4.7μF
C
IN
INPUT
SUPPLY
2.5V TO 30V
GND
PLACE AS CLOSE AS
POSSIBLE TO DEVICE PINS
M1
1871 F07
INTV
CC
V
IN
GND
LOGIC
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caused by the current flowing into the FB pin during
normal operation is less than 1% (this translates to a
maximum value of R1 of about 250k).
Programming Turn-On and Turn-Off Thresholds
with the RUN Pin
The LTC1871-1 contains an independent, micropower
voltage reference and comparator detection circuit that
remains active even when the device is shut down, as
shown in Figure 8. This allows users to accurately program
an input voltage at which the converter will turn on and off.
The falling threshold voltage on the RUN pin is equal to the
internal reference voltage of 1.248V. The comparator has
100mV of hysteresis to increase noise immunity.
The turn-on and turn-off input voltage thresholds are
programmed using a resistor divider according to the
following formulas:
VV
R
R
VV
IN OFF
IN ON
()
()
.•
.•
=+
=
1 248 1 2
1
1 348 11 2
1
+
R
R
The resistor R1 is typically chosen to be less than 1M.
For applications where the RUN pin is only to be used as
a logic input, the user should be aware of the 7V
Absolute Maximum Rating for this pin! The RUN pin can
be connected to the input voltage through an external 1M
resistor, as shown in Figure 8c, for “always on” operation.
+
RUN
COMPARATOR
VIN
RUN
R2
R1
INPUT
SUPPLY OPTIONAL
FILTER
CAPACITOR
+
GND
1871 F8a
BIAS AND
START-UP
CONTROL
1.248V
μPOWER
REFERENCE
6V
Figure 8b. On/Off Control Using External Logic Figure 8c. External Pull-Up Resistor On
RUN Pin for “Always On” Operation
Figure 8a. Programming the Turn-On and Turn-Off Thresholds Using the RUN Pin
+
RUN
COMPARATOR
1.248V
1871 F08b
RUN
6V
EXTERNAL
LOGIC CONTROL
+
RUN
COMPARATOR
V
IN
RUN
R2
1M
INPUT
SUPPLY
+
GND 1.248V
1871 F08c
6V
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LTC1871-1
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Application Circuits
A basic LTC1871-1 application circuit is shown in
Figure 1. External component selection is driven by the
characteristics of the load and the input supply. The first
topology to be analyzed will be the boost converter,
followed by SEPIC (single ended primary inductance
converter).
Boost Converter: Duty Cycle Considerations
For a boost converter operating in a continuous conduc-
tion mode (CCM), the duty cycle of the main switch is:
DVVV
VV
ODIN
OD
=+
+
where V
D
is the forward voltage of the boost diode. For
converters where the input voltage is close to the output
voltage, the duty cycle is low and for converters that
develop a high output voltage from a low voltage input
supply, the duty cycle is high. The maximum output
voltage for a boost converter operating in CCM is:
VV
DV
OMAX IN MIN
MAX D() ()
=
()
1
The maximum duty cycle capability of the LTC1871-1 is
typically 92%. This allows the user to obtain high output
voltages from low input supply voltages.
Boost Converter: The Peak and Average Input Currents
The control circuit in the LTC1871-1 is measuring the
input current (either by using the R
DS(ON)
of the power
MOSFET or by using a sense resistor in the MOSFET
source), so the output current needs to be reflected back
to the input in order to dimension the power MOSFET
properly. Based on the fact that, ideally, the output power
is equal to the input power, the maximum average input
current is:
II
D
The peak input current is
II
D
IN MAX OMAX
MAX
IN PEAK O MAX
MAX
() ()
() ()
:
=
=+
1
121
χ
The maximum duty cycle, D
MAX
, should be calculated at
minimum V
IN
.
Boost Converter: Ripple Current ΔI
L
and the ‘χ’ Factor
The constant ‘χ’ in the equation above represents the
percentage peak-to-peak ripple current in the inductor,
relative to its maximum value. For example, if 30% ripple
current is chosen, then χ = 0.30, and the peak current is
15% greater than the average.
For a current mode boost regulator operating in CCM,
slope compensation must be added for duty cycles above
50% in order to avoid subharmonic oscillation. For the
LTC1871-1, this ramp compensation is internal. Having an
internally fixed ramp compensation waveform, however,
does place some constraints on the value of the inductor
and the operating frequency. If too large an inductor is
used, the resulting current ramp (ΔI
L
) will be small relative
to the internal ramp compensation (at duty cycles above
50%), and the converter operation will approach voltage
mode (ramp compensation reduces the gain of the current
loop). If too small an inductor is used, but the converter is
still operating in CCM (near critical conduction mode), the
internal ramp compensation may be inadequate to prevent
subharmonic oscillation. To ensure good current mode
gain and avoid subharmonic oscillation, it is recom-
mended that the ripple current in the inductor fall in the
range of 20% to 40% of the maximum average current. For
example, if the maximum average input current is 1A,
choose a ΔI
L
between 0.2A and 0.4A, and a value ‘χ
between 0.2 and 0.4.
Boost Converter: Inductor Selection
Given an operating input voltage range, and having chosen
the operating frequency and ripple current in the inductor,
the inductor value can be determined using the following
equation:
LV
IfD
where
II
D
IN MIN
LMAX
LOMAX
MAX
=Δ
Δ=
()
()
:
χ1
14
LTC1871-1
18711fa
Remember that boost converters are not short-circuit
protected. Under a shorted output condition, the inductor
current is limited only by the input supply capability. For
applications requiring a step-up converter that is short-
circuit protected, please refer to the applications section
covering SEPIC converters.
The minimum required saturation current of the inductor
can be expressed as a function of the duty cycle and the
load current, as follows:
II
D
L SAT OMAX
MAX
() ()
+
121
χ
The saturation current rating for the inductor should be
checked at the minimum input voltage (which results in
the highest inductor current) and maximum output
current.
Boost Converter: Operating in Discontinuous Mode
Discontinuous mode operation occurs when the load
current is low enough to allow the inductor current to run
out during the off-time of the switch, as shown in Figure 9.
Once the inductor current is near zero, the switch and
diode capacitances resonate with the inductance to form
damped ringing at 1MHz to 10MHz. If the off-time is long
enough, the drain voltage will settle to the input voltage.
Depending on the input voltage and the residual energy in
the inductor, this ringing can cause the drain of the power
MOSFET to go below ground where it is clamped by the
body diode. This ringing is not harmful to the IC and it has
not been shown to contribute significantly to EMI. Any
attempt to damp it with a snubber will degrade the efficiency.
Boost Converter: Inductor Core Selection
Once the value for L is known, the type of inductor must be
selected. High efficiency converters generally cannot af-
ford the core loss found in low cost powdered iron cores,
forcing the use of more expensive ferrite, molypermalloy
or Kool Mμ
®
cores. Actual core loss is independent of core
size for a fixed inductor value, but is very dependent on the
inductance selected. As inductance increases, core losses
go down. Unfortunately, increased inductance requires
more turns of wire and therefore, copper losses will
increase. Generally, there is a tradeoff between core losses
and copper losses that needs to be balanced.
Ferrite designs have very low core losses and are preferred
at high switching frequencies, so design goals can con-
centrate on copper losses and preventing saturation.
Ferrite core material saturates “hard,” meaning that the
inductance collapses rapidly when the peak design current
is exceeded. This results in an abrupt increase in inductor
ripple current and consequently, output voltage ripple. Do
not allow the core to saturate!
Molypermalloy (from Magnetics, Inc.) is a very good, low
cost core material for toroids, but is more expensive than
ferrite. A reasonable compromise from the same manu-
facturer is Kool Mμ.
Boost Converter: Power MOSFET Selection
The power MOSFET serves two purposes in the LTC1871-
1: it represents the main switching element in the power
path, and its R
DS(ON)
represents the current sensing ele-
ment for the control loop. Important parameters for the
power MOSFET include the drain-to-source breakdown
voltage (BV
DSS
), the threshold voltage (V
GS(TH)
), the on-
resistance (R
DS(ON)
) versus gate-to-source voltage, the
gate-to-source and gate-to-drain charges (Q
GS
and Q
GD
,
respectively), the maximum drain current (I
D(MAX)
) and
the MOSFET’s thermal resistances (R
TH(JC)
and R
TH(JA)
).
The gate drive voltage is set by the 5.2V INTV
CC
low drop
regulator. Consequently, logic-level threshold MOSFETs
should be used in most LTC1871-1 applications. If low
input voltage operation is expected (e.g., supplying power
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Figure 9. Discontinuous Mode Waveforms
MOSFET DRAIN
VOLTAGE
2V/DIV
INDUCTOR
CURRENT
2A/DIV
V
IN
= 3.3V
V
OUT
= 5V
I
OUT
= 200mA
2μs/DIV 1871 F09
15
LTC1871-1
18711fa
from a lithium-ion battery or a 3.3V logic supply), then
sublogic-level threshold MOSFETs should be used.
Pay close attention to the BV
DSS
specifications for the
MOSFETs relative to the maximum actual switch voltage in
the application. Many logic-level devices are limited to 30V
or less, and the switch node can ring during the turn-off of
the MOSFET due to layout parasitics. Check the switching
waveforms of the MOSFET directly across the drain and
source terminals using the actual PC board layout (not just
on a lab breadboard!) for excessive ringing.
During the switch on-time, the control circuit limits the
maximum voltage drop across the power MOSFET to
about 150mV (at low duty cycle). The peak inductor
current is therefore limited to 150mV/R
DS(ON)
. The rela-
tionship between the maximum load current, duty cycle
and the R
DS(ON)
of the power MOSFET is:
RV D
I
DS ON SENSE MAX MAX
O MAX T
() ( )
()
••
+
1
12
χρ
The VSENSE(MAX) term is typically 150mV at low duty
cycle, and is reduced to about 100mV at a duty cycle of
92% due to slope compensation, as shown in Figure 10.
The ρT term accounts for the temperature coefficient of
the RDS(ON) of the MOSFET, which is typically 0.4%/°C.
Figure 11 illustrates the variation of normalized RDS(ON)
over tempera
ture for a typical power MOSFET.
Another method of choosing which power MOSFET to use
is to check what the maximum output current is for a given
R
DS(ON)
, since MOSFET on-resistances are available in
discrete values.
IV D
R
O MAX SENSE MAX MAX
DS ON T
() ()
()
••
=
+
1
12
χρ
It is worth noting that the 1 – D
MAX
relationship between
I
O(MAX)
and R
DS(ON)
can cause boost converters with a
wide input range to experience a dramatic range of maxi-
mum input and output current. This should be taken into
consideration in applications where it is important to limit
the maximum current drawn from the input supply.
Calculating Power MOSFET Switching and Conduction
Losses and Junction Temperatures
In order to calculate the junction temperature of the power
MOSFET, the power dissipated by the device must be
known. This power dissipation is a function of the duty
cycle, the load current and the junction temperature itself
(due to the positive temperature coefficient of its RDS(ON)).
As a result, some iterative calculation is normally required
to determine a reasonably accurate value. Since the
con
troller is using the MOSFET as both a switching and a
sensing element, care should be taken to ensure that the
converter is capable of delivering the required load current
over all operating conditions (line voltage and tempera-
ture), and for the worst-case specifications for V
SENSE(MAX)
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DUTY CYCLE
0
MAXIMUM CURRENT SENSE VOLTAGE (mV)
100
150
0.8
1871 F10
50
00.2 0.4 0.5 1.0
200
Figure 10. Maximum SENSE Threshold Voltage vs Duty Cycle
JUNCTION TEMPERATURE (°C)
–50
ρT
NORMALIZED ON RESISTANCE
1.0
1.5
150
1871 F11
0.5
0050 100
2.0
Figure 11. Normalized RDS(ON) vs Temperature
16
LTC1871-1
18711fa
and the R
DS(ON)
of the MOSFET listed in the manufacturer’s
data sheet.
The power dissipated by the MOSFET in a boost converter is:
PI
DRD
k
FET
OMAX
MAX DS ON MAX T
=
+
()
()
••
1
2
ρ
••
••
.()
VI
DCf
O
OMAX
MAX RSS
185
1
()
The first term in the equation above represents the I
2
R
losses in the device, and the second term, the switching
losses. The constant, k = 1.7, is an empirical factor in-
versely related to the gate drive current and has the dimen-
sion of 1/current.
From a known power dissipated in the power MOSFET, its
junction temperature can be obtained using the following
formula:
T
J
= T
A
+ P
FET
• R
TH(JA)
The R
TH(JA)
to be used in this equation normally includes
the R
TH(JC)
for the device plus the thermal resistance from
the case to the ambient temperature (R
TH(CA)
). This value
of T
J
can then be compared to the original, assumed value
used in the iterative calculation process.
Boost Converter: Output Diode Selection
To maximize efficiency, a fast switching diode with low
forward drop and low reverse leakage is desired. The
output diode in a boost converter conducts current during
the switch off-time. The peak reverse voltage that the
diode must withstand is equal to the regulator output
voltage. The average forward current in normal operation
is equal to the output current, and the peak current is equal
to the peak inductor current.
II I
D
D PEAK L PEAK O MAX
MAX
()() ()
==+
121
χ
The power dissipated by the diode is:
P
D
= I
O(MAX)
• V
D
and the diode junction temperature is:
T
J
= T
A
+ P
D
• R
TH(JA)
The R
TH(JA)
to be used in this equation normally includes
the R
TH(JC)
for the device plus the thermal resistance from
the board to the ambient temperature in the enclosure.
Remember to keep the diode lead lengths short and to
observe proper switch-node layout (see Board Layout
Checklist) to avoid excessive ringing and increased
dissipation.
Boost Converter: Output Capacitor Selection
Contributions of ESR (equivalent series resistance), ESL
(equivalent series inductance) and the bulk capacitance
must be considered when choosing the correct compo-
nent for a given output ripple voltage. The effects of these
three parameters (ESR, ESL and bulk C) on the output
voltage ripple waveform are illustrated in Figure 12e for a
typical boost converter.
The choice of component(s) begins with the maximum
acceptable ripple voltage (expressed as a percentage of
the output voltage), and how this ripple should be divided
between the ESR step and the charging/discharging ΔV.
For the purpose of simplicity we will choose 2% for the
maximum output ripple, to be divided equally between
the ESR step and the charging/discharging ΔV. This
percentage ripple will change, depending on the require-
ments of the application, and the equations provided
below can easily be modified.
For a 1% contribution to the total ripple voltage, the ESR
of the output capacitor can be determined using the
following equation:
ESR V
I
COUT O
IN PEAK
001.•
()
where:
II
D
IN PEAK OMAX
MAX
() ()
=+
121
χ
For the bulk C component, which also contributes 1% to
the total ripple:
CI
Vf
OUT O MAX
O
()
.• 001
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LTC1871-1
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For many designs it is possible to choose a single capaci-
tor type that satisfies both the ESR and bulk C require-
ments for the design. In certain demanding applications,
however, the ripple voltage can be improved significantly
by connecting two or more types of capacitors in parallel.
For example, using a low ESR ceramic capacitor can
minimize the ESR step, while an electrolytic capacitor can
be used to supply the required bulk C.
Once the output capacitor ESR and bulk capacitance have
been determined, the overall ripple voltage waveform
should be verified on a dedicated PC board (see Board
Layout section for more information on component place-
ment). Lab breadboards generally suffer from excessive
series inductance (due to inter-component wiring), and
these parasitics can make the switching waveforms look
significantly worse than they would be on a properly
designed PC board.
The output capacitor in a boost regulator experiences high
RMS ripple currents, as shown in Figure 12. The RMS
output capacitor ripple current is:
II
VV
V
RMS COUT O MAX OINMIN
IN MIN
()() ()
()
Note that the ripple current ratings from capacitor manu-
facturers are often based on only 2000 hours of life. This
makes it advisable to further derate the capacitor or to
choose a capacitor rated at a higher temperature than
required. Several capacitors may also be placed in parallel
to meet size or height requirements in the design.
Manufacturers such as Nichicon, United Chemicon and
Sanyo should be considered for high performance through-
hole capacitors. The OS-CON semiconductor dielectric
capacitor available from Sanyo has the lowest product of
ESR and size of any aluminum electrolytic, at a somewhat
higher price.
In surface mount applications, multiple capacitors may
have to be placed in parallel in order to meet the ESR or
RMS current handling requirements of the application.
Aluminum electrolytic and dry tantalum capacitors are
both available in surface mount packages. In the case of
tantalum, it is critical that the capacitors have been surge
tested for use in switching power supplies. An excellent
choice is AVX TPS series of surface mount tantalum. Also,
ceramic capacitors are now available with extremely low
ESR, ESL and high ripple current ratings.
Boost Converter: Input Capacitor Selection
The input capacitor of a boost converter is less critical than
the output capacitor, due to the fact that the inductor is in
series with the input and the input current waveform is
continuous (see Figure 12b). The input voltage source im-
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VIN
LD
SW
12a. Circuit Diagram
12b. Inductor and Input Currents
COUT
VOUT
RL
IIN
IL
12c. Switch Current
ISW
tON
12d. Diode and Output Currents
12e. Output Voltage Ripple Waveform
IO
ID
VOUT
(AC)
tOFF
ΔVESR
RINGING DUE TO
TOTAL INDUCTANCE
(BOARD + CAP)
ΔVCOUT
Figure 12. Switching Waveforms for a Boost Converter
18
LTC1871-1
18711fa
pedance determines the size of the input capacitor, which
is typically in the range of 10μF to 100μF. A low ESR capaci-
tor is recommended, although it is not as critical as for the
output capacitor.
The RMS input capacitor ripple current for a boost con-
verter is:
IV
Lf D
RMS CIN IN MIN MAX() ()
.• =03
Please note that the input capacitor can see a very high
surge current when a battery is suddenly connected to the
input of the converter and solid tantalum capacitors can
fail catastrophically under these conditions. Be sure to
specify surge-tested capacitors!
Burst Mode Operation and Considerations
The choice of MOSFET R
DS(ON)
and inductor value also
determines the load current at which the LTC1871-1
enters Burst Mode operation. When bursting, the control-
ler clamps the peak inductor current to approximately:
ImV
R
BURST PEAK DS ON
() ()
=30
which represents about 20% of the maximum 150mV
SENSE pin voltage. The corresponding average current
depends upon the amount of ripple current. Lower induc-
tor values (higher ΔI
L
) will reduce the load current at which
Burst Mode operations begins, since it is the peak current
that is being clamped.
APPLICATIO S I FOR ATIO
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Table 1. Recommended Component Manufacturers
VENDOR COMPONENTS TELEPHONE WEB ADDRESS
AVX Capacitors (207) 282-5111 avxcorp.com
BH Electronics Inductors, Transformers (952) 894-9590 bhelectronics.com
Coilcraft Inductors (847) 639-6400 coilcraft.com
Coiltronics Inductors (407) 241-7876 coiltronics.com
Diodes, Inc Diodes (805) 446-4800 diodes.com
Fairchild MOSFETs (408) 822-2126 fairchildsemi.com
General Semiconductor Diodes (516) 847-3000 generalsemiconductor.com
International Rectifier MOSFETs, Diodes (310) 322-3331 irf.com
IRC Sense Resistors (361) 992-7900 irctt.com
Kemet Tantalum Capacitors (408) 986-0424 kemet.com
Magnetics Inc Toroid Cores (800) 245-3984 mag-inc.com
Microsemi Diodes (617) 926-0404 microsemi.com
Murata-Erie Inductors, Capacitors (770) 436-1300 murata.co.jp
Nichicon Capacitors (847) 843-7500 nichicon.com
On Semiconductor Diodes (602) 244-6600 onsemi.com
Panasonic Capacitors (714) 373-7334 panasonic.com
Sanyo Capacitors (619) 661-6835 sanyo.co.jp
Sumida Inductors (847) 956-0667 sumida.com
Taiyo Yuden Capacitors (408) 573-4150 t-yuden.com
TDK Capacitors, Inductors (562) 596-1212 component.tdk.com
Thermalloy Heat Sinks (972) 243-4321 aavidthermalloy.com
Tokin Capacitors (408) 432-8020 tokin.com
Toko Inductors (847) 699-3430 tokoam.com
United Chemicon Capacitors (847) 696-2000 chemi-com.com
Vishay/Dale Resistors (605) 665-9301 vishay.com
Vishay/Siliconix MOSFETs (800) 554-5565 vishay.com
Vishay/Sprague Capacitors (207) 324-4140 vishay.com
Zetex Small-Signal Discretes (631) 543-7100 zetex.com
19
LTC1871-1
18711fa
The output voltage ripple can increase during Burst Mode
operation if ΔI
L
is substantially less than I
BURST
. This can
occur if the input voltage is very low or if a very large
inductor is chosen. At high duty cycles, a skipped cycle
causes the inductor current to quickly decay to zero.
However, because ΔI
L
is small, it takes multiple cycles for
the current to ramp back up to I
BURST(PEAK)
. During this
inductor charging interval, the output capacitor must
supply the load current and a significant droop in the
output voltage can occur. Generally, it is a good idea to
choose a value of inductor ΔI
L
between 25% and 40% of
I
IN(MAX)
. The alternative is to either increase the value of
the output capacitor or disable Burst Mode operation
using the MODE/SYNC pin.
Burst Mode operation can be defeated by connecting the
MODE/SYNC pin to a high logic-level voltage (either with
a control input or by connecting this pin to INTV
CC
). In this
mode, the burst clamp is removed, and the chip can
operate at constant frequency from continuous conduc-
tion mode (CCM) at full load, down into deep discontinu-
ous conduction mode (DCM) at light load. Prior to skip-
ping pulses at very light load (i.e., <5% of full load), the
controller will operate with a minimum switch on-time in
DCM. Pulse skipping prevents a loss of control of the
output at very light loads and reduces output volt-
age ripple.
Efficiency Considerations: How Much Does V
DS
Sensing Help?
The efficiency of a switching regulator is equal to the
output power divided by the input power (×100%).
Percent efficiency can be expressed as:
% Efficiency = 100% – (L1 + L2 + L3 + …),
where L1, L2, etc. are the individual loss components as
a percentage of the input power. It is often useful to
analyze individual losses to determine what is limiting the
efficiency and which change would produce the most
improvement. Although all dissipative elements in the
circuit produce losses, four main sources usually account
for the majority of the losses in LTC1871-1 applica-
tion circuits:
1. The supply current into V
IN
. The V
IN
current is the sum
of the DC supply current I
Q
(given in the Electrical
Characteristics) and the MOSFET driver and control
currents. The DC supply current into the V
IN
pin is
typically about 550μA and represents a small power
loss (much less than 1%) that increases with V
IN
. The
driver current results from switching the gate capaci-
tance of the power MOSFET; this current is typically
much larger than the DC current. Each time the MOSFET
is switched on and then off, a packet of gate charge Q
G
is transferred from INTV
CC
to ground. The resulting
dQ/dt is a current that must be supplied to the INTV
CC
capacitor through the V
IN
pin by an external supply. If
the IC is operating in CCM:
I
Q(TOT)
I
Q
= f • Q
G
P
IC
= V
IN
• (I
Q
+ f • Q
G
)
2. Power MOSFET switching and conduction losses. The
technique of using the voltage drop across the power
MOSFET to close the current feedback loop was chosen
because of the increased efficiency that results from not
having a sense resistor. The losses in the power MOSFET
are equal to:
PI
DRD
k
FET
OMAX
MAX DS ON MAX T
=
+
()
()
••
1
2
ρ
••
••
.()
VI
DCf
O
OMAX
MAX RSS
185
1
The I
2
R power savings that result from not having a
discrete sense resistor can be calculated almost by
inspection.
PI
DRD
RSENSE
OMAX
MAX SENSE MAX()
()
••=
1
2
To understand the magnitude of the improvement with
this V
DS
sensing technique, consider the 3.3V input, 5V
output power supply shown in Figure 1. The maximum
load current is 7A (10A peak) and the duty cycle is 39%.
Assuming a ripple current of 40%, the peak inductor
current is 13.8A and the average is 11.5A. With a
maximum sense voltage of about 140mV, the sense
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20
LTC1871-1
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resistor value would be 10mΩ, and the power dissi-
pated in this resistor would be 514mW at maximum
output current. Assuming an efficiency of 90%, this
sense resistor power dissipation represents 1.3% of
the overall input power. In other words, for this appli-
cation, the use of V
DS
sensing would increase the
efficiency by approximately 1.3%.
For more details regarding the various terms in these
equations, please refer to the section Boost Converter:
Power MOSFET Selection.
3. The losses in the inductor are simply the DC input
current squared times the winding resistance. Express-
ing this loss as a function of the output current yields:
PI
DR
R WINDING
OMAX
MAX W()
()
=
1
2
4. Losses in the boost diode. The power dissipation in the
boost diode is:
P
DIODE
= I
O(MAX)
• V
D
The boost diode can be a major source of power loss in
a boost converter. For the 3.3V input, 5V output at 7A
example given above, a Schottky diode with a 0.4V
forward voltage would dissipate 2.8W, which repre-
sents 7% of the input power. Diode losses can become
significant at low output voltages where the forward
voltage is a significant percentage of the output voltage.
5. Other losses, including C
IN
and C
O
ESR dissipation and
inductor core losses, generally account for less than
2% of the total additional loss.
Checking Transient Response
The regulator loop response can be verified by looking at
the load transient response. Switching regulators gener-
ally take several cycles to respond to an instantaneous
step in resistive load current. When the load step occurs,
V
O
immediately shifts by an amount equal to (ΔI
LOAD
)(ESR),
and then C
O
begins to charge or discharge (depending on
the direction of the load step) as shown in Figure 13. The
regulator feedback loop acts on the resulting error amp
output signal to return V
O
to its steady-state value. During
this recovery time, V
O
can be monitored for overshoot or
ringing that would indicate a stability problem.
A second, more severe transient can occur when connect-
ing loads with large (>1μF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C
O
, causing a nearly instantaneous drop in V
O
. No
regulator can deliver enough current to prevent this prob-
lem if the load switch resistance is low and it is driven
quickly. The only solution is to limit the rise time of the
switch drive in order to limit the inrush current di/dt to the
load.
Boost Converter Design Example
The design example given here will be for the circuit shown
in Figure 1. The input voltage is 3.3V, and the output is 5V
at a maximum load current of 7A (10A peak).
1. The duty cycle is:
DVVV
VV
ODIN
OD
=+
+
=+
+=
–..
..%
50433
504 38 9
2. Pulse-skip operation is chosen so the MODE/SYNC pin
is shorted to INTV
CC
.
3. The operating frequency is chosen to be 300kHz to
reduce the size of the inductor. From Figure 5, the
resistor from the FREQ pin to ground is 80k.
4. An inductor ripple current of 40% of the maximum load
current is chosen, so the peak input current (which is
also the minimum saturation current) is:
II
D
IN PEAK
OMAX
MAX
()
()
.•
=+
=121 12 7
10
χ
.. .
39 13 8=A
APPLICATIO S I FOR ATIO
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I
OUT
2A/DIV
V
OUT
(AC)
100mV/DIV
Figure 13. Load Transient Response for a 3.3V Input,
5V Output Boost Converter Application, 0.7A to 7A Step
V
IN
= 3.3V
V
OUT
= 5V
MODE/SYNC = INTV
CC
(PULSE-SKIP MODE)
100μs/DIV 1871 F13
21
LTC1871-1
18711fa
The inductor ripple current is:
Δ== =II
DA
LO MAX
MAX
χ.•–. .
()
104 7
1039 46
And so the inductor value is:
LV
IfDV
A kHz H
IN MIN
LMAX
=Δ==μ
()
.
.• •. .
33
4 6 300 039 093
The component chosen is a 1μH inductor made by
Sumida (part number CEP125-H 1ROMH) which has a
saturation current of greater than 20A.
5. With the input voltage to the IC bootstrapped to the
output of the power supply (5V), a logic-level MOSFET
can be used. Because the duty cycle is 39%, the
maximum SENSE pin threshold voltage is reduced from
its low duty cycle typical value of 150mV to approxi-
mately 140mV. Assuming a MOSFET junction tempera-
ture of 125°C, the room temperature MOSFET R
DS(ON)
should be less than:
RV D
I
V
A
m
DS ON SENSE MAX MAX
O MAX T
() ( )
()
••
.• –.
.••.
.
+
=
+
=Ω
1
12
0 140 1039
104
2715
68
χρ
The MOSFET used was the Fairchild FDS7760A, which
has a maximum R
DS(ON)
of 8mΩ at 4.5V V
GS
, a BV
DSS
of greater than 30V, and a gate charge of 37nC at 5V
V
GS
.
6. The diode for this design must handle a maximum DC
output current of 10A and be rated for a minimum
reverse voltage of V
OUT
, or 5V. A 25A, 15V diode from
On Semiconductor (MBRB2515L) was chosen for its
high power dissipation capability.
7. The output capacitor usually consists of a high valued
bulk C connected in parallel with a lower valued, low
ESR ceramic. Based on a maximum output ripple
voltage of 1%, or 50mV, the bulk C needs to be great-
er than:
CI
Vf
A
V kHz F
OUT OUT MAX
OUT
=
=μ
()
.•
.•
001
7
0 01 5 300 466
The RMS ripple current rating for this capacitor needs
to exceed:
II
VV
V
AVV
VA
RMS COUT O MAX OINMIN
IN MIN
()() ()
()
–.
.
=
=7533
33 5
To satisfy this high RMS current demand, four 150μF
Panasonic capacitors (EEFUEOJ151R) are required.
In parallel with these bulk capacitors, two 22μF, low
ESR (X5R) Taiyo Yuden ceramic capacitors
(JMK325BJ226MM) are added for HF noise reduction.
Check the output ripple with a single oscilloscope
probe connected directly across the output capacitor
terminals, where the HF switching currents flow.
8. The choice of an input capacitor for a boost converter
depends on the impedance of the source supply and the
amount of input ripple the converter will safely tolerate.
For this particular design and lab setup a 100μF Sanyo
Poscap (6TPC 100M), in parallel with two 22μF Taiyo
Yuden ceramic capacitors (JMK325BJ226MM) is re-
quired (the input and return lead lengths are kept to a
few inches, but the peak input current is close to 20A!).
As with the output node, check the input ripple with a
single oscilloscope probe connected across the input
capacitor terminals.
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22
LTC1871-1
18711fa
APPLICATIO S I FOR ATIO
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PC Board Layout Checklist
1. In order to minimize switching noise and improve
output load regulation, the GND pin of the LTC1871-1
should be connected directly to 1) the negative termi-
nal of the INTVCC decoupling capacitor, 2) the negative
terminal of the output decoupling capacitors, 3) the
source of the power MOSFET or the bottom terminal of
the sense resistor, 4) the negative terminal of the input
capacitor and 5) at least one via to the ground plane
immediately adjacent to Pin 6. The ground trace on the
top layer of the PC board should be as wide and short as
possible to minimize series resistance and inductance.
LTC1871-1
M1
V
IN
1871 F14
V
OUT
SWITCH NODE IS ALSO
THE HEAT SPREADER
FOR L1, M1, D1
L1
R
T
R
C
C
C
R3
J1
C
IN
C
OUT
C
VCC
R1
R2
PSEUDO-KELVIN
SIGNAL GROUND
CONNECTION
TRUE REMOTE
OUTPUT SENSING
VIAS TO GROUND
PLANE
R4
PIN 1
C
OUT
BULK C LOW ESR CERAMIC
JUMPER
D1
Figure 14. LTC1871-1 Boost Converter Suggested Layout
RUN
I
TH
FB
FREQ
MODE/
SYNC
SENSE
V
IN
INTV
CC
GATE
GND
LTC1871-1
+
R4
J1
10
9
8
7
6
1
2
3
4
5
C
VCC
PSEUDO-KELVIN
GROUND CONNECTION
C
IN
M1
D1
L1
V
IN
GND
1871 F15
V
OUT
SWITCH
NODE
C
OUT
R
C
R1
R
T
BOLD LINES INDICATE HIGH CURRENT PATHS
R2
C
C
R3
+
Figure 15. LTC1871-1 Boost Converter Layout Diagram
23
LTC1871-1
18711fa
2. Beware of ground loops in multiple layer PC boards. Try
to maintain one central ground node on the board and
use the input capacitor to avoid excess input ripple for
high output current power supplies. If the ground plane
is to be used for high DC currents, choose a path away
from the small-signal components.
3. Place the C
VCC
capacitor immediately adjacent to the
INTV
CC
and GND pins on the IC package. This capacitor
carries high di/dt MOSFET gate drive currents. A low
ESR and ESL 4.7μF ceramic capacitor works well here.
4. The high di/dt loop from the bottom terminal of the
output capacitor, through the power MOSFET, through
the boost diode and back through the output capacitors
should be kept as tight as possible to reduce inductive
ringing. Excess inductance can cause increased stress
on the power MOSFET and increase HF noise on the
output. If low ESR ceramic capacitors are used on the
output to reduce output noise, place these capacitors
close to the boost diode in order to keep the series
inductance to a minimum.
5. Check the stress on the power MOSFET by measuring
its drain-to-source voltage directly across the device
terminals (reference the ground of a single scope probe
directly to the source pad on the PC board). Beware of
inductive ringing which can exceed the maximum speci-
fied voltage rating of the MOSFET. If this ringing cannot
be avoided and exceeds the maximum rating of the
device, either choose a higher voltage device or specify
an avalanche-rated power MOSFET. Not all MOSFETs
are created equal (some are more equal than others).
6. Place the small-signal components away from high
frequency switching nodes. In the layout shown in
Figure 14, all of the small-signal components have been
placed on one side of the IC and all of the power
components have been placed on the other. This also
allows the use of a pseudo-Kelvin connection for the
signal ground, where high di/dt gate driver currents
flow out of the IC ground pin in one direction (to the
bottom plate of the INTV
CC
decoupling capacitor) and
small-signal currents flow in the other direction.
7. If a sense resistor is used in the source of the power
MOSFET, minimize the capacitance between the SENSE
pin trace and any high frequency switching nodes. The
LTC1871-1 contains an internal leading edge blanking
time of approximately 180ns, which should be ad-
equate for most applications.
8. For optimum load regulation and true remote sensing,
the top of the output resistor divider should connect
independently to the top of the output capacitor (Kelvin
connection), staying away from any high dV/dt traces.
Place the divider resistors near the LTC1871-1 in order
to keep the high impedance FB node short.
9. For applications with multiple switching power con-
verters connected to the same input supply, make sure
that the input filter capacitor for the LTC1871-1 is not
shared with other converters. AC input current from
another converter could cause substantial input voltage
ripple, and this could interfere with the operation of the
LTC1871-1. A few inches of PC trace or wire (L
100nH) between the C
IN
of the LTC1871-1 and the
actual source V
IN
should be sufficient to prevent current
sharing problems.
APPLICATIO S I FOR ATIO
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Figures 16. SEPIC Topology and Current Flow
+
+
+
SW L2 COUT RL
VOUT
VIN
C1 D1
L1
16a. SEPIC Topology
+
+
+
RL
VOUT
VIN
D1
16c. Current Flow During Switch Off-Time
+
+
+
RL
VOUT
VIN
VIN
VIN
16b. Current Flow During Switch On-Time
24
LTC1871-1
18711fa
SEPIC Converter Applications
The LTC1871-1 is also well suited to SEPIC (single-ended
primary inductance converter) converter applications. The
SEPIC converter shown in Figure 16 uses two inductors.
The advantage of the SEPIC converter is the input voltage
may be higher or lower than the output voltage, and the
output is short-circuit protected.
The first inductor, L1, together with the main switch,
resembles a boost converter. The second inductor, L2,
together with the output diode D1, resembles a flyback or
buck-boost converter. The two inductors L1 and L2 can be
independent but can also be wound on the same core since
identical voltages are applied to L1 and L2 throughout the
switching cycle. By making L1 = L2 and winding them on
the same core the input ripple is reduced along with cost
and size. All of the SEPIC applications information that
follows assumes L1 = L2 = L.
SEPIC Converter: Duty Cycle Considerations
For a SEPIC converter operating in a continuous conduc-
tion mode (CCM), the duty cycle of the main switch is:
DVV
VVV
OD
IN O D
=+
++
where V
D
is the forward voltage of the diode. For convert-
ers where the input voltage is close to the output voltage
the duty cycle is near 50%.
The maximum output voltage for a SEPIC converter is:
VVV
D
DVD
O MAX IN D MAX
MAX DMAX
()
=+
()
1
1
1
The maximum duty cycle of the LTC1871-1 is typically
92%.
SEPIC Converter: The Peak and Average
Input Currents
The control circuit in the LTC1871-1 is measuring the
input current (either using the R
DS(ON)
of the power
MOSFET or by means of a sense resistor in the MOSFET
source), so the output current needs to be reflected back
to the input in order to dimension the power MOSFET
properly. Based on the fact that, ideally, the output power
is equal to the input power, the maximum input current for
a SEPIC converter is:
II D
D
The peak input current is
II
D
D
IN MAX O MAX MAX
MAX
IN PEAK O MAX MAX
MAX
() ()
() ()
:
••
=
=+
1
121
χ
The maximum duty cycle, D
MAX
, should be calculated at
minimum V
IN
.
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Figures 17. SEPIC Converter Switching Waveforms
17a. Input Inductor Current
IIN
IL1 SW
ON
SW
OFF
17b. Output Inductor Current
IO
IL2
17c. DC Coupling Capacitor Current
IO
IIN
IC1
17e. Output Ripple Voltage
VOUT
(AC)
ΔVESR
RINGING DUE TO
TOTAL INDUCTANCE
(BOARD + CAP)
ΔVCOUT
17d. Diode Current
IO
ID1
25
LTC1871-1
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The constant ‘χ’ represents the fraction of ripple current in
the inductor relative to its maximum value. For example, if
30% ripple current is chosen, then χ = 0.30 and the peak
current is 15% greater than the average.
It is worth noting here that SEPIC converters that operate
at high duty cycles (i.e., that develop a high output voltage
from a low input voltage) can have very high input cur-
rents, relative to the output current. Be sure to check that
the maximum load current will not overload the input
supply.
SEPIC Converter: Inductor Selection
For most SEPIC applications the equal inductor values will
fall in the range of 10μH to 100μH. Higher values will
reduce the input ripple voltage and reduce the core loss.
Lower inductor values are chosen to reduce physical size
and improve transient response.
Like the boost converter, the input current of the SEPIC
converter is calculated at full load current and minimum
input voltage. The peak inductor current can be signifi-
cantly higher than the output current, especially with
smaller inductors and lighter loads. The following formu-
las assume CCM operation and calculate the maximum
peak inductor currents at minimum V
IN
:
II
VV
V
II
VV
V
L PEAK O MAX OD
IN MIN
L PEAK O MAX IN MIN D
IN MIN
1
2
12
12
() ()
()
() () ()
()
••
••
=+
+
=+
+
χ
χ
The ripple current in the inductor is typically 20% to 40%
(i.e., a range of ‘χ’ from 0.20 to 0.40) of the maximum
average input current occurring at V
IN(MIN)
and I
O(MAX)
and ΔI
L1
= ΔI
L2
. Expressing this ripple current as a
function of the output current results in the following
equations for calculating the inductor value:
LV
IfD
IN MIN
LMAX
=Δ
()
where
II D
D
L O MAX MAX
MAX
:
••
()
Δ=χ1
By making L1 = L2 and winding them on the same core, the
value of inductance in the equation above is replace by 2L
due to mutual inductance. Doing this maintains the same
ripple current and energy storage in the inductors. For
example, a Coiltronix CTX10-4 is a 10μH inductor with two
windings. With the windings in parallel, 10μH inductance
is obtained with a current rating of 4A (the number of turns
hasn’t changed, but the wire diameter has doubled).
Splitting the two windings creates two 10μH inductors
with a current rating of 2A each. Therefore, substituting 2L
yields the following equation for coupled inductors:
LL V
If
D
IN MIN
LMAX
12
2
== Δ
()
••
Specify the maximum inductor current to safely handle
I
L(PK)
specified in the equation above.
The saturation
current rating for the inductor should be checked at the
minimum input voltage (which results in the highest
inductor current) and maximum output current.
SEPIC Converter: Power MOSFET Selection
The power MOSFET serves two purposes in the LTC1871-
1: it represents the main switching element in the power
path, and its R
DS(ON)
represents the current sensing
element for the control loop. Important parameters for the
power MOSFET include the drain-to-source breakdown
voltage (BV
DSS
), the threshold voltage (V
GS(TH)
), the on-
resistance (R
DS(ON)
) versus gate-to-source voltage, the
gate-to-source and gate-to-drain charges (Q
GS
and Q
GD
,
respectively), the maximum drain current (I
D(MAX)
) and
the MOSFET’s thermal resistances (R
TH(JC)
and R
TH(JA)
).
The gate drive voltage is set by the 5.2V INTV
CC
low
dropout regulator. Consequently, logic-level threshold
MOSFETs should be used in most LTC1871-1 applica-
tions. If low input voltage operation is expected (e.g.,
supplying power from a lithium-ion battery), then sublogic-
level threshold MOSFETs should be used.
The maximum voltage that the MOSFET switch must
sustain during the off-time in a SEPIC converter is equal to
the sum of the input and output voltages (V
O
+ V
IN
). As a
result, careful attention must be paid to the BV
DSS
speci-
fications for the MOSFETs relative to the maximum actual
switch voltage in the application. Many logic-level devices
26
LTC1871-1
18711fa
are limited to 30V or less. Check the switching waveforms
directly across the drain and source terminals of the power
MOSFET to ensure the V
DS
remains below the maximum
rating for the device.
During the MOSFET’s on-time, the control circuit limits the
maximum voltage drop across the power MOSFET to
about 150mV (at low duty cycle). The peak inductor
current is therefore limited to 150mV/R
DS(ON)
. The rela-
tionship between the maximum load current, duty cycle
and the R
DS(ON)
of the power MOSFET is:
RV
I
DS ON
SENSE MAX
OMAX T
()
()
()
+
1
12
1
χρVVV
V
OD
IN MIN
+
+
()
1
The V
SENSE(MAX)
term is typically 150mV at low duty cycle
and is reduced to about 100mV at a duty cycle of 92% due
to slope compensation, as shown in Figure 8. The constant
χ’ in the denominator represents the ripple current in the
inductors relative to their maximum current. For example,
if 30% ripple current is chosen, then χ = 0.30. The ρ
T
term
accounts for the temperature coefficient of the R
DS(ON)
of
the MOSFET, which is typically 0.4%/°C. Figure 9 illus-
trates the variation of normalized R
DS(ON)
over tempera-
ture for a typical power MOSFET.
Another method of choosing which power MOSFET to use
is to check what the maximum output current is for a given
R
DS(ON)
since MOSFET on-resistances are available in
discrete values.
IV
R
OMAX
SENSE MAX
DS ON T
()
()
()
+
1
12
1
χρVVV
V
OD
IN MIN
+
+
()
1
Calculating Power MOSFET Switching and Conduction
Losses and Junction Temperatures
In order to calculate the junction temperature of the power
MOSFET, the power dissipated by the device must be
known. This power dissipation is a function of the duty
cycle, the load current and the junction temperature itself.
As a result, some iterative calculation is normally required
to determine a reasonably accurate value. Since the con-
troller is using the MOSFET as both a switching and a
sensing element, care should be taken to ensure that the
converter is capable of delivering the required load current
over all operating conditions (load, line and temperature)
and for the worst-case specifications for V
SENSE(MAX)
and
the R
DS(ON)
of the MOSFET listed in the manufacturer’s
data sheet.
The power dissipated by the MOSFET in a SEPIC converter is:
PI D
DRD
FET O MAX MAX
MAX DS ON MAX
=
() ()
••
1
2
••
()
.
()
ρT
IN MIN O O MAX MAX
MAX
kV V I D
D
++
()
185
1••Cf
RSS
The first term in the equation above represents the I
2
R
losses in the device and the second term, the switching
losses. The constant k = 1.7 is an empirical factor inversely
related to the gate drive current and has the dimension of
1/current.
From a known power dissipated in the power MOSFET, its
junction temperature can be obtained using the following
formula:
T
J
= T
A
+ P
FET
•R
TH(JA)
The R
TH(JA)
to be used in this equation normally includes
the R
TH(JC)
for the device plus the thermal resistance from
the board to the ambient temperature in the enclosure.
This value of T
J
can then be used to check the original
assumption for the junction temperature in the iterative
calculation process.
SEPIC Converter: Output Diode Selection
To maximize efficiency, a fast-switching diode with low
forward drop and low reverse leakage is desired. The
output diode in a SEPIC converter conducts current during
the switch off-time. The peak reverse voltage that the
diode must withstand is equal to V
IN(MAX)
+ V
O
. The
average forward current in normal operation is equal to the
output current, and the peak current is equal to:
II
VV
V
DPEAK OMAX OD
IN MIN
() () ()
••=+
++121
χ
The power dissipated by the diode is:
P
D
= I
O(MAX)
• V
D
APPLICATIO S I FOR ATIO
WUUU
27
LTC1871-1
18711fa
and the diode junction temperature is:
T
J
= T
A
+ P
D
• R
TH(JA)
The R
TH(JA)
to be used in this equation normally includes
the R
TH(JC)
for the device plus the thermal resistance from
the board to the ambient temperature in the enclosure.
SEPIC Converter: Output Capacitor Selection
Because of the improved performance of today’s electro-
lytic, tantalum and ceramic capacitors, engineers need to
consider the contributions of ESR (equivalent series resis-
tance), ESL (equivalent series inductance) and the bulk
capacitance when choosing the correct component for a
given output ripple voltage. The effects of these three
parameters (ESR, ESL, and bulk C) on the output voltage
ripple waveform are illustrated in Figure 17 for a typical
coupled-inductor SEPIC converter.
The choice of component(s) begins with the maximum
acceptable ripple voltage (expressed as a percentage of
the output voltage), and how this ripple should be divided
between the ESR step and the charging/discharging ΔV.
For the purpose of simplicity we will choose 2% for the
maximum output ripple, to be divided equally between the
ESR step and the charging/discharging ΔV. This percent-
age ripple will change, depending on the requirements of
the application, and the equations provided below can
easily be modified.
For a 1% contribution to the total ripple voltage, the ESR
of the output capacitor can be determined using the
following equation:
ESR V
I
COUT O
D PEAK
001.•
()
where:
II
VV
V
D PEAK O MAX OD
IN MIN
() () ()
••=+
++
121
χ
For the bulk C component, which also contributes 1% to
the total ripple:
CI
Vf
OUT O MAX
O
()
.• 001
For many designs it is possible to choose a single capaci-
tor type that satisfies both the ESR and bulk C require-
ments for the design. In certain demanding applications,
however, the ripple voltage can be improved significantly
by connecting two or more types of capacitors in parallel.
For example, using a low ESR ceramic capacitor can
minimize the ESR step, while an electrolytic or tantalum
capacitor can be used to supply the required bulk C.
Once the output capacitor ESR and bulk capacitance have
been determined, the overall ripple voltage waveform
should be verified on a dedicated PC board (see Board
Layout section for more information on component place-
ment). Lab breadboards generally suffer from excessive
series inductance (due to inter-component wiring), and
these parasitics can make the switching waveforms look
significantly worse than they would be on a properly
designed PC board.
The output capacitor in a SEPIC regulator experiences
high RMS ripple currents, as shown in Figure 17. The RMS
output capacitor ripple current is:
II V
V
RMS COUT O MAX O
IN MIN
()() ()
=
Note that the ripple current ratings from capacitor manu-
facturers are often based on only 2000 hours of life. This
makes it advisable to further derate the capacitor or to
choose a capacitor rated at a higher temperature than
required. Several capacitors may also be placed in parallel
to meet size or height requirements in the design.
Manufacturers such as Nichicon, United Chemicon and
Sanyo should be considered for high performance through-
hole capacitors. The OS-CON semiconductor dielectric
capacitor available from Sanyo has the lowest product of
ESR and size of any aluminum electrolytic, at a somewhat
higher price.
In surface mount applications, multiple capacitors may
have to be placed in parallel in order to meet the ESR or
RMS current handling requirements of the application.
Aluminum electrolytic and dry tantalum capacitors are
both available in surface mount packages. In the case of
tantalum, it is critical that the capacitors have been surge
tested for use in switching power supplies. An excellent
APPLICATIO S I FOR ATIO
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28
LTC1871-1
18711fa
choice is AVX TPS series of surface mount tantalum. Also,
ceramic capacitors are now available with extremely low
ESR, ESL and high ripple current ratings.
SEPIC Converter: Input Capacitor Selection
The input capacitor of a SEPIC converter is less critical
than the output capacitor due to the fact that an inductor
is in series with the input and the input current waveform
is triangular in shape. The input voltage source impedance
determines the size of the input capacitor which is typically
in the range of 10μF to 100μF. A low ESR capacitor is
recommended, although it is not as critical as for the
output capacitor.
The RMS input capacitor ripple current for a SEPIC con-
verter is:
II
RMS CIN L() =Δ
1
12
Please note that the input capacitor can see a very high
surge current when a battery is suddenly connected to the
input of the converter and solid tantalum capacitors can
fail catastrophically under these conditions. Be sure to
specify surge-tested capacitors!
SEPIC Converter: Selecting the DC Coupling Capacitor
The coupling capacitor C1 in Figure 16 sees nearly a
rectangular current waveform as shown in Figure 17.
During the switch off-time the current through C1 is I
O
(V
O
/
V
IN
) while approximately –I
O
flows during the on-time.
This current waveform creates a triangular ripple voltage
on C1:
Δ=++
VI
Cf
V
VVV
CPP OMAX O
IN O D
11
() ()
The maximum voltage on C1 is then:
VV
V
C MAX IN CPP
11
2
() ()
=+
Δ
which is typically close to V
IN(MAX)
. The ripple current
through C1 is:
II VV
V
RMS C O MAX OD
IN MIN
() ( ) ()
1
=+
The value chosen for the DC coupling capacitor normally
starts with the minimum value that will satisfy 1) the RMS
current requirement and 2) the peak voltage requirement
(typically close to V
IN
). Low ESR ceramic and tantalum
capacitors work well here.
SEPIC Converter Design Example
The design example given here will be for the circuit shown
in Figure 18. The input voltage is 5V to 15V and the output
is 12V at a maximum load current of 1.5A (2A peak).
1. The duty cycle range is:
DVV
VVV to
OD
IN O D
=+
++
=45 5 71 4.% .%
2. The operating mode chosen is pulse skipping, so the
MODE/SYNC pin is shorted to INTV
CC
.
3. The operating frequency is chosen to be 300kHz to
reduce the size of the inductors; the resistor from the
FREQ pin to ground is 80k.
4. An inductor ripple current of 40% is chosen, so the peak
input current (which is also the minimum saturation
current) is:
II
VV
V
A
L PEAK O MAX OD
IN MIN
1
12
104
215 12 0 5
545
() () ()
••
.•.• ..
=+
+
=+
+=
χ
The inductor ripple current is:
Δ=
==
II D
D
A
L O MAX MAX
MAX
χ••
.•.• .
–. .
()
1
04 15 0 714
1 0 714 15
APPLICATIO S I FOR ATIO
WUUU
29
LTC1871-1
18711fa
RUN
ITH
FB
FREQ
MODE/SYNC
SENSE
VIN
INTVCC
GATE
GND
1
2
3
4
5
10
9
8
7
6
LTC1871-1
RT
80.6k
1%
R1
12.1k
1%
R2
105k
1%
R3
1M
CVCC
4.7μF
X5R
CIN
47μF
M1
CIN, COUT1: KEMET T495X476K020AS
CDC, COUT2: TAIYO YUDEN TMK432BJ106MM
D1: INTERNATIONAL RECTIFIER 30BQ040
D1
L1*
L2*
RC
33k
CC1
6.8nF
CC2
47pF
COUT1
47μF
20V
×2
VIN
4.5V to 15V
VOUT
12V
1.5A
(2A PEAK)
GND
1871 F018a
+
COUT2
10μF
25V
X5R
×2
L1, L2: BH ELECTRONICS BH510-1007 (*COUPLED INDUCTORS)
M1: INTERNATIONAL RECTIFIER IRF7811W
CDC
10μF
25V
X5R
+
Figure 18a. 4.5V to 15V Input, 12V/2A Output SEPIC Converter
OUTPUT CURRENT (A)
50
EFFICIENCY (%)
55
60
90
85
80
75
70
65
95
0.001 0.1 1 10
1871 F18b
45
0.01
100
VIN = 4.5V
VIN = 15V
VIN = 12V
VO = 12V
MODE = INTVCC
Figure 18b. SEPIC Efficiency vs Output Current
APPLICATIO S I FOR ATIO
WUUU
And so the inductor value is:
LV
If
DkH
IN MIN
LMAX
=Δ==μ
()
••
•.• •.
2
5
2 1 5 300 0 714 4
T
he component chosen is a BH Electronics BH510-
1007, which has a saturation current of 8A.
5. With an minimum input voltage of 5V, only logic-level
power MOSFETs should be considered. Because the
maximum duty cycle is 71.4%, the maximum SENSE
pin threshold voltage is reduced from its low duty cycle
typical value of 150mV to approximately 120mV.
Assuming a MOSFET junction temperature of 125°C,
the room temperature MOSFET R
DS(ON)
should be less
than:
RV
IVV
V
m
DS ON SENSE MAX
OMAX TOD
IN MIN
() ()
()
()
.
..•...
+
+
+
=
+
=Ω
1
12
1
1
012
15
1
12 15
1
12 5
51
12 7
χρ
For a SEPIC converter, the switch BV
DSS
rating must be
greater than V
IN(MAX)
+ V
O
, or 27V. This comes close to
an IRF7811W, which is rated to 30V, and has a maxi-
mum room temperature R
DS(ON)
of 12mΩ at V
GS
= 4.5V.
30
LTC1871-1
18711fa
V
OUT
(AC)
200mV/DIV
I
OUT
0.5A/DIV
Figure 19. LTC1871-1 SEPIC Converter Load Step Response
V
IN
= 4.5V
V
OUT
= 12V
V
OUT
(AC)
200mV/DIV
I
OUT
0.5A/DIV
V
IN
= 15V
V
OUT
= 12V
50μs/DIV 1871 F19a 50μs/DIV 1871 F19b
APPLICATIO S I FOR ATIO
WUUU
6. The diode for this design must handle a maximum DC
output current of 2A and be rated for a minimum
reverse voltage of V
IN
+ V
OUT
, or 27V. A 3A, 40V diode
from International Rectifier (30BQ040) is chosen for its
small size, relatively low forward drop and acceptable
reverse leakage at high temp.
7. The output capacitor usually consists of a high valued
bulk C connected in parallel with a lower valued, low
ESR ceramic. Based on a maximum output ripple
voltage of 1%, or 120mV, the bulk C needs to be greater
than:
CI
Vf
A
V kHz F
OUT OUT MAX
OUT
=
=μ
()
.•
.
.•
001
15
0 01 12 300 41
The RMS ripple current rating for this capacitor needs
to exceed:
II V
V
AV
VA
RMS COUT O MAX O
IN MIN
()() ()
.• .
=
=15 12
523
To satisfy this high RMS current demand, two 47μF
Kemet capacitors (T495X476K020AS) are required. As
a result, the output ripple voltage is a low 50mV to
60mV. In parallel with these tantalums, two 10μF, low
ESR (X5R) Taiyo Yuden ceramic capacitors
(TMK432BJ106MM) are added for HF noise reduction.
Check the output ripple with a single oscilloscope probe
connected directly across the output capacitor termi-
nals, where the HF switching currents flow.
8. The choice of an input capacitor for a SEPIC converter
depends on the impedance of the source supply and the
amount of input ripple the converter will safely tolerate.
For this particular design and lab setup, a single 47μF
Kemet tantalum capacitor (T495X476K020AS) is ad-
equate. As with the output node, check the input ripple
with a single oscilloscope probe connected across the
input capacitor terminals. If any HF switching noise is
observed it is a good idea to decouple the input with a
low ESR, X5R ceramic capacitor as close to the V
IN
and
GND pins as possible.
9. The DC coupling capacitor in a SEPIC converter is
chosen based on its RMS current requirement and
must be rated for a minimum voltage of V
IN
plus the AC
ripple voltage. Start with the minimum value which
satisfies the RMS current requirement and then check
the ripple voltage to ensure that it doesn’t exceed the DC
rating.
II VV
V
AVV
VA
RMS CI O MAX OD
IN MIN
() ( ) ()
.• ..
+
=+=15 12 0 5
524
For this design a single 10μF, low ESR (X5R) Taiyo
Yuden ceramic capacitor (TMK432BJ106MM) is
adequate.
31
LTC1871-1
18711fa
TYPICAL APPLICATIO S
U
2.5V to 3.3V Input, 5V/2A Output Boost Converter
RUN
I
TH
FB
FREQ
MODE/SYNC
SENSE
V
IN
INTV
CC
GATE
GND
1
2
3
4
5
10
9
8
7
6
LTC1871-1
R
T
80.6k
1%
R1
12.1k
1%
R2
37.4k
1%
C
VCC
4.7μF
X5R
C
IN
47μF
6.3V
M1
C
IN
: SANYO POSCAP 6TPA47M
C
OUT1
: SANYO POSCAP 6TPB150M
C
OUT2
: TAIYO YUDEN JMK316BJ106ML
C
VCC
: TAIYO YUDEN LMK316BJ475ML
D1
L1
1.8μH
R
C
22k
C
C1
6.8nF
C
C2
47pF
C
OUT1
150μF
6.3V
×2
V
IN
2.5V to 3.3V
V
OUT
5V
2A
GND
1871 TA01a
+
C
OUT2
10μF
6.3V
X5R
×2
D1: INTERNATIONAL RECTIFIER 30BQ015
L1: TOKO DS104C2 B952AS-1R8N
M1: SILICONIX/VISHAY Si9426
+
OUTPUT CURRENT (A)
65
EFFICIENCY (%)
95
100
60
55
90
75
85
80
70
0.001 0.1 1 10
1871 TA01b
50
0.01
Output Efficiency at 2.5V and 3.3V Input
32
LTC1871-1
18711fa
TYPICAL APPLICATIO S
U
RUN
ITH
FB
FREQ
MODE/SYNC
SENSE
VIN
INTVCC
GATE
GND
1
2
3
4
5
10
9
8
7
6
LTC1871-1
RT1
150k
5%
RS1
0.007Ω
1W
EXT CLOCK
INPUT (200kHz)
R2
8.45k
1%
CVCC1
4.7μF
X5R
CIN2
2.2μF
35V
X5R
M1
D1
L2
5.6μH
L5*
0.3μH
CC1
47pF
CFB1
47pF
VIN
18V to 27V
GND
VOUT
28V
14A
1871 TA04
COUT1
2.2μF
35V
X5R
×3
COUT2
330μF
50V
CIN1: SANYO 50MV330AX
CIN2, 3: TAIYO YUDEN GMK325BJ225MN
COUT2, 4, 5: SANYO 50MV330AX
COUT1, 3, 6: TAIYO YUDEN GMK325BJ225MN
CVCC1, 2: TAIYO YUDEN LMK316BJ475ML
L1 TO L4: SUMIDA CEP125-5R6MC-HD
L5: SUMIDA CEP125-0R3NC-ND
D1, D2: ON SEMICONDUCTOR MBR2045CT
M1, M2: INTERNATIONAL RECTIFIER IRLZ44NS
R1
93.1k
1%
L1
5.6μH
*L5, COUT5 AND
COUT6 ARE AN
OPTIONAL SECONDARY
FILTER TO REDUCE
OUTPUT RIPPLE FROM
<500mVP-P TO <100mVP-P
+
COUT5*
330μF
50V
×4COUT6*
2.2μF
35V
X5R
CIN1
330μF
50V
+
RUN
ITH
FB
FREQ
MODE/SYNC
SENSE
VIN
INTVCC
GATE
GND
1
2
3
4
5
10
9
8
7
6
LTC1871-1
RT2
150k
5%
R3
12.1k
1%
RC
22k
R4
261k
1%
CVCC2
4.7μF
X5R
CIN3
2.2μF
35V
X5R
M2
D2
L4
5.6μH
CC2
47pF
CC3
6.8nF
CFB2
47pF
COUT3
2.2μF
35V
X5R
×3
COUT4
330μF
50V
L3
5.6μH
+
+
RS2
0.007Ω
1W
18V to 27V Input, 28V Output, 400W 2-Phase, Low Ripple, Synchronized RF Base Station Power Supply (Boost)
RUN
ITH
FB
FREQ
MODE/SYNC
SENSE
VIN
INTVCC
GATE
GND
1
2
3
4
5
10
9
8
7
6
LTC1871-1
RT
60.4k
1% RS
0.02Ω
R4
127Ω
1%
R2
54.9k
1%
R3
1.10k
1%
CVCC
4.7μF
10V
X5R
CIN1
1μF
16V
X5R
M1
D1
L1*
RC
22k
CC1
6.8nF
CC2
100pF
CDC1
4.7μF
16V
X5R
VIN
5V to 12V
VOUT1
12V
0.4A
GND
VOUT2
–12V
0.4A
1871 TA03
COUT1
4.7μF
16V
X5R
×3
COUT2
4.7μF
16V
X5R
×3
D1, D2: MBS120T3
L1 TO L3: COILTRONICS VP1-0076 (*COUPLED INDUCTORS)
M1: SILICONIX/VISHAY Si4840
R1
127k
1%
CIN2
47μF
16V
AVX
CDC2
4.7μF
16V
X5R
+
L2*
L3*
D2
NOTE:
1. VIN UVLO+ = 4.47V
VIN UVLO = 4.14V
5V to 12V Input, ±12V/0.2A Output SEPIC Converter with Undervoltage Lockout
33
LTC1871-1
18711fa
4.5V to 28V Input, 5V/2A Output SEPIC Converter with Undervoltage Lockout and Soft-Start
TYPICAL APPLICATIO S
U
RUN
I
TH
FB
FREQ
MODE/SYNC
SENSE
V
IN
INTV
CC
GATE
GND
1
2
3
4
5
10
9
8
7
6
LTC1871-1
R
T
162k
1%
C2
1μF
X5R NOTES:
1. V
IN
UVLO
+
= 4.17V
V
IN
UVLO
= 3.86V
2. SOFT-START dV
OUT
/dt = 5V/6ms
R4
49.9k
1%
R3
154k
1%
Q1
R1
115k
1%
R2
54.9k
1%
C
VCC
4.7μF
10V
X5R
C
IN1
2.2μF
35V
X5R
C
IN2
22μF
35V
M1
D1
L1*
L2*
R
C
12k
C
C1
8.2nF
C1
4.7nF
C
C2
47pF
R6
750Ω
R5
100Ω
C
OUT1
330μF
6.3V
V
IN
4.5V to 28V
V
OUT
5V
2A
(3A TO 4A PEAK)
GND
1871 TA02a
+
C
OUT2
22μF
6.3V
X5R
C
DC
2.2μF
25V
X5R
×3
+
C
IN1
, C
DC
: TAIYO YUDEN GMK325BJ225MN
C
IN2
: AVX TPSE226M035R0300
C
OUT1
: SANYO 6TPB330M
C
OUT2
: TAIYO YUDEN JMK325BJ226MN
C
VCC
: LMK316BJ475ML
D1: INTERNATIONAL RECTIFIER 30BQ040
L1, L2: BH ELECTRONICS BH510-1007 (*COUPLED INDUCTORS)
M1: SILICONIX/VISHAY Si4840
Q1: PHILIPS BC847BF
Soft-Start
V
OUT
1V/DIV
1ms/DIV 1871 TA02b
Load Step Response at VIN = 4.5V
V
OUT
100mV/DIV
(AC)
250μs/DIV 1871 TA02c
I
OUT
1A/DIV
(DC)
V
OUT
100mV/DIV
(AC)
250μs/DIV 1871 TA02d
I
OUT
1A/DIV
(DC)
2.2A
0.5A
2.2A
0.5A
34
LTC1871-1
18711fa
TYPICAL APPLICATIO S
U
5V to 15V Input, –5V/5A Output Positive-to-Negative Converter with Undervoltage Lockout and Level-Shifted Feedback
RUN
I
TH
FB
FREQ
MODE/SYNC
SENSE
V
IN
INTV
CC
GATE
GND
1
2
3
4
5
10
9
8
7
6
LTC1871-1
R
T
80.6k
1%
R1
154k
1%
R2
68.1k
1%
C1
1nF
C
VCC
4.7μF
10V
X5R
C2
10nF
R4
10k
1% R5
40.2k
1%
R3
10k
1%
4
3
2
6
1
C
IN
47μF
16V
X5R
M1
C
IN
: TDK C5750X5R1C476M
C
DC
: TDK C5750X7R1E226M
C
OUT
: TDK C5750X5R0J107M
C
VCC
: TAIYO YUDEN LMK316BJ475ML
D1
L1* L2*
R
C
10k
C
C1
10nF
C
C2
330pF
V
IN
5V to 15V
V
OUT
–5V
5A
GND
1871 TA05
C
OUT
100μF
6.3V
X5R
×2
D1: ON SEMICONDUCTOR MBRB2035CT
L1, L2: COILTRONICS VP5-0053 (*3 WINDINGS IN PARALLEL
FOR THE PRIMARY, 3 IN PARALLEL FOR SECONDARY)
M1: INTERNATIONAL RECTIFIER IRF7822
C
DC
22μF
25V
X7R
+
LT1783
35
LTC1871-1
18711fa
U
PACKAGE DESCRIPTIO
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
MS Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661)
MSOP (MS) 0307 REV E
0.53 ± 0.152
(.021 ± .006)
SEATING
PLANE
0.18
(.007)
1.10
(.043)
MAX
0.17 – 0.27
(.007 – .011)
TYP
0.86
(.034)
REF
0.50
(.0197)
BSC
12345
4.90 ± 0.152
(.193 ± .006)
0.497 ± 0.076
(.0196 ± .003)
REF
8910 76
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.254
(.010) 0° – 6° TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
0.889 ± 0.127
(.035 ± .005)
RECOMMENDED SOLDER PAD LAYOUT
0.305 ± 0.038
(.0120 ± .0015)
TYP
0.50
(.0197)
BSC
0.1016 ± 0.0508
(.004 ± .002)
36
LTC1871-1
18711fa
© LINEAR TECHNOLOGY CORPORATION 2007
LT 0807 REV A • PRINTED IN USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
FAX: (408) 434-0507
www.linear.com
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+
RUN
ITH
FB
FREQ
MODE/SYNC
SENSE
VIN
INTVCC
GATE
GND
LTC1871-1
RT
120k f = 200kHz
*COILTRONICS VP5-0155
(PRIMARY = 3 WINDINGS IN PARALLEL)
C1
4.7μF
X5R
+CIN
220μF
16V
TPS
C3
10μF
25V
X5R
IRL2910
RS
0.012Ω
C8
0.1μF
D3
10BQ060
5
V
IN
7V TO 12V
T1*
1, 2, 3
R
C
82k
C
C1
1nF
C
C2
100pF
C
R
1nF
R1
49.9k
1%
R2
150k
1%
D4
10BQ060
6
D2
10BQ060
4
C4
10μF
25V
X5R
C
OUT
3.3μF
100V
GND
V
OUT1
–24V
200mA
V
OUT2
–72V
200mA
C5
10μF
25V
X5R
4
3
1871 TA06
2
6
1
10k
R
F1
10k
1%
R
F2
196k
1%
C2
4.7μF
50V
X5R
+
LT1783
High Power SLIC Supply with Undervoltage Lockout
(Also See the LTC3704 Data Sheet)
TYPICAL APPLICATIO S
U