ESDA5V3L - STMicroelectronics

1/6

ESDAxxL

Marchr 2000 - Ed: 4A

DUAL TRANSIL ARRAY

FOR ESD PROTECTION

SOT23

Where transient overvoltage protection in ESD

sensitive equipment is required, such as :

- COMPUTERS

- PRINTERS

- COMMUNICATION SYSTEMS

It is particulary recommended for the RS232 I/O

port protection where the line interface withstands

only with 2kV ESD surges.

APPLICATIONS

Application Specific Discretes

A.S.D.

FUNCTIONAL DIAGRAM

2 UNIDIRECTIONAL TRANSIL FUNCTIONS.

LOW LEAKAGE CURRENT : IRmax. < 20µAat

BR.

300 W PEAK PULSE POWER (8/20µs)

FEATURES

DESCRIPTION

The ESDAxxL is a dual monolithic voltage

suppressordesignedtoprotectcomponentswhich

are connected to data and transmission lines

against ESD.

It clamps the voltage just above the logic level

supply for positive transients, and to a diode drop

below ground for negative transients.

It can also work as bidirectionnal suppressor by

connecting only pin1 and 2.

BENEFITS

High ESD protection level : up to 25 kV.

High integration.

Suitable for high density boards.

IEC61000-4-2 level 4

MIL STD 883C-Method 3015-6 : class 3.

(human body model)

COMPLIESWITHTHEFOLLOWING STANDARDS:

ESDAxxL

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Symbol Parameter

VRM Stand-off voltage

VBR Breakdown voltage

VCL Clamping voltage

IRM Leakage current

IPP Peak pulse current

αTVoltage temperature coefficient

CCapacitance

Rd Dynamic resistance

VFForward voltage drop

ELECTRICAL CHARACTERISTICS (Tamb = 25°C)

VBR

VRM

IPP

IRM V

Slope:

Symbol Parameter Value Unit

VPP Electrostatic discharge

MIL STD 883C - Method 3015-6

IEC61000-4-2 air discharge

IEC61000-4-2 contact discharge

PPP Peak pulse power (8/20 µs) 300 W

Tstg

TjStorage temperature range

Maximum junction temperature -55to+150

150 °C

°C

TLMaximum lead temperature for soldering during 10s 260 °C

Top Operating temperature range -40to+125 °C

note 1: Evolution of functional parameters is given by curves.

ABSOLUTE MAXIMUM RATINGS (Tamb = 25°C)

Types VBR @IRIRM @V

RM Rd αTC V

min. max. max. typ. max. typ. max.

note 1 note 2 0V bias

VVmAµAV

Ω

10-4/⊃CpF V mA

ESDA5V3L 5.3 5.9 1 2 3 280 5 220 1.25 200

ESDA6V1L 6.1 7.2 1 20 5.25 350 6 140 1.25 200

ESDA14V2L 14.2 15.8 1 5 12 650 10 90 1.25 200

ESDA25L 25 30 1 1 24 1000 10 50 1.2 10

note 1 : Square pulse Ipp = 15A, tp=2.5µs.

note 2 :∆VBR =αT* (Tamb -25°C) * VBR (25°C)

ESDAxxL

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The ESDA family has been designed to clamp fast

spikes like ESD. Generally the PCB designers

need to calculate easily the clamping voltage VCL.

This is why we give the dynamic resistance in

addition to the classical parameters. The voltage

across the protection cell can be calculated with

the following formula:

VCL =V

BR +RdI

WhereIppisthepeakcurrentthroughtheESDAcell.

DYNAMIC RESISTANCE MEASUREMENT

The short duration of the ESD has led us to prefer

amore adapted test wave,asbelow defined, to the

classical 8/20µs and 10/1000µs surges.

2.5µs duration measurement wave.

As the value of the dynamic resistance remains

stable for a surge duration lower than 20µs, the

2.5µs rectangular surge is well adapted. In

addition both rise and fall times are optimized to

avoid any parasitic phenomenon during the

measurement of Rd.

CALCULATION OF THE CLAMPING VOLTAGE

USE OF THE DYNAMIC RESISTANCE

2µs

tp = 2.5µs

Ipp

ESDAxxL

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25 50 75 100 125

100

200

Tj(°C)

IR[Tj] / IR [T j= 2 5 ° C ]

ESDA6V1L

ESDA14V2L

ESDA5V3L

ESDA25L

Fig. 5: Relative variation of leakage current versus

junction temperature (typical values).

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

0.01

0.10

1.00

5.00

VFM(V)

IFM(A)

Tj=25°C ESDA5V3L

ESDA6V1L

ESDA14V2L

ESDA25L

Fig. 6: Peak forward voltage drop versus peak for-

ward current (typical values).

0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80

0.1

1.0

10.0

50.0

Vcl(V)

Ipp(A)

tp=2.5µs

ESDA6V1L ESDA14V2L

ESDA5V3L ESDA25L

Fig. 3: Clamping voltage versus peak pulse cur-

rent (Tj initial = 25 °C).

Rectangular waveform tp = 2.5 µs.

12 51020 50

100

200

VR(V)

C(pF)

F=1MHz

Vosc=30mV

ESDA6V1L

ESDA14V2L

ESDA5V3L

ESDA25L

Fig. 4: Capacitance versus reverse applied volt-

age (typical values).

0 25 50 75 100 125 150

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.1

Tj initial(°C )

Ppp [T j in itia l]/P p p [ T j in itia l= 2 5° C ]

Fig. 1: Peak power dissipation versus initial junc-

tion temperature.

1 10 100

100

1000

3000

tp(µs)

Ppp(W)

Fig. 2: Peak pulse power versus exponential

pulse duration (Tj initial = 25 °C).

ESDAxxL

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ESD

sensitive

device

GND

2 * ESDAXXL

I/O

1. ESD protection by the ESDAxxL

Electrostatic discharge (ESD) is a major cause of

failure in electronic systems.

Transient Voltage Suppressors (TVS) are an ideal

choice for ESD protection. They are capable of

clamping the incoming transient to a low enough

level such that damage to the protected

semiconductor is prevented.

SurfacemountTVS arrays offer the best choice for

minimal lead inductance.

They serve as parallel protection elements,

connected between the signal line to ground. As

the transient rises above the operating voltage of

the device, the TVS array becomes a low

impedance path diverting the transient current to

ground.

The ESDAxxL array is the ideal board level

protection of ESD sensitive semiconductor

components.

ThetinySOT23 package allows design flexibility in

the design of high density boards where the space

savingis at a premium.Thisenables to shorten the

routing and contributes to hardening againt ESD.

2. Circuit Board Layout

Circuit board layout is a critical design step in the

suppression of ESD induced transients. The

following guidelines are recommended :

TheESDAxxLshouldbeplacedas close as pos-

sible to the input terminals or connectors.

The path length between the ESD suppressor

and the protected line should be minimized

All conductive loops, including power and

ground loops should be minimized

The ESD transient return path to ground should

be kept as short as possible.

Ground planes should be used whenever possi-

ble.

ESDAxxL

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TYPE MARKING

ESDA5V3L EL53

ESDA6V1L EL61

ESDA14V2L EL15

ESDA25L EL25

Packaging: Standard packaging is tape and reel.

MARKING

Informationfurnishedisbelievedtobeaccurateandreliable.However,STMicroelectronicsassumesnoresponsibilityfortheconsequencesof

useofsuch information nor for any infringement of patentsorotherrights of third parties which may result fromitsuse.No license is granted by

implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to

change without notice. This publication supersedes and replaces all information previously supplied.

STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written ap-

proval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics

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PACKAGE MECHANICAL DATA

SOT23 (Plastic)

REF.

DIMENSIONS

Millimeters Inches

Min. Max. Min. Max.

A 0.89 1.4 0.035 0.055

A1 0 0.1 0 0.004

B 0.3 0.51 0.012 0.02

c 0.085 0.18 0.003 0.007

D 2.75 3.04 0.108 0.12

e 0.85 1.05 0.033 0.041

e1 1.7 2.1 0.067 0.083

E 1.2 1.6 0.047 0.063

H 2.1 2.75 0.083 0.108

L 0.6 typ. 0.024 typ.

S 0.35 0.65 0.014 0.026

FOOT PRINT (in millimeters)

0.9

0.035 0.9

0.035

1.9

0.075

inch

2.35

0.92

1.1

0.043

1.1

0.043

1.45

0.037

0.9

0.035

ORDER CODE

ESDA 6V1 L

ESD ARRAY

VBR min

PACKAGE : SOT23 PLASTIC