56800E
16-bit Digital Signal Controllers
freescale.com
56854
Data Sheet
Technical Data
DSP56854
Rev. 6
01/2007
56854 Technical Data, Rev. 6
Freescale Semiconductor 3
56854 General Description
• 120 MIPS at 120MHz
• 16K x 16-bit Program SRAM
• 16K x 16-bit Data SRAM
• 1K x 16-bit Boot ROM
• Access up to 2M words of program or 8M data memory
• Chip Select Logic for glue-less interface to ROM and
SRAM
• Six (6) independent channels of DMA
• Enhanced Synchronous Serial Interfaces (ESSI)
• Two (2) Serial Communication Interfaces (SCI)
• Serial Port Interface (SPI)
• 8-bit Parallel Host Interface
• General Purpose 16-bit Quad Timer
• JTAG/Enhanced On-Chip Emulation (OnCE™) for
unobtrusive, real-time debugging
• Computer Operating Properly (COP)/Watchdog Timer
• Time-of-Day (TOD)
• 128 LQFP package
•Up to 41 GPIO
56854 Block Diagram
JTAG/
Enhanced
OnCE
Program Controller
and
Hardware Looping Unit
Data ALU
16 x 16 + 36 → 36-Bit MAC
Three 16-bit Input Registers
Four 36-bit Accumulators
Address
Generation Unit
Bit
Manipulation
Unit
16-Bit
DSP56800E Core
XTAL
EXTAL
Interrupt
Controller
Quad
Timer
or
GPIOG
4
CLKO
External Address
Bus Switch
External Bus
Interface Unit
4
RESET
IRQA
IRQB
V
DD
V
SSIO
V
DDA
V
SSA
External Data
Bus Switch
Bus Control
WR Enable
RD Enable
CS0-CS3[3:0] or
A0-20 [20:0]
MODEA-C or
D0-D15 [15:0]
6
Program Memory
16,384 x 16 SRAM
Boot ROM
1024 x 16 ROM
Data Memory
16,384 x 16 SRAM
PDB
PDB
XAB1
XAB2
XDB2
CDBR
SPI
or
GPIOF
2 SCI
or
GPIOE
IPBus Bridge (IPBB)
3
(GPIOH0-H2)
610
V
DDIO
11
Decoding
Peripherals
4
System
Bus
Control
Memory
PAB
PAB
CDBW
CDBR
CDBW
V
SS
6
GPIOA0-GPIOA3[3:0]
6
ESSI0
or
GPIOC
Host
Interface
or
GPIOB
16
RSTO
DMA
6 channel
POR
Integration
Module
System
COP/
Watch-
dog
Time
of
Day
Clock
Generator
OSC PLL
IPBus CLK
COP/TOD CLK
Core CLK
IPAB
IPWDB
IPRDB
DMA Requests
56854 Technical Data, Rev. 6
4 Freescale Semiconductor
Part 1 Overview
1.1 56854 Features
1.1.1 Digital Signal Processing Core
• Efficient 16-bit engine with dual Harvard architecture
• 120 Million Instructions Per Second (MIPS) at 120MHz core frequency
• Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)
• Four (4) 36-bit accumulators including extension bits
• 16-bit bidirectional shifter
• Parallel instruction set with unique DSP addressing modes
• Hardware DO and REP loops
• Three (3) internal address buses and one (1) external address bus
• Four (4) internal data buses and one (1) external data bus
• Instruction set supports both DSP and controller functions
• Four (4) hardware interrupt levels
• Five (5) software interrupt levels
• Controller-style addressing modes and instructions for compact code
• Efficient C Compiler and local variable support
• Software subroutine and interrupt stack with depth limited only by memory
• JTAG/Enhanced OnCE debug programming interface
1.1.2 Memory
• Harvard architecture permits up to three (3) simultaneous accesses to program and data memory
•On-Chip Memory
—16K × 16-bit Program SRAM
—16K × 16-bit Data SRAM
—1K × 16-bit Boot ROM
• Off-Chip Memory Expansion (EMI)
— Access up to 2M words of program memory or up to 8M words of data memory
— Chip Select Logic for glue-less interface to ROM and SRAM
1.1.3 Peripheral Circuits for 56854
• General Purpose 16-bit Quad Timer*
• Two (2) Serial Communication Interfaces (SCI)*
• Serial Peripheral Interface (SPI) Port*
• Enhanced Synchronous Serial Interface (ESSI) module*
• Computer Operating Properly (COP)/Watchdog Timer
56854 Description
56854 Technical Data, Rev. 6
Freescale Semiconductor 5
• JTAG/Enhanced On-Chip Emulation (EOnCE) for unobtrusive, real-time debugging
• Six (6) independent channels of DMA
• 8-bit Parallel Host Interface*
•Time of Day
•Up to 41 GPIO
* Each peripheral I/O can be used alternately as a General Purpose I/O if not needed
1.1.4 Energy Information
• Fabricated in high-density CMOS with 3.3V, TTL-compatible digital inputs
• Wait and Stop modes available
1.2 56854 Description
The 56854 is a member of the 56800E core-based family of controllers. It combines, on a single chip, the
processing power of a Digital Signal Processor (DSP) and the functionality of a microcontroller with a
flexible set of peripherals to create an extremely cost-effective solution. Because of its low cost,
configuration flexibility, and compact program code, the 56854 is well-suited for many applications. The
56854 includes many peripherals that are especially useful for low-end Internet appliance applications and
low-end client applications such as telephony; portable devices; Internet audio; and point-of-sale systems,
such as noise suppression; ID tag readers; sonic/subsonic detectors; security access devices; remote
metering; sonic alarms.
The 56800E core is based on a Harvard-style architecture consisting of three execution units operating in
parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming
model and optimized instruction set allow straightforward generation of efficient, compact DSP and
control code. The instruction set is also highly efficient for C Compilers, enabling rapid development of
optimized control applications.
The 56854 supports program execution from either internal or external memories. Two data operands can
be accessed from the on-chip Data RAM per instruction cycle. The 56854 also provides two external
dedicated interrupt lines, and up to 41 General Purpose Input/Output (GPIO) lines, depending on
peripheral configuration.
The 56854 controller includes 16K words of Program RAM, 16K words of Data RAM, and 1K words of
Boot ROM. It also supports program execution from external memory.
This controller also provides a full set of standard programmable peripherals that include an 8-bit parallel
Host Interface, Enhanced Synchronous Serial Interface (ESSI), one Serial Peripheral Interface (SPI), two
Serial Communications Interfaces (SCIs), and a Quad Timer. The Host Interface, ESSI, SPI, SCI, four chip
selects and quad timer can be used as General Purpose Input/Outputs (GPIOs) if its primary function is not
required.
56854 Technical Data, Rev. 6
6 Freescale Semiconductor
1.3 State of the Art Development Environment
• Processor ExpertTM (PE) provides a Rapid Application Design (RAD) tool that combines easy-to-use
component-based software application creation with an expert knowledge system.
• The Code Warrior Integrated Development Environment is a sophisticated tool for code navigation,
compiling, and debugging. A complete set of evaluation modules (EVMs) and development system cards
will support concurrent engineering. Together, PE, Code Warrior and EVMs create a complete, scalable
tools solution for easy, fast, and efficient development.
1.4 Product Documentation
The four documents listed in Table 1-1 are required for a complete description of and proper design with
the 56854. Documentation is available from local Freescale distributors, Freescale Semiconductor sales
offices, Freescale Literature Distribution Centers, or online at www.freescale.com.
Table 1-1 56854 Chip Documentation
Topic Description Order Number
DSP56800E
Reference Manual
Detailed description of the 56800E architecture, 16-bit
controller core processor and the instruction set
DSP56800ERM
DSP56854
User’s Manual
Detailed description of memory, peripherals, and
interfaces of the 56854
DSP5685xUM
DSP56854
Technical Data Sheet
Electrical and timing specifications, pin descriptions,
and package descriptions
DSP56854
DSP56854
Errata
Details any chip issues that might be present DSP56854E
Data Sheet Conventions
56854 Technical Data, Rev. 6
Freescale Semiconductor 7
1.5 Data Sheet Conventions
This data sheet uses the following conventions:
OVERBAR This is used to indicate a signal that is active when pulled low. For example, the RESET pin is
active when low.
“asserted” A high true (active high) signal is high or a low true (active low) signal is low.
“deasserted” A high true (active high) signal is low or a low true (active low) signal is high.
Examples: Signal/Symbol Logic State Signal State Voltage1
1. Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.
PIN True Asserted VIL/VOL
PIN False Deasserted VIH/VOH
PIN True Asserted VIH/VOH
PIN False Deasserted VIL/VOL
56854 Technical Data, Rev. 6
8 Freescale Semiconductor
Part 2 Signal/Connection Descriptions
2.1 Introduction
The input and output signals of the 56854 are organized into functional groups, as shown in Table 2-1 and
as illustrated in Figure 2-1. In Table 3-1, each table row describes the package pin and the signal or
signals present.
1. VDD = VDD CORE, VSS = VSS CORE, VDDIO= VDD IO, VSSIO = VSS IO, VDDA = VDD ANA, VSSA = VSS ANA
2. MODA, MODB and MODC can be used as GPIO after the bootstrap process has completed.
3. The following Host Interface signals are multiplexed: HRWB to HRD, HDS to HWR, HREQ to HTRQ and HACK to HRRQ.
Table 2-1 Functional Group Pin Allocations
Functional Group Number of Pins
Power (VDD, VDDIO, or VDDA)(6, 11, 1)1
Ground (VSS, VSSIO,or VSSA)(6, 10, 1)1
PLL and Clock 3
External Bus Signals 39
External Chip Select* 4
Interrupt and Program Control 72
Host Interface (HI)* 163
Enhanced Synchronous Serial Interface (ESSI0) Port* 6
Serial Communications Interface (SCI0) Ports* 2
Serial Communications Interface (SCI1) Ports* 2
Serial Peripheral Interface (SPI) Port* 4
Quad Timer Module Port* 4
JTAG/Enhanced On-Chip Emulation (EOnCE) 6
*Alternately, GPIO pins
Introduction
56854 Technical Data, Rev. 6
Freescale Semiconductor 9
Figure 2-1 56854 Signals Identified by Functional Group2
1. Specifically for PLL, OSC, and POR.
2. Alternate pin functions are shown in parentheses.
56854
Logic
Power
I/O
Power
SCI 0
JTAG /
Enhanced
OnCE
Timer
Module
ESSI 0
SPI
Chip
Select
External
Bus
Analog
Power1
PLL /
Clock
Host
Interface
SCI 2
Interrupt /
Program
Control
VDD
VSS
VDDIO
VSSIO
VDDA
VSSA
A0 - A20
RD
D0 - D15
WR
CS0 - CS3 (GPIOA0 - A3)
HD0 - HD7 (GPIOB0 - B7)
HA0 - HA2 (GPIOB8 - B10)
HRWB (HRD) (GPIOB11)
HDS (HWR) (GPIOB12)
HCS (GPIOB13)
HREQ (HTRQ) (GPIOB14)
HACK (HRRQ) (GPIOB15)
TIO0 - TIO3 (GPIOG0 - G3)
IRQA
IRQB
MODA, MODB, MODC
(GPIOH0 - H2)
RESET
RSTO
Host
Interface
XTAL
RXDO (GPIOE0)
TXDO (GPIOE1)
RXD1 (GPIOE2)
TXD1 (GPIOE3)
STD0 (GPIOC0)
SRD0 (GPIOC1)
SCK0 (GPIOC2)
SC00 (GPIOC3)
SC01 (GPIOC4)
SC02 (GPIOC5)
MISO (GPIOF0)
MOSI (GPIOF1)
SCK (GPIOF2)
SS (GPIOF3)
EXTAL
CLKO
TCK
TDI
TDO
TMS
TRST
DE
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
3
1
1
4
1
1
1
1
1
3
8
4
1
1
16
21
1
1
10
11
6
6
56854 Technical Data, Rev. 6
10 Freescale Semiconductor
Part 3 Signals and Package Information
All digital inputs have a weak internal pull-up circuit associated with them. These pull-up circuits are
enabled by default. Exceptions:
1. When a pin has GPIO functionality, the pull-up may be disabled under software control.
2. MODE A, MODE B and MODE C pins have no pull-up.
3. TCK has a weak pull-down circuit always active.
4. Bidirectional I/O pullups automatically disable when the output is enabled.
This table is presented consistently with the Signals Identified by Functional Group figure.
1. BOLD entries in the Type column represents the state of the pin just out of reset.
2. Output(Z) means an output in a High-Z condition.
Table 3-1. 56854 Signal and Package Information for the 128-pin LQFP
Pin No. Signal Name Type Description
13 VDD VDD Power (VDD)—These pins provide power to the internal structures
of the chip, and should all be attached to VDD.
47 VDD
64 VDD
79 VDD
80 VDD
112 VDD
14 VSS VSS Ground (VSS)—These pins provide grounding for the internal
structures of the chip and should all be attached to VSS.
48 VSS
63 VSS
81 VSS
96 VSS
113 VSS
Introduction
56854 Technical Data, Rev. 6
Freescale Semiconductor 11
5 VDDIO VDDIO Power (VDDIO)—These pins provide power for all I/O and ESD
structures of the chip, and should all be attached to VDDIO (3.3V).
18 VDDIO
41 VDDIO
55 VDDIO
61 VDDIO
72 VDDIO
91 VDDIO
92 VDDIO
100 VDDIO
114 VDDIO
124 VDDIO
6 VSSIO VSSIO Ground (VSSIO)—These pins provide grounding for all I/O and ESD
structures of the chip and should all be attached to VSS.
19 VSSIO
42 VSSIO
56 VSSIO
62 VSSIO
74 VSSIO
93 VSSIO
102 VSSIO
115 VSSIO
125 VSSIO
22 VDDA VDDA Analog Power (VDDA)—These pins supply an analog power
source.
23 VSSA VSSA Analog Ground (VSSA)—This pin supplies an analog ground.
Table 3-1. 56854 Signal and Package Information for the 128-pin LQFP (Continued)
Pin No. Signal Name Type Description
56854 Technical Data, Rev. 6
12 Freescale Semiconductor
9A0 Output(Z) Address Bus (A0-A20)—These signals specify a word address for
external program or data memory access.
10 A1
11 A2
12 A3
26 A4
27 A5
28 A6
29 A7
43 A8
44 A9
45 A10
46 A11
57 A12
58 A13
59 A14
60 A15
67 A16
68 A17
69 A18
70 A19
71 A20
Table 3-1. 56854 Signal and Package Information for the 128-pin LQFP (Continued)
Pin No. Signal Name Type Description
Introduction
56854 Technical Data, Rev. 6
Freescale Semiconductor 13
73 D0 Input/Output(Z) Data Bus (D0-D15)—These pins provide the bidirectional data for
external program or data memory accesses.
86 D1
87 D2
88 D3
89 D4
90 D5
107 D6
108 D7
109 D8
110 D9
111 D10
122 D11
123 D12
126 D13
127 D14
128 D15
7RD Output Read Enable (RD) —is asserted during external memory read
cycles.
This signal is pulled high during reset.
8WR Output Write Enable (WR)— is asserted during external memory write
cycles.
This signal is pulled high during reset.
75 CS0
GPIOA0
Output
Input/Output
External Chip Select (CS0)—This pin is used as a dedicated GPIO.
Port A GPIO (0) —This pin is a General Purpose I/O (GPIO) pin
when not configured for host port usage.
76 CS1
GPIOA1
Output
Input/Output
External Chip Select (CS1)—This pin is used as a dedicated GPIO.
Port A GPIO (1) —This pin is a General Purpose I/O (GPIO) pin
when not configured for host port usage.
Table 3-1. 56854 Signal and Package Information for the 128-pin LQFP (Continued)
Pin No. Signal Name Type Description
56854 Technical Data, Rev. 6
14 Freescale Semiconductor
77 CS2
GPIOA2
Output
Input/Output
External Chip Select (CS2)—This pin is used as a dedicated GPIO.
Port A GPIO (2) —This pin is a General Purpose I/O (GPIO) pin
when not configured for host port usage.
78 CS3
GPIOA3
Output
Input/Output
External Chip Select (CS3)—This pin is used as a dedicated GPIO.
Port A GPIO (3)—This pin is a General Purpose I/O (GPIO) pin
when not configured for host port usage.
30 HD0
GPIOB0
Input
Input/Output
Host Address (HD0)—This input provides data selection for HI
registers.
This pin is disconnected internally during reset.
Port B GPIO (0)—This pin is a General Purpose I/O (GPIO) pin
when not configured for host port usage.
31 HD1
GPIOB1
Input
Input/Output
Host Address (HD1)—This input provides data selection for HI
registers.
This pin is disconnected internally during reset.
Port B GPIO (1)—This pin is a General Purpose I/O (GPIO) pin
when not configured for host port usage.
32 HD2
GPIOB2
Input
Input/Output
Host Address (HD2)—This input provides data selection for HI
registers.
This pin is disconnected internally during reset.
Port B GPIO (2)—This pin is a General Purpose I/O (GPIO) pin
when not configured for host port usage.
36 HD3
GPIOB3
Input
Input/Output
Host Address (HD3)—This input provides data selection for HI
registers.
This pin is disconnected internally during reset.
Port B GPIO (3)—This pin is a General Purpose I/O (GPIO) pin
when not configured for host port usage.
37 HD4
GPIOB4
Input
Input/Output
Host Address (HD4)—This input provides data selection for HI
registers.
This pin is disconnected internally during reset.
Port B GPIO (4)—This pin is a General Purpose I/O (GPIO) pin
when not configured for host port usage.
Table 3-1. 56854 Signal and Package Information for the 128-pin LQFP (Continued)
Pin No. Signal Name Type Description
Introduction
56854 Technical Data, Rev. 6
Freescale Semiconductor 15
38 HD5
GPIOB5
Input
Input/Output
Host Address (HD5)—This input provides data selection for HI
registers.
This pin is disconnected internally during reset.
Port B GPIO (5)—This pin is a General Purpose I/O (GPIO) pin
when not configured for host port usage.
39 HD6
GPIOB6
Input
Input/Output
Host Address (HD6)—This input provides data selection for HI
registers.
This pin is disconnected internally during reset.
Port B GPIO (6)—This pin is a General Purpose I/O (GPIO) pin
when not configured for host port usage.
40 HD7
GPIOB7
Input
Input/Output
Host Address (HD7)—This input provides data selection for HI
registers.
This pin is disconnected internally during reset.
Port B GPIO (7)—This pin is a General Purpose I/O (GPIO) pin
when not configured for host port usage.
82 HA0
GPIOB8
Input
Input/Output
Host Address (HA0)—These inputs provide the address selection
for HI registers.
These pins are disconnected internally during reset.
Port B GPIO (8)—These pins are General Purpose I/O (GPIO) pins
when not configured for host port usage.
83 HA1
GPIOB9
Input
Input/Output
Host Address (HA0)—These inputs provide the address selection
for HI registers.
These pins are disconnected internally during reset.
Port B GPIO (9)—These pins are General Purpose I/O (GPIO) pins
when not configured for host port usage.
84 HA2
GPIOB10
Input
Input/Output
Host Address (HA0)—These inputs provide the address selection
for HI registers.
These pins are disconnected internally during reset.
Port B GPIO (10)—These pins are General Purpose I/O (GPIO)
pins when not configured for host port usage.
Table 3-1. 56854 Signal and Package Information for the 128-pin LQFP (Continued)
Pin No. Signal Name Type Description
56854 Technical Data, Rev. 6
16 Freescale Semiconductor
85 HRWB
HRD
GPIOB11
Input
Input
Input/Output
Host Read/Write (HRWB)—When the HI08 is programmed to
interface to a single-data-strobe host bus and the HI function is
selected, this signal is the Read/Write input.
These pins are disconnected internally.
Host Read Data (HRD)—This signal is the Read Data input when
the HI08 is programmed to interface to a double-data-strobe host
bus and the HI function is selected.
Port B GPIO (11)—This pin is a General Purpose I/O (GPIO) pin
when not configured for host port usage.
103 HDS
HWR
GPIOB12
Input
Input
Input/Output
Host Data Strobe (HDS)—When the HI08 is programmed to
interface to a single-data-strobe host bus and the HI function is
selected, this input enables a data transfer on the HI when HCS is
asserted.
These pins are disconnected internally.
Host Write Enable (HWR)—This signal is the Write Data input
when the HI08 is programmed to interface to a double-data-strobe
host bus and the HI function is selected.
Port B GPIO (12)—This pin is a General Purpose I/O (GPIO) pin
when not configured for host port usage.
104 HCS
GPIOB13
Input
Input/Output
Host Chip Select (HCS)—This input is the chip select input for the
Host Interface.
These pins are disconnected internally.
Port B GPIO (13)—This pin is a General Purpose I/O (GPIO) pin
when not configured for host port usage.
105 HREQ
HTRQ
GPIOB14
Open Drain
Output
Open Drain
Output
Input/Output
Host Request (HREQ)—When the HI08 is programmed for
HRMS=0 functionality (typically used on a single-data-strobe bus),
this open drain output is used by the HI to request service from the
host processor. The HREQ may be connected to an interrupt
request pin of a host processor, a transfer request of a DMA
controller, or a control input of external circuitry.
These pins are disconnected internally.
Transmit Host Request (HTRQ)—This signal is the Transmit Host
Request output when the HI08 is programmed for HRMS=1
functionality and is typically used on a double-data-strobe bus.
Port B GPIO (14)—This pin is a General Purpose I/O (GPIO) pin
when not configured for host port usage.
Table 3-1. 56854 Signal and Package Information for the 128-pin LQFP (Continued)
Pin No. Signal Name Type Description
Introduction
56854 Technical Data, Rev. 6
Freescale Semiconductor 17
106 HACK
HRRQ
GPIOB15
Input
Open Drain
Output
Input/Output
Host Acknowledge (HACK)—When the HI08 is programmed for
HRMS=0 functionality (typically used on a single-data-strobe bus),
this input has two functions: (1) provide a Host Acknowledge signal
for DMA transfers or (2) to control handshaking and provide a Host
Interrupt Acknowledge compatible with the MC68000 family
processors.
These pins are disconnected internally.
Receive Host Request (HRRQ)—This signal is the Receive Host
Request output when the HI08 is programmed for HRMS=1
functionality and is typically used on a double-data-strobe bus.
Port B GPIO(15)—This pin is a General Purpose I/O (GPIO) pin
when not configured for host port usage.
101 TIO0
GPIOG0
Input/Output
Input/Output
Timer Input/Outputs (TIO0)—This pin can be independently
configured to be either a timer input source or an output flag.
Port G GPIO (0)—This pin is a General Purpose I/O (GPIO) pin that
can individually be programmed as an input or output pin.
99 TIO1
GPIOG1
Input/Output
Input/Output
Timer Input/Outputs (TIO1)—This pin can be independently
configured to be either a timer input source or an output flag.
Port G GPIO (1)—This pin is a General Purpose I/O (GPIO) pin that
can individually be programmed as an input or output pin.
98 TIO2
GPIOG2
Input/Output
Input/Output
Timer Input/Outputs (TIO2)—This pin can be independently
configured to be either a timer input source or an output flag.
Port G GPIO (2)—This pin is a General Purpose I/O (GPIO) pin that
can individually be programmed as an input or output pin.
97 TIO3
GPIOG3
Input/Output
Input/Output
Timer Input/Outputs (TIO3)—This pin can be independently
configured to be either a timer input source or an output flag.
Port G GPIO (3)—This pin is a General Purpose I/O (GPIO) pin that
can individually be programmed as an input or output pin.
20 IRQA Input External Interrupt Request A and B—The IRQA and IRQB inputs
are asynchronous external interrupt requests that indicate that an
external device is requesting service. A Schmitt trigger input is used
for noise immunity. They can be programmed to be level-sensitive
or negative-edge- triggered. If level-sensitive triggering is selected,
an external pull-up resistor is required for Wired-OR operation.
21 IRQB
Table 3-1. 56854 Signal and Package Information for the 128-pin LQFP (Continued)
Pin No. Signal Name Type Description
56854 Technical Data, Rev. 6
18 Freescale Semiconductor
15 MODA
GPIOH0
Input
Input/Output
Mode Select (MODA)—During the bootstrap process MODA
selects one of the eight bootstrap modes.
Port H GPIO (0)—This pin is a General Purpose I/O (GPIO) pin
after the bootstrap process has completed.
16 MODB
GPIOH1
Input
Input/Output
Mode Select (MODB)—During the bootstrap process MODB
selects one of the eight bootstrap modes.
Port H GPIO (1)—This pin is a General Purpose I/O (GPIO) pin
after the bootstrap process has completed.
17 MODC
GPIOH2
Input
Input/Output
Mode Select (MODC)—During the bootstrap process MODC
selects one of the eight bootstrap modes.
Port H GPIO (2)—This pin is a General Purpose I/O (GPIO) pin
after the bootstrap process has completed.
35 RESET Input Reset (RESET)—This input is a direct hardware reset on the
processor. When RESET is asserted low, the device is initialized
and placed in the Reset state. A Schmitt trigger input is used for
noise immunity. When the RESET pin is deasserted, the initial chip
operating mode is latched from the MODA, MODB, and MODC
pins.
To ensure complete hardware reset, RESET and TRST should be
asserted together. The only exception occurs in a debugging
environment when a hardware reset is required and it is necessary
not to reset the JTAG/Enhanced OnCE module. In this case, assert
RESET, but do not assert TRST.
34 RSTO Output Reset Output (RSTO)—This output is asserted on any reset
condition (external reset, low voltage, software or COP).
65 RXD0
GPIOE0
Input
Input/Output
Serial Receive Data 0 (RXD0)—This input receives byte-oriented
serial data and transfers it to the SCI 0 receive shift register.
Port E GPIO (0)—This pin is a General Purpose I/O (GPIO) pin that
can individually be programmed as input or output pin.
66 TXD0
GPIOE1
Output(Z)
Input/Output
Serial Transmit Data 0 (TXD0)—This signal transmits data from
the SCI 0 transmit data register.
Port E GPIO (1)—This pin is a General Purpose I/O (GPIO) pin that
can individually be programmed as input or output pin.
94 RXD1
GPIOE2
Input
Input/Output
Serial Receive Data 1 (RXD1)—This input receives byte-oriented
serial data and transfers it to the SCI 1 receive shift register.
Port E GPIO (2)—This pin is a General Purpose I/O (GPIO) pin that
can individually be programmed as input or output pin.
Table 3-1. 56854 Signal and Package Information for the 128-pin LQFP (Continued)
Pin No. Signal Name Type Description
Introduction
56854 Technical Data, Rev. 6
Freescale Semiconductor 19
95 TXD1
GPIOE3
Output(Z)
Input/Output
Serial Transmit Data 1 (TXD1)—This signal transmits data from
the SCI 1 transmit data register.
Port E GPIO (3)—This pin is a General Purpose I/O (GPIO) pin that
can individually be programmed as input or output pin.
116 STD0
GPIOC0
Output
Input/Output
ESSI Transmit Data (STD0)—This output pin transmits serial data
from the ESSI Transmitter Shift Register.
Port C GPIO (0)—This pin is a General Purpose I/O (GPIO) pin
when the ESSI is not in use.
117 SRD0
GPIOC1
Input
Input/Output
ESSI Receive Data (SRD0)—This input pin receives serial data
and transfers the data to the ESSI Receive Shift Register.
Port C GPIO (1)—This pin is a General Purpose I/O (GPIO) pin
when the ESSI is not in use.
118 SCK0
GPIOC2
Input/Output
Input/Output
ESSI Serial Clock (SCK0)—This bidirectional pin provides the
serial bit rate clock for the transmit section of the ESSI. The clock
signal can be continuous or gated and can be used by both the
transmitter and receiver in synchronous mode.
Port C GPIO (2)—This pin is a General Purpose I/O (GPIO) pin
when the ESSI is not in use.
119 SC00
GPIOC3
Input/Output
Input/Output
ESSI Serial Control Pin 0 (SC00)—The function of this pin is
determined by the selection of either synchronous or asynchronous
mode. For asynchronous mode, this pin will be used for the receive
clock I/O. For synchronous mode, this pin is used either for
transmitter1 output or for serial I/O flag 0.
Port C GPIO (3)—This pin is a General Purpose I/O (GPIO) pin
when the ESSI is not in use.
120 SC01
GPIOC4
Input/Output
Input/Output
ESSI Serial Control Pin 1 (SC01)—The function of this pin is
determined by the selection of either synchronous or asynchronous
mode. For asynchronous mode, this pin is the receiver frame sync
I/O. For synchronous mode, this pin is used either for transmitter2
output or for serial I/O flag 1.
Port C GPIO (4)—This pin is a General Purpose I/O (GPIO) pin
when the ESSI is not in use.
Table 3-1. 56854 Signal and Package Information for the 128-pin LQFP (Continued)
Pin No. Signal Name Type Description
56854 Technical Data, Rev. 6
20 Freescale Semiconductor
121 SC02
GPIOC5
Input/Output
Input /Output
ESSI Serial Control Pin 2 (SC02)—This pin is used for frame sync
I/O. SC02 is the frame sync for both the transmitter and receiver in
synchronous mode and for the transmitter only in asynchronous
mode. When configured as an output, this pin is the internally
generated frame sync signal. When configured as an input, this pin
receives an external frame sync signal for the transmitter (and the
receiver in synchronous operation).
Port C GPIO (5)—This pin is a General Purpose I/O (GPIO) pin
when the ESSI is not in use.
1MISO
GPIOF0
Input/Output
Input/Output
SPI Master In/Slave Out (MISO)—This serial data pin is an input to
a master device and an output from a slave device. The MISO line
of a slave device is placed in the high-impedance state if the slave
device is not selected. The driver on this pin can be configured as
an open-drain driver by the SPI’s Wired-OR mode (WOM) bit when
this pin is configured for SPI operation.
Port F GPIO (0)—This pin is a General Purpose I/O (GPIO) pin that
can be individually programmed as input or output pin.
2MOSI
GPIOF1
Input/Output (Z)
Input/Output
SPI Master Out/Slave In (MOSI)—This serial data pin is an output
from a master device and an input to a slave device. The master
device places data on the MOSI line a half-cycle before the clock
edge that the slave device uses to latch the data. The driver on this
pin can be configured as an open-drain driver by the SPI’s WOM bit
when this pin is configured for SPI operation.
Port F GPIO (1)—This pin is a General Purpose I/O (GPIO) pin that
can individually be programmed as input or output pin.
3SCK
GPIOF2
Input/Output
Input/Output
SPI Serial Clock (SCK)—This bidirectional pin provides a serial bit
rate clock for the SPI. This gated clock signal is an input to a slave
device and is generated as an output by a master device. Slave
devices ignore the SCK signal unless the SS pin is active low. In
both master and slave SPI devices, data is shifted on one edge of
the SCK signal and is sampled on the opposite edge, where data is
stable. The driver on this pin can be configured as an open-drain
driver by the SPI’s WOM bit when this pin is configured for SPI
operation. When using Wired-OR mode, the user must provide an
external pull-up device.
Port F GPIO (2)—This pin is a General Purpose I/O (GPIO) pin that
can be individually programmed as input or output pin.
Table 3-1. 56854 Signal and Package Information for the 128-pin LQFP (Continued)
Pin No. Signal Name Type Description
Introduction
56854 Technical Data, Rev. 6
Freescale Semiconductor 21
4SS
GPIOF3
Input
Input/Output
SPI Slave Select (SS)—This input pin selects a slave device before
a master device can exchange data with the slave device. SS must
be low before data transactions and must stay low for the duration
of the transaction. The SS line of the master must be held high.
Port F GPIO (3)—This pin is a General Purpose I/O (GPIO) pin that
can individually be programmed as input or output pin.
24 XTAL Input/Output Crystal Oscillator Output (XTAL)—This output connects the
internal crystal oscillator output to an external crystal. If an external
clock source other than a crystal oscillator is used, XTAL must be
used as the input.
25 EXTAL Input External Crystal Oscillator Input (EXTAL)—This input should be
connected to an external crystal. If an external clock source other
than a crystal oscillator is used, EXTAL must be tied off. See
Section 4.5.2
33 CLKO Output Clock Output (CLKO)—This pin outputs a buffered clock signal.
When enabled, this signal is the system clock divided by four.
54 TCK Input Test Clock Input (TCK)—This input pin provides a gated clock to
synchronize the test logic and to shift serial data to the
JTAG/Enhanced OnCE port. The pin is connected internally to a
pull-down resistor.
52 TDI Input Test Data Input (TDI)—This input pin provides a serial input data
stream to the JTAG/Enhanced OnCE port. It is sampled on the
rising edge of TCK and has an on-chip pull-up resistor.
51 TDO Output (Z) Test Data Output (TDO)—This tri-statable output pin provides a
serial output data stream from the JTAG/Enhanced OnCE port. It is
driven in the Shift-IR and Shift-DR controller states, and changes on
the falling edge of TCK.
53 TMS Input Test Mode Select Input (TMS)—This input pin is used to sequence
the JTAG TAP controller’s state machine. It is sampled on the rising
edge of TCK and has an on-chip pull-up resistor.
Note: Always tie the TMS pin to VDD through a 2.2K resistor.
Table 3-1. 56854 Signal and Package Information for the 128-pin LQFP (Continued)
Pin No. Signal Name Type Description
56854 Technical Data, Rev. 6
22 Freescale Semiconductor
50 TRST Input Test Reset (TRST)—As an input, a low signal on this pin provides a
reset signal to the JTAG TAP controller. To ensure complete
hardware reset, TRST should be asserted whenever RESET is
asserted. The only exception occurs in a debugging environment,
since the Enhanced OnCE/JTAG module is under the control of the
debugger. In this case it is not necessary to assert TRST when
asserting RESET . Outside of a debugging environment RESET
should be permanently asserted by grounding the signal, thus
disabling the Enhanced OnCE/JTAG module on the device.
Note: For normal operation, connect TRST directly to VSS. If the
design is to be used in a debugging environment, TRST may be tied to VSS
through a 1K resistor.
49 DE Input/Output Debug Event (DE)—This is an open-drain, bidirectional, active low
signal. As an input, it is a means of entering debug mode of
operation from an external command controller. As an output, it is a
means of acknowledging that the chip has entered debug mode.
This pin is connected internally to a weak pull-up resistor.
Table 3-1. 56854 Signal and Package Information for the 128-pin LQFP (Continued)
Pin No. Signal Name Type Description
General Characteristics
56854 Technical Data, Rev. 6
Freescale Semiconductor 23
Part 4 Specifications
4.1 General Characteristics
The 56854 is fabricated in high-density CMOS with 5-volt tolerant TTL-compatible digital inputs. The
term “5-volt tolerant” refers to the capability of an I/O pin, built on a 3.3V compatible process
technology, to withstand a voltage up to 5.5V without damaging the device. Many systems have a
mixture of devices designed for 3.3V and 5V power supplies. In such systems, a bus may carry both 3.3V
and 5V- compatible I/O voltage levels (a standard 3.3V I/O is designed to receive a maximum voltage of
3.3V ± 10% during normal operation without causing damage). This 5V tolerant capability therefore
offers the power savings of 3.3V I/O levels while being able to receive 5V levels without being damaged.
Absolute maximum ratings given in Table 4-1 are stress ratings only, and functional operation at the
maximum is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent
damage to the device.
The 56854 DC/AC electrical specifications are preliminary and are from design simulations. These
specifications may not be fully tested or guaranteed at this early stage of the product life cycle. Finalized
specifications will be published after complete characterization and device qualifications have been
completed.
CAUTION
This device contains protective circuitry to guard
against damage due to high static voltage or
electrical fields. However, normal precautions are
advised to avoid application of any voltages higher
than maximum rated voltages to this high-impedance
circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate voltage level.
56854 Technical Data, Rev. 6
24 Freescale Semiconductor
Table 4-1 Absolute Maximum Ratings
Characteristic Symbol Min Max Unit
Supply voltage, core VDD1
1. VDD must not exceed VDDIO
VSS – 0.3 VSS + 2.0 V
Supply voltage, IO
Supply voltage, analog
VDDIO2
VDDIO2
2. VDDIO and VDDA must not differ by more that 0.5V
VSSIO – 0.3
VSSA – 0.3
VSSIO + 4.0
VDDA + 4.0
V
Digital input voltages
Analog input voltages (XTAL, EXTAL)
VIN
VINA
VSSIO – 0.3
VSSA – 0.3
VSSIO + 5.5
VDDA + 0.3
V
Current drain per pin excluding VDD, GND I — 8 mA
Junction temperature TJ-40 120 °C
Storage temperature range TSTG -55 150 °C
Table 4-2 Recommended Operating Conditions
Characteristic Symbol Min Max Unit
Supply voltage for Logic Power VDD 1.62 1.98 V
Supply voltage for I/O Power VDDIO 3.0 3.6 V
Supply voltage for Analog Power VDDA 3.0 3.6 V
Ambient operating temperature TA-40 85 °C
PLL clock frequency1
1. Assumes clock source is direct clock to EXTAL or crystal oscillator running 2-4MHz. PLL must be enabled, locked, and
selected. The actual frequency depends on the source clock frequency and programming of the CGM module.
fpll —240 MHz
Operating Frequency2
2. Master clock is derived from on of the following four sources:
fclk = fxtal when the source clock is the direct clock to EXTAL
fclk = fpll when PLL is selected
fclk = fosc when the source clock is the crystal oscillator and PLL is not selected
fclk = fextal when the source clock is the direct clock to EXTAL and PLL is not selected
fop —120 MHz
Frequency of peripheral bus fipb —60 MHz
Frequency of external clock fclk —240 MHz
Frequency of oscillator fosc 2 4 MHz
Frequency of clock via XTAL fxtal —240 MHz
Frequency of clock via EXTAL fextal 2 4 MHz
DC Electrical Characteristics
56854 Technical Data, Rev. 6
Freescale Semiconductor 25
4.2 DC Electrical Characteristics
Table 4-3 Thermal Characteristics1
1. See Section 6.1 for more detail.
Characteristic
128-pin LQFP
Symbol Value Unit
Thermal resistance junction-to-ambient
(estimated)
θJA 43.1 °C/W
I/O pin power dissipation PI/O User Determined W
Power dissipation PDPD = (IDD × VDD) + PI/O W
Maximum allowed PDPDMAX (TJ – TA) / RθJA 2
2. TJ = Junction Temperature
TA = Ambient Temperature
W
Table 4-4 DC Electrical Characteristics
Operating Conditions: V
SS
= V
SSIO
= V
SSA
= 0 V, V
DD
= 1.62-1.98V, V
DDIO
= V
DDA
= 3.0–3.6V, T
A
= –40
°
to +120
°
C, C
L
≤
50pF, f
op
= 120MHz
Characteristic Symbol Min Typ Max Unit
Input high voltage (XTAL/EXTAL) VIHC VDDA – 0.8 VDDA VDDA + 0.3 V
Input low voltage (XTAL/EXTAL) VILC -0.3 —0.5 V
Input high voltage VIH 2.0 —5.5 V
Input low voltage VIL -0.3 —0.8 V
Input current low (pullups disabled) IIL -1 — 1 μA
Input current high (pullups disabled) IIH -1 — 1 μA
Output tri-state current low IOZL -10 —10 μA
Output tri-state current high IOZH -10 —10 μA
Output High Voltage VOH VDDIO – 0.7 — — V
Output Low Voltage VOL — — 0.4 V
Output High Current IOH 8 — 16 mA
Output Low Current IOL 8 — 16 mA
Input capacitance CIN — 8 — pF
Output capacitance COUT —12 —pF
56854 Technical Data, Rev. 6
26 Freescale Semiconductor
VDD supply current (Core logic, memories, peripherals)
Run 1
Deep Stop2
Light Stop3
IDD4
—
—
—
70
0.05
5
110
10
14
mA
mA
mA
VDDIO supply current (I/O circuity)
Run5
Deep Stop2
IDDIO
—40
0
50
1.5
mA
mA
VDDA supply current (analog circuity)
Deep Stop2
IDDA
—60 120 μA
Low Voltage Interrupt6VEI —2.5 2.85 V
Low Voltage Interrupt Recovery Hysteresis VEIH —50 —mV
Power on Reset7POR —1.5 2.0 V
Note: Run (operating) IDD measured using external square wave clock source (fosc = 4MHz) into XTAL. All inputs 0.2V from rail;
no DC loads; outputs unloaded. All ports configured as inputs; measured with all modules enabled. PLL set to 240MHz out.
1. Running Core, performing 50% NOP and 50% FIR. Clock at 120 MHz.
2. Deep Stop Mode - Operation frequency = 4 MHz, PLL set to 4 MHz, crystal oscillator and time of day module operating.
3. Light Stop Mode - Operation frequency = 120 MHz, PLL set to 240 MHz, crystal oscillator and time of day module operating.
4. IDD includes current for core logic, internal memories, and all internal peripheral logic circuitry.
5. Running core and performing external memory access. Clock at 120 MHz.
6. When VDD drops below VEI max value, an interrupt is generated.
7. Power-on reset occurs whenever the digital supply drops below 1.8V. While power is ramping up, this signal remains active
for as long as the internal 2.5V is below 1.8V no matter how long the ramp up rate is. The internally regulated voltage is typically
100 mV less than VDD during ramp up until 2.5V is reached, at which time it self-regulates.
Table 4-4 DC Electrical Characteristics (Continued)
Operating Conditions: V
SS
= V
SSIO
= V
SSA
= 0 V, V
DD
= 1.62-1.98V, V
DDIO
= V
DDA
= 3.0–3.6V, T
A
= –40
°
to +120
°
C, C
L
≤
50pF, f
op
= 120MHz
Characteristic Symbol Min Typ Max Unit
56854 Technical Data, Rev. 6
28 Freescale Semiconductor
4.3 Supply Voltage Sequencing and Separation Cautions
Figure 4-2 shows two situations to avoid in sequencing the VDD and VDDIO, VDDA supplies.
Notes: 1. VDD rising before VDDIO, VDDA
2. VDDIO, VDDA rising much faster than VDD
Figure 4-2 Supply Voltage Sequencing and Separation Cautions
VDD should not be allowed to rise early (1). This is usually avoided by running the regulator for the VDD
supply (1.8V) from the voltage generated by the 3.3V VDDIO supply, see Figure 4-3. This keeps VDD from
rising faster than VDDIO.
VDD should not rise so late that a large voltage difference is allowed between the two supplies (2).
Typically this situation is avoided by using external discrete diodes in series between supplies, as shown
in Figure 4-3. The series diodes forward bias when the difference between VDDIO and VDD reaches
approximately 2.1, causing VDD to rise as VDDIO ramps up. When the VDD regulator begins proper
operation, the difference between supplies will typically be 0.8V and conduction through the diode chain
reduces to essentially leakage current. During supply sequencing, the following general relationship
should be adhered to:
VDDIO > VDD > (VDDIO - 2.1V)
In practice, VDDA is typically connected directly to VDDIO with some filtering.
3.3V
1.8V
Time
0
2
1
Supplies Stable
VDD
VDDIO, VDDA
DC Power Supply Voltage
AC Electrical Characteristics
56854 Technical Data, Rev. 6
Freescale Semiconductor 29
Figure 4-3 Example Circuit to Control Supply Sequencing
4.4 AC Electrical Characteristics
Timing waveforms in Section 4.2 are tested with a VIL maximum of 0.8 V and a VIH minimum of 2.0 V
for all pins except XTAL, which is tested using the input levels in Section 4.2. In Figure 4-4 the levels of
VIH and VIL for an input signal are shown.
Figure 4-4 Input Signal Measurement References
Figure 4-5 shows the definitions of the following signal states:
• Active state, when a bus or signal is driven, and enters a low impedance state.
• Tri-stated, when a bus or signal is placed in a high impedance state.
• Data Valid state, when a signal level has reached VOL or VOH.
• Data Invalid state, when a signal level is in transition between VOL and VOH.
Figure 4-5 Signal States
3.3V
Regulator
1.8V
Regulator
Supply
V
DD
V
DDIO,
V
DDA
VIH
VIL
Fall Time
Input Signal
Note: The midpoint is VIL + (VIH – VIL)/2.
Midpoint1
Low High
90%
50%
10%
Rise Time
Data Invalid State
Data1
Data2 Valid
Data
Tri-stated
Data3 Valid
Data2 Data3
Data1 Valid
Data Active Data Active
56854 Technical Data, Rev. 6
30 Freescale Semiconductor
4.5 External Clock Operation
The 56854 system clock can be derived from a crystal or an external system clock signal. To generate a
reference frequency using the internal oscillator, a reference crystal must be connected between the
EXTAL and XTAL pins.
4.5.1 Crystal Oscillator
The internal oscillator is designed to interface with a parallel-resonant crystal resonator in the frequency
range specified for the external crystal in Table 4-6. In Figure 4-6 a typical crystal oscillator circuit is
shown. Follow the crystal supplier’s recommendations when selecting a crystal, because crystal
parameters determine the component values required to provide maximum stability and reliable start-up.
The crystal and associated components should be mounted as close as possible to the EXTAL and XTAL
pins to minimize output distortion and start-up stabilization time.
Figure 4-6 Crystal Oscillator
4.5.2 High Speed External Clock Source (> 4MHz)
The recommended method of connecting an external clock is given in Figure 4-7. The external clock
source is connected to XTAL and the EXTAL pin is held at ground, VDDA, or VDDA/2. The TOD_SEL
bit in CGM must be set to 0.
Figure 4-7 Connecting a High Speed External Clock Signal using XTAL
Sample External Crystal Parameters:
Rz = 10MΩ
TOD_SEL bit in CGM must be set to 0
Crystal Frequency = 2–4 MHz (optimized for 4MHz)
EXTAL XTAL
Rz
56854
XTAL EXTAL
External GND,VDDA,
Clock
(up to 240MHz) or VDDA/2
External Clock Operation
56854 Technical Data, Rev. 6
Freescale Semiconductor 31
4.5.3 Low Speed External Clock Source (2-4MHz)
The recommended method of connecting an external clock is given in Figure 4-8. The external clock
source is connected to XTAL and the EXTAL pin is held at VDDA/2. The TOD_SEL bit in CGM must be
set to 0.
Figure 4-8 Connecting a Low Speed External Clock Signal using XTAL
I
Figure 4-9 External Clock Timing
Table 4-5 External Clock Operation Timing Requirements4
Operating Conditions: V
SS
= V
SSIO
= V
SSA
= 0 V, V
DD
= 1.62-1.98V, V
DDIO
= V
DDA
= 3.0–3.6V, T
A
= –40
°
to +120
°
C, C
L
≤
50pF, f
op
= 120MHz
Characteristic Symbol Min Typ Max Unit
Frequency of operation (external clock driver)1
1. See Figure 4-7 for details on using the recommended connection of an external clock driver.
fosc 0 — 240 MHz
Clock Pulse Width4tPW 6.25 — — ns
External clock input rise time2, 4
2. External clock input rise time is measured from 10% to 90%.
trise — — TBD ns
External clock input fall time3, 4
3. External clock input fall time is measured from 90% to 10%.
4. Parameters listed are guaranteed by design.
tfall — — TBD ns
56854
XTAL EXTAL
External
Clock
(2-4MHz)
VDDA/2
External
Clock
VIH
VIL
Note: The midpoint is VIL + (VIH – VIL)/2.
90%
50%
10%
90%
50%
10% tPW tPW
tfall trise
56854 Technical Data, Rev. 6
32 Freescale Semiconductor
4.6 External Memory Interface Timing
The External Memory Interface is designed to access static memory and peripheral devices. Figure 4-10 shows
sample timing and parameters that are detailed in Table 4-11.
The timing of each parameter consists of both a fixed delay portion and a clock related portion; as well as user
controlled wait states. The equation:
t = D + P * (M + W)
should be used to determine the actual time of each parameter. The terms in the above equation are defined as:
t parameter delay time
D fixed portion of the delay, due to on-chip path delays.
P the period of the system clock, which determines the execution rate of the part (i.e. when the device is
operating at 120 MHz, P = 8.33 ns).
M Fixed portion of a clock period inherent in the design. This number is adjusted to account for possible
clock duty cycle derating.
W the sum of the applicable wait state controls. See the “Wait State Controls” column of Table 4-11 for
the applicable controls for each parameter. See the EMI chapter of the 83x Peripheral Manual for
details of what each wait state field controls.
Some of the parameters contain two sets of numbers. These parameters have two different paths and clock edges
that must be considered. Check both sets of numbers and use the smaller result. The appropriate entry may change
if the operating frequency of the part changes.
The timing of write cycles is different when WWS = 0 than when WWS > 0. Therefore, some parameters contain
two sets of numbers to account for this difference. The “Wait States Configuration” column of Table 4-11 should
be used to make the appropriate selection.
Table 4-6 PLL Timing
Operating Conditions: V
SS
= V
SSIO
= V
SSA
= 0 V, V
DD
= 1.62-1.98V, V
DDIO
= V
DDA
= 3.0–3.6V, T
A
= –40
°
to +120
°
C, C
L
≤
50pF, f
op
= 120MHz
Characteristic Symbol Min Typ Max Unit
External reference crystal frequency for the PLL1
1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work correctly.
The PLL is optimized for 4MHz input crystal.
fosc 2 4 4 MHz
PLL output frequency fclk 40 —240 MHz
PLL stabilization time 2
2. This is the minimum time required after the PLL setup is changed to ensure reliable operation.
tplls — 1 10 ms
External Memory Interface Timing
56854 Technical Data, Rev. 6
Freescale Semiconductor 33
Figure 4-10 External Memory Interface Timing
Figure 4-11 External Memory Interface Timing
Operating Conditions: V
SS
= V
SSIO
= V
SSA
= 0 V, V
DD
= 1.62-1.98 V, V
DDIO
= V
DDA
= 3.0–3.6V, T
A
= –40
°
to +120
°
C, C
L
< 50pF, P = 8.333ns
Characteristic Symbol Wait States
Configuration D M Wait States
Controls Unit
Address Valid to WR Asserted tAWR
WWS=0 -0.79 0.50 WWSS ns
WWS>0 -1.98 0.69
WR Width Asserted to WR
Deasserted tWR
WWS=0 -0.86 0.19 WWS ns
WWS>0 -0.01 0.00
Data Out Valid to WR Asserted
tDWR
WWS=0 -1.52 0.00
WWSS ns
WWS=0 - 5.69 0.25
WWS>0 -2.10 0.19
WWS>0 -4.66 0.50
Valid Data Out Hold Time after WR
Deasserted tDOH -1.47 0.25 WWSH ns
Valid Data Out Set Up Time to WR
Deasserted tDOS
-2.36 0.19 WWS,WWSS ns
-4.67 0.50
Valid Address after WR
Deasserted
tWAC -1.60 0.25 WWSH
tDRD
tRDD
tAD
tDOH
tDOS
tDWR
tRDWR
tWAC
tWRRD
tWR
tAWR
tWRWR
tARDD
tRDA
tRDRD
tRD
tARDA
Data Out Data In
A0-Axx,CS
RD
WR
D0-D15
Note: During read-modify-write instructions and internal instructions, the address lines do not change state.
56854 Technical Data, Rev. 6
34 Freescale Semiconductor
4.7 Reset, Stop, Wait, Mode Select, and Interrupt Timing
RD Deasserted to Address Invalid tRDA - 0.44 0.00 RWSH ns
Address Valid to RD Deasserted tARDD -2.07 1.00 RWSS,RWS ns
Valid Input Data Hold after RD
Deasserted tDRD 0.00 N/A1—ns
RD Assertion Width tRD -1.34 1.00 RWS ns
Address Valid to Input Data Valid tAD
-10.27 1.00
RWSS,RWS ns
-13.5 1.19
Address Valid to RD Asserted tARDA - 0.94 0.00 RWSS ns
RD Asserted to Input Data Valid tRDD
-9.53 1.00
RWSS,RWS ns
-12.64 1.19
WR Deasserted to RD Asserted tWRRD -0.75 0.25 WWSH,RWSS ns
RD Deasserted to RD Asserted tRDRD -0.1620.00 RWSS,RWSH ns
WR Deasserted to WR Asserted tWRWR
WWS=0 -0.44 0.75 WWSS, WWSH ns
WWS>0 -0.11 1.00
RD Deasserted to WR Asserted tRDWR
0.14 0.50 MDAR, BMDAR,
RWSH, WWSS ns
-0.57 0.69
1. N/A since device captures data before it deasserts RD
2. If RWSS = RWSH = 0, RD does not deassert during back-to-back reads and D=0.00 should be used.
Table 4-7 Reset, Stop, Wait, Mode Select, and Interrupt Timing1, 2
Operating Conditions: V
SS
= V
SSIO
= V
SSA
= 0 V, V
DD
= 1.62-1.98V, V
DDIO
= V
DDA
= 3.0–3.6V, T
A
= –40
°
to +120
°
C, C
L
≤
50pF, f
op
= 120MHz
Characteristic Symbol Min Max Unit See Figure
RESET Assertion to Address, Data and Control
Signals High Impedance tRAZ —11 ns 4-12
Minimum RESET Assertion Duration3 tRA 30 —ns 4-12
RESET Deassertion to First External Address Output tRDA —120T ns 4-12
Edge-sensitive Interrupt Request Width tIRW 1T + 3 —ns 4-13
Figure 4-11 External Memory Interface Timing (Continued)
Operating Conditions: V
SS
= V
SSIO
= V
SSA
= 0 V, V
DD
= 1.62-1.98 V, V
DDIO
= V
DDA
= 3.0–3.6V, T
A
= –40
°
to +120
°
C, C
L
< 50pF, P = 8.333ns
Characteristic Symbol Wait States
Configuration DM
Wait States
Controls Unit
Reset, Stop, Wait, Mode Select, and Interrupt Timing
56854 Technical Data, Rev. 6
Freescale Semiconductor 35
IRQA, IRQB Assertion to External Data Memory
Access Out Valid, caused by first instruction execution
in the interrupt service routine
tIDM 18T —ns 4-14
tIDM -FAST 14T —
IRQA, IRQB Assertion to General Purpose Output
Valid, caused by first instruction execution in the
interrupt service routine
tIG 18T —ns 4-14
tIG -FAST 14T —
IRQA Low to First Valid Interrupt Vector Address Out
recovery from Wait State4
tIRI 22T —ns 4-15
tIRI -FAST 18T —
Delay from IRQA Assertion (exiting Stop) to External
Data Memory5
tIW 1.5T —ns 4-16
Delay from IRQA Assertion (exiting Wait) to External
Data Memory
Fast6
Normal7
tIF
18T
22ET —
—
ns
ns
4-16
RSTO pulse width8
normal operation
internal reset mode
tRSTO
128ET
8ET
—
—
—
—
4-17
1. In the formulas, T = clock cycle. For fop = 120MHz operation and fipb = 60MHz, T = 8.33ns.
2. Parameters listed are guaranteed by design.
3. At reset, the PLL is disabled and bypassed. The part is then put into Run mode and tclk assumes the period of the source
clock, txtal, textal or tosc.
4. The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state. This is
not the minimum required so that the IRQA interrupt is accepted.
5. The interrupt instruction fetch is visible on the pins only in Mode 3.
6. Fast stop mode:
Fast stop recovery applies when external clocking is in use (direct clocking to XTAL) or when fast stop mode recovery is
requested (OMR bit 6 is set to 1). In both cases the PLL and the master clock are unaffected by stop mode entry. Recovery takes
one less cycle and tclk will continue same value it had before stop mode was entered.
7. Normal stop mode:
As a power saving feature, normal stop mode disables and bypasses the PLL. Stop mode will then shut down the master
clock, recovery will take an extra cycle (to restart the clock), and tclk will resume at the input clock source rate.
8. ET = External Clock period, For an external crystal frequency of 8MHz, ET=125 ns.
Table 4-7 Reset, Stop, Wait, Mode Select, and Interrupt Timing1, 2
Operating Conditions: V
SS
= V
SSIO
= V
SSA
= 0 V, V
DD
= 1.62-1.98V, V
DDIO
= V
DDA
= 3.0–3.6V, T
A
= –40
°
to +120
°
C, C
L
≤
50pF, f
op
= 120MHz
Characteristic Symbol Min Max Unit See Figure
56854 Technical Data, Rev. 6
36 Freescale Semiconductor
Figure 4-12 Asynchronous Reset Timing
Figure 4-13 External Interrupt Timing (Negative-Edge-Sensitive)
First Fetch
A0–A20,
D0–D15
CS,
RD, WR
RESET
First Fetch
tRDA
tRA
tRAZ
IRQA
IRQB tIRW
Reset, Stop, Wait, Mode Select, and Interrupt Timing
56854 Technical Data, Rev. 6
Freescale Semiconductor 37
Figure 4-14 External Level-Sensitive Interrupt Timing
Figure 4-15 Interrupt from Wait State Timing
Figure 4-16 Recovery from Stop State Using Asynchronous Interrupt Timing
A0–A20,
CS,
RD, WR
IRQA,
IRQB
First Interrupt Instruction Execution
a) First Interrupt Instruction Execution
Purpose
I/O Pin
IRQA,
IRQB
b) General Purpose I/O
tIG
tIDM
General
Instruction Fetch
IRQA,
IRQB
First Interrupt Vector
A0–A20,
CS,
RD, WR
tIRI
Not IRQA Interrupt Vector
IRQA
A0–A20,
CS,
RD, WR
First Instruction Fetch
tIW
tIF
56854 Technical Data, Rev. 6
38 Freescale Semiconductor
Figure 4-17 Reset Output Timing
4.8 Host Interface Port
Table 4-8 Host Interface Port Timing1
Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz
1. The formulas: T = clock cycle. f ipb = 60MHz, T = 16.7ns.
Characteristic Symbol Min Max Unit See Figure
Access time TACKDV —13 ns 4-18
Disable time TACKDZ 3 — ns 4-18
Time to disassert TACKREQH 3.5 9ns 4-18
4-21
Lead time TREQACKL 0 — ns 4-18
4-21
Access time TRADV —13 ns 4-19
4-20
Disable time TRADX 5 — ns 4-19
4-20
Disable time TRADZ 3 — ns 4-19
4-20
Setup time TDACKS 3 — ns 4-21
Hold time TACKDH 1 — ns 4-21
Setup time TADSS 3 — ns 4-22
4-23
Hold time TDSAH 1 — ns 4-22
4-23
Pulse width TWDS 5 — ns 4-22
4-23
Time to re-assert
1. After second write in 16-bit mode
2. After first write in 16-bit mode
or after write in 8-bit mode
TACKREQL 4T + 5
5
5T + 9
13
ns
ns
4-18
4-21
RESET
tRSTO
Host Interface Port
56854 Technical Data, Rev. 6
Freescale Semiconductor 39
Figure 4-18 Controller-to-Host DMA Read Mode
Figure 4-19 Single Strobe Read Mode
Figure 4-20 Dual Strobe Read Mode
HACK
HD
HREQ
TACKDV
TACKDZ
TREQACKL TACKREQL
TACKREQH
TRADV
TRADZ
TRADX
HA
HCS
HDS
HD
HRW
TRADV
TRADZ
TRADX
HA
HCS
HWR
HD
HRD
56854 Technical Data, Rev. 6
40 Freescale Semiconductor
Figure 4-21 Host-to-Controller DMA Write Mode
Figure 4-22 Single Strobe Write Mode
Figure 4-23 Dual Strobe Write Mode
HACK
HREQ
HD
TDACKS TACKDH
TREQACKL TACKREQL
TACKREQH
HA
HCS
HDS
HD
HRW
TADSS
TADSS TDSAH
TDSAH
TWDS
TDSAH
HA
HCS
HWR
HD
HRD
TWDS
TADSS
TADSS
TDSAH
Serial Peripheral Interface (SPI) Timing
56854 Technical Data, Rev. 6
Freescale Semiconductor 41
4.9 Serial Peripheral Interface (SPI) Timing
Table 4-9 SPI Timing 1
Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz
1. Parameters listed are guaranteed by design.
Characteristic Symbol Min Max Unit See Figure
Cycle time
Master
Slave
tC
25
25
—
—
ns
ns
4-24, 4-25, 4-26,
4-27
Enable lead time
Master
Slave
tELD
—
12.5
—
—
ns
ns
4-27
Enable lag time
Master
Slave
tELG
—
12.5
—
—
ns
ns
4-27
Clock (SCLK) high time
Master
Slave
tCH
9
12.5
—
—
ns
ns
4-24, 4-25, 4-26,
4-27
Clock (SCLK) low time
Master
Slave
tCL
12
12.5
—
—
ns
ns
4-27
Data set-up time required for inputs
Master
Slave
tDS
10
2
—
—
ns
ns
4-24, 4-25, 4-26,
4-27
Data hold time required for inputs
Master
Slave
tDH
0
2
—
—
ns
ns
4-24, 4-25, 4-26,
4-27
Access time (time to data active from high-impedance state)
Slave
tA
515
ns
ns
4-27
Disable time (hold time to high-impedance state)
Slave
tD
2 9
ns
ns
4-27
Data valid for outputs
Master
Slave (after enable edge)
tDV
—
—
2
14
ns
ns
4-24, 4-25, 4-26,
4-27
Data invalid
Master
Slave
tDI
0
0
—
—
ns
ns
4-24, 4-25, 4-26,
4-27
Rise time
Master
Slave
tR
—
—
11.5
10.0
ns
ns
4-24, 4-25, 4-26,
4-27
Fall time
Master
Slave
tF
—
—
9.7
9.0
ns
ns
4-24, 4-25, 4-26,
4-27
56854 Technical Data, Rev. 6
42 Freescale Semiconductor
Figure 4-24 SPI Master Timing (CPHA = 0)
Figure 4-25 SPI Master Timing (CPHA = 1)
SCLK (CPOL = 0)
(Output)
SCLK (CPOL = 1)
(Output)
MISO
(Input)
MOSI
(Output)
MSB in Bits 14–1 LSB in
Master MSB out Bits 14–1 Master LSB out
SS
(Input) SS is held High on master
tC
tR
tF
tCH
tCL
tF
tR
tCH
tCH
tDV
tDH
tDS
tDI tDI(ref)
tFtR
tCL
SCLK (CPOL = 0)
(Output)
SCLK (CPOL = 1)
(Output)
MISO
(Input)
MOSI
(Output)
MSB in Bits 14–1 LSB in
Master MSB out Bits 14– 1 Master LSB out
SS
(Input) SS is held High on master
tR
tF
tC
tCH
tCL
tCH
tCL
tF
tDS
tDH
tR
tDI
tDV(ref) tDV
tFtR
Serial Peripheral Interface (SPI) Timing
56854 Technical Data, Rev. 6
Freescale Semiconductor 43
Figure 4-26 SPI Slave Timing (CPHA = 0)
Figure 4-27 SPI Slave Timing (CPHA = 1)
SCLK (CPOL = 0)
(Input)
SCLK (CPOL = 1)
(Input)
MISO
(Output)
MOSI
(Input)
Slave MSB out Bits 14–1
MSB in Bits 14–1 LSB in
SS
(Input)
Slave LSB out
tDS
tCL
tCL
tDI tDI
tCH
tCH
tR
tR
tELG
tDH
tELD
tCtF
tF
tD
tA
tDV
SCLK (CPOL = 0)
(Input)
SCLK (CPOL = 1)
(Input)
MISO
(Output)
MOSI
(Input)
Slave MSB out Bits 14–1
MSB in Bits 14–1 LSB in
SS
(Input)
Slave LSB out
tELG
tDI
tDS
tDH
tELD
tC
tCL
tCH
tR
tF
tF
tCL
tCH
tDV
tA
tDV
tR
tD
56854 Technical Data, Rev. 6
44 Freescale Semiconductor
4.10 Quad Timer Timing
Figure 4-28 Timer Timing
4.11 Enhanced Synchronous Serial Interface (ESSI) Timing
Table 4-10 Quad Timer Timing1, 2
Operating Conditions: V
SS
= V
SSIO
= V
SSA
= 0 V, V
DD
= 1.62-1.98V, V
DDIO
= V
DDA
= 3.0–3.6V, T
A
= –40
°
to +120
°
C, C
L
≤
50pF, f
op
= 120MHz
1. In the formulas listed, T = clock cycle. For fop = 120MHz operation and fipb = 60MHz, T = 8.33ns.
2. Parameters listed are guaranteed by design.
Characteristic Symbol Min Max Unit
Timer input period PIN 2T + 3 —ns
Timer input high/low period PINHL 1T + 3 —ns
Timer output period POUT 2T - 3 —ns
Timer output high/low period POUTHL 1T - 3 —ns
Table 4-11 ESSI Master Mode1 Switching Characteristics
Operating Conditions: V
SS
= V
SSIO
= V
SSA
= 0 V, V
DD
= 1.62-1.98V, V
DDIO
= V
DDA
= 3.0–3.6V, T
A
= –40
°
to +120
°
C, C
L
≤
50pF, f
op
= 120MHz
Parameter Symbol Min Typ Max Units
SCK frequency fs — — 152MHz
SCK period3tSCKW 66.7 — — ns
SCK high time tSCKH 33.44— — ns
SCK low time tSCKL 33.44— — ns
Output clock rise/fall time — — 4 — ns
Delay from SCK high to SC2 (bl) high - Master5tTFSBHM -1.0 —1.0 ns
Timer Inputs
Timer Outputs
PINHL PINHL
PIN
POUTHL
POUTHL
POUT
Enhanced Synchronous Serial Interface (ESSI) Timing
56854 Technical Data, Rev. 6
Freescale Semiconductor 45
Delay from SCK high to SC2 (wl) high - Master5tTFSWHM -1.0 —1.0 ns
Delay from SC0 high to SC1 (bl) high - Master5tRFSBHM -1.0 —1.0 ns
Delay from SC0 high to SC1 (wl) high - Master5tRFSWHM -1.0 —1.0 ns
Delay from SCK high to SC2 (bl) low - Master5tTFSBLM -1.0 —1.0 ns
Delay from SCK high to SC2 (wl) low - Master5tTFSWLM -1.0 —1.0 ns
Delay from SC0 high to SC1 (bl) low - Master5tRFSBLM -1.0 —1.0 ns
Delay from SC0 high to SC1 (wl) low - Master5tRFSWLM -1.0 —1.0 ns
SCK high to STD enable from high impedance - Master tTXEM -0.1 — 2 ns
SCK high to STD valid - Master tTXVM -0.1 — 2 ns
SCK high to STD not valid - Master tTXNVM -0.1 — — ns
SCK high to STD high impedance - Master tTXHIM -4 — 0 ns
SRD Setup time before SC0 low - Master tSM 4 — — ns
SRD Hold time after SC0 low - Master tHM 4 — — ns
Synchronous Operation (in addition to standard internal clock parameters)
SRD Setup time before SCK low - Master tTSM 4 — — ns
SRD Hold time after SCK low - Master tTHM 4 — — ns
1. Master mode is internally generated clocks and frame syncs
2. Max clock frequency is IP_clk/4 = 60MHz / 4 = 15MHz for an 120MHz part.
3. All the timings for the ESSI are given for a non-inverted serial clock polarity (TSCKP=0 in SCR2 and RSCKP=0 in SCSR)
and a non-inverted frame sync (TFSI=0 in SCR2 and RFSI=0 in SCSR). If the polarity of the clock and/or the frame sync
have been inverted, all the timings remain valid by inverting the clock signal SCK/SC0 and/or the frame sync SC2/SC1 in
the tables and in the figures.
4. 50 percent duty cycle
5. bl = bit length; wl = word length
Table 4-11 ESSI Master Mode1 Switching Characteristics (Continued)
Operating Conditions: V
SS
= V
SSIO
= V
SSA
= 0 V, V
DD
= 1.62-1.98V, V
DDIO
= V
DDA
= 3.0–3.6V, T
A
= –40
°
to +120
°
C, C
L
≤
50pF, f
op
= 120MHz
Parameter Symbol Min Typ Max Units
56854 Technical Data, Rev. 6
46 Freescale Semiconductor
Figure 4-29 Master Mode Timing Diagram
Table 4-12 ESSI Slave Mode1 Switching Characteristics
Operating Conditions: V
SS
= V
SSIO
= V
SSA
= 0 V, V
DD
= 1.62-1.98V, V
DDIO
= V
DDA
= 3.0–3.6V, T
A
= –40
°
to +120
°
C, C
L
≤
50pF, f
op
= 120MHz
Parameter Symbol Min Typ Max Units
SCK frequency fs — — 152MHz
SCK period3tSCKW 66.7 — — ns
SCK high time tSCKH 33.44— — ns
SCK low time tSCKL 33.44— — ns
Output clock rise/fall time — — 4 — ns
Delay from SCK high to SC2 (bl) high - Slave5tTFSBHS -1 —29 ns
tTHM
tTSM
tHM
tSM
tRFSWLM
tRFSWHM
tRFBLM
tRFSBHM
tTXHIM
tTXNVM
tTXVM
tTXEM
tTFSWLM
tTFSWHM
tTFSBLM
tTFSBHM
tSCKL
tSCKW
tSCKH
First Bit Last Bit
SCK output
SC2 (bl) output
SC2 (wl) output
STD
SC0 output
SC1 (bl) output
SC1 (wl) output
SRD
Enhanced Synchronous Serial Interface (ESSI) Timing
56854 Technical Data, Rev. 6
Freescale Semiconductor 47
Delay from SCK high to SC2 (wl) high - Slave5tTFSWHS -1 —29 ns
Delay from SC0 high to SC1 (bl) high - Slave5tRFSBHS -1 —29 ns
Delay from SC0 high to SC1 (wl) high - Slave5tRFSWHS -1 —29 ns
Delay from SCK high to SC2 (bl) low - Slave5tTFSBLS -29 —29 ns
Delay from SCK high to SC2 (wl) low - Slave5tTFSWLS -29 —29 ns
Delay from SC0 high to SC1 (bl) low - Slave5tRFSBLS -29 —29 ns
Delay from SC0 high to SC1 (wl) low - Slave5tRFSWLS -29 —29 ns
SCK high to STD enable from high impedance - Slave tTXES — — 15 ns
SCK high to STD valid - Slave tTXVS 4 — 15 ns
SC2 high to STD enable from high impedance (first bit) - Slave tFTXES 4 — 15 ns
SC2 high to STD valid (first bit) - Slave tFTXVS 4 — 15 ns
SCK high to STD not valid - Slave tTXNVS 4 — 15 ns
SCK high to STD high impedance - Slave tTXHIS 4 — 15 ns
SRD Setup time before SC0 low - Slave tSS 4 — — ns
SRD Hold time after SC0 low - Slave tHS 4 — — ns
Synchronous Operation (in addition to standard external clock parameters)
SRD Setup time before SCK low - Slave tTSS 4 — — ns
SRD Hold time after SCK low - Slave tTHS 4 — — ns
1. Slave mode is externally generated clocks and frame syncs
2. Max clock frequency is IP_clk/4 = 60MHz / 4 = 15MHz for a 120MHz part.
3. All the timings for the ESSI are given for a non-inverted serial clock polarity (TSCKP=0 in SCR2 and RSCKP=0 in SCSR)
and a non-inverted frame sync (TFSI=0 in SCR2 and RFSI=0 in SCSR). If the polarity of the clock and/or the frame sync
have been inverted, all the timings remain valid by inverting the clock signal SCK/SC0 and/or the frame sync SC2/SC1 in
the tables and in the figures.
4. 50 percent duty cycle
5. bl = bit length; wl = word length
Table 4-12 ESSI Slave Mode1 Switching Characteristics (Continued)
Operating Conditions: V
SS
= V
SSIO
= V
SSA
= 0 V, V
DD
= 1.62-1.98V, V
DDIO
= V
DDA
= 3.0–3.6V, T
A
= –40
°
to +120
°
C, C
L
≤
50pF, f
op
= 120MHz
Parameter Symbol Min Typ Max Units
56854 Technical Data, Rev. 6
48 Freescale Semiconductor
Figure 4-30 Slave Mode Clock Timing
4.12 Serial Communication Interface (SCI) Timing
Table 4-13 SCI Timing4
Operating Conditions: V
SS
= V
SSIO
= V
SSA
= 0 V, V
DD
= 1.62-1.98V, V
DDIO
= V
DDA
= 3.0–3.6V, T
A
= –40
°
to +120
°
C, C
L
≤
50pF, f
op
= 120MHz
Characteristic Symbol Min Max Unit
Baud Rate1
1. fMAX is the frequency of operation of the system clock in MHz.
BR —(fMAX)/(32) Mbps
RXD2 Pulse Width
2. The RXD pin in SCI0 is named RXD0 and the RXD pin in SCI1 is named RXD1.
RXDPW 0.965/BR 1.04/BR ns
TXD3 Pulse Width
3. The TXD pin in SCI0 is named TXD0 and the TXD pin in SCI1 is named TXD1.
4. Parameters listed are guaranteed by design.
TXDPW 0.965/BR 1.04/BR ns
tTHS
tTSS
tHS
tSS
tRFSWLS
tRFSWHS
tRFBLS
tRFSBHS
tTXHIS
tTXNVS
tFTXVS
tTXVS
tFTXES
tTXES
tTFSWLS
tTFSWHS
tTFSBLS
tTFSBHS
tSCKL
tSCKW
tSCKH
First Bit Last Bit
SCK input
SC2 (bl) input
SC2 (wl) input
STD
SC0 input
SC1 (bl) input
SC1 (wl) input
SRD
JTAG Timing
56854 Technical Data, Rev. 6
Freescale Semiconductor 49
Figure 4-31 RXD Pulse Width
Figure 4-32 TXD Pulse Width
4.13 JTAG Timing
Table 4-14 JTAG Timing1, 3
Operating Conditions: V
SS
= V
SSIO
= V
SSA
= 0 V, V
DD
= 1.62-1.98V, V
DDIO
= V
DDA
= 3.0–3.6V, T
A
= –40
°
to +120
°
C, C
L
≤
50pF, f
op
= 120MHz
1. Timing is both wait state and frequency dependent. For the values listed, T = clock cycle. For 120MHz
operation, T = 8.33ns.
Characteristic Symbol Min Max Unit
TCK frequency of operation2
2. TCK frequency of operation must be less than 1/4 the processor rate.
3. Parameters listed are guaranteed by design.
fOP DC 30 MHz
TCK cycle time tCY 33.3 —ns
TCK clock pulse width tPW 16.6 —ns
TMS, TDI data setup time tDS 3 — ns
TMS, TDI data hold time tDH 3 — ns
TCK low to TDO data valid tDV —12 ns
TCK low to TDO tri-state tTS —10 ns
TRST assertion time tTRST 35 —ns
DE assertion time tDE 4T —ns
RXD
SCI receive
data pin
(Input) RXDPW
TXD
SCI receive
data pin
(Input) TXDPW
56854 Technical Data, Rev. 6
50 Freescale Semiconductor
Figure 4-33 Test Clock Input Timing Diagram
Figure 4-34 Test Access Port Timing Diagram
Figure 4-35 TRST Timing Diagram
Figure 4-36 Enhanced OnCE—Debug Event
TCK
(Input)
VM
VIL
VM = VIL + (VIH – VIL)/2
VM
VIH
tPW
tPW
tCY
Input Data Valid
Output Data Valid
TCK
(Input)
TDI
(Input)
TDO
(Output)
TDO
(Output)
TMS
tTS
tDV
tDS tDH
TRST
(Input) tTRST
DE
tDE
GPIO Timing
56854 Technical Data, Rev. 6
Freescale Semiconductor 51
4.14 GPIO Timing
Figure 4-37 GPIO Timing
Table 4-15 GPIO Timing1, 2
Operating Conditions: V
SS
= V
SSIO
= V
SSA
= 0 V, V
DD
= 1.62-1.98V, V
DDIO
= V
DDA
= 3.0–3.6V, T
A
= –40
°
to +120
°
C, C
L
≤
50pF, f
op
= 120MHz
1. In the formulas listed, T = clock cycle. For fop = 120MHz operation and fipb = 60MHz, T = 8.33ns
2. Parameters listed are guaranteed by design.
Characteristic Symbol Min Max Unit
GPIO input period PIN 2T + 3 —ns
GPIO input high/low period PINHL 1T + 3 —ns
GPIO output period POUT 2T - 3 —ns
GPIO output high/low period POUTHL 1T - 3 —ns
GPIO Inputs
GPIO Outputs
PINHL PINHL
PIN
POUTHL
POUTHL
POUT
56854 Technical Data, Rev. 6
52 Freescale Semiconductor
Part 5 Packaging
5.1 Package and Pin-Out Information 56854
This section contains package and pin-out information for the 128-pin LQFP configuration of the 56854.
Figure 5-1 Top View, 56854 128-pin LQFP Package
PIN 103
PIN 1 PIN 39
PIN 65
MOSI
SCK
SS
V
DDIO
V
SSIO
RD
WR
A1
A2
A3
V
DD
V
SS
MODA
MODB
MODC
V
DDIO
V
SSIO
IRQA
IRQB
V
DDA
V
SSA
XTAL
EXTAL
A4
ORIENTATION
MARK
RSTO
RESET
HD3
HD4
HD5
HD6
HD7
V
DDIO
V
SSIO
A8
A9
A10
A11
V
DD
V
SS
DE
TRST
TDO
TDI
TMS
TCK
V
DDIO
V
SSIO
A12
TXD1
RXD1
V
SSIO
V
DDIO
V
DDIO
D5
D4
D3
D2
D1
HRWB
HA2
HA1
HA0
V
SS
V
DD
V
DD
CS3
CS2
CS1
CS0
V
SSIO
D0
V
DDIO
A20
A13
A14
A15
V
DDIO
V
SS
V
DD
V
SS
TIO3
TIO2
TIO1
V
DDIO
TIO0
V
SSIO
HDS
HCS
HREQ
HACK
D6
D7
D8
D9
D10
V
DD
V
SS
V
DDIO
V
SSIO
STD0
SRD0
SCK0
SC00
SC01
SC02
D11
D12
V
DDIO
V
SSIO
D13
D14
D15
MISO
A5
A6
A7
HD0
HD1
HD2
A0
A19
A18
A17
A16
TXD0
RXD0
CLKO
V
SSIO
Package and Pin-Out Information 56854
56854 Technical Data, Rev. 6
Freescale Semiconductor 53
Table 5-1 56854 Pin Identification by Pin Number
Pin
No. Signal Name Pin
No. Signal Name Pin
No. Signal Name Pin
No. Signal Name
1MISO 33 CLKO 65 RXD0 97 TIO3
2MOSI 34 RSTO 66 TXDO 98 TIO2
3SCK 35 RESET 67 A16 99 TIO1
4SS 36 HD3 68 A17 100 VDDIO
5 VDDIO 37 HD4 69 A18 101 TIO0
6 VSSIO 38 HD5 70 A19 102 VSSIO
7RD 39 HD6 71 A20 103 HDS
8WR 40 HD7 72 VDDIO 104 HCS
9A0 41 VDDIO 73 D0 105 HREQ
10 A1 42 VSSIO 74 VSSIO 106 HACK
11 A2 43 A8 75 CS0 107 D6
12 A3 44 A9 76 CS1 108 D7
13 VDD 45 A10 77 CS2 109 D8
14 VSS 46 A11 78 CS3 110 D9
15 MODA 47 VDD 79 VDD 111 D10
16 MODB 48 VSS 80 VDD 112 VDD
17 MODC 49 DE 81 VSS 113 VSS
18 VDDIO 50 TRST 82 HA0 114 VDDIO
19 VSSIO 51 TDO 83 HA1 115 VSSIO
20 IRQA 52 TDI 84 HA2 116 STD0
21 IRQB 53 TMS 85 HRWB 117 SRD0
22 VDDA 54 TCK 86 D1 118 SCK0
23 VSSA 55 VDDIO 87 D2 119 SC00
24 XTAL 56 VSSIO 88 D3 120 SC01
25 EXTAL 57 A12 89 D4 121 SC02
26 A4 58 A13 90 D5 122 D11
56854 Technical Data, Rev. 6
54 Freescale Semiconductor
27 A5 59 A14 91 VDDIO 123 D12
28 A6 60 A15 92 VDDIO 124 VDDIO
29 A7 61 VDDIO 93 VSSIO 125 VSSIO
30 HD0 62 VSSIO 94 RXD1 126 D13
31 HD1 63 VSS 95 TXD1 127 D14
32 HD2 64 VDD 96 VSS 128 D15
Table 5-1 56854 Pin Identification by Pin Number (Continued)
Pin
No. Signal Name Pin
No. Signal Name Pin
No. Signal Name Pin
No. Signal Name
Package and Pin-Out Information 56854
56854 Technical Data, Rev. 6
Freescale Semiconductor 55
Figure 5-2 128-pin LQFP Mechanical Information
Please see www.freescale.com for the most current case outline.
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE H IS LOCATED AT BOTTOM OF LEAD
AND IS COINCIDENT WITH THE LEAD WHERE THE
LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF
THE PARTING LINE.
4. DATUMS A, B, AND D TO BE DETERMINED AT DATUM
PLANE H.
5. DIMENSIONS D AND E TO BE DETERMINED AT
SEATING PLANE C.
6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 PER
SIDE. DIMENSIONS D1 AND E1 DO INCLUDE MOLD
MISMATCH AND ARE DETERMINED AT DATUM
PLANE H.
7. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL NOT
CAUSE THE b DIMENSION TO EXCEED 0.35.
DIM MILLIMETERS
MIN MAX
A --- 1.60
A1 0.05 0.15
A2 1.35 1.45
b 0.17 0.27
b1 0.17 0.23
c 0.09 0.20
c1 0.09 0.16
D 22.00 BSC
D1 20.00BSC
e 0.50 BSC
E 16.00 BSC
E1 14.00 BSC
L 0.45 0.75
L1 1.00 REF
L2 0.50 REF
S 0.20 ---
R1 0.08 ---
R2 0.08 0.20
00o7o
01 0o---
02 11o13o
Case Outline - 1129-01
128
103
38
102 65
64
39
56854 Technical Data, Rev. 6
56 Freescale Semiconductor
Part 6 Design Considerations
6.1 Thermal Design Considerations
An estimation of the chip junction temperature, TJ, in °C can be obtained from the equation:
Equation 1: T
J = TA + (PD x RθJA)
Where:
TA = ambient temperature °C
RθJA = package junction-to-ambient thermal resistance °C/W
PD = power dissipation in package
Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and
a case-to-ambient thermal resistance:
Equation 2: R
θJA = RθJC + RθCA
Where:
RθJA = package junction-to-ambient thermal resistance °C/W
RθJC = package junction-to-case thermal resistance °C/W
RθCA = package case-to-ambient thermal resistance °C/W
RθJC is device-related and cannot be influenced by the user. The user controls the thermal environment to
change the case-to-ambient thermal resistance, RθCA. For example, the user can change the air flow around
the device, add a heat sink, change the mounting arrangement on the Printed Circuit Board (PCB), or
otherwise change the thermal dissipation capability of the area surrounding the device on the PCB. This
model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through
the case to the heat sink and out to the ambient environment. For ceramic packages, in situations where
the heat flow is split between a path to the case and an alternate path through the PCB, analysis of the
device thermal performance may need the additional modeling capability of a system level thermal
simulation tool.
The thermal performance of plastic packages is more dependent on the temperature of the PCB to which
the package is mounted. Again, if the estimations obtained from RθJA do not satisfactorily answer whether
the thermal performance is adequate, a system level model may be appropriate.
A complicating factor is the existence of three common definitions for determining the junction-to-case
thermal resistance in plastic packages:
• Measure the thermal resistance from the junction to the outside surface of the package (case) closest to the
chip mounting area when that surface has a proper heat sink. This is done to minimize temperature variation
across the surface.
• Measure the thermal resistance from the junction to where the leads are attached to the case. This definition
is approximately equal to a junction to board thermal resistance.
• Use the value obtained by the equation (TJ – TT)/PD where TT is the temperature of the package case
determined by a thermocouple.
Electrical Design Considerations
56854 Technical Data, Rev. 6
Freescale Semiconductor 57
As noted above, the junction-to-case thermal resistances quoted in this data sheet are determined using the
first definition. From a practical standpoint, that value is also suitable for determining the junction
temperature from a case thermocouple reading in forced convection environments. In natural convection,
using the junction-to-case thermal resistance to estimate junction temperature from a thermocouple
reading on the case of the package will estimate a junction temperature slightly hotter than actual. Hence,
the new thermal metric, Thermal Characterization Parameter, or ΨJT, has been defined to be (TJ – TT)/PD.
This value gives a better estimate of the junction temperature in natural convection when using the surface
temperature of the package. Remember that surface temperature readings of packages are subject to
significant errors caused by inadequate attachment of the sensor to the surface and to errors caused by heat
loss to the sensor. The recommended technique is to attach a 40-gauge thermocouple wire and bead to the
top center of the package with thermally conductive epoxy.
6.2 Electrical Design Considerations
Use the following list of considerations to assure correct operation:
• Provide a low-impedance path from the board power supply to each VDD pin on the controller, and from the
board ground to each VSS (GND) pin.
• The minimum bypass requirement is to place six 0.01–0.1 μF capacitors positioned as close as possible to
the package supply pins. The recommended bypass configuration is to place one bypass capacitor on each
of the ten VDD/VSS pairs, including VDDA/VSSA.
• Ensure that capacitor leads and associated printed circuit traces that connect to the chip VDD and VSS (GND)
pins are less than 0.5 inch per capacitor lead.
• Use at least a four-layer Printed Circuit Board (PCB) with two inner layers for VDD and GND.
• Bypass the VDD and GND layers of the PCB with approximately 100 μF, preferably with a high-grade
capacitor such as a tantalum capacitor.
• Because the device’s output signals have fast rise and fall times, PCB trace lengths should be minimal.
CAUTION
This device contains protective circuitry to guard against
damage due to high static voltage or electrical fields.
However, normal precautions are advised to avoid
application of any voltages higher than maximum rated
voltages to this high-impedance circuit. Reliability of
operation is enhanced if unused inputs are tied to an
appropriate voltage level.
56854 Technical Data, Rev. 6
58 Freescale Semiconductor
• Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance.
This is especially critical in systems with higher capacitive loads that could create higher transient currents
in the VDD and GND circuits.
• All inputs must be terminated (i.e., not allowed to float) using CMOS levels.
• Take special care to minimize noise levels on the VDDA and VSSA pins.
• When using Wired-OR mode on the SPI or the IRQx pins, the user must provide an external pull-up device.
• Designs that utilize the TRST pin for JTAG port or Enhance OnCE module functionality (such as
development or debugging systems) should allow a means to assert TRST whenever RESET is asserted, as
well as a means to assert TRST independently of RESET. Designs that do not require debugging
functionality, such as consumer products, should tie these pins together.
• The internal POR (Power on Reset) will reset the part at power on with reset asserted or pulled high but
requires that TRST be asserted at power on.
Electrical Design Considerations
56854 Technical Data, Rev. 6
Freescale Semiconductor 59
Part 7 Ordering Information
Table 7-1 lists the pertinent information needed to place an order. Consult a Freescale Semiconductor
sales office or authorized distributor to determine availability and to order parts.
*This package is RoHS compliant.
Table 7-1 56854 Ordering Information
Part Supply
Voltage Package Type Pin
Count
Frequency
(MHz) Order Number
DSP56854 1.8V, 3.3V Low-Profile Quad Flat Pack (LQFP) 128 120 DSP56854FG120
DSP56854 1.8V, 3.3V Low-Profile Quad Flat Pack (LQFP) 128 120 DSP56854FGE *
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Inc. All other product or service names are the property of their respective owners.
This product incorporates SuperFlash® technology licensed from SST.
© Freescale Semiconductor, Inc. 2005. All rights reserved.
DSP56854
Rev. 6
01/2007
Information in this document is provided solely to enable system and
software implementers to use Freescale Semiconductor products. There are
no express or implied copyright licenses granted hereunder to design or
fabricate any integrated circuits or integrated circuits based on the
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Freescale Semiconductor reserves the right to make changes without further
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