XCR3320C10BE - Philips Semiconductors / NXP Semiconductors

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PZ3320C/PZ3320N

320 macrocell SRAM CPLD

Product specification

Supersedes data of 1998 Jul 22

IC27 Data Handbook

1999 Apr 16

INTEGRATED CIRCUITS

Philips Semiconductors Product specification

PZ3320C/PZ3320N320 macrocell SRAM CPLD

1999 Apr 16 853–2158 21266

FEATURES

•320 macrocell SRAM based CPLD

•Configuration times of under 1.0 second

•IEEE 1149.1 compliant JTAG testing capability

–5 pin JTAG interface

–IEEE 1149.1 TAP controller

•In system configurable

•3.3 volt device with 5V tolerant I/O

•Innovative XPLA2 Architecture combines extreme flexibility and

high speeds

•8 synchronous clock networks with programmable polarity at

every macrocell

•Up to 32 asynchronous clocks support complex clocking needs

•Innovative XOR structure at every macrocell provides excellent

logic reduction capability

•Logic expandable to 36 product terms on a single macrocell

•Advanced 0.35µ SRAM process

•Design entry and verification using industry standard and Philips

CAE tools

•Control Term structure provides either sum terms or product terms

in each logic block for:

–3-State buffer control

–Asynchronous macrocell register reset/preset

•Global 3-State pin facilitates ‘bed of nails’ testing without

sacrificing logic resources

•Programmable slew rate control

•Small form factor packages with high I/O counts

•Available in commercial and industrial temperature ranges

Table 1. PZ3320C/PZ3320N Features

PZ3320C/PZ3320N

Usable gates 10,000

Maximum inputs 192

Maximum I/Os 192

Number of macrocells 320

Propagation delay (ns) 7.5

Packages 160 pin LQFP

256 pin PBGA

DESCRIPTION

The PZ3320 device is a member of the CoolRunner family of

high-density SRAM-based CPLDs (Complex Programmable Logic

Device) from Philips Semiconductors. This device combines high

speed and deterministic pin-to-pin timing with high density. The

PZ3320 uses the patented Fast Zero Power (FZP) design technique

that combines high speed and low power for the first time ever in a

CPLD. FZP allows the PZ3320 to have true pin-to-pin timing delays

of 7.5ns, and standby currents of 100 microamps without the need

for ‘turbo bits’ or other power down schemes. By replacing

conventional sense amplifier methods for implementing product

terms (a technique that has been used since the bipolar era) with a

cascaded chain of pure CMOS gates, both standby and dynamic

power are dramatically reduced when compared to other CPLDs.

The FZP design technique is also what allows Philips to offer a true

CPLD architecture in a high density device.

The Philips PZ3320C/PZ3320N devices use the XPLA2 (eXtended

Programmable Logic Array) architecture. This architecture combines

the best features of both PAL- and PLA-type logic structures to

deliver high speed and flexible logic allocation that results in

superior ability to make design changes with fixed pinouts. The

XPLA2 architecture is constructed from 80 macrocell Fast

Modules that are connected together by an interconnect array.

Within each Fast Module are four Logic Blocks of 20 macrocells

each. Each Logic Block contains a PAL structure with four dedicated

product terms for each macrocell. In addition, each Logic Block has

32 additional product terms in a PLA structure that can be shared

through a fully programmable OR array to any of the 20 macrocells.

This combination efficiently allocates logic throughout the Logic

Block, which increases device density and allows for design

changes without re-defining the pinout or changing the system

timing. The PZ3320 offers pin-to-pin propagation delays of 7.5ns

through the PAL array of a Fast Module; and if the PLA array is

used, an additional 1.5ns is added to the delay, no matter how many

PLA product terms are used. If the interconnect array between Fast

Modules is used, there is a second fixed delay of 2.0ns. This means

that the worst case pin-to-pin propagation delay within a fast module

is 7.5 + 1.5 = 9.0 ns, and the delay from any pin to any other pin

across the entire chip is 7.5 + 2.0 = 9.5ns if only the PAL array is

used, and 7.5 + 1.5 + 2.0 = 11.0ns if the PLA array is used.

Each macrocell also has a two input XOR gate with the dedicated

PAL product terms on one input and the PLA product terms on the

other input. This patent-pending Versatile XOR structure allows for

very efficient logic optimization compared to competing XOR

structures that have only one product term as the second input to

the XOR gate. The Versatile XOR allows an 8 bit XOR function to be

implemented in only 20 product terms, compared to 65 product

terms for the traditional XOR approach.

The PZ3320 is SRAM-based, which means that it is configured from

an external source at power up. See the configuration section of this

data sheet for more information. The device supports the full JTAG

specification (IEEE 1149.1) through an industry standard JTAG

interface. It can also be configured through the JTAG port, which is

very useful for prototyping. See section titled

Configuring the Device

Through JTAG

for more information.

Software support for the PZ3320 is through industry standard CAE

tools (Cadence, Mentor, Synopsys, Viewlogic, Exemplar Logic, and

Orcad) as well as Philips’ own XPLA software. Entry methods

include both text (ABEL, PHDL, VHDL, Verilog) and/or schematic.

Design verification uses industry standard simulators for functional

and timing simulation, and development tools are supported on

personal computer, SPARC, and HP Workstation platforms.

Philips Semiconductors Product specification

PZ3320C/PZ3320N320 macrocell SRAM CPLD

1999 Apr 16 3

ORDERING INFORMATION

ORDER CODE PACKAGE,

PROPAGATION DELAY DESCRIPTION DRAWING NUMBER

PZ3320C7BE 160-pin LQFP, 7.5 ns tPD Commercial temp. range, 3.3 volt power supply 10% SOT435–1

PZ3320C10BE 160-pin LQFP, 10 ns tPD Commercial temp. range, 3.3 volt power supply 10% SOT435–1

PZ3320C7EB 256-pin PBGA, 7.5 ns tPD Commercial temp. range, 3.3 volt power supply 10% SOT471–1

PZ3320C10EB 256-pin PBGA, 10 ns tPD Commercial temp. range, 3.3 volt power supply 10% SOT471–1

PZ3320N8BE 160-pin LQFP, 8.5 ns tPD Industrial temp. range, 3.3 volt power supply 10% SOT435–1

PZ3320N8EB 256-pin PBGA, 8.5 ns tPD Industrial temp. range, 3.3 volt power supply 10% SOT471–1

Philips Semiconductors Product specification

PZ3320C/PZ3320N320 macrocell SRAM CPLD

1999 Apr 16 4

XPLA2 ARCHITECTURE

Figure 1 shows a high level block diagram of the PZ3320

implementing the XPLA2 architecture. The XPLA2 architecture is a

multi-level, modular hierarchy that consists of Fast Modules

interconnected by a virtual crosspoint switch called the Global Zero

Power Interconnect Array (GZIA). Each Fast Module accepts 64 bits

from the GZIA and outputs 64 bits to the GZIA. Each Fast Module is

essentially an 80 macrocell CPLD with four logic blocks of 20

macrocells each inside. There are eight dedicated, low-skew, global

clocks for the device; and each Fast Module has access to any two

of these clocks (there are additional asynchronous clocks available

in the Fast Modules, see Figure 3). There are also Global 3-state

(gts) and Global Reset (rstn) pins that are common to all Fast

Modules. When gts is pulled high, all output buffers in the device will

be disabled, causing all I/O pins to be tri-stated. When rstn is pulled

low, all flip-flops of the device will be reset.

FAST

MODULE 64

2FAST

MODULE

FAST

MODULE 64

2FAST

MODULE

gts

DEDICATED

CLOCK INPUTS

GZIA

SP00655

rstn

Figure 1. Philips XPLA2 CPLD Architecture

Philips Semiconductors Product specification

PZ3320C/PZ3320N320 macrocell SRAM CPLD

1999 Apr 16 5

XPLA2 Fast Module

Each Fast Module consists of four Logic Blocks of 20 macrocells

each. Depending on the package, either 7 or 12 of the 20 macrocells

in each Logic Block are connected to I/O pins, and the remaining

macrocells are used as buried nodes. These four Logic Blocks are

connected together by the Local Zero Power Interconnect Array

(LZIA). The LZIA is a virtual crosspoint switch that connects the

Logic Blocks to each other and to the GZIA. The feedback from all

80 macrocells, input from the I/O pins, and the 64 bit input bus from

the GZIA are input into the LZIA. The LZIA outputs 36 signals into

each Logic Block and 64 signals into the GZIA.

LOGIC

BLOCK

I/O 36

MC0

MC1

MC19

I/O

MC0

MC1

MC19

LOGIC

BLOCK

I/O 36

MC0

MC1

MC19

I/O

MC0

MC1

MC19

LZIA

LOGIC

BLOCK

LOGIC

BLOCK

64 64

SP00656

Figure 2. Philips XPLA2 Fast Module

Philips Semiconductors Product specification

PZ3320C/PZ3320N320 macrocell SRAM CPLD

1999 Apr 16 6

XPLA2 Logic Block Architecture

Figure 3 illustrates the XPLA2 Logic Block architecture. Each Logic

Block contains 8 control terms, a PAL array, a PLA array, and 20

macrocells. The 36 inputs from the LZIA are available to all control

terms and to each product term in both the PAL and the PLA array.

The 8 control terms can individually be configured as either SUM or

PRODUCT terms, and are used to control the asynchronous preset

and reset functions of the macrocell registers, the output enables of

the 20 macrocells, and for asynchronous clocking. The PAL array

consists of a programmable AND array with a fixed OR array, while

the PLA array consists of a programmable AND array with a

programmable OR array.

Each macrocell has 4 dedicated product terms from the PAL array.

When additional logic is required, each macrocell takes the extra

product terms from the PLA array. The PLA array consists of 32

extra product terms that are shared between the 20 macrocells of

the Logic Block. The PAL product terms can be connected to the

PLA product terms through either an OR gate or an XOR gate. One

input to the XOR gate can be connected to all the PLA terms, which

provides for extremely efficient logic synthesis. An eight bit XOR

function can be implemented in only 20 product terms. Each

macrocell can use the output from the OR gate or the XOR gate in

either normal or inverted state.

MC0

MC1

MC2

MC19

(32)

PLA

ARRAY

PAL

ARRAY

CONTROL

LZIA

INPUTS

PATENT PENDING

SP00589A

Figure 3. Philips XPLA2 Logic Block Architecture

Philips Semiconductors Product specification

PZ3320C/PZ3320N320 macrocell SRAM CPLD

1999 Apr 16 7

XPLA2 Macrocell Architecture

Figure 4 shows the XPLA2 macrocell architecture used in the

PZ3320. The macrocell can be configured as either a D- or T-type

flip-flop or a combinatorial logic function. A D-type flip-flop is

generally more useful for implementing state machines and data

buffering while a T-type flip-flop is generally more useful in

implementing counters. Each of these flip-flops can be clocked from

any one of four sources. Two of the clock sources (CLK0 and CLK1)

are from the eight dedicated, low-skew, global clock networks

designed to preserve the integrity of the clock signal by reducing

skew between rising and falling edges. These clocks are designated

as “synchronous” clocks and must be driven by an external source.

Both CLK0 and CLK1 can clock the macrocell flip-flops on either the

rising edge or the falling edge of the clock signal. The other clock

sources are designated as “asynchronous” and are connected to

two of the eight control terms (CT6 and CT7) provided in each logic

block. These clocks can be individually configured as any

PRODUCT term or SUM term equation created from the 36 signals

available inside the logic block. Thus, in each Logic Block, there are

up to four possible clocks; and in each Fast Module, there are up to

10 possible clocks. Throughout the entire device, there are up to 40

possible clocks—eight from the dedicated, low-skew, global clocks,

and two for each of the 16 logic blocks.

The remaining six control terms of each logic block (CT0–CT5) are

used to control the asynchronous preset/reset of the flip-flops and

the enable/disable of the output buffers in each macrocell. Control

terms CT0 and CT1 are used to control the asynchronous

preset/reset of the macrocell’s flip-flop. Note that the power-on reset

leaves all macrocells in the “zero” state when power is properly

applied, and that the preset/reset feature for each macrocell can

also be disabled. Each macrocell can choose between an

asynchronous reset or an asynchronous preset function, but both

cannot be simultaneously used on the same register. The global rstn

function can always be used, regardless of whether or not

asynchronous reset or preset control terms are enabled. Control

terms CT2, CT3, CT4 and CT5 are used to enable or disable the

macrocell’ s output buffer. The output buffers can also be always

enabled or always disabled. All CoolRunner devices also provide a

Global 3-State (gts) pin, which, when pulled high, will 3-State all the

outputs of the device. This pin is provided to support “In-Circuit

Testing” or “Bed-of-Nails” testing used during manufacturing.

For the macrocells in the Logic Block that are associated with I/O

pins, there are two feedback paths to the LZIA: one from the

macrocell, and one from the I/O pin. The LZIA feedback path before

the output buf fer is the macrocell feedback path, while the LZIA

feedback path after the output buffer is the I/O pin feedback path.

When these macrocells are used as outputs, the output buffer is

enabled, and either feedback path can be used to feedback the logic

implemented in the macrocell. When the I/O pins are used as inputs,

the output buf fer of these macrocells will be 3-Stated and the input

signal will be fed into the LZIA via the I/O feedback path. In this case

the logic functions implemented in the buried macrocell can be fed

back into the LZIA via the macrocell feedback path. For macrocells

that are not associated with I/O pins, there is one feedback path to

the LZIA. Logic functions implemented in these buried macrocells

are fed back into the LZIA via this path. All unused inputs and I/O

pins should be properly terminated. Please refer to the section on

terminations.

CT2

CT3

CT4

CT5

VCC

GND

INIT*

D/T Q

CLK0

CLK1

TO LZIA

GND

CT0

CT1

GND

gts

CT6

CT7

SP00590

rstn

*SEE XPLA2 MACROCELL ARCHITECTURE DESCRIPTION

Figure 4. PZ3320 Macrocell Architecture

Philips Semiconductors Product specification

PZ3320C/PZ3320N320 macrocell SRAM CPLD

1999 Apr 16 8

Simple Timing Model

Figure 5 shows the PZ3320 timing model. The PZ3320 timing model

is very simple compared to the models of competing architectures.

There are three main timing parameters: the pin-to-pin delay for

combinatorial logic functions (tPD), the input pin to register set up

time (tSU), and the register clock to valid output time (tCO). As the

model shows, timing is only dependent on whether or not you use

the PLA array, and whether or not the logic function is created within

a single Fast Module or uses the GZIA. The timing starts with a set

time for tPD and tSU through the PAL array in a Fast Module, and

there are fixed delays added for use of the PLA array or the GZIA.

The tCO (pin–to-pin) timing specification never changes. For

example, a combinatorial logic function of four or fewer product

terms constructed from inputs within the same logic block would

have a tPD delay of 7.5ns. If the logic function were more than four

product terms wide, the delay would be tPD plus the fixed PLA delay,

or 7.5 + 1.5 = 9.0ns. A function that used the PAL array and inputs

from a different Fast Module would have a propagation delay of tPD

plus the fixed GZIA delay, or 7.5 + 2.0 = 9.5ns.

OUTPUT PININPUT PIN

tPD_PAL = COMBINATORIAL PAL

tPD_PLA = COMBINATORIAL PAL + PLA

OUTPUT PININPUT PIN DQ

REGISTERED

tSU_PAL = PAL

tSU_PLA = PAL + PLA REGISTERED

tCO

Within a Fast Module:

Using the Global ZIA:

OUTPUT PININPUT PIN

tPD_PAL = COMBINATORIAL PAL + GZD

tPD_PLA = COMBINATORIAL PAL + PLA ,+ GZD

OUTPUT PININPUT PIN DQ

REGISTERED

tSU_PAL = PAL + GZD

tSU_PLA = PAL + PLA + GZD REGISTERED

tCO

SP00591B

GLOBAL CLOCK PIN

Figure 5. PZ3320 Timing Model

Philips Semiconductors Product specification

PZ3320C/PZ3320N320 macrocell SRAM CPLD

1999 Apr 16 9

TotalCMOS Design Technique

for Fast Zero Power

Philips is the first to of fer a TotalCMOS CPLD, both in process

technology and design technique. Philips employs a cascade of

CMOS gates to implement its product terms instead of the traditional

sense amp approach. This CMOS gate implementation allows Philips

to offer CPLDs which are both high performance and low power,

breaking the paradigm that to have low power, you must have low

performance. This also makes it possible to manufacture high density

CPLDs like the PZ3320 that consume a fraction of the power of

competing devices. Refer to Figure 6 and Table 2 showing the IDD vs.

Frequency of the PZ3320 TotalCMOS CPLD (data taken with 20

16-bit counters @ 3.3V, 25°C, output buffers disabled).

FREQUENCY (MHz)

0 20406080

100

120

140

IDD

(mA)

100

SP00657

120

160

180

200

Figure 6. IDD vs. Frequency @ VDD = 3.3V, 25°C

Table 2. IDD vs. Frequency

VDD = 3.3V

FREQUENCY (MHz) 0 1 20 40 60 80 100 120

Typical IDD (mA) 0.01 1.3 26 51 77 102 126 152

Terminations

The CoolRunner PZ3320C/PZ3320N CPLDs are TotalCMOS

devices. As with other CMOS devices, it is important to consider

how to properly terminate unused inputs and I/O pins when

fabricating a PC board. Allowing unused inputs and I/O pins to float

can cause the voltage to be in the linear region of the CMOS input

structures, which can increase the power consumption of the device.

It can also cause the voltage on a configuration pin to float to an

unwanted voltage level, interrupting device operation.

The PZ3320C/PZ3320N CPLDs have programmable on-chip

pull-down resistors on each I/O pin. These pull-downs are

automatically activated by the fitter software for all unused I/O pins.

Note that an I/O macrocell used as buried logic that does not have

the I/O pin used for input is considered to be unused, and the

pull-down resistors will be turned on. We recommend that any

unused I/O pins on the PZ3320C/PZ3320N device be left

unconnected.

There are no on-chip pull-down structures associated with dedicated

pins used for device configuration or special device functions like

global reset and global 3-state. Philips recommends that these pins

be terminated consistent with pin functionality. Philips recommends

the use of weak pull-up and pull-down resistors for terminating these

pins. See the appropriate configuration section for more information

on terminating dedicated pins

When using the JTAG Boundary Scan functions, it is recommended

that 10k pull-up resistors be used on the tdi, tms, tck, and trstn pins.

The tdo signal pin can be left floating unless it is connected to the tdi

of another device. Letting these signals float can cause the voltage

on tms to come close to ground, which could cause the device to

enter JTAG/ISP mode at unspecified times.

Philips Semiconductors Product specification

PZ3320C/PZ3320N320 macrocell SRAM CPLD

1999 Apr 16 10

CONFIGURATION INTRODUCTION

The Philips CoolRunner series are available in technologies which

use non-volatile (EEPROM-based) and volatile (SRAM based)

configuration memory. The functionality of the XPLA2 family of the

CoolRunner series is defined by on-chip SRAM. The devices are

configured in a manner similar to that of most FPGAs. This section

describes the configuration of the PZ3320, and applies to all

similarly configured devices to be produced by Philips.

Either Philips or third party software is used to generate a JEDEC

file. The JEDEC file contains the configuration data, which is loaded

into the PZ3320 configuration memory to control the PZ3320

functionality. This is done at power-up and/or with configure

command. This section provides some of the trade-offs in selecting

a configuration mode, and provides debug hints for configuration

problems.

There are several different methods of configuring the PZ3320. The

mode used is selected using the mode select pins. There are three

basic configuration methods: master, slave, and peripheral. The

configuration data can be transmitted to the PZ3320 serially or in

parallel bytes. As a master, the PZ3320 generates the clock and

control signals to strobe configuration data into the PZ3320. As a

slave device, a clock is generated externally, and provided into the

PZ3320’ s cclk pin. In the peripheral mode, the PZ3320 interfaces as

a microprocessor peripheral. Please note that M3 should always be

high. Table 3 lists the states for the other mode pins by configuration

mode.

Design Flow Overview

Figure 7 is a diagram of the steps used in configuring the PZ3320.

The development system is used to generate configuration data in

the JEDEC file. Using the <design>.jed file, there are two general

methods of configuring the PZ3320. The utility download can load

the configuration data from a PC or workstation hard disk into the

PZ3320. Alternately, the PZ3320 can be loaded from non-volatile

ICs such as serial or parallel EEPROMs, after converting the

JEDEC file to an MCS file using the jed2mcs utility.

Table 3. Configuration Modes

M2 M1 M0 cclk CONFIGURATION MODE DATA FORMAT

0 0 0 Output Master serial Serial

0 0 1 Input Slave parallel Parallel

0 1 0 Reserved

0 1 1 Input Synchronous peripheral Parallel

1 0 0 Output Master parallel – up Parallel

1 0 1 Reserved

1 1 0 Reserved

1 1 1 Input Slave serial Serial

SP00676

DESIGN COMPILATION AND FIT

jed2mcs download

jed

PROM PROGRAMMER SLAVE SERIAL CONFIGURATION

Figure 7. Design flow

Philips Semiconductors Product specification

PZ3320C/PZ3320N320 macrocell SRAM CPLD

1999 Apr 16 11

PZ3320 STATES OF OPERATION

Prior to becoming operational, the PZ3320 goes through a sequence

of states, including initialization, configuration, and start-up. This

section discusses these three states. In the master configuration

modes, the PZ3320 is the source of configuration clock (cclk).

When configuration is initiated, a counter in the PZ3320 is set to 0

and begins to count configuration clock cycles applied to the PZ3320.

As each configuration data frame is supplied to the PZ3320, it is

internally assembled into data words. Each data word is loaded into

the internal configuration memory. The configuration loading process

is complete when the internal length count equals the loaded length

count in the length count field, and the required end of configuration

frame is written.

All configuration I/Os used as inputs operate with TTL-level input

thresholds during configuration. All I/Os that are not used during the

configuration process are 3-Stated with internal pull-downs. During

configuration, registers are reset. The combinatorial logic begins to

function as the PZ3320 is configured. Figure 8 shows the flow

between the initialization, configuration, and start-up states. Figure 9

gives the general timing information for configuring the device.

START-UP

– ALL MACROCELL FF’S ARE RESET

SP00622

POWER-UP

– POWER-ON TIME DELAY

– crcerrn HIGH

INITIALIZATION

– hdc LOW, ldcn HIGH

– done LOW

resetn

prgmn

LOW

CONFIGURATION

– M[3:0] MODE IS SELECTED

– CONFIGURATION DATA FRAME WRITTEN

– hdc HIGH, ldcn LOW

– dout ACTIVE

– crcerrn HIGH, done LOW

resetn

prgmn

LOW

prgmn

LOW

OPERATION

– I/O BECOMES ACTIVE

YES

crcerrn LOW

CRC

ERROR

DEVICE CONFIGURATION COMPLETE

– done RELEASED

– dout ACTIVE

done

HIGH

YES

Figure 8. Flow chart of initialization, configuration, and operating states

Philips Semiconductors Product specification

PZ3320C/PZ3320N320 macrocell SRAM CPLD

1999 Apr 16 12

done

SP00652

VDD

prgmn

crcerrn

resetn

cclk

M[3:0]

I/O active

tpord tPW

tcclk

tsmode

INITIALIZATION CONFIGURATION START UP OPERATIONAL

hdc

ldcn

tCL

tIL

Figure 9. General configuration mode timing diagram

Table 4. General configuration mode timing characteristics

SYMBOL PARAMETER MIN MAX UNIT

All configuration modes

tSMODE M[3:0] setup time to prgmn high 0 – ns

tHMODE M[3:0] hold time from done high 10 –s

tPW prgmn pulse width low 50 – ns

tgtsr Global 3-state disable 40 ns

tIL Initialization latency (prgmn high to hdc high) PZ3320 M3 = 1 250 700 ns

tPORD Power-on reset delay 1s

trConfiguration signal rise time – 1.0 s

Master modes

tCCLK cclk period M3 = 1 714 1667 ns

tCL Configuration latency (non-compressed) PZ3320 M3 = 1 135 316 ms

Slave serial, slave parallel, and Synchronous peripheral modes

tCCLK

cclk

eriod

Single device 100 – ns

CCLK

cclk

eriod

Daisy-chain 1000 – ns

tCL

Configuration latency (non

com

ressed) PZ3320

Single device 19 – ms

tCL

Configuration

latency

(non-com ressed)

PZ3320

Daisy-chain 189 – ms

Philips Semiconductors Product specification

PZ3320C/PZ3320N320 macrocell SRAM CPLD

1999 Apr 16 13

Initialization

Upon power-up, the device goes through an initialization process.

First, an internal power-on-reset circuit is triggered when power is

applied. When VDD reaches the voltage at which portions of the

PZ3320 begin to operate (1.5V), the configuration pins are set to be

inputs or outputs based on the configuration mode, as determined

by the mode select inputs M[2:0]. The mode pins must be stable

tsmode nanoseconds before the rising edge of prgmn or resetn. A

time-out delay is initiated when VDD reaches between 1.0V and 2.0V

to allow the power supply voltage to stabilize. The done output is

low. At power-up, if the power supply does not rise from 1.0V to VDD

in less than 25ms, the user should delay configuration by inputting a

low into prgmn or resetn until VDD is greater than the recommended

minimum operating voltage (3.0V for commercial devices). If prgmn

has a rise time of greater than one microsecond, resetn must be

held low until after prgmn goes high. If the rise time for prgmn is 1

microsecond or less, the order in which these pins go high is

arbitrary.

The High During Configuration (hdc), Low During Configuration

(ldcn), and done signals are active outputs in the PZ3320’s

initialization and configuration states. hdc, ldcn, and done can be

used to provide control of external logic signals such as reset, bus

enable, or EEPROM enable during configuration. For master parallel

configuration mode, these signals provide EEPROM enable control

and allow the data pins to be shared with user logic signals.

If configuration has begun, an assertion of resetn or prgmn initiates

an abort, returning the PZ3320 to the initialization state. The resetn

and prgmn pins must be high before the PZ3320 will enter the

configuration state, and the mode pins must be stable tsmode

nanoseconds before they rise. During the start-up and operating

states, only the assertion of prgmn causes a re-configuration.

During initialization and configuration, all I/O’s are 3-stated and the

internal weak pull-downs are active. See the section on terminations

for more information.

Start-up

After configuration, the PZ3320 enters the start-up phase. This

phase is the transition between the configuration and operational

states. This transition occurs within three cclk cycles of the done pin

going high (it is acceptable to have additional cclk cycles beyond the

three required). The system design task in the start-up phase is to

ensure that multi-function pins (see pin function on page NO TAG)

transition from configuration signals to user definable I/Os without

inadvertently activating devices in the system or causing bus

contention. The done signal goes high at the beginning of the start

up phase, which allows configuration sources to be disconnected so

that there is no bus contention when the I/Os become active. In

addition to controlling the PZ3320 during start-up, additional start-up

techniques to avoid contention include using isolation devices

between the PZ3320 and other circuits in the system, re-assigning

I/O locations, and keeping I/Os 3-stated until contentions are

resolved. For example, Figure 10 shows how to use the global

tri-state (gts) signal to avoid signal contention when any

multi-function pins are used as I/O after configuration is finished.

Holding gts high until after the multi-function pins are disconnected

from the driving source allows these pins to transition from

configuration pins to user definable I/O without signal contention. In

this case, the I/O become active a tgtsr delay after the gts pin is

pulled low.

The flip-flops are reset one cycle after done goes high so that

operation begins in a known state. The done outputs from multiple

PZ3320s can be wire ANDed and used as an active-high ready

signal, to disable PROMs with active-low enable(s), or to reset to

other parts of the system (see Figure 27).

Philips Semiconductors Product specification

PZ3320C/PZ3320N320 macrocell SRAM CPLD

1999 Apr 16 14

tgtsh

SP00653

VDD

prgmn

crcerrn

resetn

cclk

M[3:0]

I/O active

GTS

done

tpord tPW

tsmode

tgtsr

tHMODE

INITIALIZATION CONFIGURATION START UP OPERATIONAL INITIALIZATION

hdc

ldcn

tCL

tIL

tsmode

Figure 10. Using gts signal with power up to avoid signal contention with multi-function pins used as I/O

CONFIGURATION DATA FORMAT OVERVIEW

The PZ3320 functionality is determined by the state of internal

configuration RAM. This section discusses the configuration data

format, and the function of each field in configuration data packets.

Configuration Data Packets

Configuration of the PZ3320 is done using configuration packets.

The configuration packet is shown in Figure 11. The data packet

consists of a header and a data frame. There are four types of data

frames. The header is shifted into the device first, followed by one

data frame. Configuration of a single PZ3320 requires 338 data

packets, one for each address. All preceding data must contain only

1’s. Once a device is configured, it re-transmits data of any polarity.

Before and during configuration, all data re-transmitted out the

daisy-chain port (dout) are 1’s.

The ordering of the data packets may be random, but they cannot

be mixed with other devices’ data packets. Alignment bits are not

required between data packets. If used, alignment bits must be

included in the length count, and they must be at least 2 bits long.

DATA FRAME HEADER

LSBMSB

SP00593

Figure 11. Data Packet

Philips Semiconductors Product specification

PZ3320C/PZ3320N320 macrocell SRAM CPLD

1999 Apr 16 15

Table 5. Configuration Frame Size

DEVICE PZ3320

Number of frames 338

Data bits/standard frame 560

Data bits/compressed frame 14

Data bits/user_code frame 560

Data bits/isc_code frame 560

Maximum configuration data—

# bits/frame × # frames 189280

COMPRESSION

BITS CRC

ENABLE PREAMBLE/

POSTAMBLE LEADING 1s

21614w4

SP00594

MSB LSB

Figure 12. 27-bit Header

The header is fixed and consists of five fields:

– Leading 1s,

– Preamble,

– CRC Enable,

– CRC Bits,

– Compression Bits.

The leading 1s enter the device first. The following is a description of

each field in the header.

Leading 1s:

This is a four or greater bit field consisting of 1s.

Preamble/Postamble:

This is a four bit field which indicates the start of a frame or

the end of configuration:

Preamble: 0010 – signals the beginning of a configuration

data packet

Postamble: 0100 – signals the end of configuration

All other values of the preamble field force configuration of

the entire system to restart.

The segments CRC Enable, CRC Bits, and Compression Bits are

valid only if the Preamble field is 0010.

Cyclic Redundancy Check (CRC) Enable:

In this single bit field, a 0 disables CRC checking of the data

stream. If the CRC is disabled the 16 bit CRC field must be

the default described below. A 1 enables CRC error checking

of the data stream.

CRC Error Checking:

The CRC field is a 16 bit field. The default value is

1010_1010_1010_1010. The calculated value is from data,

address, stop bit, and first alignment bit (starting with

crc_reg[15:0] = [0]). Using verilog operators, the crc is

calculated as:

crc_reg[14:2] <= cr_reg[14:2] << 1;

cr_reg[2] <= cr_reg[15]^din^cr_reg[1];

cr_reg[1] <= cr_reg[0];

cr_reg[0] < cr_reg[15]^din;

cr_reg[15] <= cr_reg[15]^din^cr_reg[14];

If a CRC error is detected, configuration is halted and must

be restarted.

Compression Bits:

This 2-bit field defines the use of compression of the data

packets.

00 – Standard mode:

The data packet contains both address and data

01 – Reset mode:

The data packet contains only the address field.

This pattern causes the configuration register to be reset.

10 – Hold mode:

The data packet contains only the address field.

This pattern causes the configuration register to hold

its value.

11 – Set mode:

The data packet contains only the address field.

This pattern causes the configuration register to be set.

Data Frames

The four types of data frames are standard, compressed,

user_code, and isc_code. All fields must be completely filled, with 1s

used to fill unused bits. The definition of each frame is described

below:

Standard frame

ADDRESS DATA FRAME STOP BIT ALIGN BITS

11 546 1 (0) 2 (11)

SP00595

MSB LSB

Figure 13. Standard Frame

Address:

This is an 11 bit field for providing 338 (336 SRAM plus

2 user) addresses.

Data:

546 bit field.

Stop bit:

This is a one bit field which must be 0.

Align bit:

This is a two bit field which must be 11.

Compressed frame

ADDRESS STOP BIT ALIGN BITS

11 1 (0) 2 (11)

SP00597

MSB LSB

Figure 14. Compressed Frame

The compressed frame contains no data.

Philips Semiconductors Product specification

PZ3320C/PZ3320N320 macrocell SRAM CPLD

1999 Apr 16 16

User code frame

The user code is located at address 336.

ADDRESS

SP00598

UNUSED

274

LENGTH

COUNT

DEVICE

USER

CODE

216

STOP

BIT

1 (0)

ALIGN

BITS

2 (11)

MSB LSB

Figure 15. User code Frame

Length count:

This is a 24 bit field containing the length of the data stream

transmitted to configure all of the devices in the daisy chain.

This field is only used by a PZ3320 if it is in the master mode.

Device ID:

This is a 32-bit field containing PZ3320 device ID:

0000_001_001_010000_1_000_00000010101_1

User code:

This is a 216 bit field reserved for user information.

ISC code frame

The isc_code address is 337.

ADDRESS ISC CODE STOP BIT ALIGN BITS

11 272 1 (0) 2 (11)

SP00599

UNUSED

2722

MSB LSB

UNUSED

Figure 16. ISC Frame

The ISC frame allows the user to write an ISC code to the device.

Re-configuration

To reconfigure the PZ3320 when the device is operating in the

system, a low pulse is input into prgmn. The I/Os not used for

configuration are 3-Stated. The PZ3320 then samples the mode

select inputs and begins re-configuration. The mode pins are

continuously sampled, so the signals must be stable while prgmn is

low. When configuration is compete, done is released, allowing it to

be pulled high.

CRC Error Checking

CRC checking is done on each frame if enabled by setting the

CRCen bit in the header. If there is an error, a CRC error is flagged

by pulling crcerrn low. The PZ3320 is forced into the initialization

state, and then moves into the configuration state after prgmn and

resetn go high. The PZ3320 will also pull crcerrn low if an invalid

preamble is detected within a configuration data packet.

PZ3320 CONFIGURATION MODES

The method for configuring the PZ3320 is selected by the m0, m1, and

m2 inputs. The m3 input should be high for all modes. In master modes,

cclk is an output with a nominal frequency of 1 MHz. In slave modes,

cclk is an input with a maximum frequency of 10 MHz if configuring only

a single device, and 1 MHz if devices are daisy chained.

Master Serial Mode

In the master serial mode, the PZ3320 loads the configuration data

from an external serial ROM. The configuration data is either loaded

automatically at start-up or on a command to reconfigure. Serial

EEPROMs from Altera, Atmel, Lucent, Microchip, and Xilinx can be

used to configure the PZ3320 in the master serial mode. This

provides a simple four-pin interface in an eight-pin package. Serial

EEPROMs are available in 32K, 64K, 128K, 256K, and 1M bit

densities.

Configuration in the master serial mode can be done at power-up

and/or upon a configure command. The system or the PZ3320 must

activate the serial EEPROM’s RESET/OE and CE inputs. At

power-up, the PZ3320 and serial EEPROM each contain internal

power-on reset circuitry which allows the PZ3320 to be configured

without the system providing an external signal. The power-on reset

circuitry causes the serial EEPROMs’ internal address pointer to be

reset. After power-up, the PZ3320 automatically enters its

initialization phase.

The serial EEPROM/PZ3320 interface used depends on such

factors as the availability of a system reset pulse, availability of an

intelligent host to generate a configure command, whether a single

serial EEPROM is used or multiple serial ROMs are cascaded,

whether the serial EEPROM contains a single or multiple

configuration programs, etc.

Data is read into the PZ3320 sequentially from the serial ROM. The

DATA output from the serial EEPROM is connected directly into the

din input of the PZ3320. The cclk output from the PZ3320 is

connected to the CLOCK input of the serial EEPROM. During the

configuration process, cclk clocks one data bit into the PZ3320 on

each rising edge.

Since the data and clock are direct connects, the PZ3320/serial

EEPROM interface task is to use the system or PZ3320 to enable

the RESET/OE and CE of the serial EEPROM(s). The serial

EEPROM’s RESET/OE is programmable to function with RESET

active-low and OE active-high, which allows hdc from the PZ3320 to

control this function.

Likewise, the serial EEPROM could be programmed to function with

RESET active high and OE active low, allowing the ldcn pin from the

PZ3320 to control this function. The PZ3320 done pin is connected

to the serial EEPROM CE to enable the EEPROMs during

configuration and disable them when configuration is complete.

In Figure 17, the serial EEPROMs RESET/OE pin has been

programmed to function with RESET active low and OE active high,

and it is controlled by the PZ3320’s hdc pin. This resets the serial

EEPROMs during the initialization state and enables their output

during the configuration state. If a bit error is found during

configuration, hdc will go low, signifying the PZ3320 is back in

initialization state and also resetting the EEPROMs. This restarts the

configuration process.

The PZ3320 done pin is routed to the CE pin of the EEPROMs. The

low signal on done during configuration enable the serial EEPROMs.

At the completion of configuration, the high on done disables the

EEPROMs.

Philips Semiconductors Product specification

PZ3320C/PZ3320N320 macrocell SRAM CPLD

1999 Apr 16 17

SP00666

DATA

CLK

RESET/OE

CEO

din

cclk

done

hdc

dout TO DAISY–CHAINED

DEVICES

PZ3320

VCC

prgmn

resetn

EXTERNAL

CONTROLLER

IF DESIRED

VCC

Figure 17. Master Serial Configuration

In Figure 17, a serial EEPROM is programmed to configure a

PZ3320. When configuration data requirements exceed the capacity

of a single serial EEPROM, multiple serial EEPROMs can be

cascaded to support the configuration of a single (or multiple)

PZ3320(s). After the last bit from the first serial ROM is read, the

serial ROM outputs CEO low and 3-States the DATA output. The

next serial ROM recognizes the low on CE input and outputs

configuration data on the DATA output. After configuration is

complete, the PZ3320’s done output into CE disables the serial

EEPROMs.

In applications in which a serial EEPROM stores multiple

configuration programs, the subsequent configuration program(s)

are stored in EEPROM locations that follow the last address for the

previous configuration program. The user must ensure that the serial

EEPROMs address pointer is not reset, causing the first device

configuration to be reloaded.

Contention on the PZ3320’s din pin must be avoided. During

configuration, din receives configuration data. After configuration, it

is a user I/O.

SP00584

CCLK

DIN

DOUT

tStH

BIT N

tCH

tCL

Figure 18. Master Serial Configuration Mode Timing Diagram

Table 6. Master serial configuration mode timing characteristics

SYMBOL PARAMETER MIN NOM MAX UNIT

tSdin setup time 60 – – ns

tHdin hold time 0 – – ns

tDcclk to dout delay – – 300 ns

tCL cclk low time M3 = 1 357 500 833 ns

tCH cclk high time M3 = 1 357 500 833 ns

tCcclk frequency M3 = 1 0.6 1.0 1.4 MHz

Philips Semiconductors Product specification

PZ3320C/PZ3320N320 macrocell SRAM CPLD

1999 Apr 16 18

Master Parallel Mode

The master parallel configuration mode is generally used to interface

to industry-standard byte-wide memory such as 256K and larger

EEPROMs. Figure 19 provides the interface for master parallel

mode. The PZ3320 outputs a 20-bit address on A[19:0] to memory

and reads one byte of configuration data every eighth cclk. The

parallel bytes are internally serialized starting with the least

significant bit, D0. The starting memory address is 00000 Hex and

the PZ3320 increments the address for each byte loaded. The

starting address is output when the device enters the configuration

state. The PZ3320 latches the data byte on the second rising edge

of CCLK. This next data byte is latched in the PZ3320 seven cclk

cycles later.

SP00667

TO DAISY-CHAINED

DEVICES

dout

cclk

prgmn

done

D[7:0]

A[19:0]

D[7:0]

EEPROM

EXTERNALLY CONTROLLED

IF DESIRED VDD

PZ3320

mpmi

resetn EXTERNALLY CONTROL

IF DESIRED

(SEE PIN DESCRIPTION)

VCC

Figure 19. Master Parallel Configuration

Philips Semiconductors Product specification

PZ3320C/PZ3320N320 macrocell SRAM CPLD

1999 Apr 16 19

SP00585

BYTE N BYTE N + 1

D0 D1 D2 D3 D4 D5 D6 D7

A[19:0]

D[7:0]

CCLK

DOUT D0 D1 D2 D3

BYTE N BYTE N + 1

tCH

tCL

Figure 20. Master Parallel Configuration Mode Timing Diagram

Table 7. Master parallel configuration mode timing characteristics

SYMBOL PARAMETER MIN NOM MAX UNIT

tAV cclk to address valid 0 – 200 ns

tSD[7:0] setup time to cclk high 60 – ns

tHD[7:0] hold time from cclk high 0 – ns

tCL cclk low time M3 = 1 357 500 833 ns

tCH cclk high time M3 = 1 357 500 833 ns

tDcclk to dout delay – 300 ns

fCcclk frequency M3 = 1 0.6 1.0 1.4 MHz

Philips Semiconductors Product specification

PZ3320C/PZ3320N320 macrocell SRAM CPLD

1999 Apr 16 20

Synchronous Peripheral Mode

In the synchronous peripheral mode, byte-wide data is input into

D[7:0] on the rising edge of the cclk input. The first data byte is

clocked in on the second cclk after hdc goes high. Subsequent data

bytes are clocked in on every eighth rising edge of cclk. The process

repeats until all of the data is loaded into the PZ3320. The serial

data begins shifting out on dout 0.5 cycles after the parallel data was

loaded. It requires additional cclks after the last byte is loaded to

complete the shifting. Figure 21 shows the interface for synchronous

peripheral mode. When configuring a single device, the frequency of

cclk can be up to 10 MHz. As with master modes, this mode can be

used for the lead PZ3320 for daisy-chained devices. Note that the

cclk frequency for daisy-chained operation is limited to 1 MHz.

Also note that CS1 is a multi-function pin, which means that it is

available as a user I/O during normal device operation. As with all

user I/O on the PZ3320, CS1 has an internal pull-down resistor that

is automatically activated if the I/O pin is not used (see section on

terminations for more information). If CS1 is left attached to VCC

after configuration, and it is not used as an I/O, the internal

pull-down must be disabled or a path from VCC to ground is created.

To disable the pull-down, use the XPLA property statement ‘

signal

name:pin number

tri-state’ to disable the resistor.

SP00675

MICRO–

PROCESSOR

SYSTEM

D[7:0]

done

crcerrn

cclk

prgmn

cs1

cs0n

VCC

PZ3320

dout

TO DAISY-CHAINED

DEVICES

resetn

SPMI

EXTERNALLY CONTROLLED

IF DESIRED

SEE TABLE 9

VCC

wrn

Figure 21. Synchronous Peripheral Configuration

Philips Semiconductors Product specification

PZ3320C/PZ3320N320 macrocell SRAM CPLD

1999 Apr 16 21

SP00609

CCLK

hdc

D[7:0]

DOUT

BYTE 0 BYTE 1

D1 D2 D3 D4 D5 D6 D7 D0 D1

tCH

tCL

CS0N

CS1

Figure 22. Synchronous Peripheral Configuration Mode Timing Diagram

Table 8. Synchronous peripheral configuration mode timing characteristics

SYMBOL PARAMETER MIN MAX UNIT

tSD[7:0] setup time 20 0 ns

tHD[7:0] hold time 0 – ns

cclk high time

Single device 50 – ns

cclk

high

time

Daisy-chain device 500 – ns

cclk low time

Single device 50 – ns

cclk

time

Daisy-chain device 500 – ns

cclk frequency

Single device – 10 MHz

cclk

freq

enc

yDaisy-chain device – 1 MHz

Philips Semiconductors Product specification

PZ3320C/PZ3320N320 macrocell SRAM CPLD

1999 Apr 16 22

Slave Serial Mode

Figure 23 shows the interface for the slave serial configuration

mode. The configuration data is provided into the PZ3320’s din input

synchronous with the cclk input. After the PZ3320 has loaded its

configuration data, it re-transmits incoming configuration data on

dout. When configuring a single device, the frequency of cclk can be

up to 10 MHz.

A device in slave serial mode can be used as the lead device in a

daisy-chain. When used in daisy-chained operation, cclk is routed

into all slave serial mode devices in parallel and the frequency is

limited to 1 MHz. The dout pin of the lead device is connected to the

din pin of the next device and so on. In daisy-chained operation, all

downstream devices use slave serial mode regardless of the

configuration mode of the lead device.

Multiple slave PZ3320s can be loaded with identical configurations

simultaneously. This is done by loading the configuration data into

the din inputs in parallel.

SP00668

MICRO–

PROCESSOR

DOWNLOAD

CABLE

crcerrn

prgmn

done

cclk

VCC

dout

TO DAISY–CHAINED

DEVICES

din

PZ3320

resetn EXTERNALLY CONTROLLED

IF DESIRED

VCC

Figure 23. Slave Serial Configuration Schematic

BIT N

DIN

CCLK

DOUT BIT N

tStH

tCL tCH

SP00610

BIT N – 1 BIT N + 1

Figure 24. Slave Serial Configuration Mode Timing Diagram

Table 9. Slave serial configuration mode timing characteristics

SYMBOL PARAMETER MIN MAX UNIT

tSdin setup time 20 0 ns

tHdin hold time 0 – ns

cclk high time

Single device 50 – ns

cclk

high

time

Daisy-chain device 500 – ns

cclk low time

Single device 50 – ns

cclk

time

Daisy-chain device 500 – ns

cclk frequency

Single device – 10 MHz

cclk

freq

enc

yDaisy-chain device – 1 MHz

Philips Semiconductors Product specification

PZ3320C/PZ3320N320 macrocell SRAM CPLD

1999 Apr 16 23

Slave Parallel Mode

The slave parallel mode is essentially the same as the synchronous

peripheral mode, except that the chip select pins (cs1 and cs0n) are

not used. As in the synchronous peripheral mode, byte-wide data is

input into D[7:0] on the rising edge of the cclk input. The first data

byte is clocked in on the second cclk after hdc goes high.

Subsequent data bytes are clocked in on every eighth rising edge of

cclk. The process repeats until all of the data is loaded into the

PZ3320. The serial data begins shifting out on dout 0.5 cycles after

the parallel data was loaded. It requires additional cclks after the last

byte is loaded to complete the shifting. Figure 25 shows the

interface for slave parallel mode. When configuring a single device,

the frequency of cclk can be up to 10 MHz.

As with synchronous peripheral mode, the slave parallel mode can

be used as the lead PZ3320 for daisy-chained devices. Note that

the cclk frequency for daisy-chain operation is limited to 1 MHz.

SP00669

MICRO–

PROCESSOR

crcerrn

prgmn

done

cclk

VCC

dout

TO DAISY–CHAINED

DEVICES

D[7:0]

PZ3320

resetn EXTERNALLY CONTROLLED

IF DESIRED

VCC

CS1

WRN

CS0N

Figure 25. Slave Parallel Configuration Schematic

SP00654

CCLK

hdc

D[7:0]

DOUT

BYTE 0 BYTE 1

D1 D2 D3 D4 D5 D6 D7 D0 D1

tCH

tCL

Figure 26. Slave Parallel Configuration Mode Timing Diagram

Philips Semiconductors Product specification

PZ3320C/PZ3320N320 macrocell SRAM CPLD

1999 Apr 16 24

Table 10. Slave parallel configuration mode timing characteristics

SYMBOL PARAMETER MIN MAX UNIT

tSD[7:0] setup time 20 0 ns

tHD[7:0] hold time 0 – ns

tCH

cclk high time

Single device 50 – ns

cclk

high

time

Daisy-chain device 500 – ns

tCL

cclk low time

Single device 50 – ns

cclk

low

time

Daisy-chain device 500 – ns

cclk frequency

Single device – 10 MHz

cclk

frequency

Daisy-chain device – 1 MHz

DAISY CHAIN OPERATION

Multiple PZ3320s can be configured by using a daisy-chain of

PZ3320s. Daisy-chaining uses a lead PZ3320 and one or more

PZ3320s configured in slave serial mode. The lead PZ3320 can be

configured in any mode. Figure 27 shows the connections for

loading multiple PZ3320s in a daisy-chain configuration with the lead

devices configured in master parallel mode. Figure 28 shows the

connections for loading multiple PZ3320’s with the lead device

configured in master serial mode.

Daisy-chained PZ3320s are connected in series. An upstream

PZ3320 which has received the preamble outputs a high on dout,

ensuring that downstream PZ3320s do not receive frame start bits.

When the lead device receives the postamble, its configuration is

complete. At this point, the configuration RAM of the lead device is

full and its done pin is released. The lead device continues to load

configuration data until the internal frame bit counter reaches the

length count or all the done pins of the chain have gone high. Since

the configuration RAM of the lead device is full, this data is shifted

out serially to the downstream devices on the dout pin. As the

configuration is completed for the downstream devices, each will

release its done pin. Because the done pins of each device in the

chain are wire-anded together, the done pin will be pulled high when

all devices in the daisy-chain have completed configuration. All

devices now move to the start-up state simultaneously.

The generation of cclk for the daisy-chained devices which are in

slave serial mode differs depending on the configuration mode of the

lead device. A master parallel mode device uses its internal timing

generator to produce an internal cclk. If the lead device is configured

in either synchronous peripheral, slave serial mode, or slave parallel

mode, cclk is an input and is mated to the lead device and to all of

the daisy-chained devices in parallel. The configuration data is read

into din of slave devices on the positive edge of cclk, and shifted out

dout on the negative edge of cclk. Note that daisy-chain operation is

limited to a cclk frequency of 1 MHz. If a CRC error or an invalid

preamble is detected by a slave device, crcerrn will be pulled low

and in turn pull prgmn low, halting configuration for all devices. If a

CRC error is detected by the master device, hdc will be pulled low,

resetting the EEPROM to the first address and restarting

configuration.

The development software can create a composite configuration file

for configuring daisy-chained PZ3320s. The configuration data

consists of multiple concatenated data packets.

SP00670

EEPROM

D[7:0]

A[19:0]

cclk

A[19:0]

D[7:0]

done

prgmn

cclk

din

MASTER

PARALLEL/LEAD SLAVE #2

done

prgmn

crcerrn

dout

hdc

ldcn

crcerrn

hdc

ldcn

dout

PROGRAM VCC

cclk

din

SLAVE #1

done

prgmn

crcerrn

dout

hdc

ldcn

VCC

M3 M3M3

Figure 27. Daisy-chain Schematic with lead device in master parallel

Philips Semiconductors Product specification

PZ3320C/PZ3320N320 macrocell SRAM CPLD

1999 Apr 16 25

reset/OE

SP00665

EEPROM

dout

cclk

din

SLAVE #2

pgrmn

resetn

crcerrn

dout

hdc

cclk

done

VCC

cclk

din

SLAVE #1

pgrmn

resetn

crcerrn

dout

hdc

done

VCC

cclk

din

MASTER SERIAL

LEAD

pgrmn

resetn

crcerrn

dout

hdc

done

VCC

Figure 28. Daisy Chain Schematic with Master Serial Lead Device

JTAG Testing Capability

JTAG is the commonly-used acronym for the Boundary Scan Test

(BST) feature defined for integrated circuits by IEEE Standard

1149.1. This standard defines input/output pins, logic control

functions, and commands which facilitate both board and device

level testing without the use of specialized test equipment. BST

provides the ability to test the external connections of a device, test

the internal logic of the device, and capture data from the device

during normal operation. BST provides a number of benefits in each

of the following areas:

•Testability

–Allows testing of an unlimited number of interconnects on the

printed circuit board

–Testability is designed in at the component level

–Enables desired signal levels to be set at specific pins (Preload)

–Data from pin or core logic signals can be examined during

normal operation

•Reliability

–Eliminates physical contacts common to existing test fixtures

(e.g., “bed-of-nails”)

–Degradation of test equipment is no longer a concern

–Facilitates the handling of smaller, surface-mount components

–Allows for testing when components exist on both sides of the

printed circuit board

•Cost

–Reduces/eliminates the need for expensive test equipment

–Reduces test preparation time

–Reduces spare board inventories

The Philips PZ3320’s JTAG interface includes a TAP Port and a TAP

Controller, both of which are defined by the IEEE 1149.1 JTAG

Specification. As implemented in the Philips PZ3320, the TAP Port

includes five pins (refer to Table 11) described in the JTAG

specification: tck, tms, tdi, tdo, and trstn. These pins should be

connected to an external pull-up resistor to keep the JTAG signals

from floating when they are not being used.

Table 12 defines the dedicated pins used by the mandatory JTAG

signals for the PZ3320.

The JTAG specifications define two sets of commands to support

boundary-scan testing: high-level commands and low-level

commands. High-level commands are executed via board test

software on an a user test station such as automated test

equipment, a PC, or an engineering workstation (EWS). Each

high-level command comprises a sequence of low level commands.

These low-level commands are executed within the component

under test, and therefore must be implemented as part of the TAP

Controller design. The set of low-level boundary-scan commands

implemented in the PZ3320 is defined in Table 13. By supporting

this set of low-level commands, the PZ3320 allows execution of all

high-level boundary-scan commands.

Philips Semiconductors Product specification

PZ3320C/PZ3320N320 macrocell SRAM CPLD

1999 Apr 16 26

Table 11. JTAG Pin Description

PIN NAME DESCRIPTION

tck Test Clock Output Clock pin to shift the serial data and instructions in and out of the tdi and tdo pins, respectively. tck is

also used to clock the TAP Controller state machine.

tms Test Mode Select Serial input pin selects the JTAG instruction mode. tms should be driven high during user mode

operation.

tdi Test Data Input Serial input pin for instructions and test data. Data is shifted in on the rising edge of tck.

tdo Test Data Output Serial output pin for instructions and test data. Data is shifted out on the falling edge of tck. The

signal is tri-stated if data is not being shifted out of the device.

trstn Test Reset Forces TAP controller to test logic reset state. This signal is active low.

Table 12. PZ3320 JTAG Pinout by Package Type

DEVICE

(PIN NUMBER / MACROCELL #)

DEVICE

tck tms tdi tdo trstn

PZ3320

256 pin PBGA V4 W4 U5 Y4 L18

160 pin LQFP 41 43 42 44 97

Table 13. PZ3320 Low-Level JTAG Boundary-Scan Commands

INSTRUCTION

(Instruction Code)

DESCRIPTION

SAMPLE/PRELOAD

(00010)

Boundary-Scan Register

The mandatory SAMPLE/PRELOAD instruction allows a snapshot of the normal operation of the component

to be taken and examined. It also allows data values to be loaded onto the latched parallel outputs of the

Boundary-Scan Shift-Register prior to selection of the other boundary-scan test instructions.

EXTEST

(00000)

Boundary-Scan Register

The mandatory EXTEST instruction allows testing of off-chip circuitry and board level interconnections. Data

would typically be loaded onto the latched parallel outputs of Boundary-Scan Shift-Register using the

SAMPLE/PRELOAD instruction prior to selection of the EXTEST instruction.

BYPASS

(11111)

Bypass Register

Places the 1 bit bypass register between the tdi and tdo pins, which allows the BST data to pass

synchronously through the selected device to adjacent devices during normal device operation. The BYPASS

instruction can be entered by holding tdi at a constant high value and completing an Instruction-Scan cycle.

IDCODE

(00001)

Boundary-Scan Register

Selects the IDCODE register and places it between tdi and tdo, allowing the IDCODE to be serially shifted

out of tdo. The IDCODE instruction permits blind interrogation of the components assembled onto a printed

circuit board. Thus, in circumstances where the component population may vary, it is possible to determine

what components exist in a product.

HIGHZ

(00101)

Bypass Register

The HIGHZ instruction places the component in a state in which all of its system logic outputs are placed in

an inactive drive state (e.g., high impedance). In this state, an in-circuit test system may drive signals onto

the connections normally driven by a component output without incurring the risk of damage to the

component. The HIGHZ instruction also forces the Bypass Register between tdi and tdo.

INTEST

(00011)

Boundary-Scan Register

The INTEST instruction allows testing of the on-chip system logic while the component is assembled on the

board. The boundary-scan register is connected between TDI and TDO. Using the INTEST instruction, test

stimuli are shifted in one at a time and applied to the on-chip system logic. The test results are captured

into the boundary-scan register and are examined by subsequent shifting, Data would typically be loaded

onto the latched parallel outputs of boundary-scan shift-register stages using the SAMPLE/PRELOAD

instruction prior to selection of the INTEST instruction.

NOTE: Following use of the INTEST instruction, the on-chip system logic may be in an indeterminate state

that will persist until a system reset is applied. Therefore, the on-chip system logic may need to be reset on

return or normal (i.e., nontest) operation.

Philips Semiconductors Product specification

PZ3320C/PZ3320N320 macrocell SRAM CPLD

1999 Apr 16 27

SP00613

tStH

tCH tCL

TCK

TMS

TDI

TDO

Figure 29. Boundary Scan Timing Diagram

Table 14. Boundary scan timing characteristics

SYMBOL PARAMETER MIN MAX UNIT

tStdi/tms to tck setup time 20 – ns

tHtdi/tms from tck hold time 0 – ns

tCH tck high time 50 – ns

tCL tck low time 50 – ns

fTCK tck frequency – 10 MHz

tDtck to tdo delay – 35 ns

DEVICE CONFIGURATION THROUGH JTAG

In addition to the normal configuration modes, the PZ3320 can also

be configured through the JTAG port. This feature is very useful for

design prototyping and debug before the device is put into the final

product. In System Configuration of the PZ3320 is supported by

Philips Semiconductors’ PC-ISP software. Table 15 shows the ISC

commands supported by the PZ3320, and Table 16 details the AC

and DC specification for configuring the device through the JTAG

port.

To configure the device through the JTAG port, mode pins M0, M1,

and M2 should all be held low. M3, as always, should be high and

the JTAG pins should be terminated as described in the

Terminations

section of this data sheet.

Table 15. Low Level ISP Commands

INSTRUCTION

(Register Used)

INSTRUCTION

CODE DESCRIPTION

Enable

(ISP Shift Register)

1001 Enables the Erase, Program, and Verify commands. Using the ENABLE instruction before the

Erase, Program, and Verify instructions allows the user to specify the outputs the device using

the JTAG Boundary-Scan SAMPLE/PRELOAD command.

Erase

(ISP Shift Register)

1010 Erases the entire EEPROM array. The outputs during this operation can be defined by user by

using the JTAG SAMPLE/PRELOAD command.

Program

(ISP Shift Register)

1011 Programs the data in the ISP Shift Register into the addressed EEPROM row . The outputs

during this operation can be defined by user by using the JTAG SAMPLE/PRELOAD command.

Verify

(ISP Shift Register)

1100 Transfers the data from the addressed row to the ISP Shift Register. The data can then be

shifted out and compared with the JEDEC file. The outputs during this operation can be defined

by the user.

Philips Semiconductors Product specification

PZ3320C/PZ3320N320 macrocell SRAM CPLD

1999 Apr 16 28

Table 16. Programming Specifications

SYMBOL PARAMETER MIN. MAX UNIT

DC Parameters

VCCP VCC supply program/verify V

ICCP ICC limit program/verify mA

VIH Input voltage (High) V

VIL Input voltage (Low) V

VSOL Output voltage (Low) V

VSOH Output voltage (High) V

TDO_IOL Output current (Low) mA

TDO_IOH Output current (High) mA

AC Parameters

fMAX TCK maximum frequency MHz

PWE Pulse width erase ms

PWP Pulse width program ms

PWV Pulse width verify µs

INIT Initialization time µs

TMS_SU TMS setup time before TCK ↑ns

TDI_SU TDI setup time before TCK ↑ns

TMS_H TMS hold time after TCK ↑ns

TDI_H TDI hold time after TCK ↑ns

TDO_CO TDO valid after TCK ↓ns

ABSOLUTE MAXIMUM RATINGS1

SYMBOL PARAMETER MIN MAX UNIT

VDD Supply voltage –0.5 4.6 V

VIN Input voltage –1.2 5.75 V

VOUT Output voltage –0.5 VDD+0.5 V

IIN Input current –30 30 mA

TJJunction temperature range –40 150 °C

TSTG Storage temperature range –65 150 °C

NOTE:

1. Stresses above these listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at

these or any other condition above those indicated in the operational and programming specification is not implied.

OPERATING RANGE

PRODUCT GRADE TEMPERATURE VOLTAGE

Commercial 0 to 70_C3.3 10% V

Industrial –40 to 85_C3.3 10% V

Philips Semiconductors Product specification

PZ3320C/PZ3320N320 macrocell SRAM CPLD

1999 Apr 16 29

DC ELECTRICAL CHARACTERISTICS FOR COMMERCIAL GRADE DEVICES

Commercial temperature range: VDD = 3.0V to 3.6V; 0°C < Tamb < 70°C

SYMBOL PARAMETER TEST CONDITIONS MIN MAX UNIT

VIH Input high voltage 2.0 5.5 V

VIL Input low voltage –0.3 0.8 V

VOH Output high voltage IOH = –8mA 2.4 – V

VOL Output low voltage IOL = 8mA – 0.4 V

IIInput leakage current VI = 0 or 5.5 V –10 10 µA

IDDSB Standby current Tamb = 25°C; no output loads,

inputs at VDD or VSS.– 100 µA

CIN Input capacitance Tamb = 25°C; VDD = 3.3V ; f = 1MHz – 10 pF

CIO I/O capacitance Tamb = 25°C; VDD = 3.3V ; f = 1MHz – 10 pF

CCLK Clock pin capacitance Tamb = 25°C; VDD = 3.3V; f = 1MHz – 12 pF

RDONE done pull-up resistor VDD = 3.0 V ; VIN = 0 V 5 20 kΩ

RPD Unused I/O pull-down resistor VDD = 3.6V ; V IN = VDD 100 400 kΩ

IOZH Input leakage VIN = 5.5 V or 3.6 V –10 10 A

IOZL Input leakage VIN = 0.0 V –10 10 A

Philips Semiconductors Product specification

PZ3320C/PZ3320N320 macrocell SRAM CPLD

1999 Apr 16 30

AC ELECTRICAL CHARACTERISTICS FOR COMMERCIAL GRADE DEVICES

Commercial temperature range: VDD = 3.0V to 3.6V; 0°C < Tamb < 70°C

C7 C10

SYMBOL PARAMETER MIN MAX MIN MAX UNIT

Timing requirements

tCL Clock LOW time 2.5 3.0 ns

tCH Clock HIGH time 2.5 3.0 ns

tSU_PAL PAL setup time (Global clock) 3.0 4.0 ns

tSU_PLA PLA setup time (Global clock) 4.5 5.5 ns

tSU_XOR XOR setup time (Global clock) 5.5 6.5 ns

tHHold time (Global clock) 0 0 ns

Output characteristics

tPD_PAL Input to output delay through PAL 7.5 10.0 ns

tPD_PLA Input to output delay through PLA 9.0 11.5 ns

tPD_XOR Input to output delay through XOR 10.0 12.5 ns

tPDF_PAL Input (or feedback node) to internal feedback node delay time through PAL 4.5 6.0 ns

tPDF_PLA Input (or feedback node) to internal feedback node delay time through PLA 6.0 7.5 ns

tPDF_XOR Input (or feedback node) to internal feedback node delay time through XOR 7.0 8.5 ns

tCF Global clock to feedback delay 3.0 3.5 ns

tCO Global clock to out delay 6.0 7.5 ns

tCS Clock skew (variance for switching outputs with common global clock) 1.0 1.5 ns

fMAX1 Maximum flip-flop toggle rate ǒ1

tCL )tCHǓ200 166 MHz

fMAX2 Maximum internal frequency ǒ1

tSU_PAL )tCFǓ166 133 MHz

fMAX3 Maximum external frequency ǒ1

tSU_PAL )tCOǓ111 87 MHz

tBUFF Output buf fer delay (fast) 3.0 4.0 ns

tSSR Slow slew rate incremental delay 5.0 6.0 ns

tEA Output enable delay 10.0 12.0 ns

tER Output disable delay110.0 12.0 ns

tGTSA Global 3-State enable 10.0 12.0 ns

tGTSR Global 3-State disable 10.0 12.0 ns

tRR Input to register reset 10.5 12.0 ns

tRP Input to register preset 9.5 11.0 ns

tGRR Global reset to register reset 10 12.0 ns

tGZIA Global ZIA delay 2.0 2.5 ns

NOTE:

1. Output CL = 5.0pF.

Philips Semiconductors Product specification

PZ3320C/PZ3320N320 macrocell SRAM CPLD

1999 Apr 16 31

DC ELECTRICAL CHARACTERISTICS FOR INDUSTRIAL GRADE DEVICES

Industrial temperature range: VDD = 3.0V to 3.6V; –40°C < Tamb < 85°C

SYMBOL PARAMETER TEST CONDITIONS MIN MAX UNIT

VIH Input high voltage 2.0 5.5 V

VIL Input low voltage –0.3 0.8 V

VOH Output high voltage IOH = –8mA 2.4 – V

VOL Output low voltage IOL = 8mA – 0.4 V

IIInput leakage current VI = 0 or 5.5 V –10 10 µA

IDDSB Standby current Tamb = 25°C; no output loads,

inputs at VDD or VSS.– 100 µA

CIN Input capacitance Tamb = 25°C; VDD = 3.3V ; f = 1MHz – 10 pF

CIO I/O capacitance Tamb = 25°C; VDD = 3.3V ; f = 1MHz – 10 pF

CCLK Clock pin capacitance Tamb = 25°C; VDD = 3.3V; f = 1MHz – 12 pF

RDONE done pull-up resistor VDD = 3.0 V ; VIN = 0 V 5 20 kΩ

RPD Unused I/O pull-down resistor VDD = 3.6V ; V IN = VDD 100 400 kΩ

IOZH Input leakage VIN = 5.5 V or 3.6 V –10 10 A

IOZL Input leakage VIN = 0.0 V –10 10 A

Philips Semiconductors Product specification

PZ3320C/PZ3320N320 macrocell SRAM CPLD

1999 Apr 16 32

AC ELECTRICAL CHARACTERISTICS FOR INDUSTRIAL GRADE DEVICES

Industrial temperature range: VDD = 3.0V to 3.6V; –40°C < Tamb < 85°C

SYMBOL PARAMETER MIN MAX UNIT

Timing requirements

tCL Clock LOW time 2.5 ns

tCH Clock HIGH time 2.5 ns

tSU_PAL PAL setup time (Global clock) 3.5 ns

tSU_PLA PLA setup time (Global clock) 5.0 ns

tSU_XOR XOR setup time (Global clock) 6.0 ns

tHHold time (Global clock) 0 ns

Output characteristics

tPD_PAL Input to output delay through PAL 8.5 ns

tPD_PLA Input to output delay through PLA 10 ns

tPD_XOR Input to output delay through XOR 11 ns

tPDF_PAL Input (or feedback node) to internal feedback node delay time through PAL 5.0 ns

tPDF_PLA Input (or feedback node) to internal feedback node delay time through PLA 6.5 ns

tPDF_XOR Input (or feedback node) to internal feedback node delay time through XOR 7.5 ns

tCF Global clock to feedback delay 3.5 ns

tCO Global clock to out delay 7.0 ns

tCS Clock skew (variance for switching outputs with common global clock) 1.0 ns

fMAX1 Maximum flip-flop toggle rate ǒ1

tCL )tCHǓ200 MHz

fMAX2 Maximum internal frequency ǒ1

tSU_PAL )tCFǓ143 MHz

fMAX3 Maximum external frequency ǒ1

tSU_PAL )tCOǓ95 MHz

tBUFF Output buf fer delay (fast) 3.5 ns

tSSR Slow slew rate incremental delay 5.5 ns

tEA Output enable delay 11.0 ns

tER Output disable delay111.0 ns

tGTSA Global 3-State enable 11.0 ns

tGTSR Global 3-State disable 11.0 ns

tRR Input to register reset 11.5 ns

tRP Input to register preset 10.0 ns

tGRR Global reset to register reset 11 ns

tGZIA Global ZIA delay 2.5 ns

NOTE:

1. Output CL = 5.0pF.

Philips Semiconductors Product specification

PZ3320C/PZ3320N320 macrocell SRAM CPLD

1999 Apr 16 33

THEVENIN EQUIVALENT

25pF

200Ω

DUT OUTPUT

VL = 0.5 VDD

SP00629

VOLTAGE WAVEFORM

90%

10%

2.0 ns2.0 ns

+3.0V

tRtF

MEASUREMENTS:

All circuit delays are measured at the +1.5V level of

inputs and outputs, unless otherwise specified.

Input Pulses

SP00630

Philips Semiconductors Product specification

PZ3320C/PZ3320N320 macrocell SRAM CPLD

1999 Apr 16 34

PINNING

256-pin Plastic Ball Grid Array (PBGA)

A1 BALL PAD CORNER

BOTTOM VIEW

2019181716151413121110987654321

SP00671

Philips Semiconductors Product specification

PZ3320C/PZ3320N320 macrocell SRAM CPLD

1999 Apr 16 35

Pin Functions

Function is Fast Module_Logic block_Macrocell. For example, F1_0_5 means Fast Module 1, Logic block 0, Macrocell 5.

Pkg

Ball Function

A1 GND

A2 F0_2_11

A3 F0_2_9

A4 cclk

A5 F0_2_5*

A6 F0_2_2*

A7 F0_3_0

A8 F0_3_3

A9 F0_3_6

A10 F0_3_9

A11 F0_3_10

A12 F1_1_10

A13 F1_1_7

A14 F1_1_4

A15 F1_1_1

A16 F1_0_1

A17 F1_0_4

A18 F1_0_8

A19 F1_0_10

A20 F1_0_11

B1 F0_0_11

B2 GND

B3 F0_2_10

B4 resetn

B5 F0_2_6

B6 F0_2_3

B7 F0_2_0*

B8 F0_3_2

B9 F0_3_5

B10 F0_3_8

B11 F0_3_11

B12 F1_1_9

B13 F1_1_6*

B14 F1_1_3

B15 F1_1_0

B16 F1_0_2

B17 F1_0_5*

B18 F1_0_9

B19 GND

B20 F1_2_11

Pkg

Ball Function

C1 F0_0_9

C2 F0_0_10

C3 GND

C4 pgrm

C5 F0_2_7

C6 F0_2_4

C7 F0_2_1

C8 F0_3_1

C9 FO_3_4

C10 F0_3_7

C11 F1_1_11

C12 F1_1_8

C13 F1_1_5*

C14 F1_1_2

C15 F1_0_0

C16 F1_0_3

C17 F1_0_7

C18 GND

C19 F1_2_10

C20 F1_2_9

D1 F0_0_6*

D2 F0_0_7

D3 F0_0_8

D4 GND

D5 F0_2_8

D6 done

D7 VCC

D8 VCC

D9 GND

D10 VCC

D11 VCC

D12 GND

D13 VCC

D14 VCC

D15 VCC

D16 F1_0_6

D17 GND

D18 F1_2_8

D19 F1_2_7

D20 F1_2_6*

Pkg

Ball Function

E1 F0_0_2*

E2 F0_0_3

E3 F0_0_4*

E4 F0_0_5

E17 F1_2_5

E18 F1_2_4

E19 F1_2_3

E20 F1_2_2

F1 F0_1_1

F2 F0_1_0*

F3 F0_0_0*

F4 F0_0_1

F17 F1_2_1

F18 F1_2_0

F19 F1_3_0

F20 F1_3_1

G1 F0_1_4*

G2 F0_1_3

G3 F0_1_2*

G4 VCC

G17 VCC

G18 F1_3_2*

G19 F1_3_3

G20 F1_3_4*

H1 F0_1_8

H2 F0_1_7

H3 F0_1_6

H4 F0_1_5

H17 F1_3_5

H18 F1_3_6

H19 F1_3_7

H20 F1_3_8

J1 F0_1_11

J2 F0_1_10

J3 F0_1_9

J4 GND

J17 GND

J18 F1_3_9

J19 F1_3_10

J20 F1_3_11

K1 clk_2

K2 clk_1

K3 clk_0

K4 VCC

K17 VCC

K18 clk_4

K19 clk_5

K20 clk_6

Pkg

Ball Function

L1 clk_3

L2 gts

L3 GND

L4 VCC

L17 VCC

L18 trstn

L19 GND

L20 CLK_7

M1 F3_3_11

M2 F3_3_10

M3 F3_3_9

M4 GND

M17 GND

M18 F2_1_9

M19 F2_1_10

M20 F2_1_11

N1 F3_3_8

N2 F3_3_7

N3 F3_3_6

N4 F3_3_5*

N17 F2_1_5*

N18 F2_1_6

N19 F2_1_7

N20 F2_1_8

P1 F3_3_4

P2 F3_3_3*

P3 F3_3_2

P4 VCC

P17 VCC

P18 F2_1_2

P19 F2_1_3*

P20 F2_1_4

R1 F3_3_1*

R2 F3_3_0

R3 F3_2_0

R4 F3_2_1*

R17 F2_0_1*

R18 F2_0_0

R19 F2_1_0

R20 F2_1_1*

T1 F3_2_2

T2 F3_2_3*

T3 F3_2_4

T4 F3_2_5

T17 F2_0_5

T18 F2_0_4

T19 F2_0_3*

T20 F2_0_2

Pkg

Ball Function

U1 F3_2_6*

U2 F3_2_7

U3 F3_2_8

U4 GND

U5 tdi

U6 VCC

U7 VCC

U8 VCC

U9 GND

U10 VCC

U11 VCC

U12 GND

U13 VCC

U14 VCC

U15 F2_2_6

U16 F2_2_8

U17 GND

U18 F2_0_8

U19 F2_0_7

U20 F2_0_6*

V1 F3_2_9

V2 F3_2_10

V3 GND

V4 tck

V5 F3_0_7

V6 F3_0_4*

V7 F3_0_1

V8 F3_1_1

V9 F3_1_4*

V10 F3_1_7

V11 F2_3_11

V12 F2_3_8

V13 F2_3_5*

V14 F2_3_2

V15 F2_2_0*

V16 F2_2_3

V17 F2_2_7

V18 GND

V19 F2_0_10

V20 F2_0_9

Pkg

Ball Function

W1 F3_2_11

W2 GND

W3 F3_0_9

W4 tms

W5 F3_0_6

W6 F3_0_3

W7 F3_0_0*

W8 F3_1_2

W9 F3_1_5

W10 F3_1_8

W11 F3_1_11

W12 F2_3_9

W13 F2_3_6*

W14 F2_3_3*

W15 F2_3_0

W16 F2_2_2*

W17 F2_2_5*

W18 F2_2_10

W19 GND

W20 F2_0_11

Y1 F3_0_11

Y2 F3_0_10

Y3 F3_0_8

Y4 tdo

Y5 F3_0_5*

Y6 F3_0_2*

Y7 F3_1_0*

Y8 F3_1_3

Y9 F3_1_6

Y10 F3_1_9

Y11 F3_1_10

Y12 F2_3_10

Y13 F2_3_7

Y14 F2_3_4

Y15 F2_3_1*

Y16 F2_2_1

Y17 F2_2_4

Y18 F2_2_9

Y19 F2_2_11

Y20 GND

*Represents multi-function pins

Philips Semiconductors Product specification

PZ3320C/PZ3320N320 macrocell SRAM CPLD

1999 Apr 16 36

Table 17. Pin Description

SYMBOL PIN NUMBER TYPE DESCRIPTION

VDD D7, D8, D10,

D11, D13, D14,

D15, G4, G17,

K4, K17, L4,

L17, P4, P17,

U6, U7, U8,

U10, U11, U13,

U14

–Positive power supply.

GND A1, B2, B19,

C3, C18, D4,

D9, D12, D17,

J4, J17, L3,

L19, M4, M17,

U4, U9, U12,

U17, V3, V18,

W2, W19, Y20

–Ground supply.

resetn B4 IDuring configuration, resetn forces the start of initialization. After configuration, resetn is a direct

input which can be used to asynchronously reset all the flip-flops. If the global reset is not being

used, this pin should be pulled high. If the rise time of the prgmn signal is greater than 1

microsecond, this signal must be held low until prgmn is high.

cclk A4 I/O In the master modes, cclk is an output which strobes configuration data in. In the slave or

synchronous peripheral mode, cclk is an input synchronous with the data on din or D[7:0]. After

configuration, this pin should be pulled low.

done D6 I/O done is a bi-directional signal with a weak pull-up resistor attached. As an output, done pulling

high indicates configuration is complete. As an input, a low level on done will delay the enabling

of user I/O. If only one device is used, this pin can be left floating. If multiple devices are daisy

chained, an external pull-up should be used.

prgmn C4 Iprgmn is an active-low input that forces the restart of configuration and initialization and resets the

boundary-scan circuitry. After configuration, the pin should be pulled high. This signal must have a rise

time less than 1 microsecond. If the rise time of this signal is greater than 1 microsecond, resetn must

be held low until prgmn is high.

spmi Y5 OSpecial purpose configuration pin that must be left floating during configuration for all

configuration modes. After configuration the pin is a user-programmable I/O, and no external

termination is required. See the section on terminations for more information.

mpmi W13 OSpecial purpose configuration pin that must be left floating during configuration for all

configuration modes. After configuration the pin is a user-programmable I/O, and no external

termination is required. See the section on terminations for more information.

din E1 IDuring slave serial or master serial configuration modes, din accepts serial configuration data

synchronous with cclk. During parallel configuration modes, din is the D[0] input. After

configuration, the pin is a user-programmable I/O, and no external termination is required. See the

section on terminations for more information.

M2 N17 IM2/M1/M0 are used to select the configuration mode. After configuration, the pins are

bl I/O d t l t i ti i i d S th ti t i ti

M0 G18 user-programmable I/O, and no external termination is required. See the section on terminations

for more information

M1 G20

for

information

M3 A6 I M3 should be pulled high during configuration for all configuration modes. After configuration, the pin

is a user-programmable I/O, and no external termination is required. See the section on terminations

for more information.

tdi

tdo

tck

tms

trstn

L18

Test Data In, Test Data Out, Test Clock, Test Mode Select, Test Reset are dedicated pins for

boundary-scan through the JTAG port. If JTAG is not being used, tdi, tck, tms, and trstn should

be terminated with a weak pull-up resistor. tdo can be left unterminated. See section on

terminations for more information.

hdc B7 OHigh During Configuration (hdc) is output high when the PZ3320 is in the configuration state.

hdc is used as a control output indicating that configuration is in progress. After configuration,

the pin is a user-programmable I/O, and no external termination is required. See the section on

terminations for more information.

ldcn V9 OLow During Configuration (ldcn) is output low when the PZ3320 is in the configuration state.

ldcn is used as a control output indicating that configuration is in progress. After configuration,

the pin is a user-programmable I/O, and no external termination is required. See the section on

terminations for more information.

Philips Semiconductors Product specification

PZ3320C/PZ3320N320 macrocell SRAM CPLD

1999 Apr 16 37

SYMBOL DESCRIPTIONTYPEPIN NUMBER

crcerrn C13 I/O crcerrn goes low when the PZ3320 detects a CRC error or an invalid peramble during

configuration. The PZ3320 that detected the error will go into the initialization state and will not

resume configuration until prgmn and resetn are both high. Once configuration has resumed

crcerrn will go high. During configuration, an internal pull-up is enabled. If only one device is

used, this pin can be left floating. If multiple devices are daisy chained, an external pull-up

should be used. After configuration, the pin is a user-programmable I/O, and no external

termination is required. See the section on terminations for more information.

gts L2 IGlobal 3-State is an active-high dedicated input used to 3-state the I/Os and activate the internal

pull-down resistors. If this feature is not used, the pin should be pulled low.

cs0n

cs1

wrn

B17

W17

B13

Ics0n/cs1/wrn are used in the peripheral configuration mode. The PZ3320 is selected when cs0n

and wrn are low and cs1 is high. After configuration, these pins are user-programmable I/O.

cs0N and wrn require no external termination. See the section on terminations for more

information. If cs1 is not used as an I/O after configuration in synchronous peripheral mode, the

tristate property should be used to disable the internal pull-down resistor. See the section on

synchronous peripheral configuration for more information.

A[19:0] N4, P2, R1,

R4, T2, P19,

U1, V6, Y6,

W7, Y7, V13,

W14, Y15,

V15, W16,

U20, T19, R17,

R20

OIn the master parallel configuration mode, A[19:0] address the configuration EEPROM. After

configuration, the pin is a user-programmable I/O, and no external termination is required. See

the section on terminations for more information.

D[7:0] G1, A5, G3,

D1, F2, F3, E3,

IDuring master parallel, peripheral, and slave parallel configuration modes, D[7:0] receive

configuration data. After configuration, the pin is a user-programmable I/O, and no external

termination is required. See the section on terminations for more information.

dout D20 ODuring configuration, dout is the serial data out that is used to drive the din of daisy-chained slave

devices. Data on dout changes on the falling edge of cclk. After configuration, the pin is a

user-programmable I/O, and no external termination is required. See the section on terminations

for more information.

Philips Semiconductors Product specification

PZ3320C/PZ3320N320 macrocell SRAM CPLD

1999 Apr 16 38

PZ3320 – 160-Pin Plastic Low Profile Quad Flat Package

SP00672

LQFP

160 121

120

41 80

Pin Functions

Function is Fast Module_Logic block_Macrocell. For example, F1_0_5 means Fast Module 1, Logic block 0, Macrocell 5.

Pin Function

1 F0_0_6*

2 F0_0_5

3 F0_0_4*

4 F0_0_3

5 F0_0_2*

6 F0_0_1

7 F0_0_0*

8 GND

9 F0_1_0*

10 F0_1_1

11 F0_1_2*

12 F0_1_3

13 F0_1_4*

14 F0_1_5

15 VCC

16 F0_1_6

17 GND

18 clk_0

19 clk_1

20 clk_2

21 clk_3

22 gts

23 VCC

24 GND

25 F3_3_6

26 F3_3_5*

27 F3_3_4

28 F3_3_3*

29 F3_3_2

30 F3_3_1*

31 F3_3_0

32 GND

Pin Function

33 F3_2_0

34 F3_2_1*

35 F3_2_2

36 F3_2_3*

37 F3_2_4

38 F3_2_5

39 F3_2_6*

40 VCC

41 TCK

42 TDI

43 TMS

44 TDO

45 F3_0_6

46 F3_0_5*

47 GND

48 F3_0_4*

49 F3_0_3

50 F3_0_2*

51 F3_0_1

52 F3_0_0*

53 VCC

54 F3_1_0*

55 F3_1_1

56 F3_1_2

57 F3_1_3

58 F3_1_4*

59 F3_1_5

60 GND

61 F3_1_6

62 VCC

63 F2_3_6*

64 GND

Pin Function

65 F2_3_5*

66 F2_3_4

67 F2_3_4*

68 F2_3_2

69 F2_3_1*

70 F2_3_0

71 VCC

72 F2_2_0*

73 F2_2_1

74 F2_2_2*

75 F2_2_3

76 F2_2_4

77 GND

78 F2_2_5*

79 F2_2_6

80 VCC

81 VCC

82 F2_0_6*

83 F2_0_5

84 F2_0_4

85 F2_0_3*

86 F2_0_2

87 F2_0_1*

88 F2_0_0

89 GND

90 F2_1_0

91 F2_1_1*

92 F2_1_2

93 F2_1_3*

94 F2_1_4

95 F2_1_5*

96 F2_1_6

Pin Function

97 TRSTN

98 GND

99 VCC

100 CLK_7

101 CLK_6

102 CLK_5

103 CLK_4

104 GND

105 F1_3_6

106 VCC

107 F1_3_5

108 F1_3_4*

109 F1_3_3

110 F1_3_2*

111 F1_3_1

112 F1_3_0

113 GND

114 F1_2_0

115 F1_2_1

116 F1_2_2

117 F1_2_3

118 F1_2_4

119 F1_2_5

120 F1_2_6*

121 VCC

122 F1_0_6

123 F1_0_5*

124 GND

125 F1_0_4

126 F1_0_3

127 F1_0_2

128 F1_0_1

Pin Function

129 F1_0_0

130 VCC

131 F1_1_0

132 F1_1_1

133 F1_1_2

134 F1_1_3

135 F1_1_4

136 F1_1_5*

137 GND

138 F1_1_6*

139 VCC

140 F0_3_6

141 GND

142 F0_3_5

143 F0_3_4

144 F0_3_3

145 F0_3_2

146 F0_3_1

147 F0_3_0

148 VCC

149 F0_2_0*

150 F0_2_1

151 F0_2_2*

152 F0_2_3

153 F0_2_4

154 GND

155 F0_2_5*

156 F0_2_6

157 CCLK

158 DONE

159 RESETN

160 PGRM

*Represents multi-function pins

Philips Semiconductors Product specification

PZ3320C/PZ3320N320 macrocell SRAM CPLD

1999 Apr 16 39

Table 18. Pin Description

SYMBOL PIN NUMBER TYPE DESCRIPTION

VDD 15, 23, 40, 53,

62, 71, 80, 81,

99, 106, 121,

130, 139, 148

–Positive power supply.

GND 8, 17, 24, 32,

47, 60, 64, 77,

89, 98, 104,

113, 124, 137,

141, 154

–Ground supply.

resetn 159 IDuring configuration, resetn forces the start of initialization. After configuration, resetn is a direct

input which can be used to asynchronously reset all the flip-flops. If the global reset is not being

used, this pin should be pulled high. If the rise time of the prgmn signal is greater than 1

microsecond, this signal must be held low until prgmn is high.

cclk 157 I/O In the master modes, cclk is an output which strobes configuration data in. In the slave or

synchronous peripheral mode, cclk is an input synchronous with the data on din or D[7:0]. After

configuration, this pin should be pulled low.

done 158 I/O done is a bi-directional signal with a weak pull-up resistor attached. As an output, done pulling

high indicates configuration is complete. As an input, a low level on done will delay the enabling

of user I/O. If only one device is used, this pin can be left floating. If multiple devices are daisy

chained, an external pull-up should be used.

prgmn 160 Iprgmn is an active-low input that forces the restart of configuration and initialization and resets the

boundary-scan circuitry. After configuration, the pin should be pulled high. This signal must have a rise

time less than 1 microsecond. If the rise time of this signal is greater than 1 microsecond, resetn must

be held low until prgmn is high.

spmi 46 OSpecial purpose configuration pin that must be left floating during configuration for all

configuration modes. After configuration the pin is a user-programmable I/O, and no external

termination is required. See the section on terminations for more information.

mpmi 63 OSpecial purpose configuration pin that must be left floating during configuration for all

configuration modes. After configuration the pin is a user-programmable I/O, and no external

termination is required. See the section on terminations for more information.

din 5 I During slave serial or master serial configuration modes, din accepts serial configuration data

synchronous with cclk. During parallel configuration modes, din is the D[0] input. After

configuration, the pin is a user-programmable I/O, and no external termination is required. See the

section on terminations for more information.

M2 95 IM2/M1/M0 are used to select the configuration mode. After configuration, the pins are

bl I/O d t l t i ti i i d S th ti t i ti

M0 110 user-programmable I/O, and no external termination is required. See the section on terminations

for more information

M1 108

for

information

M3 151 I M3 should be pulled high during configuration for all configuration modes. After configuration, the pin

is a user-programmable I/O, and no external termination is required. See the section on terminations

for more information.

tdi

tdo

tck

tms

trstn

Test Data In, Test Data Out, Test Clock, Test Mode Select, Test Reset are dedicated pins for

boundary-scan through the JTAG port. If JTAG is not being used, tdi, tck, tms, and trstn should

be terminated with a weak pull-up resistor. tdo can be left unterminated. See section on

terminations for more information.

hdc 149 OHigh During Configuration (hdc) is output high when the PZ3320 is in the configuration state.

hdc is used as a control output indicating that configuration is in progress. After configuration,

the pin is a user-programmable I/O, and no external termination is required. See the section on

terminations for more information.

ldcn 58 OLow During Configuration (ldcn) is output low when the PZ3320 is in the configuration state.

ldcn is used as a control output indicating that configuration is in progress. After configuration,

the pin is a user-programmable I/O, and no external termination is required. See the section on

terminations for more information.

crcerrn 136 I/O crcerrn goes low when the PZ3320 detects a CRC error or an invalid peramble during

configuration. The PZ3320 that detected the error will go into the initialization state and will not

resume configuration until prgmn and resetn are both high. Once configuration has resumed

crcerrn will go high. During configuration, an internal pull-up is enabled. If only one device is

used, this pin can be left floating. If multiple devices are daisy chained, an external pull-up

should be used. After configuration, the pin is a user-programmable I/O, and no external

termination is required. See the section on terminations for more information.

Philips Semiconductors Product specification

PZ3320C/PZ3320N320 macrocell SRAM CPLD

1999 Apr 16 40

SYMBOL DESCRIPTIONTYPEPIN NUMBER

gts 22 IGlobal 3-State is an active-high dedicated input used to 3-state the I/Os and activate the internal

pull-down resistors. If this feature is not used, the pin should be pulled low.

cs0n

cs1

wrn

123

138

Ics0n/cs1/wrn are used in the peripheral configuration mode. The PZ3320 is selected when cs0n

and wrn are low and cs1 is high. After configuration, these pins are user-programmable I/O.

cs0N and wrn require no external termination. See the section on terminations for more

information. If cs1 is not used as an I/O after configuration in synchronous peripheral mode, the

tristate property should be used to disable the internal pull-down resistor. See the section on

synchronous peripheral configuration for more information.

A[19:0] 26, 28, 30, 34,

36, 93, 39, 48,

50, 52, 54, 65,

67, 69, 72, 74,

82, 85, 87, 91

OIn the master parallel configuration mode, A[19:0] address the configuration EEPROM. After

configuration, the pin is a user-programmable I/O, and no external termination is required. See

the section on terminations for more information.

D[7:0] 13, 155, 11, 1,

9, 7, 3, 5 IDuring master parallel, peripheral, and slave parallel configuration modes, D[7:0] receive

configuration data. After configuration, the pin is a user-programmable I/O, and no external

termination is required. See the section on terminations for more information.

dout 120 ODuring configuration, dout is the serial data out that is used to drive the din of daisy-chained slave

devices. Data on dout changes on the falling edge of cclk. After configuration, the pin is a

user-programmable I/O, and no external termination is required. See the section on terminations

for more information.

Philips Semiconductors Product specification

PZ3320C/PZ3320N320 macrocell SRAM CPLD

1999 Apr 16 41

BGA256: plastic ball grid array package; 256 balls; body 27 x 27 x 1.55 mm SOT471-1

Philips Semiconductors Product specification

PZ3320C/PZ3320N320 macrocell SRAM CPLD

1999 Apr 16 42

LQFP160: plastic low profile quad flat package; 160 leads; body 24 x 24 x 1.4 mm SOT435-1

Philips Semiconductors Product specification

PZ3320C/PZ3320N320 macrocell SRAM CPLD

1999 Apr 16 43

NOTES

Philips Semiconductors Product specification

PZ3320C/PZ3320N320 macrocell SRAM CPLD

1999 Apr 16 44

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.

Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or

at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended

periods may af fect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips

Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or

modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can

reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications

do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard

cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no

responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these

products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless

otherwise specified.

Philips Semiconductors

811 East Arques A venue

P.O. Box 3409

Sunnyvale, California 94088–3409

Telephone 800-234-7381

 Copyright Philips Electronics North America Corporation 1999

Date of release: 04-99

Document order number: 9397 750 05502

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Data sheet

status

Objective

specification

Preliminary

specification

Product

specification

Product

status

Development

Qualification

Production

Definition [1]

This data sheet contains the design target or goal specifications for product development.

Specification may change in any manner without notice.

This data sheet contains preliminary data, and supplementary data will be published at a later date.

Philips Semiconductors reserves the right to make chages at any time without notice in order to

improve design and supply the best possible product.

This data sheet contains final specifications. Philips Semiconductors reserves the right to make

changes at any time without notice in order to improve design and supply the best possible product.

Data sheet status

[1] Please consult the most recently issued datasheet before initiating or completing a design.