TPS43350-Q1 TPS43351-Q1 www.ti.com SLVSAR7B - JUNE 2011 - REVISED MAY 2012 LOW IQ, DUAL SYNCHRONOUS BUCK CONTROLLER Check for Samples: TPS43350-Q1, TPS43351-Q1 FEATURES 1 * * 2 * * * * * * * Qualified for Automotive Applications AEC-Q100 Test Guidance With the Following Results: - Device Temperature Grade 1: -40C to 125C Ambient Operating Temperature - Device HBM ESD Classification Level H2 - Device HBM CDM Classification Level C2 Two Synchronous Buck Controllers Input Range up to 40 V, (Transients up to 60 V) Low-Power Mode IQ: 30 A (One Buck On), 35 A (Two Bucks On) Low Shutdown Current Ish < 4 A Buck Output Range 0.9 V to 11 V Programmable Frequency and External Synchronization Range 150 kHz to 600 kHz Separate Enable Inputs (ENA, ENB) * * * * * * Frequency Spread Spectrum (TPS43351-Q1) Selectable Forced Continuous Mode or Automatic Low-Power Mode at Light Loads Sense Resistor or Inductor DCR Sensing Out-of-Phase Switching Between Buck Channels Peak Gate Drive Current 1.5 A Thermally Enhanced, 38-Pin HTSSOP (DAP) PowerPADTM Package APPLICATIONS * * Automotive Infotainment, Navigation, and Instrument Cluster Systems Industrial/Automotive Multi-Rail DC Power Distribution Systems and Electronic Control Units DESCRIPTION The TPS43350-Q1 and TPS43351-Q1 include two current-mode synchronous buck controllers designed for the harsh environment in automotive applications. The part is ideally suited for a multi-rail system with low quiescent requirements, as the part automatically operates in low-power mode (consuming only 30 A) at light loads. The part offers protection features such as thermal, soft-start, and overcurrent protection. During short-circuit conditions of the regulator output, the current through the MOSFETs can be limited for power dissipation by activation of the current foldback feature. The two independent soft-start inputs allow ramp-up of the output voltage independently during start-up. The switching frequency can be programmed over 150 kHz to 600 kHz or synchronized to an external clock in the same range. Additionally, the TPS43351-Q1 offers frequency-hopping spread-spectrum operation. spacer VBAT Reverse Battery MOSFET Control SYNC VBUCKA BUCKA Internal VREG RCOSC External Sync ENA SSA Buck Enalbe SSA DLYAB SoftStart BUCKB ENB VBUCKB Figure 1. Typical Application Diagram 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2011-2012, Texas Instruments Incorporated TPS43350-Q1 TPS43351-Q1 SLVSAR7B - JUNE 2011 - REVISED MAY 2012 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION (1) (2) TJ -40C to 150C (1) (2) OPTION PACKAGE Frequency-hopping spread spectrum OFF Frequency-hopping spread spectrum ON DAP ORDERABLE PART NUMBER TPS43350QDAPRQ1 TPS43351QDAPRQ1 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI Web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. ABSOLUTE MAXIMUM RATINGS (1) Voltage MIN MAX Input voltage: VIN, VBAT -0.3 60 V Enable inputs: ENA, ENB -0.3 60 V Bootstrap inputs: CBA, CBB -0.3 68 V Phase inputs: PHA, PHB -0.7 60 V Phase inputs: PHA, PHB (for 150 ns) Voltage (Buck function: BuckA and BuckB) Voltage (PMOS driver) Temperature -1 -0.3 13 V Error amplifier outputs: COMPA, COMPB -0.3 13 V High-side MOSFET driver: GA1-PHA, GB1-PHB -0.3 8.8 V Low-side MOSFET drivers: GA2, GB2 -0.3 8.8 V Current-sense voltage: SA1, SA2, SB1, SB2 -0.3 13 V Soft start: SSA, SSB -0.3 13 V Power-good output: PGA, PGB -0.3 13 V Power-good delay: DLYAB -0.3 13 V Switching-frequency timing resistor: RT -0.3 13 V SYNC, EXTSUP -0.3 13 V P-channel MOSFET driver: GC2 -0.3 60 V P-channel MOSFET driver: VIN-GC2 -0.3 8.8 V Gate-driver supply: VREG -0.3 8.8 V Junction temperature: TJ -40 150 C Operating temperature: TA -40 125 C Storage temperature: Tstg -55 165 C Charged-device model (CDM) AEC-Q11 Classification Level C2 Machine model (MM) (1) 2 V Feedback inputs: FBA, FBB Human-body model (HBM) AECQ11 Classification Level H2 Electrostatic discharge ratings UNIT 2 FBA, FBB, RT, DLYAB 400 VBAT, SYNC, VIN 750 All other pins 500 PGA, PGB 150 All other pins 200 kV V Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to GND. Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS43350-Q1 TPS43351-Q1 TPS43350-Q1 TPS43351-Q1 www.ti.com SLVSAR7B - JUNE 2011 - REVISED MAY 2012 THERMAL INFORMATION TPS4335x-Q1 THERMAL METRIC (1) DAP UNIT 38 PINS Junction-to-ambient thermal resistance (2) JA (3) 27.3 JCtop Junction-to-case (top) thermal resistance JB Junction-to-board thermal resistance (4) 15.9 JT Junction-to-top characterization parameter (5) 0.24 JB Junction-to-board characterization parameter (6) 6.6 JCbot Junction-to-case (bottom) thermal resistance (7) 1.2 (1) (2) (3) (4) (5) (6) (7) 19.6 C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, JT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining JA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, JB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining JA , using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. RECOMMENDED OPERATING CONDITIONS Buck function: BuckA and BuckB voltage MIN MAX Input voltage: VIN, VBAT 4 40 V Enable inputs: ENA, ENB 0 40 V Boot inputs: CBA, CBB 4 48 V -0.6 40 V Current-sense voltage: SA1, SA2, SB1, SB2 0 11 V Power-good output: PGA, PGB 0 11 V SYNC, EXTSUP 0 9 V -40 125 C Phase inputs: PHA, PHB Operating temperature: TA Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS43350-Q1 TPS43351-Q1 Submit Documentation Feedback UNIT 3 TPS43350-Q1 TPS43351-Q1 SLVSAR7B - JUNE 2011 - REVISED MAY 2012 www.ti.com DC ELECTRICAL CHARACTERISTICS VIN = 8 V to 18 V, TJ = -40C to 150C (unless otherwise noted) NO. PARAMETER 1.0 Input Supply 1.1 VBat 1.2 1.3 VIN VIN TEST CONDITIONS MIN Supply voltage After initial start-up, condition is satisfied. Device operating range Input voltage required for device on initial start-up Buck undervoltage lockout Iq_LPM_ LPM quiescent current: TA = 25C (1) 40 V 40 V 4 40 V 3.6 3.8 V 3.8 4 V 30 40 A 35 45 A 40 50 A 45 55 A 4.85 5.3 mA 7 7.6 mA 5 5.5 mA VIN = 13 V, BuckA, B: CCM 7.5 8 mA BuckA, B: off, VBat = 13 V 2.5 4 A VIN falling 3.5 VIN rising VIN = 13 V, BuckB: LPM, BuckA: off VIN = 13 V, BuckA, B: LPM VIN = 13 V, BuckA: LPM, BuckB: off 1.6 Iq_LPM LPM quiescent current: TA = 125C (1) UNIT 4 VIN = 13 V, BuckA: LPM, BuckB: off 1.5 MAX 6.5 Buck regulator operating range after initial start-up UV TYP VIN = 13 V, BuckB: LPM, BuckA: off VIN = 13 V, BuckA, B: LPM Normal operation, SYNC = 5 V 1.7 Iq_NRM VIN = 13 V, BuckA: CCM, BuckB: off Quiescent current: TA = 25C (1) VIN = 13 V, BuckB: CCM, BuckA: off VIN = 13 V, BuckA, B: CCM Normal operation, SYNC = 5V VIN = 13 V, BuckA: CCM, BuckB: off 1.8 Iq_NRM Quiescent current: TA = 125C (1) 1.9 Ibat_sh Shutdown current 2.0 Input Voltage VIN - Overvoltage Lockout 2.1 VOVLO Overvoltage shutdown 2.2 OVLOHys Hysteresis 2.3 OVLOfilter Filter time VIN = 13 V, BuckB: CCM, BuckA: off VIN rising 45 46 47 V VIN falling 43 44 45 V 1 2 3 5 V s Gate Driver for PMOS 3.1 rDS(on) PMOS OFF 3.2 IPMOS_ON Gate current VIN = 13.5 V, Vgs = -5 V 3.3 tdelay_ON Turnon delay C = 10 nF 4.0 Buck Controllers 4.1 VBuckA/B Adjustable output voltage range 4.2 Vref, NRM Internal reference voltage in normal mode Measure FBX pin 4.3 Vref, LPM Internal reference voltage in low power mode Measure FBX pin V sense for forward current limit in CCM Maximum sense voltage FBx = 0.75 V (low duty cycles) V sense for reverse current limit in CCM Minimum sense voltage FBx = 1 V Sense voltage in foldback FBx = 0 V 4.4 Vsense 4.5 (1) 4 10 4.6 VI-Foldback V sense for output short 4.7 tdead Shoot-through delay, blanking time 4.8 DCNRM Duty cycle 4.9 DCLPM Duty cycle LPM 20 10 5 10 s 11 V 0.800 0.808 V 0.9 0.792 Internal tolerance on reference -1% 0.784 Internal tolerance on reference 1% 0.800 -2% High-side minimum on-time Maximum duty cycle (digitally controlled) mA 0.816 V 2% 60 75 90 mV -65 -37.5 -23 mV 17 32.5 48 mV 100 ns 100 ns 98.75% 80% Quiescent current specification is non-switching current consumption without including the current in the external feedback resistor divider. Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS43350-Q1 TPS43351-Q1 TPS43350-Q1 TPS43351-Q1 www.ti.com SLVSAR7B - JUNE 2011 - REVISED MAY 2012 DC ELECTRICAL CHARACTERISTICS (continued) VIN = 8 V to 18 V, TJ = -40C to 150C (unless otherwise noted) NO. PARAMETER ILPM_Entry 4.10 ILPM_Exit TEST CONDITIONS LPM entry threshold load current as fraction of maximum set load current LPM exit threshold load current as fraction of maximum set load current MIN TYP MAX UNIT 1% The exit threshold is specified to be always higher than entry threshold 10% High-Side External NMOS Gate Drivers for Buck Controller 4.11 IGX1_peak Gate driver peak current 4.12 rDS(on) Source and sink driver 1.5 VREG = 5.8 V, IGX1 current = 200 mA A 2 2 Low-Side NMOS Gate Drivers for Buck Controller 4.13 IGX2_peak Gate-driver peak current 4.14 rDS(on) Source and sink driver 1.5 VREG = 5.8 V, IGX2 current = 200 mA A Error Amplifier (OTA) for Buck Converters 4.15 GmBUCK Transconductance COMPA, COMPB = 0.8 V, source/sink = 5 A, test in feedback loop 4.16 IPULLUP_FBx Pullup current at FBx pins 5.0 Digital Inputs: ENA, ENB, SYNC 5.1 Vih 5.2 Vil 5.3 5.4 0.72 1 1.35 mS FBx = 0 V 50 100 200 nA Higher threshold VIN = 13 V 1.7 Lower threshold VIN = 13 V Rih_SYNC Resistance VSYNC = 5 V, SYNC: pulldown resistance 500 k Ril_ENC Resistance VENC = 5 V, ENC: pulldown resistance 500 k Pullup current VENx = 0 V, ENA, ENB: pull up current source 0.5 2 A V 0.7 V 5.5 Iil_ENx 6.0 Switching Parameters - Buck DC-DC Controllers 6.1 fSW_Buck Buck switching frequency RT pin: GND 360 400 440 kHz 6.2 fSW_Buck Buck switching frequency RT pin: 60-k external resistor 360 400 440 kHz 6.3 fSW_adj Buck adjustable range RT pin: using external resistor 150 600 kHz 6.4 fSYNC Buck synch. range External clock input 150 600 kHz 6.5 fSS Spread-spectrum spreading TPS43351 only 7.0 Internal Gate-Driver Supply 5.8 6.1 V 7.1 VREG 0.2% 1% 7.5 7.8 7.2 VREG-EXTSUP 0.2% 1% 7.3 4.6 4.8 V 150 250 mV 5% Internal regulated supply VIN = 8 V to 18 V, EXTSUP = 0 V, SYNC = High Load regulation IVREG = 0 mA to 100 mA, EXTSUP = 0 V, SYNC = high Internal regulated supply EXTSUP = 8.5 V Load regulation IEXTSUP = 0 mA to 125 mA, SYNC = High EXTSUP = 8.5 V to 13 V VEXTSUP-VREG Switchover voltage IVREG = 0 mA to 100 mA , EXTSUP ramping positive 7.4 VEXTSUP-Hys Switchover hysteresis 7.5 IREG-Limit Current limit on VREG EXTSUP = 0 V, normal mode as well as LPM 100 400 mA 7.6 IREG_EXTSUP- Current limit on VREG when using EXTSUP IVREG = 0 mA to 100 mA, EXTSUP = 8.5 V, SYNC = High 125 400 mA Soft-start source current SSA and SSB = 0 V 0.75 1.25 A Limit 8.0 Soft Start 8.1 ISSx 9.0 Oscillator (RT) 9.1 VRT 10.0 Power Good / Delay 10.1 PGpullup Pullup for A and B internal pullup to Sx2 10.2 PGth1 Power-good threshold FBx falling 10.3 PGhys Hysteresis 10.4 PGdrop Voltage drop 5.5 7.2 4.4 Oscillator reference voltage 1 1.2 V 50 -5% -7% V k -9% 2% 10.5 IPGA = 5 mA 450 mV IPGA = 1 mA 100 mV 1 A 16 us 10.6 PGleak Leakage VSx2 = VPGx = 13 V 10.7 tdeglitch Deglitch time Power-good deglitch Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS43350-Q1 TPS43351-Q1 2 Submit Documentation Feedback 5 TPS43350-Q1 TPS43351-Q1 SLVSAR7B - JUNE 2011 - REVISED MAY 2012 www.ti.com DC ELECTRICAL CHARACTERISTICS (continued) VIN = 8 V to 18 V, TJ = -40C to 150C (unless otherwise noted) NO. 6 PARAMETER TEST CONDITIONS 10.8 tdelay Reset delay External capacitor = 1 nF VBUCKX < PGth1 MIN TYP MAX 1 UNIT ms 10.9 tdelay_fix Fixed reset delay No external capacitor, pin open 20 50 s 10.10 Ioh Activate current source Current to charge external capacitor 30 40 50 A 10.11 Iil Activate current sink Current to discharge external capacitor 30 40 50 A 11.0 Overtemperature Protection 11.1 Tshutdown 150 165 C 11.2 Thys 15 C Shutdown threshold Submit Documentation Feedback Junction temperature Hysteresis Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS43350-Q1 TPS43351-Q1 TPS43350-Q1 TPS43351-Q1 www.ti.com SLVSAR7B - JUNE 2011 - REVISED MAY 2012 DEVICE INFORMATION DAP Package (Top View) VBAT 1 28 VIN NC 2 37 EXTSUP NC 3 36 NC GC2 4 35 VREG CBA 5 34 CBB GA1 6 33 GB1 PHA 7 32 PHB GA2 8 31 GB2 PGNDA 9 30 PGNDB SA1 10 29 SB1 SA2 11 28 SB2 FBA 12 27 FBB COMPA 13 26 COMPB SSA 14 25 SSB PGA 15 24 PGB ENA 16 23 AGND ENB 17 22 RT NC 18 21 DLYAB AGND 19 20 SYNC PIN FUNCTIONS NAME NO. I/O 19, 23 O Analog ground reference CBA 5 I A capacitor on this pin acts as the voltage supply for the high-side N-channel MOSFET gate-drive circuitry in buck controller BuckA. When the buck is in a dropout condition, the device automatically reduces the duty cycle of the high-side MOSFET to approximately 95% on every fourth cycle to allow the capacitor to recharge. CBB 34 I A capacitor on this pin acts as the voltage supply for the high-side N-channel MOSFET gate-drive circuitry in buck controller BuckB. When the buck is in a dropout condition, the device automatically reduces the duty cycle of the high-side MOSFET to approximately 95% on every fourth cycle to allow the capacitor to recharge. COMPA 13 O Error-amplifier output of BuckA and compensation node for voltage loop stability. The voltage at this node sets the target for the peak current through the inductor of BuckA. This voltage is clamped on the upper and lower ends to provide current-limit protection for the external MOSFETs. COMPB 26 O Error amplifier output of BuckB and compensation node for voltage loop stability. The voltage at this node sets the target for the peak current through the inductor of BuckB. This voltage is clamped on the upper and lower ends to provide current-limit protection for the external MOSFETs. DLYAB 21 O The capacitor at the DLYAB pin sets the power-good delay interval used to de-glitch the outputs of the powergood comparators. When this pin is left open, the power-good delay is set to an internal default value of 20 s typical. ENA 16 I Enable inputs for BuckA (active-high with an internal pullup current source). An input voltage higher than 1.5 V enables the controller, whereas an input voltage lower than 0.7 V disables the controller. When both ENA and ENB are low, the device is shut down and consumes less than 4 A of current. ENB 17 I Enable inputs for BuckB (active-high with an internal pullup current source). An input voltage higher than 1.5 V enables the controller, whereas an input voltage lower than 0.7 V disables the controller. When both ENA and ENB are low, the device is shut down and consumes less than 4 A of current. EXTSUP 37 I EXTSUP can be used to supply the VREG regulator from one of the TPS43350-Q1 or TPS43351-Q1 buck regulator rails to reduce power dissipation in cases where VIN is expected to be high. When EXTSUP is open or lower than 4.6 V, the regulator is powered from VIN. FBA 12 I Feedback voltage pin for BuckA. The buck controller regulates the feedback voltage to the internal reference of 0.8 V. A suitable resistor divider network between the buck output and the feedback pin sets the desired output voltage. FBB 27 I Feedback voltage pin for BuckB. The buck controller regulates the feedback voltage to the internal reference of 0.8 V. A suitable resistor divider network between the buck output and the feedback pin sets the desired output voltage. AGND DESCRIPTION Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS43350-Q1 TPS43351-Q1 Submit Documentation Feedback 7 TPS43350-Q1 TPS43351-Q1 SLVSAR7B - JUNE 2011 - REVISED MAY 2012 www.ti.com PIN FUNCTIONS (continued) NAME NO. I/O DESCRIPTION GA1 6 O External high-side N-channel MOSFET for buck regulator BuckA can be driven from this output. The output provides high peak currents to drive capacitive loads. The gate drive is referred to a floating ground reference provided by PHA and has a voltage swing provided by CBA. GA2 8 O External low-side N-channel MOSFET for buck regulator BuckA can be driven from this output. The output provides high peak currents to drive capacitive loads. The voltage swing on this pin is provided by VREG. GB1 33 O External high-side N-channel MOSFET for buck regulator BuckB can be driven from this output. The output provides high peak currents to drive capacitive loads. The gate drive is referred to a floating ground reference provided by PHB and has a voltage swing provided by CBB. GB2 31 O External low-side N-channel MOSFETs forbuck regulator BuckB can be driven from this output. The output provides high peak currents to drive capacitive loads. The voltage swing on this pin is provided by VREG. GC2 4 O A floating output drive to control the external P-channel MOSFET is available at this pin. This MOSFET can be used to bypass a reverse-protection diode, and thus reduce power losses. 2, 3, 18, 36 - PGNDA 9 O Power ground connection to the source of the low-side N-channel MOSFETs of BuckA. PGNDB 30 O Power ground connection to the source of the low-side N-channel MOSFETs of BuckB PGA 15 O Open-drain power-good indicator pin for BuckA. An internal power-good comparator monitors the voltage at the feedback pin and pulls this output low when the output voltage falls below 93% of the set value. PGB 24 O Open-drain power-good indicator pin for BuckB. An internal power-good comparator monitors the voltage at the feedback pin and pulls this output low when the output voltage falls below 93% of the set value. PHA 7 O Switching terminal of buck regulator BuckA, providing a floating ground reference for the high-side MOSFET gatedriver circuitry and used to sense current reversal in the inductor when discontinuous-mode operation is desired. PHB 32 O Switching terminal of buck regulator BuckB, providing a floating ground reference for the high-side MOSFET gatedriver circuitry and used to sense current reversal in the inductor when discontinuous-mode operation is desired. RT 22 O The operating switching frequency of the buck controllers is set by connecting a resistor to ground on this pin. A short circuit to ground on this pin defaults operation to 400 kHz for the buck controllers. SA1 10 I SA2 11 I SB1 29 I SB2 28 I SSA 14 O Soft-start or tracking input for buck controller BuckA. The buck controller regulates the FBA voltage to the lower of 0.8 V or the SSA pin voltage. An internal pullup current source of 1 A is present at the pin, and an appropriate capacitor connected here can be used to set the soft-start ramp interval. A resistor divider connected to another supply can also be used to provide a tracking input to this pin. SSB 25 O Soft-start or tracking input for buck controller BuckB. The buck controller regulates the FBB voltage to the lower of 0.8 V or the SSB pin voltage. An internal pullup current source of 1 A is present at the pin, and an appropriate capacitor connected here can be used to set the soft-start ramp interval. A resistor divider connected to another supply can also be used to provide a tracking input to this pin. NC High-impedance differential-voltage inputs from the current-sense element (sense resistor or inductor DCR) for each buck controller. The current-sense element should be chosen to set the maximum current through the inductor based on the current-limit threshold (subject to tolerances) and considering the typical characteristics across duty cycle and VIN. (SA1 positive node, SA2 negative node) High-Impedance differential-voltage inputs from the current-sense element (sense resistor or inductor DCR) for each buck controller. The current-sense element should be chosen to set the maximum current through the inductor based on the current-limit threshold (subject to tolerances) and considering the typical characteristics across duty cycle and VIN. (SB1 positive node, SB2 negative node) SYNC 20 I If an external clock is present on this pin, the device detects it, and the internal PLL locks on to the external clock. This overrides the internal oscillator frequency. The device can synchronize to frequencies from 150 kHz to 600 kHz. A high logic level on this pin ensures forced continuous-mode operation of the buck controllers and inhibits transition to low-power mode. An open or low allows discontinuous-mode operation and entry into low-power mode at light loads. On the TPS43351, a high level enables frequency-hopping spread spectrum, whereas an open or a low level disables it. VBAT 1 I Supply pin VIN 38 I Main input pin. This is the buck controller input pin. Additionally, it powers the internal control circuits of the device. O An external capacitor on this pin is required to provide a regulated supply for the gate drivers of the buck controllers. A capacitance in the order of 4.7 F is recommended. The regulator can be used such that it is either powered from VIN or EXTSUP. This pin has current-limit protection and should not be used to drive any other loads. VREG 8 35 Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS43350-Q1 TPS43351-Q1 TPS43350-Q1 TPS43351-Q1 www.ti.com SLVSAR7B - JUNE 2011 - REVISED MAY 2012 VIN 38 VBAT 1 EXTSUP 37 VREG 35 RT 22 Gate Driver Supply CBA 6 GA1 7 PHA 8 GA2 9 PGNDA 10 SA1 - 11 SA2 - 12 FBA 13 COMPA 15 PGA 34 CBB 33 GB1 32 PHB 31 GB2 30 PGNDB 29 SB1 28 SB2 27 FBB 26 COMPB 24 PGB PWM logic VREG Internal Oscillator Slope Comp 180deg SYNC 5 Internal ref (Band gap) 20 + SYNC &LPM + + Current Sense Amp - GC2 Source/Sink Logic 4 PWM comp gm OTA + + 0.8 V SSA EN 1A - SSA FBA SA2 14 ENA VIN VIN 500 nA 500 nA ENA 16 ENB 17 SSB 25 + 1A ENB VREF 40 A DLYAB Second Buck Controller Channel 21 40 A AGND 23 Figure 2. Functional Block Diagram Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS43350-Q1 TPS43351-Q1 Submit Documentation Feedback 9 TPS43350-Q1 TPS43351-Q1 SLVSAR7B - JUNE 2011 - REVISED MAY 2012 www.ti.com TYPICAL CHARACTERISTICS EFFICIENCY ACROSS OUTPUT CURRENTS (BUCKS) VIN = 12V, VOUT = 5V, SWITCHING FREQUENCY = 400kHz INDUCTOR = 4.7H, RSENSE = 10mW 90 10000 EFFICIENCY, SYNC = LOW 1000 EFFICIENCY (%) 80 70 60 POWER LOSS, SYNC = HIGH 100 50 40 POWER LOSS, SYNC = LOW 30 10 1 20 EFFICIENCY, SYNC = HIGH 10 0 0.0001 POWER LOSS (mW) 100 0.1 0.001 0.01 0.1 1 10 OUTPUT CURRENT (A) Figure 3. Figure 4. SOFT-START OUTPUTS (BUCK) VOUTA VOUTB 1V/DIV 2ms/DIV Figure 5. 10 Submit Documentation Feedback Figure 6. Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS43350-Q1 TPS43351-Q1 TPS43350-Q1 TPS43351-Q1 www.ti.com SLVSAR7B - JUNE 2011 - REVISED MAY 2012 TYPICAL CHARACTERISTICS (continued) BUCK LOAD STEP: LOW POWER MODE EXIT (90 mA TO 4 A AT 2.5 A/s) VIN = 12 V, VOUT = 5 V, SWITCHING FREQUENCY = 400 kHz INDUCTOR = 4.7 H, RSENSE = 10 mW 100 mV/DIV VOUT AC-COUPLED 2 A/DIV IIND 50 s/DIV Figure 7. Figure 8. Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS43350-Q1 TPS43351-Q1 Submit Documentation Feedback 11 TPS43350-Q1 TPS43351-Q1 SLVSAR7B - JUNE 2011 - REVISED MAY 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) BUCKx PEAK CURRENT LIMIT vs. COMPx VOLTAGE PEAK CURRENT SENSE VOLTAGE (mV) NO-LOAD QUIESCENT CURRENT ACROSS TEMPERATURE Quiescent Current (A) 60 50 BOTH BUCKS ON 40 30 ONE BUCK ON 20 10 NEITHER BUCK ON 0 -40 -15 10 85 35 60 Temperature (C) 110 135 160 75 62.5 50 37.5 25 12.5 SYNC = LOW 0 -12.5 -25 SYNC = HIGH -37.5 0.65 0.8 0.95 FOLDBACK CURRENT LIMIT (BUCK) 150C 25C 3 5 4 6 7 8 9 10 11 12 PEAK CURRENT SENSE VOLTAGE (mV) SENSE CURRENT (A) 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 2 80 70 60 50 40 30 20 10 0 0 0.2 OUTPUT VOLTAGE (V) 0.4 Figure 12. CURRENT LIMIT VS DUTY CYCLE (BUCK) PEAK CURRENT SENSE VOLTAGE (mV) REGULATED FBx VOLTAGE vs TEMPERATURE (BUCK) REGULATED FBx VOLTAGE (mV) 805 804 803 802 801 800 799 798 797 796 795 -15 10 35 60 85 110 135 160 80 70 60 VIN = 8V 50 40 VIN = 12V 30 20 10 0 0 10 20 Figure 13. Submit Documentation Feedback 30 40 50 60 70 80 90 100 DUTY CYCLE (%) TEMPERATURE (C) 12 0.8 0.6 FBx VOLTAGE (V) Figure 11. -40 1.55 Figure 10. CURRENT SENSE PINS INPUT CURRENT (BUCK) 1 1.4 COMPx VOLTAGE (V) Figure 9. 0 1.25 1.1 Figure 14. Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS43350-Q1 TPS43351-Q1 TPS43350-Q1 TPS43351-Q1 www.ti.com SLVSAR7B - JUNE 2011 - REVISED MAY 2012 DETAILED DESCRIPTION BUCK CONTROLLERS: NORMAL MODE PWM OPERATION Frequency Selection and External Synchronization The buck controllers operate using constant-frequency peak-current mode control for optimal transient behavior and ease of component choices. The switching frequency is programmable between 150 kHz and 600 kHz, depending upon the resistor value at the RT pin. A short circuit to ground at this pin sets the default switching frequency to 400 kHz. The frequency can also be set by a resistor at RT according to the formula: fSW = X (X=24kxMHz) RT fSW =24x 109 RT Equation 1. Switching Frequency For example, 600 kHz requires 40 k 150 kHz requires 160 k It is also possible to synchronize to an external clock at the SYNC pin in the same frequency range of 150 kHz to 600 kHz. The device detects clock pulses at this pin, and an internal PLL locks on to the external clock within the specified range. The device can also detect a loss of clock at this pin, and when this is detected it sets the switching frequency to the internal oscillator. The two buck controllers operate at identical switching frequencies, 180 degrees out of phase. Enable Inputs The buck controllers are enabled using independent enable inputs from the ENA and ENB pins. These are highvoltage pins with a threshold of 1.5 V for high level and can be connected directly to the battery for self-bias. The low threshold is 0.7 V. Both these pins have internal pullup currents of 0.5 A (typical). As a result, an open circuit on these pins enables the respective buck controllers. When both buck controllers are disabled, the device is shut down and consumes a current less than 4 A. Feedback Inputs The output voltage is set by choosing the right resistor feedback divider network connected to the FBx (feedback) pins. This is to be chosen such that the regulated voltage at the FBx pin equals 0.8 V. The FBx pins have a 100nA pullup current source as a protection feature in case the pins open up as a result of physical damage. Soft-Start Inputs In order to avoid large inrush currents, the buck controllers have independent programmable soft-start timers. The voltage at the SSx pins acts as the soft-start reference voltage. A 1-A pullup current is available at the SSx pins, and by choosing a suitable capacitor, a ramp of the desired soft-start speed can be generated. After startup, the pullup current ensures that this node is higher than the internal reference of 0.8 V ,which then becomes the reference for the buck controllers. The soft-start ramp time is defined by: I xt CSS = SS V (Farads) Equation 2. SoftStart Ramp Time where, ISS = 1 A (typical) V = 0.8 V CSS is the required capacitor for t, the desired soft-start time. Alternatively, the soft-start pins can be used as tracking inputs. In this case, they should be connected to the supply to be tracked via a suitable resistor divider network. Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS43350-Q1 TPS43351-Q1 Submit Documentation Feedback 13 TPS43350-Q1 TPS43351-Q1 SLVSAR7B - JUNE 2011 - REVISED MAY 2012 www.ti.com Current-Mode Operation Peak current-mode control regulates the peak current through the inductor such that the output voltage is maintained at its set value. The error between the feedback voltage at FBx and the internal reference produces a signal at the output of the error amplifier (COMPx) which serves as a target for the peak inductor current. The current through the inductor is sensed as a differential voltage at Sx1 - Sx2 and compared with this target during each cycle. A fall or rise in load current produces a rise or fall in voltage at FBx, causing COMPx to fall or rise respectively, thus increasing/decreasing the current through the inductor until the average current matches the load. In this way, the output voltage is maintained in regulation. The top N-channel MOSFET is turned on at the beginning of each clock cycle and kept on until the inductor current reaches its peak value. Once this MOSFET is turned off, and after a small delay (shoot-through delay) the lower N-channel MOSFET is turned on until the start of the next clock cycle. In dropout operation, the highside MOSFET stays on continuously. In every fourth clock cycle, the duty cycle is limited to 95% in order to charge the bootstrap capacitor at CBx. This allows a maximum duty cycle of 98.75% for the buck regulators. During dropout, the buck regulator switches at one-fourth of its normal frequency. Current Sensing and Current Limit With Foldback The maximum value of COMPx is clamped such that the maximum current through the inductor is limited to a specified value. When the output of the buck regulator (and hence the feedback value at FBx) falls to a low value due to a short-circuit or overcurrent condition, the clamped voltage at COMPx successively decreases, thus providing current foldback protection. This protects the high-side external MOSFET from excess current (forwarddirection current limit). Similarly, if due to a fault condition the output is shorted to a high voltage and the low-side MOSFET turns fully on, the COMPx node drops low. It is clamped on the lower end as well, in order to limit the maximum current in the low-side MOSFET (reverse-direction current limit). The current through the inductor is sensed by an external resistor. The sense resistor should be chosen such that the maximum forward peak current in the inductor generates a voltage of 75 mV across the sense pins. This value is specified at low duty cycles only. At typical duty-cycle conditions around 40% (assuming 5-V output and 12-V input), 50 mV is a more reasonable value, considering tolerances and mismatches. The typical characteristics provide a guide for using the correct current-limit sense voltage. The current-sense pins Sx1 and Sx2 are high-impedance pins with low leakage across the entire output range. This allows DCR current sensing using the dc resistance of the inductor for higher efficiency. DCR sensing is shown in Figure 15. Here the series resistance (DCR) of the inductor is used as the sense element. The filter components should be placed close to the device for noise immunity. It should be remembered that while the DCR sensing gives high efficiency, it is inaccurate due to the temperature sensitivity and a wide variation of the parasitic inductor series resistance. Hence, it may often be advantageous to use the more-accurate sense resistor for current sensing. Inductor L TPS43350-Q1 TPS43351-Q1 VBUCK X DCR R1 C1 Sx2 VC Sx1 Figure 15. DCR Sensing Configuration 14 Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS43350-Q1 TPS43351-Q1 TPS43350-Q1 TPS43351-Q1 www.ti.com SLVSAR7B - JUNE 2011 - REVISED MAY 2012 Slope Compensation Optimal slope compensation, which is adaptive to changes in input voltage and duty cycle, allows stable operation at all conditions. For optimal performance of this circuit, the following condition must be satisfied in the choice of inductor and sense resistor: LxfSW =200 RS Equation 3 Inductor and Sense Resistor Choice where L is the buck regulator inductor in henries RS is the sense resistor in ohms fsw is the buck regulator switching frequency in hertz Power Good Outputs and Filter Delays Each buck controller has an independent power-good comparator monitoring the feedback voltage at the FBx pins and indicating whether the output voltage has fallen below a specified power-good threshold. This threshold has a typical value of 93% of the regulated output voltage. The power-good indicator is available as an opendrain output at the PGx pins. An internal 50-k pullup resistor to Sx2 is available or an external resistor can be used. When a buck controller is shut down, the power-good indicator is pulled down internally. Connecting the pullup resistor to a rail other than the output of that particular buck channel causes a constant current flow through the resistor when the buck controller is powered down. In order to avoid triggering the power-good indicators due to noise or fast transients on the output voltage, an internal delay circuit for de-glitching is used. Similarly, when the output voltage returns to its set value after a long negative transient, the power-good indicator is asserted high (the open-drain pin released) after the same delay. This can be used to delay the reset to the circuits being powered from the buck regulator rail. The delay of this circuit can be programmed by using a suitable capacitor at the DLYAB pin according to the equation: tDELAY 1 msec = CDLYAB 1 nF Equation 4 Power Good Indicator Delay When the DLYAB pin is open, the delay is set to a default value of 20 s, typical. The power-good delay timing is common to both the buck rails, but the power-good comparators and indicators function independently. Light Load PFM Mode An external clock or a high level on the SYNC pin results in forced continuous-mode operation of the bucks. When the SYNC pin is low or open, the buck controllers are allowed to operate in discontinuous mode at light loads by turning off the low-side MOSFET whenever a zero-crossing in the inductor current is detected. In discontinuous mode, as the load decreases, the duration of the clock period when both the high-side and the low-side MOSFETs are turned off increases (deep discontinuous mode). In case the duration exceeds 60% of the clock period and VBAT > 8 V, the buck controller switches to a low-power operation mode. The design ensures that this typically occurs at 1% of the set full-load current if the inductor and the sense resistor have been chosen appropriately as recommended in the Slope Compensation section. In low-power PFM mode, the buck monitors the FBx voltage and compares it with the 0.8-V internal reference. Whenever the FBx value falls below the reference, the high-side MOSFET is turned on for a pulse duration inversely proportional to the difference VIN - Sx2. At the end of this on-time, the high-side MOSFET is turned off and the current in the inductor decays until it becomes zero. The low-side MOSFET is not turned on. The next pulse occurs the next time FBx falls below the reference value. This results in a constant volt-second ton hysteretic operation with a total device quiescent current consumption of 30 A when a single buck channel is active and 35 A when both channels are active. As the load increases, the pulses become more and more frequent and move closer to each other until the current in the inductor becomes continuous. At this point, the buck controller returns to normal fixed-frequency current-mode control. Another criterion to exit the low-power mode is when VIN falls low enough to require higher than 80% duty cycle of the high-side MOSFET. Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS43350-Q1 TPS43351-Q1 Submit Documentation Feedback 15 TPS43350-Q1 TPS43351-Q1 SLVSAR7B - JUNE 2011 - REVISED MAY 2012 www.ti.com The TPS43350-Q1 and TPS43351-Q1 can support the full current load during low-power mode until the transition to normal mode takes place. The design ensures that exit from the low-power mode occurs at 10% (typical) of full-load current if the inductor and sense resistor have been chosen as recommended. Moreover, there is always a hysteresis between the entry and exit thresholds to avoid oscillating between the two modes. In the event that both buck controllers are active, low-power mode is only possible when both buck controllers have light loads that are low enough for low-power-mode entry. Frequency-Hopping Spread Spectrum (TPS43351 Only) The TPS43351-Q1 features a frequency-hopping pseudo-random spectrum spreading architecture. On this device, whenever the SYNC pin is high, the internal oscillator frequency is varied from one cycle to the next within a band of 5% around the value programmed by the resistor at the RT pin. The implementation uses a linear feedback shift register that changes the frequency of the internal oscillator based on a digital code. The shift register is long enough to make the hops pseudo-random in nature and is designed in such a way that the frequency shifts only by one step at each cycle to avoid large jumps in the buck switching frequencies. Table 1. Frequency Hopping Control SYNC TERMINAL FREQUENCY SPREAD SPECTRUM (FSS) COMMENTS External clock Not active Device in forced continuous mode, internal PLL locks into external clock between 150 kHz and 600 kHz. Low or open Not active Device can enter discontinuous mode. Automatic LPM entry and exit, depending on load conditions TPS43350: FSS not active High Device in forced continuous mode TPS43351: FSS active Table 2. Mode of Operation ENABLE AND INHIBIT PINS ENA Low Low High High ENB Low High Low High SYNC X Low High Low High Low High BUCK CONTROLLER STATUS Shutdown BuckB running BuckA running Bucks A and B running DEVICE STATUS QUIESCENT CURRENT Shutdown 4 A BuckB: LPM enabled 30 A (light loads) BuckB: LPM inhibited mA range BuckA: LPM enabled 30 A (light loads) BuckA: LPM inhibited mA range BuckA/B: LPM enabled 35 A (light loads) BuckA/B: LPM inhibited mA range Gate Driver Supply (VREG, EXTSUP) The gate drivers of the buck controllers are supplied from an internal linear regulator whose output (5.8 V typical) is available at the VREG pin and should be decoupled using at least a 3.3-F ceramic capacitor. This pin has an internal current-limit protection and should not be used to power any other circuits. The VREG linear regulator is powered from VIN by default when the EXTSUP voltage is lower than 4.6 V (typ.). In case VIN expected to go to high levels, there can be excessive power dissipation in this regulator, especially at high switching frequencies and when using large external MOSFETs. In this case, it is advantageous to power this regulator from the EXTSUP pin, which can be connected to a supply lower than VIN but high enough to provide the gate drive. When EXTSUP is connected to a voltage greater than 4.6 V, the linear regulator automatically switches to EXTSUP as its input to provide this advantage. Efficiency improvements are possible when one of the switching regulator rails from the TPS4335x-Q! or any other voltage available in the system is used to power EXTSUP. The maximum voltage that should be applied to EXTSUP is 13 V. 16 Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS43350-Q1 TPS43351-Q1 TPS43350-Q1 TPS43351-Q1 www.ti.com SLVSAR7B - JUNE 2011 - REVISED MAY 2012 VIN typ 5.8 V LDO VIN EXTSUP typ 7.5 V LDO EXTSUP typ 4.6 V VREG Figure 16. Internal Gate Driver Supply Using a large value for EXTSUP is advantageous as it provides a large gate drive and hence better onresistance of the external MOSFETs. A 0.1-F ceramic capacitor is recommended for decoupling the EXTSUP pin when not being used. During low-power mode, the EXTSUP functionality is not available. The internal regulator operates as a shunt regulator powered from VIN and has a typical value of 7.5 V. Current -limit protection for VREG is available in low-power mode as well. External P-Channel Drive (GC2) and Reverse Battery Protection The TPS43350x-Q1 includes a gate driver for an external P-channel MOSFET which can be connected across the reverse-battery diode. This is useful to reduce power losses and the voltage drop over a typical diode. The gate driver provides a swing of 6 V typical below the VIN voltage in order to drive a P-channel MOSFET. GC2 TPS43350/1 VBAT VIN Fuse VBAT Figure 17. Reverse-Battery Protection Option Undervoltage Lockout and Overvoltage Protection The TPS4335x-Q1 starts up at a VIN voltage of 6.5 V (minimum), required for the internal supply (VREG). Once it has started up, the device operates down to a VIN voltage of 3.6 V; below this voltage level, the undervoltage lockout disables the device. Note: if Vin drops, VREG drops as well; hence, the gate-drive voltage is reduced while the digital logic is fully functional. A voltage of 46 V at VIN triggers the overvoltage comparator, which shuts down the device. In order to prevent transient spikes from shutting down the device, under- and overvoltage protection have filter times of 5 s (typical). When the voltages return to the normal operating region, the enabled switching regulators start including a new soft-start ramp for the buck regulators. Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS43350-Q1 TPS43351-Q1 Submit Documentation Feedback 17 TPS43350-Q1 TPS43351-Q1 SLVSAR7B - JUNE 2011 - REVISED MAY 2012 www.ti.com Thermal Protection The TPS43350/1 protects itself from overheating using an internal thermal shutdown circuit. If the die temperature exceeds the thermal shutdown threshold of 165 degrees Celsius due to excessive power dissipation (for example, Due to fault conditions such as a short circuit at the gate drivers or VREG), the controllers are turned off and restarted when the temperature has fallen by 15 degrees. 18 Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS43350-Q1 TPS43351-Q1 TPS43350-Q1 TPS43351-Q1 www.ti.com SLVSAR7B - JUNE 2011 - REVISED MAY 2012 APPLICATION INFORMATION The following example illustrates the design process and component selection for the TPS43350-Q1. The design goal parameters are given in Table 3. Table 3. Application Example PARAMETER VBUCK A VBUCK B VIN 6 V to 30 V 12 V - typ VIN 6 V to 30 V 12 V - typ Output voltage, VO 5V 3.3 V Max - output current, IO 3A 2A 0.2 V 0.12 V 0.1 A to 3 A 0.1 A to 2 A 400 kHz 400 kHz Input voltage Load step output tolerance, VO Current output load step, IO Converter switching frequency, fSW This is a starting point, and theoretical representation of the values to be used for the application; further optimization of the components derived may be required to improve the performance of the device. BuckA Component Selection Minimum ON Time, tON min VO 5V t ON min = = = 416 ns VIN max f SW 30 V 400 kHz This is higher than the minimum on-time specified (100 ns typical). Hence, the minimum duty cycle is achievable at this frequency. Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS43350-Q1 TPS43351-Q1 Submit Documentation Feedback 19 TPS43350-Q1 TPS43351-Q1 SLVSAR7B - JUNE 2011 - REVISED MAY 2012 www.ti.com Current Sense Resistor RSENSE Based on the typical characteristics for VSENSE limit with VIN versus duty cycle, the sense limit is approximately 65 mV (at VIN = 12 V and duty cycle of 5 V / 12 V = 0.416). Allowing for tolerances and ripple currents, choose VSENSE max of 50 mV. Select 15 m. Inductor Selection L As explained in the description of the buck controllers, for optimal slope compensation and loop response, the inductor should be chosen such that: KFLR = Coil selection constant = 200 Choose a standard value of 8.2 H. For the buck converter, the inductor saturation currents and core should be chosen to sustain the maximum currents. Inductor Ripple Current IRIPPLE At nominal input voltage of 12V, this gives a ripple current of 30% of IO max 1A. Output Capacitor CO Select an output capacitance CO of 100 F with low ESR in the range of 10 m. This gives VO(Ripple) 15 mV and V drop of 180 mV during a load step, which does not trigger the power-good comparator and is within the required limits. Bandwidth of Buck Converter fC Use the following guidelines to set frequency poles, zeroes and crossover values for a tradeoff between stability and transient response. * Crossover frequency fC between fSW / 6 and fSW / 10. Assume fC = 50 kHz. * Select the zero fz fC / 10. * Make the second pole fP2 fSW / 2. spacer spacer spacer spacer 20 Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS43350-Q1 TPS43351-Q1 TPS43350-Q1 TPS43351-Q1 www.ti.com SLVSAR7B - JUNE 2011 - REVISED MAY 2012 Selection of Components for Type II Compensation VO RESR RL R1 VSENSE GmBUCK CO R2 Vref COMP Type 2A R3 R0 C2 C1 Figure 18. Buck Compensation Components R3 = 2p f C VO CO GmBUCK K CFB VREF = 2p 50 kHz 5 V 100F GmBUCK K CFB VREF = 23.57 kW Use the standard value of R3 = 24 k, Where VO = 5 V, CO = 100 F, GmBUCK = 1 mS, VREF = 0.8 V KCFB = 0.125 / RSENSE = 8.33 S (0.125 is an internal constant) C1 = 10 2p R3 fC = 10 2p 24 kW 50 kHz = 1.33 nF Use the standard value of 1.5 nF. The resulting bandwidth of Buck Converter fC fC = fC = GmBUCK R3 KCFB 2p CO VREF VO 1mS 24 kW 8.33 S 0.8 V 2p 100 F 5 V = 50.9 kHz This is close to the target bandwidth of 50 kHz. The resulting zero frequency fZ1 This is close to the fC / 10 guideline of 5 kHz. The second pole frequency fP2 This is close to the fSW / 2 guideline of 200 kHz. Hence, all requirements for a good loop response are satisfied. Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS43350-Q1 TPS43351-Q1 Submit Documentation Feedback 21 TPS43350-Q1 TPS43351-Q1 SLVSAR7B - JUNE 2011 - REVISED MAY 2012 www.ti.com Resistor Divider Selection for setting VO Voltage VREF 0.8 V b= = = 0.16 VO 5V Choose the divider current through R1 and R2 to be 50 A. Then and Therefore, R2 = 16 k and R1 = 84 k. BuckB Component Selection Using the same method as VBUCKA, the following parameters and components are realized VO 5V t ON min = = = 416 ns VIN max f SW 30 V 400 kHz This is higher than the minimum duty cycle specified (100 ns typical). Iripple current 0.4 A (approx. 20% of IO max) Select an output capacitance CO of 100 F with low ESR in the range of 10 m. This gives VO (Ripple) 7.5 mV and a V drop 120 mV during a load step. Assume fC = 50 kHz. R3 = = 2p f C VO CO GmBUCK K CFB VREF 2p 50 kHz 3.3 V 100 mF 1mS 4.16 S 0.8 V = 31kW Use the standard value of R3 = 30 k. 22 Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS43350-Q1 TPS43351-Q1 TPS43350-Q1 TPS43351-Q1 www.ti.com SLVSAR7B - JUNE 2011 - REVISED MAY 2012 10 C1 = 2p R3 fC = 10 2p 30 kW 50 kHz C1 C2 = ae fSW e 2 2p R3 C1 c = fC = = = 1.1nF o / -1 o 1.1nF ae 400 kHz o 2p 30 kW 1.1nF c / -1 2 e o GmBUCK R3 K CFB 2 p CO = 27 pF VREF VO 1mS 30 kW 4.16 S 0.8 V 2p 100 F 3.3 V = 48 kHz This is close to the target bandwidth of 50 kHz. The resulting zero frequency fZ1 fZ1 = 1 2p R3 C1 = 1 2p 30 kW 1.1nF = 4.8 kHz This is close to the fC guideline of 5 kHz. The second pole frequency fP2 fP2 = 1 2p R3 C2 = 1 2p 30 kW 27 pF = 196 kHz This is close to the fSW / 2 guideline of 200 kHz. Hence, all requirements for a good loop response are satisfied. Resistor Divider Selection for Setting VO Voltage V 0.8 V b = REF = = 0.242 VO 3.3 V Choose the divider current through R1 and R2 to be 50 A. Then and Therefore, R2 = 16 k and R1 = 50 k. Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS43350-Q1 TPS43351-Q1 Submit Documentation Feedback 23 TPS43350-Q1 TPS43351-Q1 SLVSAR7B - JUNE 2011 - REVISED MAY 2012 www.ti.com BuckX High-Side and Low-Side N-Channel MOSFETs The gate-drive supply for these MOSFETs is supplied by an internal supply which is 5.8 V typical under normal operating conditions. The output is a totem pole allowing full voltage drive of VREG to the gate with peak output current of 1.2 A. The high-side MOSFET is referenced to a floating node at the phase terminal (PHx) and the low-side MOSFET is referenced to the power ground (PGx) terminal. For a particular application, these MOSFETs should be selected with consideration for the following parameters: rds(on), gate charge Qg, drain-tosource breakdown voltage BVDSS, maximum dc current IDC(max), and thermal resistance for the package. The times tr and tf denote the rising and falling times of the switching node and are related to the gate-driver strength of the TPS43350x-Q1 and gate Miller capacitance of the MOSFET. The first term denotes the conduction losses, which are minimized when the on-resistance of the MOSFET is low. The second term denotes the transition losses, which arise due to the full application of the input voltage across the drain-source of the MOSFET as it turns on or off. They are lower at low currents and when the switching time is low. ae V I o PBuckTOPFET = (IO )2 rDS(on) (1 + TC) D + c I O / (tr + t f ) f SW e 2 o 2 PbuckLOWERFET = (IO ) rDS(on) (1 + TC) (1 - D) + VF IO (2 t d ) fSW In addition, during dead time td when both the MOSFETs are off, the body diode of the low-side MOSFET conducts, increasing the losses. This is denoted by the second term in the foregoing equation. Using external Schottky diodes in parallel to the low-side MOSFETs of the buck converters helps to reduce this loss. Note: The rDS(on) has a positive temperature coefficient which is accounted for in the TC term for rDS(on). TC = d x delta T[C]. The temperature coefficient d is available as a normalized value from MOSFET data sheets and can be assumed to be 0.005 / C as a starting value. 24 Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS43350-Q1 TPS43351-Q1 TPS43350-Q1 TPS43351-Q1 www.ti.com SLVSAR7B - JUNE 2011 - REVISED MAY 2012 Schematic The following section summarizes the previously calculated example and gives schematic and component proposals. Table 3. Table 4. Application Example PARAMETER VbuckA VbuckB VIN 6 V to 30 V 12 V, typ. VIN 6 V to 30 V 12 V, typ. Output voltage, VO 5V 3.3 V Max - output current, IO 3A 2A 0.2 V 0.12 V 0.1 A to 3 A 0.1 A to 2 A 400 kHz 400 kHz Input voltage Load step output tolerance, VO Current output load step, IO Converter switching frequency, fSW VIN VBAT 0.1F VIN SWRB EXTSUP GC2 VBAT 0.1F VREG 1k 0.1F 0.1F VIN SWAH SWAL L1 8.2H CBA CBB GA1 GB1 PHA PHB GA2 GB2 PGNDA VBUCKA 5V, 3A SA1 VIN SWBH SWBL L2 15H PGNDB VBUCKB 3.3V, 2A SB1 0.015 COUTA 100A 0.03 SA2 SB2 FBA FBB 84k 5k 16k COUTB 100A 50k 16k 27pF 33pF 1.5nF COMPA 10nF 1.1nF COMPB 24k 30k SSA SSB PGA PGB ENA AGND ENB 5k 10nF RT DLYAB 1nF SYNC Figure 19. Simplified Application Schematic Example Table 5. Application Example - Component Proposals COMPONENT PROPOSAL VALUE L1 NAME MSS1278T-822ML (Coilcraft) 8.2 H L2 MSS1278T-153ML (Coilcraft) 15 H D1 SK103 (Micro Commercial Components) SWRB IRF7416 (International Rectifier) SWAH, SWAL, SWBH, SWBL Si4840DY-T1-E3 (Vishay) COUTA, COUTB ECASD91A107M010K00 (Murata) 100 F CIN EEEFK1V331P (Panasonic) 330 F Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS43350-Q1 TPS43351-Q1 Submit Documentation Feedback 25 TPS43350-Q1 TPS43351-Q1 SLVSAR7B - JUNE 2011 - REVISED MAY 2012 www.ti.com Power Dissipation Derating Profile, 38-Pin HTTSOP PowerPAD Package Figure 20. Power Dissipation Derating Profile Based on High-K JEDEC PCB PCB Layout Guidelines Grounding and PCB Circuit Layout Considerations Buck Converter 1. Connect the drain of SWAH and SWBH MOSFETs together with the positive terminal of the input capacitor COUTA. The trace length between these terminals should be short. 2. Connect a local decoupling capacitor between the drain of SWxH and source of SWxL. 3. The Kelvin current sensing for the shunt resistor should have minimum trace spacing and routed parallel to each other. Any filtering capacitors for noise should be placed near the IC pins. 4. The resistor divider for sensing output voltage is connected between the positive terminal of the respective output capacitor and COUTA or COUTB and the IC signal ground. These components and the traces should not be routed near any switching nodes or high-current traces. Other Considerations 1. PGNDx and AGND should be shorted to the thermal pad. Use a star ground configuration if connecting to a nonground plane system. Use tie-ins for the EXTSUP capacitor, compensation-network ground, and voltagesense feedback-ground networks to this star ground. 2. Connect a compensation network between the compensation pins and IC signal ground. Connect the oscillator resistor (frequency setting) between the RT pin and IC signal ground. These sensitive circuits should NOT be located near the dv/dt nodes; these include the gate-drive outputs and phase pins. 3. Reduce the surface area of the high-current-carrying loops to a minimum by ensuring optimal component placement. Ensure the bypass capacitors are located as close as possible to their respective power and ground pins. 26 Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS43350-Q1 TPS43351-Q1 TPS43350-Q1 TPS43351-Q1 www.ti.com SLVSAR7B - JUNE 2011 - REVISED MAY 2012 PCB Layout POWER INPUT Power Lines Connection to GND Plane of PCB through vias Connection to top/bottom of PCB through vias Voltage Rail Outputs VIN VBAT EXTSUP NC NC GC2 VREG CBA CBB GA1 GB1 PHA PHB GB2 GA2 PGNDB PGNDA SA1 SB1 SA2 SB2 FBB FBA COMPB COMPA SSA SSB PGA PGB ENA AGND RT ENB NC AGND Microcontroller VBUCKB VBUCKA NC Exposed Pad connected to GND Plane DLYAB SYNC Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS43350-Q1 TPS43351-Q1 Submit Documentation Feedback 27 PACKAGE OPTION ADDENDUM www.ti.com 18-Apr-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) TPS43350QDAPRQ1 ACTIVE HTSSOP DAP 38 1 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TPS43351QDAPRQ1 ACTIVE HTSSOP DAP 38 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. 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