SDRAM 256Mb E-die (x4, x8, x16) CMOS SDRAM
Rev. 1.3 August 2004
SDRAM 256Mb E-die (x4, x8, x16)
256Mb E-die SDRAM Specification
Revision 1.3
August 2004
* Samsung Electronics reserves the right to change products or specification without notice.
54 TSOP-II with Pb-Free
(RoHS compliant)
SDRAM 256Mb E-die (x4, x8, x16) CMOS SDRAM
Rev. 1.3 August 2004
SDRAM 256Mb E-die (x4, x8, x16)
Revision History
Revision 1.0 (May. 2003)
- First generation for Pb_free products
Revision 1.1 (August. 2003)
- Corrected typo in Page #8, 9
Revision 1.2 (May. 2004)
- Added Note 5. sentense of tRDL parameter
Revision 1.3 (August. 2004)
- Corrected typo.
SDRAM 256Mb E-die (x4, x8, x16) CMOS SDRAM
Rev. 1.3 August 2004
SDRAM 256Mb E-die (x4, x8, x16)
Part No. Orgainization Max Freq. Interface Package
K4S560432E-UC(L)75 64M x 4 133MHz LVTTL 54pin TSOP(II)
K4S560832E-UC(L)75 32M x 8 133MHz LVTTL 54pin TSOP(II)
K4S561632E-UC(L)60/75 16M x 16 133MHz LVTTL 54pin TSOP(II)
The K4S560432E / K4S560832E / K4S561632E is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x
16,785,216 / 4 x 8,392,608 / 4 x 4,196,304 words by 4bits, fabricated with SAMSUNG's high performance CMOS technology. Synchro-
nous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of oper-
ating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high
bandwidth, high performance memory system applications.
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system clock.
• Burst read single-bit write operation
• DQM (x4,x8) & L(U)DQM (x16) for masking
• Auto & self refresh
• 64ms refresh period (8K Cycle)
• 54 TSOP(II) Pb-free Package
• RoHS compliant
GENERAL DESCRIPTION
FEATURES
16M x 4Bit x 4 Banks / 8M x 8Bit x 4 Banks / 4M x 16Bit x 4 Banks SDRAM
Ordering Information
Row & Column address configuration
Organization Row Address Column Address
64Mx4 A0~A12 A0-A9, A11
32Mx8 A0~A12 A0-A9
16Mx16 A0~A12 A0-A8
SDRAM 256Mb E-die (x4, x8, x16) CMOS SDRAM
Rev. 1.3 August 2004
SDRAM 256Mb E-die (x4, x8, x16)
11.76±0.20
0.463±0.008
0.002
0.05 MIN
0.008
0.21
± 0.002
± 0.05
0.020
0.50
( )
0.005-0.001
+0.003
0.125-0.035
+0.075
0.400
10.16
0.45~0.75
0.018~0.030
0.010
0.25 TYP
0~8°C
#54 #28
#1 #27
0.004
0.10 MAX
0.028
0.71
( ) 0.012
0.30 0.0315
0.80
0.047
1.20 MAX
0.039
1.00
± 0.004
± 0.10
0.891
22.62 MAX
0.875
22.22
± 0.004
± 0.10
+0.10
-0.05
+0.004
-0.002
54Pin TSOP(II) Package Dimension
Package Physical Dimension
SDRAM 256Mb E-die (x4, x8, x16) CMOS SDRAM
Rev. 1.3 August 2004
SDRAM 256Mb E-die (x4, x8, x16)
FUNCTIONAL BLOCK DIAGRAM
Bank Select
Data Input Register
16M x 4 / 8M x 8 / 4M x 16
16M x 4 / 8M x 8 / 4M x 16
Sense AMP
Output BufferI/O Control
Column Decoder
Latency & Burst Length
Programming Register
Address Register
Row Buffer
Refresh Counter
Row Decoder Col. Buffer
LRAS
LCBR
LCKE
LRAS LCBR LWE LDQM
CLK CKE CS RAS CAS WE L(U)DQM
LWE
LDQM
DQi
CLK
ADD
LCAS LWCBR
16M x 4 / 8M x 8 / 4M x 16
16M x 4 / 8M x 8 / 4M x 16
Timing Register
* Samsung Electronics reserves the right to change products or specification without notice.
SDRAM 256Mb E-die (x4, x8, x16) CMOS SDRAM
Rev. 1.3 August 2004
SDRAM 256Mb E-die (x4, x8, x16)
PIN CONFIGURATION (Top view)
VDD
N.C
VDDQ
N.C
DQ0
VSSQ
N.C
N.C
VDDQ
N.C
DQ1
VSSQ
N.C
VDD
N.C
WE
CAS
RAS
CS
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VSS
N.C
VSSQ
N.C
DQ3
VDDQ
N.C
N.C
VSSQ
N.C
DQ2
VDDQ
N.C
VSS
N.C/RFU
DQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
VSS
54Pin TSOP
(400mil x 875mil)
(0.8 mm Pin pitch)
PIN FUNCTION DESCRIPTION
Pin Name Input Function
CLK System clock Active on the positive going edge to sample all inputs.
CS Chip select Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
CKE Clock enable Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
A0 ~ A12 Address Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA12,
Column address : (x4 : CA0 ~ CA9,CA11), (x8 : CA0 ~ CA9), (x16 : CA0 ~ CA8)
BA0 ~ BA1Bank select address Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
RAS Row address strobe Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
CAS Column address strobe Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
WE Write enable Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
DQM Data input/output mask Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active.
DQ0 ~ NData input/output Data inputs/outputs are multiplexed on the same pins.
(x4 : DQ0 ~ 3), (x8 : DQ0 ~ 7), (x16 : DQ0 ~ 15)
VDD/VSS Power supply/ground Power and ground for the input buffers and the core logic.
VDDQ/VSSQ Data output power/ground Isolated power supply and ground for the output buffers to provide improved noise
immunity.
N.C/RFU No connection
/reserved for future use This pin is recommended to be left No Connection on the device.
VDD
DQ0
VDDQ
N.C
DQ1
VSSQ
N.C
DQ2
VDDQ
N.C
DQ3
VSSQ
N.C
VDD
N.C
WE
CAS
RAS
CS
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
VSS
DQ7
VSSQ
N.C
DQ6
VDDQ
N.C
DQ5
VSSQ
N.C
DQ4
VDDQ
N.C
VSS
N.C/RFU
DQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
VSS
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
VDD
LDQM
WE
CAS
RAS
CS
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
VSS
N.C/RFU
UDQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
VSS
x16 x8 x4 x16
x8x4
SDRAM 256Mb E-die (x4, x8, x16) CMOS SDRAM
Rev. 1.3 August 2004
SDRAM 256Mb E-die (x4, x8, x16)
ABSOLUTE MAXIMUM RATINGS
Parameter Symbol Value Unit
Voltage on any pin relative to Vss VIN, VOUT -1.0 ~ 4.6 V
Voltage on VDD supply relative to Vss VDD, VDDQ -1.0 ~ 4.6 V
Storage temperature TSTG -55 ~ +150 °C
Power dissipation PD1W
Short circuit current IOS 50 mA
Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
Note :
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C)
Parameter Symbol Min Typ Max Unit Note
Supply voltage VDD, VDDQ 3.0 3.3 3.6 V
Input logic high voltage VIH 2.0 3.0 VDD+0.3 V 1
Input logic low voltage VIL -0.3 0 0.8 V 2
Output logic high voltage VOH 2.4 - - V IOH = -2mA
Output logic low voltage VOL --0.4VIOL = 2mA
Input leakage current ILI -10 - 10 uA 3
1. VIH (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns.
2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.
3. Any input 0V ≤ VIN ≤ VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
Notes :
CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF =1.4V ± 200 mV)
Pin Symbol Min Max Unit Note
Clock CCLK 2.5 3.5 pF
RAS, CAS, WE, CS, CKE, DQM CIN 2.5 3.8 pF
Address CADD 2.5 3.8 pF
(x4 : DQ0 ~ DQ3), (x8 : DQ0 ~ DQ7), (x16 : DQ0 ~ DQ15) COUT 4.0 6.0 pF
SDRAM 256Mb E-die (x4, x8, x16) CMOS SDRAM
Rev. 1.3 August 2004
SDRAM 256Mb E-die (x4, x8, x16)
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Parameter Symbol Test Condition Version Unit Note
75
Operating current
(One bank active) ICC1 Burst length = 1
tRC ≥ tRC(min)
IO = 0 mA 80 mA 1
Precharge standby current in
power-down mode ICC2P CKE ≤ VIL(max), tCC = 10ns 2 mA
ICC2PS CKE & CLK ≤ VIL(max), tCC = ∞2
Precharge standby current in
non power-down mode
ICC2NCKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns 20 mA
ICC2NS CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable 10
Active standby current in
power-down mode ICC3P CKE ≤ VIL(max), tCC = 10ns 6 mA
ICC3PS CKE & CLK ≤ VIL(max), tCC = ∞6
Active standby current in
non power-down mode
(One bank active)
ICC3NCKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns 25 mA
ICC3NS CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable 25 mA
Operating current
(Burst mode) ICC4
IO = 0 mA
Page burst
4banks Activated.
tCCD = 2CLKs 100 mA 1
Refresh current ICC5 tRC ≥ tRC(min) 180 mA 2
Self refresh current ICC6 CKE ≤ 0.2V C3mA3
L1.5mA4
1. Measured with outputs open.
2. Refresh period is 64ms.
3. K4S5604(08)32E-UC
4. K4S5604(08)32E-UL
5. Unless otherwise noticed, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ).
Notes :
DC CHARACTERISTICS (x4, x8)
SDRAM 256Mb E-die (x4, x8, x16) CMOS SDRAM
Rev. 1.3 August 2004
SDRAM 256Mb E-die (x4, x8, x16)SDRAM 256Mb E-die (x4, x8, x16)SDRAM 256Mb E-die (x4, x8, x16)
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Parameter Symbol Test Condition Version Unit Note
60 75
Operating current
(One bank active) ICC1 Burst length = 1
tRC ≥ tRC(min)
IO = 0 mA 140 90 mA 1
Precharge standby current in
power-down mode ICC2PCKE ≤ VIL(max), tCC = 10ns 2mA
ICC2PS CKE & CLK ≤ VIL(max), tCC = ∞ 2
Precharge standby current in
non power-down mode
ICC2NCKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns 20 mA
ICC2NS CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable 10
Active standby current in
power-down mode ICC3PCKE ≤ VIL(max), tCC = 10ns 6mA
ICC3PS CKE & CLK ≤ VIL(max), tCC = ∞ 6
Active standby current in
non power-down mode
(One bank active)
ICC3NCKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns 25 mA
ICC3NS CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable 25 mA
Operating current
(Burst mode) ICC4
IO = 0 mA
Page burst
4banks Activated.
tCCD = 2CLKs
170 130 mA 1
Refresh current ICC5 tRC ≥ tRC(min) 200 180 mA 2
Self refresh current ICC6 CKE ≤ 0.2V C 3 mA 3
L 1.5 mA 4
1. Measured with outputs open.
2. Refresh period is 64ms.
3. K4S561632E-UC
4. K4S561632E-UL
5. Unless otherwise noticed, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ).
Notes :
DC CHARACTERISTICS (x16)
SDRAM 256Mb E-die (x4, x8, x16) CMOS SDRAM
Rev. 1.3 August 2004
SDRAM 256Mb E-die (x4, x8, x16)
AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70°C)
Parameter Value Unit
AC input levels (Vih/Vil) 2.4/0.4 V
Input timing measurement reference level 1.4 V
Input rise and fall time tr/tf = 1/1 ns
Output timing measurement reference level 1.4 V
Output load condition See Fig. 2
3.3V
1200Ω
870Ω
Output
50pF
VOH (DC) = 2.4V, IOH = -2mA
VOL (DC) = 0.4V, IOL = 2mA
Vtt = 1.4V
50Ω
Output
50pF
Z0 = 50Ω
(Fig. 2) AC output load circuit (Fig. 1) DC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter Symbol Version Unit Note
60 75
Row active to row active delay tRRD(min) 12 15 ns 1
RAS to CAS delay tRCD(min) 18 20 ns 1
Row precharge time tRP(min) 18 20 ns 1
Row active time tRAS(min) 42 45 ns 1
tRAS(max) 100 us
Row cycle time tRC(min) 60 65 ns 1
Last data in to row precharge tRDL(min) 2 CLK 2, 5
Last data in to Active delay tDAL(min) 2 CLK + tRP - 5
Last data in to new col. address delay tCDL(min) 1 CLK 2
Last data in to burst stop tBDL(min) 1 CLK 2
Col. address to col. address delay tCCD(min) 1 CLK 3
Number of valid output data CAS latency=3 2 ea 4
CAS latency=2 - 1
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported.
SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.
Notes :
SDRAM 256Mb E-die (x4, x8, x16) CMOS SDRAM
Rev. 1.3 August 2004
SDRAM 256Mb E-die (x4, x8, x16)
DQ BUFFER OUTPUT DRIVE CHARACTERISTICS
Parameter Symbol Condition Min Typ Max Unit Notes
Output rise time trh Measure in linear
region : 1.2V ~ 1.8V 1.37 4.37 Volts/ns 3
Output fall time tfh Measure in linear
region : 1.2V ~ 1.8V 1.30 3.8 Volts/ns 3
Output rise time trh Measure in linear
region : 1.2V ~ 1.8V 2.8 3.9 5.6 Volts/ns 1,2
Output fall time tfh Measure in linear
region : 1.2V ~ 1.8V 2.0 2.9 5.0 Volts/ns 1,2
1. Rise time specification based on 0pF + 50 Ω to VSS, use these values to design to.
2. Fall time specification based on 0pF + 50 Ω to VDD, use these values to design to.
3. Measured into 50pF only, use these values to characterize to.
4. All measurements done with respect to VSS.
Notes :
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Parameter Symbol 60 75 Unit Note
Min Max Min Max
CLK cycle time CAS latency=3 tCC 61000 7.5 1000 ns 1
CAS latency=2 - 10
CLK to valid
output delay CAS latency=3 tSAC 55.4
ns 1,2
CAS latency=2 - 6
Output data
hold time CAS latency=3 tOH 2.5 3 ns 2
CAS latency=2 - 3
CLK high pulse width tCH 2.5 2.5 ns 3
CLK low pulse width tCL 2.5 2.5 ns 3
Input setup time tSS 1.5 1.5 ns 3
Input hold time tSH 10.8ns3
CLK to output in Low-Z tSLZ 11ns2
CLK to output in Hi-Z CAS latency=3 tSHZ 55.4
ns
CAS latency=2 - 6
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Notes :
SDRAM 256Mb E-die (x4, x8, x16) CMOS SDRAM
Rev. 1.3 August 2004
SDRAM 256Mb E-die (x4, x8, x16)
IOH Characteristics (Pull-up)
Voltage 100MHz
133MHz
Min
100MHz
133MHz
Max
66MHz
Min
(V) I (mA) I (mA) I (mA)
3.45 -2.4
3.3 -27.3
3.0 0.0 -74.1 -0.7
2.6 -21.1 -129.2 -7.5
2.4 -34.1 -153.3 -13.3
2.0 -58.7 -197.0 -27.5
1.8 -67.3 -226.2 -35.5
1.65 -73.0 -248.0 -41.1
1.5 -77.9 -269.7 -47.9
1.4 -80.8 -284.3 -52.4
1.0 -88.6 -344.5 -72.5
0.0 -93.0 -502.4 -93.0
IBIS SPECIFICATION
IOL Characteristics (Pull-down)
Voltage 100MHz
133MHz
Min
100MHz
133MHz
Max
66MHz
Min
(V) I (mA) I (mA) I (mA)
0.0 0.0 0.0 0.0
0.4 27.5 70.2 17.7
0.65 41.8 107.5 26.9
0.85 51.6 133.8 33.3
1.0 58.0 151.2 37.6
1.4 70.7 187.7 46.6
1.5 72.9 194.4 48.0
1.65 75.4 202.5 49.5
1.8 77.0 208.6 50.7
1.95 77.6 212.0 51.5
3.0 80.3 219.6 54.2
3.45 81.4 222.6 54.9
0
-100
-200
-300
-400
-500
-600
030.5 1 1.5 2 2.5 3.5
Voltage
mA
250
200
150
100
50
0030.5 1 1.5 2 2.5 3.5
Voltage
mA
66MHz and 100MHz/133MHz Pull-up
66MHz and 100MHz/133MHz Pull-down
IOH Min (100MHz)
IOH Max (66 and 100MHz)
IOH Min (66MHz)
IOL Min (100MHz)
IOL Max (100MHz)
IOL Min (66MHz)
SDRAM 256Mb E-die (x4, x8, x16) CMOS SDRAM
Rev. 1.3 August 2004
SDRAM 256Mb E-die (x4, x8, x16)
VDD Clamp @ CLK, CKE, CS, DQM & DQ
VDD (V) I (mA)
0.0 0.0
0.2 0.0
0.4 0.0
0.6 0.0
0.7 0.0
0.8 0.0
0.9 0.0
1.0 0.23
1.2 1.34
1.4 3.02
1.6 5.06
1.8 7.35
2.0 9.83
2.2 12.48
2.4 15.30
2.6 18.31
VSS Clamp @ CLK, CKE, CS, DQM & DQ
VSS (V) I (mA)
-2.6 -57.23
-2.4 -45.77
-2.2 -38.26
-2.0 -31.22
-1.8 -24.58
-1.6 -18.37
-1.4 -12.56
-1.2 -7.57
-1.0 -3.37
-0.9 -1.75
-0.8 -0.58
-0.7 -0.05
-0.6 0.0
-0.4 0.0
-0.2 0.0
0.0 0.0
20
15
10
5
00312
Voltage
mA
I (mA)
Voltage
mA
I (mA)
Minimum VDD clamp current
(Referenced to VDD)
Minimum VSS clamp current
0
-10
-20
-30
-40
-3 0-2 -1
-50
-60
SDRAM 256Mb E-die (x4, x8, x16) CMOS SDRAM
Rev. 1.3 August 2004
SDRAM 256Mb E-die (x4, x8, x16)
SIMPLIFIED TRUTH TABLE (V=Valid, X=Don't care, H=Logic high, L=Logic low)
Command CKEn-1 CKEn CS RAS CAS WE DQM BA0,1 A10/AP A0 ~ A9
A11, A12 Note
Register Mode register set H X L L L L X OP code 1,2
Refresh
Auto refresh HHLL LHX X 3
Self
refresh
Entry L 3
Exit L H LHHHXX3
HX XX 3
Bank active & row addr. H X L L H H X V Row address
Read &
column address Auto precharge disable HXLHLHXVLColumn
address 4
Auto precharge enable H 4,5
Write &
column address Auto precharge disable HXLHLLXVLColumn
address 4
Auto precharge enable H 4,5
Burst stop H X L H H L X X 6
Precharge Bank selection HXLLHLX
VL X
All banks XH
Clock suspend or
active power down Entry H L HX XXXXLVVV
Exit L H X X X X X
Precharge power down mode Entry H L HX XXXX
LHHH
Exit L H HX XXX
LVVV
DQM H X V X 7
No operation command H X HX XXXX
LHHH
Notes :1. OP Code : Operand code
A0 ~ A12 & BA0 ~ BA1 : Program keys. (@ MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.
If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
