CD74HCT132E96 - Texas Instruments

Data sheet acquired from Harris Semiconductor

SCHS145A

Features

• Unlimited Input Rise and Fall Times

• Exceptionally High Noise Immunity

• Typical Propagation Delay: 10ns at VCC = 5V,

CL = 15pF, TA = 25oC

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating T emperature Range . . . -55oC to 125oC

• Balanced Propagation Delay and Transition Times

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: NIL = 37%, NIH = 51% of VCC

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

VIL= 0.8V (Max), VIH = 2V (Min)

- CMOS Input Compatibility, Il≤1µA at VOL, VOH

Description

The ’HC132 and ’HCT132 each contain four 2-input NAND

Schmitt Triggers in one package. This logic device utilizes

silicon gate CMOS technology to achieve operating speeds

similar to LSTTL gates with the low power consumption of

standard CMOS integrated circuits. All devices have the

ability to drive 10 LSTTL loads. The HCT logic family is

functionally pin compatible with the standard LS logic family.

Pinout

CD54HC132, CD54HCT132

(CERDIP)

CD74HC132, CD74HCT132

(PDIP, SOIC)

TOP VIEW

Ordering Information

PART NUMBER TEMP. RANGE

(oC) PACKAGE

CD54HC132F3A -55 to 125 14 Ld CERDIP

CD74HC132E -55 to 125 14 Ld PDIP

CD74HC132M -55 to 125 14 Ld SOIC

CD54HCT132F -55 to 125 14 Ld CERDIP

CD54HCT132F3A -55 to 125 14 Ld CERDIP

CD74HCT132E -55 to 125 14 Ld PDIP

CD74HCT132M -55 to 125 14 Ld SOIC

NOTES:

1. When ordering, use the entire part number. Add the sufﬁx 96 to

obtain the variant in the tape and reel.

2. Die for this part number is available which meets all electrical

specifications. Please contact your local TI sales office or cus-

tomer service for ordering information.

GND

VCC

August 1997 - Revised May 2000

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

CD54/74HC132,

CD54/74HCT132

High Speed CMOS Logic

Quad 2-Input NAND Schmitt Trigger

[ /Title

(CD74

HC132

CD74

HCT13

Sub-

ect

(High

Speed

CMOS

Logic

Quad

2-Input

NAND

Schmit

Functional Diagram

Logic Symbol

TRUTH TABLE

INPUTS OUTPUT

nA nB nY

LLH

LHH

HLH

HHL

NOTE: H = High Voltage Level, L = Low Voltage Level

GND

VCC

93A

CD54/74HC132, CD54/74HCT132

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, IIK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, IOK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Source or Sink Current per Output Pin, IO

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, VCC

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100ms (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100ms (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100ms (Max)

Thermal Resistance (Typical, Note 3) θJA (oC/W)

PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC

(SOIC - Lead Tips Only)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation

of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

NOTE:

3. θJA is measured with the component mounted on an evaluation PC board in free air.

DC Electrical Speciﬁcations

PARAMETER SYMBOL

TEST

CONDITIONS

VCC (V)

25oC -40oC TO 85oC -55oC TO 125oC

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

HC TYPES

Input Switch Points

(Note 6) VT+ - - 2 0.7 - 1.5 0.7 1.5 0.7 1.5 V

4.5 1.7 - 3.15 1.7 3.15 1.7 3.15 V

6 2.1 - 4.2 2.1 4.2 2.1 4.2 V

VT- - - 2 0.3 - 1 0.3 1 0.3 1 V

4.5 0.9 - 2.2 0.9 2.2 0.9 2.2 V

6 1.2 - 3 1.2 3 1.2 3 V

VH2 0.2 - 1 0.2 1 0.2 1 V

4.5 0.4 - 1.4 0.4 1.4 0.4 1.4 V

6 0.6 - 1.6 0.6 1.6 0.6 1.6 V

High Level Output

Voltage

CMOS Loads

VOH VT+ or

VT--0.02 2 1.9 - - 1.9 - 1.9 - V

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

High Level Output

Voltage

TTL Loads

-4 4.5 3.98 - - 3.84 - 3.7 - V

-5.2 6 5.48 - - 5.34 - 5.2 - V

CD54/74HC132, CD54/74HCT132

Low Level Output

Voltage

CMOS Loads

VOL VT+ or

VT-0.02 2 - - 0.1 - 0.1 - 0.1 V

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V

Low Level Output

Voltage

TTL Loads

4 4.5 - - 0.26 - 0.33 - 0.4 V

5.2 6 - - 0.26 - 0.33 - 0.4 V

Input Leakage

Current IIVCC or

GND -6--±0.1 - ±1-±1µA

Quiescent Device

Current ICC VCC or

GND 0 6 - - 2 - 20 - 40 µA

HCT TYPES

Input Switch Points

(Note 6) VT+ - - 4.5 1.2 - 1.9 1.2 1.9 1.2 1.9 V

5.5 1.4 - 2.1 1.4 2.1 1.4 2.1 V

VT- - - 4.5 0.5 - 1.2 0.5 1.2 0.5 1.2 V

5.5 0.6 - 1.4 0.6 1.4 0.6 1.4 V

VH- - 4.5 0.4 - 1.4 0.4 1.4 0.4 1.4 V

5.5 0.4 - 1.5 0.4 1.5 0.4 1.5 V

High Level Output

Voltage

CMOS Loads

-VT+ or

VT-- 4.5 4.4 - - 4.4 - 4.4 - V

High Level Output

Voltage

TTL Loads

- 4.5 3.98 - - 3.84 - 3.7 - V

Low Level Output

Voltage CMOS Loads VOL VT+ or

VT--4 4.5 - - 0.1 - 0.1 - 0.1 V

Low Level Output

Voltage

TTL Loads

0.02 4.5 - - 0.26 - 0.33 - 0.4 V

Input Leakage

Current IIVCC

and

GND

4 5.5 - - ±0.1 - ±1-±1µA

Quiescent Device

Current ICC VCC or

GND 0 5.5 - - 2 - 20 - 40 µA

Additional Quiescent

Device Current Per

Input Pin: 1 Unit Load

(Note 4)

∆ICC VCC

- 2.1 - 4.5 to

5.5 - 100 360 - 450 - 490 µA

NOTES:

4. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.

5. Die for this part number is available which meets all electrical specifications.

6. Hysteresis definition, characteristic and test setup see Test Circuits and Waveforms.

DC Electrical Speciﬁcations (Continued)

PARAMETER SYMBOL

TEST

CONDITIONS

VCC (V)

25oC -40oC TO 85oC -55oC TO 125oC

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

CD54/74HC132, CD54/74HCT132

HCT Input Loading Table

INPUT UNIT LOADS

nA, nB 0.6

NOTE: Unit Load is ∆ICC limit speciﬁed in DC Electrical Speciﬁca-

tions table, e.g. 360µA max at 25oC.

Switching Speciﬁcations Input tr, tf = 6ns

PARAMETER SYMBOL TEST

CONDITIONS VCC

(V)

25oC -40oC TO 85oC -55oC TO 125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

HC TYPES

Propagation Delay

A, B to Y (Figure 1) tPLH, tPHL CL= 50pF 2 - - 125 - 156 - 188 ns

4.5 - - 25 - 31 - 38 ns

6 - - 21 - 27 - 32 ns

Propagation Delay

A, B to Y tTLH, tTHL CL= 15pF 5 - 10 - ----pF

Transition Times (Figure 1) tTLH, tTHL CL= 50pF 2 - - 75 - 95 - 110 ns

4.5 - - 15 - 19 - 22 ns

6 - - 13 - 16 - 19 ns

Input Capacitance CI- - - - 10 - 10 - 10 pF

Power Dissipation Capacitance

(Notes 7, 8) CPD - 5-30-----pF

HCT TYPES

Propagation Delay

A, B to Y

(Figure 2)

tPHL, tPHL CL= 50pF 4.5 - - 33 - 41 - 50 ns

Propagation Delay

A, B to Y tPLH, tPHL CL= 15pF 5 - 13 - ----pF

Transition Times (Figure 2) tTLH, tTHL CL= 50pF 4.5 - - 15 - 19 - 22 ns

Input Capacitance CI- - - - 10 - 10 - 10 pF

Power Dissipation Capacitance

(Notes 7, 8) CPD - 5-30-----pF

NOTES:

7. CPD is used to determine the dynamic power consumption, per gate.

8. PD = VCC2 fi (CPD + CL) where fi = input frequency, CL = output load capacitance, VCC = supply voltage.

CD54/74HC132, CD54/74HCT132

Test Circuits and Waveforms

FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGA-

TION DELAY TIMES, COMBINATION LOGIC FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

FIGURE 3. HYSTERESIS DEFINITION, CHARACTERISTIC, AND TEST SET-UP

tPHL tPLH

tTHL tTLH

90%

50%

10%

50%

10%

INVERTING

OUTPUT

INPUT

GND

VCC

tr = 6ns tf = 6ns

90%

tPHL tPLH

tTHL tTLH

2.7V

1.3V

0.3V

1.3V

10%

INVERTING

OUTPUT

INPUT

GND

tr = 6ns tf = 6ns

90%

VCC

GND

VCC

GND

VCC

VlVO

VOVH

VH= V+

T- V-

V+

CD54/74HC132, CD54/74HCT132

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