18-Bit, 2.5 LSB INL, 800 kSPS, SAR ADC
Data Sheet
AD7674
Rev. B Document Feedback
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FEATURES
18-bit resolution with no missing codes
No pipeline delay (SAR architecture)
Differential input range: ±VREF (VREF up to 5 V)
Throughput
800 kSPS (warp mode)
666 kSPS (normal mode)
570 kSPS (impulse mode)
INL: ±2.5 LSB max (±9.5 ppm of full scale)
Dynamic range : 103 dB typ (VREF = 5 V)
SINAD: 100 dB typ at 2 kHz (VREF = 5 V)
Parallel (18-, 16-, or 8-bit bus) and serial 5 V/3 V interface
SPI/QSPI™/MICROWIRE/DSP compatible
On-board reference buffer
Single 5 V supply operation
Power dissipation
98 mW typ at 800 kSPS
78 mW typ at 500 kSPS (impulse mode)
160 µW at 1 kSPS (impulse mode)
48-lead LQFP or 48-lead LFCSP
Pin-to-pin compatible upgrade of AD7676, AD7678,
and AD7679
APPLICATIONS
CT scanners
High dynamic data acquisition
Geophone and hydrophone sensors
∑-∆ replacement (low power, multichannel)
Instrumentation
Spectrum analysis
Medical instruments
GENERAL DESCRIPTION
The AD7674 is an 18-bit, 800 kSPS, charge redistribution,
successive approximation register (SAR) fully differential
analog-to-digital converter (ADC) that operates on a single 5 V
power supply. The device contains a high speed, 18-bit sampling
ADC, an internal conversion clock, an internal reference buffer,
error correction circuits, and both serial and parallel system
interface ports.
The device is available in a 48-lead LQFP or a 48-lead LFCSP
with operation specified from −40°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
SWITCHED
CAP DAC
18
CONTROL LOGIC AND
CALIBRATION CIRCUITRY
CLOCK
AD7674
D[17:0]
BUSY
RD
CS
MODE0
OGND
OVDD
DGND
DVDD
AVDD
AGND
REFREFGND
IN+
IN–
PD
RESET
SERIAL
PORT
PARALLEL
INTERFACE
CNVST
PDBUF
REFBUFIN
WARP IMPULSE
MODE1
03083–0–001
Figure 1.
Table 1. PulSARTM Selection
Type
100 kSPS to
250 kSPS
500 kSPS to
570 kSPS
800 kSPS to
1000 kSPS
Pseudo-
Differential
AD7651,
AD7660/
AD7661
AD7650/AD7652,
AD7664/AD7666
AD7653,
AD7667
True Bipolar AD7663 AD7665 AD7671
True Differential AD7675 AD7676 AD7677
18-Bit AD7678 AD7679 AD7674
Multichannel/
Simultaneous
AD7654, AD7655
PRODUCT HIGHLIGHTS
1. High Resolution, Fast Throughput. The AD7674 is an
800 kSPS, charge redistribution, 18-bit, SAR ADC (no
latency).
2. Excellent Accuracy. The AD7674 has a maximum integral
nonlinearity of 2.5 LSB with no missing 18-bit codes.
3. Serial or Parallel Interface. Versatile parallel (18-, 16- or
8-bit bus) or 3-wire serial interface arrangement
compatible with both 3 V and 5 V logic.
AD7674 Data Sheet
Rev. B | Page 2 of 28
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Table of Contents .............................................................................. 2
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Timing Specifications .................................................................. 5
Absolute Maximum Ratings ............................................................ 7
ESD Caution .................................................................................. 7
Pin Configuration and Function Descriptions ............................. 8
Terminology .................................................................................... 11
Typical Performance Characteristics ........................................... 12
Circuit Information ........................................................................ 16
Converter Operation .................................................................. 16
Typical Connection Diagram ................................................... 17
Power Dissipation versus Throughput .................................... 20
Conversion Control ................................................................... 20
Digital Interface .......................................................................... 20
Parallel Interface ......................................................................... 21
Serial Interface ............................................................................ 21
Master Serial Interface ............................................................... 21
Slave Serial Interface .................................................................. 23
Microprocessor Interfacing ....................................................... 24
Applications Information .............................................................. 25
Layout .......................................................................................... 25
Evaluating AD7674 Performance ............................................. 25
Outline Dimensions ....................................................................... 26
Ordering Guide .......................................................................... 26
REVISION HISTORY
6/2016—Rev. A to Rev. B
Changed CP-48-1 to CP-48-4 and ADSP-219x to
ADSP-2191M ................................................................. Throughout
Changes to Figure 4 and Table 6 ..................................................... 8
Added Figure 5; Renumbered Sequentially .................................. 8
Changes to Serial Peripheral Interface (SPI) Section ................. 24
Updated Outline Dimensions ....................................................... 26
Changes to Ordering Guide .......................................................... 26
6/2009—Rev. 0 to Rev. A
Changes to Zero Error, TMIN to TMAX Parameter ........................... 3
Changes to Gain Error, TMIN to TMAX Parameter ........................... 3
Changes to Endnote 3 ...................................................................... 4
Changes to Pin Configuration Section .......................................... 8
Changes to Evaluating the AD7674’s Performance Section ...... 25
Changes to Ordering Guide .......................................................... 26
7/2003—Revision 0: Initial Version
Data Sheet AD7674
Rev. B | Page 3 of 28
SPECIFICATIONS
−40°C to +85°C, VREF = 4.096 V, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.
Table 2.
Parameter Test Conditions/Comments Min Typ Max Unit
RESOLUTION 18 Bits
ANALOG INPUT
Voltage Range VIN+ − VIN− −VREF +VREF V
Operating Input Voltage
V
IN+
, V
IN−
to AGND
−0.1
AVDD
V
Analog Input CMRR fIN = 100 kHz 65 dB
Input Current 800 kSPS throughput 100 µA
Input Impedance1
THROUGHPUT SPEED
Complete Cycle In warp mode 1.25 µs
Throughput Rate In warp mode 1 800 kSPS
Time Between Conversions In warp mode 1 ms
Complete Cycle In normal mode 1.5 µs
Throughput Rate
In normal mode
0
666
kSPS
Complete Cycle In impulse mode 1.75 µs
Throughput Rate In impulse mode 0 570 kSPS
DC ACCURACY
Integral Linearity Error −2.5 +2.5 LSB2
Differential Linearity Error −1 +1.75 LSB
No Missing Codes 18 Bits
Transition Noise VREF = 5 V 0.7 LSB
Zero Error, T
MIN
to T
MAX
In warp mode
−25
+25
LSB
Zero Error, TMIN to TMAX In normal mode or impulse mode −85 +85 LSB
Zero Error Temperature Drift All modes ±0.5 ppm/°C
Gain Error, TMIN to TMAX 3 In warp mode −0.034 +0.034 % of FSR
Gain Error, TMIN to TMAX3 In normal mode or impulse mode −0.048 +0.048 % of FSR
Gain Error Temperature Drift All modes ±1.6 ppm/°C
Power Supply Sensitivity
AVDD = 5 V ± 5%
±4
LSB
AC ACCURACY
Signal-to-Noise fIN = 2 kHz, VREF = 5 V 101 dB4
VREF = 4.096 V 97.5 99 dB
fIN = 10 kHz, VREF = 4.096 V 98 dB
fIN = 100 kHz, VREF = 4.096 V 97 dB
Dynamic Range VIN+ = VIN− = VREF/2 = 2.5 V 103 dB
Spurious-Free Dynamic Range fIN = 2 kHz 120 dB
f
IN
= 10 kHz
118
dB
fIN = 100 kHz 105 dB
Total Harmonic Distortion fIN = 2 kHz −115 dB
fIN = 10 kHz −113 dB
fIN = 100 kHz −98 dB
Signal-to-Noise-and-Distortion Ratio fIN = 2 kHz, VREF = 4.096 V 98 dB
f
IN
= 2 kHz, −60 dB input
40
dB
−3 dB Input Bandwidth 26 MHz
SAMPLING DYNAMICS
Aperture Delay 2 ns
Aperture Jitter 5 ps rms
Transient Response Full-scale step 250 ns
Overvoltage Recovery 250 ns
AD7674 Data Sheet
Rev. B | Page 4 of 28
Parameter Test Conditions/Comments Min Typ Max Unit
REFERENCE
External Reference Voltage Range REF 3 4.096 AVDD + 0.1 V
REF Voltage with Reference Buffer REFBUFIN = 2.5 V 4.05 4.096 4.15 V
Reference Buffer Input Voltage Range REFBUFIN 1.8 2.5 2.6 V
REFBUFIN Input Current
−1
+1
µA
REF Current Drain 800 kSPS throughput 330 µA
DIGITAL INPUTS
Logic Levels
VIL −0.3 +0.8 V
VIH +2.0 DVDD + 0.3 V
IIL −1 +1 µA
IIH −1 +1 µA
DIGITAL OUTPUTS
Data Format5
Pipeline Delay6
VOL ISINK = 1.6 mA 0.4 V
VOH ISOURCE = −500 µA OVDD − 0.6 V
POWER SUPPLIES
Specified Performance
AVDD 4.75 5 5.25 V
DVDD 4.75 5 5.25 V
OVDD 2.7 DVDD + 0.37 V
Operating Current8 800 kSPS throughput
AVDD 16 mA
DVDD9
6.5
mA
OVDD9 50 µA
POWER DISSIPATION9 PDBUF high at 500 kSPS10 78 90 mW
PDBUF high at 1 kSPS10 160 µW
PDBUF high at 800 kSPS8 114 126 mW
PDBUF low at 800 kSPS8 126 138 mW
TEMPERATURE RANGE11
Specified Performance TMIN to TMAX −40 +85 °C
1 See the Analog Inputs section.
2 LSB means least significant bit. With the ±4.096 V input range, 1 LSB is 31.25 µV.
3 See the Terminology section. The nominal gain error is not centered at zero and is −0.029% of FSR. This specification is the deviation from this nominal value. These
specifications do not include the error contribution from the external reference, but do include the error contribution from the reference buffer if used.
4 All specifications in dB are referred to a full-scale input, FS. Tested with an input signal at 0.5 dB below full scale unless otherwise specified.
5 Data format parallel or serial 18-bit.
6 Conversion results are available immediately after completed conversion.
7 The max should be the minimum of 5.25 V and DVDD + 0.3 V.
8 In warp mode.
9 Tested in parallel reading mode.
10 In impulse mode.
11 Contact factory for extended temperature range.
Data Sheet AD7674
Rev. B | Page 5 of 28
TIMING SPECIFICATIONS
−40°C to +85°C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.
Table 3.
Parameter Symbol Min Typ Max Unit
Refer to Figure 35 and Figure 36
Convert Pulse Width t1 10 ns
Time Between Conversions (Warp Mode/Normal Mode/Impulse Mode)1 t2 1.25/1.5/1.75 µs
CNVST Low to BUSY High Delay t3 35 ns
BUSY High All Modes Except Master Serial Read After Convert (Warp Mode/
Normal Mode/Impulse Mode) t4 1/1.25/1.5 µs
Aperture Delay t5 2 ns
End of Conversion to BUSY Low Delay t6 10 ns
Conversion Time (Warp Mode/Normal Mode/Impulse Mode) t7 1/1.25/1.5 µs
Acquisition Time t8 250 ns
RESET Pulse Width t9 10 ns
Refer to Figure 37, Figure 38, and Figure 39 (Parallel Interface Modes)
CNVST Low to Data Valid Delay (Warp Mode/Normal Mode/Impulse Mode) t10 1/1.25/1.5 µs
Data Valid to BUSY Low Delay t11 20 ns
Bus Access Request to Data Valid t12 45 ns
Bus Relinquish Time t13 5 15 ns
Refer to Figure 41 and Figure 42 (Master Serial Interface Modes) 2
CS Low to SYNC Valid Delay t14 10 ns
CS Low to Internal SCLK Valid Delay t15 10 ns
CS Low to SDOUT Delay t16 10 ns
CNVST Low to SYNC Delay (Warp Mode/Normal Mode/Impulse Mode) t17 25/275/525 ns
SYNC Asserted to SCLK First Edge Delay3 t18 3 ns
Internal SCLK Period
3
t
19
25
40
ns
Internal SCLK High3 t20 12 ns
Internal SCLK Low3 t21 7 ns
SDOUT Valid Setup Time3 t22 4 ns
SDOUT Valid Hold Time3 t23 2 ns
SCLK Last Edge to SYNC Delay3 t24 3
CS High to SYNC High-Z t25 10 ns
CS High to Internal SCLK High-Z t26 10 ns
CS High to SDOUT High-Z t27 10 ns
BUSY High in Master Serial Read After Convert3 t28 Table 4
CNVST Low to SYNC Asserted Delay (Warp Mode/Normal Mode/
Impulse Mode) t29 1/1.25/1.5 µs
SYNC Deasserted to BUSY Low Delay t30 25 ns
Refer to Figure 43 and Figure 44 (Slave Serial Interface Modes)
External SCLK Setup Time
t
31
5
ns
External SCLK Active Edge to SDOUT Delay t32 3 18 ns
SDIN Setup Time t33 5 ns
SDIN Hold Time t34 5 ns
External SCLK Period t35 25 ns
External SCLK High
t
36
10
ns
External SCLK Low t37 10 ns
1In warp mode only, the maximum time between conversions is 1 ms; otherwise, there is no required maximum time.
2In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum.
3In serial master read during convert mode. See Table 4 for serial master read after convert mode.
AD7674 Data Sheet
Rev. B | Page 6 of 28
Table 4. Serial Clock Timings in Master Read After Convert
DIVSCLK[1]
Symbol
0 0 1 1
Unit
DIVSCLK[0] 0 1 0 1
SYNC to SCLK First Edge Delay Minimum t18 3 17 17 17 ns
Internal SCLK Period Minimum t19 25 60 120 240 ns
Internal SCLK Period Maximum
t
19
40
80
160
320
ns
Internal SCLK High Minimum t20 12 22 50 100 ns
Internal SCLK Low Minimum t21 7 21 49 99 ns
SDOUT Valid Setup Time Minimum t22 4 18 18 18 ns
SDOUT Valid Hold Time Minimum t23 2 4 30 89 ns
SCLK Last Edge to SYNC Delay Minimum t24 3 60 140 300 ns
BUSY High Width Maximum (Warp Mode) t28 1.75 2.5 4 7 µs
BUSY High Width Maximum (Normal Mode) t28 2 2.75 4.25 7.25 µs
BUSY High Width Maximum (Impulse Mode) t28 2.25 3 4.5 7.5 µs
Data Sheet AD7674
Rev. B | Page 7 of 28
ABSOLUTE MAXIMUM RATINGS
Table 5. AD7674 Absolute Maximum Ratings
Parameter Rating
Analog Inputs
IN+1, IN−1, REF, REFBUFIN, REFGND
to AGND
AGND − 0.3 V to
AVDD + 0.3 V
Ground Voltage Differences
AGND, DGND, OGND ±0.3 V
Supply Voltages
AVDD, DVDD, OVDD −0.3 V to +7 V
AVDD to DVDD, AVDD to OVDD
±7 V
DVDD to OVDD −0.3 V to +7 V
Digital Inputs −0.3 V to DVDD + 0.3 V
Internal Power Dissipation2 700 mW
Internal Power Dissipation3 2.5 W
Junction Temperature 150°C
Storage Temperature Range −65°C to +150°C
Lead Temperature Range
(Soldering 10 sec)
300°C
1See the Analog Inputs section.
2Specification is for device in free air: 48-Lead LQFP: θJA = 91°C/W,
θJC = 30°C/W.
3 Specification is for device in free air: 48-Lead LFCSP: θJA = 26°C/W.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
TO OUTPUT
PIN C
L
60pF
1
500µAI
OH
1.6mA I
OL
1.4V
IN SERIAL INTERFACE MODES,THE SYNC, SCLK, AND
SDOUT TIMINGS ARE DEFINEDWITH A MAXIMUM LOAD
C
L
OF 10pF; OTHERWISE,THE LOAD IS 60pF MAXIMUM.
NOTE
1
03083–0–002
Figure 2. Load Circuit for Digital Interface Timing, SDOUT, SYNC, SCLK
Outputs, CL = 10 pF
0.8V 2V
2V
0.8V
t
DELAY
2V
0.8V
t
DELAY
03083–0–003
Figure 3. Voltage Reference Levels for Timing
ESD CAUTION
AD7674 Data Sheet
Rev. B | Page 8 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
48
PDBUF
47
AVDD
46
REFBUFIN
45
DNC
44
AGND
43
IN+
42
NIC
41
NIC
40
NIC
39
IN–
38
REFGND
37
REF
35 CNVST
34 PD
33 RESET
30 DGND
31 RD
32 CS
36 AGND
29 BUSY
28 D17
27 D16
25 D14
26 D15
2
AVDD
3
MODE0
4
MODE1
7
IMPULSE
6
WARP
5
D0/OB/2C
1
AGND
8
D1/A0
9
D2/A1
10
D3
12
D5/DIVSCLK[1]
11
D4/DIVSCLK[0]
NOTES
1. NIC = NO INTERN
A
L CONNECTI O N.
2. DNC = DO NO T CONNE
C
T.
13
D6/EXT/INT
14
D7/INVSYNC
15
D8/INVSCLK
16
D9/RDC/SDIN
17
OGND
18
OVDD
19
DVDD
20
DGND
21
D10/SDOUT
22
D11/SCLK
23
D12/SYNC
24
D13/RDERROR
003083–0–004
AD7674
(No t t o Scale)
TOP VIEW
Figure 4. 48-Lead LQFP Pin Configuration
NOTES
1. NIC = NO I NTE RNAL CO NNECT IO N.
2. DNC = DO NOT C ONNECT.
3. THE EXPOSE D PAD I S INT ERNAL LY CONNECTED TO AGND. THIS
CONNECTION IS NOT REQUIRED TO MEET T HE ELECTRICAL PERFORMANCES.
HOWEVER, FOR INCREASED RELIABILITY OF THE SOLDER JOINTS, IT IS
RECOMMENDED THAT THE PAD BE SOLDERED TO THE ANALOG GROUND OF
THE SYSTEM.
003083–0–104
1
2
3
AGND
CNVST
PD
4RESET
5CS
6RD
7DGND
24
D13/RDERROR 23
D12/SYNC 22
D11/SCLK 21
D10/SDOUT 20
DGND 19
DVDD 18
OVDD 17
OGND 16
D9/RDC/SDIN 15
D8/INVSCLK 14
D7/INVSYNC 13
D6/EXT/INT
44 AGND
45 DNC
46 REFBUFIN
47 AVDD
48 PDBUF
43 IN+
42 NIC
41 NIC
40 NIC
39 IN–
38 REFGND
37 REF
AD7674
TOP VIEW
(No t t o Scale)
25
D5/DIVSCLK[1] 26
D4/DIVSCLK[0] 27
D3 28
D2/A1 29
D1/A0 30
IMPULSE 31
WARP 32
D0/OB/2C 33
MODE1 34
MODE0 35
AVDD 36
AGND
8BUSY
9D17
10 D16
11 D15
12 D14
Figure 5. 48-Lead LFCSP Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Type1 Description
1, 44 AGND P Analog Power Ground Pin.
2, 47 AVDD P Input Analog Power Pins. Nominally 5 V.
3 MODE0 DI Data Output Interface Mode Selection.
4 MODE1 DI Data Output Interface Mode Selection:
Interface Mode No. MODE1 MODE0 Description
0 0 0 18-bit interface
1 0 1 16-bit interface
2 1 0 Byte interface
3 1 1 Serial interface
5 D0/OB/2C DI/O In Mode 0, 18-bit interface mode, this pin is Bit 0 of the parallel port data output bus and the data
coding is straight binary. In all other modes, this pin allows a choice of straight binary/binary twos
complement. When OB/2C is high, the digital output is straight binary; when low, the MSB is inverted,
resulting in a twos complement output from its internal shift register.
6 WARP DI
Conversion Mode Selection. When this input is high and the IMPULSE pin is low, WARP selects the
fastest mode, the maximum throughput is achievable, and a minimum conversion rate must be
applied to guarantee full specified accuracy. When low, full accuracy is maintained independent of
the minimum conversion rate.
7 IMPULSE DI
Conversion Mode Selection. When this input is high and the WARP pin is low, IMPULSE selects a
reduced power mode. In this mode, the power dissipation is approximately proportional to the
sampling rate. When the WARP pin and the IMPULSE pin are low, the normal mode is selected.
8 D1/A0 DI/O
In Mode 0, 18-bit interface mode, this pin is Bit 1 of the parallel port data output bus. In all other
modes, this input pin controls the form in which data is output, as shown in Table 7.
9 D2/A1 DI/O
In Mode 0, 18-bit interface mode, or Mode 1, 16-bit interface mode, this pin is Bit 2 of the parallel port data
output bus. In all other modes, this input pin controls the form in which data is output, as shown in Table 7.
10 D3 DO
In all modes except Mode 3, this output is used as Bit 3 of the parallel port data output bus. This pin is
always an output, regardless of the interface mode.
Data Sheet AD7674
Rev. B | Page 9 of 28
Pin No. Mnemonic Type1 Description
11, 12 D4/DIVSCLK[0],
D5/DIVSCLK[1]
DI/O In all modes except Mode 3, these pins are Bit 4 and Bit 5 of the parallel port data output bus. In
Mode 3, serial interface mode, when EXT/INT is low and RDC/SDIN is low (serial master read after
convert), these inputs, part of the serial port, are used to slow down, if desired, the internal serial
clock that clocks the data output. In other serial modes, these pins are not used.
13 D6/EXT/INT DI/O In all modes except Mode 3, this output is used as Bit 6 of the parallel port data output bus. In Mode 3,
serial interface mode, this input, part of the serial port, is used as a digital select input for choosing the
internal data clock or an external data clock. With EXT/INT tied low, the internal clock is selected on
the SCLK output. With EXT/INT set to a logic high, the output data is synchronized to an external clock
signal connected to the SCLK input.
14 D7/INVSYNC DI/O
In all modes except Mode 3, this output is used as Bit 7 of the parallel port data output bus. In Mode 3,
serial interface mode, this input, part of the serial port, is used to select the active state of the
SYNC signal. When low, SYNC is active high. When high, SYNC is active low.
15 D8/INVSCLK DI/O
In all modes except Mode 3, this output is used as Bit 8 of the parallel port data output bus. In Mode 3,
serial interface mode, this input, part of the serial port, is used to invert the SCLK signal. It is active in
both master and slave mode.
16 D9/RDC/SDIN DI/O
In all modes except Mode 3, this output is used as Bit 9 of the parallel port data output bus. In Mode 3,
serial interface mode, this input, part of the serial port, is used as either an external data input or a
read mode selection input depending on the state of EXT/INT. When EXT/INT is high, RDC/SDIN can be
used as a data input to daisy-chain the conversion results from two or more ADCs onto a single
SDOUT line. The digital data level on SDIN is output on SDOUT with a delay of 18 SCLK periods after
the initiation of the read sequence. When EXT/INT is low, RDC/SDIN is used to select the read mode.
When RDC/SDIN is high, the data is output on SDOUT during conversion. When RDC/SDIN is low, the
data can be output on SDOUT only when the conversion is complete.
17 OGND P Input/Output Interface Digital Power Ground.
18 OVDD P
Output Interface Digital Power. Nominally at the same supply as the host interface (5 V or 3 V). Should
not exceed DVDD by more than 0.3 V.
19 DVDD P Digital Power. Nominally at 5 V.
20 DGND P Digital Power Ground.
21 D10/SDOUT DO
In all modes except Mode 3, this output is used as Bit 10 of the parallel port data output bus. In Mode 3,
serial interface mode, this output, part of the serial port, is used as a serial data output synchronized
to SCLK. Conversion results are stored in an on-chip register. The AD7674 provides the conversion
result, MSB first, from its internal shift register. The data format is determined by the logic level of
OB/2C. In serial mode when EXT/INT is low, SDOUT is valid on both edges of SCLK. In serial mode
when EXT/INT is high and INVSCLK is low, SDOUT is updated on the SCLK rising edge and is valid on
the next falling edge; if INVSCLK is high, SDOUT is updated on the SCLK falling edge and is valid on the
next rising edge.
22 D11/SCLK DI/O
In all modes except Mode 3, this output is used as Bit 11 of the parallel port data output bus. In Mode 3,
serial interface mode, this pin, part of the serial port, is used as a serial data clock input or output,
dependent upon the logic state of the EXT/INT pin. The active edge where the data SDOUT is updated
depends upon the logic state of the INVSCLK pin.
23 D12/SYNC DO
In all modes except Mode 3, this output is used as Bit 12 of the parallel port data output bus. In Mode 3,
serial interface mode, this output, part of the serial port, is used as a digital output frame synchronization
for use with the internal data clock (EXT/INT = logic low). When a read sequence is initiated and INVSYNC is
low, SYNC is driven high and remains high while the SDOUT output is valid. When a read sequence is
initiated and INVSYNC is high, SYNC is driven low and remains low while SDOUT output is valid.
24 D13/RDERROR DO
In all modes except Mode 3, this output is used as Bit 13 of the parallel port data output bus. In
Mode 3, serial interface mode, and when EXT/INT is high, this output, part of the serial port, is used as
an incomplete read error flag. In slave mode, when a data read is started and not complete when the
following conversion is complete, the current data is lost and RDERROR is pulsed high.
25 to
28
D14 to D17 DO Bit 14 to Bit 17 of the Parallel Port Data Output Bus. These pins are always outputs regardless of the
interface mode.
29 BUSY DO
Busy Output. Transitions high when a conversion is started. Remains high until the conversion is
complete and the data is latched into the on-chip shift register. The falling edge of BUSY can be used
as a data ready clock signal.
30 DGND P Must Be Tied to Digital Ground.
31 RD DI Read Data. When CS and RD are both low, the interface parallel or serial output bus is enabled.
AD7674 Data Sheet
Rev. B | Page 10 of 28
Pin No. Mnemonic Type1 Description
32 CS DI Chip Select. When CS and RD are both low, the interface parallel or serial output bus is enabled. CS is
also used to gate the external clock.
33 RESET DI
Reset Input. When set to a logic high, reset the AD7674. Current conversion, if any, is aborted. If not
used, this pin can be tied to DGND.
34 PD DI
Power-Down Input. When set to a logic high, power consumption is reduced and conversions are
inhibited after the current one is completed.
35 CNVST DI Start Conversion. A falling edge on CNVST puts the internal sample/hold into the hold state and
initiates a conversion. In impulse mode (IMPULSE high, WARP low), if CNVST is held low when the
acquisition phase (t8) is complete, the internal sample/hold is put into hold and a conversion is
immediately started.
36 AGND P Must Be Tied to Analog Ground.
37 REF AI
Reference Input Voltage and Internal Reference Buffer Output. Apply an external reference on REF if
the internal reference buffer is not used. Should be decoupled effectively with or without the internal
buffer.
38 REFGND AI Reference Input Analog Ground.
39 IN– AI Differential Negative Analog Input.
40 to
42
NIC No Internal Connection.
43 IN+ AI Differential Positive Analog Input.
45 DNC Do Not Connect. Do not connect to this pin.
46 REFBUFIN AI
Reference Buffer Input Voltage. The internal reference buffer has a fixed gain. It outputs 4.096 V
typically when 2.5 V is applied on this pin.
48 PDBUF DI Allows Choice of Buffering Reference. When low, buffer is selected. When high, buffer is switched off.
0 EPAD Exposed Pad. The exposed pad is internally connected to AGND. This connection is not required to
meet the electrical performances. However, for increased reliability of the solder joints, it is
recommended that the pad be soldered to the analog ground of the system.
1AI = Analog Input; DI = Digital Input; DI/O = Bidirectional Digital; DO = Digital Output; P = Power.
Table 7. Data Bus Interface Definitions1
Mode MODE1 MODE0 D0/OB/2C D1/A0 D2/A1 D[3] D[4:9] D[10:11] D[12:15] D[16:17] Description
0 0 0 R[0] R[1] R[2] R[3] R[4:9] R[10:11] R[12:15] R[16:17] 18-bit parallel
1 0 1 OB/2C A0:0 R[2] R[3] R[4:9] R[10:11] R[12:15] R[16:17] 16-bit high word
1 0 1 OB/2C A0:1 R[0] R[1] All zeros 16-bit low word
2 1 0 OB/2C A0:0 A1:0 All high-Z R[10:11] R[12:15] R[16:17] 8-bit high byte
2 1 0 OB/2C A0:0 A1:1 All high-Z R[2:3] R[4:7] R[8:9] 8-bit mid byte
2 1 0 OB/2C A0:1 A1:0 All high-Z R[0:1] All zeros 8-bit low byte
2 1 0 OB/2C A0:1 A1:1 All high-Z All zeros R[0:1] 8-bit low byte
3 1 1 OB/2C All high-Z Serial interface Serial interface
1 R[0:17] is the 18-bit ADC value stored in its output register.
Data Sheet AD7674
Rev. B | Page 11 of 28
TERMINOLOGY
Integral Nonlinearity Error (INL)
Linearity error refers to the deviation of each individual code
from a line drawn from negative full scale through positive full
scale. The point used as negative full scale occurs ½ LSB before
the first code transition. Positive full scale is defined as a level
1½ LSB beyond the last code transition. The deviation is measured
from the middle of each code to the true straight line.
Differential Nonlinearity Error (DNL)
In an ideal ADC, code transitions are 1 LSB apart. Differential
nonlinearity is the maximum deviation from this ideal value. It
is often specified in terms of resolution for which no missing
codes are guaranteed.
Gain Error
The first transition (from 000…00 to 000…01) should occur for
an analog voltage ½ LSB above the nominal negative full scale
(−4.095991 V for the ±4.096 V range). The last transition (from
111…10 to 111…11) should occur for an analog voltage 1½ LSB
below the nominal full scale (4.095977 V for the ±4.096 V
range). The gain error is the deviation of the difference between
the actual level of the last transition and the actual level of the
first transition from the difference between the ideal levels.
Zero Error
The zero error is the difference between the ideal midscale
input voltage (0 V) from the actual voltage producing the
midscale output code.
Spurious-Free Dynamic Range (SFDR)
SFDR is the difference, in decibels (dB), between the rms
amplitude of the input signal and the peak spurious signal.
Effective Number of Bits (ENOB)
ENOB is a measurement of the resolution with a sine wave
input, and is expressed in bits. It is related to SINAD by the
following formula:
ENOB = (SINADdB – 1.76)/6.02
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal, and is
expressed in decibels.
Dynamic Range
Dynamic range is the ratio of the rms value of the full scale to
the rms noise measured with the inputs shorted together. The
value for dynamic range is expressed in decibels.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.
Signal-to-Noise-and-Distortion Ratio (SINAD)
SINAD is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
SINAD is expressed in decibels.
Aperture Delay
Aperture delay is a measure of the acquisition performance and
is measured from the falling edge of the CNVST input to when
the input signal is held for a conversion.
Transient Response
Transient response is the time required for the AD7674 to
achieve its rated accuracy after a full-scale step function is
applied to its input.
AD7674 Data Sheet
Rev. B | Page 12 of 28
TYPICAL PERFORMANCE CHARACTERISTICS
CODE
2.5
0 65536 131072 196608 262144
INL - L S B (18 -Bit)
1.5
1.0
0
–1.5
0.5
–0.5
03083-0-005
–1.0
2.0
Figure 6. Integral Nonlinearity vs. Code
CODE IN HEX
70000
2004C
0
COUNTS
60000
40000
20000
0
30000
10000
50000
2004D
0
2004E
87
2004F
5073
20050
59121
20051 20052 20053
47
20054
0
20055
0
V
REF
= 5V
7165
58556
03083-0-006
Figure 7. Histogram of 131,072 Conversions of a
DC Input at the Code Transition
POSITIVE INL (LSB)
120
0
NUMBER OF UNITS
100
60
20
0
40
80
0.5 1.0 1.5 2.0
03083-0-007
2.5
Figure 8. Typical Positive INL Distribution (424 Units)
CODE
2.0
0 65536 131072 196608 262144
DNL- L S B (18- Bit)
1.5
1.0
0
–1.0
0.5
–0.5
03083-0-008
Figure 9. Differential Nonlinearity vs. Code
CODE IN HEX
90000
2004D
0
COUNTS
60000
40000
20000
0
30000
10000
50000
1
2004E 2004F 20050 20051 20052 20053
627
20054
8
20055
0
V
REF
= 5V
25964
70000
80000
26939
28939
03083-0-009
793
Figure 10. Histogram of 131,072 Conversions of a
DC Input at the Code Center
NEGATIVE INL (LSB)
100
–2.5
NUMBER OF UNITS
80
60
20
0
50
70
–2.0 –1.5 1.0 –0.5
03083-0-010
90
40
30
10
0
Figure 11. Typical Negative INL Distribution (424 Units)
Data Sheet AD7674
Rev. B | Page 13 of 28
POSITIVE DNL (LSB)
120
0
NUMBER OF UNITS
100
60
20
0
40
80
0.5 1.0 1.5
03083-0-011
2.0
Figure 12. Typical Positive DNL Distribution (424 Units)
FREQUENCY (kHz)
0
0 50 100 400
AMPLITUDE (dB of Full Scale)
–40
–60
–100
–180
–80
–120
03083-0-012
–140
–20
–160
150 200 250 300 350
f
S
= 800kSPS
f
IN
= 10kHz
V
REF
= 4.096V
SNR = 98.4dB
THD = 119.1dB
SFDR = 120.4dB
SINAD = 98.4dB
Figure 13. FFT (10 kHz Tone)
FREQUENCY (kHz)
0
0 50 100 400
AMPLITUDE (dB of Full Scale)
–40
–60
–100
–180
–80
–120
03083-0-013
–140
–20
–160
150 200 250 300 350
f
S
= 800kSPS
f
IN
= 100kHz
V
REF
= 4.096V
SNR = 98.8dB
THD = 104.3dB
SFDR = 104.9dB
SINAD = 97.8dB
Figure 14. FFT (100 kHz Tone)
NEGATIVE DNL (LSB)
250
–2.0
NUMBER OF UNITS
200
150
50
0–1.5 –1.0 –0.5
03083-0-014
100
0
Figure 15. Typical Negative DNL Distribution (424 Units)
FRE QUENCY (kHz)
102
1
SNR AND SINAD (dB)
99
90
78
75
84
96
10 100 1000
03083-0-015
93
81
87
ENOB
SINAD
SNR
16.0
16.5
15.0
15.5
14.0
14.5
13.5
ENOB (Bits)
Figure 16. SNR, SINAD, and ENOB vs. Frequency
FREQUENCY (kHz)
–60
1
THD, HARMONICS (dB)
–70
–100
–130
–120
–80
10 100 1000
03083-0-016
–90
–110
THD
THIRD
HARMONIC
SFDR
140
60
20
40
0
SFDR (dB)
120
80
100
SECOND
HARMONIC
Figure 17. THD, SFDR, and Harmonics vs. Frequency
AD7674 Data Sheet
Rev. B | Page 14 of 28
INPUT LEVEL (dB)
–60
SNR REF E RRED TO F UL L SCALE (dB)
101
98
95
96
100
03083-0-017
99
97
SNR
–50 0–10–20–30–40
105
102
104
103
V
REF
= 4.096V
SINAD
Figure 18. SNR and SINAD vs. Input Level
–55
SNR, S I NAD ( d B)
98
96
03083-0-018
99
97
–35 12585655–15
100
SNR
ENOB
14.5
15.0
15.5
16.5
16.0
SINAD
25 45 105
TE M P E RATURE (C)
V
REF
= 4.096V
ENOB (Bits)
Figure 19. SNR, SINAD, and ENOB vs. Temperature
TEMPERATURE (C)
–55
THD, HARMONICS (dB)
–120
–140
03083-0-019
–110
–130
–35 12585655–15
–100
25 45 105
THIRD
HARMONIC
SECOND
HARMONIC
THD
Figure 20. THD and Harmonics vs. Temperature
SAMPLING RATE (SPS)
100000
OPERATING CURRENTS (A)
0.001 1M
10000
1000
100
10
1
0.1
0.01
100k10k1k1001
AVDD,WARP/NORMAL
AVDD, IMPULSE
10
DVDD,WARP/NORMAL
DVDD, IMPULSE
OVDD, ALL MODES
PDBUF HIGH
03083-0-020
Figure 21. Operating Current vs. Sampling Rate
TEMPERATURE (
C)
800
–55
POWER-DOWN OPERATING CURRENTS (nA)
700
500
300
0
400
100
600
125
DVDD
–35–155 25456585105
AVDD
OVDD
03083-0-021
Figure 22. Power-Down Operating Currents vs. Temperature
TEMPERATURE (
C)
–55
ZERO ERROR,POSITIVE AND
NEGATIVE FULL SCALE (LSB)
–15
–25
03083-0-022
–20
–35 12585655–15
25
25 45 105
–5
5
–10
0
10
15
20
POSITIVE
FULL SCALE
NEGATIVE
FULL SCALE
ZERO ERROR
Figure 23. Zero Error, Positive Full Scale, and Negative Full Scale vs.
Temperature
Data Sheet AD7674
Rev. B | Page 15 of 28
AVDD (V)
4.50
20
–30
03083-0-023
5.505.254.75
30
5.00
10
10
20
ZERO ERROR,POSITIVE AND
NEGATIVE FULL SCALE (LSB)
POSITIVE
FULL SCALE
NEGATIVE
FULL SCALE
ZERO ERROR
0
Figure 24. Zero Error, Positive Full Scale, and Negative Full Scale vs. Supply
C
L
(pF)
0
t
12
DELAY (ns)
10
0
03083-0-024
20015050
50
100
30
20
40 OVDD = 2.7V @ 85°C
OVDD = 5V @ 85°C
OVDD = 5V @ 25°C
OVDD = 2.7V @ 25°C
Figure 25. Typical Delay vs. Load Capacitance (CL)
AD7674 Data Sheet
Rev. B | Page 16 of 28
CIRCUIT INFORMATION
IN+
REF
REFGND
IN–
MSB 4C 2C C C LSB SW+ SWITCHES
CONTROL
262,144C 131,072C
MSB
4C 2C C C LSB SW–
BUSY
OUTPUT
CODE
CNVST
CONTROL
LOGIC
COMP
262,144C 131,072C
03083–0–025
Figure 26. ADC Simplified Schematic
The AD7674 is a very fast, low power, single-supply, precise
18-bit analog-to-digital converter (ADC) using successive
approximation architecture.
The linearity and dynamic range of the AD7674 are similar
to or better than many ∑-Δ ADCs. With the advantages of its
successive architecture, which ease multiplexing and reduce
power with throughput, it can be advantageous in applications
that normally use ∑-Δ ADCs.
The AD7674 features different modes to optimize performance
according to the applications. In warp mode, the AD7674 is
capable of converting 800,000 samples per second (800 kSPS).
The AD7674 provides the user with an on-chip track/hold,
successive approximation ADC that does not exhibit any
pipeline or latency, making it ideal for multiple multiplexed
channel applications.
The AD7674 can be operated from a single 5 V supply and can
be interfaced to either 5 V or 3 V digital logic. It is housed in a
48-lead LQFP, or a tiny 48-lead LFCSP that offers space savings
and allows for flexible configurations as either a serial or
parallel interface. The AD7674 is a pin-to-pin compatible
upgrade of the AD7676, AD7678, and AD7679.
CONVERTER OPERATION
The AD7674 is a successive approximation ADC based on a
charge redistribution DAC. Figure 26 shows the simplified
schematic of the ADC. The capacitive DAC consists of two
identical arrays of 18 binary weighted capacitors that are
connected to the two comparator inputs.
During the acquisition phase, terminals of the array tied to the
input of the comparator are connected to AGND via SW+ and
SW−. All independent switches are connected to the analog
inputs. Thus, the capacitor arrays are used as sampling capacitors
and acquire the analog signal on the IN+ and IN− inputs. When
the acquisition phase is complete and the CNVST input goes
low, a conversion phase is initiated. When the conversion phase
begins, SW+ and SW− are opened first. The two capacitor
arrays are then disconnected from the inputs and connected to
the REFGND input. Therefore, the differential voltage between
the IN+ and IN– inputs captured at the end of the acquisition
phase is applied to the comparator inputs, causing the comparator
to become unbalanced. By switching each element of the capacitor
array between REFGND and REF, the comparator input varies by
binary weighted voltage steps (VREF/2, VREF/4, ... VREF/262144). The
control logic toggles these switches, starting with the MSB first,
to bring the comparator back into a balanced condition. After
completing this process, the control logic generates the ADC
output code and brings the BUSY output low.
Modes of Operation
The AD7674 features three modes of operation: warp, normal,
and impulse. Each mode is more suited for specific applications.
Warp mode allows conversion rates up to 800 kSPS. However,
in this mode and this mode only, the full specified accuracy is
guaranteed only when the time between conversions does not
exceed 1 ms. If the time between two consecutive conversions is
longer than 1 ms (for example, after power-up), the first conversion
result should be ignored. This mode makes the AD7674 ideal
for applications where a fast sample rate is required.
Normal mode is the fastest mode (666 kSPS) without any
limitation on the time between conversions. This mode makes
the AD7674 ideal for asynchronous applications such as data
acquisition systems, where both high accuracy and fast sample
rate are required.
Impulse mode, the lowest power dissipation mode, allows power
saving between conversions. The maximum throughput in this
mode is 570 kSPS. When operating at 1 kSPS, for example, it
typically consumes only 136 μW. This feature makes the
AD7674 ideal for battery-powered applications.
Data Sheet AD7674
Rev. B | Page 17 of 28
Transfer Functions
Except in 18-bit interface mode, the AD7674 offers straight
binary and twos complement output coding when using OB/2C.
See Figure 27 and Table 8 for the ideal transfer characteristic.
000...000
000...001
000...010
111...101
111...110
111...111
ANALOG INPUT+FS – 1.5 LSB
+FS – 1 LSB
–FS + 1 LSB–FS
–FS + 0.5 LSB
ADC CODE (Straight Binary)
03083-0-026
Figure 27. ADC Ideal Transfer Function
Table 8. Output Codes and Ideal Input Voltages
Description
Analog Input
VREF = 4.096 V
Straight
Binary
(Hex)
Twos
Complement
(Hex)
FSR − 1 LSB 4.095962 V 3FFFF1 1FFFF1
FSR − 2 LSB 4.095924 V 3FFFE 1FFFE
Midscale + 1 LSB 31.25 μV 20001 00001
Midscale 0 V 20000 00000
Midscale − 1 LSB −31.25 μV 1FFFF 3FFFF
−FSR + 1 LSB −4.095962 V 00001 20001
−FSR −4.096 V 000002 200002
1 This is also the code for overrange analog input (VIN+ – VIN− above VREF –
VREFGND).
2 This is also the code for underrange analog input (VIN+ – VIN− below –VREF +
VREFGND).
TYPICAL CONNECTION DIAGRAM
Figure 28 shows a typical connection diagram for the AD7674.
Different circuitry shown on this diagram is optional and is
discussed later in this data sheet.
AVDD AGND DGND DVDD OVDD OGND
CNVST
BUSY
SDOUT
SCLK
RD
CS
RESET
PD
2.5V REF
NOTE 1
REFBUFIN
20
D
CLOCK
AD7674
C/P/DSP
SERIAL PORT
DIGITAL SUPPLY
(3.3V OR 5V)
ANALOG
SUPPLY
(5V)
DVDD
OB/2C
NOTE 6
PDBUF
DVDD
50k
100nF
1M
IN+
ANALOG INPUT+
C
C
2.7nF
U1
NOTE 3
NOTE 4
50
AD8021
–
+
15
NOTE 2
NOTE 5
ADR421
10F100nF
+10F 100nF
+100nF +10F
IN–
ANALOG INPUT–
C
C
2.7nF
U2
NOTE 3
NOTE 4
50
AD8021
–
+
15
50
100nF
NOTES
1. SEEVOLTAGE REFERENCE INPUT SECTION.
2. OPTIONAL CIRCUITRY FOR HARDWARE GAIN CALIBRATION.
3.THE AD8021 IS RECOMMENDED. SEE DRIVER AMPLIFIER CHOICE SECTION.
4. SEE ANALOG INPUTS SECTION.
5. OPTION, SEE POWER SUPPLY SECTION.
6. OPTIONAL LOW JITTER CNVST, SEE CONVERSION CONTROL SECTION.
47F
MODE1
MODE0
NOTE 1
C
REF
REF
REFGND
03083-0-027
Figure 28. Typical Connection Diagram (Internal Reference Buffer, Serial Interface)
AD7674 Data Sheet
Rev. B | Page 18 of 28
Analog Inputs
Figure 29 shows a simplified analog input section of the AD7674.
The diodes shown in Figure 29 provide ESD protection for the
inputs. Care must be taken to ensure that the analog input signal
never exceeds the absolute ratings on these inputs. This causes
these diodes to become forward biased and start conducting
current. These diodes can handle a forward-biased current of
120 mA max. This condition can eventually occur when the U1
or U2 supplies of the input buffer are different from AVDD. In
such a case, an input buffer with a short-circuit current
limitation can be used to protect the device.
IN+
IN–
AGND
AVDD
R+ = 102Ω
C
S
C
S
R– = 102Ω
03083-0-028
Figure 29. Simplified Analog Input
This analog input structure is a true differential structure. By
using these differential inputs, signals common to both inputs
are rejected as shown in Figure 30, which represents typical
CMRR over frequency.
FREQUECY (kHz)
66
CMRR (dB)
64
50 100 1000 100001 10
62
60
58
56
54
52
03083-0-029
Figure 30. Analog Input CMRR vs. Frequency
During the acquisition phase for ac signals, the AD7674 behaves
like a 1-pole RC filter consisting of the equivalent resistance R+,
R–, and CS. The R+ and R– resistors are typically 102 Ω and are
lumped components made up of a serial resistor and the on
resistance of the switches. CS is typically 60 pF and mainly
consists of the ADC sampling capacitor. This 1-pole filter with a
−3 dB cutoff frequency of 26 MHz typ reduces any undesirable
aliasing effect and limits the noise coming from the inputs.
Because the input impedance of the AD7674 is very high, the
device can be driven directly by a low impedance source without
gain error. This allows the user to put an external 1-pole RC
filter between the amplifier output and the ADC analog inputs,
as shown in Figure 28, to improve the noise filtering done by the
AD7674 analog input circuit. However, the source impedance has
to be kept low because it affects the ac performance, especially
the total harmonic distortion (THD). The maximum source
impedance depends on the amount of THD that can be tolerated.
The THD degrades as a function of source impedance and the
maximum input frequency, as shown in Figure 31.
INPUT RESISTANCE (Ω)
–95
THD (dB)
–120 45 75 10515
–100
–105
–110
–115
20kHz
10kHz
2kHz
03083-0-030
Figure 31. THD vs. Analog Input Frequency and Source Resistance
Driver Amplifier Choice
Although the AD7674 is easy to drive, the driver amplifier
needs to meet the following requirements:
• The driver amplifier and the AD7674 analog input circuit
have to be able to settle for a full-scale step of the capacitor
array at an 18-bit level (0.0004%). In the amplifier data sheet,
settling at 0.1% or 0.01% is more commonly specified. This
can differ significantly from the settling time at an 18-bit
level and, therefore, should be verified prior to driver
selection. The tiny op amp AD8021, which combines
ultralow noise and high gain-bandwidth, meets this
settling time requirement.
• The noise generated by the driver amplifier needs to be
kept as low as possible to preserve the SNR and transition
noise performance of the AD7674. The noise coming from
the driver is filtered by the AD7674 analog input circuit 1-
pole low-pass filter made by R+, R–, and CS. The SNR
degradation due to the amplifier is
=
π+ 2
)(625
25
log20
N
3dB–
LOSS
Ne
f
SNR
where:
f–3dB is the –3 dB input bandwidth in MHz of the AD7674
(26 MHz) or the cutoff frequency of the input filter, if used.
N is the noise factor of the amplifiers (1 if in buffer
configuration).
eN is the equivalent input noise voltage of each op amp in
nV/√Hz.
Data Sheet AD7674
Rev. B | Page 19 of 28
For instance, for a driver with an equivalent input noise of
2 nV/√Hz (for example, the AD8021) configured as a buffer,
thus with a noise gain of +1, the SNR degrades by only 0.34 dB
with the filter in Figure 28, and by 1.8 dB without it.
• The driver needs to have a THD performance suitable to
that of the AD7674.
The AD8021 meets these requirements and is usually appropriate
for almost all applications. The AD8021 needs a 10 pF external
compensation capacitor, which should have good linearity as an
NPO ceramic or mica type.
The AD8022 can be used if a dual version is needed and gain of
1 is present. The AD829 is an alternative in applications where
high frequency (above 100 kHz) performance is not required. In
gain of 1 applications, it requires an 82 pF compensation capacitor.
The AD8610 is another option when low bias current is needed
in low frequency applications.
Single-to-Differential Driver
For applications using unipolar analog signals, a single-ended-
to-differential driver allows for a differential input into the device.
The schematic is shown in Figure 32. When provided an input
signal of 0 to VREF, this configuration produces a differential
±VREF with midscale at VREF/2.
If the application can tolerate more noise, the AD8138
differential driver can be used.
U2
8.25kΩ
2.5V
AD8021
590Ω
AD7674
IN+
IN–
REF
U1
ANALOG INPUT
(UNIPOLAR
0V TO 4.096V) 10pF
AD8021
590Ω
10pF 10
µ
F
100nF
1.82kΩ2.7nF
15Ω
2.7nF
15Ω
REFBUFIN
03083-0-031
Figure 32. Single-Ended-to-Differential Driver Circuit
(Internal Reference Buffer Used)
Voltage Reference
The AD7674 allows the use of an external voltage reference
either with or without the internal reference buffer.
Using the internal reference buffer is recommended when
sharing a common reference voltage between multiple ADCs is
desired.
However, the advantages of using the external reference voltage
directly are:
• The SNR and dynamic range improvement (about 1.7 dB)
resulting from the use of a reference voltage very close to
the supply (5 V) instead of a typical 4.096 V reference
when the internal buffer is used.
• The power saving when the internal reference buffer is
powered down (PDBUF High)
To u se t he internal reference buffer, PDBUF should be LOW. A
2.5 V reference voltage applied on the REFBUFIN input results
in a 4.096 V reference on the REF pin.
In both cases, the voltage reference input REF has a dynamic
input impedance and therefore requires an efficient decoupling
between REF and REFGND inputs, The decoupling consists of
a low ESR 47 µF tantalum capacitor connected to the REF and
REFGND inputs with minimum parasitic inductance.
Care should also be taken with the reference temperature
coefficient of the voltage reference, which directly affects the
full-scale accuracy if this parameter matters. For instance, a
±4 ppm/°C temperature coefficient of the reference changes the
full scale by ±1 LSB/°C.
Power Supply
The AD7674 uses three sets of power supply pins: an analog 5 V
supply (AVDD), a digital 5 V core supply (DVDD), and a digital
output interface supply (OVDD). The OVDD supply defines
the output logic level and allows direct interface with any logic
working between 2.7 V and DVDD + 0.3 V. To reduce the
number of supplies needed, the digital core (DVDD) can be
supplied through a simple RC filter from the analog supply, as
shown in Figure 28. The AD7674 is independent of power
supply sequencing once OVDD does not exceed DVDD by
more than 0.3 V, and is therefore free from supply voltage
induced latch-up. Additionally, it is very insensitive to power
supply variations over a wide frequency range, as shown in
Figure 33.
AD7674 Data Sheet
Rev. B | Page 20 of 28
FREQUECY (kHz)
70
PSRR (dB)
65
40 100 1000 100001 10
60
55
50
45
03083-0-032
Figure 33. PSRR vs. Frequency
POWER DISSIPATION VERSUS THROUGHPUT
In Impulse mode, the AD7674 automatically reduces its power
consumption at the end of each conversion phase. During the
acquisition phase, the operating currents are very low, which
allows for a significant power savings when the conversion rate
is reduced, as shown in Figure 34. This feature makes the AD7674
ideal for very low power battery applications. It should be noted
that the digital interface remains active even during the acquisition
phase. To reduce the operating digital supply currents even
further, the digital inputs need to be driven close to the power
rails (DVDD and DGND), and OVDD should not exceed
DVDD by more than 0.3 V.
SAMPLING RATE (SPS)
1000000
POWER DISSAPATION (µW)
1M
100000
10000
1000
100
10
1
0.1 100k10k1k1001
WARP/NORMAL
10
PDBUFHIGH
03083-0-033
IMPULSE
Figure 34. Power Dissipation vs. Sample Rate
CONVERSION CONTROL
Figure 35 shows the detailed timing diagrams of the conversion
process. The AD7674 is controlled by the CNVST signal, which
initiates conversion. Once initiated, it cannot be restarted or
aborted, even by PD, until the conversion is complete. The
CNVST signal operates independently of CS and RD signals.
CNVST
t
1
t
2
MODE ACQUIRE CONVERT ACQUIRE CONVERT
t
7
t
8
BUSY
t
4
t
3
t
5
t
6
03083-0-034
Figure 35. Basic Conversion Timing
Although CNVST is a digital signal, it should be designed with
special care with fast, clean edges and levels with minimum
overshoot and undershoot or ringing.
For applications where SNR is critical, the CNVST signal should
have very low jitter. This may be achieved by using a dedicated
oscillator for CNVST generation, or to clock it with a high
frequency low jitter clock, as shown in Figure 28.
In Impulse mode, conversions can be initiated automatically. If
CNVST is held low when BUSY goes low, the AD7674 controls
the acquisition phase and automatically initiates a new conversion.
By keeping CNVST low, the AD7674 keeps the conversion process
running by itself. Note that the analog input has to be settled
when BUSY goes low. Also, at power-up, CNVST should be
brought low once to initiate the conversion process. In this
mode, the AD7674 can sometimes run slightly faster than the
guaranteed limits of 570 kSPS in Impulse mode. This feature
does not exist in Warp or Normal modes.
DIGITAL INTERFACE
The AD7674 has a versatile digital interface; it can be interfaced
with the host system by using either a serial or parallel interface.
The serial interface is multiplexed on the parallel data bus. The
AD7674 digital interface also accommodates both 3 V and 5 V
logic by simply connecting the OVDD supply pin of the AD7674
to the host system interface digital supply. Finally, by using the
OB/2C input pin in any mode but 18-bit interface mode, both
twos complement and straight binary coding can be used.
The two signals, CS and RD, control the interface. When at least
one of these signals is high, the interface outputs are in high
impedance. Usually, CS allows the selection of each AD7674 in
multicircuit applications, and is held low in a single AD7674
design. RD is generally used to enable the conversion result on
the data bus.
Data Sheet AD7674
Rev. B | Page 21 of 28
t
9
RESET
DATA
BUS
BUSY
CNVST
t
8
03083-0-035
Figure 36. RESET Timing
CNVST
BUSY
DATA
BUS
CS = RD = 0
PREVIOUS CONVERSION DATA NEW DATA
t
1
t
10
t
4
t
3
t
11
03083-0-036
Figure 37. Master Parallel Data Timing for Reading (Continuous Read)
PARALLEL INTERFACE
The AD7674 is configured to use the parallel interface with an
18-bit, a 16-bit, or an 8-bit bus width, according to Table 7. The
data can be read either after each conversion, which is during
the next acquisition phase, or during the following conversion,
as shown in Figure 38 and Figure 39, respectively. When the
data is read during the conversion, however, it is recommended
that it is read only during the first half of the conversion phase.
This avoids any potential feedthrough between voltage transients
on the digital interface and the most critical analog conversion
circuitry. Refer to Table 7 for a detailed description of the
different options available.
DATA
BUS
t12 t13
BUSY
CS
RD
CURRENT
CONVERSION
03083-0-037
Figure 38. Slave Parallel Data Timing for Reading (Read After Convert)
CS = 0
CNVST,
RD
t1
PREVIOUS
CONVERSION
DATA
BUS
t12 t13
BUSY
t4
t3
03083-0-038
Figure 39. Slave Parallel Data Timing for Reading (Read During Convert)
CS
RD
A0, A1
PINS D[15:8]
PINS D[7:0] HI-Z
HI-Z HIGH BYTE LOW BYTE
LOW BYTE HIGH BYTE HI-Z
HI-Z
t12 t12 t13
03083-0-039
Figure 40. 8-Bit and 16-Bit Parallel Interface
SERIAL INTERFACE
The AD7674 is configured to use the serial interface when MODE0
and MODE1 are held high. The AD7674 outputs 18 bits of data,
MSB first, on the SDOUT pin. This data is synchronized with
the 18 clock pulses provided on the SCLK pin. The output data
is valid on both the rising and falling edge of the data clock.
MASTER SERIAL INTERFACE
Internal Clock
The AD7674 is configured to generate and provide the serial
data clock SCLK when the EXT/INT pin is held low. The AD7674
also generates a SYNC signal to indicate to the host when the
serial data is valid. The serial clock SCLK and the SYNC signal
can be inverted if desired. Depending on the RDC/SDIN input,
the data can be read after each conversion or during the following
conversion. Figure 41 and Figure 42 show the detailed timing
diagrams of these two modes.
Usually, because the AD7674 is used with a fast throughput, the
master read during conversion mode is the most recommended
serial mode.
In read during conversion mode, the serial clock and data
toggle at appropriate instants, minimizing potential feedthrough
between digital activity and critical conversion decisions.
In read after conversion mode, note that unlike in other modes,
the BUSY signal returns low after the 18 data bits are pulsed out
and not at the end of the conversion phase, which results in a
longer BUSY width. To accommodate slow digital hosts, the
serial clock can be slowed down by using DIVSCLK.
AD7674 Data Sheet
Rev. B | Page 22 of 28
t
3
BUSY
CS, RD
CNVST
SYNC
SCLK
SDOUT
1 2 3 16 1718
D17 D16 D2 D1 D0X
EXT/INT = 0 RDC/SDIN = 0 INVSCLK = INVSYNC = 0
t
14
t
20
t
15
t
16
t
22
t
23
t
29
t
28
t
18
t
19
t
21
t
30
t
25
t
24
t
26
t
27
03083-0-040
Figure 41. Master Serial Data Timing for Reading (Read After Convert)
RDC/SDIN = 1 INVSCLK = INVSYNC = 0
D17 D16 D2 D1 D0X
1 2 3 16 17 18
BUSY
SYNC
SCLK
SDOUT
CS, RD
CNVST
t3
t1
t17
t14
t15
t19
t20 t21
t16 t22 t23
t24
t27
t26
t25
t
18
EXT/INT = 0
03083-0-046
Figure 42. Master Serial Data Timing for Reading (Read Previous Conversion During Convert)
Data Sheet AD7674
Rev. B | Page 23 of 28
SLAVE SERIAL INTERFACE
External Clock
The AD7674 is configured to accept an externally supplied
serial data clock on the SCLK pin when the EXT/INT pin is
held high. In this mode, several methods can be used to read
the data. The external serial clock is gated by CS. When CS and
RD are both low, the data can be read after each conversion or
during the following conversion. The external clock can be
either a continuous or a discontinuous clock. A discontinuous
clock can be either normally high or normally low when
inactive. Figure 43 and Figure 44 show the detailed timing
diagrams of these methods.
While the AD7674 is performing a bit decision, it is important
that voltage transients not occur on digital input/output pins or
degradation of the conversion result can occur. This is particularly
important during the second half of the conversion phase
because the AD7674 provides error correction circuitry that can
correct for an improper bit decision made during the first half
of the conversion phase. For this reason, it is recommended that
when an external clock is being provided, it is a discontinuous
clock that only toggles when BUSY is low or, more importantly,
that it does not transition during the latter half of BUSY high.
External Discontinuous Clock Data Read after
Conversion
Though maximum throughput cannot be achieved using this
mode, it is the most recommended of the serial slave modes.
Figure 43 shows the detailed timing diagrams of this method.
After a conversion is complete, indicated by BUSY returning
low, the result of this conversion can be read while both CS and
RD are low. Data is shifted out MSB first with 18 clock pulses,
and is valid on the rising and falling edge of the clock.
Among the advantages of this method, the conversion performance
is not degraded because there are no voltage transients on the
digital interface during the conversion process. Also, data can
be read at speeds up to 40 MHz, accommodating both slow
digital host interface and the fastest serial reading.
Finally, in this mode only, the AD7674 provides a daisy-chain
feature using the RDC/SDIN input pin to cascade multiple
converters together. This feature is useful for reducing component
count and wiring connections when desired (for instance, in
isolated multiconverter applications).
An example of the concatenation of two devices is shown in
Figure 45. Simultaneous sampling is possible by using a common
CNVST signal. It should be noted that the RDC/SDIN input is
latched on the edge of SCLK opposite the one used to shift out
data on SDOUT. Thus, the MSB of the upstream converter follows
the LSB of the downstream converter on the next SCLK cycle.
SCLK
SDOUT D17 D16 D1 D0D15
X17 X16 X15 X1 X0 Y17 Y16
BUSY
SDIN
INVSCLK = 0
X17 X16X
1 2 3 16 17 18 19 20
EXT/INT = 1 RD = 0
t
35
t
36
t
37
t
31
t
32
t
34
t
16
t
33
CS
03083-0-042
Figure 43. Slave Serial Data Timing for Reading (Read After Convert)
AD7674 Data Sheet
Rev. B | Page 24 of 28
SDOUT
SCLK
D1 D0
X D17 D16 D15
123 16 17 18
BUSY
INVSCLK = 0
EXT/INT = 1 RD = 0
t35
t36 t37
t31 t32
t16
t3
CS
CNVST
03083-0-043
Figure 44. Slave Serial Data Timing for Reading (Read Previous Conversion During Convert)
BUSY BUSY
AD7674
#2 (UPSTREAM)
AD7674
#1 (DOWNSTREAM)
RDC/SDIN SDOUT
CNVST
CS
SCLK
RDC/SDIN SDOUT
CNVST
CS
SCLK
DATA
OUT
SCLK IN
CS IN
CNVST IN
BUSY
OUT
03083-0-044
Figure 45. Two AD7674 Devices in a Daisy-Chain Configuration
External Clock Data Read during Conversion
Figure 44 shows the detailed timing diagrams of this method.
During a conversion, while both CS and RD are low, the result
of the previous conversion can be read. The data is shifted out
MSB first with 18 clock pulses, and is valid on both the rising
and falling edge of the clock. The 18 bits have to be read before
the current conversion is complete. If that is not done, RDERROR
is pulsed high and can be used to interrupt the host interface to
prevent incomplete data reading. There is no daisy-chain feature
in this mode, and the RDC/SDIN input should always be tied
either high or low.
To reduce performance degradation due to digital activity, a fast
discontinuous clock is recommended to ensure that all bits are
read during the first half of the conversion phase. It is also
possible to begin to read the data after conversion and continue
to read the last bits even after a new conversion has been initiated.
MICROPROCESSOR INTERFACING
The AD7674 is ideally suited for traditional dc measurement
applications supporting a microprocessor, and for ac signal
processing applications interfacing to a digital signal processor.
The AD7674 is designed to interface either with a parallel 8-bit
or 16-bit wide interface, or with a general-purpose serial port or
input/output ports on a microcontroller. A variety of external
buffers can be used with the AD7674 to prevent digital noise
from coupling into the ADC. The Serial Peripheral Interface
(SPI) section illustrates the use of the AD7674 with an SPI
equipped DSP, the ADSP-2191M.
Serial Peripheral Interface (SPI)
The AD7674 digital interface is compatible with SPI. As an
example, Figure 46 shows an interface diagram between the
AD7674 and the SPI equipped ADSP-2191M. To accommodate
the slower speed of the DSP, the AD7674 acts as a slave device,
and data must be read after conversion. This mode also allows
the daisy-chain feature. The convert command can be initiated in
response to an internal timer interrupt. The 18-bit output data
are read with 3-byte SPI access. The reading process can be
initiated in response to the end-of-conversion signal (BUSY
going low) using an interrupt line of the DSP. The serial
interface (SPI) on the ADSP-2191M is configured for master
mode (MSTR) = 1, Clock Polarity Bit (CPOL) = 0, Clock Phase
Bit (CPHA) = 1, and SPI interrupt enable (TIMOD) = 00, by
writing to the SPI Control register (SPICLTx). It should be
noted that to meet all timing requirements, the SPI clock should
be limited to 17 Mbps, which allows it to read an ADC result in
about 1.1 µs. When a higher sampling rate is desired, use of one
of the parallel interface modes is recommended.
AD7674* ADSP-2191M*
SER/PAR
PFx
MISOx
SCKx
PFx or TFSx
BUSY
SDOUT
SCLK
CNVST
EXT/INT
CS
RD
INVSCLK
DVDD
*ADDITIONAL PINS OMITTED FOR CLARITY
SPIxSEL (PFx)
03083-0-045
Figure 46. Interfacing the AD7674 to an SPI Interface
Data Sheet AD7674
Rev. B | Page 25 of 28
APPLICATIONS INFORMATION
LAYOUT
The AD7674 has very good immunity to noise on the power
supplies. However, care should still be taken with regard to
grounding layout.
The printed circuit board that houses the AD7674 should be
designed so that the analog and digital sections are separated
and confined to certain areas of the board. This calls for the use
of ground planes, which can be easily separated. Digital and analog
ground planes should be joined in only one place, preferably
underneath the AD7674, or at least as close to the AD7674 as
possible. If the AD7674 is in a system where multiple devices
require analog-to-digital ground connections, the connection
should still be made at one point only, a star ground point that
should be established as close to the AD7674 as possible.
The user should avoid running digital lines under the device, as
these couple noise onto the die. The analog ground plane should
be allowed to run under the AD7674 to avoid noise coupling.
Fast switching signals like CNVST or clocks should be shielded
with digital ground to avoid radiating noise to other sections of
the board, and should never run near analog signal paths.
Crossover of digital and analog signals should be avoided. Traces
on different but close layers of the board should run at right
angles to each other. This reduces the effect of feedthrough through
the board. The power supply lines to the AD7674 should use
as large a trace as possible to provide low impedance paths and
reduce the effect of glitches on the power supply lines. Good
decoupling is also important to lower the impedance of the supply
presented to the AD7674 and to reduce the magnitude of the
supply spikes. Decoupling ceramic capacitors, typically 100 nF,
should be placed close to and ideally right up against each
power supply pin (AVDD, DVDD, and OVDD) and their
corresponding ground pins. Additionally, low ESR 10 µF
capacitors should be located near the ADC to further reduce
low frequency ripple.
The DVDD supply of the AD7674 can be a separate supply or
can come from the analog supply, AVDD, or the digital
interface supply, OVDD. When the system digital supply is
noisy or when fast switching digital signals are present, and if
no separate supply is available, the user should connect the
DVDD digital supply to the analog supply AVDD through an
RC filter (see Figure 28) and connect the system supply to the
interface digital supply OVDD and the remaining digital circuitry.
When DVDD is powered from the system supply, it is useful to
insert a bead to further reduce high frequency spikes.
The AD7674 has four different ground pins: REFGND, AGND,
DGND, and OGND. REFGND senses the reference voltage and
should be a low impedance return to the reference because it
carries pulsed currents. AGND is the ground to which most
internal ADC analog signals are referenced. This ground must
be connected with the least resistance to the analog ground
plane. DGND must be tied to the analog or digital ground plane
depending on the configuration. OGND is connected to the
digital system ground.
The layout of the decoupling of the reference voltage is
important. The decoupling capacitor should be close to the
ADC and should be connected with short and large traces to
minimize parasitic inductances.
EVALUATING AD7674 PERFORMANCE
An evaluation board for the AD7674 allows a quick means
to measure both DC (histograms and time domain) and AC
(time and frequency domain) performances of the converter.
The EVA L-AD7674CBZ is an evaluation board package that
includes a fully assembled and tested evaluation board,
documentation, and software. The accompanying software
requires the use of a capture board which must be ordered
separately from the evaluation board (see the Ordering Guide
for information). The evaluation board can also be used in a
standalone configuration and does not use the software when in
this mode. Refer to the E VA L -AD76XXEDZ and E VA L -
AD76XXCBZ for evaluation board details.
Two types of data capture boards can be used with the E VA L -
AD7674CBZ:
• USB based (E VA L-CED1Z recommended)
• Parallel port based (EVA L -CONTROL BRD3Z not
recommended as many newer PCs do not include parallel
ports any longer)
The recommended board layout for the AD7674 is outlined in
the evaluation board data sheet.
AD7674 Data Sheet
Rev. B | Page 26 of 28
OUTLINE DIMENSIONS
TOP VIEW
(PINS DOWN )
1
12 13 25
24
36
37
48
0.27
0.22
0.17
0.50
BSC
7.00
BSC SQ
SEATING
PLANE
1.60
MAX
0.75
0.60
0.45
VIEW A
9.00 BSC
SQ
PIN 1
0.20
0.09
1.45
1.40
1.35
0.10 MAX
COPLANARITY
VIEW A
ROTATED 90
°
CCW
SEATING
PLANE
7°
3.5°
0°
10°
6°
2°
0.15
0.05
COMPLIANT TO JEDEC STANDARDS MS-026BBC
Figure 47. 48-Lead Low Profile Quad Flat Package [LQFP]
(ST-48)
Dimensions shown in millimeters
112408-B
FOR PRO P E R CONNECTI O N OF
THE EXPOSED PAD, REFER TO
THE PIN CO NFI GURAT ION AND
FUNCTION DES CRIPTIONS
SECTION OF THIS DATA SHEET.
COM P LIANT T O JEDE C S TANDARDS MO-220-WKKD.
1
0.50
BSC
BOTTOM VIEW
TOP VIEW
PIN 1
INDICATOR
7.00
BSC SQ
48
13
24
25
36
37
12
EXPOSED
PAD
PIN 1
INDICATOR
5.20
5.10 SQ
5.00
0.45
0.40
0.35
SEATING
PLANE
0.80
0.75
0.70 0. 05 MAX
0.02 NO M
0.25 M IN
0.20 REF
COPLANARITY
0.08
0.30
0.23
0.18
Figure 48. 48-Lead Lead Frame Chip Scale Package [LFCSP]
7 mm × 7 mm Body and 0.75 mm Package Height
(CP-48-4)
Dimensions shown in millimeters
ORDERING GUIDE
Model1, 2, 3 Temperature Range Package Description Package Option
AD7674ASTZ −40°C to +85°C 48-Lead Low Profile Quad Flat Package [LQFP] ST-48
AD7674ASTZL −40°C to +85°C 48-Lead Low Profile Quad Flat Package [LQFP] ST-48
AD7674ACPZ
−40°C to +85°C
48-Lead Lead Frame Chip Scale Package [LFCSP]
CP-48-4
AD7674ACPZRL −40°C to +85°C 48-Lead Lead Frame Chip Scale Package [LFCSP] CP-48-4
EVAL-AD7674CBZ Evaluation Board
EVAL-CED1Z USB Data Capture Board
EVAL-CONTROL BRD2Z
Parallel Port Capture Board, 32 k RAM
EVAL-CONTROL BRD3Z Parallel Port Capture Board, 128 k RAM
1 Z = RoHS Compliant Part.
2The EVAL-AD7674CBZ can be used as a standalone evaluation board or in conjunction with a capture board for evaluation/demonstration purposes.
3 The capture boards allow the PC to control and communicate with all Analog Devices evaluation boards ending in ED for EVAL-CED1Z and CB for EVAL-CONTROL
BRD2Z/EVAL-CONTROL BRD3Z.
Data Sheet AD7674
Rev. B | Page 27 of 28
NOTES
