CD74HC154EN96 - Texas Instruments

Data sheet acquired from Harris Semiconductor

SCHS152A

Features

• Two Enable Inputs to Facilitate Demultiplexing and

Cascading Functions

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating T emperature Range . . . -55oC to 125oC

• Balanced Propagation Delay and Transition Times

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: NIL = 30%, NIH = 30%of VCC at

VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

VIL= 0.8V (Max), VIH = 2V (Min)

- CMOS Input Compatibility, Il≤1µA at VOL, VOH

Description

The ’HC154 and ’HCT154 are 4-to-16 line

decoders/demultiplexers with two enable inputs, E1 and E2.

A High on either enable input forces the output into the High

state. The demultiplexing function is performed by using the

four input lines, A0 to A3, to select the output lines Y0 to

Y15, and using one enable as the data input while holding

the other enable low.

Pinout

CD54HC154, CD54HCT154

(CERDIP)

CD74HC154, CD74HCT154

(PDIP, SOIC)

TOP VIEW

Ordering Information

PART NUMBER TEMP. RANGE

(oC) PACKAGE

CD54HC154F3A -55 to 125 24 Ld CERDIP

CD74HC154E -55 to 125 24 Ld PDIP

CD74HC154EN -55 to 125 24 Ld PDIP

CD74HC154M -55 to 125 24 Ld SOIC

CD54HCT154F3A -55 to 125 24 Ld CERDIP

CD74HCT154E -55 to 125 24 Ld PDIP

CD74HCT154EN -55 to 125 24 Ld PDIP

CD74HCT154M -55 to 125 24 Ld SOIC

NOTES:

1. When ordering, use the entire part number. Add the sufﬁx 96 to

obtain the variant in the tape and reel.

2. Waferor diefor thispart numberis availablewhich meetsall elec-

trical specifications. Please contact your local TI sales office or

customer service for ordering information.

Y10

GND

VCC

Y15

Y13

Y12

Y11

Y14

September 1997 - Revised May 2000

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

CD54/74HC154,

CD54/74HCT154

High Speed CMOS Logic

4-to-16 Line Decoder/Demultiplexer

[ /Title

(CD74

HC154

CD74

HCT15

Sub-

ect

(High

Speed

CMOS

Logic

4-to-16

Line

Decod

er/Dem

Functional Diagram

TRUTH TABLE

INPUTS OUTPUTS

E1 E2 A3 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15

LLLLLLLHHHHHHHHHHHHHHH

LLLLLHHLHHHHHHHHHHHHHH

LLLLHLHHLHHHHHHHHHHHHH

LLLLHHHHHLHHHHHHHHHHHH

LLLHLLHHHHLHHHHHHHHHHH

LLLHLHHHHHHLHHHHHHHHHH

LLLHHLHHHHHHLHHHHHHHHH

LLLHHHHHHHHHHLHHHHHHHH

LLHLLLHHHHHHHHLHHHHHHH

LLLHLHHHHHHHHHHLHHHHHH

LLHLHLHHHHHHHHHHLHHHHH

LLHLHHHHHHHHHHHHHLHHHH

LLHHLLHHHHHHHHHHHHLHHH

LLHHLHHHHHHHHHHHHHHLHH

LLHHHLHHHHHHHHHHHHHHLH

LLHHHHHHHHHHHHHHHHHHHL

LHXXXXHHHHHHHHHHHHHHHH

HLXXXXHHHHHHHHHHHHHHHH

HHXXXXHHHHHHHHHHHHHHHH

NOTE: H = High Voltage Level, L = Low Voltage Level, X = Don’t Care

9Y8

10 Y9

11 Y10

GND = 12

VCC = 24

Y11

Y12

Y13

Y14

Y15

CD54/74HC154, CD54/74HCT154

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, IIK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, IOK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Source or Sink Current per Output Pin, IO

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, VCC

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

Thermal Resistance (Typical, Note 3) θJA (oC/W)

PDIP Package (.300). . . . . . . . . . . . . . . . . . . . . . . . 75

PDIP Package (.600). . . . . . . . . . . . . . . . . . . . . . . . 60

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC

(SOIC - Lead Tips Only)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation

of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

NOTE:

3. θJA is measured with the component mounted on an evaluation PC board in free air.

DC Electrical Speciﬁcations

PARAMETER SYMBOL

TEST

CONDITIONS VCC

(V)

25oC -40oC TO 85oC -55oC TO 125oC

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

HC TYPES

High Level Input

Voltage VIH - - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V

6 4.2 - - 4.2 - 4.2 - V

Low Level Input

Voltage VIL - - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V

6 - - 1.8 - 1.8 - 1.8 V

High Level Output

Voltage

CMOS Loads

VOH VIH or VIL -0.02 2 1.9 - - 1.9 - 1.9 - V

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

High Level Output

Voltage

TTL Loads

- - ---- - - -V

-4 4.5 3.98 - - 3.84 - 3.7 - V

-5.2 6 5.48 - - 5.34 - 5.2 - V

Low Level Output

Voltage

CMOS Loads

VOL VIH or VIL 0.02 2 - - 0.1 - 0.1 - 0.1 V

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V

Low Level Output

Voltage

TTL Loads

- - ---- - - -V

4 4.5 - - 0.26 - 0.33 - 0.4 V

5.2 6 - - 0.26 - 0.33 - 0.4 V

Input Leakage

Current IIVCC or

GND -6--±0.1 - ±1-±1µA

Quiescent Device

Current ICC VCC or

GND 0 6 - - 8 - 80 - 160 µA

CD54/74HC154, CD54/74HCT154

HCT TYPES

High Level Input

Voltage VIH - - 4.5 to

5.5 2--2 - 2 - V

Low Level Input

Voltage VIL - - 4.5 to

5.5 - - 0.8 - 0.8 - 0.8 V

High Level Output

Voltage

CMOS Loads

VOH VIH or VIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V

High Level Output

Voltage

TTL Loads

-4 4.5 3.98 - - 3.84 - 3.7 - V

Low Level Output

Voltage

CMOS Loads

VOL VIH or VIL 0.02 4.5 - - 0.1 - 0.1 - 0.1 V

Low Level Output

Voltage

TTL Loads

4 4.5 - - 0.26 - 0.33 - 0.4 V

Input Leakage

Current IIVCC and

GND 0 5.5 - ±0.1 - ±1-±1µA

Quiescent Device

Current ICC VCC or

GND 0 5.5 - - 8 - 80 - 160 µA

Additional Quiescent

Device Current Per

Input Pin: 1 Unit Load

∆ICC VCC

-2.1 - 4.5 to

5.5 - 100 360 - 450 - 490 µA

NOTE: For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) speciﬁcation is 1.8mA.

DC Electrical Speciﬁcations (Continued)

PARAMETER SYMBOL

TEST

CONDITIONS VCC

(V)

25oC -40oC TO 85oC -55oC TO 125oC

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

HCT Input Loading Table

INPUT UNIT LOADS

A0 - A3 1.4

E1, E2 1.3

NOTE: Unit Load is ∆ICC limit speciﬁed in DC Electrical Table, e.g.,

360µA max at 25oC.

Switching Speciﬁcations Input tr, tf = 6ns

PARAMETER SYMBOL TEST

CONDITIONS VCC (V)

25oC-40oC TO

85oC -55oC T O 125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

HC TYPES

Propagation Delay (Figure 1) tPLH, tPHL CL= 50pF 2 - - 175 - 220 - 265 ns

Address to Output 4.5 - - 35 - 44 - 53 ns

CL=15pF 5 - 14 - - - - - ns

CL= 50pF 6 - - 30 - 37 - 45 ns

E1 to Output tPLH, tPHL CL= 50pF 2 - - 175 - 220 - 265 ns

4.5 - - 35 - 44 - 53 ns

CL=15pF 5 - 14 - - - - - ns

CL= 50pF 6 - - 30 - 37 - 45 ns

CD54/74HC154, CD54/74HCT154

E2 to Output tPLH, tPHL CL= 50pF 2 - - 175 - 220 - 265 ns

4.5 - - 35 - 44 - 53 ns

CL=15pF 5 - 14 - - - - - ns

CL= 50pF 6 - - 30 - 37 - 45 ns

Output Transition Time

(Figure 1) tTLH, tTHL CL= 50pF 2 - - 75 - 95 - 110 ns

4.5 - - 15 - 19 - 22 ns

6 - - 13 - 16 - 19 ns

Input Capacitance CIN - - - - 10 - 10 - 10 pF

Power Dissipation Capacitance

(Notes 4, 5) CPD -5-88-----pF

HCT TYPES

Propagation Delay (Figure 2) tPLH, tPHL

Address to Output CL= 50pF 4.5 - - 35 - 44 - 53 ns

CL=15pF 5 - 14 - - - - ns

E1 to Output tPLH, tPHL CL= 50pF 4.5 - - 34 - 43 - 51 ns

CL=15pF 5 - 14 - - - - - ns

E2 to Output tPLH, tPHL CL= 50pF 4.5 - 34 - 43 - 51 ns

CL=15pF 5 - 14 - - - - - ns

Output Transition Time tTLH, tTHL CL= 50pF 4.5 - - 15 - 19 - 22 ns

Input Capacitance CIN - - - - 10 - 10 - 10 pF

Power Dissipation Capacitance

(Notes 4, 5) CPD - 5 84 - - - - - pF

NOTES:

4. CPD is used to determine the dynamic power consumption, per gate.

5. PD = VCC2 fi(CPD + CL) where fi = input frequency, CL = output load capacitance, VCC = supply voltage.

Switching Speciﬁcations Input tr, tf = 6ns (Continued)

PARAMETER SYMBOL TEST

CONDITIONS VCC (V)

25oC-40oC TO

85oC -55oC T O 125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

Test Circuits and Waveforms

FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGA-

TION DELAY TIMES, COMBINATION LOGIC FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

tPHL tPLH

tTHL tTLH

90%

50%

10%

50%

10%

INVERTING

OUTPUT

INPUT

GND

VCC

tr = 6ns tf = 6ns

90%

tPHL tPLH

tTHL tTLH

2.7V

1.3V

0.3V

1.3V

10%

INVERTING

OUTPUT

INPUT

GND

tr = 6ns tf = 6ns

90%

CD54/74HC154, CD54/74HCT154

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